stats: update stats for previous changes.
[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-switcheroo-full / config.ini
1 [root]
2 type=Root
3 children=system
4 full_system=true
5 time_sync_enable=false
6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
8
9 [system]
10 type=LinuxArmSystem
11 children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
12 atags_addr=256
13 boot_loader=/gem5/dist/binaries/boot.arm
14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
15 clock=1000
16 dtb_filename=
17 early_kernel_symbols=false
18 enable_context_switch_stats_dump=false
19 flags_addr=268435504
20 gic_cpu_addr=520093952
21 init_param=0
22 kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
23 load_addr_mask=268435455
24 machine_type=RealView_PBX
25 mem_mode=atomic
26 mem_ranges=0:134217727
27 memories=system.realview.nvmem system.physmem
28 multi_proc=true
29 num_work_ids=16
30 readfile=tests/halt.sh
31 symbolfile=
32 work_begin_ckpt_count=0
33 work_begin_cpu_id_exit=-1
34 work_begin_exit_count=0
35 work_cpus_ckpt_count=0
36 work_end_ckpt_count=0
37 work_end_exit_count=0
38 work_item_id=-1
39 system_port=system.membus.slave[0]
40
41 [system.bridge]
42 type=Bridge
43 clock=1000
44 delay=50000
45 ranges=268435456:520093695 1073741824:1610612735
46 req_size=16
47 resp_size=16
48 master=system.iobus.slave[0]
49 slave=system.membus.master[0]
50
51 [system.cf0]
52 type=IdeDisk
53 children=image
54 delay=1000000
55 driveID=master
56 image=system.cf0.image
57
58 [system.cf0.image]
59 type=CowDiskImage
60 children=child
61 child=system.cf0.image.child
62 image_file=
63 read_only=false
64 table_size=65536
65
66 [system.cf0.image.child]
67 type=RawDiskImage
68 image_file=/gem5/dist/disks/linux-arm-ael.img
69 read_only=true
70
71 [system.cpu0]
72 type=AtomicSimpleCPU
73 children=dcache dtb icache interrupts isa itb tracer
74 checker=Null
75 clock=500
76 cpu_id=0
77 do_checkpoint_insts=true
78 do_quiesce=true
79 do_statistics_insts=true
80 dtb=system.cpu0.dtb
81 fastmem=false
82 function_trace=false
83 function_trace_start=0
84 interrupts=system.cpu0.interrupts
85 isa=system.cpu0.isa
86 itb=system.cpu0.itb
87 max_insts_all_threads=0
88 max_insts_any_thread=0
89 max_loads_all_threads=0
90 max_loads_any_thread=0
91 numThreads=1
92 profile=0
93 progress_interval=0
94 simulate_data_stalls=false
95 simulate_inst_stalls=false
96 switched_out=false
97 system=system
98 tracer=system.cpu0.tracer
99 width=1
100 workload=
101 dcache_port=system.cpu0.dcache.cpu_side
102 icache_port=system.cpu0.icache.cpu_side
103
104 [system.cpu0.dcache]
105 type=BaseCache
106 addr_ranges=0:18446744073709551615
107 assoc=4
108 block_size=64
109 clock=500
110 forward_snoops=true
111 hit_latency=2
112 is_top_level=true
113 max_miss_count=0
114 mshrs=4
115 prefetch_on_access=false
116 prefetcher=Null
117 response_latency=2
118 size=32768
119 system=system
120 tgts_per_mshr=20
121 two_queue=false
122 write_buffers=8
123 cpu_side=system.cpu0.dcache_port
124 mem_side=system.toL2Bus.slave[1]
125
126 [system.cpu0.dtb]
127 type=ArmTLB
128 children=walker
129 size=64
130 walker=system.cpu0.dtb.walker
131
132 [system.cpu0.dtb.walker]
133 type=ArmTableWalker
134 clock=500
135 num_squash_per_cycle=2
136 sys=system
137 port=system.toL2Bus.slave[3]
138
139 [system.cpu0.icache]
140 type=BaseCache
141 addr_ranges=0:18446744073709551615
142 assoc=1
143 block_size=64
144 clock=500
145 forward_snoops=true
146 hit_latency=2
147 is_top_level=true
148 max_miss_count=0
149 mshrs=4
150 prefetch_on_access=false
151 prefetcher=Null
152 response_latency=2
153 size=32768
154 system=system
155 tgts_per_mshr=20
156 two_queue=false
157 write_buffers=8
158 cpu_side=system.cpu0.icache_port
159 mem_side=system.toL2Bus.slave[0]
160
161 [system.cpu0.interrupts]
162 type=ArmInterrupts
163
164 [system.cpu0.isa]
165 type=ArmISA
166 fpsid=1090793632
167 id_isar0=34607377
168 id_isar1=34677009
169 id_isar2=555950401
170 id_isar3=17899825
171 id_isar4=268501314
172 id_isar5=0
173 id_mmfr0=3
174 id_mmfr1=0
175 id_mmfr2=19070976
176 id_mmfr3=4027589137
177 id_pfr0=49
178 id_pfr1=1
179 midr=890224640
180
181 [system.cpu0.itb]
182 type=ArmTLB
183 children=walker
184 size=64
185 walker=system.cpu0.itb.walker
186
187 [system.cpu0.itb.walker]
188 type=ArmTableWalker
189 clock=500
190 num_squash_per_cycle=2
191 sys=system
192 port=system.toL2Bus.slave[2]
193
194 [system.cpu0.tracer]
195 type=ExeTracer
196
197 [system.cpu1]
198 type=TimingSimpleCPU
199 children=dtb interrupts isa itb tracer
200 checker=Null
201 clock=500
202 cpu_id=0
203 do_checkpoint_insts=true
204 do_quiesce=true
205 do_statistics_insts=true
206 dtb=system.cpu1.dtb
207 function_trace=false
208 function_trace_start=0
209 interrupts=system.cpu1.interrupts
210 isa=system.cpu1.isa
211 itb=system.cpu1.itb
212 max_insts_all_threads=0
213 max_insts_any_thread=0
214 max_loads_all_threads=0
215 max_loads_any_thread=0
216 numThreads=1
217 profile=0
218 progress_interval=0
219 switched_out=true
220 system=system
221 tracer=system.cpu1.tracer
222 workload=
223
224 [system.cpu1.dtb]
225 type=ArmTLB
226 children=walker
227 size=64
228 walker=system.cpu1.dtb.walker
229
230 [system.cpu1.dtb.walker]
231 type=ArmTableWalker
232 clock=500
233 num_squash_per_cycle=2
234 sys=system
235
236 [system.cpu1.interrupts]
237 type=ArmInterrupts
238
239 [system.cpu1.isa]
240 type=ArmISA
241 fpsid=1090793632
242 id_isar0=34607377
243 id_isar1=34677009
244 id_isar2=555950401
245 id_isar3=17899825
246 id_isar4=268501314
247 id_isar5=0
248 id_mmfr0=3
249 id_mmfr1=0
250 id_mmfr2=19070976
251 id_mmfr3=4027589137
252 id_pfr0=49
253 id_pfr1=1
254 midr=890224640
255
256 [system.cpu1.itb]
257 type=ArmTLB
258 children=walker
259 size=64
260 walker=system.cpu1.itb.walker
261
262 [system.cpu1.itb.walker]
263 type=ArmTableWalker
264 clock=500
265 num_squash_per_cycle=2
266 sys=system
267
268 [system.cpu1.tracer]
269 type=ExeTracer
270
271 [system.cpu2]
272 type=DerivO3CPU
273 children=dtb fuPool interrupts isa itb tracer
274 BTBEntries=4096
275 BTBTagSize=16
276 LFSTSize=1024
277 LQEntries=32
278 LSQCheckLoads=true
279 LSQDepCheckShift=4
280 RASSize=16
281 SQEntries=32
282 SSITSize=1024
283 activity=0
284 backComSize=5
285 cachePorts=200
286 checker=Null
287 choiceCtrBits=2
288 choicePredictorSize=8192
289 clock=500
290 commitToDecodeDelay=1
291 commitToFetchDelay=1
292 commitToIEWDelay=1
293 commitToRenameDelay=1
294 commitWidth=8
295 cpu_id=0
296 decodeToFetchDelay=1
297 decodeToRenameDelay=1
298 decodeWidth=8
299 dispatchWidth=8
300 do_checkpoint_insts=true
301 do_quiesce=true
302 do_statistics_insts=true
303 dtb=system.cpu2.dtb
304 fetchToDecodeDelay=1
305 fetchTrapLatency=1
306 fetchWidth=8
307 forwardComSize=5
308 fuPool=system.cpu2.fuPool
309 function_trace=false
310 function_trace_start=0
311 globalCtrBits=2
312 globalHistoryBits=13
313 globalPredictorSize=8192
314 iewToCommitDelay=1
315 iewToDecodeDelay=1
316 iewToFetchDelay=1
317 iewToRenameDelay=1
318 instShiftAmt=2
319 interrupts=system.cpu2.interrupts
320 isa=system.cpu2.isa
321 issueToExecuteDelay=1
322 issueWidth=8
323 itb=system.cpu2.itb
324 localCtrBits=2
325 localHistoryBits=11
326 localHistoryTableSize=2048
327 localPredictorSize=2048
328 max_insts_all_threads=0
329 max_insts_any_thread=0
330 max_loads_all_threads=0
331 max_loads_any_thread=0
332 needsTSO=false
333 numIQEntries=64
334 numPhysFloatRegs=256
335 numPhysIntRegs=256
336 numROBEntries=192
337 numRobs=1
338 numThreads=1
339 predType=tournament
340 profile=0
341 progress_interval=0
342 renameToDecodeDelay=1
343 renameToFetchDelay=1
344 renameToIEWDelay=2
345 renameToROBDelay=1
346 renameWidth=8
347 smtCommitPolicy=RoundRobin
348 smtFetchPolicy=SingleThread
349 smtIQPolicy=Partitioned
350 smtIQThreshold=100
351 smtLSQPolicy=Partitioned
352 smtLSQThreshold=100
353 smtNumFetchingThreads=1
354 smtROBPolicy=Partitioned
355 smtROBThreshold=100
356 squashWidth=8
357 store_set_clear_period=250000
358 switched_out=true
359 system=system
360 tracer=system.cpu2.tracer
361 trapLatency=13
362 wbDepth=1
363 wbWidth=8
364 workload=
365
366 [system.cpu2.dtb]
367 type=ArmTLB
368 children=walker
369 size=64
370 walker=system.cpu2.dtb.walker
371
372 [system.cpu2.dtb.walker]
373 type=ArmTableWalker
374 clock=500
375 num_squash_per_cycle=2
376 sys=system
377
378 [system.cpu2.fuPool]
379 type=FUPool
380 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
381 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
382
383 [system.cpu2.fuPool.FUList0]
384 type=FUDesc
385 children=opList
386 count=6
387 opList=system.cpu2.fuPool.FUList0.opList
388
389 [system.cpu2.fuPool.FUList0.opList]
390 type=OpDesc
391 issueLat=1
392 opClass=IntAlu
393 opLat=1
394
395 [system.cpu2.fuPool.FUList1]
396 type=FUDesc
397 children=opList0 opList1
398 count=2
399 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
400
401 [system.cpu2.fuPool.FUList1.opList0]
402 type=OpDesc
403 issueLat=1
404 opClass=IntMult
405 opLat=3
406
407 [system.cpu2.fuPool.FUList1.opList1]
408 type=OpDesc
409 issueLat=19
410 opClass=IntDiv
411 opLat=20
412
413 [system.cpu2.fuPool.FUList2]
414 type=FUDesc
415 children=opList0 opList1 opList2
416 count=4
417 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
418
419 [system.cpu2.fuPool.FUList2.opList0]
420 type=OpDesc
421 issueLat=1
422 opClass=FloatAdd
423 opLat=2
424
425 [system.cpu2.fuPool.FUList2.opList1]
426 type=OpDesc
427 issueLat=1
428 opClass=FloatCmp
429 opLat=2
430
431 [system.cpu2.fuPool.FUList2.opList2]
432 type=OpDesc
433 issueLat=1
434 opClass=FloatCvt
435 opLat=2
436
437 [system.cpu2.fuPool.FUList3]
438 type=FUDesc
439 children=opList0 opList1 opList2
440 count=2
441 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
442
443 [system.cpu2.fuPool.FUList3.opList0]
444 type=OpDesc
445 issueLat=1
446 opClass=FloatMult
447 opLat=4
448
449 [system.cpu2.fuPool.FUList3.opList1]
450 type=OpDesc
451 issueLat=12
452 opClass=FloatDiv
453 opLat=12
454
455 [system.cpu2.fuPool.FUList3.opList2]
456 type=OpDesc
457 issueLat=24
458 opClass=FloatSqrt
459 opLat=24
460
461 [system.cpu2.fuPool.FUList4]
462 type=FUDesc
463 children=opList
464 count=0
465 opList=system.cpu2.fuPool.FUList4.opList
466
467 [system.cpu2.fuPool.FUList4.opList]
468 type=OpDesc
469 issueLat=1
470 opClass=MemRead
471 opLat=1
472
473 [system.cpu2.fuPool.FUList5]
474 type=FUDesc
475 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
476 count=4
477 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
478
479 [system.cpu2.fuPool.FUList5.opList00]
480 type=OpDesc
481 issueLat=1
482 opClass=SimdAdd
483 opLat=1
484
485 [system.cpu2.fuPool.FUList5.opList01]
486 type=OpDesc
487 issueLat=1
488 opClass=SimdAddAcc
489 opLat=1
490
491 [system.cpu2.fuPool.FUList5.opList02]
492 type=OpDesc
493 issueLat=1
494 opClass=SimdAlu
495 opLat=1
496
497 [system.cpu2.fuPool.FUList5.opList03]
498 type=OpDesc
499 issueLat=1
500 opClass=SimdCmp
501 opLat=1
502
503 [system.cpu2.fuPool.FUList5.opList04]
504 type=OpDesc
505 issueLat=1
506 opClass=SimdCvt
507 opLat=1
508
509 [system.cpu2.fuPool.FUList5.opList05]
510 type=OpDesc
511 issueLat=1
512 opClass=SimdMisc
513 opLat=1
514
515 [system.cpu2.fuPool.FUList5.opList06]
516 type=OpDesc
517 issueLat=1
518 opClass=SimdMult
519 opLat=1
520
521 [system.cpu2.fuPool.FUList5.opList07]
522 type=OpDesc
523 issueLat=1
524 opClass=SimdMultAcc
525 opLat=1
526
527 [system.cpu2.fuPool.FUList5.opList08]
528 type=OpDesc
529 issueLat=1
530 opClass=SimdShift
531 opLat=1
532
533 [system.cpu2.fuPool.FUList5.opList09]
534 type=OpDesc
535 issueLat=1
536 opClass=SimdShiftAcc
537 opLat=1
538
539 [system.cpu2.fuPool.FUList5.opList10]
540 type=OpDesc
541 issueLat=1
542 opClass=SimdSqrt
543 opLat=1
544
545 [system.cpu2.fuPool.FUList5.opList11]
546 type=OpDesc
547 issueLat=1
548 opClass=SimdFloatAdd
549 opLat=1
550
551 [system.cpu2.fuPool.FUList5.opList12]
552 type=OpDesc
553 issueLat=1
554 opClass=SimdFloatAlu
555 opLat=1
556
557 [system.cpu2.fuPool.FUList5.opList13]
558 type=OpDesc
559 issueLat=1
560 opClass=SimdFloatCmp
561 opLat=1
562
563 [system.cpu2.fuPool.FUList5.opList14]
564 type=OpDesc
565 issueLat=1
566 opClass=SimdFloatCvt
567 opLat=1
568
569 [system.cpu2.fuPool.FUList5.opList15]
570 type=OpDesc
571 issueLat=1
572 opClass=SimdFloatDiv
573 opLat=1
574
575 [system.cpu2.fuPool.FUList5.opList16]
576 type=OpDesc
577 issueLat=1
578 opClass=SimdFloatMisc
579 opLat=1
580
581 [system.cpu2.fuPool.FUList5.opList17]
582 type=OpDesc
583 issueLat=1
584 opClass=SimdFloatMult
585 opLat=1
586
587 [system.cpu2.fuPool.FUList5.opList18]
588 type=OpDesc
589 issueLat=1
590 opClass=SimdFloatMultAcc
591 opLat=1
592
593 [system.cpu2.fuPool.FUList5.opList19]
594 type=OpDesc
595 issueLat=1
596 opClass=SimdFloatSqrt
597 opLat=1
598
599 [system.cpu2.fuPool.FUList6]
600 type=FUDesc
601 children=opList
602 count=0
603 opList=system.cpu2.fuPool.FUList6.opList
604
605 [system.cpu2.fuPool.FUList6.opList]
606 type=OpDesc
607 issueLat=1
608 opClass=MemWrite
609 opLat=1
610
611 [system.cpu2.fuPool.FUList7]
612 type=FUDesc
613 children=opList0 opList1
614 count=4
615 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
616
617 [system.cpu2.fuPool.FUList7.opList0]
618 type=OpDesc
619 issueLat=1
620 opClass=MemRead
621 opLat=1
622
623 [system.cpu2.fuPool.FUList7.opList1]
624 type=OpDesc
625 issueLat=1
626 opClass=MemWrite
627 opLat=1
628
629 [system.cpu2.fuPool.FUList8]
630 type=FUDesc
631 children=opList
632 count=1
633 opList=system.cpu2.fuPool.FUList8.opList
634
635 [system.cpu2.fuPool.FUList8.opList]
636 type=OpDesc
637 issueLat=3
638 opClass=IprAccess
639 opLat=3
640
641 [system.cpu2.interrupts]
642 type=ArmInterrupts
643
644 [system.cpu2.isa]
645 type=ArmISA
646 fpsid=1090793632
647 id_isar0=34607377
648 id_isar1=34677009
649 id_isar2=555950401
650 id_isar3=17899825
651 id_isar4=268501314
652 id_isar5=0
653 id_mmfr0=3
654 id_mmfr1=0
655 id_mmfr2=19070976
656 id_mmfr3=4027589137
657 id_pfr0=49
658 id_pfr1=1
659 midr=890224640
660
661 [system.cpu2.itb]
662 type=ArmTLB
663 children=walker
664 size=64
665 walker=system.cpu2.itb.walker
666
667 [system.cpu2.itb.walker]
668 type=ArmTableWalker
669 clock=500
670 num_squash_per_cycle=2
671 sys=system
672
673 [system.cpu2.tracer]
674 type=ExeTracer
675
676 [system.intrctrl]
677 type=IntrControl
678 sys=system
679
680 [system.iobus]
681 type=NoncoherentBus
682 block_size=64
683 clock=1000
684 header_cycles=1
685 use_default_range=false
686 width=8
687 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
688 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
689
690 [system.iocache]
691 type=BaseCache
692 addr_ranges=0:134217727
693 assoc=8
694 block_size=64
695 clock=1000
696 forward_snoops=false
697 hit_latency=50
698 is_top_level=true
699 max_miss_count=0
700 mshrs=20
701 prefetch_on_access=false
702 prefetcher=Null
703 response_latency=50
704 size=1024
705 system=system
706 tgts_per_mshr=12
707 two_queue=false
708 write_buffers=8
709 cpu_side=system.iobus.master[25]
710 mem_side=system.membus.slave[2]
711
712 [system.l2c]
713 type=BaseCache
714 addr_ranges=0:18446744073709551615
715 assoc=8
716 block_size=64
717 clock=500
718 forward_snoops=true
719 hit_latency=20
720 is_top_level=false
721 max_miss_count=0
722 mshrs=20
723 prefetch_on_access=false
724 prefetcher=Null
725 response_latency=20
726 size=4194304
727 system=system
728 tgts_per_mshr=12
729 two_queue=false
730 write_buffers=8
731 cpu_side=system.toL2Bus.master[0]
732 mem_side=system.membus.slave[1]
733
734 [system.membus]
735 type=CoherentBus
736 children=badaddr_responder
737 block_size=64
738 clock=1000
739 header_cycles=1
740 use_default_range=false
741 width=8
742 default=system.membus.badaddr_responder.pio
743 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
744 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
745
746 [system.membus.badaddr_responder]
747 type=IsaFake
748 clock=1000
749 fake_mem=false
750 pio_addr=0
751 pio_latency=100000
752 pio_size=8
753 ret_bad_addr=true
754 ret_data16=65535
755 ret_data32=4294967295
756 ret_data64=18446744073709551615
757 ret_data8=255
758 system=system
759 update_data=false
760 warn_access=warn
761 pio=system.membus.default
762
763 [system.physmem]
764 type=SimpleDRAM
765 addr_mapping=openmap
766 banks_per_rank=8
767 clock=1000
768 conf_table_reported=true
769 in_addr_map=true
770 lines_per_rowbuffer=64
771 mem_sched_policy=fcfs
772 null=false
773 page_policy=open
774 range=0:134217727
775 ranks_per_channel=2
776 read_buffer_size=32
777 tBURST=4000
778 tCL=14000
779 tRCD=14000
780 tREFI=7800000
781 tRFC=300000
782 tRP=14000
783 tWTR=1000
784 write_buffer_size=32
785 write_thresh_perc=70
786 zero=false
787 port=system.membus.master[2]
788
789 [system.realview]
790 type=RealView
791 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
792 intrctrl=system.intrctrl
793 max_mem_size=268435456
794 mem_start_addr=0
795 pci_cfg_base=0
796 system=system
797
798 [system.realview.a9scu]
799 type=A9SCU
800 clock=1000
801 pio_addr=520093696
802 pio_latency=100000
803 system=system
804 pio=system.membus.master[5]
805
806 [system.realview.aaci_fake]
807 type=AmbaFake
808 amba_id=0
809 clock=1000
810 ignore_access=false
811 pio_addr=268451840
812 pio_latency=100000
813 system=system
814 pio=system.iobus.master[21]
815
816 [system.realview.cf_ctrl]
817 type=IdeController
818 BAR0=402653184
819 BAR0LegacyIO=true
820 BAR0Size=16
821 BAR1=402653440
822 BAR1LegacyIO=true
823 BAR1Size=1
824 BAR2=1
825 BAR2LegacyIO=false
826 BAR2Size=8
827 BAR3=1
828 BAR3LegacyIO=false
829 BAR3Size=4
830 BAR4=1
831 BAR4LegacyIO=false
832 BAR4Size=16
833 BAR5=1
834 BAR5LegacyIO=false
835 BAR5Size=0
836 BIST=0
837 CacheLineSize=0
838 CardbusCIS=0
839 ClassCode=1
840 Command=1
841 DeviceID=28945
842 ExpansionROM=0
843 HeaderType=0
844 InterruptLine=31
845 InterruptPin=1
846 LatencyTimer=0
847 MaximumLatency=0
848 MinimumGrant=0
849 ProgIF=133
850 Revision=0
851 Status=640
852 SubClassCode=1
853 SubsystemID=0
854 SubsystemVendorID=0
855 VendorID=32902
856 clock=1000
857 config_latency=20000
858 ctrl_offset=2
859 disks=system.cf0
860 io_shift=1
861 pci_bus=2
862 pci_dev=7
863 pci_func=0
864 pio_latency=30000
865 platform=system.realview
866 system=system
867 config=system.iobus.master[8]
868 dma=system.iobus.slave[2]
869 pio=system.iobus.master[7]
870
871 [system.realview.clcd]
872 type=Pl111
873 amba_id=1315089
874 clock=1000
875 gic=system.realview.gic
876 int_num=55
877 pio_addr=268566528
878 pio_latency=10000
879 pixel_clock=41667
880 system=system
881 vnc=system.vncserver
882 dma=system.iobus.slave[1]
883 pio=system.iobus.master[4]
884
885 [system.realview.dmac_fake]
886 type=AmbaFake
887 amba_id=0
888 clock=1000
889 ignore_access=false
890 pio_addr=268632064
891 pio_latency=100000
892 system=system
893 pio=system.iobus.master[9]
894
895 [system.realview.flash_fake]
896 type=IsaFake
897 clock=1000
898 fake_mem=true
899 pio_addr=1073741824
900 pio_latency=100000
901 pio_size=536870912
902 ret_bad_addr=false
903 ret_data16=65535
904 ret_data32=4294967295
905 ret_data64=18446744073709551615
906 ret_data8=255
907 system=system
908 update_data=false
909 warn_access=
910 pio=system.iobus.master[24]
911
912 [system.realview.gic]
913 type=Gic
914 clock=1000
915 cpu_addr=520093952
916 cpu_pio_delay=10000
917 dist_addr=520097792
918 dist_pio_delay=10000
919 int_latency=10000
920 it_lines=128
921 platform=system.realview
922 system=system
923 pio=system.membus.master[3]
924
925 [system.realview.gpio0_fake]
926 type=AmbaFake
927 amba_id=0
928 clock=1000
929 ignore_access=false
930 pio_addr=268513280
931 pio_latency=100000
932 system=system
933 pio=system.iobus.master[16]
934
935 [system.realview.gpio1_fake]
936 type=AmbaFake
937 amba_id=0
938 clock=1000
939 ignore_access=false
940 pio_addr=268517376
941 pio_latency=100000
942 system=system
943 pio=system.iobus.master[17]
944
945 [system.realview.gpio2_fake]
946 type=AmbaFake
947 amba_id=0
948 clock=1000
949 ignore_access=false
950 pio_addr=268521472
951 pio_latency=100000
952 system=system
953 pio=system.iobus.master[18]
954
955 [system.realview.kmi0]
956 type=Pl050
957 amba_id=1314896
958 clock=1000
959 gic=system.realview.gic
960 int_delay=1000000
961 int_num=52
962 is_mouse=false
963 pio_addr=268460032
964 pio_latency=100000
965 system=system
966 vnc=system.vncserver
967 pio=system.iobus.master[5]
968
969 [system.realview.kmi1]
970 type=Pl050
971 amba_id=1314896
972 clock=1000
973 gic=system.realview.gic
974 int_delay=1000000
975 int_num=53
976 is_mouse=true
977 pio_addr=268464128
978 pio_latency=100000
979 system=system
980 vnc=system.vncserver
981 pio=system.iobus.master[6]
982
983 [system.realview.l2x0_fake]
984 type=IsaFake
985 clock=1000
986 fake_mem=false
987 pio_addr=520101888
988 pio_latency=100000
989 pio_size=4095
990 ret_bad_addr=false
991 ret_data16=65535
992 ret_data32=4294967295
993 ret_data64=18446744073709551615
994 ret_data8=255
995 system=system
996 update_data=false
997 warn_access=
998 pio=system.membus.master[4]
999
1000 [system.realview.local_cpu_timer]
1001 type=CpuLocalTimer
1002 clock=1000
1003 gic=system.realview.gic
1004 int_num_timer=29
1005 int_num_watchdog=30
1006 pio_addr=520095232
1007 pio_latency=100000
1008 system=system
1009 pio=system.membus.master[6]
1010
1011 [system.realview.mmc_fake]
1012 type=AmbaFake
1013 amba_id=0
1014 clock=1000
1015 ignore_access=false
1016 pio_addr=268455936
1017 pio_latency=100000
1018 system=system
1019 pio=system.iobus.master[22]
1020
1021 [system.realview.nvmem]
1022 type=SimpleMemory
1023 bandwidth=73.000000
1024 clock=1000
1025 conf_table_reported=false
1026 in_addr_map=true
1027 latency=30000
1028 latency_var=0
1029 null=false
1030 range=2147483648:2214592511
1031 zero=true
1032 port=system.membus.master[1]
1033
1034 [system.realview.realview_io]
1035 type=RealViewCtrl
1036 clock=1000
1037 idreg=0
1038 pio_addr=268435456
1039 pio_latency=100000
1040 proc_id0=201326592
1041 proc_id1=201327138
1042 system=system
1043 pio=system.iobus.master[1]
1044
1045 [system.realview.rtc]
1046 type=PL031
1047 amba_id=3412017
1048 clock=1000
1049 gic=system.realview.gic
1050 int_delay=100000
1051 int_num=42
1052 pio_addr=268529664
1053 pio_latency=100000
1054 system=system
1055 time=Thu Jan 1 00:00:00 2009
1056 pio=system.iobus.master[23]
1057
1058 [system.realview.sci_fake]
1059 type=AmbaFake
1060 amba_id=0
1061 clock=1000
1062 ignore_access=false
1063 pio_addr=268492800
1064 pio_latency=100000
1065 system=system
1066 pio=system.iobus.master[20]
1067
1068 [system.realview.smc_fake]
1069 type=AmbaFake
1070 amba_id=0
1071 clock=1000
1072 ignore_access=false
1073 pio_addr=269357056
1074 pio_latency=100000
1075 system=system
1076 pio=system.iobus.master[13]
1077
1078 [system.realview.sp810_fake]
1079 type=AmbaFake
1080 amba_id=0
1081 clock=1000
1082 ignore_access=true
1083 pio_addr=268439552
1084 pio_latency=100000
1085 system=system
1086 pio=system.iobus.master[14]
1087
1088 [system.realview.ssp_fake]
1089 type=AmbaFake
1090 amba_id=0
1091 clock=1000
1092 ignore_access=false
1093 pio_addr=268488704
1094 pio_latency=100000
1095 system=system
1096 pio=system.iobus.master[19]
1097
1098 [system.realview.timer0]
1099 type=Sp804
1100 amba_id=1316868
1101 clock=1000
1102 clock0=1000000
1103 clock1=1000000
1104 gic=system.realview.gic
1105 int_num0=36
1106 int_num1=36
1107 pio_addr=268505088
1108 pio_latency=100000
1109 system=system
1110 pio=system.iobus.master[2]
1111
1112 [system.realview.timer1]
1113 type=Sp804
1114 amba_id=1316868
1115 clock=1000
1116 clock0=1000000
1117 clock1=1000000
1118 gic=system.realview.gic
1119 int_num0=37
1120 int_num1=37
1121 pio_addr=268509184
1122 pio_latency=100000
1123 system=system
1124 pio=system.iobus.master[3]
1125
1126 [system.realview.uart]
1127 type=Pl011
1128 clock=1000
1129 end_on_eot=false
1130 gic=system.realview.gic
1131 int_delay=100000
1132 int_num=44
1133 pio_addr=268472320
1134 pio_latency=100000
1135 platform=system.realview
1136 system=system
1137 terminal=system.terminal
1138 pio=system.iobus.master[0]
1139
1140 [system.realview.uart1_fake]
1141 type=AmbaFake
1142 amba_id=0
1143 clock=1000
1144 ignore_access=false
1145 pio_addr=268476416
1146 pio_latency=100000
1147 system=system
1148 pio=system.iobus.master[10]
1149
1150 [system.realview.uart2_fake]
1151 type=AmbaFake
1152 amba_id=0
1153 clock=1000
1154 ignore_access=false
1155 pio_addr=268480512
1156 pio_latency=100000
1157 system=system
1158 pio=system.iobus.master[11]
1159
1160 [system.realview.uart3_fake]
1161 type=AmbaFake
1162 amba_id=0
1163 clock=1000
1164 ignore_access=false
1165 pio_addr=268484608
1166 pio_latency=100000
1167 system=system
1168 pio=system.iobus.master[12]
1169
1170 [system.realview.watchdog_fake]
1171 type=AmbaFake
1172 amba_id=0
1173 clock=1000
1174 ignore_access=false
1175 pio_addr=268500992
1176 pio_latency=100000
1177 system=system
1178 pio=system.iobus.master[15]
1179
1180 [system.terminal]
1181 type=Terminal
1182 intr_control=system.intrctrl
1183 number=0
1184 output=true
1185 port=3456
1186
1187 [system.toL2Bus]
1188 type=CoherentBus
1189 block_size=64
1190 clock=500
1191 header_cycles=1
1192 use_default_range=false
1193 width=8
1194 master=system.l2c.cpu_side
1195 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
1196
1197 [system.vncserver]
1198 type=VncServer
1199 frame_capture=false
1200 number=0
1201 port=5900
1202