6 time_sync_period=100000000000
7 time_sync_spin_threshold=100000000
11 children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
13 boot_loader=/gem5/dist/binaries/boot.arm
14 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
17 early_kernel_symbols=false
18 enable_context_switch_stats_dump=false
20 gic_cpu_addr=520093952
22 kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
23 load_addr_mask=268435455
24 machine_type=RealView_PBX
26 mem_ranges=0:134217727
27 memories=system.realview.nvmem system.physmem
30 readfile=tests/halt.sh
32 work_begin_ckpt_count=0
33 work_begin_cpu_id_exit=-1
34 work_begin_exit_count=0
35 work_cpus_ckpt_count=0
39 system_port=system.membus.slave[0]
45 ranges=268435456:520093695 1073741824:1610612735
48 master=system.iobus.slave[0]
49 slave=system.membus.master[0]
56 image=system.cf0.image
61 child=system.cf0.image.child
66 [system.cf0.image.child]
68 image_file=/gem5/dist/disks/linux-arm-ael.img
73 children=dcache dtb icache interrupts isa itb tracer
77 do_checkpoint_insts=true
79 do_statistics_insts=true
83 function_trace_start=0
84 interrupts=system.cpu0.interrupts
87 max_insts_all_threads=0
88 max_insts_any_thread=0
89 max_loads_all_threads=0
90 max_loads_any_thread=0
94 simulate_data_stalls=false
95 simulate_inst_stalls=false
98 tracer=system.cpu0.tracer
101 dcache_port=system.cpu0.dcache.cpu_side
102 icache_port=system.cpu0.icache.cpu_side
106 addr_ranges=0:18446744073709551615
115 prefetch_on_access=false
123 cpu_side=system.cpu0.dcache_port
124 mem_side=system.toL2Bus.slave[1]
130 walker=system.cpu0.dtb.walker
132 [system.cpu0.dtb.walker]
135 num_squash_per_cycle=2
137 port=system.toL2Bus.slave[3]
141 addr_ranges=0:18446744073709551615
150 prefetch_on_access=false
158 cpu_side=system.cpu0.icache_port
159 mem_side=system.toL2Bus.slave[0]
161 [system.cpu0.interrupts]
185 walker=system.cpu0.itb.walker
187 [system.cpu0.itb.walker]
190 num_squash_per_cycle=2
192 port=system.toL2Bus.slave[2]
199 children=dtb interrupts isa itb tracer
203 do_checkpoint_insts=true
205 do_statistics_insts=true
208 function_trace_start=0
209 interrupts=system.cpu1.interrupts
212 max_insts_all_threads=0
213 max_insts_any_thread=0
214 max_loads_all_threads=0
215 max_loads_any_thread=0
221 tracer=system.cpu1.tracer
228 walker=system.cpu1.dtb.walker
230 [system.cpu1.dtb.walker]
233 num_squash_per_cycle=2
236 [system.cpu1.interrupts]
260 walker=system.cpu1.itb.walker
262 [system.cpu1.itb.walker]
265 num_squash_per_cycle=2
273 children=dtb fuPool interrupts isa itb tracer
288 choicePredictorSize=8192
290 commitToDecodeDelay=1
293 commitToRenameDelay=1
297 decodeToRenameDelay=1
300 do_checkpoint_insts=true
302 do_statistics_insts=true
308 fuPool=system.cpu2.fuPool
310 function_trace_start=0
313 globalPredictorSize=8192
319 interrupts=system.cpu2.interrupts
321 issueToExecuteDelay=1
326 localHistoryTableSize=2048
327 localPredictorSize=2048
328 max_insts_all_threads=0
329 max_insts_any_thread=0
330 max_loads_all_threads=0
331 max_loads_any_thread=0
342 renameToDecodeDelay=1
347 smtCommitPolicy=RoundRobin
348 smtFetchPolicy=SingleThread
349 smtIQPolicy=Partitioned
351 smtLSQPolicy=Partitioned
353 smtNumFetchingThreads=1
354 smtROBPolicy=Partitioned
357 store_set_clear_period=250000
360 tracer=system.cpu2.tracer
370 walker=system.cpu2.dtb.walker
372 [system.cpu2.dtb.walker]
375 num_squash_per_cycle=2
380 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
381 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
383 [system.cpu2.fuPool.FUList0]
387 opList=system.cpu2.fuPool.FUList0.opList
389 [system.cpu2.fuPool.FUList0.opList]
395 [system.cpu2.fuPool.FUList1]
397 children=opList0 opList1
399 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
401 [system.cpu2.fuPool.FUList1.opList0]
407 [system.cpu2.fuPool.FUList1.opList1]
413 [system.cpu2.fuPool.FUList2]
415 children=opList0 opList1 opList2
417 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
419 [system.cpu2.fuPool.FUList2.opList0]
425 [system.cpu2.fuPool.FUList2.opList1]
431 [system.cpu2.fuPool.FUList2.opList2]
437 [system.cpu2.fuPool.FUList3]
439 children=opList0 opList1 opList2
441 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
443 [system.cpu2.fuPool.FUList3.opList0]
449 [system.cpu2.fuPool.FUList3.opList1]
455 [system.cpu2.fuPool.FUList3.opList2]
461 [system.cpu2.fuPool.FUList4]
465 opList=system.cpu2.fuPool.FUList4.opList
467 [system.cpu2.fuPool.FUList4.opList]
473 [system.cpu2.fuPool.FUList5]
475 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
477 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
479 [system.cpu2.fuPool.FUList5.opList00]
485 [system.cpu2.fuPool.FUList5.opList01]
491 [system.cpu2.fuPool.FUList5.opList02]
497 [system.cpu2.fuPool.FUList5.opList03]
503 [system.cpu2.fuPool.FUList5.opList04]
509 [system.cpu2.fuPool.FUList5.opList05]
515 [system.cpu2.fuPool.FUList5.opList06]
521 [system.cpu2.fuPool.FUList5.opList07]
527 [system.cpu2.fuPool.FUList5.opList08]
533 [system.cpu2.fuPool.FUList5.opList09]
539 [system.cpu2.fuPool.FUList5.opList10]
545 [system.cpu2.fuPool.FUList5.opList11]
551 [system.cpu2.fuPool.FUList5.opList12]
557 [system.cpu2.fuPool.FUList5.opList13]
563 [system.cpu2.fuPool.FUList5.opList14]
569 [system.cpu2.fuPool.FUList5.opList15]
575 [system.cpu2.fuPool.FUList5.opList16]
578 opClass=SimdFloatMisc
581 [system.cpu2.fuPool.FUList5.opList17]
584 opClass=SimdFloatMult
587 [system.cpu2.fuPool.FUList5.opList18]
590 opClass=SimdFloatMultAcc
593 [system.cpu2.fuPool.FUList5.opList19]
596 opClass=SimdFloatSqrt
599 [system.cpu2.fuPool.FUList6]
603 opList=system.cpu2.fuPool.FUList6.opList
605 [system.cpu2.fuPool.FUList6.opList]
611 [system.cpu2.fuPool.FUList7]
613 children=opList0 opList1
615 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
617 [system.cpu2.fuPool.FUList7.opList0]
623 [system.cpu2.fuPool.FUList7.opList1]
629 [system.cpu2.fuPool.FUList8]
633 opList=system.cpu2.fuPool.FUList8.opList
635 [system.cpu2.fuPool.FUList8.opList]
641 [system.cpu2.interrupts]
665 walker=system.cpu2.itb.walker
667 [system.cpu2.itb.walker]
670 num_squash_per_cycle=2
685 use_default_range=false
687 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
688 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
692 addr_ranges=0:134217727
701 prefetch_on_access=false
709 cpu_side=system.iobus.master[25]
710 mem_side=system.membus.slave[2]
714 addr_ranges=0:18446744073709551615
723 prefetch_on_access=false
731 cpu_side=system.toL2Bus.master[0]
732 mem_side=system.membus.slave[1]
736 children=badaddr_responder
740 use_default_range=false
742 default=system.membus.badaddr_responder.pio
743 master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
744 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
746 [system.membus.badaddr_responder]
755 ret_data32=4294967295
756 ret_data64=18446744073709551615
761 pio=system.membus.default
768 conf_table_reported=true
770 lines_per_rowbuffer=64
771 mem_sched_policy=fcfs
787 port=system.membus.master[2]
791 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
792 intrctrl=system.intrctrl
793 max_mem_size=268435456
798 [system.realview.a9scu]
804 pio=system.membus.master[5]
806 [system.realview.aaci_fake]
814 pio=system.iobus.master[21]
816 [system.realview.cf_ctrl]
865 platform=system.realview
867 config=system.iobus.master[8]
868 dma=system.iobus.slave[2]
869 pio=system.iobus.master[7]
871 [system.realview.clcd]
875 gic=system.realview.gic
882 dma=system.iobus.slave[1]
883 pio=system.iobus.master[4]
885 [system.realview.dmac_fake]
893 pio=system.iobus.master[9]
895 [system.realview.flash_fake]
904 ret_data32=4294967295
905 ret_data64=18446744073709551615
910 pio=system.iobus.master[24]
912 [system.realview.gic]
921 platform=system.realview
923 pio=system.membus.master[3]
925 [system.realview.gpio0_fake]
933 pio=system.iobus.master[16]
935 [system.realview.gpio1_fake]
943 pio=system.iobus.master[17]
945 [system.realview.gpio2_fake]
953 pio=system.iobus.master[18]
955 [system.realview.kmi0]
959 gic=system.realview.gic
967 pio=system.iobus.master[5]
969 [system.realview.kmi1]
973 gic=system.realview.gic
981 pio=system.iobus.master[6]
983 [system.realview.l2x0_fake]
992 ret_data32=4294967295
993 ret_data64=18446744073709551615
998 pio=system.membus.master[4]
1000 [system.realview.local_cpu_timer]
1003 gic=system.realview.gic
1009 pio=system.membus.master[6]
1011 [system.realview.mmc_fake]
1019 pio=system.iobus.master[22]
1021 [system.realview.nvmem]
1025 conf_table_reported=false
1030 range=2147483648:2214592511
1032 port=system.membus.master[1]
1034 [system.realview.realview_io]
1043 pio=system.iobus.master[1]
1045 [system.realview.rtc]
1049 gic=system.realview.gic
1055 time=Thu Jan 1 00:00:00 2009
1056 pio=system.iobus.master[23]
1058 [system.realview.sci_fake]
1066 pio=system.iobus.master[20]
1068 [system.realview.smc_fake]
1076 pio=system.iobus.master[13]
1078 [system.realview.sp810_fake]
1086 pio=system.iobus.master[14]
1088 [system.realview.ssp_fake]
1096 pio=system.iobus.master[19]
1098 [system.realview.timer0]
1104 gic=system.realview.gic
1110 pio=system.iobus.master[2]
1112 [system.realview.timer1]
1118 gic=system.realview.gic
1124 pio=system.iobus.master[3]
1126 [system.realview.uart]
1130 gic=system.realview.gic
1135 platform=system.realview
1137 terminal=system.terminal
1138 pio=system.iobus.master[0]
1140 [system.realview.uart1_fake]
1148 pio=system.iobus.master[10]
1150 [system.realview.uart2_fake]
1158 pio=system.iobus.master[11]
1160 [system.realview.uart3_fake]
1168 pio=system.iobus.master[12]
1170 [system.realview.watchdog_fake]
1178 pio=system.iobus.master[15]
1182 intr_control=system.intrctrl
1192 use_default_range=false
1194 master=system.l2c.cpu_side
1195 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port