stats: update stats for cache occupancy and clock domain changes
[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-switcheroo-full / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=true
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=LinuxArmSystem
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14 atags_addr=256
15 boot_loader=/dist/binaries/boot.arm
16 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
17 cache_line_size=64
18 clk_domain=system.clk_domain
19 dtb_filename=
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
22 eventq_index=0
23 flags_addr=268435504
24 gic_cpu_addr=520093952
25 init_param=0
26 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
27 load_addr_mask=268435455
28 machine_type=RealView_PBX
29 mem_mode=atomic
30 mem_ranges=0:134217727
31 memories=system.physmem system.realview.nvmem
32 multi_proc=true
33 num_work_ids=16
34 panic_on_oops=true
35 panic_on_panic=true
36 readfile=tests/halt.sh
37 symbolfile=
38 work_begin_ckpt_count=0
39 work_begin_cpu_id_exit=-1
40 work_begin_exit_count=0
41 work_cpus_ckpt_count=0
42 work_end_ckpt_count=0
43 work_end_exit_count=0
44 work_item_id=-1
45 system_port=system.membus.slave[0]
46
47 [system.bridge]
48 type=Bridge
49 clk_domain=system.clk_domain
50 delay=50000
51 eventq_index=0
52 ranges=268435456:520093695 1073741824:1610612735
53 req_size=16
54 resp_size=16
55 master=system.iobus.slave[0]
56 slave=system.membus.master[0]
57
58 [system.cf0]
59 type=IdeDisk
60 children=image
61 delay=1000000
62 driveID=master
63 eventq_index=0
64 image=system.cf0.image
65
66 [system.cf0.image]
67 type=CowDiskImage
68 children=child
69 child=system.cf0.image.child
70 eventq_index=0
71 image_file=
72 read_only=false
73 table_size=65536
74
75 [system.cf0.image.child]
76 type=RawDiskImage
77 eventq_index=0
78 image_file=/dist/disks/linux-arm-ael.img
79 read_only=true
80
81 [system.clk_domain]
82 type=SrcClockDomain
83 clock=1000
84 eventq_index=0
85 voltage_domain=system.voltage_domain
86
87 [system.cpu0]
88 type=AtomicSimpleCPU
89 children=dcache dtb icache interrupts isa itb tracer
90 checker=Null
91 clk_domain=system.cpu_clk_domain
92 cpu_id=0
93 do_checkpoint_insts=true
94 do_quiesce=true
95 do_statistics_insts=true
96 dtb=system.cpu0.dtb
97 eventq_index=0
98 fastmem=false
99 function_trace=false
100 function_trace_start=0
101 interrupts=system.cpu0.interrupts
102 isa=system.cpu0.isa
103 itb=system.cpu0.itb
104 max_insts_all_threads=0
105 max_insts_any_thread=0
106 max_loads_all_threads=0
107 max_loads_any_thread=0
108 numThreads=1
109 profile=0
110 progress_interval=0
111 simpoint_interval=100000000
112 simpoint_profile=false
113 simpoint_profile_file=simpoint.bb.gz
114 simpoint_start_insts=
115 simulate_data_stalls=false
116 simulate_inst_stalls=false
117 switched_out=false
118 system=system
119 tracer=system.cpu0.tracer
120 width=1
121 workload=
122 dcache_port=system.cpu0.dcache.cpu_side
123 icache_port=system.cpu0.icache.cpu_side
124
125 [system.cpu0.dcache]
126 type=BaseCache
127 children=tags
128 addr_ranges=0:18446744073709551615
129 assoc=4
130 clk_domain=system.cpu_clk_domain
131 eventq_index=0
132 forward_snoops=true
133 hit_latency=2
134 is_top_level=true
135 max_miss_count=0
136 mshrs=4
137 prefetch_on_access=false
138 prefetcher=Null
139 response_latency=2
140 sequential_access=false
141 size=32768
142 system=system
143 tags=system.cpu0.dcache.tags
144 tgts_per_mshr=20
145 two_queue=false
146 write_buffers=8
147 cpu_side=system.cpu0.dcache_port
148 mem_side=system.toL2Bus.slave[1]
149
150 [system.cpu0.dcache.tags]
151 type=LRU
152 assoc=4
153 block_size=64
154 clk_domain=system.cpu_clk_domain
155 eventq_index=0
156 hit_latency=2
157 sequential_access=false
158 size=32768
159
160 [system.cpu0.dtb]
161 type=ArmTLB
162 children=walker
163 eventq_index=0
164 size=64
165 walker=system.cpu0.dtb.walker
166
167 [system.cpu0.dtb.walker]
168 type=ArmTableWalker
169 clk_domain=system.cpu_clk_domain
170 eventq_index=0
171 num_squash_per_cycle=2
172 sys=system
173 port=system.toL2Bus.slave[3]
174
175 [system.cpu0.icache]
176 type=BaseCache
177 children=tags
178 addr_ranges=0:18446744073709551615
179 assoc=1
180 clk_domain=system.cpu_clk_domain
181 eventq_index=0
182 forward_snoops=true
183 hit_latency=2
184 is_top_level=true
185 max_miss_count=0
186 mshrs=4
187 prefetch_on_access=false
188 prefetcher=Null
189 response_latency=2
190 sequential_access=false
191 size=32768
192 system=system
193 tags=system.cpu0.icache.tags
194 tgts_per_mshr=20
195 two_queue=false
196 write_buffers=8
197 cpu_side=system.cpu0.icache_port
198 mem_side=system.toL2Bus.slave[0]
199
200 [system.cpu0.icache.tags]
201 type=LRU
202 assoc=1
203 block_size=64
204 clk_domain=system.cpu_clk_domain
205 eventq_index=0
206 hit_latency=2
207 sequential_access=false
208 size=32768
209
210 [system.cpu0.interrupts]
211 type=ArmInterrupts
212 eventq_index=0
213
214 [system.cpu0.isa]
215 type=ArmISA
216 eventq_index=0
217 fpsid=1090793632
218 id_isar0=34607377
219 id_isar1=34677009
220 id_isar2=555950401
221 id_isar3=17899825
222 id_isar4=268501314
223 id_isar5=0
224 id_mmfr0=3
225 id_mmfr1=0
226 id_mmfr2=19070976
227 id_mmfr3=4027589137
228 id_pfr0=49
229 id_pfr1=1
230 midr=890224640
231
232 [system.cpu0.itb]
233 type=ArmTLB
234 children=walker
235 eventq_index=0
236 size=64
237 walker=system.cpu0.itb.walker
238
239 [system.cpu0.itb.walker]
240 type=ArmTableWalker
241 clk_domain=system.cpu_clk_domain
242 eventq_index=0
243 num_squash_per_cycle=2
244 sys=system
245 port=system.toL2Bus.slave[2]
246
247 [system.cpu0.tracer]
248 type=ExeTracer
249 eventq_index=0
250
251 [system.cpu1]
252 type=TimingSimpleCPU
253 children=dtb isa itb tracer
254 checker=Null
255 clk_domain=system.cpu_clk_domain
256 cpu_id=0
257 do_checkpoint_insts=true
258 do_quiesce=true
259 do_statistics_insts=true
260 dtb=system.cpu1.dtb
261 eventq_index=0
262 function_trace=false
263 function_trace_start=0
264 interrupts=Null
265 isa=system.cpu1.isa
266 itb=system.cpu1.itb
267 max_insts_all_threads=0
268 max_insts_any_thread=0
269 max_loads_all_threads=0
270 max_loads_any_thread=0
271 numThreads=1
272 profile=0
273 progress_interval=0
274 simpoint_start_insts=
275 switched_out=true
276 system=system
277 tracer=system.cpu1.tracer
278 workload=
279
280 [system.cpu1.dtb]
281 type=ArmTLB
282 children=walker
283 eventq_index=0
284 size=64
285 walker=system.cpu1.dtb.walker
286
287 [system.cpu1.dtb.walker]
288 type=ArmTableWalker
289 clk_domain=system.cpu_clk_domain
290 eventq_index=0
291 num_squash_per_cycle=2
292 sys=system
293
294 [system.cpu1.isa]
295 type=ArmISA
296 eventq_index=0
297 fpsid=1090793632
298 id_isar0=34607377
299 id_isar1=34677009
300 id_isar2=555950401
301 id_isar3=17899825
302 id_isar4=268501314
303 id_isar5=0
304 id_mmfr0=3
305 id_mmfr1=0
306 id_mmfr2=19070976
307 id_mmfr3=4027589137
308 id_pfr0=49
309 id_pfr1=1
310 midr=890224640
311
312 [system.cpu1.itb]
313 type=ArmTLB
314 children=walker
315 eventq_index=0
316 size=64
317 walker=system.cpu1.itb.walker
318
319 [system.cpu1.itb.walker]
320 type=ArmTableWalker
321 clk_domain=system.cpu_clk_domain
322 eventq_index=0
323 num_squash_per_cycle=2
324 sys=system
325
326 [system.cpu1.tracer]
327 type=ExeTracer
328 eventq_index=0
329
330 [system.cpu2]
331 type=DerivO3CPU
332 children=branchPred dtb fuPool isa itb tracer
333 LFSTSize=1024
334 LQEntries=32
335 LSQCheckLoads=true
336 LSQDepCheckShift=4
337 SQEntries=32
338 SSITSize=1024
339 activity=0
340 backComSize=5
341 branchPred=system.cpu2.branchPred
342 cachePorts=200
343 checker=Null
344 clk_domain=system.cpu_clk_domain
345 commitToDecodeDelay=1
346 commitToFetchDelay=1
347 commitToIEWDelay=1
348 commitToRenameDelay=1
349 commitWidth=8
350 cpu_id=0
351 decodeToFetchDelay=1
352 decodeToRenameDelay=1
353 decodeWidth=8
354 dispatchWidth=8
355 do_checkpoint_insts=true
356 do_quiesce=true
357 do_statistics_insts=true
358 dtb=system.cpu2.dtb
359 eventq_index=0
360 fetchBufferSize=64
361 fetchToDecodeDelay=1
362 fetchTrapLatency=1
363 fetchWidth=8
364 forwardComSize=5
365 fuPool=system.cpu2.fuPool
366 function_trace=false
367 function_trace_start=0
368 iewToCommitDelay=1
369 iewToDecodeDelay=1
370 iewToFetchDelay=1
371 iewToRenameDelay=1
372 interrupts=Null
373 isa=system.cpu2.isa
374 issueToExecuteDelay=1
375 issueWidth=8
376 itb=system.cpu2.itb
377 max_insts_all_threads=0
378 max_insts_any_thread=0
379 max_loads_all_threads=0
380 max_loads_any_thread=0
381 needsTSO=false
382 numIQEntries=64
383 numPhysCCRegs=0
384 numPhysFloatRegs=256
385 numPhysIntRegs=256
386 numROBEntries=192
387 numRobs=1
388 numThreads=1
389 profile=0
390 progress_interval=0
391 renameToDecodeDelay=1
392 renameToFetchDelay=1
393 renameToIEWDelay=2
394 renameToROBDelay=1
395 renameWidth=8
396 simpoint_start_insts=
397 smtCommitPolicy=RoundRobin
398 smtFetchPolicy=SingleThread
399 smtIQPolicy=Partitioned
400 smtIQThreshold=100
401 smtLSQPolicy=Partitioned
402 smtLSQThreshold=100
403 smtNumFetchingThreads=1
404 smtROBPolicy=Partitioned
405 smtROBThreshold=100
406 squashWidth=8
407 store_set_clear_period=250000
408 switched_out=true
409 system=system
410 tracer=system.cpu2.tracer
411 trapLatency=13
412 wbDepth=1
413 wbWidth=8
414 workload=
415
416 [system.cpu2.branchPred]
417 type=BranchPredictor
418 BTBEntries=4096
419 BTBTagSize=16
420 RASSize=16
421 choiceCtrBits=2
422 choicePredictorSize=8192
423 eventq_index=0
424 globalCtrBits=2
425 globalPredictorSize=8192
426 instShiftAmt=2
427 localCtrBits=2
428 localHistoryTableSize=2048
429 localPredictorSize=2048
430 numThreads=1
431 predType=tournament
432
433 [system.cpu2.dtb]
434 type=ArmTLB
435 children=walker
436 eventq_index=0
437 size=64
438 walker=system.cpu2.dtb.walker
439
440 [system.cpu2.dtb.walker]
441 type=ArmTableWalker
442 clk_domain=system.cpu_clk_domain
443 eventq_index=0
444 num_squash_per_cycle=2
445 sys=system
446
447 [system.cpu2.fuPool]
448 type=FUPool
449 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
450 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
451 eventq_index=0
452
453 [system.cpu2.fuPool.FUList0]
454 type=FUDesc
455 children=opList
456 count=6
457 eventq_index=0
458 opList=system.cpu2.fuPool.FUList0.opList
459
460 [system.cpu2.fuPool.FUList0.opList]
461 type=OpDesc
462 eventq_index=0
463 issueLat=1
464 opClass=IntAlu
465 opLat=1
466
467 [system.cpu2.fuPool.FUList1]
468 type=FUDesc
469 children=opList0 opList1
470 count=2
471 eventq_index=0
472 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
473
474 [system.cpu2.fuPool.FUList1.opList0]
475 type=OpDesc
476 eventq_index=0
477 issueLat=1
478 opClass=IntMult
479 opLat=3
480
481 [system.cpu2.fuPool.FUList1.opList1]
482 type=OpDesc
483 eventq_index=0
484 issueLat=19
485 opClass=IntDiv
486 opLat=20
487
488 [system.cpu2.fuPool.FUList2]
489 type=FUDesc
490 children=opList0 opList1 opList2
491 count=4
492 eventq_index=0
493 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
494
495 [system.cpu2.fuPool.FUList2.opList0]
496 type=OpDesc
497 eventq_index=0
498 issueLat=1
499 opClass=FloatAdd
500 opLat=2
501
502 [system.cpu2.fuPool.FUList2.opList1]
503 type=OpDesc
504 eventq_index=0
505 issueLat=1
506 opClass=FloatCmp
507 opLat=2
508
509 [system.cpu2.fuPool.FUList2.opList2]
510 type=OpDesc
511 eventq_index=0
512 issueLat=1
513 opClass=FloatCvt
514 opLat=2
515
516 [system.cpu2.fuPool.FUList3]
517 type=FUDesc
518 children=opList0 opList1 opList2
519 count=2
520 eventq_index=0
521 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
522
523 [system.cpu2.fuPool.FUList3.opList0]
524 type=OpDesc
525 eventq_index=0
526 issueLat=1
527 opClass=FloatMult
528 opLat=4
529
530 [system.cpu2.fuPool.FUList3.opList1]
531 type=OpDesc
532 eventq_index=0
533 issueLat=12
534 opClass=FloatDiv
535 opLat=12
536
537 [system.cpu2.fuPool.FUList3.opList2]
538 type=OpDesc
539 eventq_index=0
540 issueLat=24
541 opClass=FloatSqrt
542 opLat=24
543
544 [system.cpu2.fuPool.FUList4]
545 type=FUDesc
546 children=opList
547 count=0
548 eventq_index=0
549 opList=system.cpu2.fuPool.FUList4.opList
550
551 [system.cpu2.fuPool.FUList4.opList]
552 type=OpDesc
553 eventq_index=0
554 issueLat=1
555 opClass=MemRead
556 opLat=1
557
558 [system.cpu2.fuPool.FUList5]
559 type=FUDesc
560 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
561 count=4
562 eventq_index=0
563 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
564
565 [system.cpu2.fuPool.FUList5.opList00]
566 type=OpDesc
567 eventq_index=0
568 issueLat=1
569 opClass=SimdAdd
570 opLat=1
571
572 [system.cpu2.fuPool.FUList5.opList01]
573 type=OpDesc
574 eventq_index=0
575 issueLat=1
576 opClass=SimdAddAcc
577 opLat=1
578
579 [system.cpu2.fuPool.FUList5.opList02]
580 type=OpDesc
581 eventq_index=0
582 issueLat=1
583 opClass=SimdAlu
584 opLat=1
585
586 [system.cpu2.fuPool.FUList5.opList03]
587 type=OpDesc
588 eventq_index=0
589 issueLat=1
590 opClass=SimdCmp
591 opLat=1
592
593 [system.cpu2.fuPool.FUList5.opList04]
594 type=OpDesc
595 eventq_index=0
596 issueLat=1
597 opClass=SimdCvt
598 opLat=1
599
600 [system.cpu2.fuPool.FUList5.opList05]
601 type=OpDesc
602 eventq_index=0
603 issueLat=1
604 opClass=SimdMisc
605 opLat=1
606
607 [system.cpu2.fuPool.FUList5.opList06]
608 type=OpDesc
609 eventq_index=0
610 issueLat=1
611 opClass=SimdMult
612 opLat=1
613
614 [system.cpu2.fuPool.FUList5.opList07]
615 type=OpDesc
616 eventq_index=0
617 issueLat=1
618 opClass=SimdMultAcc
619 opLat=1
620
621 [system.cpu2.fuPool.FUList5.opList08]
622 type=OpDesc
623 eventq_index=0
624 issueLat=1
625 opClass=SimdShift
626 opLat=1
627
628 [system.cpu2.fuPool.FUList5.opList09]
629 type=OpDesc
630 eventq_index=0
631 issueLat=1
632 opClass=SimdShiftAcc
633 opLat=1
634
635 [system.cpu2.fuPool.FUList5.opList10]
636 type=OpDesc
637 eventq_index=0
638 issueLat=1
639 opClass=SimdSqrt
640 opLat=1
641
642 [system.cpu2.fuPool.FUList5.opList11]
643 type=OpDesc
644 eventq_index=0
645 issueLat=1
646 opClass=SimdFloatAdd
647 opLat=1
648
649 [system.cpu2.fuPool.FUList5.opList12]
650 type=OpDesc
651 eventq_index=0
652 issueLat=1
653 opClass=SimdFloatAlu
654 opLat=1
655
656 [system.cpu2.fuPool.FUList5.opList13]
657 type=OpDesc
658 eventq_index=0
659 issueLat=1
660 opClass=SimdFloatCmp
661 opLat=1
662
663 [system.cpu2.fuPool.FUList5.opList14]
664 type=OpDesc
665 eventq_index=0
666 issueLat=1
667 opClass=SimdFloatCvt
668 opLat=1
669
670 [system.cpu2.fuPool.FUList5.opList15]
671 type=OpDesc
672 eventq_index=0
673 issueLat=1
674 opClass=SimdFloatDiv
675 opLat=1
676
677 [system.cpu2.fuPool.FUList5.opList16]
678 type=OpDesc
679 eventq_index=0
680 issueLat=1
681 opClass=SimdFloatMisc
682 opLat=1
683
684 [system.cpu2.fuPool.FUList5.opList17]
685 type=OpDesc
686 eventq_index=0
687 issueLat=1
688 opClass=SimdFloatMult
689 opLat=1
690
691 [system.cpu2.fuPool.FUList5.opList18]
692 type=OpDesc
693 eventq_index=0
694 issueLat=1
695 opClass=SimdFloatMultAcc
696 opLat=1
697
698 [system.cpu2.fuPool.FUList5.opList19]
699 type=OpDesc
700 eventq_index=0
701 issueLat=1
702 opClass=SimdFloatSqrt
703 opLat=1
704
705 [system.cpu2.fuPool.FUList6]
706 type=FUDesc
707 children=opList
708 count=0
709 eventq_index=0
710 opList=system.cpu2.fuPool.FUList6.opList
711
712 [system.cpu2.fuPool.FUList6.opList]
713 type=OpDesc
714 eventq_index=0
715 issueLat=1
716 opClass=MemWrite
717 opLat=1
718
719 [system.cpu2.fuPool.FUList7]
720 type=FUDesc
721 children=opList0 opList1
722 count=4
723 eventq_index=0
724 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
725
726 [system.cpu2.fuPool.FUList7.opList0]
727 type=OpDesc
728 eventq_index=0
729 issueLat=1
730 opClass=MemRead
731 opLat=1
732
733 [system.cpu2.fuPool.FUList7.opList1]
734 type=OpDesc
735 eventq_index=0
736 issueLat=1
737 opClass=MemWrite
738 opLat=1
739
740 [system.cpu2.fuPool.FUList8]
741 type=FUDesc
742 children=opList
743 count=1
744 eventq_index=0
745 opList=system.cpu2.fuPool.FUList8.opList
746
747 [system.cpu2.fuPool.FUList8.opList]
748 type=OpDesc
749 eventq_index=0
750 issueLat=3
751 opClass=IprAccess
752 opLat=3
753
754 [system.cpu2.isa]
755 type=ArmISA
756 eventq_index=0
757 fpsid=1090793632
758 id_isar0=34607377
759 id_isar1=34677009
760 id_isar2=555950401
761 id_isar3=17899825
762 id_isar4=268501314
763 id_isar5=0
764 id_mmfr0=3
765 id_mmfr1=0
766 id_mmfr2=19070976
767 id_mmfr3=4027589137
768 id_pfr0=49
769 id_pfr1=1
770 midr=890224640
771
772 [system.cpu2.itb]
773 type=ArmTLB
774 children=walker
775 eventq_index=0
776 size=64
777 walker=system.cpu2.itb.walker
778
779 [system.cpu2.itb.walker]
780 type=ArmTableWalker
781 clk_domain=system.cpu_clk_domain
782 eventq_index=0
783 num_squash_per_cycle=2
784 sys=system
785
786 [system.cpu2.tracer]
787 type=ExeTracer
788 eventq_index=0
789
790 [system.cpu_clk_domain]
791 type=SrcClockDomain
792 clock=500
793 eventq_index=0
794 voltage_domain=system.voltage_domain
795
796 [system.intrctrl]
797 type=IntrControl
798 eventq_index=0
799 sys=system
800
801 [system.iobus]
802 type=NoncoherentBus
803 clk_domain=system.clk_domain
804 eventq_index=0
805 header_cycles=1
806 use_default_range=false
807 width=8
808 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
809 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
810
811 [system.iocache]
812 type=BaseCache
813 children=tags
814 addr_ranges=0:134217727
815 assoc=8
816 clk_domain=system.clk_domain
817 eventq_index=0
818 forward_snoops=false
819 hit_latency=50
820 is_top_level=true
821 max_miss_count=0
822 mshrs=20
823 prefetch_on_access=false
824 prefetcher=Null
825 response_latency=50
826 sequential_access=false
827 size=1024
828 system=system
829 tags=system.iocache.tags
830 tgts_per_mshr=12
831 two_queue=false
832 write_buffers=8
833 cpu_side=system.iobus.master[25]
834 mem_side=system.membus.slave[2]
835
836 [system.iocache.tags]
837 type=LRU
838 assoc=8
839 block_size=64
840 clk_domain=system.clk_domain
841 eventq_index=0
842 hit_latency=50
843 sequential_access=false
844 size=1024
845
846 [system.l2c]
847 type=BaseCache
848 children=tags
849 addr_ranges=0:18446744073709551615
850 assoc=8
851 clk_domain=system.cpu_clk_domain
852 eventq_index=0
853 forward_snoops=true
854 hit_latency=20
855 is_top_level=false
856 max_miss_count=0
857 mshrs=20
858 prefetch_on_access=false
859 prefetcher=Null
860 response_latency=20
861 sequential_access=false
862 size=4194304
863 system=system
864 tags=system.l2c.tags
865 tgts_per_mshr=12
866 two_queue=false
867 write_buffers=8
868 cpu_side=system.toL2Bus.master[0]
869 mem_side=system.membus.slave[1]
870
871 [system.l2c.tags]
872 type=LRU
873 assoc=8
874 block_size=64
875 clk_domain=system.cpu_clk_domain
876 eventq_index=0
877 hit_latency=20
878 sequential_access=false
879 size=4194304
880
881 [system.membus]
882 type=CoherentBus
883 children=badaddr_responder
884 clk_domain=system.clk_domain
885 eventq_index=0
886 header_cycles=1
887 system=system
888 use_default_range=false
889 width=8
890 default=system.membus.badaddr_responder.pio
891 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
892 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
893
894 [system.membus.badaddr_responder]
895 type=IsaFake
896 clk_domain=system.clk_domain
897 eventq_index=0
898 fake_mem=false
899 pio_addr=0
900 pio_latency=100000
901 pio_size=8
902 ret_bad_addr=true
903 ret_data16=65535
904 ret_data32=4294967295
905 ret_data64=18446744073709551615
906 ret_data8=255
907 system=system
908 update_data=false
909 warn_access=warn
910 pio=system.membus.default
911
912 [system.physmem]
913 type=SimpleDRAM
914 activation_limit=4
915 addr_mapping=RaBaChCo
916 banks_per_rank=8
917 burst_length=8
918 channels=1
919 clk_domain=system.clk_domain
920 conf_table_reported=true
921 device_bus_width=8
922 device_rowbuffer_size=1024
923 devices_per_rank=8
924 eventq_index=0
925 in_addr_map=true
926 mem_sched_policy=frfcfs
927 null=false
928 page_policy=open
929 range=0:134217727
930 ranks_per_channel=2
931 read_buffer_size=32
932 static_backend_latency=10000
933 static_frontend_latency=10000
934 tBURST=5000
935 tCL=13750
936 tRAS=35000
937 tRCD=13750
938 tREFI=7800000
939 tRFC=300000
940 tRP=13750
941 tRRD=6250
942 tWTR=7500
943 tXAW=40000
944 write_buffer_size=32
945 write_high_thresh_perc=70
946 write_low_thresh_perc=0
947 port=system.membus.master[6]
948
949 [system.realview]
950 type=RealView
951 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
952 eventq_index=0
953 intrctrl=system.intrctrl
954 max_mem_size=268435456
955 mem_start_addr=0
956 pci_cfg_base=0
957 system=system
958
959 [system.realview.a9scu]
960 type=A9SCU
961 clk_domain=system.clk_domain
962 eventq_index=0
963 pio_addr=520093696
964 pio_latency=100000
965 system=system
966 pio=system.membus.master[4]
967
968 [system.realview.aaci_fake]
969 type=AmbaFake
970 amba_id=0
971 clk_domain=system.clk_domain
972 eventq_index=0
973 ignore_access=false
974 pio_addr=268451840
975 pio_latency=100000
976 system=system
977 pio=system.iobus.master[21]
978
979 [system.realview.cf_ctrl]
980 type=IdeController
981 BAR0=402653184
982 BAR0LegacyIO=true
983 BAR0Size=16
984 BAR1=402653440
985 BAR1LegacyIO=true
986 BAR1Size=1
987 BAR2=1
988 BAR2LegacyIO=false
989 BAR2Size=8
990 BAR3=1
991 BAR3LegacyIO=false
992 BAR3Size=4
993 BAR4=1
994 BAR4LegacyIO=false
995 BAR4Size=16
996 BAR5=1
997 BAR5LegacyIO=false
998 BAR5Size=0
999 BIST=0
1000 CacheLineSize=0
1001 CapabilityPtr=0
1002 CardbusCIS=0
1003 ClassCode=1
1004 Command=1
1005 DeviceID=28945
1006 ExpansionROM=0
1007 HeaderType=0
1008 InterruptLine=31
1009 InterruptPin=1
1010 LatencyTimer=0
1011 MSICAPBaseOffset=0
1012 MSICAPCapId=0
1013 MSICAPMaskBits=0
1014 MSICAPMsgAddr=0
1015 MSICAPMsgCtrl=0
1016 MSICAPMsgData=0
1017 MSICAPMsgUpperAddr=0
1018 MSICAPNextCapability=0
1019 MSICAPPendingBits=0
1020 MSIXCAPBaseOffset=0
1021 MSIXCAPCapId=0
1022 MSIXCAPNextCapability=0
1023 MSIXMsgCtrl=0
1024 MSIXPbaOffset=0
1025 MSIXTableOffset=0
1026 MaximumLatency=0
1027 MinimumGrant=0
1028 PMCAPBaseOffset=0
1029 PMCAPCapId=0
1030 PMCAPCapabilities=0
1031 PMCAPCtrlStatus=0
1032 PMCAPNextCapability=0
1033 PXCAPBaseOffset=0
1034 PXCAPCapId=0
1035 PXCAPCapabilities=0
1036 PXCAPDevCap2=0
1037 PXCAPDevCapabilities=0
1038 PXCAPDevCtrl=0
1039 PXCAPDevCtrl2=0
1040 PXCAPDevStatus=0
1041 PXCAPLinkCap=0
1042 PXCAPLinkCtrl=0
1043 PXCAPLinkStatus=0
1044 PXCAPNextCapability=0
1045 ProgIF=133
1046 Revision=0
1047 Status=640
1048 SubClassCode=1
1049 SubsystemID=0
1050 SubsystemVendorID=0
1051 VendorID=32902
1052 clk_domain=system.clk_domain
1053 config_latency=20000
1054 ctrl_offset=2
1055 disks=system.cf0
1056 eventq_index=0
1057 io_shift=1
1058 pci_bus=2
1059 pci_dev=7
1060 pci_func=0
1061 pio_latency=30000
1062 platform=system.realview
1063 system=system
1064 config=system.iobus.master[8]
1065 dma=system.iobus.slave[2]
1066 pio=system.iobus.master[7]
1067
1068 [system.realview.clcd]
1069 type=Pl111
1070 amba_id=1315089
1071 clk_domain=system.clk_domain
1072 enable_capture=true
1073 eventq_index=0
1074 gic=system.realview.gic
1075 int_num=55
1076 pio_addr=268566528
1077 pio_latency=10000
1078 pixel_clock=41667
1079 system=system
1080 vnc=system.vncserver
1081 dma=system.iobus.slave[1]
1082 pio=system.iobus.master[4]
1083
1084 [system.realview.dmac_fake]
1085 type=AmbaFake
1086 amba_id=0
1087 clk_domain=system.clk_domain
1088 eventq_index=0
1089 ignore_access=false
1090 pio_addr=268632064
1091 pio_latency=100000
1092 system=system
1093 pio=system.iobus.master[9]
1094
1095 [system.realview.flash_fake]
1096 type=IsaFake
1097 clk_domain=system.clk_domain
1098 eventq_index=0
1099 fake_mem=true
1100 pio_addr=1073741824
1101 pio_latency=100000
1102 pio_size=536870912
1103 ret_bad_addr=false
1104 ret_data16=65535
1105 ret_data32=4294967295
1106 ret_data64=18446744073709551615
1107 ret_data8=255
1108 system=system
1109 update_data=false
1110 warn_access=
1111 pio=system.iobus.master[24]
1112
1113 [system.realview.gic]
1114 type=Pl390
1115 clk_domain=system.clk_domain
1116 cpu_addr=520093952
1117 cpu_pio_delay=10000
1118 dist_addr=520097792
1119 dist_pio_delay=10000
1120 eventq_index=0
1121 int_latency=10000
1122 it_lines=128
1123 msix_addr=0
1124 platform=system.realview
1125 system=system
1126 pio=system.membus.master[2]
1127
1128 [system.realview.gpio0_fake]
1129 type=AmbaFake
1130 amba_id=0
1131 clk_domain=system.clk_domain
1132 eventq_index=0
1133 ignore_access=false
1134 pio_addr=268513280
1135 pio_latency=100000
1136 system=system
1137 pio=system.iobus.master[16]
1138
1139 [system.realview.gpio1_fake]
1140 type=AmbaFake
1141 amba_id=0
1142 clk_domain=system.clk_domain
1143 eventq_index=0
1144 ignore_access=false
1145 pio_addr=268517376
1146 pio_latency=100000
1147 system=system
1148 pio=system.iobus.master[17]
1149
1150 [system.realview.gpio2_fake]
1151 type=AmbaFake
1152 amba_id=0
1153 clk_domain=system.clk_domain
1154 eventq_index=0
1155 ignore_access=false
1156 pio_addr=268521472
1157 pio_latency=100000
1158 system=system
1159 pio=system.iobus.master[18]
1160
1161 [system.realview.kmi0]
1162 type=Pl050
1163 amba_id=1314896
1164 clk_domain=system.clk_domain
1165 eventq_index=0
1166 gic=system.realview.gic
1167 int_delay=1000000
1168 int_num=52
1169 is_mouse=false
1170 pio_addr=268460032
1171 pio_latency=100000
1172 system=system
1173 vnc=system.vncserver
1174 pio=system.iobus.master[5]
1175
1176 [system.realview.kmi1]
1177 type=Pl050
1178 amba_id=1314896
1179 clk_domain=system.clk_domain
1180 eventq_index=0
1181 gic=system.realview.gic
1182 int_delay=1000000
1183 int_num=53
1184 is_mouse=true
1185 pio_addr=268464128
1186 pio_latency=100000
1187 system=system
1188 vnc=system.vncserver
1189 pio=system.iobus.master[6]
1190
1191 [system.realview.l2x0_fake]
1192 type=IsaFake
1193 clk_domain=system.clk_domain
1194 eventq_index=0
1195 fake_mem=false
1196 pio_addr=520101888
1197 pio_latency=100000
1198 pio_size=4095
1199 ret_bad_addr=false
1200 ret_data16=65535
1201 ret_data32=4294967295
1202 ret_data64=18446744073709551615
1203 ret_data8=255
1204 system=system
1205 update_data=false
1206 warn_access=
1207 pio=system.membus.master[3]
1208
1209 [system.realview.local_cpu_timer]
1210 type=CpuLocalTimer
1211 clk_domain=system.clk_domain
1212 eventq_index=0
1213 gic=system.realview.gic
1214 int_num_timer=29
1215 int_num_watchdog=30
1216 pio_addr=520095232
1217 pio_latency=100000
1218 system=system
1219 pio=system.membus.master[5]
1220
1221 [system.realview.mmc_fake]
1222 type=AmbaFake
1223 amba_id=0
1224 clk_domain=system.clk_domain
1225 eventq_index=0
1226 ignore_access=false
1227 pio_addr=268455936
1228 pio_latency=100000
1229 system=system
1230 pio=system.iobus.master[22]
1231
1232 [system.realview.nvmem]
1233 type=SimpleMemory
1234 bandwidth=73.000000
1235 clk_domain=system.clk_domain
1236 conf_table_reported=false
1237 eventq_index=0
1238 in_addr_map=true
1239 latency=30000
1240 latency_var=0
1241 null=false
1242 range=2147483648:2214592511
1243 port=system.membus.master[1]
1244
1245 [system.realview.realview_io]
1246 type=RealViewCtrl
1247 clk_domain=system.clk_domain
1248 eventq_index=0
1249 idreg=0
1250 pio_addr=268435456
1251 pio_latency=100000
1252 proc_id0=201326592
1253 proc_id1=201327138
1254 system=system
1255 pio=system.iobus.master[1]
1256
1257 [system.realview.rtc]
1258 type=PL031
1259 amba_id=3412017
1260 clk_domain=system.clk_domain
1261 eventq_index=0
1262 gic=system.realview.gic
1263 int_delay=100000
1264 int_num=42
1265 pio_addr=268529664
1266 pio_latency=100000
1267 system=system
1268 time=Thu Jan 1 00:00:00 2009
1269 pio=system.iobus.master[23]
1270
1271 [system.realview.sci_fake]
1272 type=AmbaFake
1273 amba_id=0
1274 clk_domain=system.clk_domain
1275 eventq_index=0
1276 ignore_access=false
1277 pio_addr=268492800
1278 pio_latency=100000
1279 system=system
1280 pio=system.iobus.master[20]
1281
1282 [system.realview.smc_fake]
1283 type=AmbaFake
1284 amba_id=0
1285 clk_domain=system.clk_domain
1286 eventq_index=0
1287 ignore_access=false
1288 pio_addr=269357056
1289 pio_latency=100000
1290 system=system
1291 pio=system.iobus.master[13]
1292
1293 [system.realview.sp810_fake]
1294 type=AmbaFake
1295 amba_id=0
1296 clk_domain=system.clk_domain
1297 eventq_index=0
1298 ignore_access=true
1299 pio_addr=268439552
1300 pio_latency=100000
1301 system=system
1302 pio=system.iobus.master[14]
1303
1304 [system.realview.ssp_fake]
1305 type=AmbaFake
1306 amba_id=0
1307 clk_domain=system.clk_domain
1308 eventq_index=0
1309 ignore_access=false
1310 pio_addr=268488704
1311 pio_latency=100000
1312 system=system
1313 pio=system.iobus.master[19]
1314
1315 [system.realview.timer0]
1316 type=Sp804
1317 amba_id=1316868
1318 clk_domain=system.clk_domain
1319 clock0=1000000
1320 clock1=1000000
1321 eventq_index=0
1322 gic=system.realview.gic
1323 int_num0=36
1324 int_num1=36
1325 pio_addr=268505088
1326 pio_latency=100000
1327 system=system
1328 pio=system.iobus.master[2]
1329
1330 [system.realview.timer1]
1331 type=Sp804
1332 amba_id=1316868
1333 clk_domain=system.clk_domain
1334 clock0=1000000
1335 clock1=1000000
1336 eventq_index=0
1337 gic=system.realview.gic
1338 int_num0=37
1339 int_num1=37
1340 pio_addr=268509184
1341 pio_latency=100000
1342 system=system
1343 pio=system.iobus.master[3]
1344
1345 [system.realview.uart]
1346 type=Pl011
1347 clk_domain=system.clk_domain
1348 end_on_eot=false
1349 eventq_index=0
1350 gic=system.realview.gic
1351 int_delay=100000
1352 int_num=44
1353 pio_addr=268472320
1354 pio_latency=100000
1355 platform=system.realview
1356 system=system
1357 terminal=system.terminal
1358 pio=system.iobus.master[0]
1359
1360 [system.realview.uart1_fake]
1361 type=AmbaFake
1362 amba_id=0
1363 clk_domain=system.clk_domain
1364 eventq_index=0
1365 ignore_access=false
1366 pio_addr=268476416
1367 pio_latency=100000
1368 system=system
1369 pio=system.iobus.master[10]
1370
1371 [system.realview.uart2_fake]
1372 type=AmbaFake
1373 amba_id=0
1374 clk_domain=system.clk_domain
1375 eventq_index=0
1376 ignore_access=false
1377 pio_addr=268480512
1378 pio_latency=100000
1379 system=system
1380 pio=system.iobus.master[11]
1381
1382 [system.realview.uart3_fake]
1383 type=AmbaFake
1384 amba_id=0
1385 clk_domain=system.clk_domain
1386 eventq_index=0
1387 ignore_access=false
1388 pio_addr=268484608
1389 pio_latency=100000
1390 system=system
1391 pio=system.iobus.master[12]
1392
1393 [system.realview.watchdog_fake]
1394 type=AmbaFake
1395 amba_id=0
1396 clk_domain=system.clk_domain
1397 eventq_index=0
1398 ignore_access=false
1399 pio_addr=268500992
1400 pio_latency=100000
1401 system=system
1402 pio=system.iobus.master[15]
1403
1404 [system.terminal]
1405 type=Terminal
1406 eventq_index=0
1407 intr_control=system.intrctrl
1408 number=0
1409 output=true
1410 port=3456
1411
1412 [system.toL2Bus]
1413 type=CoherentBus
1414 clk_domain=system.cpu_clk_domain
1415 eventq_index=0
1416 header_cycles=1
1417 system=system
1418 use_default_range=false
1419 width=8
1420 master=system.l2c.cpu_side
1421 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
1422
1423 [system.vncserver]
1424 type=VncServer
1425 eventq_index=0
1426 frame_capture=false
1427 number=0
1428 port=5900
1429
1430 [system.voltage_domain]
1431 type=VoltageDomain
1432 eventq_index=0
1433 voltage=1.000000
1434