8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/dist/binaries/boot.arm
16 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
18 clk_domain=system.clk_domain
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
24 gic_cpu_addr=520093952
26 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
27 load_addr_mask=268435455
28 machine_type=RealView_PBX
30 mem_ranges=0:134217727
31 memories=system.physmem system.realview.nvmem
36 readfile=tests/halt.sh
38 work_begin_ckpt_count=0
39 work_begin_cpu_id_exit=-1
40 work_begin_exit_count=0
41 work_cpus_ckpt_count=0
45 system_port=system.membus.slave[0]
49 clk_domain=system.clk_domain
52 ranges=268435456:520093695 1073741824:1610612735
55 master=system.iobus.slave[0]
56 slave=system.membus.master[0]
64 image=system.cf0.image
69 child=system.cf0.image.child
75 [system.cf0.image.child]
78 image_file=/dist/disks/linux-arm-ael.img
85 voltage_domain=system.voltage_domain
89 children=dcache dtb icache interrupts isa itb tracer
91 clk_domain=system.cpu_clk_domain
93 do_checkpoint_insts=true
95 do_statistics_insts=true
100 function_trace_start=0
101 interrupts=system.cpu0.interrupts
104 max_insts_all_threads=0
105 max_insts_any_thread=0
106 max_loads_all_threads=0
107 max_loads_any_thread=0
111 simpoint_interval=100000000
112 simpoint_profile=false
113 simpoint_profile_file=simpoint.bb.gz
114 simpoint_start_insts=
115 simulate_data_stalls=false
116 simulate_inst_stalls=false
119 tracer=system.cpu0.tracer
122 dcache_port=system.cpu0.dcache.cpu_side
123 icache_port=system.cpu0.icache.cpu_side
128 addr_ranges=0:18446744073709551615
130 clk_domain=system.cpu_clk_domain
137 prefetch_on_access=false
140 sequential_access=false
143 tags=system.cpu0.dcache.tags
147 cpu_side=system.cpu0.dcache_port
148 mem_side=system.toL2Bus.slave[1]
150 [system.cpu0.dcache.tags]
154 clk_domain=system.cpu_clk_domain
157 sequential_access=false
165 walker=system.cpu0.dtb.walker
167 [system.cpu0.dtb.walker]
169 clk_domain=system.cpu_clk_domain
171 num_squash_per_cycle=2
173 port=system.toL2Bus.slave[3]
178 addr_ranges=0:18446744073709551615
180 clk_domain=system.cpu_clk_domain
187 prefetch_on_access=false
190 sequential_access=false
193 tags=system.cpu0.icache.tags
197 cpu_side=system.cpu0.icache_port
198 mem_side=system.toL2Bus.slave[0]
200 [system.cpu0.icache.tags]
204 clk_domain=system.cpu_clk_domain
207 sequential_access=false
210 [system.cpu0.interrupts]
237 walker=system.cpu0.itb.walker
239 [system.cpu0.itb.walker]
241 clk_domain=system.cpu_clk_domain
243 num_squash_per_cycle=2
245 port=system.toL2Bus.slave[2]
253 children=dtb isa itb tracer
255 clk_domain=system.cpu_clk_domain
257 do_checkpoint_insts=true
259 do_statistics_insts=true
263 function_trace_start=0
267 max_insts_all_threads=0
268 max_insts_any_thread=0
269 max_loads_all_threads=0
270 max_loads_any_thread=0
274 simpoint_start_insts=
277 tracer=system.cpu1.tracer
285 walker=system.cpu1.dtb.walker
287 [system.cpu1.dtb.walker]
289 clk_domain=system.cpu_clk_domain
291 num_squash_per_cycle=2
317 walker=system.cpu1.itb.walker
319 [system.cpu1.itb.walker]
321 clk_domain=system.cpu_clk_domain
323 num_squash_per_cycle=2
332 children=branchPred dtb fuPool isa itb tracer
341 branchPred=system.cpu2.branchPred
344 clk_domain=system.cpu_clk_domain
345 commitToDecodeDelay=1
348 commitToRenameDelay=1
352 decodeToRenameDelay=1
355 do_checkpoint_insts=true
357 do_statistics_insts=true
365 fuPool=system.cpu2.fuPool
367 function_trace_start=0
374 issueToExecuteDelay=1
377 max_insts_all_threads=0
378 max_insts_any_thread=0
379 max_loads_all_threads=0
380 max_loads_any_thread=0
391 renameToDecodeDelay=1
396 simpoint_start_insts=
397 smtCommitPolicy=RoundRobin
398 smtFetchPolicy=SingleThread
399 smtIQPolicy=Partitioned
401 smtLSQPolicy=Partitioned
403 smtNumFetchingThreads=1
404 smtROBPolicy=Partitioned
407 store_set_clear_period=250000
410 tracer=system.cpu2.tracer
416 [system.cpu2.branchPred]
422 choicePredictorSize=8192
425 globalPredictorSize=8192
428 localHistoryTableSize=2048
429 localPredictorSize=2048
438 walker=system.cpu2.dtb.walker
440 [system.cpu2.dtb.walker]
442 clk_domain=system.cpu_clk_domain
444 num_squash_per_cycle=2
449 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
450 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
453 [system.cpu2.fuPool.FUList0]
458 opList=system.cpu2.fuPool.FUList0.opList
460 [system.cpu2.fuPool.FUList0.opList]
467 [system.cpu2.fuPool.FUList1]
469 children=opList0 opList1
472 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
474 [system.cpu2.fuPool.FUList1.opList0]
481 [system.cpu2.fuPool.FUList1.opList1]
488 [system.cpu2.fuPool.FUList2]
490 children=opList0 opList1 opList2
493 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
495 [system.cpu2.fuPool.FUList2.opList0]
502 [system.cpu2.fuPool.FUList2.opList1]
509 [system.cpu2.fuPool.FUList2.opList2]
516 [system.cpu2.fuPool.FUList3]
518 children=opList0 opList1 opList2
521 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
523 [system.cpu2.fuPool.FUList3.opList0]
530 [system.cpu2.fuPool.FUList3.opList1]
537 [system.cpu2.fuPool.FUList3.opList2]
544 [system.cpu2.fuPool.FUList4]
549 opList=system.cpu2.fuPool.FUList4.opList
551 [system.cpu2.fuPool.FUList4.opList]
558 [system.cpu2.fuPool.FUList5]
560 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
563 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
565 [system.cpu2.fuPool.FUList5.opList00]
572 [system.cpu2.fuPool.FUList5.opList01]
579 [system.cpu2.fuPool.FUList5.opList02]
586 [system.cpu2.fuPool.FUList5.opList03]
593 [system.cpu2.fuPool.FUList5.opList04]
600 [system.cpu2.fuPool.FUList5.opList05]
607 [system.cpu2.fuPool.FUList5.opList06]
614 [system.cpu2.fuPool.FUList5.opList07]
621 [system.cpu2.fuPool.FUList5.opList08]
628 [system.cpu2.fuPool.FUList5.opList09]
635 [system.cpu2.fuPool.FUList5.opList10]
642 [system.cpu2.fuPool.FUList5.opList11]
649 [system.cpu2.fuPool.FUList5.opList12]
656 [system.cpu2.fuPool.FUList5.opList13]
663 [system.cpu2.fuPool.FUList5.opList14]
670 [system.cpu2.fuPool.FUList5.opList15]
677 [system.cpu2.fuPool.FUList5.opList16]
681 opClass=SimdFloatMisc
684 [system.cpu2.fuPool.FUList5.opList17]
688 opClass=SimdFloatMult
691 [system.cpu2.fuPool.FUList5.opList18]
695 opClass=SimdFloatMultAcc
698 [system.cpu2.fuPool.FUList5.opList19]
702 opClass=SimdFloatSqrt
705 [system.cpu2.fuPool.FUList6]
710 opList=system.cpu2.fuPool.FUList6.opList
712 [system.cpu2.fuPool.FUList6.opList]
719 [system.cpu2.fuPool.FUList7]
721 children=opList0 opList1
724 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
726 [system.cpu2.fuPool.FUList7.opList0]
733 [system.cpu2.fuPool.FUList7.opList1]
740 [system.cpu2.fuPool.FUList8]
745 opList=system.cpu2.fuPool.FUList8.opList
747 [system.cpu2.fuPool.FUList8.opList]
777 walker=system.cpu2.itb.walker
779 [system.cpu2.itb.walker]
781 clk_domain=system.cpu_clk_domain
783 num_squash_per_cycle=2
790 [system.cpu_clk_domain]
794 voltage_domain=system.voltage_domain
803 clk_domain=system.clk_domain
806 use_default_range=false
808 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
809 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
814 addr_ranges=0:134217727
816 clk_domain=system.clk_domain
823 prefetch_on_access=false
826 sequential_access=false
829 tags=system.iocache.tags
833 cpu_side=system.iobus.master[25]
834 mem_side=system.membus.slave[2]
836 [system.iocache.tags]
840 clk_domain=system.clk_domain
843 sequential_access=false
849 addr_ranges=0:18446744073709551615
851 clk_domain=system.cpu_clk_domain
858 prefetch_on_access=false
861 sequential_access=false
868 cpu_side=system.toL2Bus.master[0]
869 mem_side=system.membus.slave[1]
875 clk_domain=system.cpu_clk_domain
878 sequential_access=false
883 children=badaddr_responder
884 clk_domain=system.clk_domain
888 use_default_range=false
890 default=system.membus.badaddr_responder.pio
891 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
892 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
894 [system.membus.badaddr_responder]
896 clk_domain=system.clk_domain
904 ret_data32=4294967295
905 ret_data64=18446744073709551615
910 pio=system.membus.default
915 addr_mapping=RaBaChCo
919 clk_domain=system.clk_domain
920 conf_table_reported=true
922 device_rowbuffer_size=1024
926 mem_sched_policy=frfcfs
932 static_backend_latency=10000
933 static_frontend_latency=10000
945 write_high_thresh_perc=70
946 write_low_thresh_perc=0
947 port=system.membus.master[6]
951 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
953 intrctrl=system.intrctrl
954 max_mem_size=268435456
959 [system.realview.a9scu]
961 clk_domain=system.clk_domain
966 pio=system.membus.master[4]
968 [system.realview.aaci_fake]
971 clk_domain=system.clk_domain
977 pio=system.iobus.master[21]
979 [system.realview.cf_ctrl]
1017 MSICAPMsgUpperAddr=0
1018 MSICAPNextCapability=0
1022 MSIXCAPNextCapability=0
1032 PMCAPNextCapability=0
1037 PXCAPDevCapabilities=0
1044 PXCAPNextCapability=0
1052 clk_domain=system.clk_domain
1053 config_latency=20000
1062 platform=system.realview
1064 config=system.iobus.master[8]
1065 dma=system.iobus.slave[2]
1066 pio=system.iobus.master[7]
1068 [system.realview.clcd]
1071 clk_domain=system.clk_domain
1074 gic=system.realview.gic
1080 vnc=system.vncserver
1081 dma=system.iobus.slave[1]
1082 pio=system.iobus.master[4]
1084 [system.realview.dmac_fake]
1087 clk_domain=system.clk_domain
1093 pio=system.iobus.master[9]
1095 [system.realview.flash_fake]
1097 clk_domain=system.clk_domain
1105 ret_data32=4294967295
1106 ret_data64=18446744073709551615
1111 pio=system.iobus.master[24]
1113 [system.realview.gic]
1115 clk_domain=system.clk_domain
1119 dist_pio_delay=10000
1124 platform=system.realview
1126 pio=system.membus.master[2]
1128 [system.realview.gpio0_fake]
1131 clk_domain=system.clk_domain
1137 pio=system.iobus.master[16]
1139 [system.realview.gpio1_fake]
1142 clk_domain=system.clk_domain
1148 pio=system.iobus.master[17]
1150 [system.realview.gpio2_fake]
1153 clk_domain=system.clk_domain
1159 pio=system.iobus.master[18]
1161 [system.realview.kmi0]
1164 clk_domain=system.clk_domain
1166 gic=system.realview.gic
1173 vnc=system.vncserver
1174 pio=system.iobus.master[5]
1176 [system.realview.kmi1]
1179 clk_domain=system.clk_domain
1181 gic=system.realview.gic
1188 vnc=system.vncserver
1189 pio=system.iobus.master[6]
1191 [system.realview.l2x0_fake]
1193 clk_domain=system.clk_domain
1201 ret_data32=4294967295
1202 ret_data64=18446744073709551615
1207 pio=system.membus.master[3]
1209 [system.realview.local_cpu_timer]
1211 clk_domain=system.clk_domain
1213 gic=system.realview.gic
1219 pio=system.membus.master[5]
1221 [system.realview.mmc_fake]
1224 clk_domain=system.clk_domain
1230 pio=system.iobus.master[22]
1232 [system.realview.nvmem]
1235 clk_domain=system.clk_domain
1236 conf_table_reported=false
1242 range=2147483648:2214592511
1243 port=system.membus.master[1]
1245 [system.realview.realview_io]
1247 clk_domain=system.clk_domain
1255 pio=system.iobus.master[1]
1257 [system.realview.rtc]
1260 clk_domain=system.clk_domain
1262 gic=system.realview.gic
1268 time=Thu Jan 1 00:00:00 2009
1269 pio=system.iobus.master[23]
1271 [system.realview.sci_fake]
1274 clk_domain=system.clk_domain
1280 pio=system.iobus.master[20]
1282 [system.realview.smc_fake]
1285 clk_domain=system.clk_domain
1291 pio=system.iobus.master[13]
1293 [system.realview.sp810_fake]
1296 clk_domain=system.clk_domain
1302 pio=system.iobus.master[14]
1304 [system.realview.ssp_fake]
1307 clk_domain=system.clk_domain
1313 pio=system.iobus.master[19]
1315 [system.realview.timer0]
1318 clk_domain=system.clk_domain
1322 gic=system.realview.gic
1328 pio=system.iobus.master[2]
1330 [system.realview.timer1]
1333 clk_domain=system.clk_domain
1337 gic=system.realview.gic
1343 pio=system.iobus.master[3]
1345 [system.realview.uart]
1347 clk_domain=system.clk_domain
1350 gic=system.realview.gic
1355 platform=system.realview
1357 terminal=system.terminal
1358 pio=system.iobus.master[0]
1360 [system.realview.uart1_fake]
1363 clk_domain=system.clk_domain
1369 pio=system.iobus.master[10]
1371 [system.realview.uart2_fake]
1374 clk_domain=system.clk_domain
1380 pio=system.iobus.master[11]
1382 [system.realview.uart3_fake]
1385 clk_domain=system.clk_domain
1391 pio=system.iobus.master[12]
1393 [system.realview.watchdog_fake]
1396 clk_domain=system.clk_domain
1402 pio=system.iobus.master[15]
1407 intr_control=system.intrctrl
1414 clk_domain=system.cpu_clk_domain
1418 use_default_range=false
1420 master=system.l2c.cpu_side
1421 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
1430 [system.voltage_domain]