2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.817969 # Number of seconds simulated
4 sim_ticks 2817968959500 # Number of ticks simulated
5 final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 310224 # Simulator instruction rate (inst/s)
8 host_op_rate 376688 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 6925358539 # Simulator tick rate (ticks/s)
10 host_mem_usage 560716 # Number of bytes of host memory used
11 host_seconds 406.91 # Real time elapsed on the host
12 sim_insts 126231917 # Number of instructions simulated
13 sim_ops 153276568 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory
26 system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory
27 system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory
28 system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory
31 system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory
32 system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory
33 system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
34 system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
35 system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
36 system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory
37 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory
46 system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory
47 system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory
48 system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory
49 system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory
50 system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
51 system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
52 system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
53 system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory
54 system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu0.data 1556605 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_read::cpu2.inst 183167 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s)
65 system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s)
66 system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s)
67 system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s)
68 system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s)
69 system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s)
70 system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s)
71 system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s)
72 system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
73 system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
74 system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s)
75 system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s)
84 system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s)
85 system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s)
86 system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s)
87 system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s)
88 system.physmem.readReqs 92768 # Number of read requests accepted
89 system.physmem.writeReqs 67796 # Number of write requests accepted
90 system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue
91 system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue
92 system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM
93 system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue
94 system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM
95 system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side
96 system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side
97 system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue
98 system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
99 system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write
100 system.physmem.perBankRdBursts::0 6044 # Per bank write bursts
101 system.physmem.perBankRdBursts::1 5813 # Per bank write bursts
102 system.physmem.perBankRdBursts::2 5577 # Per bank write bursts
103 system.physmem.perBankRdBursts::3 6085 # Per bank write bursts
104 system.physmem.perBankRdBursts::4 5556 # Per bank write bursts
105 system.physmem.perBankRdBursts::5 5466 # Per bank write bursts
106 system.physmem.perBankRdBursts::6 6173 # Per bank write bursts
107 system.physmem.perBankRdBursts::7 6793 # Per bank write bursts
108 system.physmem.perBankRdBursts::8 6458 # Per bank write bursts
109 system.physmem.perBankRdBursts::9 6393 # Per bank write bursts
110 system.physmem.perBankRdBursts::10 5737 # Per bank write bursts
111 system.physmem.perBankRdBursts::11 5119 # Per bank write bursts
112 system.physmem.perBankRdBursts::12 5308 # Per bank write bursts
113 system.physmem.perBankRdBursts::13 5463 # Per bank write bursts
114 system.physmem.perBankRdBursts::14 5329 # Per bank write bursts
115 system.physmem.perBankRdBursts::15 5386 # Per bank write bursts
116 system.physmem.perBankWrBursts::0 4258 # Per bank write bursts
117 system.physmem.perBankWrBursts::1 3939 # Per bank write bursts
118 system.physmem.perBankWrBursts::2 4228 # Per bank write bursts
119 system.physmem.perBankWrBursts::3 4685 # Per bank write bursts
120 system.physmem.perBankWrBursts::4 4137 # Per bank write bursts
121 system.physmem.perBankWrBursts::5 4140 # Per bank write bursts
122 system.physmem.perBankWrBursts::6 4393 # Per bank write bursts
123 system.physmem.perBankWrBursts::7 4905 # Per bank write bursts
124 system.physmem.perBankWrBursts::8 4554 # Per bank write bursts
125 system.physmem.perBankWrBursts::9 4640 # Per bank write bursts
126 system.physmem.perBankWrBursts::10 4209 # Per bank write bursts
127 system.physmem.perBankWrBursts::11 3550 # Per bank write bursts
128 system.physmem.perBankWrBursts::12 4025 # Per bank write bursts
129 system.physmem.perBankWrBursts::13 4273 # Per bank write bursts
130 system.physmem.perBankWrBursts::14 3934 # Per bank write bursts
131 system.physmem.perBankWrBursts::15 3898 # Per bank write bursts
132 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
133 system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
134 system.physmem.totGap 2816402816000 # Total gap between requests
135 system.physmem.readPktSize::0 0 # Read request sizes (log2)
136 system.physmem.readPktSize::1 0 # Read request sizes (log2)
137 system.physmem.readPktSize::2 1 # Read request sizes (log2)
138 system.physmem.readPktSize::3 0 # Read request sizes (log2)
139 system.physmem.readPktSize::4 0 # Read request sizes (log2)
140 system.physmem.readPktSize::5 0 # Read request sizes (log2)
141 system.physmem.readPktSize::6 92767 # Read request sizes (log2)
142 system.physmem.writePktSize::0 0 # Write request sizes (log2)
143 system.physmem.writePktSize::1 0 # Write request sizes (log2)
144 system.physmem.writePktSize::2 2 # Write request sizes (log2)
145 system.physmem.writePktSize::3 0 # Write request sizes (log2)
146 system.physmem.writePktSize::4 0 # Write request sizes (log2)
147 system.physmem.writePktSize::5 0 # Write request sizes (log2)
148 system.physmem.writePktSize::6 67794 # Write request sizes (log2)
149 system.physmem.rdQLenPdf::0 61106 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::1 28126 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::2 2948 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::3 515 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
176 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
177 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
178 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
179 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
180 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
181 system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::11 49 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::19 3367 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::20 3811 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::21 3969 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::22 4287 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::23 4633 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
240 system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see
241 system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
242 system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
243 system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
244 system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
245 system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation
259 system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes
261 system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes
262 system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes
263 system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
264 system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes
265 system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads
299 system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads
300 system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads
301 system.physmem.totQLat 1185317250 # Total ticks spent queuing
302 system.physmem.totMemAccLat 2923442250 # Total ticks spent from burst creation until serviced by the DRAM
303 system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers
304 system.physmem.avgQLat 12786.59 # Average queueing delay per DRAM burst
305 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
306 system.physmem.avgMemAccLat 31536.59 # Average memory access latency per DRAM burst
307 system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
308 system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
309 system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
310 system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
311 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
312 system.physmem.busUtil 0.03 # Data bus utilization in percentage
313 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
314 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
315 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
316 system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing
317 system.physmem.readRowHits 76736 # Number of row buffer hits during reads
318 system.physmem.writeRowHits 50876 # Number of row buffer hits during writes
319 system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads
320 system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes
321 system.physmem.avgGap 17540686.68 # Average gap between requests
322 system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
323 system.physmem.memoryStateTime::IDLE 2704844342250 # Time in different power states
324 system.physmem.memoryStateTime::REF 94098160000 # Time in different power states
325 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
326 system.physmem.memoryStateTime::ACT 19026363250 # Time in different power states
327 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
328 system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ)
329 system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ)
330 system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ)
331 system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ)
332 system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ)
333 system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ)
334 system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ)
335 system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ)
336 system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ)
337 system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ)
338 system.physmem.actBackEnergy::0 70810444215 # Energy for active background per rank (pJ)
339 system.physmem.actBackEnergy::1 69981019830 # Energy for active background per rank (pJ)
340 system.physmem.preBackEnergy::0 1628666804250 # Energy for precharge background per rank (pJ)
341 system.physmem.preBackEnergy::1 1629394369500 # Energy for precharge background per rank (pJ)
342 system.physmem.totalEnergy::0 1884329287755 # Total energy per rank (pJ)
343 system.physmem.totalEnergy::1 1884181443675 # Total energy per rank (pJ)
344 system.physmem.averagePower::0 668.683537 # Core power per rank (mW)
345 system.physmem.averagePower::1 668.631072 # Core power per rank (mW)
346 system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
347 system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
348 system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
349 system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
350 system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
351 system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
352 system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
353 system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
354 system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
355 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
356 system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
357 system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
358 system.membus.trans_dist::ReadReq 74237 # Transaction distribution
359 system.membus.trans_dist::ReadResp 74236 # Transaction distribution
360 system.membus.trans_dist::WriteReq 27571 # Transaction distribution
361 system.membus.trans_dist::WriteResp 27571 # Transaction distribution
362 system.membus.trans_dist::Writeback 92896 # Transaction distribution
363 system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
364 system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
365 system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution
366 system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
367 system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution
368 system.membus.trans_dist::ReadExReq 137042 # Transaction distribution
369 system.membus.trans_dist::ReadExResp 137042 # Transaction distribution
370 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
371 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
372 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
373 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes)
374 system.membus.pkt_count_system.l2c.mem_side::total 579193 # Packet count per connected master and slave (bytes)
375 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
376 system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
377 system.membus.pkt_count::total 652020 # Packet count per connected master and slave (bytes)
378 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
379 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
380 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
381 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes)
382 system.membus.pkt_size_system.l2c.mem_side::total 17102703 # Cumulative packet size per connected master and slave (bytes)
383 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
384 system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
385 system.membus.pkt_size::total 19429167 # Cumulative packet size per connected master and slave (bytes)
386 system.membus.snoops 125 # Total snoops (count)
387 system.membus.snoop_fanout::samples 304844 # Request fanout histogram
388 system.membus.snoop_fanout::mean 1 # Request fanout histogram
389 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
390 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
391 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
392 system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram
393 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
394 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
395 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
396 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
397 system.membus.snoop_fanout::total 304844 # Request fanout histogram
398 system.membus.reqLayer0.occupancy 40698500 # Layer occupancy (ticks)
399 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
400 system.membus.reqLayer2.occupancy 463500 # Layer occupancy (ticks)
401 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
402 system.membus.reqLayer5.occupancy 735391250 # Layer occupancy (ticks)
403 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
404 system.membus.respLayer2.occupancy 906935534 # Layer occupancy (ticks)
405 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
406 system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks)
407 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
408 system.cpu_clk_domain.clock 500 # Clock period in ticks
409 system.l2c.tags.replacements 100821 # number of replacements
410 system.l2c.tags.tagsinuse 65118.790978 # Cycle average of tags in use
411 system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks.
412 system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks.
413 system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks.
414 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415 system.l2c.tags.occ_blocks::writebacks 49797.187016 # Average occupied blocks per requestor
416 system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor
417 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
418 system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor
419 system.l2c.tags.occ_blocks::cpu0.data 2854.503749 # Average occupied blocks per requestor
420 system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor
421 system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor
422 system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor
423 system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966166 # Average occupied blocks per requestor
424 system.l2c.tags.occ_blocks::cpu2.inst 3505.210474 # Average occupied blocks per requestor
425 system.l2c.tags.occ_blocks::cpu2.data 1537.513263 # Average occupied blocks per requestor
426 system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy
427 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
428 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
429 system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy
430 system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy
431 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
432 system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy
433 system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy
434 system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy
435 system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy
436 system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy
437 system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy
438 system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
439 system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id
440 system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
441 system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
442 system.l2c.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
443 system.l2c.tags.age_task_id_blocks_1024::2 3115 # Occupied blocks per task id
444 system.l2c.tags.age_task_id_blocks_1024::3 8083 # Occupied blocks per task id
445 system.l2c.tags.age_task_id_blocks_1024::4 53656 # Occupied blocks per task id
446 system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id
447 system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id
448 system.l2c.tags.tag_accesses 27447983 # Number of tag accesses
449 system.l2c.tags.data_accesses 27447983 # Number of data accesses
450 system.l2c.ReadReq_hits::cpu0.dtb.walker 4963 # number of ReadReq hits
451 system.l2c.ReadReq_hits::cpu0.itb.walker 2545 # number of ReadReq hits
452 system.l2c.ReadReq_hits::cpu0.inst 856871 # number of ReadReq hits
453 system.l2c.ReadReq_hits::cpu0.data 242835 # number of ReadReq hits
454 system.l2c.ReadReq_hits::cpu1.dtb.walker 1453 # number of ReadReq hits
455 system.l2c.ReadReq_hits::cpu1.itb.walker 744 # number of ReadReq hits
456 system.l2c.ReadReq_hits::cpu1.inst 248099 # number of ReadReq hits
457 system.l2c.ReadReq_hits::cpu1.data 77823 # number of ReadReq hits
458 system.l2c.ReadReq_hits::cpu2.dtb.walker 27437 # number of ReadReq hits
459 system.l2c.ReadReq_hits::cpu2.itb.walker 6484 # number of ReadReq hits
460 system.l2c.ReadReq_hits::cpu2.inst 674506 # number of ReadReq hits
461 system.l2c.ReadReq_hits::cpu2.data 203103 # number of ReadReq hits
462 system.l2c.ReadReq_hits::total 2346863 # number of ReadReq hits
463 system.l2c.Writeback_hits::writebacks 692569 # number of Writeback hits
464 system.l2c.Writeback_hits::total 692569 # number of Writeback hits
465 system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits
466 system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
467 system.l2c.UpgradeReq_hits::cpu2.data 40 # number of UpgradeReq hits
468 system.l2c.UpgradeReq_hits::total 54 # number of UpgradeReq hits
469 system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits
470 system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
471 system.l2c.ReadExReq_hits::cpu0.data 81755 # number of ReadExReq hits
472 system.l2c.ReadExReq_hits::cpu1.data 19470 # number of ReadExReq hits
473 system.l2c.ReadExReq_hits::cpu2.data 56351 # number of ReadExReq hits
474 system.l2c.ReadExReq_hits::total 157576 # number of ReadExReq hits
475 system.l2c.demand_hits::cpu0.dtb.walker 4963 # number of demand (read+write) hits
476 system.l2c.demand_hits::cpu0.itb.walker 2545 # number of demand (read+write) hits
477 system.l2c.demand_hits::cpu0.inst 856871 # number of demand (read+write) hits
478 system.l2c.demand_hits::cpu0.data 324590 # number of demand (read+write) hits
479 system.l2c.demand_hits::cpu1.dtb.walker 1453 # number of demand (read+write) hits
480 system.l2c.demand_hits::cpu1.itb.walker 744 # number of demand (read+write) hits
481 system.l2c.demand_hits::cpu1.inst 248099 # number of demand (read+write) hits
482 system.l2c.demand_hits::cpu1.data 97293 # number of demand (read+write) hits
483 system.l2c.demand_hits::cpu2.dtb.walker 27437 # number of demand (read+write) hits
484 system.l2c.demand_hits::cpu2.itb.walker 6484 # number of demand (read+write) hits
485 system.l2c.demand_hits::cpu2.inst 674506 # number of demand (read+write) hits
486 system.l2c.demand_hits::cpu2.data 259454 # number of demand (read+write) hits
487 system.l2c.demand_hits::total 2504439 # number of demand (read+write) hits
488 system.l2c.overall_hits::cpu0.dtb.walker 4963 # number of overall hits
489 system.l2c.overall_hits::cpu0.itb.walker 2545 # number of overall hits
490 system.l2c.overall_hits::cpu0.inst 856871 # number of overall hits
491 system.l2c.overall_hits::cpu0.data 324590 # number of overall hits
492 system.l2c.overall_hits::cpu1.dtb.walker 1453 # number of overall hits
493 system.l2c.overall_hits::cpu1.itb.walker 744 # number of overall hits
494 system.l2c.overall_hits::cpu1.inst 248099 # number of overall hits
495 system.l2c.overall_hits::cpu1.data 97293 # number of overall hits
496 system.l2c.overall_hits::cpu2.dtb.walker 27437 # number of overall hits
497 system.l2c.overall_hits::cpu2.itb.walker 6484 # number of overall hits
498 system.l2c.overall_hits::cpu2.inst 674506 # number of overall hits
499 system.l2c.overall_hits::cpu2.data 259454 # number of overall hits
500 system.l2c.overall_hits::total 2504439 # number of overall hits
501 system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
502 system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
503 system.l2c.ReadReq_misses::cpu0.inst 9638 # number of ReadReq misses
504 system.l2c.ReadReq_misses::cpu0.data 6914 # number of ReadReq misses
505 system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
506 system.l2c.ReadReq_misses::cpu1.inst 2046 # number of ReadReq misses
507 system.l2c.ReadReq_misses::cpu1.data 2575 # number of ReadReq misses
508 system.l2c.ReadReq_misses::cpu2.dtb.walker 95 # number of ReadReq misses
509 system.l2c.ReadReq_misses::cpu2.inst 8072 # number of ReadReq misses
510 system.l2c.ReadReq_misses::cpu2.data 4575 # number of ReadReq misses
511 system.l2c.ReadReq_misses::total 33921 # number of ReadReq misses
512 system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses
513 system.l2c.UpgradeReq_misses::cpu1.data 366 # number of UpgradeReq misses
514 system.l2c.UpgradeReq_misses::cpu2.data 1066 # number of UpgradeReq misses
515 system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses
516 system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
517 system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
518 system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
519 system.l2c.ReadExReq_misses::cpu0.data 62387 # number of ReadExReq misses
520 system.l2c.ReadExReq_misses::cpu1.data 14112 # number of ReadExReq misses
521 system.l2c.ReadExReq_misses::cpu2.data 62374 # number of ReadExReq misses
522 system.l2c.ReadExReq_misses::total 138873 # number of ReadExReq misses
523 system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
524 system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
525 system.l2c.demand_misses::cpu0.inst 9638 # number of demand (read+write) misses
526 system.l2c.demand_misses::cpu0.data 69301 # number of demand (read+write) misses
527 system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
528 system.l2c.demand_misses::cpu1.inst 2046 # number of demand (read+write) misses
529 system.l2c.demand_misses::cpu1.data 16687 # number of demand (read+write) misses
530 system.l2c.demand_misses::cpu2.dtb.walker 95 # number of demand (read+write) misses
531 system.l2c.demand_misses::cpu2.inst 8072 # number of demand (read+write) misses
532 system.l2c.demand_misses::cpu2.data 66949 # number of demand (read+write) misses
533 system.l2c.demand_misses::total 172794 # number of demand (read+write) misses
534 system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
535 system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
536 system.l2c.overall_misses::cpu0.inst 9638 # number of overall misses
537 system.l2c.overall_misses::cpu0.data 69301 # number of overall misses
538 system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
539 system.l2c.overall_misses::cpu1.inst 2046 # number of overall misses
540 system.l2c.overall_misses::cpu1.data 16687 # number of overall misses
541 system.l2c.overall_misses::cpu2.dtb.walker 95 # number of overall misses
542 system.l2c.overall_misses::cpu2.inst 8072 # number of overall misses
543 system.l2c.overall_misses::cpu2.data 66949 # number of overall misses
544 system.l2c.overall_misses::total 172794 # number of overall misses
545 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles
546 system.l2c.ReadReq_miss_latency::cpu1.inst 148548750 # number of ReadReq miss cycles
547 system.l2c.ReadReq_miss_latency::cpu1.data 192290250 # number of ReadReq miss cycles
548 system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7339250 # number of ReadReq miss cycles
549 system.l2c.ReadReq_miss_latency::cpu2.inst 615969000 # number of ReadReq miss cycles
550 system.l2c.ReadReq_miss_latency::cpu2.data 366986496 # number of ReadReq miss cycles
551 system.l2c.ReadReq_miss_latency::total 1331208246 # number of ReadReq miss cycles
552 system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles
553 system.l2c.UpgradeReq_miss_latency::cpu2.data 325486 # number of UpgradeReq miss cycles
554 system.l2c.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles
555 system.l2c.ReadExReq_miss_latency::cpu1.data 994399991 # number of ReadExReq miss cycles
556 system.l2c.ReadExReq_miss_latency::cpu2.data 4662408726 # number of ReadExReq miss cycles
557 system.l2c.ReadExReq_miss_latency::total 5656808717 # number of ReadExReq miss cycles
558 system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
559 system.l2c.demand_miss_latency::cpu1.inst 148548750 # number of demand (read+write) miss cycles
560 system.l2c.demand_miss_latency::cpu1.data 1186690241 # number of demand (read+write) miss cycles
561 system.l2c.demand_miss_latency::cpu2.dtb.walker 7339250 # number of demand (read+write) miss cycles
562 system.l2c.demand_miss_latency::cpu2.inst 615969000 # number of demand (read+write) miss cycles
563 system.l2c.demand_miss_latency::cpu2.data 5029395222 # number of demand (read+write) miss cycles
564 system.l2c.demand_miss_latency::total 6988016963 # number of demand (read+write) miss cycles
565 system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
566 system.l2c.overall_miss_latency::cpu1.inst 148548750 # number of overall miss cycles
567 system.l2c.overall_miss_latency::cpu1.data 1186690241 # number of overall miss cycles
568 system.l2c.overall_miss_latency::cpu2.dtb.walker 7339250 # number of overall miss cycles
569 system.l2c.overall_miss_latency::cpu2.inst 615969000 # number of overall miss cycles
570 system.l2c.overall_miss_latency::cpu2.data 5029395222 # number of overall miss cycles
571 system.l2c.overall_miss_latency::total 6988016963 # number of overall miss cycles
572 system.l2c.ReadReq_accesses::cpu0.dtb.walker 4967 # number of ReadReq accesses(hits+misses)
573 system.l2c.ReadReq_accesses::cpu0.itb.walker 2546 # number of ReadReq accesses(hits+misses)
574 system.l2c.ReadReq_accesses::cpu0.inst 866509 # number of ReadReq accesses(hits+misses)
575 system.l2c.ReadReq_accesses::cpu0.data 249749 # number of ReadReq accesses(hits+misses)
576 system.l2c.ReadReq_accesses::cpu1.dtb.walker 1454 # number of ReadReq accesses(hits+misses)
577 system.l2c.ReadReq_accesses::cpu1.itb.walker 744 # number of ReadReq accesses(hits+misses)
578 system.l2c.ReadReq_accesses::cpu1.inst 250145 # number of ReadReq accesses(hits+misses)
579 system.l2c.ReadReq_accesses::cpu1.data 80398 # number of ReadReq accesses(hits+misses)
580 system.l2c.ReadReq_accesses::cpu2.dtb.walker 27532 # number of ReadReq accesses(hits+misses)
581 system.l2c.ReadReq_accesses::cpu2.itb.walker 6484 # number of ReadReq accesses(hits+misses)
582 system.l2c.ReadReq_accesses::cpu2.inst 682578 # number of ReadReq accesses(hits+misses)
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814 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency
815 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency
816 system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency
817 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
818 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency
819 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency
820 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
821 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
822 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.903132 # average ReadExReq mshr miss latency
823 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency
824 system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.780757 # average ReadExReq mshr miss latency
825 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
826 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
827 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency
828 system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
829 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
830 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
831 system.l2c.demand_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency
832 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
833 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
834 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency
835 system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
836 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
837 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
838 system.l2c.overall_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency
839 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
840 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
841 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
842 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
843 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
844 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
845 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
846 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
847 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
848 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
849 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
850 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
851 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
852 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
853 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
854 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
855 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
856 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
857 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
858 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
859 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
860 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
861 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
862 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
863 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
864 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
865 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
866 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
867 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
868 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
869 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
870 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
871 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
872 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
873 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
874 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
875 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
876 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
877 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
878 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
879 system.realview.ethernet.droppedPackets 0 # number of packets dropped
880 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
881 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
882 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
883 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
884 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
885 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
886 system.toL2Bus.trans_dist::ReadReq 2443721 # Transaction distribution
887 system.toL2Bus.trans_dist::ReadResp 2443718 # Transaction distribution
888 system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
889 system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
890 system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution
891 system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution
892 system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution
893 system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
894 system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
895 system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution
896 system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution
897 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616609 # Packet count per connected master and slave (bytes)
898 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes)
899 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes)
900 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes)
901 system.toL2Bus.pkt_count::total 6218459 # Packet count per connected master and slave (bytes)
902 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187260 # Cumulative packet size per connected master and slave (bytes)
903 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes)
904 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes)
905 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes)
906 system.toL2Bus.pkt_size::total 213301515 # Cumulative packet size per connected master and slave (bytes)
907 system.toL2Bus.snoops 51755 # Total snoops (count)
908 system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram
909 system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram
910 system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram
911 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
912 system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
913 system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
914 system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
915 system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
916 system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
917 system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram
918 system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram
919 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
920 system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
921 system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
922 system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram
923 system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks)
924 system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
925 system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks)
926 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
927 system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks)
928 system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
929 system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks)
930 system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
931 system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks)
932 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
933 system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks)
934 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
935 system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
936 system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
937 system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
938 system.iobus.trans_dist::WriteResp 45563 # Transaction distribution
939 system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution
940 system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution
941 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
942 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
943 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
944 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
945 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
946 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
947 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
948 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
949 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
950 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
951 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
952 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
953 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
954 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
955 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
956 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
957 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
958 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
959 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
960 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
961 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
962 system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
963 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
964 system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
965 system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
966 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
967 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
968 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
969 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
970 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
971 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
972 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
973 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
974 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
975 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
976 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
977 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
978 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
979 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
980 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
981 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
982 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
983 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
984 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
985 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
986 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
987 system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
988 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
989 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
990 system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
991 system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
992 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
993 system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
994 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
995 system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
996 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
997 system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
998 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
999 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1000 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1001 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1002 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1003 system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1004 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1005 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1006 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1007 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1008 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1009 system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1010 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1011 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
1012 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1013 system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks)
1014 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1015 system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
1016 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1017 system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
1018 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1019 system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
1020 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1021 system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks)
1022 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1023 system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks)
1024 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1025 system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks)
1026 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1027 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1028 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1029 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1030 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1031 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1032 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1033 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1034 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1035 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1036 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1037 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1038 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1039 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1040 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1041 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1042 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1043 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1044 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1045 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1046 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1047 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1048 system.cpu0.dtb.inst_hits 0 # ITB inst hits
1049 system.cpu0.dtb.inst_misses 0 # ITB inst misses
1050 system.cpu0.dtb.read_hits 14476225 # DTB read hits
1051 system.cpu0.dtb.read_misses 4878 # DTB read misses
1052 system.cpu0.dtb.write_hits 11074159 # DTB write hits
1053 system.cpu0.dtb.write_misses 931 # DTB write misses
1054 system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed
1055 system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
1056 system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1057 system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1058 system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB
1059 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1060 system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch
1061 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1062 system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions
1063 system.cpu0.dtb.read_accesses 14481103 # DTB read accesses
1064 system.cpu0.dtb.write_accesses 11075090 # DTB write accesses
1065 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1066 system.cpu0.dtb.hits 25550384 # DTB hits
1067 system.cpu0.dtb.misses 5809 # DTB misses
1068 system.cpu0.dtb.accesses 25556193 # DTB accesses
1069 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1070 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1071 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1072 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1073 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1074 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1075 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1076 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1077 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1078 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1079 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1080 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1081 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1082 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1083 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1084 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1085 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1086 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1087 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1088 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1089 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1090 system.cpu0.itb.inst_hits 67954631 # ITB inst hits
1091 system.cpu0.itb.inst_misses 2810 # ITB inst misses
1092 system.cpu0.itb.read_hits 0 # DTB read hits
1093 system.cpu0.itb.read_misses 0 # DTB read misses
1094 system.cpu0.itb.write_hits 0 # DTB write hits
1095 system.cpu0.itb.write_misses 0 # DTB write misses
1096 system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed
1097 system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
1098 system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1099 system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1100 system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB
1101 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1102 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1103 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1104 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1105 system.cpu0.itb.read_accesses 0 # DTB read accesses
1106 system.cpu0.itb.write_accesses 0 # DTB write accesses
1107 system.cpu0.itb.inst_accesses 67957441 # ITB inst accesses
1108 system.cpu0.itb.hits 67954631 # DTB hits
1109 system.cpu0.itb.misses 2810 # DTB misses
1110 system.cpu0.itb.accesses 67957441 # DTB accesses
1111 system.cpu0.numCycles 82556870 # number of cpu cycles simulated
1112 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1113 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1114 system.cpu0.committedInsts 66160123 # Number of instructions committed
1115 system.cpu0.committedOps 80652277 # Number of ops (including micro ops) committed
1116 system.cpu0.num_int_alu_accesses 70891568 # Number of integer alu accesses
1117 system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses
1118 system.cpu0.num_func_calls 7292026 # number of times a function call or return occured
1119 system.cpu0.num_conditional_control_insts 8778447 # number of instructions that are conditional controls
1120 system.cpu0.num_int_insts 70891568 # number of integer instructions
1121 system.cpu0.num_fp_insts 5582 # number of float instructions
1122 system.cpu0.num_int_register_reads 131506227 # number of times the integer registers were read
1123 system.cpu0.num_int_register_writes 49334420 # number of times the integer registers were written
1124 system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read
1125 system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
1126 system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read
1127 system.cpu0.num_cc_register_writes 29383073 # number of times the CC registers were written
1128 system.cpu0.num_mem_refs 26220754 # number of memory refs
1129 system.cpu0.num_load_insts 14652166 # Number of load instructions
1130 system.cpu0.num_store_insts 11568588 # Number of store instructions
1131 system.cpu0.num_idle_cycles 77950731.061702 # Number of idle cycles
1132 system.cpu0.num_busy_cycles 4606138.938298 # Number of busy cycles
1133 system.cpu0.not_idle_fraction 0.055794 # Percentage of non-idle cycles
1134 system.cpu0.idle_fraction 0.944206 # Percentage of idle cycles
1135 system.cpu0.Branches 16465385 # Number of branches fetched
1136 system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction
1137 system.cpu0.op_class::IntAlu 55784741 67.97% 67.97% # Class of executed instruction
1138 system.cpu0.op_class::IntMult 58719 0.07% 68.05% # Class of executed instruction
1139 system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction
1140 system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction
1141 system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
1142 system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
1143 system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
1144 system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
1145 system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
1146 system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
1147 system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
1148 system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
1149 system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
1150 system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
1151 system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
1152 system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
1153 system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
1154 system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
1155 system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
1156 system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
1157 system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
1158 system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
1159 system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
1160 system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
1161 system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
1162 system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Class of executed instruction
1163 system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
1164 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
1165 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
1166 system.cpu0.op_class::MemRead 14652166 17.85% 85.90% # Class of executed instruction
1167 system.cpu0.op_class::MemWrite 11568588 14.10% 100.00% # Class of executed instruction
1168 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1169 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1170 system.cpu0.op_class::total 82070947 # Class of executed instruction
1171 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1172 system.cpu0.kern.inst.quiesce 3056 # number of quiesce instructions executed
1173 system.cpu0.icache.tags.replacements 1798781 # number of replacements
1174 system.cpu0.icache.tags.tagsinuse 511.545341 # Cycle average of tags in use
1175 system.cpu0.icache.tags.total_refs 100889008 # Total number of references to valid blocks.
1176 system.cpu0.icache.tags.sampled_refs 1799292 # Sample count of references to valid blocks.
1177 system.cpu0.icache.tags.avg_refs 56.071504 # Average number of references to valid blocks.
1178 system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit.
1179 system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.678395 # Average occupied blocks per requestor
1180 system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.508688 # Average occupied blocks per requestor
1181 system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.358258 # Average occupied blocks per requestor
1182 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932966 # Average percentage of cache occupancy
1183 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.042009 # Average percentage of cache occupancy
1184 system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024137 # Average percentage of cache occupancy
1185 system.cpu0.icache.tags.occ_percent::total 0.999112 # Average percentage of cache occupancy
1186 system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1187 system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
1188 system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
1189 system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
1190 system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1191 system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses
1192 system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses
1193 system.cpu0.icache.ReadReq_hits::cpu0.inst 67090157 # number of ReadReq hits
1194 system.cpu0.icache.ReadReq_hits::cpu1.inst 21677955 # number of ReadReq hits
1195 system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits
1196 system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits
1197 system.cpu0.icache.demand_hits::cpu0.inst 67090157 # number of demand (read+write) hits
1198 system.cpu0.icache.demand_hits::cpu1.inst 21677955 # number of demand (read+write) hits
1199 system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits
1200 system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits
1201 system.cpu0.icache.overall_hits::cpu0.inst 67090157 # number of overall hits
1202 system.cpu0.icache.overall_hits::cpu1.inst 21677955 # number of overall hits
1203 system.cpu0.icache.overall_hits::cpu2.inst 12120896 # number of overall hits
1204 system.cpu0.icache.overall_hits::total 100889008 # number of overall hits
1205 system.cpu0.icache.ReadReq_misses::cpu0.inst 866515 # number of ReadReq misses
1206 system.cpu0.icache.ReadReq_misses::cpu1.inst 250147 # number of ReadReq misses
1207 system.cpu0.icache.ReadReq_misses::cpu2.inst 732935 # number of ReadReq misses
1208 system.cpu0.icache.ReadReq_misses::total 1849597 # number of ReadReq misses
1209 system.cpu0.icache.demand_misses::cpu0.inst 866515 # number of demand (read+write) misses
1210 system.cpu0.icache.demand_misses::cpu1.inst 250147 # number of demand (read+write) misses
1211 system.cpu0.icache.demand_misses::cpu2.inst 732935 # number of demand (read+write) misses
1212 system.cpu0.icache.demand_misses::total 1849597 # number of demand (read+write) misses
1213 system.cpu0.icache.overall_misses::cpu0.inst 866515 # number of overall misses
1214 system.cpu0.icache.overall_misses::cpu1.inst 250147 # number of overall misses
1215 system.cpu0.icache.overall_misses::cpu2.inst 732935 # number of overall misses
1216 system.cpu0.icache.overall_misses::total 1849597 # number of overall misses
1217 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3389079250 # number of ReadReq miss cycles
1218 system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10061046680 # number of ReadReq miss cycles
1219 system.cpu0.icache.ReadReq_miss_latency::total 13450125930 # number of ReadReq miss cycles
1220 system.cpu0.icache.demand_miss_latency::cpu1.inst 3389079250 # number of demand (read+write) miss cycles
1221 system.cpu0.icache.demand_miss_latency::cpu2.inst 10061046680 # number of demand (read+write) miss cycles
1222 system.cpu0.icache.demand_miss_latency::total 13450125930 # number of demand (read+write) miss cycles
1223 system.cpu0.icache.overall_miss_latency::cpu1.inst 3389079250 # number of overall miss cycles
1224 system.cpu0.icache.overall_miss_latency::cpu2.inst 10061046680 # number of overall miss cycles
1225 system.cpu0.icache.overall_miss_latency::total 13450125930 # number of overall miss cycles
1226 system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956672 # number of ReadReq accesses(hits+misses)
1227 system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928102 # number of ReadReq accesses(hits+misses)
1228 system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses)
1229 system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses)
1230 system.cpu0.icache.demand_accesses::cpu0.inst 67956672 # number of demand (read+write) accesses
1231 system.cpu0.icache.demand_accesses::cpu1.inst 21928102 # number of demand (read+write) accesses
1232 system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses
1233 system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses
1234 system.cpu0.icache.overall_accesses::cpu0.inst 67956672 # number of overall (read+write) accesses
1235 system.cpu0.icache.overall_accesses::cpu1.inst 21928102 # number of overall (read+write) accesses
1236 system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses
1237 system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses
1238 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses
1239 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011408 # miss rate for ReadReq accesses
1240 system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057021 # miss rate for ReadReq accesses
1241 system.cpu0.icache.ReadReq_miss_rate::total 0.018003 # miss rate for ReadReq accesses
1242 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012751 # miss rate for demand accesses
1243 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011408 # miss rate for demand accesses
1244 system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057021 # miss rate for demand accesses
1245 system.cpu0.icache.demand_miss_rate::total 0.018003 # miss rate for demand accesses
1246 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012751 # miss rate for overall accesses
1247 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011408 # miss rate for overall accesses
1248 system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057021 # miss rate for overall accesses
1249 system.cpu0.icache.overall_miss_rate::total 0.018003 # miss rate for overall accesses
1250 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.350570 # average ReadReq miss latency
1251 system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.065401 # average ReadReq miss latency
1252 system.cpu0.icache.ReadReq_avg_miss_latency::total 7271.922440 # average ReadReq miss latency
1253 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency
1254 system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency
1255 system.cpu0.icache.demand_avg_miss_latency::total 7271.922440 # average overall miss latency
1256 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency
1257 system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency
1258 system.cpu0.icache.overall_avg_miss_latency::total 7271.922440 # average overall miss latency
1259 system.cpu0.icache.blocked_cycles::no_mshrs 5408 # number of cycles access was blocked
1260 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1261 system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked
1262 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1263 system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.859238 # average number of cycles each access was blocked
1264 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1265 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1266 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1267 system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50271 # number of ReadReq MSHR hits
1268 system.cpu0.icache.ReadReq_mshr_hits::total 50271 # number of ReadReq MSHR hits
1269 system.cpu0.icache.demand_mshr_hits::cpu2.inst 50271 # number of demand (read+write) MSHR hits
1270 system.cpu0.icache.demand_mshr_hits::total 50271 # number of demand (read+write) MSHR hits
1271 system.cpu0.icache.overall_mshr_hits::cpu2.inst 50271 # number of overall MSHR hits
1272 system.cpu0.icache.overall_mshr_hits::total 50271 # number of overall MSHR hits
1273 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250147 # number of ReadReq MSHR misses
1274 system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682664 # number of ReadReq MSHR misses
1275 system.cpu0.icache.ReadReq_mshr_misses::total 932811 # number of ReadReq MSHR misses
1276 system.cpu0.icache.demand_mshr_misses::cpu1.inst 250147 # number of demand (read+write) MSHR misses
1277 system.cpu0.icache.demand_mshr_misses::cpu2.inst 682664 # number of demand (read+write) MSHR misses
1278 system.cpu0.icache.demand_mshr_misses::total 932811 # number of demand (read+write) MSHR misses
1279 system.cpu0.icache.overall_mshr_misses::cpu1.inst 250147 # number of overall MSHR misses
1280 system.cpu0.icache.overall_mshr_misses::cpu2.inst 682664 # number of overall MSHR misses
1281 system.cpu0.icache.overall_mshr_misses::total 932811 # number of overall MSHR misses
1282 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888042750 # number of ReadReq MSHR miss cycles
1283 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8209155812 # number of ReadReq MSHR miss cycles
1284 system.cpu0.icache.ReadReq_mshr_miss_latency::total 11097198562 # number of ReadReq MSHR miss cycles
1285 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888042750 # number of demand (read+write) MSHR miss cycles
1286 system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8209155812 # number of demand (read+write) MSHR miss cycles
1287 system.cpu0.icache.demand_mshr_miss_latency::total 11097198562 # number of demand (read+write) MSHR miss cycles
1288 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888042750 # number of overall MSHR miss cycles
1289 system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8209155812 # number of overall MSHR miss cycles
1290 system.cpu0.icache.overall_mshr_miss_latency::total 11097198562 # number of overall MSHR miss cycles
1291 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for ReadReq accesses
1292 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for ReadReq accesses
1293 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009079 # mshr miss rate for ReadReq accesses
1294 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for demand accesses
1295 system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for demand accesses
1296 system.cpu0.icache.demand_mshr_miss_rate::total 0.009079 # mshr miss rate for demand accesses
1297 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for overall accesses
1298 system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for overall accesses
1299 system.cpu0.icache.overall_mshr_miss_rate::total 0.009079 # mshr miss rate for overall accesses
1300 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average ReadReq mshr miss latency
1301 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average ReadReq mshr miss latency
1302 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.513401 # average ReadReq mshr miss latency
1303 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency
1304 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency
1305 system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency
1306 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency
1307 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency
1308 system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency
1309 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1310 system.cpu0.dcache.tags.replacements 833731 # number of replacements
1311 system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use
1312 system.cpu0.dcache.tags.total_refs 47004235 # Total number of references to valid blocks.
1313 system.cpu0.dcache.tags.sampled_refs 834243 # Sample count of references to valid blocks.
1314 system.cpu0.dcache.tags.avg_refs 56.343577 # Average number of references to valid blocks.
1315 system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit.
1316 system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853552 # Average occupied blocks per requestor
1317 system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.631337 # Average occupied blocks per requestor
1318 system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.511911 # Average occupied blocks per requestor
1319 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948933 # Average percentage of cache occupancy
1320 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032483 # Average percentage of cache occupancy
1321 system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018578 # Average percentage of cache occupancy
1322 system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
1323 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1324 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
1325 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
1326 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
1327 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1328 system.cpu0.dcache.tags.tag_accesses 198572858 # Number of tag accesses
1329 system.cpu0.dcache.tags.data_accesses 198572858 # Number of data accesses
1330 system.cpu0.dcache.ReadReq_hits::cpu0.data 13788624 # number of ReadReq hits
1331 system.cpu0.dcache.ReadReq_hits::cpu1.data 4405133 # number of ReadReq hits
1332 system.cpu0.dcache.ReadReq_hits::cpu2.data 8515109 # number of ReadReq hits
1333 system.cpu0.dcache.ReadReq_hits::total 26708866 # number of ReadReq hits
1334 system.cpu0.dcache.WriteReq_hits::cpu0.data 10680775 # number of WriteReq hits
1335 system.cpu0.dcache.WriteReq_hits::cpu1.data 3155078 # number of WriteReq hits
1336 system.cpu0.dcache.WriteReq_hits::cpu2.data 5164116 # number of WriteReq hits
1337 system.cpu0.dcache.WriteReq_hits::total 18999969 # number of WriteReq hits
1338 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190600 # number of SoftPFReq hits
1339 system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60611 # number of SoftPFReq hits
1340 system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130493 # number of SoftPFReq hits
1341 system.cpu0.dcache.SoftPFReq_hits::total 381704 # number of SoftPFReq hits
1342 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235254 # number of LoadLockedReq hits
1343 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80501 # number of LoadLockedReq hits
1344 system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 135396 # number of LoadLockedReq hits
1345 system.cpu0.dcache.LoadLockedReq_hits::total 451151 # number of LoadLockedReq hits
1346 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236603 # number of StoreCondReq hits
1347 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 83020 # number of StoreCondReq hits
1348 system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140074 # number of StoreCondReq hits
1349 system.cpu0.dcache.StoreCondReq_hits::total 459697 # number of StoreCondReq hits
1350 system.cpu0.dcache.demand_hits::cpu0.data 24469399 # number of demand (read+write) hits
1351 system.cpu0.dcache.demand_hits::cpu1.data 7560211 # number of demand (read+write) hits
1352 system.cpu0.dcache.demand_hits::cpu2.data 13679225 # number of demand (read+write) hits
1353 system.cpu0.dcache.demand_hits::total 45708835 # number of demand (read+write) hits
1354 system.cpu0.dcache.overall_hits::cpu0.data 24659999 # number of overall hits
1355 system.cpu0.dcache.overall_hits::cpu1.data 7620822 # number of overall hits
1356 system.cpu0.dcache.overall_hits::cpu2.data 13809718 # number of overall hits
1357 system.cpu0.dcache.overall_hits::total 46090539 # number of overall hits
1358 system.cpu0.dcache.ReadReq_misses::cpu0.data 190274 # number of ReadReq misses
1359 system.cpu0.dcache.ReadReq_misses::cpu1.data 59406 # number of ReadReq misses
1360 system.cpu0.dcache.ReadReq_misses::cpu2.data 316505 # number of ReadReq misses
1361 system.cpu0.dcache.ReadReq_misses::total 566185 # number of ReadReq misses
1362 system.cpu0.dcache.WriteReq_misses::cpu0.data 145437 # number of WriteReq misses
1363 system.cpu0.dcache.WriteReq_misses::cpu1.data 33952 # number of WriteReq misses
1364 system.cpu0.dcache.WriteReq_misses::cpu2.data 1529558 # number of WriteReq misses
1365 system.cpu0.dcache.WriteReq_misses::total 1708947 # number of WriteReq misses
1366 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 55030 # number of SoftPFReq misses
1367 system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20141 # number of SoftPFReq misses
1368 system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65518 # number of SoftPFReq misses
1369 system.cpu0.dcache.SoftPFReq_misses::total 140689 # number of SoftPFReq misses
1370 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4445 # number of LoadLockedReq misses
1371 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3284 # number of LoadLockedReq misses
1372 system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9694 # number of LoadLockedReq misses
1373 system.cpu0.dcache.LoadLockedReq_misses::total 17423 # number of LoadLockedReq misses
1374 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
1375 system.cpu0.dcache.StoreCondReq_misses::cpu2.data 13 # number of StoreCondReq misses
1376 system.cpu0.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses
1377 system.cpu0.dcache.demand_misses::cpu0.data 335711 # number of demand (read+write) misses
1378 system.cpu0.dcache.demand_misses::cpu1.data 93358 # number of demand (read+write) misses
1379 system.cpu0.dcache.demand_misses::cpu2.data 1846063 # number of demand (read+write) misses
1380 system.cpu0.dcache.demand_misses::total 2275132 # number of demand (read+write) misses
1381 system.cpu0.dcache.overall_misses::cpu0.data 390741 # number of overall misses
1382 system.cpu0.dcache.overall_misses::cpu1.data 113499 # number of overall misses
1383 system.cpu0.dcache.overall_misses::cpu2.data 1911581 # number of overall misses
1384 system.cpu0.dcache.overall_misses::total 2415821 # number of overall misses
1385 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905009250 # number of ReadReq miss cycles
1386 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5267719081 # number of ReadReq miss cycles
1387 system.cpu0.dcache.ReadReq_miss_latency::total 6172728331 # number of ReadReq miss cycles
1388 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312526367 # number of WriteReq miss cycles
1389 system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70730774620 # number of WriteReq miss cycles
1390 system.cpu0.dcache.WriteReq_miss_latency::total 72043300987 # number of WriteReq miss cycles
1391 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46439000 # number of LoadLockedReq miss cycles
1392 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132211248 # number of LoadLockedReq miss cycles
1393 system.cpu0.dcache.LoadLockedReq_miss_latency::total 178650248 # number of LoadLockedReq miss cycles
1394 system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 181001 # number of StoreCondReq miss cycles
1395 system.cpu0.dcache.StoreCondReq_miss_latency::total 181001 # number of StoreCondReq miss cycles
1396 system.cpu0.dcache.demand_miss_latency::cpu1.data 2217535617 # number of demand (read+write) miss cycles
1397 system.cpu0.dcache.demand_miss_latency::cpu2.data 75998493701 # number of demand (read+write) miss cycles
1398 system.cpu0.dcache.demand_miss_latency::total 78216029318 # number of demand (read+write) miss cycles
1399 system.cpu0.dcache.overall_miss_latency::cpu1.data 2217535617 # number of overall miss cycles
1400 system.cpu0.dcache.overall_miss_latency::cpu2.data 75998493701 # number of overall miss cycles
1401 system.cpu0.dcache.overall_miss_latency::total 78216029318 # number of overall miss cycles
1402 system.cpu0.dcache.ReadReq_accesses::cpu0.data 13978898 # number of ReadReq accesses(hits+misses)
1403 system.cpu0.dcache.ReadReq_accesses::cpu1.data 4464539 # number of ReadReq accesses(hits+misses)
1404 system.cpu0.dcache.ReadReq_accesses::cpu2.data 8831614 # number of ReadReq accesses(hits+misses)
1405 system.cpu0.dcache.ReadReq_accesses::total 27275051 # number of ReadReq accesses(hits+misses)
1406 system.cpu0.dcache.WriteReq_accesses::cpu0.data 10826212 # number of WriteReq accesses(hits+misses)
1407 system.cpu0.dcache.WriteReq_accesses::cpu1.data 3189030 # number of WriteReq accesses(hits+misses)
1408 system.cpu0.dcache.WriteReq_accesses::cpu2.data 6693674 # number of WriteReq accesses(hits+misses)
1409 system.cpu0.dcache.WriteReq_accesses::total 20708916 # number of WriteReq accesses(hits+misses)
1410 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 245630 # number of SoftPFReq accesses(hits+misses)
1411 system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 80752 # number of SoftPFReq accesses(hits+misses)
1412 system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196011 # number of SoftPFReq accesses(hits+misses)
1413 system.cpu0.dcache.SoftPFReq_accesses::total 522393 # number of SoftPFReq accesses(hits+misses)
1414 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239699 # number of LoadLockedReq accesses(hits+misses)
1415 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83785 # number of LoadLockedReq accesses(hits+misses)
1416 system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145090 # number of LoadLockedReq accesses(hits+misses)
1417 system.cpu0.dcache.LoadLockedReq_accesses::total 468574 # number of LoadLockedReq accesses(hits+misses)
1418 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236605 # number of StoreCondReq accesses(hits+misses)
1419 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 83020 # number of StoreCondReq accesses(hits+misses)
1420 system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140087 # number of StoreCondReq accesses(hits+misses)
1421 system.cpu0.dcache.StoreCondReq_accesses::total 459712 # number of StoreCondReq accesses(hits+misses)
1422 system.cpu0.dcache.demand_accesses::cpu0.data 24805110 # number of demand (read+write) accesses
1423 system.cpu0.dcache.demand_accesses::cpu1.data 7653569 # number of demand (read+write) accesses
1424 system.cpu0.dcache.demand_accesses::cpu2.data 15525288 # number of demand (read+write) accesses
1425 system.cpu0.dcache.demand_accesses::total 47983967 # number of demand (read+write) accesses
1426 system.cpu0.dcache.overall_accesses::cpu0.data 25050740 # number of overall (read+write) accesses
1427 system.cpu0.dcache.overall_accesses::cpu1.data 7734321 # number of overall (read+write) accesses
1428 system.cpu0.dcache.overall_accesses::cpu2.data 15721299 # number of overall (read+write) accesses
1429 system.cpu0.dcache.overall_accesses::total 48506360 # number of overall (read+write) accesses
1430 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013612 # miss rate for ReadReq accesses
1431 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013306 # miss rate for ReadReq accesses
1432 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035838 # miss rate for ReadReq accesses
1433 system.cpu0.dcache.ReadReq_miss_rate::total 0.020758 # miss rate for ReadReq accesses
1434 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013434 # miss rate for WriteReq accesses
1435 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010646 # miss rate for WriteReq accesses
1436 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228508 # miss rate for WriteReq accesses
1437 system.cpu0.dcache.WriteReq_miss_rate::total 0.082522 # miss rate for WriteReq accesses
1438 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224036 # miss rate for SoftPFReq accesses
1439 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249418 # miss rate for SoftPFReq accesses
1440 system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334257 # miss rate for SoftPFReq accesses
1441 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269316 # miss rate for SoftPFReq accesses
1442 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018544 # miss rate for LoadLockedReq accesses
1443 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039196 # miss rate for LoadLockedReq accesses
1444 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066814 # miss rate for LoadLockedReq accesses
1445 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037183 # miss rate for LoadLockedReq accesses
1446 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
1447 system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000093 # miss rate for StoreCondReq accesses
1448 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000033 # miss rate for StoreCondReq accesses
1449 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013534 # miss rate for demand accesses
1450 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012198 # miss rate for demand accesses
1451 system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118907 # miss rate for demand accesses
1452 system.cpu0.dcache.demand_miss_rate::total 0.047414 # miss rate for demand accesses
1453 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015598 # miss rate for overall accesses
1454 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014675 # miss rate for overall accesses
1455 system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121592 # miss rate for overall accesses
1456 system.cpu0.dcache.overall_miss_rate::total 0.049804 # miss rate for overall accesses
1457 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15234.307141 # average ReadReq miss latency
1458 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16643.399254 # average ReadReq miss latency
1459 system.cpu0.dcache.ReadReq_avg_miss_latency::total 10902.316965 # average ReadReq miss latency
1460 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.293090 # average WriteReq miss latency
1461 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46242.623438 # average WriteReq miss latency
1462 system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.544929 # average WriteReq miss latency
1463 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.986602 # average LoadLockedReq miss latency
1464 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13638.461729 # average LoadLockedReq miss latency
1465 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10253.701888 # average LoadLockedReq miss latency
1466 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency
1467 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency
1468 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.032595 # average overall miss latency
1469 system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41167.876557 # average overall miss latency
1470 system.cpu0.dcache.demand_avg_miss_latency::total 34378.677509 # average overall miss latency
1471 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.930880 # average overall miss latency
1472 system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39756.878574 # average overall miss latency
1473 system.cpu0.dcache.overall_avg_miss_latency::total 32376.583082 # average overall miss latency
1474 system.cpu0.dcache.blocked_cycles::no_mshrs 377833 # number of cycles access was blocked
1475 system.cpu0.dcache.blocked_cycles::no_targets 25059 # number of cycles access was blocked
1476 system.cpu0.dcache.blocked::no_mshrs 25141 # number of cycles access was blocked
1477 system.cpu0.dcache.blocked::no_targets 516 # number of cycles access was blocked
1478 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.028559 # average number of cycles each access was blocked
1479 system.cpu0.dcache.avg_blocked_cycles::no_targets 48.563953 # average number of cycles each access was blocked
1480 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1481 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1482 system.cpu0.dcache.writebacks::writebacks 692569 # number of writebacks
1483 system.cpu0.dcache.writebacks::total 692569 # number of writebacks
1484 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 109 # number of ReadReq MSHR hits
1485 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155609 # number of ReadReq MSHR hits
1486 system.cpu0.dcache.ReadReq_mshr_hits::total 155718 # number of ReadReq MSHR hits
1487 system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1409743 # number of WriteReq MSHR hits
1488 system.cpu0.dcache.WriteReq_mshr_hits::total 1409743 # number of WriteReq MSHR hits
1489 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1933 # number of LoadLockedReq MSHR hits
1490 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6811 # number of LoadLockedReq MSHR hits
1491 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8744 # number of LoadLockedReq MSHR hits
1492 system.cpu0.dcache.demand_mshr_hits::cpu1.data 109 # number of demand (read+write) MSHR hits
1493 system.cpu0.dcache.demand_mshr_hits::cpu2.data 1565352 # number of demand (read+write) MSHR hits
1494 system.cpu0.dcache.demand_mshr_hits::total 1565461 # number of demand (read+write) MSHR hits
1495 system.cpu0.dcache.overall_mshr_hits::cpu1.data 109 # number of overall MSHR hits
1496 system.cpu0.dcache.overall_mshr_hits::cpu2.data 1565352 # number of overall MSHR hits
1497 system.cpu0.dcache.overall_mshr_hits::total 1565461 # number of overall MSHR hits
1498 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59297 # number of ReadReq MSHR misses
1499 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160896 # number of ReadReq MSHR misses
1500 system.cpu0.dcache.ReadReq_mshr_misses::total 220193 # number of ReadReq MSHR misses
1501 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33952 # number of WriteReq MSHR misses
1502 system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 119815 # number of WriteReq MSHR misses
1503 system.cpu0.dcache.WriteReq_mshr_misses::total 153767 # number of WriteReq MSHR misses
1504 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19750 # number of SoftPFReq MSHR misses
1505 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43915 # number of SoftPFReq MSHR misses
1506 system.cpu0.dcache.SoftPFReq_mshr_misses::total 63665 # number of SoftPFReq MSHR misses
1507 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1351 # number of LoadLockedReq MSHR misses
1508 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2883 # number of LoadLockedReq MSHR misses
1509 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4234 # number of LoadLockedReq MSHR misses
1510 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 13 # number of StoreCondReq MSHR misses
1511 system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
1512 system.cpu0.dcache.demand_mshr_misses::cpu1.data 93249 # number of demand (read+write) MSHR misses
1513 system.cpu0.dcache.demand_mshr_misses::cpu2.data 280711 # number of demand (read+write) MSHR misses
1514 system.cpu0.dcache.demand_mshr_misses::total 373960 # number of demand (read+write) MSHR misses
1515 system.cpu0.dcache.overall_mshr_misses::cpu1.data 112999 # number of overall MSHR misses
1516 system.cpu0.dcache.overall_mshr_misses::cpu2.data 324626 # number of overall MSHR misses
1517 system.cpu0.dcache.overall_mshr_misses::total 437625 # number of overall MSHR misses
1518 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 783780250 # number of ReadReq MSHR miss cycles
1519 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2132755212 # number of ReadReq MSHR miss cycles
1520 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2916535462 # number of ReadReq MSHR miss cycles
1521 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238573617 # number of WriteReq MSHR miss cycles
1522 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5438601702 # number of WriteReq MSHR miss cycles
1523 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677175319 # number of WriteReq MSHR miss cycles
1524 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles
1525 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles
1526 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles
1527 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21611000 # number of LoadLockedReq MSHR miss cycles
1528 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251 # number of LoadLockedReq MSHR miss cycles
1529 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles
1530 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles
1531 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles
1532 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022353867 # number of demand (read+write) MSHR miss cycles
1533 system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles
1534 system.cpu0.dcache.demand_mshr_miss_latency::total 9593710781 # number of demand (read+write) MSHR miss cycles
1535 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275609367 # number of overall MSHR miss cycles
1536 system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles
1537 system.cpu0.dcache.overall_mshr_miss_latency::total 10505788787 # number of overall MSHR miss cycles
1538 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles
1539 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles
1540 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles
1541 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777844500 # number of WriteReq MSHR uncacheable cycles
1542 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1314970500 # number of WriteReq MSHR uncacheable cycles
1543 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092815000 # number of WriteReq MSHR uncacheable cycles
1544 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1797210500 # number of overall MSHR uncacheable cycles
1545 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3008091000 # number of overall MSHR uncacheable cycles
1546 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805301500 # number of overall MSHR uncacheable cycles
1547 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses
1548 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018218 # mshr miss rate for ReadReq accesses
1549 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008073 # mshr miss rate for ReadReq accesses
1550 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010646 # mshr miss rate for WriteReq accesses
1551 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017900 # mshr miss rate for WriteReq accesses
1552 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses
1553 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244576 # mshr miss rate for SoftPFReq accesses
1554 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224044 # mshr miss rate for SoftPFReq accesses
1555 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121872 # mshr miss rate for SoftPFReq accesses
1556 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses
1557 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019870 # mshr miss rate for LoadLockedReq accesses
1558 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009036 # mshr miss rate for LoadLockedReq accesses
1559 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses
1560 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses
1561 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012184 # mshr miss rate for demand accesses
1562 system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018081 # mshr miss rate for demand accesses
1563 system.cpu0.dcache.demand_mshr_miss_rate::total 0.007793 # mshr miss rate for demand accesses
1564 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014610 # mshr miss rate for overall accesses
1565 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020649 # mshr miss rate for overall accesses
1566 system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022 # mshr miss rate for overall accesses
1567 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency
1568 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency
1569 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency
1570 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.137164 # average WriteReq mshr miss latency
1571 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency
1572 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.981212 # average WriteReq mshr miss latency
1573 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency
1574 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency
1575 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency
1576 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency
1577 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344 # average LoadLockedReq mshr miss latency
1578 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency
1579 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency
1580 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency
1581 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.673509 # average overall mshr miss latency
1582 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency
1583 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.376888 # average overall mshr miss latency
1584 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.314206 # average overall mshr miss latency
1585 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency
1586 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.372550 # average overall mshr miss latency
1587 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1588 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
1589 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1590 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1591 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
1592 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1593 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1594 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
1595 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1596 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1597 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1598 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1599 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1600 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1601 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1602 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1603 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1604 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1605 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1606 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1607 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1608 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1609 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1610 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1611 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1612 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1613 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1614 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1615 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1616 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1617 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1618 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1619 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1620 system.cpu1.dtb.read_hits 4634872 # DTB read hits
1621 system.cpu1.dtb.read_misses 1584 # DTB read misses
1622 system.cpu1.dtb.write_hits 3276619 # DTB write hits
1623 system.cpu1.dtb.write_misses 228 # DTB write misses
1624 system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed
1625 system.cpu1.dtb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA
1626 system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1627 system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1628 system.cpu1.dtb.flush_entries 1208 # Number of entries that have been flushed from TLB
1629 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1630 system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
1631 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1632 system.cpu1.dtb.perms_faults 51 # Number of TLB faults due to permissions restrictions
1633 system.cpu1.dtb.read_accesses 4636456 # DTB read accesses
1634 system.cpu1.dtb.write_accesses 3276847 # DTB write accesses
1635 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1636 system.cpu1.dtb.hits 7911491 # DTB hits
1637 system.cpu1.dtb.misses 1812 # DTB misses
1638 system.cpu1.dtb.accesses 7913303 # DTB accesses
1639 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1640 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1641 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1642 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1643 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1644 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1645 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1646 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1647 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1648 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1649 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1650 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1651 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1652 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1653 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1654 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1655 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1656 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1657 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1658 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1659 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1660 system.cpu1.itb.inst_hits 21928102 # ITB inst hits
1661 system.cpu1.itb.inst_misses 848 # ITB inst misses
1662 system.cpu1.itb.read_hits 0 # DTB read hits
1663 system.cpu1.itb.read_misses 0 # DTB read misses
1664 system.cpu1.itb.write_hits 0 # DTB write hits
1665 system.cpu1.itb.write_misses 0 # DTB write misses
1666 system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed
1667 system.cpu1.itb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA
1668 system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1669 system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1670 system.cpu1.itb.flush_entries 700 # Number of entries that have been flushed from TLB
1671 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1672 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1673 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1674 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1675 system.cpu1.itb.read_accesses 0 # DTB read accesses
1676 system.cpu1.itb.write_accesses 0 # DTB write accesses
1677 system.cpu1.itb.inst_accesses 21928950 # ITB inst accesses
1678 system.cpu1.itb.hits 21928102 # DTB hits
1679 system.cpu1.itb.misses 848 # DTB misses
1680 system.cpu1.itb.accesses 21928950 # DTB accesses
1681 system.cpu1.numCycles 158012618 # number of cpu cycles simulated
1682 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1683 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1684 system.cpu1.committedInsts 21219740 # Number of instructions committed
1685 system.cpu1.committedOps 25418010 # Number of ops (including micro ops) committed
1686 system.cpu1.num_int_alu_accesses 22602371 # Number of integer alu accesses
1687 system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses
1688 system.cpu1.num_func_calls 2405283 # number of times a function call or return occured
1689 system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls
1690 system.cpu1.num_int_insts 22602371 # number of integer instructions
1691 system.cpu1.num_fp_insts 1626 # number of float instructions
1692 system.cpu1.num_int_register_reads 41665137 # number of times the integer registers were read
1693 system.cpu1.num_int_register_writes 15857681 # number of times the integer registers were written
1694 system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read
1695 system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
1696 system.cpu1.num_cc_register_reads 92378686 # number of times the CC registers were read
1697 system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written
1698 system.cpu1.num_mem_refs 8126078 # number of memory refs
1699 system.cpu1.num_load_insts 4682102 # Number of load instructions
1700 system.cpu1.num_store_insts 3443976 # Number of store instructions
1701 system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles
1702 system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles
1703 system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles
1704 system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles
1705 system.cpu1.Branches 5257577 # Number of branches fetched
1706 system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction
1707 system.cpu1.op_class::IntAlu 17988056 68.83% 68.83% # Class of executed instruction
1708 system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction
1709 system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
1710 system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
1711 system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
1712 system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction
1713 system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction
1714 system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction
1715 system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction
1716 system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction
1717 system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction
1718 system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction
1719 system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction
1720 system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction
1721 system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction
1722 system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction
1723 system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction
1724 system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction
1725 system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction
1726 system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction
1727 system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction
1728 system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction
1729 system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction
1730 system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction
1731 system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction
1732 system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction
1733 system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction
1734 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction
1735 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction
1736 system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction
1737 system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction
1738 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1739 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1740 system.cpu1.op_class::total 26134332 # Class of executed instruction
1741 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1742 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1743 system.cpu2.branchPred.lookups 17411527 # Number of BP lookups
1744 system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted
1745 system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect
1746 system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups
1747 system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits
1748 system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1749 system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage
1750 system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target.
1751 system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions.
1752 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1753 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1754 system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1755 system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1756 system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1757 system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1758 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1759 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1760 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1761 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1762 system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1763 system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1764 system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1765 system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1766 system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1767 system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1768 system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1769 system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1770 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1771 system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1772 system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1773 system.cpu2.dtb.inst_hits 0 # ITB inst hits
1774 system.cpu2.dtb.inst_misses 0 # ITB inst misses
1775 system.cpu2.dtb.read_hits 9691496 # DTB read hits
1776 system.cpu2.dtb.read_misses 37543 # DTB read misses
1777 system.cpu2.dtb.write_hits 7160478 # DTB write hits
1778 system.cpu2.dtb.write_misses 5658 # DTB write misses
1779 system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed
1780 system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
1781 system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1782 system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1783 system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB
1784 system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions
1785 system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch
1786 system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1787 system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions
1788 system.cpu2.dtb.read_accesses 9729039 # DTB read accesses
1789 system.cpu2.dtb.write_accesses 7166136 # DTB write accesses
1790 system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
1791 system.cpu2.dtb.hits 16851974 # DTB hits
1792 system.cpu2.dtb.misses 43201 # DTB misses
1793 system.cpu2.dtb.accesses 16895175 # DTB accesses
1794 system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1795 system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1796 system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1797 system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1798 system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1799 system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1800 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1801 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1802 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1803 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1804 system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1805 system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1806 system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1807 system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1808 system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1809 system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1810 system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1811 system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1812 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1813 system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1814 system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1815 system.cpu2.itb.inst_hits 12855360 # ITB inst hits
1816 system.cpu2.itb.inst_misses 6344 # ITB inst misses
1817 system.cpu2.itb.read_hits 0 # DTB read hits
1818 system.cpu2.itb.read_misses 0 # DTB read misses
1819 system.cpu2.itb.write_hits 0 # DTB write hits
1820 system.cpu2.itb.write_misses 0 # DTB write misses
1821 system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed
1822 system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
1823 system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1824 system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1825 system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB
1826 system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1827 system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1828 system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1829 system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions
1830 system.cpu2.itb.read_accesses 0 # DTB read accesses
1831 system.cpu2.itb.write_accesses 0 # DTB write accesses
1832 system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses
1833 system.cpu2.itb.hits 12855360 # DTB hits
1834 system.cpu2.itb.misses 6344 # DTB misses
1835 system.cpu2.itb.accesses 12861704 # DTB accesses
1836 system.cpu2.numCycles 69831868 # number of cpu cycles simulated
1837 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1838 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1839 system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss
1840 system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed
1841 system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered
1842 system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken
1843 system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked
1844 system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing
1845 system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb
1846 system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1847 system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain
1848 system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps
1849 system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions
1850 system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
1851 system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched
1852 system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed
1853 system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed
1854 system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total)
1855 system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total)
1856 system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total)
1857 system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1858 system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total)
1859 system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total)
1860 system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total)
1861 system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total)
1862 system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total)
1863 system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total)
1864 system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total)
1865 system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total)
1866 system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total)
1867 system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1868 system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1869 system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1870 system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total)
1871 system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle
1872 system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle
1873 system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle
1874 system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked
1875 system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running
1876 system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking
1877 system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing
1878 system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch
1879 system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction
1880 system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode
1881 system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode
1882 system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing
1883 system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle
1884 system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking
1885 system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst
1886 system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running
1887 system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking
1888 system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename
1889 system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full
1890 system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full
1891 system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full
1892 system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full
1893 system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed
1894 system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made
1895 system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups
1896 system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups
1897 system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed
1898 system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing
1899 system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed
1900 system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed
1901 system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer
1902 system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit.
1903 system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit.
1904 system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads.
1905 system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores.
1906 system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec)
1907 system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ
1908 system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued
1909 system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued
1910 system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling
1911 system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph
1912 system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed
1913 system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle
1914 system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle
1915 system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle
1916 system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1917 system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle
1918 system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle
1919 system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle
1920 system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle
1921 system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle
1922 system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle
1923 system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle
1924 system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle
1925 system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle
1926 system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1927 system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1928 system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1929 system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle
1930 system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1931 system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available
1932 system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available
1933 system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available
1934 system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available
1935 system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available
1936 system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available
1937 system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available
1938 system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available
1939 system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
1940 system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available
1941 system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available
1942 system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available
1943 system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available
1944 system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available
1945 system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available
1946 system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available
1947 system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available
1948 system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available
1949 system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available
1950 system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available
1951 system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available
1952 system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available
1953 system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available
1954 system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available
1955 system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available
1956 system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available
1957 system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available
1958 system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available
1959 system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
1960 system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available
1961 system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available
1962 system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1963 system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1964 system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued
1965 system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued
1966 system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued
1967 system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued
1968 system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued
1969 system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
1970 system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
1971 system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
1972 system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
1973 system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
1974 system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
1975 system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
1976 system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued
1977 system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
1978 system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
1979 system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued
1980 system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
1981 system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
1982 system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued
1983 system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
1984 system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
1985 system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
1986 system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
1987 system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued
1988 system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
1989 system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued
1990 system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued
1991 system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
1992 system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued
1993 system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
1994 system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued
1995 system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued
1996 system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1997 system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1998 system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued
1999 system.cpu2.iq.rate 0.744849 # Inst issue rate
2000 system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested
2001 system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst)
2002 system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads
2003 system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes
2004 system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses
2005 system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads
2006 system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes
2007 system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses
2008 system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses
2009 system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses
2010 system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores
2011 system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2012 system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed
2013 system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed
2014 system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations
2015 system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed
2016 system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2017 system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2018 system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled
2019 system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked
2020 system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2021 system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing
2022 system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking
2023 system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking
2024 system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ
2025 system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch
2026 system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions
2027 system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions
2028 system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions
2029 system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall
2030 system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall
2031 system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations
2032 system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly
2033 system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly
2034 system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute
2035 system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions
2036 system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed
2037 system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute
2038 system.cpu2.iew.exec_swp 0 # number of swp insts executed
2039 system.cpu2.iew.exec_nop 107408 # number of nop insts executed
2040 system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed
2041 system.cpu2.iew.exec_branches 9489180 # Number of branches executed
2042 system.cpu2.iew.exec_stores 7465028 # Number of stores executed
2043 system.cpu2.iew.exec_rate 0.738611 # Inst execution rate
2044 system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit
2045 system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back
2046 system.cpu2.iew.wb_producers 26486298 # num instructions producing a value
2047 system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value
2048 system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2049 system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle
2050 system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back
2051 system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2052 system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit
2053 system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards
2054 system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted
2055 system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle
2056 system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle
2057 system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle
2058 system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2059 system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle
2060 system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle
2061 system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle
2062 system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle
2063 system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle
2064 system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle
2065 system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle
2066 system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle
2067 system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle
2068 system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2069 system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2070 system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2071 system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle
2072 system.cpu2.commit.committedInsts 38915831 # Number of instructions committed
2073 system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed
2074 system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
2075 system.cpu2.commit.refs 15804910 # Number of memory references committed
2076 system.cpu2.commit.loads 8667813 # Number of loads committed
2077 system.cpu2.commit.membars 226604 # Number of memory barriers committed
2078 system.cpu2.commit.branches 8912074 # Number of branches committed
2079 system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
2080 system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions.
2081 system.cpu2.commit.function_calls 1635579 # Number of function calls committed.
2082 system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2083 system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction
2084 system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction
2085 system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction
2086 system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction
2087 system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction
2088 system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction
2089 system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction
2090 system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction
2091 system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction
2092 system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction
2093 system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction
2094 system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction
2095 system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction
2096 system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction
2097 system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction
2098 system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction
2099 system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction
2100 system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction
2101 system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction
2102 system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction
2103 system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction
2104 system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction
2105 system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction
2106 system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction
2107 system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction
2108 system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction
2109 system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
2110 system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
2111 system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
2112 system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction
2113 system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction
2114 system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2115 system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2116 system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction
2117 system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached
2118 system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
2119 system.cpu2.rob.rob_reads 113043839 # The number of ROB reads
2120 system.cpu2.rob.rob_writes 112575250 # The number of ROB writes
2121 system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself
2122 system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling
2123 system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2124 system.cpu2.committedInsts 38852054 # Number of Instructions Simulated
2125 system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated
2126 system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction
2127 system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads
2128 system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle
2129 system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads
2130 system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads
2131 system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes
2132 system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads
2133 system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes
2134 system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads
2135 system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes
2136 system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads
2137 system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes
2138 system.iocache.tags.replacements 36442 # number of replacements
2139 system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use
2140 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2141 system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
2142 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2143 system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit.
2144 system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor
2145 system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy
2146 system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy
2147 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2148 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2149 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2150 system.iocache.tags.tag_accesses 328356 # Number of tag accesses
2151 system.iocache.tags.data_accesses 328356 # Number of data accesses
2152 system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
2153 system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
2154 system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
2155 system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2156 system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses
2157 system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses
2158 system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
2159 system.iocache.demand_misses::total 252 # number of demand (read+write) misses
2160 system.iocache.overall_misses::realview.ide 252 # number of overall misses
2161 system.iocache.overall_misses::total 252 # number of overall misses
2162 system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles
2163 system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles
2164 system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles
2165 system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles
2166 system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles
2167 system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles
2168 system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
2169 system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2170 system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses)
2171 system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses)
2172 system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
2173 system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
2174 system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
2175 system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
2176 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2177 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2178 system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses
2179 system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses
2180 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2181 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2182 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2183 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2184 system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency
2185 system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency
2186 system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
2187 system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency
2188 system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
2189 system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency
2190 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2191 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2192 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2193 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2194 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2195 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2196 system.iocache.fast_writes 36224 # number of fast writes performed
2197 system.iocache.cache_copies 0 # number of cache copies performed
2198 system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses
2199 system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses
2200 system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses
2201 system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses
2202 system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses
2203 system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses
2204 system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles
2205 system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles
2206 system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles
2207 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles
2208 system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles
2209 system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles
2210 system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles
2211 system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles
2212 system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses
2213 system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses
2214 system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses
2215 system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses
2216 system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses
2217 system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses
2218 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency
2219 system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency
2220 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
2221 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2222 system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
2223 system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
2224 system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
2225 system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
2226 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2227 system.cpu2.kern.inst.arm 0 # number of arm instructions executed
2228 system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
2230 ---------- End Simulation Statistics ----------
projects / gem5.git / blob