tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=0
  37 machine_type=RealView_PBX
  38 mem_mode=timing
  39 mem_ranges=0:134217727
  40 memories=system.physmem system.realview.nvmem
  41 multi_proc=true
  42 num_work_ids=16
  43 panic_on_oops=true
  44 panic_on_panic=true
  45 phys_addr_range_64=40
  46 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
  47 reset_addr_64=0
  48 symbolfile=
  49 work_begin_ckpt_count=0
  50 work_begin_cpu_id_exit=-1
  51 work_begin_exit_count=0
  52 work_cpus_ckpt_count=0
  53 work_end_ckpt_count=0
  54 work_end_exit_count=0
  55 work_item_id=-1
  56 system_port=system.membus.slave[0]
  57
  58 [system.bridge]
  59 type=Bridge
  60 clk_domain=system.clk_domain
  61 delay=50000
  62 eventq_index=0
  63 ranges=268435456:520093695 1073741824:1610612735
  64 req_size=16
  65 resp_size=16
  66 master=system.iobus.slave[0]
  67 slave=system.membus.master[0]
  68
  69 [system.cf0]
  70 type=IdeDisk
  71 children=image
  72 delay=1000000
  73 driveID=master
  74 eventq_index=0
  75 image=system.cf0.image
  76
  77 [system.cf0.image]
  78 type=CowDiskImage
  79 children=child
  80 child=system.cf0.image.child
  81 eventq_index=0
  82 image_file=
  83 read_only=false
  84 table_size=65536
  85
  86 [system.cf0.image.child]
  87 type=RawDiskImage
  88 eventq_index=0
  89 image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
  90 read_only=true
  91
  92 [system.clk_domain]
  93 type=SrcClockDomain
  94 clock=1000
  95 domain_id=-1
  96 eventq_index=0
  97 init_perf_level=0
  98 voltage_domain=system.voltage_domain
  99
 100 [system.cpu0]
 101 type=DerivO3CPU
 102 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
 103 LFSTSize=1024
 104 LQEntries=32
 105 LSQCheckLoads=true
 106 LSQDepCheckShift=4
 107 SQEntries=32
 108 SSITSize=1024
 109 activity=0
 110 backComSize=5
 111 branchPred=system.cpu0.branchPred
 112 cachePorts=200
 113 checker=Null
 114 clk_domain=system.cpu_clk_domain
 115 commitToDecodeDelay=1
 116 commitToFetchDelay=1
 117 commitToIEWDelay=1
 118 commitToRenameDelay=1
 119 commitWidth=8
 120 cpu_id=0
 121 decodeToFetchDelay=1
 122 decodeToRenameDelay=1
 123 decodeWidth=8
 124 dispatchWidth=8
 125 do_checkpoint_insts=true
 126 do_quiesce=true
 127 do_statistics_insts=true
 128 dstage2_mmu=system.cpu0.dstage2_mmu
 129 dtb=system.cpu0.dtb
 130 eventq_index=0
 131 fetchBufferSize=64
 132 fetchToDecodeDelay=1
 133 fetchTrapLatency=1
 134 fetchWidth=8
 135 forwardComSize=5
 136 fuPool=system.cpu0.fuPool
 137 function_trace=false
 138 function_trace_start=0
 139 iewToCommitDelay=1
 140 iewToDecodeDelay=1
 141 iewToFetchDelay=1
 142 iewToRenameDelay=1
 143 interrupts=system.cpu0.interrupts
 144 isa=system.cpu0.isa
 145 issueToExecuteDelay=1
 146 issueWidth=8
 147 istage2_mmu=system.cpu0.istage2_mmu
 148 itb=system.cpu0.itb
 149 max_insts_all_threads=0
 150 max_insts_any_thread=0
 151 max_loads_all_threads=0
 152 max_loads_any_thread=0
 153 needsTSO=false
 154 numIQEntries=64
 155 numPhysCCRegs=0
 156 numPhysFloatRegs=256
 157 numPhysIntRegs=256
 158 numROBEntries=192
 159 numRobs=1
 160 numThreads=1
 161 profile=0
 162 progress_interval=0
 163 renameToDecodeDelay=1
 164 renameToFetchDelay=1
 165 renameToIEWDelay=2
 166 renameToROBDelay=1
 167 renameWidth=8
 168 simpoint_start_insts=
 169 smtCommitPolicy=RoundRobin
 170 smtFetchPolicy=SingleThread
 171 smtIQPolicy=Partitioned
 172 smtIQThreshold=100
 173 smtLSQPolicy=Partitioned
 174 smtLSQThreshold=100
 175 smtNumFetchingThreads=1
 176 smtROBPolicy=Partitioned
 177 smtROBThreshold=100
 178 socket_id=0
 179 squashWidth=8
 180 store_set_clear_period=250000
 181 switched_out=false
 182 system=system
 183 tracer=system.cpu0.tracer
 184 trapLatency=13
 185 wbDepth=1
 186 wbWidth=8
 187 workload=
 188 dcache_port=system.cpu0.dcache.cpu_side
 189 icache_port=system.cpu0.icache.cpu_side
 190
 191 [system.cpu0.branchPred]
 192 type=BranchPredictor
 193 BTBEntries=4096
 194 BTBTagSize=16
 195 RASSize=16
 196 choiceCtrBits=2
 197 choicePredictorSize=8192
 198 eventq_index=0
 199 globalCtrBits=2
 200 globalPredictorSize=8192
 201 instShiftAmt=2
 202 localCtrBits=2
 203 localHistoryTableSize=2048
 204 localPredictorSize=2048
 205 numThreads=1
 206 predType=tournament
 207
 208 [system.cpu0.dcache]
 209 type=BaseCache
 210 children=tags
 211 addr_ranges=0:18446744073709551615
 212 assoc=4
 213 clk_domain=system.cpu_clk_domain
 214 eventq_index=0
 215 forward_snoops=true
 216 hit_latency=2
 217 is_top_level=true
 218 max_miss_count=0
 219 mshrs=4
 220 prefetch_on_access=false
 221 prefetcher=Null
 222 response_latency=2
 223 sequential_access=false
 224 size=32768
 225 system=system
 226 tags=system.cpu0.dcache.tags
 227 tgts_per_mshr=20
 228 two_queue=false
 229 write_buffers=8
 230 cpu_side=system.cpu0.dcache_port
 231 mem_side=system.toL2Bus.slave[1]
 232
 233 [system.cpu0.dcache.tags]
 234 type=LRU
 235 assoc=4
 236 block_size=64
 237 clk_domain=system.cpu_clk_domain
 238 eventq_index=0
 239 hit_latency=2
 240 sequential_access=false
 241 size=32768
 242
 243 [system.cpu0.dstage2_mmu]
 244 type=ArmStage2MMU
 245 children=stage2_tlb
 246 eventq_index=0
 247 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 248 tlb=system.cpu0.dtb
 249
 250 [system.cpu0.dstage2_mmu.stage2_tlb]
 251 type=ArmTLB
 252 children=walker
 253 eventq_index=0
 254 is_stage2=true
 255 size=32
 256 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 257
 258 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 259 type=ArmTableWalker
 260 clk_domain=system.cpu_clk_domain
 261 eventq_index=0
 262 is_stage2=true
 263 num_squash_per_cycle=2
 264 sys=system
 265 port=system.toL2Bus.slave[5]
 266
 267 [system.cpu0.dtb]
 268 type=ArmTLB
 269 children=walker
 270 eventq_index=0
 271 is_stage2=false
 272 size=64
 273 walker=system.cpu0.dtb.walker
 274
 275 [system.cpu0.dtb.walker]
 276 type=ArmTableWalker
 277 clk_domain=system.cpu_clk_domain
 278 eventq_index=0
 279 is_stage2=false
 280 num_squash_per_cycle=2
 281 sys=system
 282 port=system.toL2Bus.slave[3]
 283
 284 [system.cpu0.fuPool]
 285 type=FUPool
 286 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 287 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
 288 eventq_index=0
 289
 290 [system.cpu0.fuPool.FUList0]
 291 type=FUDesc
 292 children=opList
 293 count=6
 294 eventq_index=0
 295 opList=system.cpu0.fuPool.FUList0.opList
 296
 297 [system.cpu0.fuPool.FUList0.opList]
 298 type=OpDesc
 299 eventq_index=0
 300 issueLat=1
 301 opClass=IntAlu
 302 opLat=1
 303
 304 [system.cpu0.fuPool.FUList1]
 305 type=FUDesc
 306 children=opList0 opList1
 307 count=2
 308 eventq_index=0
 309 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 310
 311 [system.cpu0.fuPool.FUList1.opList0]
 312 type=OpDesc
 313 eventq_index=0
 314 issueLat=1
 315 opClass=IntMult
 316 opLat=3
 317
 318 [system.cpu0.fuPool.FUList1.opList1]
 319 type=OpDesc
 320 eventq_index=0
 321 issueLat=19
 322 opClass=IntDiv
 323 opLat=20
 324
 325 [system.cpu0.fuPool.FUList2]
 326 type=FUDesc
 327 children=opList0 opList1 opList2
 328 count=4
 329 eventq_index=0
 330 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
 331
 332 [system.cpu0.fuPool.FUList2.opList0]
 333 type=OpDesc
 334 eventq_index=0
 335 issueLat=1
 336 opClass=FloatAdd
 337 opLat=2
 338
 339 [system.cpu0.fuPool.FUList2.opList1]
 340 type=OpDesc
 341 eventq_index=0
 342 issueLat=1
 343 opClass=FloatCmp
 344 opLat=2
 345
 346 [system.cpu0.fuPool.FUList2.opList2]
 347 type=OpDesc
 348 eventq_index=0
 349 issueLat=1
 350 opClass=FloatCvt
 351 opLat=2
 352
 353 [system.cpu0.fuPool.FUList3]
 354 type=FUDesc
 355 children=opList0 opList1 opList2
 356 count=2
 357 eventq_index=0
 358 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
 359
 360 [system.cpu0.fuPool.FUList3.opList0]
 361 type=OpDesc
 362 eventq_index=0
 363 issueLat=1
 364 opClass=FloatMult
 365 opLat=4
 366
 367 [system.cpu0.fuPool.FUList3.opList1]
 368 type=OpDesc
 369 eventq_index=0
 370 issueLat=12
 371 opClass=FloatDiv
 372 opLat=12
 373
 374 [system.cpu0.fuPool.FUList3.opList2]
 375 type=OpDesc
 376 eventq_index=0
 377 issueLat=24
 378 opClass=FloatSqrt
 379 opLat=24
 380
 381 [system.cpu0.fuPool.FUList4]
 382 type=FUDesc
 383 children=opList
 384 count=0
 385 eventq_index=0
 386 opList=system.cpu0.fuPool.FUList4.opList
 387
 388 [system.cpu0.fuPool.FUList4.opList]
 389 type=OpDesc
 390 eventq_index=0
 391 issueLat=1
 392 opClass=MemRead
 393 opLat=1
 394
 395 [system.cpu0.fuPool.FUList5]
 396 type=FUDesc
 397 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 398 count=4
 399 eventq_index=0
 400 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
 401
 402 [system.cpu0.fuPool.FUList5.opList00]
 403 type=OpDesc
 404 eventq_index=0
 405 issueLat=1
 406 opClass=SimdAdd
 407 opLat=1
 408
 409 [system.cpu0.fuPool.FUList5.opList01]
 410 type=OpDesc
 411 eventq_index=0
 412 issueLat=1
 413 opClass=SimdAddAcc
 414 opLat=1
 415
 416 [system.cpu0.fuPool.FUList5.opList02]
 417 type=OpDesc
 418 eventq_index=0
 419 issueLat=1
 420 opClass=SimdAlu
 421 opLat=1
 422
 423 [system.cpu0.fuPool.FUList5.opList03]
 424 type=OpDesc
 425 eventq_index=0
 426 issueLat=1
 427 opClass=SimdCmp
 428 opLat=1
 429
 430 [system.cpu0.fuPool.FUList5.opList04]
 431 type=OpDesc
 432 eventq_index=0
 433 issueLat=1
 434 opClass=SimdCvt
 435 opLat=1
 436
 437 [system.cpu0.fuPool.FUList5.opList05]
 438 type=OpDesc
 439 eventq_index=0
 440 issueLat=1
 441 opClass=SimdMisc
 442 opLat=1
 443
 444 [system.cpu0.fuPool.FUList5.opList06]
 445 type=OpDesc
 446 eventq_index=0
 447 issueLat=1
 448 opClass=SimdMult
 449 opLat=1
 450
 451 [system.cpu0.fuPool.FUList5.opList07]
 452 type=OpDesc
 453 eventq_index=0
 454 issueLat=1
 455 opClass=SimdMultAcc
 456 opLat=1
 457
 458 [system.cpu0.fuPool.FUList5.opList08]
 459 type=OpDesc
 460 eventq_index=0
 461 issueLat=1
 462 opClass=SimdShift
 463 opLat=1
 464
 465 [system.cpu0.fuPool.FUList5.opList09]
 466 type=OpDesc
 467 eventq_index=0
 468 issueLat=1
 469 opClass=SimdShiftAcc
 470 opLat=1
 471
 472 [system.cpu0.fuPool.FUList5.opList10]
 473 type=OpDesc
 474 eventq_index=0
 475 issueLat=1
 476 opClass=SimdSqrt
 477 opLat=1
 478
 479 [system.cpu0.fuPool.FUList5.opList11]
 480 type=OpDesc
 481 eventq_index=0
 482 issueLat=1
 483 opClass=SimdFloatAdd
 484 opLat=1
 485
 486 [system.cpu0.fuPool.FUList5.opList12]
 487 type=OpDesc
 488 eventq_index=0
 489 issueLat=1
 490 opClass=SimdFloatAlu
 491 opLat=1
 492
 493 [system.cpu0.fuPool.FUList5.opList13]
 494 type=OpDesc
 495 eventq_index=0
 496 issueLat=1
 497 opClass=SimdFloatCmp
 498 opLat=1
 499
 500 [system.cpu0.fuPool.FUList5.opList14]
 501 type=OpDesc
 502 eventq_index=0
 503 issueLat=1
 504 opClass=SimdFloatCvt
 505 opLat=1
 506
 507 [system.cpu0.fuPool.FUList5.opList15]
 508 type=OpDesc
 509 eventq_index=0
 510 issueLat=1
 511 opClass=SimdFloatDiv
 512 opLat=1
 513
 514 [system.cpu0.fuPool.FUList5.opList16]
 515 type=OpDesc
 516 eventq_index=0
 517 issueLat=1
 518 opClass=SimdFloatMisc
 519 opLat=1
 520
 521 [system.cpu0.fuPool.FUList5.opList17]
 522 type=OpDesc
 523 eventq_index=0
 524 issueLat=1
 525 opClass=SimdFloatMult
 526 opLat=1
 527
 528 [system.cpu0.fuPool.FUList5.opList18]
 529 type=OpDesc
 530 eventq_index=0
 531 issueLat=1
 532 opClass=SimdFloatMultAcc
 533 opLat=1
 534
 535 [system.cpu0.fuPool.FUList5.opList19]
 536 type=OpDesc
 537 eventq_index=0
 538 issueLat=1
 539 opClass=SimdFloatSqrt
 540 opLat=1
 541
 542 [system.cpu0.fuPool.FUList6]
 543 type=FUDesc
 544 children=opList
 545 count=0
 546 eventq_index=0
 547 opList=system.cpu0.fuPool.FUList6.opList
 548
 549 [system.cpu0.fuPool.FUList6.opList]
 550 type=OpDesc
 551 eventq_index=0
 552 issueLat=1
 553 opClass=MemWrite
 554 opLat=1
 555
 556 [system.cpu0.fuPool.FUList7]
 557 type=FUDesc
 558 children=opList0 opList1
 559 count=4
 560 eventq_index=0
 561 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 562
 563 [system.cpu0.fuPool.FUList7.opList0]
 564 type=OpDesc
 565 eventq_index=0
 566 issueLat=1
 567 opClass=MemRead
 568 opLat=1
 569
 570 [system.cpu0.fuPool.FUList7.opList1]
 571 type=OpDesc
 572 eventq_index=0
 573 issueLat=1
 574 opClass=MemWrite
 575 opLat=1
 576
 577 [system.cpu0.fuPool.FUList8]
 578 type=FUDesc
 579 children=opList
 580 count=1
 581 eventq_index=0
 582 opList=system.cpu0.fuPool.FUList8.opList
 583
 584 [system.cpu0.fuPool.FUList8.opList]
 585 type=OpDesc
 586 eventq_index=0
 587 issueLat=3
 588 opClass=IprAccess
 589 opLat=3
 590
 591 [system.cpu0.icache]
 592 type=BaseCache
 593 children=tags
 594 addr_ranges=0:18446744073709551615
 595 assoc=1
 596 clk_domain=system.cpu_clk_domain
 597 eventq_index=0
 598 forward_snoops=true
 599 hit_latency=2
 600 is_top_level=true
 601 max_miss_count=0
 602 mshrs=4
 603 prefetch_on_access=false
 604 prefetcher=Null
 605 response_latency=2
 606 sequential_access=false
 607 size=32768
 608 system=system
 609 tags=system.cpu0.icache.tags
 610 tgts_per_mshr=20
 611 two_queue=false
 612 write_buffers=8
 613 cpu_side=system.cpu0.icache_port
 614 mem_side=system.toL2Bus.slave[0]
 615
 616 [system.cpu0.icache.tags]
 617 type=LRU
 618 assoc=1
 619 block_size=64
 620 clk_domain=system.cpu_clk_domain
 621 eventq_index=0
 622 hit_latency=2
 623 sequential_access=false
 624 size=32768
 625
 626 [system.cpu0.interrupts]
 627 type=ArmInterrupts
 628 eventq_index=0
 629
 630 [system.cpu0.isa]
 631 type=ArmISA
 632 eventq_index=0
 633 fpsid=1090793632
 634 id_aa64afr0_el1=0
 635 id_aa64afr1_el1=0
 636 id_aa64dfr0_el1=1052678
 637 id_aa64dfr1_el1=0
 638 id_aa64isar0_el1=0
 639 id_aa64isar1_el1=0
 640 id_aa64mmfr0_el1=15728642
 641 id_aa64mmfr1_el1=0
 642 id_aa64pfr0_el1=17
 643 id_aa64pfr1_el1=0
 644 id_isar0=34607377
 645 id_isar1=34677009
 646 id_isar2=555950401
 647 id_isar3=17899825
 648 id_isar4=268501314
 649 id_isar5=0
 650 id_mmfr0=270536963
 651 id_mmfr1=0
 652 id_mmfr2=19070976
 653 id_mmfr3=34611729
 654 id_pfr0=49
 655 id_pfr1=4113
 656 midr=1091551472
 657 system=system
 658
 659 [system.cpu0.istage2_mmu]
 660 type=ArmStage2MMU
 661 children=stage2_tlb
 662 eventq_index=0
 663 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 664 tlb=system.cpu0.itb
 665
 666 [system.cpu0.istage2_mmu.stage2_tlb]
 667 type=ArmTLB
 668 children=walker
 669 eventq_index=0
 670 is_stage2=true
 671 size=32
 672 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 673
 674 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 675 type=ArmTableWalker
 676 clk_domain=system.cpu_clk_domain
 677 eventq_index=0
 678 is_stage2=true
 679 num_squash_per_cycle=2
 680 sys=system
 681 port=system.toL2Bus.slave[4]
 682
 683 [system.cpu0.itb]
 684 type=ArmTLB
 685 children=walker
 686 eventq_index=0
 687 is_stage2=false
 688 size=64
 689 walker=system.cpu0.itb.walker
 690
 691 [system.cpu0.itb.walker]
 692 type=ArmTableWalker
 693 clk_domain=system.cpu_clk_domain
 694 eventq_index=0
 695 is_stage2=false
 696 num_squash_per_cycle=2
 697 sys=system
 698 port=system.toL2Bus.slave[2]
 699
 700 [system.cpu0.tracer]
 701 type=ExeTracer
 702 eventq_index=0
 703
 704 [system.cpu1]
 705 type=DerivO3CPU
 706 children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
 707 LFSTSize=1024
 708 LQEntries=32
 709 LSQCheckLoads=true
 710 LSQDepCheckShift=4
 711 SQEntries=32
 712 SSITSize=1024
 713 activity=0
 714 backComSize=5
 715 branchPred=system.cpu1.branchPred
 716 cachePorts=200
 717 checker=Null
 718 clk_domain=system.cpu_clk_domain
 719 commitToDecodeDelay=1
 720 commitToFetchDelay=1
 721 commitToIEWDelay=1
 722 commitToRenameDelay=1
 723 commitWidth=8
 724 cpu_id=0
 725 decodeToFetchDelay=1
 726 decodeToRenameDelay=1
 727 decodeWidth=8
 728 dispatchWidth=8
 729 do_checkpoint_insts=true
 730 do_quiesce=true
 731 do_statistics_insts=true
 732 dstage2_mmu=system.cpu1.dstage2_mmu
 733 dtb=system.cpu1.dtb
 734 eventq_index=0
 735 fetchBufferSize=64
 736 fetchToDecodeDelay=1
 737 fetchTrapLatency=1
 738 fetchWidth=8
 739 forwardComSize=5
 740 fuPool=system.cpu1.fuPool
 741 function_trace=false
 742 function_trace_start=0
 743 iewToCommitDelay=1
 744 iewToDecodeDelay=1
 745 iewToFetchDelay=1
 746 iewToRenameDelay=1
 747 interrupts=Null
 748 isa=system.cpu1.isa
 749 issueToExecuteDelay=1
 750 issueWidth=8
 751 istage2_mmu=system.cpu1.istage2_mmu
 752 itb=system.cpu1.itb
 753 max_insts_all_threads=0
 754 max_insts_any_thread=0
 755 max_loads_all_threads=0
 756 max_loads_any_thread=0
 757 needsTSO=false
 758 numIQEntries=64
 759 numPhysCCRegs=0
 760 numPhysFloatRegs=256
 761 numPhysIntRegs=256
 762 numROBEntries=192
 763 numRobs=1
 764 numThreads=1
 765 profile=0
 766 progress_interval=0
 767 renameToDecodeDelay=1
 768 renameToFetchDelay=1
 769 renameToIEWDelay=2
 770 renameToROBDelay=1
 771 renameWidth=8
 772 simpoint_start_insts=
 773 smtCommitPolicy=RoundRobin
 774 smtFetchPolicy=SingleThread
 775 smtIQPolicy=Partitioned
 776 smtIQThreshold=100
 777 smtLSQPolicy=Partitioned
 778 smtLSQThreshold=100
 779 smtNumFetchingThreads=1
 780 smtROBPolicy=Partitioned
 781 smtROBThreshold=100
 782 socket_id=0
 783 squashWidth=8
 784 store_set_clear_period=250000
 785 switched_out=true
 786 system=system
 787 tracer=system.cpu1.tracer
 788 trapLatency=13
 789 wbDepth=1
 790 wbWidth=8
 791 workload=
 792
 793 [system.cpu1.branchPred]
 794 type=BranchPredictor
 795 BTBEntries=4096
 796 BTBTagSize=16
 797 RASSize=16
 798 choiceCtrBits=2
 799 choicePredictorSize=8192
 800 eventq_index=0
 801 globalCtrBits=2
 802 globalPredictorSize=8192
 803 instShiftAmt=2
 804 localCtrBits=2
 805 localHistoryTableSize=2048
 806 localPredictorSize=2048
 807 numThreads=1
 808 predType=tournament
 809
 810 [system.cpu1.dstage2_mmu]
 811 type=ArmStage2MMU
 812 children=stage2_tlb
 813 eventq_index=0
 814 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
 815 tlb=system.cpu1.dtb
 816
 817 [system.cpu1.dstage2_mmu.stage2_tlb]
 818 type=ArmTLB
 819 children=walker
 820 eventq_index=0
 821 is_stage2=true
 822 size=32
 823 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
 824
 825 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
 826 type=ArmTableWalker
 827 clk_domain=system.cpu_clk_domain
 828 eventq_index=0
 829 is_stage2=true
 830 num_squash_per_cycle=2
 831 sys=system
 832
 833 [system.cpu1.dtb]
 834 type=ArmTLB
 835 children=walker
 836 eventq_index=0
 837 is_stage2=false
 838 size=64
 839 walker=system.cpu1.dtb.walker
 840
 841 [system.cpu1.dtb.walker]
 842 type=ArmTableWalker
 843 clk_domain=system.cpu_clk_domain
 844 eventq_index=0
 845 is_stage2=false
 846 num_squash_per_cycle=2
 847 sys=system
 848
 849 [system.cpu1.fuPool]
 850 type=FUPool
 851 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 852 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
 853 eventq_index=0
 854
 855 [system.cpu1.fuPool.FUList0]
 856 type=FUDesc
 857 children=opList
 858 count=6
 859 eventq_index=0
 860 opList=system.cpu1.fuPool.FUList0.opList
 861
 862 [system.cpu1.fuPool.FUList0.opList]
 863 type=OpDesc
 864 eventq_index=0
 865 issueLat=1
 866 opClass=IntAlu
 867 opLat=1
 868
 869 [system.cpu1.fuPool.FUList1]
 870 type=FUDesc
 871 children=opList0 opList1
 872 count=2
 873 eventq_index=0
 874 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 875
 876 [system.cpu1.fuPool.FUList1.opList0]
 877 type=OpDesc
 878 eventq_index=0
 879 issueLat=1
 880 opClass=IntMult
 881 opLat=3
 882
 883 [system.cpu1.fuPool.FUList1.opList1]
 884 type=OpDesc
 885 eventq_index=0
 886 issueLat=19
 887 opClass=IntDiv
 888 opLat=20
 889
 890 [system.cpu1.fuPool.FUList2]
 891 type=FUDesc
 892 children=opList0 opList1 opList2
 893 count=4
 894 eventq_index=0
 895 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
 896
 897 [system.cpu1.fuPool.FUList2.opList0]
 898 type=OpDesc
 899 eventq_index=0
 900 issueLat=1
 901 opClass=FloatAdd
 902 opLat=2
 903
 904 [system.cpu1.fuPool.FUList2.opList1]
 905 type=OpDesc
 906 eventq_index=0
 907 issueLat=1
 908 opClass=FloatCmp
 909 opLat=2
 910
 911 [system.cpu1.fuPool.FUList2.opList2]
 912 type=OpDesc
 913 eventq_index=0
 914 issueLat=1
 915 opClass=FloatCvt
 916 opLat=2
 917
 918 [system.cpu1.fuPool.FUList3]
 919 type=FUDesc
 920 children=opList0 opList1 opList2
 921 count=2
 922 eventq_index=0
 923 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
 924
 925 [system.cpu1.fuPool.FUList3.opList0]
 926 type=OpDesc
 927 eventq_index=0
 928 issueLat=1
 929 opClass=FloatMult
 930 opLat=4
 931
 932 [system.cpu1.fuPool.FUList3.opList1]
 933 type=OpDesc
 934 eventq_index=0
 935 issueLat=12
 936 opClass=FloatDiv
 937 opLat=12
 938
 939 [system.cpu1.fuPool.FUList3.opList2]
 940 type=OpDesc
 941 eventq_index=0
 942 issueLat=24
 943 opClass=FloatSqrt
 944 opLat=24
 945
 946 [system.cpu1.fuPool.FUList4]
 947 type=FUDesc
 948 children=opList
 949 count=0
 950 eventq_index=0
 951 opList=system.cpu1.fuPool.FUList4.opList
 952
 953 [system.cpu1.fuPool.FUList4.opList]
 954 type=OpDesc
 955 eventq_index=0
 956 issueLat=1
 957 opClass=MemRead
 958 opLat=1
 959
 960 [system.cpu1.fuPool.FUList5]
 961 type=FUDesc
 962 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 963 count=4
 964 eventq_index=0
 965 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
 966
 967 [system.cpu1.fuPool.FUList5.opList00]
 968 type=OpDesc
 969 eventq_index=0
 970 issueLat=1
 971 opClass=SimdAdd
 972 opLat=1
 973
 974 [system.cpu1.fuPool.FUList5.opList01]
 975 type=OpDesc
 976 eventq_index=0
 977 issueLat=1
 978 opClass=SimdAddAcc
 979 opLat=1
 980
 981 [system.cpu1.fuPool.FUList5.opList02]
 982 type=OpDesc
 983 eventq_index=0
 984 issueLat=1
 985 opClass=SimdAlu
 986 opLat=1
 987
 988 [system.cpu1.fuPool.FUList5.opList03]
 989 type=OpDesc
 990 eventq_index=0
 991 issueLat=1
 992 opClass=SimdCmp
 993 opLat=1
 994
 995 [system.cpu1.fuPool.FUList5.opList04]
 996 type=OpDesc
 997 eventq_index=0
 998 issueLat=1
 999 opClass=SimdCvt
1000 opLat=1
1001
1002 [system.cpu1.fuPool.FUList5.opList05]
1003 type=OpDesc
1004 eventq_index=0
1005 issueLat=1
1006 opClass=SimdMisc
1007 opLat=1
1008
1009 [system.cpu1.fuPool.FUList5.opList06]
1010 type=OpDesc
1011 eventq_index=0
1012 issueLat=1
1013 opClass=SimdMult
1014 opLat=1
1015
1016 [system.cpu1.fuPool.FUList5.opList07]
1017 type=OpDesc
1018 eventq_index=0
1019 issueLat=1
1020 opClass=SimdMultAcc
1021 opLat=1
1022
1023 [system.cpu1.fuPool.FUList5.opList08]
1024 type=OpDesc
1025 eventq_index=0
1026 issueLat=1
1027 opClass=SimdShift
1028 opLat=1
1029
1030 [system.cpu1.fuPool.FUList5.opList09]
1031 type=OpDesc
1032 eventq_index=0
1033 issueLat=1
1034 opClass=SimdShiftAcc
1035 opLat=1
1036
1037 [system.cpu1.fuPool.FUList5.opList10]
1038 type=OpDesc
1039 eventq_index=0
1040 issueLat=1
1041 opClass=SimdSqrt
1042 opLat=1
1043
1044 [system.cpu1.fuPool.FUList5.opList11]
1045 type=OpDesc
1046 eventq_index=0
1047 issueLat=1
1048 opClass=SimdFloatAdd
1049 opLat=1
1050
1051 [system.cpu1.fuPool.FUList5.opList12]
1052 type=OpDesc
1053 eventq_index=0
1054 issueLat=1
1055 opClass=SimdFloatAlu
1056 opLat=1
1057
1058 [system.cpu1.fuPool.FUList5.opList13]
1059 type=OpDesc
1060 eventq_index=0
1061 issueLat=1
1062 opClass=SimdFloatCmp
1063 opLat=1
1064
1065 [system.cpu1.fuPool.FUList5.opList14]
1066 type=OpDesc
1067 eventq_index=0
1068 issueLat=1
1069 opClass=SimdFloatCvt
1070 opLat=1
1071
1072 [system.cpu1.fuPool.FUList5.opList15]
1073 type=OpDesc
1074 eventq_index=0
1075 issueLat=1
1076 opClass=SimdFloatDiv
1077 opLat=1
1078
1079 [system.cpu1.fuPool.FUList5.opList16]
1080 type=OpDesc
1081 eventq_index=0
1082 issueLat=1
1083 opClass=SimdFloatMisc
1084 opLat=1
1085
1086 [system.cpu1.fuPool.FUList5.opList17]
1087 type=OpDesc
1088 eventq_index=0
1089 issueLat=1
1090 opClass=SimdFloatMult
1091 opLat=1
1092
1093 [system.cpu1.fuPool.FUList5.opList18]
1094 type=OpDesc
1095 eventq_index=0
1096 issueLat=1
1097 opClass=SimdFloatMultAcc
1098 opLat=1
1099
1100 [system.cpu1.fuPool.FUList5.opList19]
1101 type=OpDesc
1102 eventq_index=0
1103 issueLat=1
1104 opClass=SimdFloatSqrt
1105 opLat=1
1106
1107 [system.cpu1.fuPool.FUList6]
1108 type=FUDesc
1109 children=opList
1110 count=0
1111 eventq_index=0
1112 opList=system.cpu1.fuPool.FUList6.opList
1113
1114 [system.cpu1.fuPool.FUList6.opList]
1115 type=OpDesc
1116 eventq_index=0
1117 issueLat=1
1118 opClass=MemWrite
1119 opLat=1
1120
1121 [system.cpu1.fuPool.FUList7]
1122 type=FUDesc
1123 children=opList0 opList1
1124 count=4
1125 eventq_index=0
1126 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
1127
1128 [system.cpu1.fuPool.FUList7.opList0]
1129 type=OpDesc
1130 eventq_index=0
1131 issueLat=1
1132 opClass=MemRead
1133 opLat=1
1134
1135 [system.cpu1.fuPool.FUList7.opList1]
1136 type=OpDesc
1137 eventq_index=0
1138 issueLat=1
1139 opClass=MemWrite
1140 opLat=1
1141
1142 [system.cpu1.fuPool.FUList8]
1143 type=FUDesc
1144 children=opList
1145 count=1
1146 eventq_index=0
1147 opList=system.cpu1.fuPool.FUList8.opList
1148
1149 [system.cpu1.fuPool.FUList8.opList]
1150 type=OpDesc
1151 eventq_index=0
1152 issueLat=3
1153 opClass=IprAccess
1154 opLat=3
1155
1156 [system.cpu1.isa]
1157 type=ArmISA
1158 eventq_index=0
1159 fpsid=1090793632
1160 id_aa64afr0_el1=0
1161 id_aa64afr1_el1=0
1162 id_aa64dfr0_el1=1052678
1163 id_aa64dfr1_el1=0
1164 id_aa64isar0_el1=0
1165 id_aa64isar1_el1=0
1166 id_aa64mmfr0_el1=15728642
1167 id_aa64mmfr1_el1=0
1168 id_aa64pfr0_el1=17
1169 id_aa64pfr1_el1=0
1170 id_isar0=34607377
1171 id_isar1=34677009
1172 id_isar2=555950401
1173 id_isar3=17899825
1174 id_isar4=268501314
1175 id_isar5=0
1176 id_mmfr0=270536963
1177 id_mmfr1=0
1178 id_mmfr2=19070976
1179 id_mmfr3=34611729
1180 id_pfr0=49
1181 id_pfr1=4113
1182 midr=1091551472
1183 system=system
1184
1185 [system.cpu1.istage2_mmu]
1186 type=ArmStage2MMU
1187 children=stage2_tlb
1188 eventq_index=0
1189 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1190 tlb=system.cpu1.itb
1191
1192 [system.cpu1.istage2_mmu.stage2_tlb]
1193 type=ArmTLB
1194 children=walker
1195 eventq_index=0
1196 is_stage2=true
1197 size=32
1198 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1199
1200 [system.cpu1.istage2_mmu.stage2_tlb.walker]
1201 type=ArmTableWalker
1202 clk_domain=system.cpu_clk_domain
1203 eventq_index=0
1204 is_stage2=true
1205 num_squash_per_cycle=2
1206 sys=system
1207
1208 [system.cpu1.itb]
1209 type=ArmTLB
1210 children=walker
1211 eventq_index=0
1212 is_stage2=false
1213 size=64
1214 walker=system.cpu1.itb.walker
1215
1216 [system.cpu1.itb.walker]
1217 type=ArmTableWalker
1218 clk_domain=system.cpu_clk_domain
1219 eventq_index=0
1220 is_stage2=false
1221 num_squash_per_cycle=2
1222 sys=system
1223
1224 [system.cpu1.tracer]
1225 type=ExeTracer
1226 eventq_index=0
1227
1228 [system.cpu_clk_domain]
1229 type=SrcClockDomain
1230 clock=500
1231 domain_id=-1
1232 eventq_index=0
1233 init_perf_level=0
1234 voltage_domain=system.voltage_domain
1235
1236 [system.dvfs_handler]
1237 type=DVFSHandler
1238 domains=
1239 enable=false
1240 eventq_index=0
1241 sys_clk_domain=system.clk_domain
1242 transition_latency=100000000
1243
1244 [system.intrctrl]
1245 type=IntrControl
1246 eventq_index=0
1247 sys=system
1248
1249 [system.iobus]
1250 type=NoncoherentBus
1251 clk_domain=system.clk_domain
1252 eventq_index=0
1253 header_cycles=1
1254 use_default_range=false
1255 width=8
1256 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1257 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1258
1259 [system.iocache]
1260 type=BaseCache
1261 children=tags
1262 addr_ranges=0:134217727
1263 assoc=8
1264 clk_domain=system.clk_domain
1265 eventq_index=0
1266 forward_snoops=false
1267 hit_latency=50
1268 is_top_level=true
1269 max_miss_count=0
1270 mshrs=20
1271 prefetch_on_access=false
1272 prefetcher=Null
1273 response_latency=50
1274 sequential_access=false
1275 size=1024
1276 system=system
1277 tags=system.iocache.tags
1278 tgts_per_mshr=12
1279 two_queue=false
1280 write_buffers=8
1281 cpu_side=system.iobus.master[25]
1282 mem_side=system.membus.slave[2]
1283
1284 [system.iocache.tags]
1285 type=LRU
1286 assoc=8
1287 block_size=64
1288 clk_domain=system.clk_domain
1289 eventq_index=0
1290 hit_latency=50
1291 sequential_access=false
1292 size=1024
1293
1294 [system.l2c]
1295 type=BaseCache
1296 children=tags
1297 addr_ranges=0:18446744073709551615
1298 assoc=8
1299 clk_domain=system.cpu_clk_domain
1300 eventq_index=0
1301 forward_snoops=true
1302 hit_latency=20
1303 is_top_level=false
1304 max_miss_count=0
1305 mshrs=20
1306 prefetch_on_access=false
1307 prefetcher=Null
1308 response_latency=20
1309 sequential_access=false
1310 size=4194304
1311 system=system
1312 tags=system.l2c.tags
1313 tgts_per_mshr=12
1314 two_queue=false
1315 write_buffers=8
1316 cpu_side=system.toL2Bus.master[0]
1317 mem_side=system.membus.slave[1]
1318
1319 [system.l2c.tags]
1320 type=LRU
1321 assoc=8
1322 block_size=64
1323 clk_domain=system.cpu_clk_domain
1324 eventq_index=0
1325 hit_latency=20
1326 sequential_access=false
1327 size=4194304
1328
1329 [system.membus]
1330 type=CoherentBus
1331 children=badaddr_responder
1332 clk_domain=system.clk_domain
1333 eventq_index=0
1334 header_cycles=1
1335 system=system
1336 use_default_range=false
1337 width=8
1338 default=system.membus.badaddr_responder.pio
1339 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
1340 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1341
1342 [system.membus.badaddr_responder]
1343 type=IsaFake
1344 clk_domain=system.clk_domain
1345 eventq_index=0
1346 fake_mem=false
1347 pio_addr=0
1348 pio_latency=100000
1349 pio_size=8
1350 ret_bad_addr=true
1351 ret_data16=65535
1352 ret_data32=4294967295
1353 ret_data64=18446744073709551615
1354 ret_data8=255
1355 system=system
1356 update_data=false
1357 warn_access=warn
1358 pio=system.membus.default
1359
1360 [system.physmem]
1361 type=DRAMCtrl
1362 activation_limit=4
1363 addr_mapping=RoRaBaChCo
1364 banks_per_rank=8
1365 burst_length=8
1366 channels=1
1367 clk_domain=system.clk_domain
1368 conf_table_reported=true
1369 device_bus_width=8
1370 device_rowbuffer_size=1024
1371 devices_per_rank=8
1372 eventq_index=0
1373 in_addr_map=true
1374 max_accesses_per_row=16
1375 mem_sched_policy=frfcfs
1376 min_writes_per_switch=16
1377 null=false
1378 page_policy=open_adaptive
1379 range=0:134217727
1380 ranks_per_channel=2
1381 read_buffer_size=32
1382 static_backend_latency=10000
1383 static_frontend_latency=10000
1384 tBURST=5000
1385 tCK=1250
1386 tCL=13750
1387 tRAS=35000
1388 tRCD=13750
1389 tREFI=7800000
1390 tRFC=260000
1391 tRP=13750
1392 tRRD=6000
1393 tRTP=7500
1394 tRTW=2500
1395 tWR=15000
1396 tWTR=7500
1397 tXAW=30000
1398 write_buffer_size=64
1399 write_high_thresh_perc=85
1400 write_low_thresh_perc=50
1401 port=system.membus.master[6]
1402
1403 [system.realview]
1404 type=RealView
1405 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1406 eventq_index=0
1407 intrctrl=system.intrctrl
1408 max_mem_size=268435456
1409 mem_start_addr=0
1410 pci_cfg_base=0
1411 system=system
1412
1413 [system.realview.a9scu]
1414 type=A9SCU
1415 clk_domain=system.clk_domain
1416 eventq_index=0
1417 pio_addr=520093696
1418 pio_latency=100000
1419 system=system
1420 pio=system.membus.master[4]
1421
1422 [system.realview.aaci_fake]
1423 type=AmbaFake
1424 amba_id=0
1425 clk_domain=system.clk_domain
1426 eventq_index=0
1427 ignore_access=false
1428 pio_addr=268451840
1429 pio_latency=100000
1430 system=system
1431 pio=system.iobus.master[21]
1432
1433 [system.realview.cf_ctrl]
1434 type=IdeController
1435 BAR0=402653184
1436 BAR0LegacyIO=true
1437 BAR0Size=16
1438 BAR1=402653440
1439 BAR1LegacyIO=true
1440 BAR1Size=1
1441 BAR2=1
1442 BAR2LegacyIO=false
1443 BAR2Size=8
1444 BAR3=1
1445 BAR3LegacyIO=false
1446 BAR3Size=4
1447 BAR4=1
1448 BAR4LegacyIO=false
1449 BAR4Size=16
1450 BAR5=1
1451 BAR5LegacyIO=false
1452 BAR5Size=0
1453 BIST=0
1454 CacheLineSize=0
1455 CapabilityPtr=0
1456 CardbusCIS=0
1457 ClassCode=1
1458 Command=1
1459 DeviceID=28945
1460 ExpansionROM=0
1461 HeaderType=0
1462 InterruptLine=31
1463 InterruptPin=1
1464 LatencyTimer=0
1465 MSICAPBaseOffset=0
1466 MSICAPCapId=0
1467 MSICAPMaskBits=0
1468 MSICAPMsgAddr=0
1469 MSICAPMsgCtrl=0
1470 MSICAPMsgData=0
1471 MSICAPMsgUpperAddr=0
1472 MSICAPNextCapability=0
1473 MSICAPPendingBits=0
1474 MSIXCAPBaseOffset=0
1475 MSIXCAPCapId=0
1476 MSIXCAPNextCapability=0
1477 MSIXMsgCtrl=0
1478 MSIXPbaOffset=0
1479 MSIXTableOffset=0
1480 MaximumLatency=0
1481 MinimumGrant=0
1482 PMCAPBaseOffset=0
1483 PMCAPCapId=0
1484 PMCAPCapabilities=0
1485 PMCAPCtrlStatus=0
1486 PMCAPNextCapability=0
1487 PXCAPBaseOffset=0
1488 PXCAPCapId=0
1489 PXCAPCapabilities=0
1490 PXCAPDevCap2=0
1491 PXCAPDevCapabilities=0
1492 PXCAPDevCtrl=0
1493 PXCAPDevCtrl2=0
1494 PXCAPDevStatus=0
1495 PXCAPLinkCap=0
1496 PXCAPLinkCtrl=0
1497 PXCAPLinkStatus=0
1498 PXCAPNextCapability=0
1499 ProgIF=133
1500 Revision=0
1501 Status=640
1502 SubClassCode=1
1503 SubsystemID=0
1504 SubsystemVendorID=0
1505 VendorID=32902
1506 clk_domain=system.clk_domain
1507 config_latency=20000
1508 ctrl_offset=2
1509 disks=system.cf0
1510 eventq_index=0
1511 io_shift=1
1512 pci_bus=2
1513 pci_dev=7
1514 pci_func=0
1515 pio_latency=30000
1516 platform=system.realview
1517 system=system
1518 config=system.iobus.master[8]
1519 dma=system.iobus.slave[2]
1520 pio=system.iobus.master[7]
1521
1522 [system.realview.clcd]
1523 type=Pl111
1524 amba_id=1315089
1525 clk_domain=system.clk_domain
1526 enable_capture=true
1527 eventq_index=0
1528 gic=system.realview.gic
1529 int_num=55
1530 pio_addr=268566528
1531 pio_latency=10000
1532 pixel_clock=41667
1533 system=system
1534 vnc=system.vncserver
1535 dma=system.iobus.slave[1]
1536 pio=system.iobus.master[4]
1537
1538 [system.realview.dmac_fake]
1539 type=AmbaFake
1540 amba_id=0
1541 clk_domain=system.clk_domain
1542 eventq_index=0
1543 ignore_access=false
1544 pio_addr=268632064
1545 pio_latency=100000
1546 system=system
1547 pio=system.iobus.master[9]
1548
1549 [system.realview.flash_fake]
1550 type=IsaFake
1551 clk_domain=system.clk_domain
1552 eventq_index=0
1553 fake_mem=true
1554 pio_addr=1073741824
1555 pio_latency=100000
1556 pio_size=536870912
1557 ret_bad_addr=false
1558 ret_data16=65535
1559 ret_data32=4294967295
1560 ret_data64=18446744073709551615
1561 ret_data8=255
1562 system=system
1563 update_data=false
1564 warn_access=
1565 pio=system.iobus.master[24]
1566
1567 [system.realview.gic]
1568 type=Pl390
1569 clk_domain=system.clk_domain
1570 cpu_addr=520093952
1571 cpu_pio_delay=10000
1572 dist_addr=520097792
1573 dist_pio_delay=10000
1574 eventq_index=0
1575 int_latency=10000
1576 it_lines=128
1577 msix_addr=0
1578 platform=system.realview
1579 system=system
1580 pio=system.membus.master[2]
1581
1582 [system.realview.gpio0_fake]
1583 type=AmbaFake
1584 amba_id=0
1585 clk_domain=system.clk_domain
1586 eventq_index=0
1587 ignore_access=false
1588 pio_addr=268513280
1589 pio_latency=100000
1590 system=system
1591 pio=system.iobus.master[16]
1592
1593 [system.realview.gpio1_fake]
1594 type=AmbaFake
1595 amba_id=0
1596 clk_domain=system.clk_domain
1597 eventq_index=0
1598 ignore_access=false
1599 pio_addr=268517376
1600 pio_latency=100000
1601 system=system
1602 pio=system.iobus.master[17]
1603
1604 [system.realview.gpio2_fake]
1605 type=AmbaFake
1606 amba_id=0
1607 clk_domain=system.clk_domain
1608 eventq_index=0
1609 ignore_access=false
1610 pio_addr=268521472
1611 pio_latency=100000
1612 system=system
1613 pio=system.iobus.master[18]
1614
1615 [system.realview.kmi0]
1616 type=Pl050
1617 amba_id=1314896
1618 clk_domain=system.clk_domain
1619 eventq_index=0
1620 gic=system.realview.gic
1621 int_delay=1000000
1622 int_num=52
1623 is_mouse=false
1624 pio_addr=268460032
1625 pio_latency=100000
1626 system=system
1627 vnc=system.vncserver
1628 pio=system.iobus.master[5]
1629
1630 [system.realview.kmi1]
1631 type=Pl050
1632 amba_id=1314896
1633 clk_domain=system.clk_domain
1634 eventq_index=0
1635 gic=system.realview.gic
1636 int_delay=1000000
1637 int_num=53
1638 is_mouse=true
1639 pio_addr=268464128
1640 pio_latency=100000
1641 system=system
1642 vnc=system.vncserver
1643 pio=system.iobus.master[6]
1644
1645 [system.realview.l2x0_fake]
1646 type=IsaFake
1647 clk_domain=system.clk_domain
1648 eventq_index=0
1649 fake_mem=false
1650 pio_addr=520101888
1651 pio_latency=100000
1652 pio_size=4095
1653 ret_bad_addr=false
1654 ret_data16=65535
1655 ret_data32=4294967295
1656 ret_data64=18446744073709551615
1657 ret_data8=255
1658 system=system
1659 update_data=false
1660 warn_access=
1661 pio=system.membus.master[3]
1662
1663 [system.realview.local_cpu_timer]
1664 type=CpuLocalTimer
1665 clk_domain=system.clk_domain
1666 eventq_index=0
1667 gic=system.realview.gic
1668 int_num_timer=29
1669 int_num_watchdog=30
1670 pio_addr=520095232
1671 pio_latency=100000
1672 system=system
1673 pio=system.membus.master[5]
1674
1675 [system.realview.mmc_fake]
1676 type=AmbaFake
1677 amba_id=0
1678 clk_domain=system.clk_domain
1679 eventq_index=0
1680 ignore_access=false
1681 pio_addr=268455936
1682 pio_latency=100000
1683 system=system
1684 pio=system.iobus.master[22]
1685
1686 [system.realview.nvmem]
1687 type=SimpleMemory
1688 bandwidth=73.000000
1689 clk_domain=system.clk_domain
1690 conf_table_reported=false
1691 eventq_index=0
1692 in_addr_map=true
1693 latency=30000
1694 latency_var=0
1695 null=false
1696 range=2147483648:2214592511
1697 port=system.membus.master[1]
1698
1699 [system.realview.realview_io]
1700 type=RealViewCtrl
1701 clk_domain=system.clk_domain
1702 eventq_index=0
1703 idreg=0
1704 pio_addr=268435456
1705 pio_latency=100000
1706 proc_id0=201326592
1707 proc_id1=201327138
1708 system=system
1709 pio=system.iobus.master[1]
1710
1711 [system.realview.rtc]
1712 type=PL031
1713 amba_id=3412017
1714 clk_domain=system.clk_domain
1715 eventq_index=0
1716 gic=system.realview.gic
1717 int_delay=100000
1718 int_num=42
1719 pio_addr=268529664
1720 pio_latency=100000
1721 system=system
1722 time=Thu Jan  1 00:00:00 2009
1723 pio=system.iobus.master[23]
1724
1725 [system.realview.sci_fake]
1726 type=AmbaFake
1727 amba_id=0
1728 clk_domain=system.clk_domain
1729 eventq_index=0
1730 ignore_access=false
1731 pio_addr=268492800
1732 pio_latency=100000
1733 system=system
1734 pio=system.iobus.master[20]
1735
1736 [system.realview.smc_fake]
1737 type=AmbaFake
1738 amba_id=0
1739 clk_domain=system.clk_domain
1740 eventq_index=0
1741 ignore_access=false
1742 pio_addr=269357056
1743 pio_latency=100000
1744 system=system
1745 pio=system.iobus.master[13]
1746
1747 [system.realview.sp810_fake]
1748 type=AmbaFake
1749 amba_id=0
1750 clk_domain=system.clk_domain
1751 eventq_index=0
1752 ignore_access=true
1753 pio_addr=268439552
1754 pio_latency=100000
1755 system=system
1756 pio=system.iobus.master[14]
1757
1758 [system.realview.ssp_fake]
1759 type=AmbaFake
1760 amba_id=0
1761 clk_domain=system.clk_domain
1762 eventq_index=0
1763 ignore_access=false
1764 pio_addr=268488704
1765 pio_latency=100000
1766 system=system
1767 pio=system.iobus.master[19]
1768
1769 [system.realview.timer0]
1770 type=Sp804
1771 amba_id=1316868
1772 clk_domain=system.clk_domain
1773 clock0=1000000
1774 clock1=1000000
1775 eventq_index=0
1776 gic=system.realview.gic
1777 int_num0=36
1778 int_num1=36
1779 pio_addr=268505088
1780 pio_latency=100000
1781 system=system
1782 pio=system.iobus.master[2]
1783
1784 [system.realview.timer1]
1785 type=Sp804
1786 amba_id=1316868
1787 clk_domain=system.clk_domain
1788 clock0=1000000
1789 clock1=1000000
1790 eventq_index=0
1791 gic=system.realview.gic
1792 int_num0=37
1793 int_num1=37
1794 pio_addr=268509184
1795 pio_latency=100000
1796 system=system
1797 pio=system.iobus.master[3]
1798
1799 [system.realview.uart]
1800 type=Pl011
1801 clk_domain=system.clk_domain
1802 end_on_eot=false
1803 eventq_index=0
1804 gic=system.realview.gic
1805 int_delay=100000
1806 int_num=44
1807 pio_addr=268472320
1808 pio_latency=100000
1809 platform=system.realview
1810 system=system
1811 terminal=system.terminal
1812 pio=system.iobus.master[0]
1813
1814 [system.realview.uart1_fake]
1815 type=AmbaFake
1816 amba_id=0
1817 clk_domain=system.clk_domain
1818 eventq_index=0
1819 ignore_access=false
1820 pio_addr=268476416
1821 pio_latency=100000
1822 system=system
1823 pio=system.iobus.master[10]
1824
1825 [system.realview.uart2_fake]
1826 type=AmbaFake
1827 amba_id=0
1828 clk_domain=system.clk_domain
1829 eventq_index=0
1830 ignore_access=false
1831 pio_addr=268480512
1832 pio_latency=100000
1833 system=system
1834 pio=system.iobus.master[11]
1835
1836 [system.realview.uart3_fake]
1837 type=AmbaFake
1838 amba_id=0
1839 clk_domain=system.clk_domain
1840 eventq_index=0
1841 ignore_access=false
1842 pio_addr=268484608
1843 pio_latency=100000
1844 system=system
1845 pio=system.iobus.master[12]
1846
1847 [system.realview.watchdog_fake]
1848 type=AmbaFake
1849 amba_id=0
1850 clk_domain=system.clk_domain
1851 eventq_index=0
1852 ignore_access=false
1853 pio_addr=268500992
1854 pio_latency=100000
1855 system=system
1856 pio=system.iobus.master[15]
1857
1858 [system.terminal]
1859 type=Terminal
1860 eventq_index=0
1861 intr_control=system.intrctrl
1862 number=0
1863 output=true
1864 port=3456
1865
1866 [system.toL2Bus]
1867 type=CoherentBus
1868 clk_domain=system.cpu_clk_domain
1869 eventq_index=0
1870 header_cycles=1
1871 system=system
1872 use_default_range=false
1873 width=8
1874 master=system.l2c.cpu_side
1875 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
1876
1877 [system.vncserver]
1878 type=VncServer
1879 eventq_index=0
1880 frame_capture=false
1881 number=0
1882 port=5900
1883
1884 [system.voltage_domain]
1885 type=VoltageDomain
1886 eventq_index=0
1887 voltage=1.000000
1888