tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/dist/binaries/boot.arm
  16 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 load_addr_mask=268435455
  35 load_offset=0
  36 machine_type=RealView_PBX
  37 mem_mode=timing
  38 mem_ranges=0:134217727
  39 memories=system.physmem system.realview.nvmem
  40 multi_proc=true
  41 num_work_ids=16
  42 panic_on_oops=true
  43 panic_on_panic=true
  44 phys_addr_range_64=40
  45 readfile=tests/halt.sh
  46 reset_addr_64=0
  47 symbolfile=
  48 work_begin_ckpt_count=0
  49 work_begin_cpu_id_exit=-1
  50 work_begin_exit_count=0
  51 work_cpus_ckpt_count=0
  52 work_end_ckpt_count=0
  53 work_end_exit_count=0
  54 work_item_id=-1
  55 system_port=system.membus.slave[0]
  56
  57 [system.bridge]
  58 type=Bridge
  59 clk_domain=system.clk_domain
  60 delay=50000
  61 eventq_index=0
  62 ranges=268435456:520093695 1073741824:1610612735
  63 req_size=16
  64 resp_size=16
  65 master=system.iobus.slave[0]
  66 slave=system.membus.master[0]
  67
  68 [system.cf0]
  69 type=IdeDisk
  70 children=image
  71 delay=1000000
  72 driveID=master
  73 eventq_index=0
  74 image=system.cf0.image
  75
  76 [system.cf0.image]
  77 type=CowDiskImage
  78 children=child
  79 child=system.cf0.image.child
  80 eventq_index=0
  81 image_file=
  82 read_only=false
  83 table_size=65536
  84
  85 [system.cf0.image.child]
  86 type=RawDiskImage
  87 eventq_index=0
  88 image_file=/dist/disks/linux-arm-ael.img
  89 read_only=true
  90
  91 [system.clk_domain]
  92 type=SrcClockDomain
  93 clock=1000
  94 eventq_index=0
  95 voltage_domain=system.voltage_domain
  96
  97 [system.cpu0]
  98 type=DerivO3CPU
  99 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
 100 LFSTSize=1024
 101 LQEntries=32
 102 LSQCheckLoads=true
 103 LSQDepCheckShift=4
 104 SQEntries=32
 105 SSITSize=1024
 106 activity=0
 107 backComSize=5
 108 branchPred=system.cpu0.branchPred
 109 cachePorts=200
 110 checker=Null
 111 clk_domain=system.cpu_clk_domain
 112 commitToDecodeDelay=1
 113 commitToFetchDelay=1
 114 commitToIEWDelay=1
 115 commitToRenameDelay=1
 116 commitWidth=8
 117 cpu_id=0
 118 decodeToFetchDelay=1
 119 decodeToRenameDelay=1
 120 decodeWidth=8
 121 dispatchWidth=8
 122 do_checkpoint_insts=true
 123 do_quiesce=true
 124 do_statistics_insts=true
 125 dstage2_mmu=system.cpu0.dstage2_mmu
 126 dtb=system.cpu0.dtb
 127 eventq_index=0
 128 fetchBufferSize=64
 129 fetchToDecodeDelay=1
 130 fetchTrapLatency=1
 131 fetchWidth=8
 132 forwardComSize=5
 133 fuPool=system.cpu0.fuPool
 134 function_trace=false
 135 function_trace_start=0
 136 iewToCommitDelay=1
 137 iewToDecodeDelay=1
 138 iewToFetchDelay=1
 139 iewToRenameDelay=1
 140 interrupts=system.cpu0.interrupts
 141 isa=system.cpu0.isa
 142 issueToExecuteDelay=1
 143 issueWidth=8
 144 istage2_mmu=system.cpu0.istage2_mmu
 145 itb=system.cpu0.itb
 146 max_insts_all_threads=0
 147 max_insts_any_thread=0
 148 max_loads_all_threads=0
 149 max_loads_any_thread=0
 150 needsTSO=false
 151 numIQEntries=64
 152 numPhysCCRegs=0
 153 numPhysFloatRegs=256
 154 numPhysIntRegs=256
 155 numROBEntries=192
 156 numRobs=1
 157 numThreads=1
 158 profile=0
 159 progress_interval=0
 160 renameToDecodeDelay=1
 161 renameToFetchDelay=1
 162 renameToIEWDelay=2
 163 renameToROBDelay=1
 164 renameWidth=8
 165 simpoint_start_insts=
 166 smtCommitPolicy=RoundRobin
 167 smtFetchPolicy=SingleThread
 168 smtIQPolicy=Partitioned
 169 smtIQThreshold=100
 170 smtLSQPolicy=Partitioned
 171 smtLSQThreshold=100
 172 smtNumFetchingThreads=1
 173 smtROBPolicy=Partitioned
 174 smtROBThreshold=100
 175 squashWidth=8
 176 store_set_clear_period=250000
 177 switched_out=false
 178 system=system
 179 tracer=system.cpu0.tracer
 180 trapLatency=13
 181 wbDepth=1
 182 wbWidth=8
 183 workload=
 184 dcache_port=system.cpu0.dcache.cpu_side
 185 icache_port=system.cpu0.icache.cpu_side
 186
 187 [system.cpu0.branchPred]
 188 type=BranchPredictor
 189 BTBEntries=4096
 190 BTBTagSize=16
 191 RASSize=16
 192 choiceCtrBits=2
 193 choicePredictorSize=8192
 194 eventq_index=0
 195 globalCtrBits=2
 196 globalPredictorSize=8192
 197 instShiftAmt=2
 198 localCtrBits=2
 199 localHistoryTableSize=2048
 200 localPredictorSize=2048
 201 numThreads=1
 202 predType=tournament
 203
 204 [system.cpu0.dcache]
 205 type=BaseCache
 206 children=tags
 207 addr_ranges=0:18446744073709551615
 208 assoc=4
 209 clk_domain=system.cpu_clk_domain
 210 eventq_index=0
 211 forward_snoops=true
 212 hit_latency=2
 213 is_top_level=true
 214 max_miss_count=0
 215 mshrs=4
 216 prefetch_on_access=false
 217 prefetcher=Null
 218 response_latency=2
 219 sequential_access=false
 220 size=32768
 221 system=system
 222 tags=system.cpu0.dcache.tags
 223 tgts_per_mshr=20
 224 two_queue=false
 225 write_buffers=8
 226 cpu_side=system.cpu0.dcache_port
 227 mem_side=system.toL2Bus.slave[1]
 228
 229 [system.cpu0.dcache.tags]
 230 type=LRU
 231 assoc=4
 232 block_size=64
 233 clk_domain=system.cpu_clk_domain
 234 eventq_index=0
 235 hit_latency=2
 236 sequential_access=false
 237 size=32768
 238
 239 [system.cpu0.dstage2_mmu]
 240 type=ArmStage2MMU
 241 children=stage2_tlb
 242 eventq_index=0
 243 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 244 tlb=system.cpu0.dtb
 245
 246 [system.cpu0.dstage2_mmu.stage2_tlb]
 247 type=ArmTLB
 248 children=walker
 249 eventq_index=0
 250 is_stage2=true
 251 size=32
 252 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 253
 254 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 255 type=ArmTableWalker
 256 clk_domain=system.cpu_clk_domain
 257 eventq_index=0
 258 is_stage2=true
 259 num_squash_per_cycle=2
 260 sys=system
 261 port=system.toL2Bus.slave[5]
 262
 263 [system.cpu0.dtb]
 264 type=ArmTLB
 265 children=walker
 266 eventq_index=0
 267 is_stage2=false
 268 size=64
 269 walker=system.cpu0.dtb.walker
 270
 271 [system.cpu0.dtb.walker]
 272 type=ArmTableWalker
 273 clk_domain=system.cpu_clk_domain
 274 eventq_index=0
 275 is_stage2=false
 276 num_squash_per_cycle=2
 277 sys=system
 278 port=system.toL2Bus.slave[3]
 279
 280 [system.cpu0.fuPool]
 281 type=FUPool
 282 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 283 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
 284 eventq_index=0
 285
 286 [system.cpu0.fuPool.FUList0]
 287 type=FUDesc
 288 children=opList
 289 count=6
 290 eventq_index=0
 291 opList=system.cpu0.fuPool.FUList0.opList
 292
 293 [system.cpu0.fuPool.FUList0.opList]
 294 type=OpDesc
 295 eventq_index=0
 296 issueLat=1
 297 opClass=IntAlu
 298 opLat=1
 299
 300 [system.cpu0.fuPool.FUList1]
 301 type=FUDesc
 302 children=opList0 opList1
 303 count=2
 304 eventq_index=0
 305 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 306
 307 [system.cpu0.fuPool.FUList1.opList0]
 308 type=OpDesc
 309 eventq_index=0
 310 issueLat=1
 311 opClass=IntMult
 312 opLat=3
 313
 314 [system.cpu0.fuPool.FUList1.opList1]
 315 type=OpDesc
 316 eventq_index=0
 317 issueLat=19
 318 opClass=IntDiv
 319 opLat=20
 320
 321 [system.cpu0.fuPool.FUList2]
 322 type=FUDesc
 323 children=opList0 opList1 opList2
 324 count=4
 325 eventq_index=0
 326 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
 327
 328 [system.cpu0.fuPool.FUList2.opList0]
 329 type=OpDesc
 330 eventq_index=0
 331 issueLat=1
 332 opClass=FloatAdd
 333 opLat=2
 334
 335 [system.cpu0.fuPool.FUList2.opList1]
 336 type=OpDesc
 337 eventq_index=0
 338 issueLat=1
 339 opClass=FloatCmp
 340 opLat=2
 341
 342 [system.cpu0.fuPool.FUList2.opList2]
 343 type=OpDesc
 344 eventq_index=0
 345 issueLat=1
 346 opClass=FloatCvt
 347 opLat=2
 348
 349 [system.cpu0.fuPool.FUList3]
 350 type=FUDesc
 351 children=opList0 opList1 opList2
 352 count=2
 353 eventq_index=0
 354 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
 355
 356 [system.cpu0.fuPool.FUList3.opList0]
 357 type=OpDesc
 358 eventq_index=0
 359 issueLat=1
 360 opClass=FloatMult
 361 opLat=4
 362
 363 [system.cpu0.fuPool.FUList3.opList1]
 364 type=OpDesc
 365 eventq_index=0
 366 issueLat=12
 367 opClass=FloatDiv
 368 opLat=12
 369
 370 [system.cpu0.fuPool.FUList3.opList2]
 371 type=OpDesc
 372 eventq_index=0
 373 issueLat=24
 374 opClass=FloatSqrt
 375 opLat=24
 376
 377 [system.cpu0.fuPool.FUList4]
 378 type=FUDesc
 379 children=opList
 380 count=0
 381 eventq_index=0
 382 opList=system.cpu0.fuPool.FUList4.opList
 383
 384 [system.cpu0.fuPool.FUList4.opList]
 385 type=OpDesc
 386 eventq_index=0
 387 issueLat=1
 388 opClass=MemRead
 389 opLat=1
 390
 391 [system.cpu0.fuPool.FUList5]
 392 type=FUDesc
 393 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 394 count=4
 395 eventq_index=0
 396 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
 397
 398 [system.cpu0.fuPool.FUList5.opList00]
 399 type=OpDesc
 400 eventq_index=0
 401 issueLat=1
 402 opClass=SimdAdd
 403 opLat=1
 404
 405 [system.cpu0.fuPool.FUList5.opList01]
 406 type=OpDesc
 407 eventq_index=0
 408 issueLat=1
 409 opClass=SimdAddAcc
 410 opLat=1
 411
 412 [system.cpu0.fuPool.FUList5.opList02]
 413 type=OpDesc
 414 eventq_index=0
 415 issueLat=1
 416 opClass=SimdAlu
 417 opLat=1
 418
 419 [system.cpu0.fuPool.FUList5.opList03]
 420 type=OpDesc
 421 eventq_index=0
 422 issueLat=1
 423 opClass=SimdCmp
 424 opLat=1
 425
 426 [system.cpu0.fuPool.FUList5.opList04]
 427 type=OpDesc
 428 eventq_index=0
 429 issueLat=1
 430 opClass=SimdCvt
 431 opLat=1
 432
 433 [system.cpu0.fuPool.FUList5.opList05]
 434 type=OpDesc
 435 eventq_index=0
 436 issueLat=1
 437 opClass=SimdMisc
 438 opLat=1
 439
 440 [system.cpu0.fuPool.FUList5.opList06]
 441 type=OpDesc
 442 eventq_index=0
 443 issueLat=1
 444 opClass=SimdMult
 445 opLat=1
 446
 447 [system.cpu0.fuPool.FUList5.opList07]
 448 type=OpDesc
 449 eventq_index=0
 450 issueLat=1
 451 opClass=SimdMultAcc
 452 opLat=1
 453
 454 [system.cpu0.fuPool.FUList5.opList08]
 455 type=OpDesc
 456 eventq_index=0
 457 issueLat=1
 458 opClass=SimdShift
 459 opLat=1
 460
 461 [system.cpu0.fuPool.FUList5.opList09]
 462 type=OpDesc
 463 eventq_index=0
 464 issueLat=1
 465 opClass=SimdShiftAcc
 466 opLat=1
 467
 468 [system.cpu0.fuPool.FUList5.opList10]
 469 type=OpDesc
 470 eventq_index=0
 471 issueLat=1
 472 opClass=SimdSqrt
 473 opLat=1
 474
 475 [system.cpu0.fuPool.FUList5.opList11]
 476 type=OpDesc
 477 eventq_index=0
 478 issueLat=1
 479 opClass=SimdFloatAdd
 480 opLat=1
 481
 482 [system.cpu0.fuPool.FUList5.opList12]
 483 type=OpDesc
 484 eventq_index=0
 485 issueLat=1
 486 opClass=SimdFloatAlu
 487 opLat=1
 488
 489 [system.cpu0.fuPool.FUList5.opList13]
 490 type=OpDesc
 491 eventq_index=0
 492 issueLat=1
 493 opClass=SimdFloatCmp
 494 opLat=1
 495
 496 [system.cpu0.fuPool.FUList5.opList14]
 497 type=OpDesc
 498 eventq_index=0
 499 issueLat=1
 500 opClass=SimdFloatCvt
 501 opLat=1
 502
 503 [system.cpu0.fuPool.FUList5.opList15]
 504 type=OpDesc
 505 eventq_index=0
 506 issueLat=1
 507 opClass=SimdFloatDiv
 508 opLat=1
 509
 510 [system.cpu0.fuPool.FUList5.opList16]
 511 type=OpDesc
 512 eventq_index=0
 513 issueLat=1
 514 opClass=SimdFloatMisc
 515 opLat=1
 516
 517 [system.cpu0.fuPool.FUList5.opList17]
 518 type=OpDesc
 519 eventq_index=0
 520 issueLat=1
 521 opClass=SimdFloatMult
 522 opLat=1
 523
 524 [system.cpu0.fuPool.FUList5.opList18]
 525 type=OpDesc
 526 eventq_index=0
 527 issueLat=1
 528 opClass=SimdFloatMultAcc
 529 opLat=1
 530
 531 [system.cpu0.fuPool.FUList5.opList19]
 532 type=OpDesc
 533 eventq_index=0
 534 issueLat=1
 535 opClass=SimdFloatSqrt
 536 opLat=1
 537
 538 [system.cpu0.fuPool.FUList6]
 539 type=FUDesc
 540 children=opList
 541 count=0
 542 eventq_index=0
 543 opList=system.cpu0.fuPool.FUList6.opList
 544
 545 [system.cpu0.fuPool.FUList6.opList]
 546 type=OpDesc
 547 eventq_index=0
 548 issueLat=1
 549 opClass=MemWrite
 550 opLat=1
 551
 552 [system.cpu0.fuPool.FUList7]
 553 type=FUDesc
 554 children=opList0 opList1
 555 count=4
 556 eventq_index=0
 557 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 558
 559 [system.cpu0.fuPool.FUList7.opList0]
 560 type=OpDesc
 561 eventq_index=0
 562 issueLat=1
 563 opClass=MemRead
 564 opLat=1
 565
 566 [system.cpu0.fuPool.FUList7.opList1]
 567 type=OpDesc
 568 eventq_index=0
 569 issueLat=1
 570 opClass=MemWrite
 571 opLat=1
 572
 573 [system.cpu0.fuPool.FUList8]
 574 type=FUDesc
 575 children=opList
 576 count=1
 577 eventq_index=0
 578 opList=system.cpu0.fuPool.FUList8.opList
 579
 580 [system.cpu0.fuPool.FUList8.opList]
 581 type=OpDesc
 582 eventq_index=0
 583 issueLat=3
 584 opClass=IprAccess
 585 opLat=3
 586
 587 [system.cpu0.icache]
 588 type=BaseCache
 589 children=tags
 590 addr_ranges=0:18446744073709551615
 591 assoc=1
 592 clk_domain=system.cpu_clk_domain
 593 eventq_index=0
 594 forward_snoops=true
 595 hit_latency=2
 596 is_top_level=true
 597 max_miss_count=0
 598 mshrs=4
 599 prefetch_on_access=false
 600 prefetcher=Null
 601 response_latency=2
 602 sequential_access=false
 603 size=32768
 604 system=system
 605 tags=system.cpu0.icache.tags
 606 tgts_per_mshr=20
 607 two_queue=false
 608 write_buffers=8
 609 cpu_side=system.cpu0.icache_port
 610 mem_side=system.toL2Bus.slave[0]
 611
 612 [system.cpu0.icache.tags]
 613 type=LRU
 614 assoc=1
 615 block_size=64
 616 clk_domain=system.cpu_clk_domain
 617 eventq_index=0
 618 hit_latency=2
 619 sequential_access=false
 620 size=32768
 621
 622 [system.cpu0.interrupts]
 623 type=ArmInterrupts
 624 eventq_index=0
 625
 626 [system.cpu0.isa]
 627 type=ArmISA
 628 eventq_index=0
 629 fpsid=1090793632
 630 id_aa64afr0_el1=0
 631 id_aa64afr1_el1=0
 632 id_aa64dfr0_el1=1052678
 633 id_aa64dfr1_el1=0
 634 id_aa64isar0_el1=0
 635 id_aa64isar1_el1=0
 636 id_aa64mmfr0_el1=15728642
 637 id_aa64mmfr1_el1=0
 638 id_aa64pfr0_el1=17
 639 id_aa64pfr1_el1=0
 640 id_isar0=34607377
 641 id_isar1=34677009
 642 id_isar2=555950401
 643 id_isar3=17899825
 644 id_isar4=268501314
 645 id_isar5=0
 646 id_mmfr0=270536963
 647 id_mmfr1=0
 648 id_mmfr2=19070976
 649 id_mmfr3=34611729
 650 id_pfr0=49
 651 id_pfr1=4113
 652 midr=1091551472
 653 system=system
 654
 655 [system.cpu0.istage2_mmu]
 656 type=ArmStage2MMU
 657 children=stage2_tlb
 658 eventq_index=0
 659 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 660 tlb=system.cpu0.itb
 661
 662 [system.cpu0.istage2_mmu.stage2_tlb]
 663 type=ArmTLB
 664 children=walker
 665 eventq_index=0
 666 is_stage2=true
 667 size=32
 668 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 669
 670 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 671 type=ArmTableWalker
 672 clk_domain=system.cpu_clk_domain
 673 eventq_index=0
 674 is_stage2=true
 675 num_squash_per_cycle=2
 676 sys=system
 677 port=system.toL2Bus.slave[4]
 678
 679 [system.cpu0.itb]
 680 type=ArmTLB
 681 children=walker
 682 eventq_index=0
 683 is_stage2=false
 684 size=64
 685 walker=system.cpu0.itb.walker
 686
 687 [system.cpu0.itb.walker]
 688 type=ArmTableWalker
 689 clk_domain=system.cpu_clk_domain
 690 eventq_index=0
 691 is_stage2=false
 692 num_squash_per_cycle=2
 693 sys=system
 694 port=system.toL2Bus.slave[2]
 695
 696 [system.cpu0.tracer]
 697 type=ExeTracer
 698 eventq_index=0
 699
 700 [system.cpu1]
 701 type=DerivO3CPU
 702 children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
 703 LFSTSize=1024
 704 LQEntries=32
 705 LSQCheckLoads=true
 706 LSQDepCheckShift=4
 707 SQEntries=32
 708 SSITSize=1024
 709 activity=0
 710 backComSize=5
 711 branchPred=system.cpu1.branchPred
 712 cachePorts=200
 713 checker=Null
 714 clk_domain=system.cpu_clk_domain
 715 commitToDecodeDelay=1
 716 commitToFetchDelay=1
 717 commitToIEWDelay=1
 718 commitToRenameDelay=1
 719 commitWidth=8
 720 cpu_id=0
 721 decodeToFetchDelay=1
 722 decodeToRenameDelay=1
 723 decodeWidth=8
 724 dispatchWidth=8
 725 do_checkpoint_insts=true
 726 do_quiesce=true
 727 do_statistics_insts=true
 728 dstage2_mmu=system.cpu1.dstage2_mmu
 729 dtb=system.cpu1.dtb
 730 eventq_index=0
 731 fetchBufferSize=64
 732 fetchToDecodeDelay=1
 733 fetchTrapLatency=1
 734 fetchWidth=8
 735 forwardComSize=5
 736 fuPool=system.cpu1.fuPool
 737 function_trace=false
 738 function_trace_start=0
 739 iewToCommitDelay=1
 740 iewToDecodeDelay=1
 741 iewToFetchDelay=1
 742 iewToRenameDelay=1
 743 interrupts=Null
 744 isa=system.cpu1.isa
 745 issueToExecuteDelay=1
 746 issueWidth=8
 747 istage2_mmu=system.cpu1.istage2_mmu
 748 itb=system.cpu1.itb
 749 max_insts_all_threads=0
 750 max_insts_any_thread=0
 751 max_loads_all_threads=0
 752 max_loads_any_thread=0
 753 needsTSO=false
 754 numIQEntries=64
 755 numPhysCCRegs=0
 756 numPhysFloatRegs=256
 757 numPhysIntRegs=256
 758 numROBEntries=192
 759 numRobs=1
 760 numThreads=1
 761 profile=0
 762 progress_interval=0
 763 renameToDecodeDelay=1
 764 renameToFetchDelay=1
 765 renameToIEWDelay=2
 766 renameToROBDelay=1
 767 renameWidth=8
 768 simpoint_start_insts=
 769 smtCommitPolicy=RoundRobin
 770 smtFetchPolicy=SingleThread
 771 smtIQPolicy=Partitioned
 772 smtIQThreshold=100
 773 smtLSQPolicy=Partitioned
 774 smtLSQThreshold=100
 775 smtNumFetchingThreads=1
 776 smtROBPolicy=Partitioned
 777 smtROBThreshold=100
 778 squashWidth=8
 779 store_set_clear_period=250000
 780 switched_out=true
 781 system=system
 782 tracer=system.cpu1.tracer
 783 trapLatency=13
 784 wbDepth=1
 785 wbWidth=8
 786 workload=
 787
 788 [system.cpu1.branchPred]
 789 type=BranchPredictor
 790 BTBEntries=4096
 791 BTBTagSize=16
 792 RASSize=16
 793 choiceCtrBits=2
 794 choicePredictorSize=8192
 795 eventq_index=0
 796 globalCtrBits=2
 797 globalPredictorSize=8192
 798 instShiftAmt=2
 799 localCtrBits=2
 800 localHistoryTableSize=2048
 801 localPredictorSize=2048
 802 numThreads=1
 803 predType=tournament
 804
 805 [system.cpu1.dstage2_mmu]
 806 type=ArmStage2MMU
 807 children=stage2_tlb
 808 eventq_index=0
 809 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
 810 tlb=system.cpu1.dtb
 811
 812 [system.cpu1.dstage2_mmu.stage2_tlb]
 813 type=ArmTLB
 814 children=walker
 815 eventq_index=0
 816 is_stage2=true
 817 size=32
 818 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
 819
 820 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
 821 type=ArmTableWalker
 822 clk_domain=system.cpu_clk_domain
 823 eventq_index=0
 824 is_stage2=true
 825 num_squash_per_cycle=2
 826 sys=system
 827
 828 [system.cpu1.dtb]
 829 type=ArmTLB
 830 children=walker
 831 eventq_index=0
 832 is_stage2=false
 833 size=64
 834 walker=system.cpu1.dtb.walker
 835
 836 [system.cpu1.dtb.walker]
 837 type=ArmTableWalker
 838 clk_domain=system.cpu_clk_domain
 839 eventq_index=0
 840 is_stage2=false
 841 num_squash_per_cycle=2
 842 sys=system
 843
 844 [system.cpu1.fuPool]
 845 type=FUPool
 846 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 847 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
 848 eventq_index=0
 849
 850 [system.cpu1.fuPool.FUList0]
 851 type=FUDesc
 852 children=opList
 853 count=6
 854 eventq_index=0
 855 opList=system.cpu1.fuPool.FUList0.opList
 856
 857 [system.cpu1.fuPool.FUList0.opList]
 858 type=OpDesc
 859 eventq_index=0
 860 issueLat=1
 861 opClass=IntAlu
 862 opLat=1
 863
 864 [system.cpu1.fuPool.FUList1]
 865 type=FUDesc
 866 children=opList0 opList1
 867 count=2
 868 eventq_index=0
 869 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 870
 871 [system.cpu1.fuPool.FUList1.opList0]
 872 type=OpDesc
 873 eventq_index=0
 874 issueLat=1
 875 opClass=IntMult
 876 opLat=3
 877
 878 [system.cpu1.fuPool.FUList1.opList1]
 879 type=OpDesc
 880 eventq_index=0
 881 issueLat=19
 882 opClass=IntDiv
 883 opLat=20
 884
 885 [system.cpu1.fuPool.FUList2]
 886 type=FUDesc
 887 children=opList0 opList1 opList2
 888 count=4
 889 eventq_index=0
 890 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
 891
 892 [system.cpu1.fuPool.FUList2.opList0]
 893 type=OpDesc
 894 eventq_index=0
 895 issueLat=1
 896 opClass=FloatAdd
 897 opLat=2
 898
 899 [system.cpu1.fuPool.FUList2.opList1]
 900 type=OpDesc
 901 eventq_index=0
 902 issueLat=1
 903 opClass=FloatCmp
 904 opLat=2
 905
 906 [system.cpu1.fuPool.FUList2.opList2]
 907 type=OpDesc
 908 eventq_index=0
 909 issueLat=1
 910 opClass=FloatCvt
 911 opLat=2
 912
 913 [system.cpu1.fuPool.FUList3]
 914 type=FUDesc
 915 children=opList0 opList1 opList2
 916 count=2
 917 eventq_index=0
 918 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
 919
 920 [system.cpu1.fuPool.FUList3.opList0]
 921 type=OpDesc
 922 eventq_index=0
 923 issueLat=1
 924 opClass=FloatMult
 925 opLat=4
 926
 927 [system.cpu1.fuPool.FUList3.opList1]
 928 type=OpDesc
 929 eventq_index=0
 930 issueLat=12
 931 opClass=FloatDiv
 932 opLat=12
 933
 934 [system.cpu1.fuPool.FUList3.opList2]
 935 type=OpDesc
 936 eventq_index=0
 937 issueLat=24
 938 opClass=FloatSqrt
 939 opLat=24
 940
 941 [system.cpu1.fuPool.FUList4]
 942 type=FUDesc
 943 children=opList
 944 count=0
 945 eventq_index=0
 946 opList=system.cpu1.fuPool.FUList4.opList
 947
 948 [system.cpu1.fuPool.FUList4.opList]
 949 type=OpDesc
 950 eventq_index=0
 951 issueLat=1
 952 opClass=MemRead
 953 opLat=1
 954
 955 [system.cpu1.fuPool.FUList5]
 956 type=FUDesc
 957 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 958 count=4
 959 eventq_index=0
 960 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
 961
 962 [system.cpu1.fuPool.FUList5.opList00]
 963 type=OpDesc
 964 eventq_index=0
 965 issueLat=1
 966 opClass=SimdAdd
 967 opLat=1
 968
 969 [system.cpu1.fuPool.FUList5.opList01]
 970 type=OpDesc
 971 eventq_index=0
 972 issueLat=1
 973 opClass=SimdAddAcc
 974 opLat=1
 975
 976 [system.cpu1.fuPool.FUList5.opList02]
 977 type=OpDesc
 978 eventq_index=0
 979 issueLat=1
 980 opClass=SimdAlu
 981 opLat=1
 982
 983 [system.cpu1.fuPool.FUList5.opList03]
 984 type=OpDesc
 985 eventq_index=0
 986 issueLat=1
 987 opClass=SimdCmp
 988 opLat=1
 989
 990 [system.cpu1.fuPool.FUList5.opList04]
 991 type=OpDesc
 992 eventq_index=0
 993 issueLat=1
 994 opClass=SimdCvt
 995 opLat=1
 996
 997 [system.cpu1.fuPool.FUList5.opList05]
 998 type=OpDesc
 999 eventq_index=0
1000 issueLat=1
1001 opClass=SimdMisc
1002 opLat=1
1003
1004 [system.cpu1.fuPool.FUList5.opList06]
1005 type=OpDesc
1006 eventq_index=0
1007 issueLat=1
1008 opClass=SimdMult
1009 opLat=1
1010
1011 [system.cpu1.fuPool.FUList5.opList07]
1012 type=OpDesc
1013 eventq_index=0
1014 issueLat=1
1015 opClass=SimdMultAcc
1016 opLat=1
1017
1018 [system.cpu1.fuPool.FUList5.opList08]
1019 type=OpDesc
1020 eventq_index=0
1021 issueLat=1
1022 opClass=SimdShift
1023 opLat=1
1024
1025 [system.cpu1.fuPool.FUList5.opList09]
1026 type=OpDesc
1027 eventq_index=0
1028 issueLat=1
1029 opClass=SimdShiftAcc
1030 opLat=1
1031
1032 [system.cpu1.fuPool.FUList5.opList10]
1033 type=OpDesc
1034 eventq_index=0
1035 issueLat=1
1036 opClass=SimdSqrt
1037 opLat=1
1038
1039 [system.cpu1.fuPool.FUList5.opList11]
1040 type=OpDesc
1041 eventq_index=0
1042 issueLat=1
1043 opClass=SimdFloatAdd
1044 opLat=1
1045
1046 [system.cpu1.fuPool.FUList5.opList12]
1047 type=OpDesc
1048 eventq_index=0
1049 issueLat=1
1050 opClass=SimdFloatAlu
1051 opLat=1
1052
1053 [system.cpu1.fuPool.FUList5.opList13]
1054 type=OpDesc
1055 eventq_index=0
1056 issueLat=1
1057 opClass=SimdFloatCmp
1058 opLat=1
1059
1060 [system.cpu1.fuPool.FUList5.opList14]
1061 type=OpDesc
1062 eventq_index=0
1063 issueLat=1
1064 opClass=SimdFloatCvt
1065 opLat=1
1066
1067 [system.cpu1.fuPool.FUList5.opList15]
1068 type=OpDesc
1069 eventq_index=0
1070 issueLat=1
1071 opClass=SimdFloatDiv
1072 opLat=1
1073
1074 [system.cpu1.fuPool.FUList5.opList16]
1075 type=OpDesc
1076 eventq_index=0
1077 issueLat=1
1078 opClass=SimdFloatMisc
1079 opLat=1
1080
1081 [system.cpu1.fuPool.FUList5.opList17]
1082 type=OpDesc
1083 eventq_index=0
1084 issueLat=1
1085 opClass=SimdFloatMult
1086 opLat=1
1087
1088 [system.cpu1.fuPool.FUList5.opList18]
1089 type=OpDesc
1090 eventq_index=0
1091 issueLat=1
1092 opClass=SimdFloatMultAcc
1093 opLat=1
1094
1095 [system.cpu1.fuPool.FUList5.opList19]
1096 type=OpDesc
1097 eventq_index=0
1098 issueLat=1
1099 opClass=SimdFloatSqrt
1100 opLat=1
1101
1102 [system.cpu1.fuPool.FUList6]
1103 type=FUDesc
1104 children=opList
1105 count=0
1106 eventq_index=0
1107 opList=system.cpu1.fuPool.FUList6.opList
1108
1109 [system.cpu1.fuPool.FUList6.opList]
1110 type=OpDesc
1111 eventq_index=0
1112 issueLat=1
1113 opClass=MemWrite
1114 opLat=1
1115
1116 [system.cpu1.fuPool.FUList7]
1117 type=FUDesc
1118 children=opList0 opList1
1119 count=4
1120 eventq_index=0
1121 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
1122
1123 [system.cpu1.fuPool.FUList7.opList0]
1124 type=OpDesc
1125 eventq_index=0
1126 issueLat=1
1127 opClass=MemRead
1128 opLat=1
1129
1130 [system.cpu1.fuPool.FUList7.opList1]
1131 type=OpDesc
1132 eventq_index=0
1133 issueLat=1
1134 opClass=MemWrite
1135 opLat=1
1136
1137 [system.cpu1.fuPool.FUList8]
1138 type=FUDesc
1139 children=opList
1140 count=1
1141 eventq_index=0
1142 opList=system.cpu1.fuPool.FUList8.opList
1143
1144 [system.cpu1.fuPool.FUList8.opList]
1145 type=OpDesc
1146 eventq_index=0
1147 issueLat=3
1148 opClass=IprAccess
1149 opLat=3
1150
1151 [system.cpu1.isa]
1152 type=ArmISA
1153 eventq_index=0
1154 fpsid=1090793632
1155 id_aa64afr0_el1=0
1156 id_aa64afr1_el1=0
1157 id_aa64dfr0_el1=1052678
1158 id_aa64dfr1_el1=0
1159 id_aa64isar0_el1=0
1160 id_aa64isar1_el1=0
1161 id_aa64mmfr0_el1=15728642
1162 id_aa64mmfr1_el1=0
1163 id_aa64pfr0_el1=17
1164 id_aa64pfr1_el1=0
1165 id_isar0=34607377
1166 id_isar1=34677009
1167 id_isar2=555950401
1168 id_isar3=17899825
1169 id_isar4=268501314
1170 id_isar5=0
1171 id_mmfr0=270536963
1172 id_mmfr1=0
1173 id_mmfr2=19070976
1174 id_mmfr3=34611729
1175 id_pfr0=49
1176 id_pfr1=4113
1177 midr=1091551472
1178 system=system
1179
1180 [system.cpu1.istage2_mmu]
1181 type=ArmStage2MMU
1182 children=stage2_tlb
1183 eventq_index=0
1184 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1185 tlb=system.cpu1.itb
1186
1187 [system.cpu1.istage2_mmu.stage2_tlb]
1188 type=ArmTLB
1189 children=walker
1190 eventq_index=0
1191 is_stage2=true
1192 size=32
1193 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1194
1195 [system.cpu1.istage2_mmu.stage2_tlb.walker]
1196 type=ArmTableWalker
1197 clk_domain=system.cpu_clk_domain
1198 eventq_index=0
1199 is_stage2=true
1200 num_squash_per_cycle=2
1201 sys=system
1202
1203 [system.cpu1.itb]
1204 type=ArmTLB
1205 children=walker
1206 eventq_index=0
1207 is_stage2=false
1208 size=64
1209 walker=system.cpu1.itb.walker
1210
1211 [system.cpu1.itb.walker]
1212 type=ArmTableWalker
1213 clk_domain=system.cpu_clk_domain
1214 eventq_index=0
1215 is_stage2=false
1216 num_squash_per_cycle=2
1217 sys=system
1218
1219 [system.cpu1.tracer]
1220 type=ExeTracer
1221 eventq_index=0
1222
1223 [system.cpu_clk_domain]
1224 type=SrcClockDomain
1225 clock=500
1226 eventq_index=0
1227 voltage_domain=system.voltage_domain
1228
1229 [system.intrctrl]
1230 type=IntrControl
1231 eventq_index=0
1232 sys=system
1233
1234 [system.iobus]
1235 type=NoncoherentBus
1236 clk_domain=system.clk_domain
1237 eventq_index=0
1238 header_cycles=1
1239 use_default_range=false
1240 width=8
1241 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1242 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1243
1244 [system.iocache]
1245 type=BaseCache
1246 children=tags
1247 addr_ranges=0:134217727
1248 assoc=8
1249 clk_domain=system.clk_domain
1250 eventq_index=0
1251 forward_snoops=false
1252 hit_latency=50
1253 is_top_level=true
1254 max_miss_count=0
1255 mshrs=20
1256 prefetch_on_access=false
1257 prefetcher=Null
1258 response_latency=50
1259 sequential_access=false
1260 size=1024
1261 system=system
1262 tags=system.iocache.tags
1263 tgts_per_mshr=12
1264 two_queue=false
1265 write_buffers=8
1266 cpu_side=system.iobus.master[25]
1267 mem_side=system.membus.slave[2]
1268
1269 [system.iocache.tags]
1270 type=LRU
1271 assoc=8
1272 block_size=64
1273 clk_domain=system.clk_domain
1274 eventq_index=0
1275 hit_latency=50
1276 sequential_access=false
1277 size=1024
1278
1279 [system.l2c]
1280 type=BaseCache
1281 children=tags
1282 addr_ranges=0:18446744073709551615
1283 assoc=8
1284 clk_domain=system.cpu_clk_domain
1285 eventq_index=0
1286 forward_snoops=true
1287 hit_latency=20
1288 is_top_level=false
1289 max_miss_count=0
1290 mshrs=20
1291 prefetch_on_access=false
1292 prefetcher=Null
1293 response_latency=20
1294 sequential_access=false
1295 size=4194304
1296 system=system
1297 tags=system.l2c.tags
1298 tgts_per_mshr=12
1299 two_queue=false
1300 write_buffers=8
1301 cpu_side=system.toL2Bus.master[0]
1302 mem_side=system.membus.slave[1]
1303
1304 [system.l2c.tags]
1305 type=LRU
1306 assoc=8
1307 block_size=64
1308 clk_domain=system.cpu_clk_domain
1309 eventq_index=0
1310 hit_latency=20
1311 sequential_access=false
1312 size=4194304
1313
1314 [system.membus]
1315 type=CoherentBus
1316 children=badaddr_responder
1317 clk_domain=system.clk_domain
1318 eventq_index=0
1319 header_cycles=1
1320 system=system
1321 use_default_range=false
1322 width=8
1323 default=system.membus.badaddr_responder.pio
1324 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
1325 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1326
1327 [system.membus.badaddr_responder]
1328 type=IsaFake
1329 clk_domain=system.clk_domain
1330 eventq_index=0
1331 fake_mem=false
1332 pio_addr=0
1333 pio_latency=100000
1334 pio_size=8
1335 ret_bad_addr=true
1336 ret_data16=65535
1337 ret_data32=4294967295
1338 ret_data64=18446744073709551615
1339 ret_data8=255
1340 system=system
1341 update_data=false
1342 warn_access=warn
1343 pio=system.membus.default
1344
1345 [system.physmem]
1346 type=SimpleDRAM
1347 activation_limit=4
1348 addr_mapping=RaBaChCo
1349 banks_per_rank=8
1350 burst_length=8
1351 channels=1
1352 clk_domain=system.clk_domain
1353 conf_table_reported=true
1354 device_bus_width=8
1355 device_rowbuffer_size=1024
1356 devices_per_rank=8
1357 eventq_index=0
1358 in_addr_map=true
1359 mem_sched_policy=frfcfs
1360 null=false
1361 page_policy=open
1362 range=0:134217727
1363 ranks_per_channel=2
1364 read_buffer_size=32
1365 static_backend_latency=10000
1366 static_frontend_latency=10000
1367 tBURST=5000
1368 tCL=13750
1369 tRAS=35000
1370 tRCD=13750
1371 tREFI=7800000
1372 tRFC=300000
1373 tRP=13750
1374 tRRD=6250
1375 tWTR=7500
1376 tXAW=40000
1377 write_buffer_size=32
1378 write_high_thresh_perc=70
1379 write_low_thresh_perc=0
1380 port=system.membus.master[6]
1381
1382 [system.realview]
1383 type=RealView
1384 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1385 eventq_index=0
1386 intrctrl=system.intrctrl
1387 max_mem_size=268435456
1388 mem_start_addr=0
1389 pci_cfg_base=0
1390 system=system
1391
1392 [system.realview.a9scu]
1393 type=A9SCU
1394 clk_domain=system.clk_domain
1395 eventq_index=0
1396 pio_addr=520093696
1397 pio_latency=100000
1398 system=system
1399 pio=system.membus.master[4]
1400
1401 [system.realview.aaci_fake]
1402 type=AmbaFake
1403 amba_id=0
1404 clk_domain=system.clk_domain
1405 eventq_index=0
1406 ignore_access=false
1407 pio_addr=268451840
1408 pio_latency=100000
1409 system=system
1410 pio=system.iobus.master[21]
1411
1412 [system.realview.cf_ctrl]
1413 type=IdeController
1414 BAR0=402653184
1415 BAR0LegacyIO=true
1416 BAR0Size=16
1417 BAR1=402653440
1418 BAR1LegacyIO=true
1419 BAR1Size=1
1420 BAR2=1
1421 BAR2LegacyIO=false
1422 BAR2Size=8
1423 BAR3=1
1424 BAR3LegacyIO=false
1425 BAR3Size=4
1426 BAR4=1
1427 BAR4LegacyIO=false
1428 BAR4Size=16
1429 BAR5=1
1430 BAR5LegacyIO=false
1431 BAR5Size=0
1432 BIST=0
1433 CacheLineSize=0
1434 CapabilityPtr=0
1435 CardbusCIS=0
1436 ClassCode=1
1437 Command=1
1438 DeviceID=28945
1439 ExpansionROM=0
1440 HeaderType=0
1441 InterruptLine=31
1442 InterruptPin=1
1443 LatencyTimer=0
1444 MSICAPBaseOffset=0
1445 MSICAPCapId=0
1446 MSICAPMaskBits=0
1447 MSICAPMsgAddr=0
1448 MSICAPMsgCtrl=0
1449 MSICAPMsgData=0
1450 MSICAPMsgUpperAddr=0
1451 MSICAPNextCapability=0
1452 MSICAPPendingBits=0
1453 MSIXCAPBaseOffset=0
1454 MSIXCAPCapId=0
1455 MSIXCAPNextCapability=0
1456 MSIXMsgCtrl=0
1457 MSIXPbaOffset=0
1458 MSIXTableOffset=0
1459 MaximumLatency=0
1460 MinimumGrant=0
1461 PMCAPBaseOffset=0
1462 PMCAPCapId=0
1463 PMCAPCapabilities=0
1464 PMCAPCtrlStatus=0
1465 PMCAPNextCapability=0
1466 PXCAPBaseOffset=0
1467 PXCAPCapId=0
1468 PXCAPCapabilities=0
1469 PXCAPDevCap2=0
1470 PXCAPDevCapabilities=0
1471 PXCAPDevCtrl=0
1472 PXCAPDevCtrl2=0
1473 PXCAPDevStatus=0
1474 PXCAPLinkCap=0
1475 PXCAPLinkCtrl=0
1476 PXCAPLinkStatus=0
1477 PXCAPNextCapability=0
1478 ProgIF=133
1479 Revision=0
1480 Status=640
1481 SubClassCode=1
1482 SubsystemID=0
1483 SubsystemVendorID=0
1484 VendorID=32902
1485 clk_domain=system.clk_domain
1486 config_latency=20000
1487 ctrl_offset=2
1488 disks=system.cf0
1489 eventq_index=0
1490 io_shift=1
1491 pci_bus=2
1492 pci_dev=7
1493 pci_func=0
1494 pio_latency=30000
1495 platform=system.realview
1496 system=system
1497 config=system.iobus.master[8]
1498 dma=system.iobus.slave[2]
1499 pio=system.iobus.master[7]
1500
1501 [system.realview.clcd]
1502 type=Pl111
1503 amba_id=1315089
1504 clk_domain=system.clk_domain
1505 enable_capture=true
1506 eventq_index=0
1507 gic=system.realview.gic
1508 int_num=55
1509 pio_addr=268566528
1510 pio_latency=10000
1511 pixel_clock=41667
1512 system=system
1513 vnc=system.vncserver
1514 dma=system.iobus.slave[1]
1515 pio=system.iobus.master[4]
1516
1517 [system.realview.dmac_fake]
1518 type=AmbaFake
1519 amba_id=0
1520 clk_domain=system.clk_domain
1521 eventq_index=0
1522 ignore_access=false
1523 pio_addr=268632064
1524 pio_latency=100000
1525 system=system
1526 pio=system.iobus.master[9]
1527
1528 [system.realview.flash_fake]
1529 type=IsaFake
1530 clk_domain=system.clk_domain
1531 eventq_index=0
1532 fake_mem=true
1533 pio_addr=1073741824
1534 pio_latency=100000
1535 pio_size=536870912
1536 ret_bad_addr=false
1537 ret_data16=65535
1538 ret_data32=4294967295
1539 ret_data64=18446744073709551615
1540 ret_data8=255
1541 system=system
1542 update_data=false
1543 warn_access=
1544 pio=system.iobus.master[24]
1545
1546 [system.realview.gic]
1547 type=Pl390
1548 clk_domain=system.clk_domain
1549 cpu_addr=520093952
1550 cpu_pio_delay=10000
1551 dist_addr=520097792
1552 dist_pio_delay=10000
1553 eventq_index=0
1554 int_latency=10000
1555 it_lines=128
1556 msix_addr=0
1557 platform=system.realview
1558 system=system
1559 pio=system.membus.master[2]
1560
1561 [system.realview.gpio0_fake]
1562 type=AmbaFake
1563 amba_id=0
1564 clk_domain=system.clk_domain
1565 eventq_index=0
1566 ignore_access=false
1567 pio_addr=268513280
1568 pio_latency=100000
1569 system=system
1570 pio=system.iobus.master[16]
1571
1572 [system.realview.gpio1_fake]
1573 type=AmbaFake
1574 amba_id=0
1575 clk_domain=system.clk_domain
1576 eventq_index=0
1577 ignore_access=false
1578 pio_addr=268517376
1579 pio_latency=100000
1580 system=system
1581 pio=system.iobus.master[17]
1582
1583 [system.realview.gpio2_fake]
1584 type=AmbaFake
1585 amba_id=0
1586 clk_domain=system.clk_domain
1587 eventq_index=0
1588 ignore_access=false
1589 pio_addr=268521472
1590 pio_latency=100000
1591 system=system
1592 pio=system.iobus.master[18]
1593
1594 [system.realview.kmi0]
1595 type=Pl050
1596 amba_id=1314896
1597 clk_domain=system.clk_domain
1598 eventq_index=0
1599 gic=system.realview.gic
1600 int_delay=1000000
1601 int_num=52
1602 is_mouse=false
1603 pio_addr=268460032
1604 pio_latency=100000
1605 system=system
1606 vnc=system.vncserver
1607 pio=system.iobus.master[5]
1608
1609 [system.realview.kmi1]
1610 type=Pl050
1611 amba_id=1314896
1612 clk_domain=system.clk_domain
1613 eventq_index=0
1614 gic=system.realview.gic
1615 int_delay=1000000
1616 int_num=53
1617 is_mouse=true
1618 pio_addr=268464128
1619 pio_latency=100000
1620 system=system
1621 vnc=system.vncserver
1622 pio=system.iobus.master[6]
1623
1624 [system.realview.l2x0_fake]
1625 type=IsaFake
1626 clk_domain=system.clk_domain
1627 eventq_index=0
1628 fake_mem=false
1629 pio_addr=520101888
1630 pio_latency=100000
1631 pio_size=4095
1632 ret_bad_addr=false
1633 ret_data16=65535
1634 ret_data32=4294967295
1635 ret_data64=18446744073709551615
1636 ret_data8=255
1637 system=system
1638 update_data=false
1639 warn_access=
1640 pio=system.membus.master[3]
1641
1642 [system.realview.local_cpu_timer]
1643 type=CpuLocalTimer
1644 clk_domain=system.clk_domain
1645 eventq_index=0
1646 gic=system.realview.gic
1647 int_num_timer=29
1648 int_num_watchdog=30
1649 pio_addr=520095232
1650 pio_latency=100000
1651 system=system
1652 pio=system.membus.master[5]
1653
1654 [system.realview.mmc_fake]
1655 type=AmbaFake
1656 amba_id=0
1657 clk_domain=system.clk_domain
1658 eventq_index=0
1659 ignore_access=false
1660 pio_addr=268455936
1661 pio_latency=100000
1662 system=system
1663 pio=system.iobus.master[22]
1664
1665 [system.realview.nvmem]
1666 type=SimpleMemory
1667 bandwidth=73.000000
1668 clk_domain=system.clk_domain
1669 conf_table_reported=false
1670 eventq_index=0
1671 in_addr_map=true
1672 latency=30000
1673 latency_var=0
1674 null=false
1675 range=2147483648:2214592511
1676 port=system.membus.master[1]
1677
1678 [system.realview.realview_io]
1679 type=RealViewCtrl
1680 clk_domain=system.clk_domain
1681 eventq_index=0
1682 idreg=0
1683 pio_addr=268435456
1684 pio_latency=100000
1685 proc_id0=201326592
1686 proc_id1=201327138
1687 system=system
1688 pio=system.iobus.master[1]
1689
1690 [system.realview.rtc]
1691 type=PL031
1692 amba_id=3412017
1693 clk_domain=system.clk_domain
1694 eventq_index=0
1695 gic=system.realview.gic
1696 int_delay=100000
1697 int_num=42
1698 pio_addr=268529664
1699 pio_latency=100000
1700 system=system
1701 time=Thu Jan  1 00:00:00 2009
1702 pio=system.iobus.master[23]
1703
1704 [system.realview.sci_fake]
1705 type=AmbaFake
1706 amba_id=0
1707 clk_domain=system.clk_domain
1708 eventq_index=0
1709 ignore_access=false
1710 pio_addr=268492800
1711 pio_latency=100000
1712 system=system
1713 pio=system.iobus.master[20]
1714
1715 [system.realview.smc_fake]
1716 type=AmbaFake
1717 amba_id=0
1718 clk_domain=system.clk_domain
1719 eventq_index=0
1720 ignore_access=false
1721 pio_addr=269357056
1722 pio_latency=100000
1723 system=system
1724 pio=system.iobus.master[13]
1725
1726 [system.realview.sp810_fake]
1727 type=AmbaFake
1728 amba_id=0
1729 clk_domain=system.clk_domain
1730 eventq_index=0
1731 ignore_access=true
1732 pio_addr=268439552
1733 pio_latency=100000
1734 system=system
1735 pio=system.iobus.master[14]
1736
1737 [system.realview.ssp_fake]
1738 type=AmbaFake
1739 amba_id=0
1740 clk_domain=system.clk_domain
1741 eventq_index=0
1742 ignore_access=false
1743 pio_addr=268488704
1744 pio_latency=100000
1745 system=system
1746 pio=system.iobus.master[19]
1747
1748 [system.realview.timer0]
1749 type=Sp804
1750 amba_id=1316868
1751 clk_domain=system.clk_domain
1752 clock0=1000000
1753 clock1=1000000
1754 eventq_index=0
1755 gic=system.realview.gic
1756 int_num0=36
1757 int_num1=36
1758 pio_addr=268505088
1759 pio_latency=100000
1760 system=system
1761 pio=system.iobus.master[2]
1762
1763 [system.realview.timer1]
1764 type=Sp804
1765 amba_id=1316868
1766 clk_domain=system.clk_domain
1767 clock0=1000000
1768 clock1=1000000
1769 eventq_index=0
1770 gic=system.realview.gic
1771 int_num0=37
1772 int_num1=37
1773 pio_addr=268509184
1774 pio_latency=100000
1775 system=system
1776 pio=system.iobus.master[3]
1777
1778 [system.realview.uart]
1779 type=Pl011
1780 clk_domain=system.clk_domain
1781 end_on_eot=false
1782 eventq_index=0
1783 gic=system.realview.gic
1784 int_delay=100000
1785 int_num=44
1786 pio_addr=268472320
1787 pio_latency=100000
1788 platform=system.realview
1789 system=system
1790 terminal=system.terminal
1791 pio=system.iobus.master[0]
1792
1793 [system.realview.uart1_fake]
1794 type=AmbaFake
1795 amba_id=0
1796 clk_domain=system.clk_domain
1797 eventq_index=0
1798 ignore_access=false
1799 pio_addr=268476416
1800 pio_latency=100000
1801 system=system
1802 pio=system.iobus.master[10]
1803
1804 [system.realview.uart2_fake]
1805 type=AmbaFake
1806 amba_id=0
1807 clk_domain=system.clk_domain
1808 eventq_index=0
1809 ignore_access=false
1810 pio_addr=268480512
1811 pio_latency=100000
1812 system=system
1813 pio=system.iobus.master[11]
1814
1815 [system.realview.uart3_fake]
1816 type=AmbaFake
1817 amba_id=0
1818 clk_domain=system.clk_domain
1819 eventq_index=0
1820 ignore_access=false
1821 pio_addr=268484608
1822 pio_latency=100000
1823 system=system
1824 pio=system.iobus.master[12]
1825
1826 [system.realview.watchdog_fake]
1827 type=AmbaFake
1828 amba_id=0
1829 clk_domain=system.clk_domain
1830 eventq_index=0
1831 ignore_access=false
1832 pio_addr=268500992
1833 pio_latency=100000
1834 system=system
1835 pio=system.iobus.master[15]
1836
1837 [system.terminal]
1838 type=Terminal
1839 eventq_index=0
1840 intr_control=system.intrctrl
1841 number=0
1842 output=true
1843 port=3456
1844
1845 [system.toL2Bus]
1846 type=CoherentBus
1847 clk_domain=system.cpu_clk_domain
1848 eventq_index=0
1849 header_cycles=1
1850 system=system
1851 use_default_range=false
1852 width=8
1853 master=system.l2c.cpu_side
1854 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
1855
1856 [system.vncserver]
1857 type=VncServer
1858 eventq_index=0
1859 frame_capture=false
1860 number=0
1861 port=5900
1862
1863 [system.voltage_domain]
1864 type=VoltageDomain
1865 eventq_index=0
1866 voltage=1.000000
1867