tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=256
  15 boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
  17 boot_release_addr=65528
  18 cache_line_size=64
  19 clk_domain=system.clk_domain
  20 dtb_filename=
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 flags_addr=268435504
  25 gic_cpu_addr=520093952
  26 have_generic_timer=false
  27 have_large_asid_64=false
  28 have_lpae=false
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
  34 load_addr_mask=268435455
  35 load_offset=0
  36 machine_type=RealView_PBX
  37 mem_mode=timing
  38 mem_ranges=0:134217727
  39 memories=system.physmem system.realview.nvmem
  40 multi_proc=true
  41 num_work_ids=16
  42 panic_on_oops=true
  43 panic_on_panic=true
  44 phys_addr_range_64=40
  45 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
  46 reset_addr_64=0
  47 symbolfile=
  48 work_begin_ckpt_count=0
  49 work_begin_cpu_id_exit=-1
  50 work_begin_exit_count=0
  51 work_cpus_ckpt_count=0
  52 work_end_ckpt_count=0
  53 work_end_exit_count=0
  54 work_item_id=-1
  55 system_port=system.membus.slave[0]
  56
  57 [system.bridge]
  58 type=Bridge
  59 clk_domain=system.clk_domain
  60 delay=50000
  61 eventq_index=0
  62 ranges=268435456:520093695 1073741824:1610612735
  63 req_size=16
  64 resp_size=16
  65 master=system.iobus.slave[0]
  66 slave=system.membus.master[0]
  67
  68 [system.cf0]
  69 type=IdeDisk
  70 children=image
  71 delay=1000000
  72 driveID=master
  73 eventq_index=0
  74 image=system.cf0.image
  75
  76 [system.cf0.image]
  77 type=CowDiskImage
  78 children=child
  79 child=system.cf0.image.child
  80 eventq_index=0
  81 image_file=
  82 read_only=false
  83 table_size=65536
  84
  85 [system.cf0.image.child]
  86 type=RawDiskImage
  87 eventq_index=0
  88 image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
  89 read_only=true
  90
  91 [system.clk_domain]
  92 type=SrcClockDomain
  93 clock=1000
  94 eventq_index=0
  95 voltage_domain=system.voltage_domain
  96
  97 [system.cpu0]
  98 type=DerivO3CPU
  99 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
 100 LFSTSize=1024
 101 LQEntries=32
 102 LSQCheckLoads=true
 103 LSQDepCheckShift=4
 104 SQEntries=32
 105 SSITSize=1024
 106 activity=0
 107 backComSize=5
 108 branchPred=system.cpu0.branchPred
 109 cachePorts=200
 110 checker=Null
 111 clk_domain=system.cpu_clk_domain
 112 commitToDecodeDelay=1
 113 commitToFetchDelay=1
 114 commitToIEWDelay=1
 115 commitToRenameDelay=1
 116 commitWidth=8
 117 cpu_id=0
 118 decodeToFetchDelay=1
 119 decodeToRenameDelay=1
 120 decodeWidth=8
 121 dispatchWidth=8
 122 do_checkpoint_insts=true
 123 do_quiesce=true
 124 do_statistics_insts=true
 125 dstage2_mmu=system.cpu0.dstage2_mmu
 126 dtb=system.cpu0.dtb
 127 eventq_index=0
 128 fetchBufferSize=64
 129 fetchToDecodeDelay=1
 130 fetchTrapLatency=1
 131 fetchWidth=8
 132 forwardComSize=5
 133 fuPool=system.cpu0.fuPool
 134 function_trace=false
 135 function_trace_start=0
 136 iewToCommitDelay=1
 137 iewToDecodeDelay=1
 138 iewToFetchDelay=1
 139 iewToRenameDelay=1
 140 interrupts=system.cpu0.interrupts
 141 isa=system.cpu0.isa
 142 issueToExecuteDelay=1
 143 issueWidth=8
 144 istage2_mmu=system.cpu0.istage2_mmu
 145 itb=system.cpu0.itb
 146 max_insts_all_threads=0
 147 max_insts_any_thread=0
 148 max_loads_all_threads=0
 149 max_loads_any_thread=0
 150 needsTSO=false
 151 numIQEntries=64
 152 numPhysCCRegs=0
 153 numPhysFloatRegs=256
 154 numPhysIntRegs=256
 155 numROBEntries=192
 156 numRobs=1
 157 numThreads=1
 158 profile=0
 159 progress_interval=0
 160 renameToDecodeDelay=1
 161 renameToFetchDelay=1
 162 renameToIEWDelay=2
 163 renameToROBDelay=1
 164 renameWidth=8
 165 simpoint_start_insts=
 166 smtCommitPolicy=RoundRobin
 167 smtFetchPolicy=SingleThread
 168 smtIQPolicy=Partitioned
 169 smtIQThreshold=100
 170 smtLSQPolicy=Partitioned
 171 smtLSQThreshold=100
 172 smtNumFetchingThreads=1
 173 smtROBPolicy=Partitioned
 174 smtROBThreshold=100
 175 socket_id=0
 176 squashWidth=8
 177 store_set_clear_period=250000
 178 switched_out=false
 179 system=system
 180 tracer=system.cpu0.tracer
 181 trapLatency=13
 182 wbDepth=1
 183 wbWidth=8
 184 workload=
 185 dcache_port=system.cpu0.dcache.cpu_side
 186 icache_port=system.cpu0.icache.cpu_side
 187
 188 [system.cpu0.branchPred]
 189 type=BranchPredictor
 190 BTBEntries=4096
 191 BTBTagSize=16
 192 RASSize=16
 193 choiceCtrBits=2
 194 choicePredictorSize=8192
 195 eventq_index=0
 196 globalCtrBits=2
 197 globalPredictorSize=8192
 198 instShiftAmt=2
 199 localCtrBits=2
 200 localHistoryTableSize=2048
 201 localPredictorSize=2048
 202 numThreads=1
 203 predType=tournament
 204
 205 [system.cpu0.dcache]
 206 type=BaseCache
 207 children=tags
 208 addr_ranges=0:18446744073709551615
 209 assoc=4
 210 clk_domain=system.cpu_clk_domain
 211 eventq_index=0
 212 forward_snoops=true
 213 hit_latency=2
 214 is_top_level=true
 215 max_miss_count=0
 216 mshrs=4
 217 prefetch_on_access=false
 218 prefetcher=Null
 219 response_latency=2
 220 sequential_access=false
 221 size=32768
 222 system=system
 223 tags=system.cpu0.dcache.tags
 224 tgts_per_mshr=20
 225 two_queue=false
 226 write_buffers=8
 227 cpu_side=system.cpu0.dcache_port
 228 mem_side=system.toL2Bus.slave[1]
 229
 230 [system.cpu0.dcache.tags]
 231 type=LRU
 232 assoc=4
 233 block_size=64
 234 clk_domain=system.cpu_clk_domain
 235 eventq_index=0
 236 hit_latency=2
 237 sequential_access=false
 238 size=32768
 239
 240 [system.cpu0.dstage2_mmu]
 241 type=ArmStage2MMU
 242 children=stage2_tlb
 243 eventq_index=0
 244 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 245 tlb=system.cpu0.dtb
 246
 247 [system.cpu0.dstage2_mmu.stage2_tlb]
 248 type=ArmTLB
 249 children=walker
 250 eventq_index=0
 251 is_stage2=true
 252 size=32
 253 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 254
 255 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 256 type=ArmTableWalker
 257 clk_domain=system.cpu_clk_domain
 258 eventq_index=0
 259 is_stage2=true
 260 num_squash_per_cycle=2
 261 sys=system
 262 port=system.toL2Bus.slave[5]
 263
 264 [system.cpu0.dtb]
 265 type=ArmTLB
 266 children=walker
 267 eventq_index=0
 268 is_stage2=false
 269 size=64
 270 walker=system.cpu0.dtb.walker
 271
 272 [system.cpu0.dtb.walker]
 273 type=ArmTableWalker
 274 clk_domain=system.cpu_clk_domain
 275 eventq_index=0
 276 is_stage2=false
 277 num_squash_per_cycle=2
 278 sys=system
 279 port=system.toL2Bus.slave[3]
 280
 281 [system.cpu0.fuPool]
 282 type=FUPool
 283 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 284 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
 285 eventq_index=0
 286
 287 [system.cpu0.fuPool.FUList0]
 288 type=FUDesc
 289 children=opList
 290 count=6
 291 eventq_index=0
 292 opList=system.cpu0.fuPool.FUList0.opList
 293
 294 [system.cpu0.fuPool.FUList0.opList]
 295 type=OpDesc
 296 eventq_index=0
 297 issueLat=1
 298 opClass=IntAlu
 299 opLat=1
 300
 301 [system.cpu0.fuPool.FUList1]
 302 type=FUDesc
 303 children=opList0 opList1
 304 count=2
 305 eventq_index=0
 306 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 307
 308 [system.cpu0.fuPool.FUList1.opList0]
 309 type=OpDesc
 310 eventq_index=0
 311 issueLat=1
 312 opClass=IntMult
 313 opLat=3
 314
 315 [system.cpu0.fuPool.FUList1.opList1]
 316 type=OpDesc
 317 eventq_index=0
 318 issueLat=19
 319 opClass=IntDiv
 320 opLat=20
 321
 322 [system.cpu0.fuPool.FUList2]
 323 type=FUDesc
 324 children=opList0 opList1 opList2
 325 count=4
 326 eventq_index=0
 327 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
 328
 329 [system.cpu0.fuPool.FUList2.opList0]
 330 type=OpDesc
 331 eventq_index=0
 332 issueLat=1
 333 opClass=FloatAdd
 334 opLat=2
 335
 336 [system.cpu0.fuPool.FUList2.opList1]
 337 type=OpDesc
 338 eventq_index=0
 339 issueLat=1
 340 opClass=FloatCmp
 341 opLat=2
 342
 343 [system.cpu0.fuPool.FUList2.opList2]
 344 type=OpDesc
 345 eventq_index=0
 346 issueLat=1
 347 opClass=FloatCvt
 348 opLat=2
 349
 350 [system.cpu0.fuPool.FUList3]
 351 type=FUDesc
 352 children=opList0 opList1 opList2
 353 count=2
 354 eventq_index=0
 355 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
 356
 357 [system.cpu0.fuPool.FUList3.opList0]
 358 type=OpDesc
 359 eventq_index=0
 360 issueLat=1
 361 opClass=FloatMult
 362 opLat=4
 363
 364 [system.cpu0.fuPool.FUList3.opList1]
 365 type=OpDesc
 366 eventq_index=0
 367 issueLat=12
 368 opClass=FloatDiv
 369 opLat=12
 370
 371 [system.cpu0.fuPool.FUList3.opList2]
 372 type=OpDesc
 373 eventq_index=0
 374 issueLat=24
 375 opClass=FloatSqrt
 376 opLat=24
 377
 378 [system.cpu0.fuPool.FUList4]
 379 type=FUDesc
 380 children=opList
 381 count=0
 382 eventq_index=0
 383 opList=system.cpu0.fuPool.FUList4.opList
 384
 385 [system.cpu0.fuPool.FUList4.opList]
 386 type=OpDesc
 387 eventq_index=0
 388 issueLat=1
 389 opClass=MemRead
 390 opLat=1
 391
 392 [system.cpu0.fuPool.FUList5]
 393 type=FUDesc
 394 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 395 count=4
 396 eventq_index=0
 397 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
 398
 399 [system.cpu0.fuPool.FUList5.opList00]
 400 type=OpDesc
 401 eventq_index=0
 402 issueLat=1
 403 opClass=SimdAdd
 404 opLat=1
 405
 406 [system.cpu0.fuPool.FUList5.opList01]
 407 type=OpDesc
 408 eventq_index=0
 409 issueLat=1
 410 opClass=SimdAddAcc
 411 opLat=1
 412
 413 [system.cpu0.fuPool.FUList5.opList02]
 414 type=OpDesc
 415 eventq_index=0
 416 issueLat=1
 417 opClass=SimdAlu
 418 opLat=1
 419
 420 [system.cpu0.fuPool.FUList5.opList03]
 421 type=OpDesc
 422 eventq_index=0
 423 issueLat=1
 424 opClass=SimdCmp
 425 opLat=1
 426
 427 [system.cpu0.fuPool.FUList5.opList04]
 428 type=OpDesc
 429 eventq_index=0
 430 issueLat=1
 431 opClass=SimdCvt
 432 opLat=1
 433
 434 [system.cpu0.fuPool.FUList5.opList05]
 435 type=OpDesc
 436 eventq_index=0
 437 issueLat=1
 438 opClass=SimdMisc
 439 opLat=1
 440
 441 [system.cpu0.fuPool.FUList5.opList06]
 442 type=OpDesc
 443 eventq_index=0
 444 issueLat=1
 445 opClass=SimdMult
 446 opLat=1
 447
 448 [system.cpu0.fuPool.FUList5.opList07]
 449 type=OpDesc
 450 eventq_index=0
 451 issueLat=1
 452 opClass=SimdMultAcc
 453 opLat=1
 454
 455 [system.cpu0.fuPool.FUList5.opList08]
 456 type=OpDesc
 457 eventq_index=0
 458 issueLat=1
 459 opClass=SimdShift
 460 opLat=1
 461
 462 [system.cpu0.fuPool.FUList5.opList09]
 463 type=OpDesc
 464 eventq_index=0
 465 issueLat=1
 466 opClass=SimdShiftAcc
 467 opLat=1
 468
 469 [system.cpu0.fuPool.FUList5.opList10]
 470 type=OpDesc
 471 eventq_index=0
 472 issueLat=1
 473 opClass=SimdSqrt
 474 opLat=1
 475
 476 [system.cpu0.fuPool.FUList5.opList11]
 477 type=OpDesc
 478 eventq_index=0
 479 issueLat=1
 480 opClass=SimdFloatAdd
 481 opLat=1
 482
 483 [system.cpu0.fuPool.FUList5.opList12]
 484 type=OpDesc
 485 eventq_index=0
 486 issueLat=1
 487 opClass=SimdFloatAlu
 488 opLat=1
 489
 490 [system.cpu0.fuPool.FUList5.opList13]
 491 type=OpDesc
 492 eventq_index=0
 493 issueLat=1
 494 opClass=SimdFloatCmp
 495 opLat=1
 496
 497 [system.cpu0.fuPool.FUList5.opList14]
 498 type=OpDesc
 499 eventq_index=0
 500 issueLat=1
 501 opClass=SimdFloatCvt
 502 opLat=1
 503
 504 [system.cpu0.fuPool.FUList5.opList15]
 505 type=OpDesc
 506 eventq_index=0
 507 issueLat=1
 508 opClass=SimdFloatDiv
 509 opLat=1
 510
 511 [system.cpu0.fuPool.FUList5.opList16]
 512 type=OpDesc
 513 eventq_index=0
 514 issueLat=1
 515 opClass=SimdFloatMisc
 516 opLat=1
 517
 518 [system.cpu0.fuPool.FUList5.opList17]
 519 type=OpDesc
 520 eventq_index=0
 521 issueLat=1
 522 opClass=SimdFloatMult
 523 opLat=1
 524
 525 [system.cpu0.fuPool.FUList5.opList18]
 526 type=OpDesc
 527 eventq_index=0
 528 issueLat=1
 529 opClass=SimdFloatMultAcc
 530 opLat=1
 531
 532 [system.cpu0.fuPool.FUList5.opList19]
 533 type=OpDesc
 534 eventq_index=0
 535 issueLat=1
 536 opClass=SimdFloatSqrt
 537 opLat=1
 538
 539 [system.cpu0.fuPool.FUList6]
 540 type=FUDesc
 541 children=opList
 542 count=0
 543 eventq_index=0
 544 opList=system.cpu0.fuPool.FUList6.opList
 545
 546 [system.cpu0.fuPool.FUList6.opList]
 547 type=OpDesc
 548 eventq_index=0
 549 issueLat=1
 550 opClass=MemWrite
 551 opLat=1
 552
 553 [system.cpu0.fuPool.FUList7]
 554 type=FUDesc
 555 children=opList0 opList1
 556 count=4
 557 eventq_index=0
 558 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 559
 560 [system.cpu0.fuPool.FUList7.opList0]
 561 type=OpDesc
 562 eventq_index=0
 563 issueLat=1
 564 opClass=MemRead
 565 opLat=1
 566
 567 [system.cpu0.fuPool.FUList7.opList1]
 568 type=OpDesc
 569 eventq_index=0
 570 issueLat=1
 571 opClass=MemWrite
 572 opLat=1
 573
 574 [system.cpu0.fuPool.FUList8]
 575 type=FUDesc
 576 children=opList
 577 count=1
 578 eventq_index=0
 579 opList=system.cpu0.fuPool.FUList8.opList
 580
 581 [system.cpu0.fuPool.FUList8.opList]
 582 type=OpDesc
 583 eventq_index=0
 584 issueLat=3
 585 opClass=IprAccess
 586 opLat=3
 587
 588 [system.cpu0.icache]
 589 type=BaseCache
 590 children=tags
 591 addr_ranges=0:18446744073709551615
 592 assoc=1
 593 clk_domain=system.cpu_clk_domain
 594 eventq_index=0
 595 forward_snoops=true
 596 hit_latency=2
 597 is_top_level=true
 598 max_miss_count=0
 599 mshrs=4
 600 prefetch_on_access=false
 601 prefetcher=Null
 602 response_latency=2
 603 sequential_access=false
 604 size=32768
 605 system=system
 606 tags=system.cpu0.icache.tags
 607 tgts_per_mshr=20
 608 two_queue=false
 609 write_buffers=8
 610 cpu_side=system.cpu0.icache_port
 611 mem_side=system.toL2Bus.slave[0]
 612
 613 [system.cpu0.icache.tags]
 614 type=LRU
 615 assoc=1
 616 block_size=64
 617 clk_domain=system.cpu_clk_domain
 618 eventq_index=0
 619 hit_latency=2
 620 sequential_access=false
 621 size=32768
 622
 623 [system.cpu0.interrupts]
 624 type=ArmInterrupts
 625 eventq_index=0
 626
 627 [system.cpu0.isa]
 628 type=ArmISA
 629 eventq_index=0
 630 fpsid=1090793632
 631 id_aa64afr0_el1=0
 632 id_aa64afr1_el1=0
 633 id_aa64dfr0_el1=1052678
 634 id_aa64dfr1_el1=0
 635 id_aa64isar0_el1=0
 636 id_aa64isar1_el1=0
 637 id_aa64mmfr0_el1=15728642
 638 id_aa64mmfr1_el1=0
 639 id_aa64pfr0_el1=17
 640 id_aa64pfr1_el1=0
 641 id_isar0=34607377
 642 id_isar1=34677009
 643 id_isar2=555950401
 644 id_isar3=17899825
 645 id_isar4=268501314
 646 id_isar5=0
 647 id_mmfr0=270536963
 648 id_mmfr1=0
 649 id_mmfr2=19070976
 650 id_mmfr3=34611729
 651 id_pfr0=49
 652 id_pfr1=4113
 653 midr=1091551472
 654 system=system
 655
 656 [system.cpu0.istage2_mmu]
 657 type=ArmStage2MMU
 658 children=stage2_tlb
 659 eventq_index=0
 660 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 661 tlb=system.cpu0.itb
 662
 663 [system.cpu0.istage2_mmu.stage2_tlb]
 664 type=ArmTLB
 665 children=walker
 666 eventq_index=0
 667 is_stage2=true
 668 size=32
 669 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 670
 671 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 672 type=ArmTableWalker
 673 clk_domain=system.cpu_clk_domain
 674 eventq_index=0
 675 is_stage2=true
 676 num_squash_per_cycle=2
 677 sys=system
 678 port=system.toL2Bus.slave[4]
 679
 680 [system.cpu0.itb]
 681 type=ArmTLB
 682 children=walker
 683 eventq_index=0
 684 is_stage2=false
 685 size=64
 686 walker=system.cpu0.itb.walker
 687
 688 [system.cpu0.itb.walker]
 689 type=ArmTableWalker
 690 clk_domain=system.cpu_clk_domain
 691 eventq_index=0
 692 is_stage2=false
 693 num_squash_per_cycle=2
 694 sys=system
 695 port=system.toL2Bus.slave[2]
 696
 697 [system.cpu0.tracer]
 698 type=ExeTracer
 699 eventq_index=0
 700
 701 [system.cpu1]
 702 type=DerivO3CPU
 703 children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
 704 LFSTSize=1024
 705 LQEntries=32
 706 LSQCheckLoads=true
 707 LSQDepCheckShift=4
 708 SQEntries=32
 709 SSITSize=1024
 710 activity=0
 711 backComSize=5
 712 branchPred=system.cpu1.branchPred
 713 cachePorts=200
 714 checker=Null
 715 clk_domain=system.cpu_clk_domain
 716 commitToDecodeDelay=1
 717 commitToFetchDelay=1
 718 commitToIEWDelay=1
 719 commitToRenameDelay=1
 720 commitWidth=8
 721 cpu_id=0
 722 decodeToFetchDelay=1
 723 decodeToRenameDelay=1
 724 decodeWidth=8
 725 dispatchWidth=8
 726 do_checkpoint_insts=true
 727 do_quiesce=true
 728 do_statistics_insts=true
 729 dstage2_mmu=system.cpu1.dstage2_mmu
 730 dtb=system.cpu1.dtb
 731 eventq_index=0
 732 fetchBufferSize=64
 733 fetchToDecodeDelay=1
 734 fetchTrapLatency=1
 735 fetchWidth=8
 736 forwardComSize=5
 737 fuPool=system.cpu1.fuPool
 738 function_trace=false
 739 function_trace_start=0
 740 iewToCommitDelay=1
 741 iewToDecodeDelay=1
 742 iewToFetchDelay=1
 743 iewToRenameDelay=1
 744 interrupts=Null
 745 isa=system.cpu1.isa
 746 issueToExecuteDelay=1
 747 issueWidth=8
 748 istage2_mmu=system.cpu1.istage2_mmu
 749 itb=system.cpu1.itb
 750 max_insts_all_threads=0
 751 max_insts_any_thread=0
 752 max_loads_all_threads=0
 753 max_loads_any_thread=0
 754 needsTSO=false
 755 numIQEntries=64
 756 numPhysCCRegs=0
 757 numPhysFloatRegs=256
 758 numPhysIntRegs=256
 759 numROBEntries=192
 760 numRobs=1
 761 numThreads=1
 762 profile=0
 763 progress_interval=0
 764 renameToDecodeDelay=1
 765 renameToFetchDelay=1
 766 renameToIEWDelay=2
 767 renameToROBDelay=1
 768 renameWidth=8
 769 simpoint_start_insts=
 770 smtCommitPolicy=RoundRobin
 771 smtFetchPolicy=SingleThread
 772 smtIQPolicy=Partitioned
 773 smtIQThreshold=100
 774 smtLSQPolicy=Partitioned
 775 smtLSQThreshold=100
 776 smtNumFetchingThreads=1
 777 smtROBPolicy=Partitioned
 778 smtROBThreshold=100
 779 socket_id=0
 780 squashWidth=8
 781 store_set_clear_period=250000
 782 switched_out=true
 783 system=system
 784 tracer=system.cpu1.tracer
 785 trapLatency=13
 786 wbDepth=1
 787 wbWidth=8
 788 workload=
 789
 790 [system.cpu1.branchPred]
 791 type=BranchPredictor
 792 BTBEntries=4096
 793 BTBTagSize=16
 794 RASSize=16
 795 choiceCtrBits=2
 796 choicePredictorSize=8192
 797 eventq_index=0
 798 globalCtrBits=2
 799 globalPredictorSize=8192
 800 instShiftAmt=2
 801 localCtrBits=2
 802 localHistoryTableSize=2048
 803 localPredictorSize=2048
 804 numThreads=1
 805 predType=tournament
 806
 807 [system.cpu1.dstage2_mmu]
 808 type=ArmStage2MMU
 809 children=stage2_tlb
 810 eventq_index=0
 811 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
 812 tlb=system.cpu1.dtb
 813
 814 [system.cpu1.dstage2_mmu.stage2_tlb]
 815 type=ArmTLB
 816 children=walker
 817 eventq_index=0
 818 is_stage2=true
 819 size=32
 820 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
 821
 822 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
 823 type=ArmTableWalker
 824 clk_domain=system.cpu_clk_domain
 825 eventq_index=0
 826 is_stage2=true
 827 num_squash_per_cycle=2
 828 sys=system
 829
 830 [system.cpu1.dtb]
 831 type=ArmTLB
 832 children=walker
 833 eventq_index=0
 834 is_stage2=false
 835 size=64
 836 walker=system.cpu1.dtb.walker
 837
 838 [system.cpu1.dtb.walker]
 839 type=ArmTableWalker
 840 clk_domain=system.cpu_clk_domain
 841 eventq_index=0
 842 is_stage2=false
 843 num_squash_per_cycle=2
 844 sys=system
 845
 846 [system.cpu1.fuPool]
 847 type=FUPool
 848 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 849 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
 850 eventq_index=0
 851
 852 [system.cpu1.fuPool.FUList0]
 853 type=FUDesc
 854 children=opList
 855 count=6
 856 eventq_index=0
 857 opList=system.cpu1.fuPool.FUList0.opList
 858
 859 [system.cpu1.fuPool.FUList0.opList]
 860 type=OpDesc
 861 eventq_index=0
 862 issueLat=1
 863 opClass=IntAlu
 864 opLat=1
 865
 866 [system.cpu1.fuPool.FUList1]
 867 type=FUDesc
 868 children=opList0 opList1
 869 count=2
 870 eventq_index=0
 871 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 872
 873 [system.cpu1.fuPool.FUList1.opList0]
 874 type=OpDesc
 875 eventq_index=0
 876 issueLat=1
 877 opClass=IntMult
 878 opLat=3
 879
 880 [system.cpu1.fuPool.FUList1.opList1]
 881 type=OpDesc
 882 eventq_index=0
 883 issueLat=19
 884 opClass=IntDiv
 885 opLat=20
 886
 887 [system.cpu1.fuPool.FUList2]
 888 type=FUDesc
 889 children=opList0 opList1 opList2
 890 count=4
 891 eventq_index=0
 892 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
 893
 894 [system.cpu1.fuPool.FUList2.opList0]
 895 type=OpDesc
 896 eventq_index=0
 897 issueLat=1
 898 opClass=FloatAdd
 899 opLat=2
 900
 901 [system.cpu1.fuPool.FUList2.opList1]
 902 type=OpDesc
 903 eventq_index=0
 904 issueLat=1
 905 opClass=FloatCmp
 906 opLat=2
 907
 908 [system.cpu1.fuPool.FUList2.opList2]
 909 type=OpDesc
 910 eventq_index=0
 911 issueLat=1
 912 opClass=FloatCvt
 913 opLat=2
 914
 915 [system.cpu1.fuPool.FUList3]
 916 type=FUDesc
 917 children=opList0 opList1 opList2
 918 count=2
 919 eventq_index=0
 920 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
 921
 922 [system.cpu1.fuPool.FUList3.opList0]
 923 type=OpDesc
 924 eventq_index=0
 925 issueLat=1
 926 opClass=FloatMult
 927 opLat=4
 928
 929 [system.cpu1.fuPool.FUList3.opList1]
 930 type=OpDesc
 931 eventq_index=0
 932 issueLat=12
 933 opClass=FloatDiv
 934 opLat=12
 935
 936 [system.cpu1.fuPool.FUList3.opList2]
 937 type=OpDesc
 938 eventq_index=0
 939 issueLat=24
 940 opClass=FloatSqrt
 941 opLat=24
 942
 943 [system.cpu1.fuPool.FUList4]
 944 type=FUDesc
 945 children=opList
 946 count=0
 947 eventq_index=0
 948 opList=system.cpu1.fuPool.FUList4.opList
 949
 950 [system.cpu1.fuPool.FUList4.opList]
 951 type=OpDesc
 952 eventq_index=0
 953 issueLat=1
 954 opClass=MemRead
 955 opLat=1
 956
 957 [system.cpu1.fuPool.FUList5]
 958 type=FUDesc
 959 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 960 count=4
 961 eventq_index=0
 962 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
 963
 964 [system.cpu1.fuPool.FUList5.opList00]
 965 type=OpDesc
 966 eventq_index=0
 967 issueLat=1
 968 opClass=SimdAdd
 969 opLat=1
 970
 971 [system.cpu1.fuPool.FUList5.opList01]
 972 type=OpDesc
 973 eventq_index=0
 974 issueLat=1
 975 opClass=SimdAddAcc
 976 opLat=1
 977
 978 [system.cpu1.fuPool.FUList5.opList02]
 979 type=OpDesc
 980 eventq_index=0
 981 issueLat=1
 982 opClass=SimdAlu
 983 opLat=1
 984
 985 [system.cpu1.fuPool.FUList5.opList03]
 986 type=OpDesc
 987 eventq_index=0
 988 issueLat=1
 989 opClass=SimdCmp
 990 opLat=1
 991
 992 [system.cpu1.fuPool.FUList5.opList04]
 993 type=OpDesc
 994 eventq_index=0
 995 issueLat=1
 996 opClass=SimdCvt
 997 opLat=1
 998
 999 [system.cpu1.fuPool.FUList5.opList05]
1000 type=OpDesc
1001 eventq_index=0
1002 issueLat=1
1003 opClass=SimdMisc
1004 opLat=1
1005
1006 [system.cpu1.fuPool.FUList5.opList06]
1007 type=OpDesc
1008 eventq_index=0
1009 issueLat=1
1010 opClass=SimdMult
1011 opLat=1
1012
1013 [system.cpu1.fuPool.FUList5.opList07]
1014 type=OpDesc
1015 eventq_index=0
1016 issueLat=1
1017 opClass=SimdMultAcc
1018 opLat=1
1019
1020 [system.cpu1.fuPool.FUList5.opList08]
1021 type=OpDesc
1022 eventq_index=0
1023 issueLat=1
1024 opClass=SimdShift
1025 opLat=1
1026
1027 [system.cpu1.fuPool.FUList5.opList09]
1028 type=OpDesc
1029 eventq_index=0
1030 issueLat=1
1031 opClass=SimdShiftAcc
1032 opLat=1
1033
1034 [system.cpu1.fuPool.FUList5.opList10]
1035 type=OpDesc
1036 eventq_index=0
1037 issueLat=1
1038 opClass=SimdSqrt
1039 opLat=1
1040
1041 [system.cpu1.fuPool.FUList5.opList11]
1042 type=OpDesc
1043 eventq_index=0
1044 issueLat=1
1045 opClass=SimdFloatAdd
1046 opLat=1
1047
1048 [system.cpu1.fuPool.FUList5.opList12]
1049 type=OpDesc
1050 eventq_index=0
1051 issueLat=1
1052 opClass=SimdFloatAlu
1053 opLat=1
1054
1055 [system.cpu1.fuPool.FUList5.opList13]
1056 type=OpDesc
1057 eventq_index=0
1058 issueLat=1
1059 opClass=SimdFloatCmp
1060 opLat=1
1061
1062 [system.cpu1.fuPool.FUList5.opList14]
1063 type=OpDesc
1064 eventq_index=0
1065 issueLat=1
1066 opClass=SimdFloatCvt
1067 opLat=1
1068
1069 [system.cpu1.fuPool.FUList5.opList15]
1070 type=OpDesc
1071 eventq_index=0
1072 issueLat=1
1073 opClass=SimdFloatDiv
1074 opLat=1
1075
1076 [system.cpu1.fuPool.FUList5.opList16]
1077 type=OpDesc
1078 eventq_index=0
1079 issueLat=1
1080 opClass=SimdFloatMisc
1081 opLat=1
1082
1083 [system.cpu1.fuPool.FUList5.opList17]
1084 type=OpDesc
1085 eventq_index=0
1086 issueLat=1
1087 opClass=SimdFloatMult
1088 opLat=1
1089
1090 [system.cpu1.fuPool.FUList5.opList18]
1091 type=OpDesc
1092 eventq_index=0
1093 issueLat=1
1094 opClass=SimdFloatMultAcc
1095 opLat=1
1096
1097 [system.cpu1.fuPool.FUList5.opList19]
1098 type=OpDesc
1099 eventq_index=0
1100 issueLat=1
1101 opClass=SimdFloatSqrt
1102 opLat=1
1103
1104 [system.cpu1.fuPool.FUList6]
1105 type=FUDesc
1106 children=opList
1107 count=0
1108 eventq_index=0
1109 opList=system.cpu1.fuPool.FUList6.opList
1110
1111 [system.cpu1.fuPool.FUList6.opList]
1112 type=OpDesc
1113 eventq_index=0
1114 issueLat=1
1115 opClass=MemWrite
1116 opLat=1
1117
1118 [system.cpu1.fuPool.FUList7]
1119 type=FUDesc
1120 children=opList0 opList1
1121 count=4
1122 eventq_index=0
1123 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
1124
1125 [system.cpu1.fuPool.FUList7.opList0]
1126 type=OpDesc
1127 eventq_index=0
1128 issueLat=1
1129 opClass=MemRead
1130 opLat=1
1131
1132 [system.cpu1.fuPool.FUList7.opList1]
1133 type=OpDesc
1134 eventq_index=0
1135 issueLat=1
1136 opClass=MemWrite
1137 opLat=1
1138
1139 [system.cpu1.fuPool.FUList8]
1140 type=FUDesc
1141 children=opList
1142 count=1
1143 eventq_index=0
1144 opList=system.cpu1.fuPool.FUList8.opList
1145
1146 [system.cpu1.fuPool.FUList8.opList]
1147 type=OpDesc
1148 eventq_index=0
1149 issueLat=3
1150 opClass=IprAccess
1151 opLat=3
1152
1153 [system.cpu1.isa]
1154 type=ArmISA
1155 eventq_index=0
1156 fpsid=1090793632
1157 id_aa64afr0_el1=0
1158 id_aa64afr1_el1=0
1159 id_aa64dfr0_el1=1052678
1160 id_aa64dfr1_el1=0
1161 id_aa64isar0_el1=0
1162 id_aa64isar1_el1=0
1163 id_aa64mmfr0_el1=15728642
1164 id_aa64mmfr1_el1=0
1165 id_aa64pfr0_el1=17
1166 id_aa64pfr1_el1=0
1167 id_isar0=34607377
1168 id_isar1=34677009
1169 id_isar2=555950401
1170 id_isar3=17899825
1171 id_isar4=268501314
1172 id_isar5=0
1173 id_mmfr0=270536963
1174 id_mmfr1=0
1175 id_mmfr2=19070976
1176 id_mmfr3=34611729
1177 id_pfr0=49
1178 id_pfr1=4113
1179 midr=1091551472
1180 system=system
1181
1182 [system.cpu1.istage2_mmu]
1183 type=ArmStage2MMU
1184 children=stage2_tlb
1185 eventq_index=0
1186 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1187 tlb=system.cpu1.itb
1188
1189 [system.cpu1.istage2_mmu.stage2_tlb]
1190 type=ArmTLB
1191 children=walker
1192 eventq_index=0
1193 is_stage2=true
1194 size=32
1195 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1196
1197 [system.cpu1.istage2_mmu.stage2_tlb.walker]
1198 type=ArmTableWalker
1199 clk_domain=system.cpu_clk_domain
1200 eventq_index=0
1201 is_stage2=true
1202 num_squash_per_cycle=2
1203 sys=system
1204
1205 [system.cpu1.itb]
1206 type=ArmTLB
1207 children=walker
1208 eventq_index=0
1209 is_stage2=false
1210 size=64
1211 walker=system.cpu1.itb.walker
1212
1213 [system.cpu1.itb.walker]
1214 type=ArmTableWalker
1215 clk_domain=system.cpu_clk_domain
1216 eventq_index=0
1217 is_stage2=false
1218 num_squash_per_cycle=2
1219 sys=system
1220
1221 [system.cpu1.tracer]
1222 type=ExeTracer
1223 eventq_index=0
1224
1225 [system.cpu_clk_domain]
1226 type=SrcClockDomain
1227 clock=500
1228 eventq_index=0
1229 voltage_domain=system.voltage_domain
1230
1231 [system.intrctrl]
1232 type=IntrControl
1233 eventq_index=0
1234 sys=system
1235
1236 [system.iobus]
1237 type=NoncoherentBus
1238 clk_domain=system.clk_domain
1239 eventq_index=0
1240 header_cycles=1
1241 use_default_range=false
1242 width=8
1243 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
1244 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
1245
1246 [system.iocache]
1247 type=BaseCache
1248 children=tags
1249 addr_ranges=0:134217727
1250 assoc=8
1251 clk_domain=system.clk_domain
1252 eventq_index=0
1253 forward_snoops=false
1254 hit_latency=50
1255 is_top_level=true
1256 max_miss_count=0
1257 mshrs=20
1258 prefetch_on_access=false
1259 prefetcher=Null
1260 response_latency=50
1261 sequential_access=false
1262 size=1024
1263 system=system
1264 tags=system.iocache.tags
1265 tgts_per_mshr=12
1266 two_queue=false
1267 write_buffers=8
1268 cpu_side=system.iobus.master[25]
1269 mem_side=system.membus.slave[2]
1270
1271 [system.iocache.tags]
1272 type=LRU
1273 assoc=8
1274 block_size=64
1275 clk_domain=system.clk_domain
1276 eventq_index=0
1277 hit_latency=50
1278 sequential_access=false
1279 size=1024
1280
1281 [system.l2c]
1282 type=BaseCache
1283 children=tags
1284 addr_ranges=0:18446744073709551615
1285 assoc=8
1286 clk_domain=system.cpu_clk_domain
1287 eventq_index=0
1288 forward_snoops=true
1289 hit_latency=20
1290 is_top_level=false
1291 max_miss_count=0
1292 mshrs=20
1293 prefetch_on_access=false
1294 prefetcher=Null
1295 response_latency=20
1296 sequential_access=false
1297 size=4194304
1298 system=system
1299 tags=system.l2c.tags
1300 tgts_per_mshr=12
1301 two_queue=false
1302 write_buffers=8
1303 cpu_side=system.toL2Bus.master[0]
1304 mem_side=system.membus.slave[1]
1305
1306 [system.l2c.tags]
1307 type=LRU
1308 assoc=8
1309 block_size=64
1310 clk_domain=system.cpu_clk_domain
1311 eventq_index=0
1312 hit_latency=20
1313 sequential_access=false
1314 size=4194304
1315
1316 [system.membus]
1317 type=CoherentBus
1318 children=badaddr_responder
1319 clk_domain=system.clk_domain
1320 eventq_index=0
1321 header_cycles=1
1322 system=system
1323 use_default_range=false
1324 width=8
1325 default=system.membus.badaddr_responder.pio
1326 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
1327 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
1328
1329 [system.membus.badaddr_responder]
1330 type=IsaFake
1331 clk_domain=system.clk_domain
1332 eventq_index=0
1333 fake_mem=false
1334 pio_addr=0
1335 pio_latency=100000
1336 pio_size=8
1337 ret_bad_addr=true
1338 ret_data16=65535
1339 ret_data32=4294967295
1340 ret_data64=18446744073709551615
1341 ret_data8=255
1342 system=system
1343 update_data=false
1344 warn_access=warn
1345 pio=system.membus.default
1346
1347 [system.physmem]
1348 type=DRAMCtrl
1349 activation_limit=4
1350 addr_mapping=RoRaBaChCo
1351 banks_per_rank=8
1352 burst_length=8
1353 channels=1
1354 clk_domain=system.clk_domain
1355 conf_table_reported=true
1356 device_bus_width=8
1357 device_rowbuffer_size=1024
1358 devices_per_rank=8
1359 eventq_index=0
1360 in_addr_map=true
1361 max_accesses_per_row=16
1362 mem_sched_policy=frfcfs
1363 min_writes_per_switch=16
1364 null=false
1365 page_policy=open_adaptive
1366 range=0:134217727
1367 ranks_per_channel=2
1368 read_buffer_size=32
1369 static_backend_latency=10000
1370 static_frontend_latency=10000
1371 tBURST=5000
1372 tCK=1250
1373 tCL=13750
1374 tRAS=35000
1375 tRCD=13750
1376 tREFI=7800000
1377 tRFC=260000
1378 tRP=13750
1379 tRRD=6000
1380 tRTP=7500
1381 tRTW=2500
1382 tWR=15000
1383 tWTR=7500
1384 tXAW=30000
1385 write_buffer_size=64
1386 write_high_thresh_perc=85
1387 write_low_thresh_perc=50
1388 port=system.membus.master[6]
1389
1390 [system.realview]
1391 type=RealView
1392 children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
1393 eventq_index=0
1394 intrctrl=system.intrctrl
1395 max_mem_size=268435456
1396 mem_start_addr=0
1397 pci_cfg_base=0
1398 system=system
1399
1400 [system.realview.a9scu]
1401 type=A9SCU
1402 clk_domain=system.clk_domain
1403 eventq_index=0
1404 pio_addr=520093696
1405 pio_latency=100000
1406 system=system
1407 pio=system.membus.master[4]
1408
1409 [system.realview.aaci_fake]
1410 type=AmbaFake
1411 amba_id=0
1412 clk_domain=system.clk_domain
1413 eventq_index=0
1414 ignore_access=false
1415 pio_addr=268451840
1416 pio_latency=100000
1417 system=system
1418 pio=system.iobus.master[21]
1419
1420 [system.realview.cf_ctrl]
1421 type=IdeController
1422 BAR0=402653184
1423 BAR0LegacyIO=true
1424 BAR0Size=16
1425 BAR1=402653440
1426 BAR1LegacyIO=true
1427 BAR1Size=1
1428 BAR2=1
1429 BAR2LegacyIO=false
1430 BAR2Size=8
1431 BAR3=1
1432 BAR3LegacyIO=false
1433 BAR3Size=4
1434 BAR4=1
1435 BAR4LegacyIO=false
1436 BAR4Size=16
1437 BAR5=1
1438 BAR5LegacyIO=false
1439 BAR5Size=0
1440 BIST=0
1441 CacheLineSize=0
1442 CapabilityPtr=0
1443 CardbusCIS=0
1444 ClassCode=1
1445 Command=1
1446 DeviceID=28945
1447 ExpansionROM=0
1448 HeaderType=0
1449 InterruptLine=31
1450 InterruptPin=1
1451 LatencyTimer=0
1452 MSICAPBaseOffset=0
1453 MSICAPCapId=0
1454 MSICAPMaskBits=0
1455 MSICAPMsgAddr=0
1456 MSICAPMsgCtrl=0
1457 MSICAPMsgData=0
1458 MSICAPMsgUpperAddr=0
1459 MSICAPNextCapability=0
1460 MSICAPPendingBits=0
1461 MSIXCAPBaseOffset=0
1462 MSIXCAPCapId=0
1463 MSIXCAPNextCapability=0
1464 MSIXMsgCtrl=0
1465 MSIXPbaOffset=0
1466 MSIXTableOffset=0
1467 MaximumLatency=0
1468 MinimumGrant=0
1469 PMCAPBaseOffset=0
1470 PMCAPCapId=0
1471 PMCAPCapabilities=0
1472 PMCAPCtrlStatus=0
1473 PMCAPNextCapability=0
1474 PXCAPBaseOffset=0
1475 PXCAPCapId=0
1476 PXCAPCapabilities=0
1477 PXCAPDevCap2=0
1478 PXCAPDevCapabilities=0
1479 PXCAPDevCtrl=0
1480 PXCAPDevCtrl2=0
1481 PXCAPDevStatus=0
1482 PXCAPLinkCap=0
1483 PXCAPLinkCtrl=0
1484 PXCAPLinkStatus=0
1485 PXCAPNextCapability=0
1486 ProgIF=133
1487 Revision=0
1488 Status=640
1489 SubClassCode=1
1490 SubsystemID=0
1491 SubsystemVendorID=0
1492 VendorID=32902
1493 clk_domain=system.clk_domain
1494 config_latency=20000
1495 ctrl_offset=2
1496 disks=system.cf0
1497 eventq_index=0
1498 io_shift=1
1499 pci_bus=2
1500 pci_dev=7
1501 pci_func=0
1502 pio_latency=30000
1503 platform=system.realview
1504 system=system
1505 config=system.iobus.master[8]
1506 dma=system.iobus.slave[2]
1507 pio=system.iobus.master[7]
1508
1509 [system.realview.clcd]
1510 type=Pl111
1511 amba_id=1315089
1512 clk_domain=system.clk_domain
1513 enable_capture=true
1514 eventq_index=0
1515 gic=system.realview.gic
1516 int_num=55
1517 pio_addr=268566528
1518 pio_latency=10000
1519 pixel_clock=41667
1520 system=system
1521 vnc=system.vncserver
1522 dma=system.iobus.slave[1]
1523 pio=system.iobus.master[4]
1524
1525 [system.realview.dmac_fake]
1526 type=AmbaFake
1527 amba_id=0
1528 clk_domain=system.clk_domain
1529 eventq_index=0
1530 ignore_access=false
1531 pio_addr=268632064
1532 pio_latency=100000
1533 system=system
1534 pio=system.iobus.master[9]
1535
1536 [system.realview.flash_fake]
1537 type=IsaFake
1538 clk_domain=system.clk_domain
1539 eventq_index=0
1540 fake_mem=true
1541 pio_addr=1073741824
1542 pio_latency=100000
1543 pio_size=536870912
1544 ret_bad_addr=false
1545 ret_data16=65535
1546 ret_data32=4294967295
1547 ret_data64=18446744073709551615
1548 ret_data8=255
1549 system=system
1550 update_data=false
1551 warn_access=
1552 pio=system.iobus.master[24]
1553
1554 [system.realview.gic]
1555 type=Pl390
1556 clk_domain=system.clk_domain
1557 cpu_addr=520093952
1558 cpu_pio_delay=10000
1559 dist_addr=520097792
1560 dist_pio_delay=10000
1561 eventq_index=0
1562 int_latency=10000
1563 it_lines=128
1564 msix_addr=0
1565 platform=system.realview
1566 system=system
1567 pio=system.membus.master[2]
1568
1569 [system.realview.gpio0_fake]
1570 type=AmbaFake
1571 amba_id=0
1572 clk_domain=system.clk_domain
1573 eventq_index=0
1574 ignore_access=false
1575 pio_addr=268513280
1576 pio_latency=100000
1577 system=system
1578 pio=system.iobus.master[16]
1579
1580 [system.realview.gpio1_fake]
1581 type=AmbaFake
1582 amba_id=0
1583 clk_domain=system.clk_domain
1584 eventq_index=0
1585 ignore_access=false
1586 pio_addr=268517376
1587 pio_latency=100000
1588 system=system
1589 pio=system.iobus.master[17]
1590
1591 [system.realview.gpio2_fake]
1592 type=AmbaFake
1593 amba_id=0
1594 clk_domain=system.clk_domain
1595 eventq_index=0
1596 ignore_access=false
1597 pio_addr=268521472
1598 pio_latency=100000
1599 system=system
1600 pio=system.iobus.master[18]
1601
1602 [system.realview.kmi0]
1603 type=Pl050
1604 amba_id=1314896
1605 clk_domain=system.clk_domain
1606 eventq_index=0
1607 gic=system.realview.gic
1608 int_delay=1000000
1609 int_num=52
1610 is_mouse=false
1611 pio_addr=268460032
1612 pio_latency=100000
1613 system=system
1614 vnc=system.vncserver
1615 pio=system.iobus.master[5]
1616
1617 [system.realview.kmi1]
1618 type=Pl050
1619 amba_id=1314896
1620 clk_domain=system.clk_domain
1621 eventq_index=0
1622 gic=system.realview.gic
1623 int_delay=1000000
1624 int_num=53
1625 is_mouse=true
1626 pio_addr=268464128
1627 pio_latency=100000
1628 system=system
1629 vnc=system.vncserver
1630 pio=system.iobus.master[6]
1631
1632 [system.realview.l2x0_fake]
1633 type=IsaFake
1634 clk_domain=system.clk_domain
1635 eventq_index=0
1636 fake_mem=false
1637 pio_addr=520101888
1638 pio_latency=100000
1639 pio_size=4095
1640 ret_bad_addr=false
1641 ret_data16=65535
1642 ret_data32=4294967295
1643 ret_data64=18446744073709551615
1644 ret_data8=255
1645 system=system
1646 update_data=false
1647 warn_access=
1648 pio=system.membus.master[3]
1649
1650 [system.realview.local_cpu_timer]
1651 type=CpuLocalTimer
1652 clk_domain=system.clk_domain
1653 eventq_index=0
1654 gic=system.realview.gic
1655 int_num_timer=29
1656 int_num_watchdog=30
1657 pio_addr=520095232
1658 pio_latency=100000
1659 system=system
1660 pio=system.membus.master[5]
1661
1662 [system.realview.mmc_fake]
1663 type=AmbaFake
1664 amba_id=0
1665 clk_domain=system.clk_domain
1666 eventq_index=0
1667 ignore_access=false
1668 pio_addr=268455936
1669 pio_latency=100000
1670 system=system
1671 pio=system.iobus.master[22]
1672
1673 [system.realview.nvmem]
1674 type=SimpleMemory
1675 bandwidth=73.000000
1676 clk_domain=system.clk_domain
1677 conf_table_reported=false
1678 eventq_index=0
1679 in_addr_map=true
1680 latency=30000
1681 latency_var=0
1682 null=false
1683 range=2147483648:2214592511
1684 port=system.membus.master[1]
1685
1686 [system.realview.realview_io]
1687 type=RealViewCtrl
1688 clk_domain=system.clk_domain
1689 eventq_index=0
1690 idreg=0
1691 pio_addr=268435456
1692 pio_latency=100000
1693 proc_id0=201326592
1694 proc_id1=201327138
1695 system=system
1696 pio=system.iobus.master[1]
1697
1698 [system.realview.rtc]
1699 type=PL031
1700 amba_id=3412017
1701 clk_domain=system.clk_domain
1702 eventq_index=0
1703 gic=system.realview.gic
1704 int_delay=100000
1705 int_num=42
1706 pio_addr=268529664
1707 pio_latency=100000
1708 system=system
1709 time=Thu Jan  1 00:00:00 2009
1710 pio=system.iobus.master[23]
1711
1712 [system.realview.sci_fake]
1713 type=AmbaFake
1714 amba_id=0
1715 clk_domain=system.clk_domain
1716 eventq_index=0
1717 ignore_access=false
1718 pio_addr=268492800
1719 pio_latency=100000
1720 system=system
1721 pio=system.iobus.master[20]
1722
1723 [system.realview.smc_fake]
1724 type=AmbaFake
1725 amba_id=0
1726 clk_domain=system.clk_domain
1727 eventq_index=0
1728 ignore_access=false
1729 pio_addr=269357056
1730 pio_latency=100000
1731 system=system
1732 pio=system.iobus.master[13]
1733
1734 [system.realview.sp810_fake]
1735 type=AmbaFake
1736 amba_id=0
1737 clk_domain=system.clk_domain
1738 eventq_index=0
1739 ignore_access=true
1740 pio_addr=268439552
1741 pio_latency=100000
1742 system=system
1743 pio=system.iobus.master[14]
1744
1745 [system.realview.ssp_fake]
1746 type=AmbaFake
1747 amba_id=0
1748 clk_domain=system.clk_domain
1749 eventq_index=0
1750 ignore_access=false
1751 pio_addr=268488704
1752 pio_latency=100000
1753 system=system
1754 pio=system.iobus.master[19]
1755
1756 [system.realview.timer0]
1757 type=Sp804
1758 amba_id=1316868
1759 clk_domain=system.clk_domain
1760 clock0=1000000
1761 clock1=1000000
1762 eventq_index=0
1763 gic=system.realview.gic
1764 int_num0=36
1765 int_num1=36
1766 pio_addr=268505088
1767 pio_latency=100000
1768 system=system
1769 pio=system.iobus.master[2]
1770
1771 [system.realview.timer1]
1772 type=Sp804
1773 amba_id=1316868
1774 clk_domain=system.clk_domain
1775 clock0=1000000
1776 clock1=1000000
1777 eventq_index=0
1778 gic=system.realview.gic
1779 int_num0=37
1780 int_num1=37
1781 pio_addr=268509184
1782 pio_latency=100000
1783 system=system
1784 pio=system.iobus.master[3]
1785
1786 [system.realview.uart]
1787 type=Pl011
1788 clk_domain=system.clk_domain
1789 end_on_eot=false
1790 eventq_index=0
1791 gic=system.realview.gic
1792 int_delay=100000
1793 int_num=44
1794 pio_addr=268472320
1795 pio_latency=100000
1796 platform=system.realview
1797 system=system
1798 terminal=system.terminal
1799 pio=system.iobus.master[0]
1800
1801 [system.realview.uart1_fake]
1802 type=AmbaFake
1803 amba_id=0
1804 clk_domain=system.clk_domain
1805 eventq_index=0
1806 ignore_access=false
1807 pio_addr=268476416
1808 pio_latency=100000
1809 system=system
1810 pio=system.iobus.master[10]
1811
1812 [system.realview.uart2_fake]
1813 type=AmbaFake
1814 amba_id=0
1815 clk_domain=system.clk_domain
1816 eventq_index=0
1817 ignore_access=false
1818 pio_addr=268480512
1819 pio_latency=100000
1820 system=system
1821 pio=system.iobus.master[11]
1822
1823 [system.realview.uart3_fake]
1824 type=AmbaFake
1825 amba_id=0
1826 clk_domain=system.clk_domain
1827 eventq_index=0
1828 ignore_access=false
1829 pio_addr=268484608
1830 pio_latency=100000
1831 system=system
1832 pio=system.iobus.master[12]
1833
1834 [system.realview.watchdog_fake]
1835 type=AmbaFake
1836 amba_id=0
1837 clk_domain=system.clk_domain
1838 eventq_index=0
1839 ignore_access=false
1840 pio_addr=268500992
1841 pio_latency=100000
1842 system=system
1843 pio=system.iobus.master[15]
1844
1845 [system.terminal]
1846 type=Terminal
1847 eventq_index=0
1848 intr_control=system.intrctrl
1849 number=0
1850 output=true
1851 port=3456
1852
1853 [system.toL2Bus]
1854 type=CoherentBus
1855 clk_domain=system.cpu_clk_domain
1856 eventq_index=0
1857 header_cycles=1
1858 system=system
1859 use_default_range=false
1860 width=8
1861 master=system.l2c.cpu_side
1862 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
1863
1864 [system.vncserver]
1865 type=VncServer
1866 eventq_index=0
1867 frame_capture=false
1868 number=0
1869 port=5900
1870
1871 [system.voltage_domain]
1872 type=VoltageDomain
1873 eventq_index=0
1874 voltage=1.000000
1875