2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.541288 # Number of seconds simulated
4 sim_ticks 2541288206500 # Number of ticks simulated
5 final_tick 2541288206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 64704 # Simulator instruction rate (inst/s)
8 host_op_rate 83256 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2726411009 # Simulator tick rate (ticks/s)
10 host_mem_usage 408332 # Number of bytes of host memory used
11 host_seconds 932.10 # Real time elapsed on the host
12 sim_insts 60310239 # Number of instructions simulated
13 sim_ops 77602695 # Number of ops (including micro ops) simulated
14 system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
15 system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
16 system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
17 system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
18 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
19 system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
20 system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
21 system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
22 system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
23 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
24 system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
25 system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
26 system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
27 system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
28 system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
29 system.physmem.bytes_read::cpu0.inst 503232 # Number of bytes read from this memory
30 system.physmem.bytes_read::cpu0.data 4160720 # Number of bytes read from this memory
31 system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
32 system.physmem.bytes_read::cpu1.inst 298048 # Number of bytes read from this memory
33 system.physmem.bytes_read::cpu1.data 4933980 # Number of bytes read from this memory
34 system.physmem.bytes_read::total 131009132 # Number of bytes read from this memory
35 system.physmem.bytes_inst_read::cpu0.inst 503232 # Number of instructions bytes read from this memory
36 system.physmem.bytes_inst_read::cpu1.inst 298048 # Number of instructions bytes read from this memory
37 system.physmem.bytes_inst_read::total 801280 # Number of instructions bytes read from this memory
38 system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory
39 system.physmem.bytes_written::cpu0.data 1345260 # Number of bytes written to this memory
40 system.physmem.bytes_written::cpu1.data 1670852 # Number of bytes written to this memory
41 system.physmem.bytes_written::total 6802288 # Number of bytes written to this memory
42 system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu0.inst 7863 # Number of read requests responded to by this memory
46 system.physmem.num_reads::cpu0.data 65045 # Number of read requests responded to by this memory
47 system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
48 system.physmem.num_reads::cpu1.inst 4657 # Number of read requests responded to by this memory
49 system.physmem.num_reads::cpu1.data 77100 # Number of read requests responded to by this memory
50 system.physmem.num_reads::total 15293522 # Number of read requests responded to by this memory
51 system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory
52 system.physmem.num_writes::cpu0.data 336315 # Number of write requests responded to by this memory
53 system.physmem.num_writes::cpu1.data 417713 # Number of write requests responded to by this memory
54 system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory
55 system.physmem.bw_read::realview.clcd 47657140 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.dtb.walker 680 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu0.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu0.inst 198022 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu0.data 1637248 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::cpu1.inst 117282 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::cpu1.data 1941527 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_read::total 51552253 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu0.inst 198022 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::cpu1.inst 117282 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_inst_read::total 315305 # Instruction read bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::writebacks 1489865 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu0.data 529361 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::cpu1.data 657482 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_write::total 2676709 # Write bandwidth from this memory (bytes/s)
71 system.physmem.bw_total::writebacks 1489865 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::realview.clcd 47657140 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.inst 198022 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu0.data 2166610 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.inst 117282 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.data 2599009 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::total 54228961 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.readReqs 15293522 # Total number of read requests seen
82 system.physmem.writeReqs 813187 # Total number of write requests seen
83 system.physmem.cpureqs 218489 # Reqs generatd by CPU via cache - shady
84 system.physmem.bytesRead 978785408 # Total number of bytes read from memory
85 system.physmem.bytesWritten 52043968 # Total number of bytes written to memory
86 system.physmem.bytesConsumedRd 131009132 # bytesRead derated as per pkt->getSize()
87 system.physmem.bytesConsumedWr 6802288 # bytesWritten derated as per pkt->getSize()
88 system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
89 system.physmem.neitherReadNorWrite 4667 # Reqs where no action is needed
90 system.physmem.perBankRdReqs::0 956238 # Track reads on a per bank basis
91 system.physmem.perBankRdReqs::1 955736 # Track reads on a per bank basis
92 system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis
93 system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis
94 system.physmem.perBankRdReqs::4 956266 # Track reads on a per bank basis
95 system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis
96 system.physmem.perBankRdReqs::6 955566 # Track reads on a per bank basis
97 system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis
98 system.physmem.perBankRdReqs::8 956096 # Track reads on a per bank basis
99 system.physmem.perBankRdReqs::9 955614 # Track reads on a per bank basis
100 system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis
101 system.physmem.perBankRdReqs::11 955925 # Track reads on a per bank basis
102 system.physmem.perBankRdReqs::12 956031 # Track reads on a per bank basis
103 system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis
104 system.physmem.perBankRdReqs::14 955324 # Track reads on a per bank basis
105 system.physmem.perBankRdReqs::15 955982 # Track reads on a per bank basis
106 system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis
107 system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis
108 system.physmem.perBankWrReqs::2 50430 # Track writes on a per bank basis
109 system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis
110 system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis
111 system.physmem.perBankWrReqs::5 50187 # Track writes on a per bank basis
112 system.physmem.perBankWrReqs::6 50285 # Track writes on a per bank basis
113 system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
114 system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis
115 system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
116 system.physmem.perBankWrReqs::10 50809 # Track writes on a per bank basis
117 system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis
118 system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis
119 system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis
120 system.physmem.perBankWrReqs::14 50633 # Track writes on a per bank basis
121 system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis
122 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
123 system.physmem.numWrRetry 1856598 # Number of times wr buffer was full causing retry
124 system.physmem.totGap 2541287063000 # Total gap between requests
125 system.physmem.readPktSize::0 0 # Categorize read packet sizes
126 system.physmem.readPktSize::1 0 # Categorize read packet sizes
127 system.physmem.readPktSize::2 43 # Categorize read packet sizes
128 system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
129 system.physmem.readPktSize::4 0 # Categorize read packet sizes
130 system.physmem.readPktSize::5 0 # Categorize read packet sizes
131 system.physmem.readPktSize::6 154663 # Categorize read packet sizes
132 system.physmem.writePktSize::0 0 # Categorize write packet sizes
133 system.physmem.writePktSize::1 0 # Categorize write packet sizes
134 system.physmem.writePktSize::2 754028 # Categorize write packet sizes
135 system.physmem.writePktSize::3 0 # Categorize write packet sizes
136 system.physmem.writePktSize::4 0 # Categorize write packet sizes
137 system.physmem.writePktSize::5 0 # Categorize write packet sizes
138 system.physmem.writePktSize::6 59159 # Categorize write packet sizes
139 system.physmem.rdQLenPdf::0 1054970 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::1 992041 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::2 961924 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::3 3604913 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::4 2718058 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::5 2722873 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::6 2698919 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::7 60155 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::9 109994 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::10 160422 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::11 109940 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::12 10067 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::13 9978 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::14 10954 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::15 8840 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
171 system.physmem.wrQLenPdf::0 2749 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::3 2931 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::4 2934 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::6 2920 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::7 2911 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::8 2910 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::11 35356 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::12 35346 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::16 35291 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::18 35258 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::22 35219 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::23 32757 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::24 32647 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::25 32608 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::26 32530 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::27 32516 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::28 32512 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::29 32503 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::30 32493 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::31 32483 # What write queue length does an incoming req see
203 system.physmem.totQLat 346675714750 # Total cycles spent in queuing delays
204 system.physmem.totMemAccLat 439850413500 # Sum of mem lat for all requests
205 system.physmem.totBusLat 76467555000 # Total cycles spent in databus access
206 system.physmem.totBankLat 16707143750 # Total cycles spent in bank access
207 system.physmem.avgQLat 22668.16 # Average queueing delay per request
208 system.physmem.avgBankLat 1092.43 # Average bank access latency per request
209 system.physmem.avgBusLat 5000.00 # Average bus latency per request
210 system.physmem.avgMemAccLat 28760.59 # Average memory access latency
211 system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s
212 system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s
213 system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s
214 system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
215 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
216 system.physmem.busUtil 3.17 # Data bus utilization in percentage
217 system.physmem.avgRdQLen 0.17 # Average read queue length over time
218 system.physmem.avgWrQLen 1.14 # Average write queue length over time
219 system.physmem.readRowHits 15218363 # Number of row buffer hits during reads
220 system.physmem.writeRowHits 794663 # Number of row buffer hits during writes
221 system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
222 system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes
223 system.physmem.avgGap 157778.17 # Average gap between requests
224 system.l2c.replacements 64431 # number of replacements
225 system.l2c.tagsinuse 51403.772051 # Cycle average of tags in use
226 system.l2c.total_refs 1904252 # Total number of references to valid blocks.
227 system.l2c.sampled_refs 129822 # Sample count of references to valid blocks.
228 system.l2c.avg_refs 14.668176 # Average number of references to valid blocks.
229 system.l2c.warmup_cycle 2505297860000 # Cycle when the warmup percentage was hit.
230 system.l2c.occ_blocks::writebacks 36947.477101 # Average occupied blocks per requestor
231 system.l2c.occ_blocks::cpu0.dtb.walker 17.181776 # Average occupied blocks per requestor
232 system.l2c.occ_blocks::cpu0.itb.walker 0.004228 # Average occupied blocks per requestor
233 system.l2c.occ_blocks::cpu0.inst 5147.781121 # Average occupied blocks per requestor
234 system.l2c.occ_blocks::cpu0.data 3278.488158 # Average occupied blocks per requestor
235 system.l2c.occ_blocks::cpu1.dtb.walker 8.683561 # Average occupied blocks per requestor
236 system.l2c.occ_blocks::cpu1.inst 3058.770363 # Average occupied blocks per requestor
237 system.l2c.occ_blocks::cpu1.data 2945.385742 # Average occupied blocks per requestor
238 system.l2c.occ_percent::writebacks 0.563774 # Average percentage of cache occupancy
239 system.l2c.occ_percent::cpu0.dtb.walker 0.000262 # Average percentage of cache occupancy
240 system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
241 system.l2c.occ_percent::cpu0.inst 0.078549 # Average percentage of cache occupancy
242 system.l2c.occ_percent::cpu0.data 0.050026 # Average percentage of cache occupancy
243 system.l2c.occ_percent::cpu1.dtb.walker 0.000133 # Average percentage of cache occupancy
244 system.l2c.occ_percent::cpu1.inst 0.046673 # Average percentage of cache occupancy
245 system.l2c.occ_percent::cpu1.data 0.044943 # Average percentage of cache occupancy
246 system.l2c.occ_percent::total 0.784359 # Average percentage of cache occupancy
247 system.l2c.ReadReq_hits::cpu0.dtb.walker 32227 # number of ReadReq hits
248 system.l2c.ReadReq_hits::cpu0.itb.walker 7171 # number of ReadReq hits
249 system.l2c.ReadReq_hits::cpu0.inst 490580 # number of ReadReq hits
250 system.l2c.ReadReq_hits::cpu0.data 213578 # number of ReadReq hits
251 system.l2c.ReadReq_hits::cpu1.dtb.walker 30476 # number of ReadReq hits
252 system.l2c.ReadReq_hits::cpu1.itb.walker 6774 # number of ReadReq hits
253 system.l2c.ReadReq_hits::cpu1.inst 480341 # number of ReadReq hits
254 system.l2c.ReadReq_hits::cpu1.data 174067 # number of ReadReq hits
255 system.l2c.ReadReq_hits::total 1435214 # number of ReadReq hits
256 system.l2c.Writeback_hits::writebacks 608440 # number of Writeback hits
257 system.l2c.Writeback_hits::total 608440 # number of Writeback hits
258 system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits
259 system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
260 system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits
261 system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
262 system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
263 system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
264 system.l2c.ReadExReq_hits::cpu0.data 57838 # number of ReadExReq hits
265 system.l2c.ReadExReq_hits::cpu1.data 55045 # number of ReadExReq hits
266 system.l2c.ReadExReq_hits::total 112883 # number of ReadExReq hits
267 system.l2c.demand_hits::cpu0.dtb.walker 32227 # number of demand (read+write) hits
268 system.l2c.demand_hits::cpu0.itb.walker 7171 # number of demand (read+write) hits
269 system.l2c.demand_hits::cpu0.inst 490580 # number of demand (read+write) hits
270 system.l2c.demand_hits::cpu0.data 271416 # number of demand (read+write) hits
271 system.l2c.demand_hits::cpu1.dtb.walker 30476 # number of demand (read+write) hits
272 system.l2c.demand_hits::cpu1.itb.walker 6774 # number of demand (read+write) hits
273 system.l2c.demand_hits::cpu1.inst 480341 # number of demand (read+write) hits
274 system.l2c.demand_hits::cpu1.data 229112 # number of demand (read+write) hits
275 system.l2c.demand_hits::total 1548097 # number of demand (read+write) hits
276 system.l2c.overall_hits::cpu0.dtb.walker 32227 # number of overall hits
277 system.l2c.overall_hits::cpu0.itb.walker 7171 # number of overall hits
278 system.l2c.overall_hits::cpu0.inst 490580 # number of overall hits
279 system.l2c.overall_hits::cpu0.data 271416 # number of overall hits
280 system.l2c.overall_hits::cpu1.dtb.walker 30476 # number of overall hits
281 system.l2c.overall_hits::cpu1.itb.walker 6774 # number of overall hits
282 system.l2c.overall_hits::cpu1.inst 480341 # number of overall hits
283 system.l2c.overall_hits::cpu1.data 229112 # number of overall hits
284 system.l2c.overall_hits::total 1548097 # number of overall hits
285 system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses
286 system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
287 system.l2c.ReadReq_misses::cpu0.inst 7754 # number of ReadReq misses
288 system.l2c.ReadReq_misses::cpu0.data 6099 # number of ReadReq misses
289 system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
290 system.l2c.ReadReq_misses::cpu1.inst 4662 # number of ReadReq misses
291 system.l2c.ReadReq_misses::cpu1.data 4629 # number of ReadReq misses
292 system.l2c.ReadReq_misses::total 23185 # number of ReadReq misses
293 system.l2c.UpgradeReq_misses::cpu0.data 1530 # number of UpgradeReq misses
294 system.l2c.UpgradeReq_misses::cpu1.data 1369 # number of UpgradeReq misses
295 system.l2c.UpgradeReq_misses::total 2899 # number of UpgradeReq misses
296 system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
297 system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
298 system.l2c.ReadExReq_misses::cpu0.data 59920 # number of ReadExReq misses
299 system.l2c.ReadExReq_misses::cpu1.data 73280 # number of ReadExReq misses
300 system.l2c.ReadExReq_misses::total 133200 # number of ReadExReq misses
301 system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
302 system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
303 system.l2c.demand_misses::cpu0.inst 7754 # number of demand (read+write) misses
304 system.l2c.demand_misses::cpu0.data 66019 # number of demand (read+write) misses
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542 system.l2c.WriteReq_mshr_uncacheable_latency::total 23619915975 # number of WriteReq MSHR uncacheable cycles
543 system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles
544 system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles
545 system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
546 system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
547 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050830 # number of overall MSHR uncacheable cycles
548 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94648810575 # number of overall MSHR uncacheable cycles
549 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95938677921 # number of overall MSHR uncacheable cycles
550 system.l2c.overall_mshr_uncacheable_latency::total 190592539326 # number of overall MSHR uncacheable cycles
551 system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for ReadReq accesses
552 system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses
553 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for ReadReq accesses
554 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027591 # mshr miss rate for ReadReq accesses
555 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for ReadReq accesses
556 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for ReadReq accesses
557 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025787 # mshr miss rate for ReadReq accesses
558 system.l2c.ReadReq_mshr_miss_rate::total 0.015847 # mshr miss rate for ReadReq accesses
559 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988372 # mshr miss rate for UpgradeReq accesses
560 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988448 # mshr miss rate for UpgradeReq accesses
561 system.l2c.UpgradeReq_mshr_miss_rate::total 0.988408 # mshr miss rate for UpgradeReq accesses
562 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
563 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses
564 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508840 # mshr miss rate for ReadExReq accesses
565 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571050 # mshr miss rate for ReadExReq accesses
566 system.l2c.ReadExReq_mshr_miss_rate::total 0.541281 # mshr miss rate for ReadExReq accesses
567 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for demand accesses
568 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses
569 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for demand accesses
570 system.l2c.demand_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for demand accesses
571 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for demand accesses
572 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for demand accesses
573 system.l2c.demand_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for demand accesses
574 system.l2c.demand_mshr_miss_rate::total 0.091706 # mshr miss rate for demand accesses
575 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for overall accesses
576 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses
577 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for overall accesses
578 system.l2c.overall_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for overall accesses
579 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for overall accesses
580 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for overall accesses
581 system.l2c.overall_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for overall accesses
582 system.l2c.overall_mshr_miss_rate::total 0.091706 # mshr miss rate for overall accesses
583 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average ReadReq mshr miss latency
584 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency
585 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average ReadReq mshr miss latency
586 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44257.251609 # average ReadReq mshr miss latency
587 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average ReadReq mshr miss latency
588 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average ReadReq mshr miss latency
589 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46034.955512 # average ReadReq mshr miss latency
590 system.l2c.ReadReq_avg_mshr_miss_latency::total 44333.289689 # average ReadReq mshr miss latency
591 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
592 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10052.097882 # average UpgradeReq mshr miss latency
593 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.130045 # average UpgradeReq mshr miss latency
594 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
595 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
596 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39846.195494 # average ReadExReq mshr miss latency
597 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.299468 # average ReadExReq mshr miss latency
598 system.l2c.ReadExReq_avg_mshr_miss_latency::total 38438.418461 # average ReadExReq mshr miss latency
599 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency
600 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency
601 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency
602 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency
603 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency
604 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency
605 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency
606 system.l2c.demand_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency
607 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency
608 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency
609 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency
610 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency
611 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency
612 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency
613 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency
614 system.l2c.overall_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency
615 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
616 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
617 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
618 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
619 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
620 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
621 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
622 system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
623 system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
624 system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
625 system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
626 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
627 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
628 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
629 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
630 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
631 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
632 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
633 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
634 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
635 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
636 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
637 system.cpu0.branchPred.lookups 7613725 # Number of BP lookups
638 system.cpu0.branchPred.condPredicted 6072642 # Number of conditional branches predicted
639 system.cpu0.branchPred.condIncorrect 379429 # Number of conditional branches incorrect
640 system.cpu0.branchPred.BTBLookups 4956500 # Number of BTB lookups
641 system.cpu0.branchPred.BTBHits 4052223 # Number of BTB hits
642 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
643 system.cpu0.branchPred.BTBHitPct 81.755735 # BTB Hit Percentage
644 system.cpu0.branchPred.usedRAS 731018 # Number of times the RAS was used to get a target.
645 system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions.
646 system.cpu0.dtb.inst_hits 0 # ITB inst hits
647 system.cpu0.dtb.inst_misses 0 # ITB inst misses
648 system.cpu0.dtb.read_hits 26054269 # DTB read hits
649 system.cpu0.dtb.read_misses 40148 # DTB read misses
650 system.cpu0.dtb.write_hits 5888543 # DTB write hits
651 system.cpu0.dtb.write_misses 9328 # DTB write misses
652 system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
653 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
654 system.cpu0.dtb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID
655 system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
656 system.cpu0.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB
657 system.cpu0.dtb.align_faults 1467 # Number of TLB faults due to alignment restrictions
658 system.cpu0.dtb.prefetch_faults 272 # Number of TLB faults due to prefetch
659 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
660 system.cpu0.dtb.perms_faults 635 # Number of TLB faults due to permissions restrictions
661 system.cpu0.dtb.read_accesses 26094417 # DTB read accesses
662 system.cpu0.dtb.write_accesses 5897871 # DTB write accesses
663 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
664 system.cpu0.dtb.hits 31942812 # DTB hits
665 system.cpu0.dtb.misses 49476 # DTB misses
666 system.cpu0.dtb.accesses 31992288 # DTB accesses
667 system.cpu0.itb.inst_hits 6107608 # ITB inst hits
668 system.cpu0.itb.inst_misses 7459 # ITB inst misses
669 system.cpu0.itb.read_hits 0 # DTB read hits
670 system.cpu0.itb.read_misses 0 # DTB read misses
671 system.cpu0.itb.write_hits 0 # DTB write hits
672 system.cpu0.itb.write_misses 0 # DTB write misses
673 system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
674 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
675 system.cpu0.itb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID
676 system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
677 system.cpu0.itb.flush_entries 2620 # Number of entries that have been flushed from TLB
678 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
679 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
680 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
681 system.cpu0.itb.perms_faults 1567 # Number of TLB faults due to permissions restrictions
682 system.cpu0.itb.read_accesses 0 # DTB read accesses
683 system.cpu0.itb.write_accesses 0 # DTB write accesses
684 system.cpu0.itb.inst_accesses 6115067 # ITB inst accesses
685 system.cpu0.itb.hits 6107608 # DTB hits
686 system.cpu0.itb.misses 7459 # DTB misses
687 system.cpu0.itb.accesses 6115067 # DTB accesses
688 system.cpu0.numCycles 239065725 # number of cpu cycles simulated
689 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
690 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
691 system.cpu0.fetch.icacheStallCycles 15475182 # Number of cycles fetch is stalled on an Icache miss
692 system.cpu0.fetch.Insts 47810378 # Number of instructions fetch has processed
693 system.cpu0.fetch.Branches 7613725 # Number of branches that fetch encountered
694 system.cpu0.fetch.predictedBranches 4783241 # Number of branches that fetch has predicted taken
695 system.cpu0.fetch.Cycles 10599303 # Number of cycles fetch has run and was not squashing or blocked
696 system.cpu0.fetch.SquashCycles 2556412 # Number of cycles fetch has spent squashing
697 system.cpu0.fetch.TlbCycles 92588 # Number of cycles fetch has spent waiting for tlb
698 system.cpu0.fetch.BlockedCycles 49524214 # Number of cycles fetch has spent blocked
699 system.cpu0.fetch.MiscStallCycles 1680 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
700 system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain
701 system.cpu0.fetch.PendingTrapStallCycles 51259 # Number of stall cycles due to pending traps
702 system.cpu0.fetch.PendingQuiesceStallCycles 101215 # Number of stall cycles due to pending quiesce instructions
703 system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR
704 system.cpu0.fetch.CacheLines 6105640 # Number of cache lines fetched
705 system.cpu0.fetch.IcacheSquashes 396425 # Number of outstanding Icache misses that were squashed
706 system.cpu0.fetch.ItlbSquashes 3088 # Number of outstanding ITLB misses that were squashed
707 system.cpu0.fetch.rateDist::samples 77615764 # Number of instructions fetched each cycle (Total)
708 system.cpu0.fetch.rateDist::mean 0.762044 # Number of instructions fetched each cycle (Total)
709 system.cpu0.fetch.rateDist::stdev 2.119690 # Number of instructions fetched each cycle (Total)
710 system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
711 system.cpu0.fetch.rateDist::0 67024086 86.35% 86.35% # Number of instructions fetched each cycle (Total)
712 system.cpu0.fetch.rateDist::1 687549 0.89% 87.24% # Number of instructions fetched each cycle (Total)
713 system.cpu0.fetch.rateDist::2 884780 1.14% 88.38% # Number of instructions fetched each cycle (Total)
714 system.cpu0.fetch.rateDist::3 1227446 1.58% 89.96% # Number of instructions fetched each cycle (Total)
715 system.cpu0.fetch.rateDist::4 1139052 1.47% 91.43% # Number of instructions fetched each cycle (Total)
716 system.cpu0.fetch.rateDist::5 576391 0.74% 92.17% # Number of instructions fetched each cycle (Total)
717 system.cpu0.fetch.rateDist::6 1322616 1.70% 93.88% # Number of instructions fetched each cycle (Total)
718 system.cpu0.fetch.rateDist::7 397461 0.51% 94.39% # Number of instructions fetched each cycle (Total)
719 system.cpu0.fetch.rateDist::8 4356383 5.61% 100.00% # Number of instructions fetched each cycle (Total)
720 system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
721 system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
722 system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
723 system.cpu0.fetch.rateDist::total 77615764 # Number of instructions fetched each cycle (Total)
724 system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle
725 system.cpu0.fetch.rate 0.199988 # Number of inst fetches per cycle
726 system.cpu0.decode.IdleCycles 16521961 # Number of cycles decode is idle
727 system.cpu0.decode.BlockedCycles 49260251 # Number of cycles decode is blocked
728 system.cpu0.decode.RunCycles 9602479 # Number of cycles decode is running
729 system.cpu0.decode.UnblockCycles 548826 # Number of cycles decode is unblocking
730 system.cpu0.decode.SquashCycles 1680126 # Number of cycles decode is squashing
731 system.cpu0.decode.BranchResolved 1023427 # Number of times decode resolved a branch
732 system.cpu0.decode.BranchMispred 90450 # Number of times decode detected a branch misprediction
733 system.cpu0.decode.DecodedInsts 56271590 # Number of instructions handled by decode
734 system.cpu0.decode.SquashedInsts 301516 # Number of squashed instructions handled by decode
735 system.cpu0.rename.SquashCycles 1680126 # Number of cycles rename is squashing
736 system.cpu0.rename.IdleCycles 17454704 # Number of cycles rename is idle
737 system.cpu0.rename.BlockCycles 18993172 # Number of cycles rename is blocking
738 system.cpu0.rename.serializeStallCycles 27018669 # count of cycles rename stalled for serializing inst
739 system.cpu0.rename.RunCycles 9147780 # Number of cycles rename is running
740 system.cpu0.rename.UnblockCycles 3319243 # Number of cycles rename is unblocking
741 system.cpu0.rename.RenamedInsts 53454491 # Number of instructions processed by rename
742 system.cpu0.rename.ROBFullEvents 13507 # Number of times rename has blocked due to ROB full
743 system.cpu0.rename.IQFullEvents 621630 # Number of times rename has blocked due to IQ full
744 system.cpu0.rename.LSQFullEvents 2155035 # Number of times rename has blocked due to LSQ full
745 system.cpu0.rename.FullRegisterEvents 566 # Number of times there has been no free registers
746 system.cpu0.rename.RenamedOperands 55623215 # Number of destination operands rename has renamed
747 system.cpu0.rename.RenameLookups 243327513 # Number of register rename lookups that rename has made
748 system.cpu0.rename.int_rename_lookups 243280007 # Number of integer rename lookups
749 system.cpu0.rename.fp_rename_lookups 47506 # Number of floating rename lookups
750 system.cpu0.rename.CommittedMaps 40387894 # Number of HB maps that are committed
751 system.cpu0.rename.UndoneMaps 15235321 # Number of HB maps that are undone due to squashing
752 system.cpu0.rename.serializingInsts 429274 # count of serializing insts renamed
753 system.cpu0.rename.tempSerializingInsts 381163 # count of temporary serializing insts renamed
754 system.cpu0.rename.skidInsts 6745844 # count of insts added to the skid buffer
755 system.cpu0.memDep0.insertedLoads 10343403 # Number of loads inserted to the mem dependence unit.
756 system.cpu0.memDep0.insertedStores 6774259 # Number of stores inserted to the mem dependence unit.
757 system.cpu0.memDep0.conflictingLoads 1062911 # Number of conflicting loads.
758 system.cpu0.memDep0.conflictingStores 1310407 # Number of conflicting stores.
759 system.cpu0.iq.iqInstsAdded 49609262 # Number of instructions added to the IQ (excludes non-spec)
760 system.cpu0.iq.iqNonSpecInstsAdded 1043693 # Number of non-speculative instructions added to the IQ
761 system.cpu0.iq.iqInstsIssued 63170275 # Number of instructions issued
762 system.cpu0.iq.iqSquashedInstsIssued 95774 # Number of squashed instructions issued
763 system.cpu0.iq.iqSquashedInstsExamined 10510467 # Number of squashed instructions iterated over during squash; mainly for profiling
764 system.cpu0.iq.iqSquashedOperandsExamined 26507766 # Number of squashed operands that are examined and possibly removed from graph
765 system.cpu0.iq.iqSquashedNonSpecRemoved 267313 # Number of squashed non-spec instructions that were removed
766 system.cpu0.iq.issued_per_cycle::samples 77615764 # Number of insts issued each cycle
767 system.cpu0.iq.issued_per_cycle::mean 0.813885 # Number of insts issued each cycle
768 system.cpu0.iq.issued_per_cycle::stdev 1.519252 # Number of insts issued each cycle
769 system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
770 system.cpu0.iq.issued_per_cycle::0 54780189 70.58% 70.58% # Number of insts issued each cycle
771 system.cpu0.iq.issued_per_cycle::1 7210578 9.29% 79.87% # Number of insts issued each cycle
772 system.cpu0.iq.issued_per_cycle::2 3685843 4.75% 84.62% # Number of insts issued each cycle
773 system.cpu0.iq.issued_per_cycle::3 3149398 4.06% 88.68% # Number of insts issued each cycle
774 system.cpu0.iq.issued_per_cycle::4 6278761 8.09% 96.76% # Number of insts issued each cycle
775 system.cpu0.iq.issued_per_cycle::5 1404530 1.81% 98.57% # Number of insts issued each cycle
776 system.cpu0.iq.issued_per_cycle::6 809241 1.04% 99.62% # Number of insts issued each cycle
777 system.cpu0.iq.issued_per_cycle::7 231115 0.30% 99.91% # Number of insts issued each cycle
778 system.cpu0.iq.issued_per_cycle::8 66109 0.09% 100.00% # Number of insts issued each cycle
779 system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
780 system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
781 system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
782 system.cpu0.iq.issued_per_cycle::total 77615764 # Number of insts issued each cycle
783 system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
784 system.cpu0.iq.fu_full::IntAlu 29823 0.67% 0.67% # attempts to use FU when none available
785 system.cpu0.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available
786 system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
787 system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
788 system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
789 system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
790 system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
791 system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
792 system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
793 system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
794 system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
795 system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
796 system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
797 system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
798 system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
799 system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
800 system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
801 system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
802 system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
803 system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
804 system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
805 system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
806 system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
807 system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
808 system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
809 system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
810 system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
811 system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
812 system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
813 system.cpu0.iq.fu_full::MemRead 4228133 94.76% 95.42% # attempts to use FU when none available
814 system.cpu0.iq.fu_full::MemWrite 204148 4.58% 100.00% # attempts to use FU when none available
815 system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
816 system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
817 system.cpu0.iq.FU_type_0::No_OpClass 195616 0.31% 0.31% # Type of FU issued
818 system.cpu0.iq.FU_type_0::IntAlu 29937335 47.39% 47.70% # Type of FU issued
819 system.cpu0.iq.FU_type_0::IntMult 46928 0.07% 47.78% # Type of FU issued
820 system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
821 system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
822 system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
823 system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued
824 system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued
825 system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued
826 system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued
827 system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued
828 system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued
829 system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
830 system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
831 system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
832 system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued
833 system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
834 system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
835 system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.78% # Type of FU issued
836 system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued
837 system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
838 system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
839 system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
840 system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
841 system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
842 system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
843 system.cpu0.iq.FU_type_0::SimdFloatMisc 1205 0.00% 47.78% # Type of FU issued
844 system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued
845 system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued
846 system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued
847 system.cpu0.iq.FU_type_0::MemRead 26771956 42.38% 90.16% # Type of FU issued
848 system.cpu0.iq.FU_type_0::MemWrite 6217218 9.84% 100.00% # Type of FU issued
849 system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
850 system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
851 system.cpu0.iq.FU_type_0::total 63170275 # Type of FU issued
852 system.cpu0.iq.rate 0.264238 # Inst issue rate
853 system.cpu0.iq.fu_busy_cnt 4462107 # FU busy when requested
854 system.cpu0.iq.fu_busy_rate 0.070636 # FU busy rate (busy events/executed inst)
855 system.cpu0.iq.int_inst_queue_reads 208551330 # Number of integer instruction queue reads
856 system.cpu0.iq.int_inst_queue_writes 61172484 # Number of integer instruction queue writes
857 system.cpu0.iq.int_inst_queue_wakeup_accesses 44142185 # Number of integer instruction queue wakeup accesses
858 system.cpu0.iq.fp_inst_queue_reads 12154 # Number of floating instruction queue reads
859 system.cpu0.iq.fp_inst_queue_writes 6481 # Number of floating instruction queue writes
860 system.cpu0.iq.fp_inst_queue_wakeup_accesses 5464 # Number of floating instruction queue wakeup accesses
861 system.cpu0.iq.int_alu_accesses 67430354 # Number of integer alu accesses
862 system.cpu0.iq.fp_alu_accesses 6412 # Number of floating point alu accesses
863 system.cpu0.iew.lsq.thread0.forwLoads 323195 # Number of loads that had data forwarded from stores
864 system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
865 system.cpu0.iew.lsq.thread0.squashedLoads 2268860 # Number of loads squashed
866 system.cpu0.iew.lsq.thread0.ignoredResponses 3534 # Number of memory responses ignored because the instruction is squashed
867 system.cpu0.iew.lsq.thread0.memOrderViolation 16121 # Number of memory ordering violations
868 system.cpu0.iew.lsq.thread0.squashedStores 886667 # Number of stores squashed
869 system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
870 system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
871 system.cpu0.iew.lsq.thread0.rescheduledLoads 17166750 # Number of loads that were rescheduled
872 system.cpu0.iew.lsq.thread0.cacheBlocked 367684 # Number of times an access to memory failed due to the cache being blocked
873 system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
874 system.cpu0.iew.iewSquashCycles 1680126 # Number of cycles IEW is squashing
875 system.cpu0.iew.iewBlockCycles 14230285 # Number of cycles IEW is blocking
876 system.cpu0.iew.iewUnblockCycles 233349 # Number of cycles IEW is unblocking
877 system.cpu0.iew.iewDispatchedInsts 50770143 # Number of instructions dispatched to IQ
878 system.cpu0.iew.iewDispSquashedInsts 105944 # Number of squashed instructions skipped by dispatch
879 system.cpu0.iew.iewDispLoadInsts 10343403 # Number of dispatched load instructions
880 system.cpu0.iew.iewDispStoreInsts 6774259 # Number of dispatched store instructions
881 system.cpu0.iew.iewDispNonSpecInsts 742754 # Number of dispatched non-speculative instructions
882 system.cpu0.iew.iewIQFullEvents 56167 # Number of times the IQ has become full, causing a stall
883 system.cpu0.iew.iewLSQFullEvents 3335 # Number of times the LSQ has become full, causing a stall
884 system.cpu0.iew.memOrderViolationEvents 16121 # Number of memory order violations
885 system.cpu0.iew.predictedTakenIncorrect 186307 # Number of branches that were predicted taken incorrectly
886 system.cpu0.iew.predictedNotTakenIncorrect 146952 # Number of branches that were predicted not taken incorrectly
887 system.cpu0.iew.branchMispredicts 333259 # Number of branch mispredicts detected at execute
888 system.cpu0.iew.iewExecutedInsts 62002420 # Number of executed instructions
889 system.cpu0.iew.iewExecLoadInsts 26414016 # Number of load instructions executed
890 system.cpu0.iew.iewExecSquashedInsts 1167855 # Number of squashed instructions skipped in execute
891 system.cpu0.iew.exec_swp 0 # number of swp insts executed
892 system.cpu0.iew.exec_nop 117188 # number of nop insts executed
893 system.cpu0.iew.exec_refs 32573974 # number of memory reference insts executed
894 system.cpu0.iew.exec_branches 6027717 # Number of branches executed
895 system.cpu0.iew.exec_stores 6159958 # Number of stores executed
896 system.cpu0.iew.exec_rate 0.259353 # Inst execution rate
897 system.cpu0.iew.wb_sent 61473665 # cumulative count of insts sent to commit
898 system.cpu0.iew.wb_count 44147649 # cumulative count of insts written-back
899 system.cpu0.iew.wb_producers 24301400 # num instructions producing a value
900 system.cpu0.iew.wb_consumers 44653762 # num instructions consuming a value
901 system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
902 system.cpu0.iew.wb_rate 0.184667 # insts written-back per cycle
903 system.cpu0.iew.wb_fanout 0.544218 # average fanout of values written-back
904 system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
905 system.cpu0.commit.commitSquashedInsts 10356873 # The number of squashed insts skipped by commit
906 system.cpu0.commit.commitNonSpecStalls 776380 # The number of times commit has been forced to stall to communicate backwards
907 system.cpu0.commit.branchMispredicts 290234 # The number of times a branch was mispredicted
908 system.cpu0.commit.committed_per_cycle::samples 75935638 # Number of insts commited each cycle
909 system.cpu0.commit.committed_per_cycle::mean 0.525589 # Number of insts commited each cycle
910 system.cpu0.commit.committed_per_cycle::stdev 1.508198 # Number of insts commited each cycle
911 system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
912 system.cpu0.commit.committed_per_cycle::0 61722766 81.28% 81.28% # Number of insts commited each cycle
913 system.cpu0.commit.committed_per_cycle::1 6904437 9.09% 90.38% # Number of insts commited each cycle
914 system.cpu0.commit.committed_per_cycle::2 2039889 2.69% 93.06% # Number of insts commited each cycle
915 system.cpu0.commit.committed_per_cycle::3 1134781 1.49% 94.56% # Number of insts commited each cycle
916 system.cpu0.commit.committed_per_cycle::4 1032872 1.36% 95.92% # Number of insts commited each cycle
917 system.cpu0.commit.committed_per_cycle::5 547307 0.72% 96.64% # Number of insts commited each cycle
918 system.cpu0.commit.committed_per_cycle::6 702356 0.92% 97.56% # Number of insts commited each cycle
919 system.cpu0.commit.committed_per_cycle::7 369637 0.49% 98.05% # Number of insts commited each cycle
920 system.cpu0.commit.committed_per_cycle::8 1481593 1.95% 100.00% # Number of insts commited each cycle
921 system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
922 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
923 system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
924 system.cpu0.commit.committed_per_cycle::total 75935638 # Number of insts commited each cycle
925 system.cpu0.commit.committedInsts 31265183 # Number of instructions committed
926 system.cpu0.commit.committedOps 39910920 # Number of ops (including micro ops) committed
927 system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
928 system.cpu0.commit.refs 13962135 # Number of memory references committed
929 system.cpu0.commit.loads 8074543 # Number of loads committed
930 system.cpu0.commit.membars 212305 # Number of memory barriers committed
931 system.cpu0.commit.branches 5202337 # Number of branches committed
932 system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions.
933 system.cpu0.commit.int_insts 35261936 # Number of committed integer instructions.
934 system.cpu0.commit.function_calls 513908 # Number of function calls committed.
935 system.cpu0.commit.bw_lim_events 1481593 # number cycles where commit BW limit reached
936 system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
937 system.cpu0.rob.rob_reads 123744681 # The number of ROB reads
938 system.cpu0.rob.rob_writes 102258102 # The number of ROB writes
939 system.cpu0.timesIdled 883709 # Number of times that the entire CPU went into an idle state and unscheduled itself
940 system.cpu0.idleCycles 161449961 # Total number of cycles that the CPU has spent unscheduled due to idling
941 system.cpu0.quiesceCycles 2289675923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
942 system.cpu0.committedInsts 31185911 # Number of Instructions Simulated
943 system.cpu0.committedOps 39831648 # Number of Ops (including micro ops) Simulated
944 system.cpu0.committedInsts_total 31185911 # Number of Instructions Simulated
945 system.cpu0.cpi 7.665825 # CPI: Cycles Per Instruction
946 system.cpu0.cpi_total 7.665825 # CPI: Total CPI of All Threads
947 system.cpu0.ipc 0.130449 # IPC: Instructions Per Cycle
948 system.cpu0.ipc_total 0.130449 # IPC: Total IPC of All Threads
949 system.cpu0.int_regfile_reads 280645626 # number of integer regfile reads
950 system.cpu0.int_regfile_writes 45419186 # number of integer regfile writes
951 system.cpu0.fp_regfile_reads 22697 # number of floating regfile reads
952 system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes
953 system.cpu0.misc_regfile_reads 15480369 # number of misc regfile reads
954 system.cpu0.misc_regfile_writes 429671 # number of misc regfile writes
955 system.cpu0.icache.replacements 983987 # number of replacements
956 system.cpu0.icache.tagsinuse 511.561827 # Cycle average of tags in use
957 system.cpu0.icache.total_refs 11034736 # Total number of references to valid blocks.
958 system.cpu0.icache.sampled_refs 984499 # Sample count of references to valid blocks.
959 system.cpu0.icache.avg_refs 11.208479 # Average number of references to valid blocks.
960 system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit.
961 system.cpu0.icache.occ_blocks::cpu0.inst 357.606132 # Average occupied blocks per requestor
962 system.cpu0.icache.occ_blocks::cpu1.inst 153.955695 # Average occupied blocks per requestor
963 system.cpu0.icache.occ_percent::cpu0.inst 0.698449 # Average percentage of cache occupancy
964 system.cpu0.icache.occ_percent::cpu1.inst 0.300695 # Average percentage of cache occupancy
965 system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy
966 system.cpu0.icache.ReadReq_hits::cpu0.inst 5565566 # number of ReadReq hits
967 system.cpu0.icache.ReadReq_hits::cpu1.inst 5469170 # number of ReadReq hits
968 system.cpu0.icache.ReadReq_hits::total 11034736 # number of ReadReq hits
969 system.cpu0.icache.demand_hits::cpu0.inst 5565566 # number of demand (read+write) hits
970 system.cpu0.icache.demand_hits::cpu1.inst 5469170 # number of demand (read+write) hits
971 system.cpu0.icache.demand_hits::total 11034736 # number of demand (read+write) hits
972 system.cpu0.icache.overall_hits::cpu0.inst 5565566 # number of overall hits
973 system.cpu0.icache.overall_hits::cpu1.inst 5469170 # number of overall hits
974 system.cpu0.icache.overall_hits::total 11034736 # number of overall hits
975 system.cpu0.icache.ReadReq_misses::cpu0.inst 539949 # number of ReadReq misses
976 system.cpu0.icache.ReadReq_misses::cpu1.inst 524997 # number of ReadReq misses
977 system.cpu0.icache.ReadReq_misses::total 1064946 # number of ReadReq misses
978 system.cpu0.icache.demand_misses::cpu0.inst 539949 # number of demand (read+write) misses
979 system.cpu0.icache.demand_misses::cpu1.inst 524997 # number of demand (read+write) misses
980 system.cpu0.icache.demand_misses::total 1064946 # number of demand (read+write) misses
981 system.cpu0.icache.overall_misses::cpu0.inst 539949 # number of overall misses
982 system.cpu0.icache.overall_misses::cpu1.inst 524997 # number of overall misses
983 system.cpu0.icache.overall_misses::total 1064946 # number of overall misses
984 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306962994 # number of ReadReq miss cycles
985 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971237994 # number of ReadReq miss cycles
986 system.cpu0.icache.ReadReq_miss_latency::total 14278200988 # number of ReadReq miss cycles
987 system.cpu0.icache.demand_miss_latency::cpu0.inst 7306962994 # number of demand (read+write) miss cycles
988 system.cpu0.icache.demand_miss_latency::cpu1.inst 6971237994 # number of demand (read+write) miss cycles
989 system.cpu0.icache.demand_miss_latency::total 14278200988 # number of demand (read+write) miss cycles
990 system.cpu0.icache.overall_miss_latency::cpu0.inst 7306962994 # number of overall miss cycles
991 system.cpu0.icache.overall_miss_latency::cpu1.inst 6971237994 # number of overall miss cycles
992 system.cpu0.icache.overall_miss_latency::total 14278200988 # number of overall miss cycles
993 system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105515 # number of ReadReq accesses(hits+misses)
994 system.cpu0.icache.ReadReq_accesses::cpu1.inst 5994167 # number of ReadReq accesses(hits+misses)
995 system.cpu0.icache.ReadReq_accesses::total 12099682 # number of ReadReq accesses(hits+misses)
996 system.cpu0.icache.demand_accesses::cpu0.inst 6105515 # number of demand (read+write) accesses
997 system.cpu0.icache.demand_accesses::cpu1.inst 5994167 # number of demand (read+write) accesses
998 system.cpu0.icache.demand_accesses::total 12099682 # number of demand (read+write) accesses
999 system.cpu0.icache.overall_accesses::cpu0.inst 6105515 # number of overall (read+write) accesses
1000 system.cpu0.icache.overall_accesses::cpu1.inst 5994167 # number of overall (read+write) accesses
1001 system.cpu0.icache.overall_accesses::total 12099682 # number of overall (read+write) accesses
1002 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088436 # miss rate for ReadReq accesses
1003 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087585 # miss rate for ReadReq accesses
1004 system.cpu0.icache.ReadReq_miss_rate::total 0.088014 # miss rate for ReadReq accesses
1005 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088436 # miss rate for demand accesses
1006 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087585 # miss rate for demand accesses
1007 system.cpu0.icache.demand_miss_rate::total 0.088014 # miss rate for demand accesses
1008 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088436 # miss rate for overall accesses
1009 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087585 # miss rate for overall accesses
1010 system.cpu0.icache.overall_miss_rate::total 0.088014 # miss rate for overall accesses
1011 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13532.691039 # average ReadReq miss latency
1012 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13278.624438 # average ReadReq miss latency
1013 system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.441305 # average ReadReq miss latency
1014 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency
1015 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency
1016 system.cpu0.icache.demand_avg_miss_latency::total 13407.441305 # average overall miss latency
1017 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency
1018 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency
1019 system.cpu0.icache.overall_avg_miss_latency::total 13407.441305 # average overall miss latency
1020 system.cpu0.icache.blocked_cycles::no_mshrs 4578 # number of cycles access was blocked
1021 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1022 system.cpu0.icache.blocked::no_mshrs 340 # number of cycles access was blocked
1023 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1024 system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.464706 # average number of cycles each access was blocked
1025 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1026 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1027 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1028 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41021 # number of ReadReq MSHR hits
1029 system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39404 # number of ReadReq MSHR hits
1030 system.cpu0.icache.ReadReq_mshr_hits::total 80425 # number of ReadReq MSHR hits
1031 system.cpu0.icache.demand_mshr_hits::cpu0.inst 41021 # number of demand (read+write) MSHR hits
1032 system.cpu0.icache.demand_mshr_hits::cpu1.inst 39404 # number of demand (read+write) MSHR hits
1033 system.cpu0.icache.demand_mshr_hits::total 80425 # number of demand (read+write) MSHR hits
1034 system.cpu0.icache.overall_mshr_hits::cpu0.inst 41021 # number of overall MSHR hits
1035 system.cpu0.icache.overall_mshr_hits::cpu1.inst 39404 # number of overall MSHR hits
1036 system.cpu0.icache.overall_mshr_hits::total 80425 # number of overall MSHR hits
1037 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498928 # number of ReadReq MSHR misses
1038 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485593 # number of ReadReq MSHR misses
1039 system.cpu0.icache.ReadReq_mshr_misses::total 984521 # number of ReadReq MSHR misses
1040 system.cpu0.icache.demand_mshr_misses::cpu0.inst 498928 # number of demand (read+write) MSHR misses
1041 system.cpu0.icache.demand_mshr_misses::cpu1.inst 485593 # number of demand (read+write) MSHR misses
1042 system.cpu0.icache.demand_mshr_misses::total 984521 # number of demand (read+write) MSHR misses
1043 system.cpu0.icache.overall_mshr_misses::cpu0.inst 498928 # number of overall MSHR misses
1044 system.cpu0.icache.overall_mshr_misses::cpu1.inst 485593 # number of overall MSHR misses
1045 system.cpu0.icache.overall_mshr_misses::total 984521 # number of overall MSHR misses
1046 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5964947994 # number of ReadReq MSHR miss cycles
1047 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687451995 # number of ReadReq MSHR miss cycles
1048 system.cpu0.icache.ReadReq_mshr_miss_latency::total 11652399989 # number of ReadReq MSHR miss cycles
1049 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5964947994 # number of demand (read+write) MSHR miss cycles
1050 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687451995 # number of demand (read+write) MSHR miss cycles
1051 system.cpu0.icache.demand_mshr_miss_latency::total 11652399989 # number of demand (read+write) MSHR miss cycles
1052 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5964947994 # number of overall MSHR miss cycles
1053 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687451995 # number of overall MSHR miss cycles
1054 system.cpu0.icache.overall_mshr_miss_latency::total 11652399989 # number of overall MSHR miss cycles
1055 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles
1056 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles
1057 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles
1058 system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles
1059 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for ReadReq accesses
1060 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for ReadReq accesses
1061 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses
1062 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for demand accesses
1063 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for demand accesses
1064 system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses
1065 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for overall accesses
1066 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for overall accesses
1067 system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses
1068 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average ReadReq mshr miss latency
1069 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average ReadReq mshr miss latency
1070 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.603292 # average ReadReq mshr miss latency
1071 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency
1072 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency
1073 system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency
1074 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency
1075 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency
1076 system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency
1077 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1078 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1079 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1080 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1081 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1082 system.cpu0.dcache.replacements 643944 # number of replacements
1083 system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use
1084 system.cpu0.dcache.total_refs 21531615 # Total number of references to valid blocks.
1085 system.cpu0.dcache.sampled_refs 644456 # Sample count of references to valid blocks.
1086 system.cpu0.dcache.avg_refs 33.410528 # Average number of references to valid blocks.
1087 system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit.
1088 system.cpu0.dcache.occ_blocks::cpu0.data 318.816885 # Average occupied blocks per requestor
1089 system.cpu0.dcache.occ_blocks::cpu1.data 193.175830 # Average occupied blocks per requestor
1090 system.cpu0.dcache.occ_percent::cpu0.data 0.622689 # Average percentage of cache occupancy
1091 system.cpu0.dcache.occ_percent::cpu1.data 0.377297 # Average percentage of cache occupancy
1092 system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
1093 system.cpu0.dcache.ReadReq_hits::cpu0.data 7106399 # number of ReadReq hits
1094 system.cpu0.dcache.ReadReq_hits::cpu1.data 6669591 # number of ReadReq hits
1095 system.cpu0.dcache.ReadReq_hits::total 13775990 # number of ReadReq hits
1096 system.cpu0.dcache.WriteReq_hits::cpu0.data 3768165 # number of WriteReq hits
1097 system.cpu0.dcache.WriteReq_hits::cpu1.data 3493394 # number of WriteReq hits
1098 system.cpu0.dcache.WriteReq_hits::total 7261559 # number of WriteReq hits
1099 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125825 # number of LoadLockedReq hits
1100 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117550 # number of LoadLockedReq hits
1101 system.cpu0.dcache.LoadLockedReq_hits::total 243375 # number of LoadLockedReq hits
1102 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127797 # number of StoreCondReq hits
1103 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119821 # number of StoreCondReq hits
1104 system.cpu0.dcache.StoreCondReq_hits::total 247618 # number of StoreCondReq hits
1105 system.cpu0.dcache.demand_hits::cpu0.data 10874564 # number of demand (read+write) hits
1106 system.cpu0.dcache.demand_hits::cpu1.data 10162985 # number of demand (read+write) hits
1107 system.cpu0.dcache.demand_hits::total 21037549 # number of demand (read+write) hits
1108 system.cpu0.dcache.overall_hits::cpu0.data 10874564 # number of overall hits
1109 system.cpu0.dcache.overall_hits::cpu1.data 10162985 # number of overall hits
1110 system.cpu0.dcache.overall_hits::total 21037549 # number of overall hits
1111 system.cpu0.dcache.ReadReq_misses::cpu0.data 435409 # number of ReadReq misses
1112 system.cpu0.dcache.ReadReq_misses::cpu1.data 315775 # number of ReadReq misses
1113 system.cpu0.dcache.ReadReq_misses::total 751184 # number of ReadReq misses
1114 system.cpu0.dcache.WriteReq_misses::cpu0.data 1387586 # number of WriteReq misses
1115 system.cpu0.dcache.WriteReq_misses::cpu1.data 1573694 # number of WriteReq misses
1116 system.cpu0.dcache.WriteReq_misses::total 2961280 # number of WriteReq misses
1117 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6805 # number of LoadLockedReq misses
1118 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6784 # number of LoadLockedReq misses
1119 system.cpu0.dcache.LoadLockedReq_misses::total 13589 # number of LoadLockedReq misses
1120 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
1121 system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses
1122 system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
1123 system.cpu0.dcache.demand_misses::cpu0.data 1822995 # number of demand (read+write) misses
1124 system.cpu0.dcache.demand_misses::cpu1.data 1889469 # number of demand (read+write) misses
1125 system.cpu0.dcache.demand_misses::total 3712464 # number of demand (read+write) misses
1126 system.cpu0.dcache.overall_misses::cpu0.data 1822995 # number of overall misses
1127 system.cpu0.dcache.overall_misses::cpu1.data 1889469 # number of overall misses
1128 system.cpu0.dcache.overall_misses::total 3712464 # number of overall misses
1129 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6464424000 # number of ReadReq miss cycles
1130 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4870396500 # number of ReadReq miss cycles
1131 system.cpu0.dcache.ReadReq_miss_latency::total 11334820500 # number of ReadReq miss cycles
1132 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52533360348 # number of WriteReq miss cycles
1133 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61938473792 # number of WriteReq miss cycles
1134 system.cpu0.dcache.WriteReq_miss_latency::total 114471834140 # number of WriteReq miss cycles
1135 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92175500 # number of LoadLockedReq miss cycles
1136 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94175500 # number of LoadLockedReq miss cycles
1137 system.cpu0.dcache.LoadLockedReq_miss_latency::total 186351000 # number of LoadLockedReq miss cycles
1138 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles
1139 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles
1140 system.cpu0.dcache.StoreCondReq_miss_latency::total 168000 # number of StoreCondReq miss cycles
1141 system.cpu0.dcache.demand_miss_latency::cpu0.data 58997784348 # number of demand (read+write) miss cycles
1142 system.cpu0.dcache.demand_miss_latency::cpu1.data 66808870292 # number of demand (read+write) miss cycles
1143 system.cpu0.dcache.demand_miss_latency::total 125806654640 # number of demand (read+write) miss cycles
1144 system.cpu0.dcache.overall_miss_latency::cpu0.data 58997784348 # number of overall miss cycles
1145 system.cpu0.dcache.overall_miss_latency::cpu1.data 66808870292 # number of overall miss cycles
1146 system.cpu0.dcache.overall_miss_latency::total 125806654640 # number of overall miss cycles
1147 system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541808 # number of ReadReq accesses(hits+misses)
1148 system.cpu0.dcache.ReadReq_accesses::cpu1.data 6985366 # number of ReadReq accesses(hits+misses)
1149 system.cpu0.dcache.ReadReq_accesses::total 14527174 # number of ReadReq accesses(hits+misses)
1150 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155751 # number of WriteReq accesses(hits+misses)
1151 system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067088 # number of WriteReq accesses(hits+misses)
1152 system.cpu0.dcache.WriteReq_accesses::total 10222839 # number of WriteReq accesses(hits+misses)
1153 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132630 # number of LoadLockedReq accesses(hits+misses)
1154 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124334 # number of LoadLockedReq accesses(hits+misses)
1155 system.cpu0.dcache.LoadLockedReq_accesses::total 256964 # number of LoadLockedReq accesses(hits+misses)
1156 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127803 # number of StoreCondReq accesses(hits+misses)
1157 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119827 # number of StoreCondReq accesses(hits+misses)
1158 system.cpu0.dcache.StoreCondReq_accesses::total 247630 # number of StoreCondReq accesses(hits+misses)
1159 system.cpu0.dcache.demand_accesses::cpu0.data 12697559 # number of demand (read+write) accesses
1160 system.cpu0.dcache.demand_accesses::cpu1.data 12052454 # number of demand (read+write) accesses
1161 system.cpu0.dcache.demand_accesses::total 24750013 # number of demand (read+write) accesses
1162 system.cpu0.dcache.overall_accesses::cpu0.data 12697559 # number of overall (read+write) accesses
1163 system.cpu0.dcache.overall_accesses::cpu1.data 12052454 # number of overall (read+write) accesses
1164 system.cpu0.dcache.overall_accesses::total 24750013 # number of overall (read+write) accesses
1165 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057733 # miss rate for ReadReq accesses
1166 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045205 # miss rate for ReadReq accesses
1167 system.cpu0.dcache.ReadReq_miss_rate::total 0.051709 # miss rate for ReadReq accesses
1168 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269134 # miss rate for WriteReq accesses
1169 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310572 # miss rate for WriteReq accesses
1170 system.cpu0.dcache.WriteReq_miss_rate::total 0.289673 # miss rate for WriteReq accesses
1171 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051308 # miss rate for LoadLockedReq accesses
1172 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054563 # miss rate for LoadLockedReq accesses
1173 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses
1174 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000047 # miss rate for StoreCondReq accesses
1175 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses
1176 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
1177 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143571 # miss rate for demand accesses
1178 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156770 # miss rate for demand accesses
1179 system.cpu0.dcache.demand_miss_rate::total 0.149998 # miss rate for demand accesses
1180 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143571 # miss rate for overall accesses
1181 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156770 # miss rate for overall accesses
1182 system.cpu0.dcache.overall_miss_rate::total 0.149998 # miss rate for overall accesses
1183 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14846.785436 # average ReadReq miss latency
1184 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15423.629166 # average ReadReq miss latency
1185 system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.273068 # average ReadReq miss latency
1186 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37859.534723 # average WriteReq miss latency
1187 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.651550 # average WriteReq miss latency
1188 system.cpu0.dcache.WriteReq_avg_miss_latency::total 38656.200744 # average WriteReq miss latency
1189 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13545.260838 # average LoadLockedReq miss latency
1190 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13882.001769 # average LoadLockedReq miss latency
1191 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13713.371109 # average LoadLockedReq miss latency
1192 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency
1193 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
1194 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency
1195 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32363.108153 # average overall miss latency
1196 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35358.542687 # average overall miss latency
1197 system.cpu0.dcache.demand_avg_miss_latency::total 33887.642989 # average overall miss latency
1198 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32363.108153 # average overall miss latency
1199 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35358.542687 # average overall miss latency
1200 system.cpu0.dcache.overall_avg_miss_latency::total 33887.642989 # average overall miss latency
1201 system.cpu0.dcache.blocked_cycles::no_mshrs 35225 # number of cycles access was blocked
1202 system.cpu0.dcache.blocked_cycles::no_targets 16625 # number of cycles access was blocked
1203 system.cpu0.dcache.blocked::no_mshrs 3569 # number of cycles access was blocked
1204 system.cpu0.dcache.blocked::no_targets 263 # number of cycles access was blocked
1205 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.869711 # average number of cycles each access was blocked
1206 system.cpu0.dcache.avg_blocked_cycles::no_targets 63.212928 # average number of cycles each access was blocked
1207 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1208 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1209 system.cpu0.dcache.writebacks::writebacks 608440 # number of writebacks
1210 system.cpu0.dcache.writebacks::total 608440 # number of writebacks
1211 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221787 # number of ReadReq MSHR hits
1212 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143125 # number of ReadReq MSHR hits
1213 system.cpu0.dcache.ReadReq_mshr_hits::total 364912 # number of ReadReq MSHR hits
1214 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1268338 # number of WriteReq MSHR hits
1215 system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444026 # number of WriteReq MSHR hits
1216 system.cpu0.dcache.WriteReq_mshr_hits::total 2712364 # number of WriteReq MSHR hits
1217 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 692 # number of LoadLockedReq MSHR hits
1218 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 696 # number of LoadLockedReq MSHR hits
1219 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1388 # number of LoadLockedReq MSHR hits
1220 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1490125 # number of demand (read+write) MSHR hits
1221 system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587151 # number of demand (read+write) MSHR hits
1222 system.cpu0.dcache.demand_mshr_hits::total 3077276 # number of demand (read+write) MSHR hits
1223 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1490125 # number of overall MSHR hits
1224 system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587151 # number of overall MSHR hits
1225 system.cpu0.dcache.overall_mshr_hits::total 3077276 # number of overall MSHR hits
1226 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213622 # number of ReadReq MSHR misses
1227 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172650 # number of ReadReq MSHR misses
1228 system.cpu0.dcache.ReadReq_mshr_misses::total 386272 # number of ReadReq MSHR misses
1229 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119248 # number of WriteReq MSHR misses
1230 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129668 # number of WriteReq MSHR misses
1231 system.cpu0.dcache.WriteReq_mshr_misses::total 248916 # number of WriteReq MSHR misses
1232 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6113 # number of LoadLockedReq MSHR misses
1233 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6088 # number of LoadLockedReq MSHR misses
1234 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12201 # number of LoadLockedReq MSHR misses
1235 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses
1236 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses
1237 system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
1238 system.cpu0.dcache.demand_mshr_misses::cpu0.data 332870 # number of demand (read+write) MSHR misses
1239 system.cpu0.dcache.demand_mshr_misses::cpu1.data 302318 # number of demand (read+write) MSHR misses
1240 system.cpu0.dcache.demand_mshr_misses::total 635188 # number of demand (read+write) MSHR misses
1241 system.cpu0.dcache.overall_mshr_misses::cpu0.data 332870 # number of overall MSHR misses
1242 system.cpu0.dcache.overall_mshr_misses::cpu1.data 302318 # number of overall MSHR misses
1243 system.cpu0.dcache.overall_mshr_misses::total 635188 # number of overall MSHR misses
1244 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899035000 # number of ReadReq MSHR miss cycles
1245 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2323789000 # number of ReadReq MSHR miss cycles
1246 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5222824000 # number of ReadReq MSHR miss cycles
1247 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3973939486 # number of WriteReq MSHR miss cycles
1248 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4489804935 # number of WriteReq MSHR miss cycles
1249 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8463744421 # number of WriteReq MSHR miss cycles
1250 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71655500 # number of LoadLockedReq MSHR miss cycles
1251 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73661500 # number of LoadLockedReq MSHR miss cycles
1252 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145317000 # number of LoadLockedReq MSHR miss cycles
1253 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles
1254 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles
1255 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144000 # number of StoreCondReq MSHR miss cycles
1256 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6872974486 # number of demand (read+write) MSHR miss cycles
1257 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6813593935 # number of demand (read+write) MSHR miss cycles
1258 system.cpu0.dcache.demand_mshr_miss_latency::total 13686568421 # number of demand (read+write) MSHR miss cycles
1259 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6872974486 # number of overall MSHR miss cycles
1260 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6813593935 # number of overall MSHR miss cycles
1261 system.cpu0.dcache.overall_mshr_miss_latency::total 13686568421 # number of overall MSHR miss cycles
1262 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91950216500 # number of ReadReq MSHR uncacheable cycles
1263 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90410818500 # number of ReadReq MSHR uncacheable cycles
1264 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361035000 # number of ReadReq MSHR uncacheable cycles
1265 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14891141407 # number of WriteReq MSHR uncacheable cycles
1266 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18622831131 # number of WriteReq MSHR uncacheable cycles
1267 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33513972538 # number of WriteReq MSHR uncacheable cycles
1268 system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
1269 system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
1270 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
1271 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
1272 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106841357907 # number of overall MSHR uncacheable cycles
1273 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109033649631 # number of overall MSHR uncacheable cycles
1274 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875007538 # number of overall MSHR uncacheable cycles
1275 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028325 # mshr miss rate for ReadReq accesses
1276 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024716 # mshr miss rate for ReadReq accesses
1277 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026590 # mshr miss rate for ReadReq accesses
1278 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses
1279 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025590 # mshr miss rate for WriteReq accesses
1280 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024349 # mshr miss rate for WriteReq accesses
1281 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046091 # mshr miss rate for LoadLockedReq accesses
1282 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048965 # mshr miss rate for LoadLockedReq accesses
1283 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047481 # mshr miss rate for LoadLockedReq accesses
1284 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses
1285 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses
1286 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
1287 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for demand accesses
1288 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for demand accesses
1289 system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses
1290 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for overall accesses
1291 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for overall accesses
1292 system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses
1293 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13570.863488 # average ReadReq mshr miss latency
1294 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13459.536635 # average ReadReq mshr miss latency
1295 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.104300 # average ReadReq mshr miss latency
1296 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33324.999044 # average WriteReq mshr miss latency
1297 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34625.388955 # average WriteReq mshr miss latency
1298 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.412143 # average WriteReq mshr miss latency
1299 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11721.822346 # average LoadLockedReq mshr miss latency
1300 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12099.457950 # average LoadLockedReq mshr miss latency
1301 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.253258 # average LoadLockedReq mshr miss latency
1302 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency
1303 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
1304 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12000 # average StoreCondReq mshr miss latency
1305 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency
1306 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency
1307 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency
1308 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency
1309 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency
1310 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency
1311 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1312 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1313 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1314 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1315 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1316 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1317 system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
1318 system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
1319 system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
1320 system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
1321 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1322 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1323 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1324 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1325 system.cpu1.branchPred.lookups 7039242 # Number of BP lookups
1326 system.cpu1.branchPred.condPredicted 5645782 # Number of conditional branches predicted
1327 system.cpu1.branchPred.condIncorrect 344121 # Number of conditional branches incorrect
1328 system.cpu1.branchPred.BTBLookups 4649860 # Number of BTB lookups
1329 system.cpu1.branchPred.BTBHits 3812908 # Number of BTB hits
1330 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1331 system.cpu1.branchPred.BTBHitPct 82.000490 # BTB Hit Percentage
1332 system.cpu1.branchPred.usedRAS 671568 # Number of times the RAS was used to get a target.
1333 system.cpu1.branchPred.RASInCorrect 34742 # Number of incorrect RAS predictions.
1334 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1335 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1336 system.cpu1.dtb.read_hits 25307959 # DTB read hits
1337 system.cpu1.dtb.read_misses 36376 # DTB read misses
1338 system.cpu1.dtb.write_hits 5825723 # DTB write hits
1339 system.cpu1.dtb.write_misses 9311 # DTB write misses
1340 system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
1341 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1342 system.cpu1.dtb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID
1343 system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
1344 system.cpu1.dtb.flush_entries 5515 # Number of entries that have been flushed from TLB
1345 system.cpu1.dtb.align_faults 1387 # Number of TLB faults due to alignment restrictions
1346 system.cpu1.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch
1347 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1348 system.cpu1.dtb.perms_faults 651 # Number of TLB faults due to permissions restrictions
1349 system.cpu1.dtb.read_accesses 25344335 # DTB read accesses
1350 system.cpu1.dtb.write_accesses 5835034 # DTB write accesses
1351 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1352 system.cpu1.dtb.hits 31133682 # DTB hits
1353 system.cpu1.dtb.misses 45687 # DTB misses
1354 system.cpu1.dtb.accesses 31179369 # DTB accesses
1355 system.cpu1.itb.inst_hits 5996114 # ITB inst hits
1356 system.cpu1.itb.inst_misses 6834 # ITB inst misses
1357 system.cpu1.itb.read_hits 0 # DTB read hits
1358 system.cpu1.itb.read_misses 0 # DTB read misses
1359 system.cpu1.itb.write_hits 0 # DTB write hits
1360 system.cpu1.itb.write_misses 0 # DTB write misses
1361 system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
1362 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1363 system.cpu1.itb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID
1364 system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
1365 system.cpu1.itb.flush_entries 2600 # Number of entries that have been flushed from TLB
1366 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1367 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1368 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1369 system.cpu1.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions
1370 system.cpu1.itb.read_accesses 0 # DTB read accesses
1371 system.cpu1.itb.write_accesses 0 # DTB write accesses
1372 system.cpu1.itb.inst_accesses 6002948 # ITB inst accesses
1373 system.cpu1.itb.hits 5996114 # DTB hits
1374 system.cpu1.itb.misses 6834 # DTB misses
1375 system.cpu1.itb.accesses 6002948 # DTB accesses
1376 system.cpu1.numCycles 234172204 # number of cpu cycles simulated
1377 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1378 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1379 system.cpu1.fetch.icacheStallCycles 15150430 # Number of cycles fetch is stalled on an Icache miss
1380 system.cpu1.fetch.Insts 46599302 # Number of instructions fetch has processed
1381 system.cpu1.fetch.Branches 7039242 # Number of branches that fetch encountered
1382 system.cpu1.fetch.predictedBranches 4484476 # Number of branches that fetch has predicted taken
1383 system.cpu1.fetch.Cycles 10276938 # Number of cycles fetch has run and was not squashing or blocked
1384 system.cpu1.fetch.SquashCycles 2612454 # Number of cycles fetch has spent squashing
1385 system.cpu1.fetch.TlbCycles 82512 # Number of cycles fetch has spent waiting for tlb
1386 system.cpu1.fetch.BlockedCycles 47518747 # Number of cycles fetch has spent blocked
1387 system.cpu1.fetch.MiscStallCycles 979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1388 system.cpu1.fetch.PendingDrainCycles 2108 # Number of cycles fetch has spent waiting on pipes to drain
1389 system.cpu1.fetch.PendingTrapStallCycles 42921 # Number of stall cycles due to pending traps
1390 system.cpu1.fetch.PendingQuiesceStallCycles 94711 # Number of stall cycles due to pending quiesce instructions
1391 system.cpu1.fetch.IcacheWaitRetryStallCycles 94 # Number of stall cycles due to full MSHR
1392 system.cpu1.fetch.CacheLines 5994168 # Number of cache lines fetched
1393 system.cpu1.fetch.IcacheSquashes 443200 # Number of outstanding Icache misses that were squashed
1394 system.cpu1.fetch.ItlbSquashes 2937 # Number of outstanding ITLB misses that were squashed
1395 system.cpu1.fetch.rateDist::samples 74957939 # Number of instructions fetched each cycle (Total)
1396 system.cpu1.fetch.rateDist::mean 0.773072 # Number of instructions fetched each cycle (Total)
1397 system.cpu1.fetch.rateDist::stdev 2.138667 # Number of instructions fetched each cycle (Total)
1398 system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1399 system.cpu1.fetch.rateDist::0 64688840 86.30% 86.30% # Number of instructions fetched each cycle (Total)
1400 system.cpu1.fetch.rateDist::1 619651 0.83% 87.13% # Number of instructions fetched each cycle (Total)
1401 system.cpu1.fetch.rateDist::2 831575 1.11% 88.24% # Number of instructions fetched each cycle (Total)
1402 system.cpu1.fetch.rateDist::3 1205005 1.61% 89.84% # Number of instructions fetched each cycle (Total)
1403 system.cpu1.fetch.rateDist::4 1040099 1.39% 91.23% # Number of instructions fetched each cycle (Total)
1404 system.cpu1.fetch.rateDist::5 534718 0.71% 91.94% # Number of instructions fetched each cycle (Total)
1405 system.cpu1.fetch.rateDist::6 1368218 1.83% 93.77% # Number of instructions fetched each cycle (Total)
1406 system.cpu1.fetch.rateDist::7 351871 0.47% 94.24% # Number of instructions fetched each cycle (Total)
1407 system.cpu1.fetch.rateDist::8 4317962 5.76% 100.00% # Number of instructions fetched each cycle (Total)
1408 system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1409 system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1410 system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1411 system.cpu1.fetch.rateDist::total 74957939 # Number of instructions fetched each cycle (Total)
1412 system.cpu1.fetch.branchRate 0.030060 # Number of branch fetches per cycle
1413 system.cpu1.fetch.rate 0.198996 # Number of inst fetches per cycle
1414 system.cpu1.decode.IdleCycles 16159118 # Number of cycles decode is idle
1415 system.cpu1.decode.BlockedCycles 47313522 # Number of cycles decode is blocked
1416 system.cpu1.decode.RunCycles 9319419 # Number of cycles decode is running
1417 system.cpu1.decode.UnblockCycles 458702 # Number of cycles decode is unblocking
1418 system.cpu1.decode.SquashCycles 1705045 # Number of cycles decode is squashing
1419 system.cpu1.decode.BranchResolved 945660 # Number of times decode resolved a branch
1420 system.cpu1.decode.BranchMispred 85957 # Number of times decode detected a branch misprediction
1421 system.cpu1.decode.DecodedInsts 54861176 # Number of instructions handled by decode
1422 system.cpu1.decode.SquashedInsts 287371 # Number of squashed instructions handled by decode
1423 system.cpu1.rename.SquashCycles 1705045 # Number of cycles rename is squashing
1424 system.cpu1.rename.IdleCycles 17094797 # Number of cycles rename is idle
1425 system.cpu1.rename.BlockCycles 18547389 # Number of cycles rename is blocking
1426 system.cpu1.rename.serializeStallCycles 25741637 # count of cycles rename stalled for serializing inst
1427 system.cpu1.rename.RunCycles 8764339 # Number of cycles rename is running
1428 system.cpu1.rename.UnblockCycles 3102678 # Number of cycles rename is unblocking
1429 system.cpu1.rename.RenamedInsts 51699813 # Number of instructions processed by rename
1430 system.cpu1.rename.ROBFullEvents 7117 # Number of times rename has blocked due to ROB full
1431 system.cpu1.rename.IQFullEvents 482642 # Number of times rename has blocked due to IQ full
1432 system.cpu1.rename.LSQFullEvents 2122595 # Number of times rename has blocked due to LSQ full
1433 system.cpu1.rename.FullRegisterEvents 48 # Number of times there has been no free registers
1434 system.cpu1.rename.RenamedOperands 53761457 # Number of destination operands rename has renamed
1435 system.cpu1.rename.RenameLookups 237355866 # Number of register rename lookups that rename has made
1436 system.cpu1.rename.int_rename_lookups 237312988 # Number of integer rename lookups
1437 system.cpu1.rename.fp_rename_lookups 42878 # Number of floating rename lookups
1438 system.cpu1.rename.CommittedMaps 38005573 # Number of HB maps that are committed
1439 system.cpu1.rename.UndoneMaps 15755883 # Number of HB maps that are undone due to squashing
1440 system.cpu1.rename.serializingInsts 403501 # count of serializing insts renamed
1441 system.cpu1.rename.tempSerializingInsts 357316 # count of temporary serializing insts renamed
1442 system.cpu1.rename.skidInsts 6247551 # count of insts added to the skid buffer
1443 system.cpu1.memDep0.insertedLoads 9846699 # Number of loads inserted to the mem dependence unit.
1444 system.cpu1.memDep0.insertedStores 6699378 # Number of stores inserted to the mem dependence unit.
1445 system.cpu1.memDep0.conflictingLoads 894839 # Number of conflicting loads.
1446 system.cpu1.memDep0.conflictingStores 1124277 # Number of conflicting stores.
1447 system.cpu1.iq.iqInstsAdded 47671789 # Number of instructions added to the IQ (excludes non-spec)
1448 system.cpu1.iq.iqNonSpecInstsAdded 942558 # Number of non-speculative instructions added to the IQ
1449 system.cpu1.iq.iqInstsIssued 60820762 # Number of instructions issued
1450 system.cpu1.iq.iqSquashedInstsIssued 80974 # Number of squashed instructions issued
1451 system.cpu1.iq.iqSquashedInstsExamined 10554667 # Number of squashed instructions iterated over during squash; mainly for profiling
1452 system.cpu1.iq.iqSquashedOperandsExamined 27991193 # Number of squashed operands that are examined and possibly removed from graph
1453 system.cpu1.iq.iqSquashedNonSpecRemoved 236389 # Number of squashed non-spec instructions that were removed
1454 system.cpu1.iq.issued_per_cycle::samples 74957939 # Number of insts issued each cycle
1455 system.cpu1.iq.issued_per_cycle::mean 0.811399 # Number of insts issued each cycle
1456 system.cpu1.iq.issued_per_cycle::stdev 1.521506 # Number of insts issued each cycle
1457 system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1458 system.cpu1.iq.issued_per_cycle::0 53217841 71.00% 71.00% # Number of insts issued each cycle
1459 system.cpu1.iq.issued_per_cycle::1 6660852 8.89% 79.88% # Number of insts issued each cycle
1460 system.cpu1.iq.issued_per_cycle::2 3522155 4.70% 84.58% # Number of insts issued each cycle
1461 system.cpu1.iq.issued_per_cycle::3 2891310 3.86% 88.44% # Number of insts issued each cycle
1462 system.cpu1.iq.issued_per_cycle::4 6221103 8.30% 96.74% # Number of insts issued each cycle
1463 system.cpu1.iq.issued_per_cycle::5 1440067 1.92% 98.66% # Number of insts issued each cycle
1464 system.cpu1.iq.issued_per_cycle::6 734950 0.98% 99.64% # Number of insts issued each cycle
1465 system.cpu1.iq.issued_per_cycle::7 210065 0.28% 99.92% # Number of insts issued each cycle
1466 system.cpu1.iq.issued_per_cycle::8 59596 0.08% 100.00% # Number of insts issued each cycle
1467 system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1468 system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1469 system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1470 system.cpu1.iq.issued_per_cycle::total 74957939 # Number of insts issued each cycle
1471 system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1472 system.cpu1.iq.fu_full::IntAlu 24217 0.55% 0.55% # attempts to use FU when none available
1473 system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available
1474 system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
1475 system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available
1476 system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available
1477 system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available
1478 system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available
1479 system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available
1480 system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
1481 system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available
1482 system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available
1483 system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available
1484 system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available
1485 system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available
1486 system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available
1487 system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available
1488 system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available
1489 system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available
1490 system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available
1491 system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available
1492 system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available
1493 system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available
1494 system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available
1495 system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available
1496 system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available
1497 system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available
1498 system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available
1499 system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available
1500 system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
1501 system.cpu1.iq.fu_full::MemRead 4143294 94.86% 95.41% # attempts to use FU when none available
1502 system.cpu1.iq.fu_full::MemWrite 200406 4.59% 100.00% # attempts to use FU when none available
1503 system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1504 system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1505 system.cpu1.iq.FU_type_0::No_OpClass 168050 0.28% 0.28% # Type of FU issued
1506 system.cpu1.iq.FU_type_0::IntAlu 28446121 46.77% 47.05% # Type of FU issued
1507 system.cpu1.iq.FU_type_0::IntMult 46643 0.08% 47.12% # Type of FU issued
1508 system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued
1509 system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued
1510 system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued
1511 system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued
1512 system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued
1513 system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued
1514 system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued
1515 system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued
1516 system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued
1517 system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued
1518 system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued
1519 system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued
1520 system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.12% # Type of FU issued
1521 system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued
1522 system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued
1523 system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued
1524 system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.12% # Type of FU issued
1525 system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued
1526 system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued
1527 system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued
1528 system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued
1529 system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued
1530 system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued
1531 system.cpu1.iq.FU_type_0::SimdFloatMisc 906 0.00% 47.12% # Type of FU issued
1532 system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued
1533 system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.12% # Type of FU issued
1534 system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued
1535 system.cpu1.iq.FU_type_0::MemRead 26040786 42.82% 89.94% # Type of FU issued
1536 system.cpu1.iq.FU_type_0::MemWrite 6118237 10.06% 100.00% # Type of FU issued
1537 system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1538 system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1539 system.cpu1.iq.FU_type_0::total 60820762 # Type of FU issued
1540 system.cpu1.iq.rate 0.259727 # Inst issue rate
1541 system.cpu1.iq.fu_busy_cnt 4367918 # FU busy when requested
1542 system.cpu1.iq.fu_busy_rate 0.071816 # FU busy rate (busy events/executed inst)
1543 system.cpu1.iq.int_inst_queue_reads 201083162 # Number of integer instruction queue reads
1544 system.cpu1.iq.int_inst_queue_writes 59177242 # Number of integer instruction queue writes
1545 system.cpu1.iq.int_inst_queue_wakeup_accesses 41793523 # Number of integer instruction queue wakeup accesses
1546 system.cpu1.iq.fp_inst_queue_reads 10683 # Number of floating instruction queue reads
1547 system.cpu1.iq.fp_inst_queue_writes 5961 # Number of floating instruction queue writes
1548 system.cpu1.iq.fp_inst_queue_wakeup_accesses 4808 # Number of floating instruction queue wakeup accesses
1549 system.cpu1.iq.int_alu_accesses 65014989 # Number of integer alu accesses
1550 system.cpu1.iq.fp_alu_accesses 5641 # Number of floating point alu accesses
1551 system.cpu1.iew.lsq.thread0.forwLoads 303389 # Number of loads that had data forwarded from stores
1552 system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1553 system.cpu1.iew.lsq.thread0.squashedLoads 2265840 # Number of loads squashed
1554 system.cpu1.iew.lsq.thread0.ignoredResponses 3135 # Number of memory responses ignored because the instruction is squashed
1555 system.cpu1.iew.lsq.thread0.memOrderViolation 14672 # Number of memory ordering violations
1556 system.cpu1.iew.lsq.thread0.squashedStores 854347 # Number of stores squashed
1557 system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1558 system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1559 system.cpu1.iew.lsq.thread0.rescheduledLoads 16937147 # Number of loads that were rescheduled
1560 system.cpu1.iew.lsq.thread0.cacheBlocked 456872 # Number of times an access to memory failed due to the cache being blocked
1561 system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1562 system.cpu1.iew.iewSquashCycles 1705045 # Number of cycles IEW is squashing
1563 system.cpu1.iew.iewBlockCycles 13964953 # Number of cycles IEW is blocking
1564 system.cpu1.iew.iewUnblockCycles 229910 # Number of cycles IEW is unblocking
1565 system.cpu1.iew.iewDispatchedInsts 48720174 # Number of instructions dispatched to IQ
1566 system.cpu1.iew.iewDispSquashedInsts 98231 # Number of squashed instructions skipped by dispatch
1567 system.cpu1.iew.iewDispLoadInsts 9846699 # Number of dispatched load instructions
1568 system.cpu1.iew.iewDispStoreInsts 6699378 # Number of dispatched store instructions
1569 system.cpu1.iew.iewDispNonSpecInsts 669323 # Number of dispatched non-speculative instructions
1570 system.cpu1.iew.iewIQFullEvents 49676 # Number of times the IQ has become full, causing a stall
1571 system.cpu1.iew.iewLSQFullEvents 3736 # Number of times the LSQ has become full, causing a stall
1572 system.cpu1.iew.memOrderViolationEvents 14672 # Number of memory order violations
1573 system.cpu1.iew.predictedTakenIncorrect 165888 # Number of branches that were predicted taken incorrectly
1574 system.cpu1.iew.predictedNotTakenIncorrect 133425 # Number of branches that were predicted not taken incorrectly
1575 system.cpu1.iew.branchMispredicts 299313 # Number of branch mispredicts detected at execute
1576 system.cpu1.iew.iewExecutedInsts 59456626 # Number of executed instructions
1577 system.cpu1.iew.iewExecLoadInsts 25635805 # Number of load instructions executed
1578 system.cpu1.iew.iewExecSquashedInsts 1364136 # Number of squashed instructions skipped in execute
1579 system.cpu1.iew.exec_swp 0 # number of swp insts executed
1580 system.cpu1.iew.exec_nop 105827 # number of nop insts executed
1581 system.cpu1.iew.exec_refs 31702395 # number of memory reference insts executed
1582 system.cpu1.iew.exec_branches 5527346 # Number of branches executed
1583 system.cpu1.iew.exec_stores 6066590 # Number of stores executed
1584 system.cpu1.iew.exec_rate 0.253901 # Inst execution rate
1585 system.cpu1.iew.wb_sent 58878116 # cumulative count of insts sent to commit
1586 system.cpu1.iew.wb_count 41798331 # cumulative count of insts written-back
1587 system.cpu1.iew.wb_producers 22764679 # num instructions producing a value
1588 system.cpu1.iew.wb_consumers 41753721 # num instructions consuming a value
1589 system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1590 system.cpu1.iew.wb_rate 0.178494 # insts written-back per cycle
1591 system.cpu1.iew.wb_fanout 0.545213 # average fanout of values written-back
1592 system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1593 system.cpu1.commit.commitSquashedInsts 10481198 # The number of squashed insts skipped by commit
1594 system.cpu1.commit.commitNonSpecStalls 706169 # The number of times commit has been forced to stall to communicate backwards
1595 system.cpu1.commit.branchMispredicts 259373 # The number of times a branch was mispredicted
1596 system.cpu1.commit.committed_per_cycle::samples 73252894 # Number of insts commited each cycle
1597 system.cpu1.commit.committed_per_cycle::mean 0.516596 # Number of insts commited each cycle
1598 system.cpu1.commit.committed_per_cycle::stdev 1.497283 # Number of insts commited each cycle
1599 system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1600 system.cpu1.commit.committed_per_cycle::0 59734394 81.55% 81.55% # Number of insts commited each cycle
1601 system.cpu1.commit.committed_per_cycle::1 6658117 9.09% 90.63% # Number of insts commited each cycle
1602 system.cpu1.commit.committed_per_cycle::2 1908666 2.61% 93.24% # Number of insts commited each cycle
1603 system.cpu1.commit.committed_per_cycle::3 1009766 1.38% 94.62% # Number of insts commited each cycle
1604 system.cpu1.commit.committed_per_cycle::4 959602 1.31% 95.93% # Number of insts commited each cycle
1605 system.cpu1.commit.committed_per_cycle::5 525640 0.72% 96.65% # Number of insts commited each cycle
1606 system.cpu1.commit.committed_per_cycle::6 705032 0.96% 97.61% # Number of insts commited each cycle
1607 system.cpu1.commit.committed_per_cycle::7 372807 0.51% 98.12% # Number of insts commited each cycle
1608 system.cpu1.commit.committed_per_cycle::8 1378870 1.88% 100.00% # Number of insts commited each cycle
1609 system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1610 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1611 system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1612 system.cpu1.commit.committed_per_cycle::total 73252894 # Number of insts commited each cycle
1613 system.cpu1.commit.committedInsts 29195437 # Number of instructions committed
1614 system.cpu1.commit.committedOps 37842156 # Number of ops (including micro ops) committed
1615 system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1616 system.cpu1.commit.refs 13425890 # Number of memory references committed
1617 system.cpu1.commit.loads 7580859 # Number of loads committed
1618 system.cpu1.commit.membars 191347 # Number of memory barriers committed
1619 system.cpu1.commit.branches 4759387 # Number of branches committed
1620 system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions.
1621 system.cpu1.commit.int_insts 33596023 # Number of committed integer instructions.
1622 system.cpu1.commit.function_calls 477418 # Number of function calls committed.
1623 system.cpu1.commit.bw_lim_events 1378870 # number cycles where commit BW limit reached
1624 system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1625 system.cpu1.rob.rob_reads 119325211 # The number of ROB reads
1626 system.cpu1.rob.rob_writes 98404070 # The number of ROB writes
1627 system.cpu1.timesIdled 873125 # Number of times that the entire CPU went into an idle state and unscheduled itself
1628 system.cpu1.idleCycles 159214265 # Total number of cycles that the CPU has spent unscheduled due to idling
1629 system.cpu1.quiesceCycles 2285839594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1630 system.cpu1.committedInsts 29124328 # Number of Instructions Simulated
1631 system.cpu1.committedOps 37771047 # Number of Ops (including micro ops) Simulated
1632 system.cpu1.committedInsts_total 29124328 # Number of Instructions Simulated
1633 system.cpu1.cpi 8.040433 # CPI: Cycles Per Instruction
1634 system.cpu1.cpi_total 8.040433 # CPI: Total CPI of All Threads
1635 system.cpu1.ipc 0.124371 # IPC: Instructions Per Cycle
1636 system.cpu1.ipc_total 0.124371 # IPC: Total IPC of All Threads
1637 system.cpu1.int_regfile_reads 269378788 # number of integer regfile reads
1638 system.cpu1.int_regfile_writes 42887039 # number of integer regfile writes
1639 system.cpu1.fp_regfile_reads 22080 # number of floating regfile reads
1640 system.cpu1.fp_regfile_writes 19702 # number of floating regfile writes
1641 system.cpu1.misc_regfile_reads 14812812 # number of misc regfile reads
1642 system.cpu1.misc_regfile_writes 402828 # number of misc regfile writes
1643 system.iocache.replacements 0 # number of replacements
1644 system.iocache.tagsinuse 0 # Cycle average of tags in use
1645 system.iocache.total_refs 0 # Total number of references to valid blocks.
1646 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1647 system.iocache.avg_refs nan # Average number of references to valid blocks.
1648 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1649 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1650 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1651 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1652 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1653 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1654 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1655 system.iocache.fast_writes 0 # number of fast writes performed
1656 system.iocache.cache_copies 0 # number of cache copies performed
1657 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of ReadReq MSHR uncacheable cycles
1658 system.iocache.ReadReq_mshr_uncacheable_latency::total 1192668399444 # number of ReadReq MSHR uncacheable cycles
1659 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of overall MSHR uncacheable cycles
1660 system.iocache.overall_mshr_uncacheable_latency::total 1192668399444 # number of overall MSHR uncacheable cycles
1661 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1662 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1663 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1664 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1665 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1666 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1667 system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed
1668 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1669 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1671 ---------- End Simulation Statistics ----------
projects / gem5.git / blob