2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.549325 # Number of seconds simulated
4 sim_ticks 2549325180000 # Number of ticks simulated
5 final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 61075 # Simulator instruction rate (inst/s)
8 host_op_rate 78588 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2581455626 # Simulator tick rate (ticks/s)
10 host_mem_usage 428832 # Number of bytes of host memory used
11 host_seconds 987.55 # Real time elapsed on the host
12 sim_insts 60314884 # Number of instructions simulated
13 sim_ops 77609482 # Number of ops (including micro ops) simulated
14 system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
15 system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
16 system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
17 system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
18 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
19 system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
20 system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
21 system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
22 system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
23 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
24 system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
25 system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
26 system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
27 system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
28 system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
29 system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory
30 system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory
31 system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory
32 system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory
33 system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory
34 system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory
35 system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory
36 system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory
37 system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory
38 system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory
39 system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory
40 system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory
41 system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory
42 system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory
46 system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory
47 system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory
48 system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory
49 system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory
50 system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory
51 system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory
52 system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory
53 system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory
54 system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory
55 system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s)
71 system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.readReqs 15293464 # Number of read requests accepted
82 system.physmem.writeReqs 813176 # Number of write requests accepted
83 system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue
84 system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue
85 system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM
86 system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue
87 system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM
88 system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side
89 system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side
90 system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue
91 system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one
92 system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write
93 system.physmem.perBankRdBursts::0 955865 # Per bank write bursts
94 system.physmem.perBankRdBursts::1 955523 # Per bank write bursts
95 system.physmem.perBankRdBursts::2 954611 # Per bank write bursts
96 system.physmem.perBankRdBursts::3 954852 # Per bank write bursts
97 system.physmem.perBankRdBursts::4 955764 # Per bank write bursts
98 system.physmem.perBankRdBursts::5 955945 # Per bank write bursts
99 system.physmem.perBankRdBursts::6 954843 # Per bank write bursts
100 system.physmem.perBankRdBursts::7 954680 # Per bank write bursts
101 system.physmem.perBankRdBursts::8 956251 # Per bank write bursts
102 system.physmem.perBankRdBursts::9 955822 # Per bank write bursts
103 system.physmem.perBankRdBursts::10 954302 # Per bank write bursts
104 system.physmem.perBankRdBursts::11 954022 # Per bank write bursts
105 system.physmem.perBankRdBursts::12 956218 # Per bank write bursts
106 system.physmem.perBankRdBursts::13 955977 # Per bank write bursts
107 system.physmem.perBankRdBursts::14 955052 # Per bank write bursts
108 system.physmem.perBankRdBursts::15 954922 # Per bank write bursts
109 system.physmem.perBankWrBursts::0 6685 # Per bank write bursts
110 system.physmem.perBankWrBursts::1 6462 # Per bank write bursts
111 system.physmem.perBankWrBursts::2 6616 # Per bank write bursts
112 system.physmem.perBankWrBursts::3 6625 # Per bank write bursts
113 system.physmem.perBankWrBursts::4 6578 # Per bank write bursts
114 system.physmem.perBankWrBursts::5 6834 # Per bank write bursts
115 system.physmem.perBankWrBursts::6 6825 # Per bank write bursts
116 system.physmem.perBankWrBursts::7 6778 # Per bank write bursts
117 system.physmem.perBankWrBursts::8 7112 # Per bank write bursts
118 system.physmem.perBankWrBursts::9 6876 # Per bank write bursts
119 system.physmem.perBankWrBursts::10 6540 # Per bank write bursts
120 system.physmem.perBankWrBursts::11 6189 # Per bank write bursts
121 system.physmem.perBankWrBursts::12 7142 # Per bank write bursts
122 system.physmem.perBankWrBursts::13 6759 # Per bank write bursts
123 system.physmem.perBankWrBursts::14 7042 # Per bank write bursts
124 system.physmem.perBankWrBursts::15 6910 # Per bank write bursts
125 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
126 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
127 system.physmem.totGap 2549324058500 # Total gap between requests
128 system.physmem.readPktSize::0 0 # Read request sizes (log2)
129 system.physmem.readPktSize::1 0 # Read request sizes (log2)
130 system.physmem.readPktSize::2 42 # Read request sizes (log2)
131 system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
132 system.physmem.readPktSize::4 0 # Read request sizes (log2)
133 system.physmem.readPktSize::5 0 # Read request sizes (log2)
134 system.physmem.readPktSize::6 154606 # Read request sizes (log2)
135 system.physmem.writePktSize::0 0 # Write request sizes (log2)
136 system.physmem.writePktSize::1 0 # Write request sizes (log2)
137 system.physmem.writePktSize::2 754025 # Write request sizes (log2)
138 system.physmem.writePktSize::3 0 # Write request sizes (log2)
139 system.physmem.writePktSize::4 0 # Write request sizes (log2)
140 system.physmem.writePktSize::5 0 # Write request sizes (log2)
141 system.physmem.writePktSize::6 59151 # Write request sizes (log2)
142 system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
174 system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
206 system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation
293 system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation
294 system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation
295 system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation
296 system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation
297 system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation
298 system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation
299 system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation
300 system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation
301 system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation
302 system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation
303 system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation
304 system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation
305 system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation
306 system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation
307 system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation
308 system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation
309 system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation
310 system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation
311 system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation
312 system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation
313 system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation
314 system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation
315 system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation
316 system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation
317 system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation
318 system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation
319 system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation
320 system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation
321 system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation
322 system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation
323 system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation
324 system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation
325 system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation
326 system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation
327 system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation
328 system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation
329 system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation
330 system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation
331 system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation
332 system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation
333 system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation
334 system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation
335 system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation
336 system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation
337 system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation
338 system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation
339 system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation
340 system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation
341 system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation
342 system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation
343 system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation
344 system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation
345 system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation
346 system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation
347 system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation
348 system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation
349 system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation
350 system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation
351 system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation
352 system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation
353 system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation
354 system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation
355 system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation
356 system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation
357 system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation
358 system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation
359 system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation
360 system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation
361 system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation
362 system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation
363 system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation
364 system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation
365 system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation
366 system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation
367 system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation
368 system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation
369 system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation
370 system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation
371 system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation
372 system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation
373 system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation
374 system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation
375 system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation
376 system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation
377 system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation
378 system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation
379 system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation
380 system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation
381 system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation
382 system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation
383 system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation
384 system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation
385 system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation
386 system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation
387 system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation
388 system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation
389 system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation
390 system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation
391 system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation
392 system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation
393 system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation
394 system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation
395 system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation
396 system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation
397 system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation
398 system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation
399 system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation
400 system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation
401 system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation
402 system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation
403 system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation
404 system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation
405 system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation
406 system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation
407 system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation
408 system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation
409 system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation
410 system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation
411 system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation
412 system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation
413 system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation
414 system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation
415 system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation
416 system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation
417 system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation
418 system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation
419 system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation
420 system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation
421 system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation
422 system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation
423 system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation
424 system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation
425 system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation
426 system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation
427 system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation
428 system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation
429 system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation
430 system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation
431 system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation
432 system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation
433 system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation
434 system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation
435 system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation
436 system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation
437 system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation
438 system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation
439 system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation
440 system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation
441 system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation
442 system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation
443 system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation
444 system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation
445 system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation
446 system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation
447 system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation
448 system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation
449 system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation
450 system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation
451 system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation
452 system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation
453 system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation
454 system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation
455 system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation
456 system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation
457 system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation
458 system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation
459 system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation
460 system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation
461 system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation
462 system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation
463 system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation
464 system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation
465 system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation
466 system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation
467 system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation
468 system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation
469 system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation
470 system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation
471 system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation
472 system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation
473 system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation
474 system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation
475 system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation
476 system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation
477 system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation
478 system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation
479 system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation
480 system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation
481 system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation
482 system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation
483 system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation
484 system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation
485 system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation
486 system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation
487 system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation
488 system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation
489 system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation
490 system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation
491 system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation
492 system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation
493 system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation
494 system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation
495 system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation
496 system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation
497 system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation
498 system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation
499 system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation
500 system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation
501 system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation
502 system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # Bytes accessed per row activation
503 system.physmem.bytesPerActivate::38400-38407 128 0.15% 87.17% # Bytes accessed per row activation
504 system.physmem.bytesPerActivate::38656-38663 68 0.08% 87.25% # Bytes accessed per row activation
505 system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation
506 system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.25% # Bytes accessed per row activation
507 system.physmem.bytesPerActivate::38912-38919 253 0.29% 87.54% # Bytes accessed per row activation
508 system.physmem.bytesPerActivate::39168-39175 134 0.15% 87.70% # Bytes accessed per row activation
509 system.physmem.bytesPerActivate::39680-39687 66 0.08% 87.77% # Bytes accessed per row activation
510 system.physmem.bytesPerActivate::39936-39943 448 0.52% 88.29% # Bytes accessed per row activation
511 system.physmem.bytesPerActivate::40192-40199 68 0.08% 88.37% # Bytes accessed per row activation
512 system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.37% # Bytes accessed per row activation
513 system.physmem.bytesPerActivate::40448-40455 66 0.08% 88.44% # Bytes accessed per row activation
514 system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation
515 system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation
516 system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation
517 system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation
518 system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation
519 system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation
520 system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation
521 system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation
522 system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation
523 system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation
524 system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation
525 system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation
526 system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation
527 system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation
528 system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation
529 system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation
530 system.physmem.bytesPerActivate::43776-43783 67 0.08% 90.40% # Bytes accessed per row activation
531 system.physmem.bytesPerActivate::44032-44039 384 0.44% 90.84% # Bytes accessed per row activation
532 system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.84% # Bytes accessed per row activation
533 system.physmem.bytesPerActivate::44288-44295 68 0.08% 90.92% # Bytes accessed per row activation
534 system.physmem.bytesPerActivate::44352-44359 1 0.00% 90.92% # Bytes accessed per row activation
535 system.physmem.bytesPerActivate::44480-44487 1 0.00% 90.92% # Bytes accessed per row activation
536 system.physmem.bytesPerActivate::44544-44551 119 0.14% 91.06% # Bytes accessed per row activation
537 system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.06% # Bytes accessed per row activation
538 system.physmem.bytesPerActivate::44800-44807 66 0.08% 91.14% # Bytes accessed per row activation
539 system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.14% # Bytes accessed per row activation
540 system.physmem.bytesPerActivate::45056-45063 383 0.44% 91.58% # Bytes accessed per row activation
541 system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.58% # Bytes accessed per row activation
542 system.physmem.bytesPerActivate::45312-45319 41 0.05% 91.63% # Bytes accessed per row activation
543 system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.71% # Bytes accessed per row activation
544 system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.71% # Bytes accessed per row activation
545 system.physmem.bytesPerActivate::45824-45831 65 0.07% 91.78% # Bytes accessed per row activation
546 system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.79% # Bytes accessed per row activation
547 system.physmem.bytesPerActivate::46080-46087 385 0.44% 92.23% # Bytes accessed per row activation
548 system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.23% # Bytes accessed per row activation
549 system.physmem.bytesPerActivate::46336-46343 129 0.15% 92.38% # Bytes accessed per row activation
550 system.physmem.bytesPerActivate::46592-46599 64 0.07% 92.45% # Bytes accessed per row activation
551 system.physmem.bytesPerActivate::46848-46855 119 0.14% 92.59% # Bytes accessed per row activation
552 system.physmem.bytesPerActivate::47104-47111 440 0.51% 93.10% # Bytes accessed per row activation
553 system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.10% # Bytes accessed per row activation
554 system.physmem.bytesPerActivate::47360-47367 58 0.07% 93.16% # Bytes accessed per row activation
555 system.physmem.bytesPerActivate::47616-47623 14 0.02% 93.18% # Bytes accessed per row activation
556 system.physmem.bytesPerActivate::47872-47879 120 0.14% 93.32% # Bytes accessed per row activation
557 system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.32% # Bytes accessed per row activation
558 system.physmem.bytesPerActivate::48128-48135 388 0.45% 93.77% # Bytes accessed per row activation
559 system.physmem.bytesPerActivate::48384-48391 122 0.14% 93.91% # Bytes accessed per row activation
560 system.physmem.bytesPerActivate::48640-48647 64 0.07% 93.98% # Bytes accessed per row activation
561 system.physmem.bytesPerActivate::48896-48903 65 0.07% 94.06% # Bytes accessed per row activation
562 system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation
563 system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.06% # Bytes accessed per row activation
564 system.physmem.bytesPerActivate::49152-49159 5147 5.93% 99.99% # Bytes accessed per row activation
565 system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.99% # Bytes accessed per row activation
566 system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation
567 system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation
568 system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation
569 system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation
570 system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation
571 system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation
572 system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation
573 system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation
574 system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation
575 system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation
576 system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation
577 system.physmem.totQLat 369633946000 # Total ticks spent queuing
578 system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM
579 system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers
580 system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks
581 system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst
582 system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst
583 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
584 system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst
585 system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s
586 system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s
587 system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s
588 system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
589 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
590 system.physmem.busUtil 3.02 # Data bus utilization in percentage
591 system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
592 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
593 system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
594 system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing
595 system.physmem.readRowHits 15212610 # Number of row buffer hits during reads
596 system.physmem.writeRowHits 93178 # Number of row buffer hits during writes
597 system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads
598 system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes
599 system.physmem.avgGap 158277.83 # Average gap between requests
600 system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined
601 system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state
602 system.membus.throughput 54996997 # Throughput (bytes/s)
603 system.membus.trans_dist::ReadReq 16346113 # Transaction distribution
604 system.membus.trans_dist::ReadResp 16346116 # Transaction distribution
605 system.membus.trans_dist::WriteReq 763348 # Transaction distribution
606 system.membus.trans_dist::WriteResp 763348 # Transaction distribution
607 system.membus.trans_dist::Writeback 59151 # Transaction distribution
608 system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution
609 system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
610 system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution
611 system.membus.trans_dist::ReadExReq 131399 # Transaction distribution
612 system.membus.trans_dist::ReadExResp 131399 # Transaction distribution
613 system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
614 system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
615 system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
616 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes)
617 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
618 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
619 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
620 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes)
621 system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes)
622 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
623 system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
624 system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes)
625 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes)
626 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
627 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
628 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
629 system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes)
630 system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes)
631 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
632 system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
633 system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes)
634 system.membus.data_through_bus 140205229 # Total data (bytes)
635 system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
636 system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks)
637 system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
638 system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
639 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
640 system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks)
641 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
642 system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
643 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
644 system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks)
645 system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
646 system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks)
647 system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
648 system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks)
649 system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
650 system.l2c.tags.replacements 64379 # number of replacements
651 system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use
652 system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks.
653 system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks.
654 system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks.
655 system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit.
656 system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor
657 system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor
658 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor
659 system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor
660 system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor
661 system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor
662 system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor
663 system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor
664 system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy
665 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy
666 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
667 system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy
668 system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy
669 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy
670 system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy
671 system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy
672 system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy
673 system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits
674 system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits
675 system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits
676 system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits
677 system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits
678 system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits
679 system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits
680 system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits
681 system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits
682 system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits
683 system.l2c.Writeback_hits::total 608382 # number of Writeback hits
684 system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits
685 system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits
686 system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits
687 system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
688 system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits
689 system.l2c.SCUpgradeReq_hits::total 15 # number of SCUpgradeReq hits
690 system.l2c.ReadExReq_hits::cpu0.data 58173 # number of ReadExReq hits
691 system.l2c.ReadExReq_hits::cpu1.data 54780 # number of ReadExReq hits
692 system.l2c.ReadExReq_hits::total 112953 # number of ReadExReq hits
693 system.l2c.demand_hits::cpu0.dtb.walker 32603 # number of demand (read+write) hits
694 system.l2c.demand_hits::cpu0.itb.walker 7139 # number of demand (read+write) hits
695 system.l2c.demand_hits::cpu0.inst 505956 # number of demand (read+write) hits
696 system.l2c.demand_hits::cpu0.data 240291 # number of demand (read+write) hits
697 system.l2c.demand_hits::cpu1.dtb.walker 30730 # number of demand (read+write) hits
698 system.l2c.demand_hits::cpu1.itb.walker 6661 # number of demand (read+write) hits
699 system.l2c.demand_hits::cpu1.inst 464492 # number of demand (read+write) hits
700 system.l2c.demand_hits::cpu1.data 260282 # number of demand (read+write) hits
701 system.l2c.demand_hits::total 1548154 # number of demand (read+write) hits
702 system.l2c.overall_hits::cpu0.dtb.walker 32603 # number of overall hits
703 system.l2c.overall_hits::cpu0.itb.walker 7139 # number of overall hits
704 system.l2c.overall_hits::cpu0.inst 505956 # number of overall hits
705 system.l2c.overall_hits::cpu0.data 240291 # number of overall hits
706 system.l2c.overall_hits::cpu1.dtb.walker 30730 # number of overall hits
707 system.l2c.overall_hits::cpu1.itb.walker 6661 # number of overall hits
708 system.l2c.overall_hits::cpu1.inst 464492 # number of overall hits
709 system.l2c.overall_hits::cpu1.data 260282 # number of overall hits
710 system.l2c.overall_hits::total 1548154 # number of overall hits
711 system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses
712 system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
713 system.l2c.ReadReq_misses::cpu0.inst 7825 # number of ReadReq misses
714 system.l2c.ReadReq_misses::cpu0.data 6187 # number of ReadReq misses
715 system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses
716 system.l2c.ReadReq_misses::cpu1.inst 4565 # number of ReadReq misses
717 system.l2c.ReadReq_misses::cpu1.data 4551 # number of ReadReq misses
718 system.l2c.ReadReq_misses::total 23171 # number of ReadReq misses
719 system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses
720 system.l2c.UpgradeReq_misses::cpu1.data 1631 # number of UpgradeReq misses
721 system.l2c.UpgradeReq_misses::total 2916 # number of UpgradeReq misses
722 system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
723 system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
724 system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
725 system.l2c.ReadExReq_misses::cpu0.data 68474 # number of ReadExReq misses
726 system.l2c.ReadExReq_misses::cpu1.data 64717 # number of ReadExReq misses
727 system.l2c.ReadExReq_misses::total 133191 # number of ReadExReq misses
728 system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
729 system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
730 system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses
731 system.l2c.demand_misses::cpu0.data 74661 # number of demand (read+write) misses
732 system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses
733 system.l2c.demand_misses::cpu1.inst 4565 # number of demand (read+write) misses
734 system.l2c.demand_misses::cpu1.data 69268 # number of demand (read+write) misses
735 system.l2c.demand_misses::total 156362 # number of demand (read+write) misses
736 system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses
737 system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
738 system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses
739 system.l2c.overall_misses::cpu0.data 74661 # number of overall misses
740 system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses
741 system.l2c.overall_misses::cpu1.inst 4565 # number of overall misses
742 system.l2c.overall_misses::cpu1.data 69268 # number of overall misses
743 system.l2c.overall_misses::total 156362 # number of overall misses
744 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2234250 # number of ReadReq miss cycles
745 system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles
746 system.l2c.ReadReq_miss_latency::cpu0.inst 566532750 # number of ReadReq miss cycles
747 system.l2c.ReadReq_miss_latency::cpu0.data 458261500 # number of ReadReq miss cycles
748 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1111500 # number of ReadReq miss cycles
749 system.l2c.ReadReq_miss_latency::cpu1.inst 342566000 # number of ReadReq miss cycles
750 system.l2c.ReadReq_miss_latency::cpu1.data 354437999 # number of ReadReq miss cycles
751 system.l2c.ReadReq_miss_latency::total 1725301999 # number of ReadReq miss cycles
752 system.l2c.UpgradeReq_miss_latency::cpu0.data 254989 # number of UpgradeReq miss cycles
753 system.l2c.UpgradeReq_miss_latency::cpu1.data 187492 # number of UpgradeReq miss cycles
754 system.l2c.UpgradeReq_miss_latency::total 442481 # number of UpgradeReq miss cycles
755 system.l2c.ReadExReq_miss_latency::cpu0.data 5097311886 # number of ReadExReq miss cycles
756 system.l2c.ReadExReq_miss_latency::cpu1.data 4928859322 # number of ReadExReq miss cycles
757 system.l2c.ReadExReq_miss_latency::total 10026171208 # number of ReadExReq miss cycles
758 system.l2c.demand_miss_latency::cpu0.dtb.walker 2234250 # number of demand (read+write) miss cycles
759 system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles
760 system.l2c.demand_miss_latency::cpu0.inst 566532750 # number of demand (read+write) miss cycles
761 system.l2c.demand_miss_latency::cpu0.data 5555573386 # number of demand (read+write) miss cycles
762 system.l2c.demand_miss_latency::cpu1.dtb.walker 1111500 # number of demand (read+write) miss cycles
763 system.l2c.demand_miss_latency::cpu1.inst 342566000 # number of demand (read+write) miss cycles
764 system.l2c.demand_miss_latency::cpu1.data 5283297321 # number of demand (read+write) miss cycles
765 system.l2c.demand_miss_latency::total 11751473207 # number of demand (read+write) miss cycles
766 system.l2c.overall_miss_latency::cpu0.dtb.walker 2234250 # number of overall miss cycles
767 system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles
768 system.l2c.overall_miss_latency::cpu0.inst 566532750 # number of overall miss cycles
769 system.l2c.overall_miss_latency::cpu0.data 5555573386 # number of overall miss cycles
770 system.l2c.overall_miss_latency::cpu1.dtb.walker 1111500 # number of overall miss cycles
771 system.l2c.overall_miss_latency::cpu1.inst 342566000 # number of overall miss cycles
772 system.l2c.overall_miss_latency::cpu1.data 5283297321 # number of overall miss cycles
773 system.l2c.overall_miss_latency::total 11751473207 # number of overall miss cycles
774 system.l2c.ReadReq_accesses::cpu0.dtb.walker 32630 # number of ReadReq accesses(hits+misses)
775 system.l2c.ReadReq_accesses::cpu0.itb.walker 7141 # number of ReadReq accesses(hits+misses)
776 system.l2c.ReadReq_accesses::cpu0.inst 513781 # number of ReadReq accesses(hits+misses)
777 system.l2c.ReadReq_accesses::cpu0.data 188305 # number of ReadReq accesses(hits+misses)
778 system.l2c.ReadReq_accesses::cpu1.dtb.walker 30744 # number of ReadReq accesses(hits+misses)
779 system.l2c.ReadReq_accesses::cpu1.itb.walker 6661 # number of ReadReq accesses(hits+misses)
780 system.l2c.ReadReq_accesses::cpu1.inst 469057 # number of ReadReq accesses(hits+misses)
781 system.l2c.ReadReq_accesses::cpu1.data 210053 # number of ReadReq accesses(hits+misses)
782 system.l2c.ReadReq_accesses::total 1458372 # number of ReadReq accesses(hits+misses)
783 system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses)
784 system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses)
785 system.l2c.UpgradeReq_accesses::cpu0.data 1307 # number of UpgradeReq accesses(hits+misses)
786 system.l2c.UpgradeReq_accesses::cpu1.data 1649 # number of UpgradeReq accesses(hits+misses)
787 system.l2c.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses)
788 system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses)
789 system.l2c.SCUpgradeReq_accesses::cpu1.data 12 # number of SCUpgradeReq accesses(hits+misses)
790 system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses)
791 system.l2c.ReadExReq_accesses::cpu0.data 126647 # number of ReadExReq accesses(hits+misses)
792 system.l2c.ReadExReq_accesses::cpu1.data 119497 # number of ReadExReq accesses(hits+misses)
793 system.l2c.ReadExReq_accesses::total 246144 # number of ReadExReq accesses(hits+misses)
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821 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989084 # miss rate for UpgradeReq accesses
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990 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989084 # mshr miss rate for UpgradeReq accesses
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993 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
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1006 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for overall accesses
1007 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for overall accesses
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1019 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency
1020 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency
1021 system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency
1022 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
1023 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency
1024 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency
1025 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
1026 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
1027 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
1028 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency
1029 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency
1030 system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency
1031 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency
1032 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
1033 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency
1034 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency
1035 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency
1036 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency
1037 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency
1038 system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency
1039 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency
1040 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
1041 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency
1042 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency
1043 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency
1044 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency
1045 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency
1046 system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency
1047 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1048 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1049 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1050 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1051 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1052 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1053 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1054 system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
1055 system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
1056 system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
1057 system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
1058 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1059 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1060 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1061 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1062 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1063 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1064 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1065 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1066 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
1067 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
1068 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
1069 system.toL2Bus.throughput 58456334 # Throughput (bytes/s)
1070 system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution
1071 system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution
1072 system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
1073 system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
1074 system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution
1075 system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution
1076 system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution
1077 system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution
1078 system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution
1079 system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution
1080 system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
1081 system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
1082 system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
1083 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes)
1084 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes)
1085 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes)
1086 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes)
1087 system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes)
1088 system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes)
1089 system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes)
1090 system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes)
1091 system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes)
1092 system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes)
1093 system.toL2Bus.data_through_bus 148816461 # Total data (bytes)
1094 system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes)
1095 system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks)
1096 system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1097 system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks)
1098 system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1099 system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks)
1100 system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
1101 system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks)
1102 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1103 system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks)
1104 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1105 system.iobus.throughput 48444532 # Throughput (bytes/s)
1106 system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution
1107 system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution
1108 system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
1109 system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
1110 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
1111 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
1112 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
1113 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
1114 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
1115 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1116 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
1117 system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
1118 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
1119 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1120 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1121 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1122 system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
1123 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
1124 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1125 system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
1126 system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
1127 system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
1128 system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
1129 system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
1130 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1131 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1132 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1133 system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes)
1134 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
1135 system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
1136 system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes)
1137 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
1138 system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
1139 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
1140 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
1141 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
1142 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1143 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
1144 system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
1145 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1146 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1147 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1148 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1149 system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1150 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
1151 system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1152 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1153 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1154 system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1155 system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1156 system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1157 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1158 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1159 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1160 system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes)
1161 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
1162 system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
1163 system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes)
1164 system.iobus.data_through_bus 123500865 # Total data (bytes)
1165 system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
1166 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1167 system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
1168 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1169 system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
1170 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1171 system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
1172 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1173 system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
1174 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1175 system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
1176 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1177 system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
1178 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1179 system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
1180 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1181 system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
1182 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1183 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1184 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1185 system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
1186 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1187 system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
1188 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1189 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1190 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1191 system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1192 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1193 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1194 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1195 system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
1196 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1197 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1198 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1199 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
1200 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1201 system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
1202 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1203 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
1204 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1205 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
1206 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1207 system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
1208 system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1209 system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
1210 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1211 system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
1212 system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
1213 system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks)
1214 system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
1215 system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks)
1216 system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
1217 system.cpu0.branchPred.lookups 7178846 # Number of BP lookups
1218 system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted
1219 system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect
1220 system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups
1221 system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits
1222 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1223 system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage
1224 system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target.
1225 system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions.
1226 system.cpu0.dtb.inst_hits 0 # ITB inst hits
1227 system.cpu0.dtb.inst_misses 0 # ITB inst misses
1228 system.cpu0.dtb.read_hits 25686724 # DTB read hits
1229 system.cpu0.dtb.read_misses 37672 # DTB read misses
1230 system.cpu0.dtb.write_hits 5882199 # DTB write hits
1231 system.cpu0.dtb.write_misses 9157 # DTB write misses
1232 system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
1233 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1234 system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID
1235 system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
1236 system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB
1237 system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions
1238 system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch
1239 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1240 system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions
1241 system.cpu0.dtb.read_accesses 25724396 # DTB read accesses
1242 system.cpu0.dtb.write_accesses 5891356 # DTB write accesses
1243 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1244 system.cpu0.dtb.hits 31568923 # DTB hits
1245 system.cpu0.dtb.misses 46829 # DTB misses
1246 system.cpu0.dtb.accesses 31615752 # DTB accesses
1247 system.cpu0.itb.inst_hits 5794960 # ITB inst hits
1248 system.cpu0.itb.inst_misses 6979 # ITB inst misses
1249 system.cpu0.itb.read_hits 0 # DTB read hits
1250 system.cpu0.itb.read_misses 0 # DTB read misses
1251 system.cpu0.itb.write_hits 0 # DTB write hits
1252 system.cpu0.itb.write_misses 0 # DTB write misses
1253 system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
1254 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1255 system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID
1256 system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
1257 system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB
1258 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1259 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1260 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1261 system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions
1262 system.cpu0.itb.read_accesses 0 # DTB read accesses
1263 system.cpu0.itb.write_accesses 0 # DTB write accesses
1264 system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses
1265 system.cpu0.itb.hits 5794960 # DTB hits
1266 system.cpu0.itb.misses 6979 # DTB misses
1267 system.cpu0.itb.accesses 5801939 # DTB accesses
1268 system.cpu0.numCycles 241329954 # number of cpu cycles simulated
1269 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1270 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1271 system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss
1272 system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed
1273 system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered
1274 system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken
1275 system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked
1276 system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing
1277 system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb
1278 system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked
1279 system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1280 system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain
1281 system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps
1282 system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions
1283 system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR
1284 system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched
1285 system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed
1286 system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed
1287 system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total)
1288 system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total)
1289 system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total)
1290 system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1291 system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total)
1292 system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total)
1293 system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total)
1294 system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total)
1295 system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total)
1296 system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total)
1297 system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total)
1298 system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total)
1299 system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total)
1300 system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1301 system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1302 system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1303 system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total)
1304 system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle
1305 system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle
1306 system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle
1307 system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked
1308 system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running
1309 system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking
1310 system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing
1311 system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch
1312 system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction
1313 system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode
1314 system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode
1315 system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing
1316 system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle
1317 system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking
1318 system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst
1319 system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running
1320 system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking
1321 system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename
1322 system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full
1323 system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full
1324 system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full
1325 system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers
1326 system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed
1327 system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made
1328 system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups
1329 system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups
1330 system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed
1331 system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing
1332 system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed
1333 system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed
1334 system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer
1335 system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit.
1336 system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit.
1337 system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads.
1338 system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores.
1339 system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec)
1340 system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ
1341 system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued
1342 system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued
1343 system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling
1344 system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph
1345 system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed
1346 system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle
1347 system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle
1348 system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle
1349 system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1350 system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle
1351 system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle
1352 system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle
1353 system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle
1354 system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle
1355 system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle
1356 system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle
1357 system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle
1358 system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle
1359 system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1360 system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1361 system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1362 system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle
1363 system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1364 system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available
1365 system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available
1366 system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
1367 system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
1368 system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
1369 system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
1370 system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
1371 system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
1372 system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
1373 system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
1374 system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
1375 system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
1376 system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
1377 system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
1378 system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
1379 system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
1380 system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
1381 system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
1382 system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
1383 system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
1384 system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
1385 system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
1386 system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
1387 system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
1388 system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
1389 system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
1390 system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
1391 system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
1392 system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
1393 system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available
1394 system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available
1395 system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1396 system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1397 system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued
1398 system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued
1399 system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued
1400 system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued
1401 system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued
1402 system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued
1403 system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued
1404 system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued
1405 system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued
1406 system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued
1407 system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued
1408 system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued
1409 system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued
1410 system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued
1411 system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued
1412 system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued
1413 system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued
1414 system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued
1415 system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued
1416 system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued
1417 system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued
1418 system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued
1419 system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued
1420 system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued
1421 system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued
1422 system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued
1423 system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued
1424 system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued
1425 system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued
1426 system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued
1427 system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued
1428 system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued
1429 system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1430 system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1431 system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued
1432 system.cpu0.iq.rate 0.252886 # Inst issue rate
1433 system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested
1434 system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst)
1435 system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads
1436 system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes
1437 system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses
1438 system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads
1439 system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes
1440 system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses
1441 system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses
1442 system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses
1443 system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores
1444 system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1445 system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed
1446 system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed
1447 system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations
1448 system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed
1449 system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1450 system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1451 system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled
1452 system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked
1453 system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1454 system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing
1455 system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking
1456 system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking
1457 system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ
1458 system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch
1459 system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions
1460 system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions
1461 system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions
1462 system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall
1463 system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall
1464 system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations
1465 system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly
1466 system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly
1467 system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute
1468 system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions
1469 system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed
1470 system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute
1471 system.cpu0.iew.exec_swp 0 # number of swp insts executed
1472 system.cpu0.iew.exec_nop 100254 # number of nop insts executed
1473 system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed
1474 system.cpu0.iew.exec_branches 5674244 # Number of branches executed
1475 system.cpu0.iew.exec_stores 6127115 # Number of stores executed
1476 system.cpu0.iew.exec_rate 0.248501 # Inst execution rate
1477 system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit
1478 system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back
1479 system.cpu0.iew.wb_producers 22797313 # num instructions producing a value
1480 system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value
1481 system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1482 system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle
1483 system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back
1484 system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1485 system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit
1486 system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards
1487 system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted
1488 system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle
1489 system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle
1490 system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle
1491 system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1492 system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle
1493 system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle
1494 system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle
1495 system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle
1496 system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle
1497 system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle
1498 system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle
1499 system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle
1500 system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle
1501 system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1502 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1503 system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1504 system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle
1505 system.cpu0.commit.committedInsts 29321704 # Number of instructions committed
1506 system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed
1507 system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
1508 system.cpu0.commit.refs 13559265 # Number of memory references committed
1509 system.cpu0.commit.loads 7698037 # Number of loads committed
1510 system.cpu0.commit.membars 204059 # Number of memory barriers committed
1511 system.cpu0.commit.branches 4889328 # Number of branches committed
1512 system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions.
1513 system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions.
1514 system.cpu0.commit.function_calls 497179 # Number of function calls committed.
1515 system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached
1516 system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
1517 system.cpu0.rob.rob_reads 121250209 # The number of ROB reads
1518 system.cpu0.rob.rob_writes 97007351 # The number of ROB writes
1519 system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself
1520 system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling
1521 system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1522 system.cpu0.committedInsts 29254206 # Number of Instructions Simulated
1523 system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated
1524 system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated
1525 system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction
1526 system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads
1527 system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle
1528 system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads
1529 system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads
1530 system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes
1531 system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads
1532 system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes
1533 system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads
1534 system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes
1535 system.cpu0.icache.tags.replacements 983492 # number of replacements
1536 system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use
1537 system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks.
1538 system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks.
1539 system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks.
1540 system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit.
1541 system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor
1542 system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor
1543 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy
1544 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy
1545 system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy
1546 system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits
1547 system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits
1548 system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits
1549 system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits
1550 system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits
1551 system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits
1552 system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits
1553 system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits
1554 system.cpu0.icache.overall_hits::total 10516196 # number of overall hits
1555 system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses
1556 system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses
1557 system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses
1558 system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses
1559 system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses
1560 system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses
1561 system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses
1562 system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses
1563 system.cpu0.icache.overall_misses::total 1065369 # number of overall misses
1564 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles
1565 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles
1566 system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles
1567 system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles
1568 system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles
1569 system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles
1570 system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles
1571 system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles
1572 system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles
1573 system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses)
1574 system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses)
1575 system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses)
1576 system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses
1577 system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses
1578 system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses
1579 system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses
1580 system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses
1581 system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses
1582 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses
1583 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses
1584 system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses
1585 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses
1586 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses
1587 system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses
1588 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses
1589 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses
1590 system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses
1591 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency
1592 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency
1593 system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency
1594 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency
1595 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency
1596 system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency
1597 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency
1598 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency
1599 system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency
1600 system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked
1601 system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked
1602 system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked
1603 system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
1604 system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.897561 # average number of cycles each access was blocked
1605 system.cpu0.icache.avg_blocked_cycles::no_targets 829 # average number of cycles each access was blocked
1606 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1607 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1608 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits
1609 system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38074 # number of ReadReq MSHR hits
1610 system.cpu0.icache.ReadReq_mshr_hits::total 81323 # number of ReadReq MSHR hits
1611 system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits
1612 system.cpu0.icache.demand_mshr_hits::cpu1.inst 38074 # number of demand (read+write) MSHR hits
1613 system.cpu0.icache.demand_mshr_hits::total 81323 # number of demand (read+write) MSHR hits
1614 system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits
1615 system.cpu0.icache.overall_mshr_hits::cpu1.inst 38074 # number of overall MSHR hits
1616 system.cpu0.icache.overall_mshr_hits::total 81323 # number of overall MSHR hits
1617 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514371 # number of ReadReq MSHR misses
1618 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469675 # number of ReadReq MSHR misses
1619 system.cpu0.icache.ReadReq_mshr_misses::total 984046 # number of ReadReq MSHR misses
1620 system.cpu0.icache.demand_mshr_misses::cpu0.inst 514371 # number of demand (read+write) MSHR misses
1621 system.cpu0.icache.demand_mshr_misses::cpu1.inst 469675 # number of demand (read+write) MSHR misses
1622 system.cpu0.icache.demand_mshr_misses::total 984046 # number of demand (read+write) MSHR misses
1623 system.cpu0.icache.overall_mshr_misses::cpu0.inst 514371 # number of overall MSHR misses
1624 system.cpu0.icache.overall_mshr_misses::cpu1.inst 469675 # number of overall MSHR misses
1625 system.cpu0.icache.overall_mshr_misses::total 984046 # number of overall MSHR misses
1626 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258994404 # number of ReadReq MSHR miss cycles
1627 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles
1628 system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles
1629 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles
1630 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles
1631 system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles
1632 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles
1633 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles
1634 system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles
1635 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles
1636 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # number of ReadReq MSHR uncacheable cycles
1637 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8426500 # number of overall MSHR uncacheable cycles
1638 system.cpu0.icache.overall_mshr_uncacheable_latency::total 8426500 # number of overall MSHR uncacheable cycles
1639 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for ReadReq accesses
1640 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for ReadReq accesses
1641 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084967 # mshr miss rate for ReadReq accesses
1642 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for demand accesses
1643 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for demand accesses
1644 system.cpu0.icache.demand_mshr_miss_rate::total 0.084967 # mshr miss rate for demand accesses
1645 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for overall accesses
1646 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for overall accesses
1647 system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses
1648 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency
1649 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency
1650 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency
1651 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency
1652 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency
1653 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency
1654 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency
1655 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency
1656 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency
1657 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1658 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1659 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1660 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1661 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1662 system.cpu0.dcache.tags.replacements 643990 # number of replacements
1663 system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use
1664 system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks.
1665 system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks.
1666 system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks.
1667 system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit.
1668 system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.795317 # Average occupied blocks per requestor
1669 system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.198007 # Average occupied blocks per requestor
1670 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499600 # Average percentage of cache occupancy
1671 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500387 # Average percentage of cache occupancy
1672 system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
1673 system.cpu0.dcache.ReadReq_hits::cpu0.data 6836118 # number of ReadReq hits
1674 system.cpu0.dcache.ReadReq_hits::cpu1.data 6942659 # number of ReadReq hits
1675 system.cpu0.dcache.ReadReq_hits::total 13778777 # number of ReadReq hits
1676 system.cpu0.dcache.WriteReq_hits::cpu0.data 3601868 # number of WriteReq hits
1677 system.cpu0.dcache.WriteReq_hits::cpu1.data 3659456 # number of WriteReq hits
1678 system.cpu0.dcache.WriteReq_hits::total 7261324 # number of WriteReq hits
1679 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114429 # number of LoadLockedReq hits
1680 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 128738 # number of LoadLockedReq hits
1681 system.cpu0.dcache.LoadLockedReq_hits::total 243167 # number of LoadLockedReq hits
1682 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116989 # number of StoreCondReq hits
1683 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 130670 # number of StoreCondReq hits
1684 system.cpu0.dcache.StoreCondReq_hits::total 247659 # number of StoreCondReq hits
1685 system.cpu0.dcache.demand_hits::cpu0.data 10437986 # number of demand (read+write) hits
1686 system.cpu0.dcache.demand_hits::cpu1.data 10602115 # number of demand (read+write) hits
1687 system.cpu0.dcache.demand_hits::total 21040101 # number of demand (read+write) hits
1688 system.cpu0.dcache.overall_hits::cpu0.data 10437986 # number of overall hits
1689 system.cpu0.dcache.overall_hits::cpu1.data 10602115 # number of overall hits
1690 system.cpu0.dcache.overall_hits::total 21040101 # number of overall hits
1691 system.cpu0.dcache.ReadReq_misses::cpu0.data 327145 # number of ReadReq misses
1692 system.cpu0.dcache.ReadReq_misses::cpu1.data 421730 # number of ReadReq misses
1693 system.cpu0.dcache.ReadReq_misses::total 748875 # number of ReadReq misses
1694 system.cpu0.dcache.WriteReq_misses::cpu0.data 1520256 # number of WriteReq misses
1695 system.cpu0.dcache.WriteReq_misses::cpu1.data 1442024 # number of WriteReq misses
1696 system.cpu0.dcache.WriteReq_misses::total 2962280 # number of WriteReq misses
1697 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7436 # number of LoadLockedReq misses
1698 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6109 # number of LoadLockedReq misses
1699 system.cpu0.dcache.LoadLockedReq_misses::total 13545 # number of LoadLockedReq misses
1700 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
1701 system.cpu0.dcache.StoreCondReq_misses::cpu1.data 12 # number of StoreCondReq misses
1702 system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses
1703 system.cpu0.dcache.demand_misses::cpu0.data 1847401 # number of demand (read+write) misses
1704 system.cpu0.dcache.demand_misses::cpu1.data 1863754 # number of demand (read+write) misses
1705 system.cpu0.dcache.demand_misses::total 3711155 # number of demand (read+write) misses
1706 system.cpu0.dcache.overall_misses::cpu0.data 1847401 # number of overall misses
1707 system.cpu0.dcache.overall_misses::cpu1.data 1863754 # number of overall misses
1708 system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses
1709 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles
1710 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles
1711 system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles
1712 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles
1713 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles
1714 system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles
1715 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles
1716 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles
1717 system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles
1718 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles
1719 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 181002 # number of StoreCondReq miss cycles
1720 system.cpu0.dcache.StoreCondReq_miss_latency::total 271503 # number of StoreCondReq miss cycles
1721 system.cpu0.dcache.demand_miss_latency::cpu0.data 81375352865 # number of demand (read+write) miss cycles
1722 system.cpu0.dcache.demand_miss_latency::cpu1.data 79671913854 # number of demand (read+write) miss cycles
1723 system.cpu0.dcache.demand_miss_latency::total 161047266719 # number of demand (read+write) miss cycles
1724 system.cpu0.dcache.overall_miss_latency::cpu0.data 81375352865 # number of overall miss cycles
1725 system.cpu0.dcache.overall_miss_latency::cpu1.data 79671913854 # number of overall miss cycles
1726 system.cpu0.dcache.overall_miss_latency::total 161047266719 # number of overall miss cycles
1727 system.cpu0.dcache.ReadReq_accesses::cpu0.data 7163263 # number of ReadReq accesses(hits+misses)
1728 system.cpu0.dcache.ReadReq_accesses::cpu1.data 7364389 # number of ReadReq accesses(hits+misses)
1729 system.cpu0.dcache.ReadReq_accesses::total 14527652 # number of ReadReq accesses(hits+misses)
1730 system.cpu0.dcache.WriteReq_accesses::cpu0.data 5122124 # number of WriteReq accesses(hits+misses)
1731 system.cpu0.dcache.WriteReq_accesses::cpu1.data 5101480 # number of WriteReq accesses(hits+misses)
1732 system.cpu0.dcache.WriteReq_accesses::total 10223604 # number of WriteReq accesses(hits+misses)
1733 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121865 # number of LoadLockedReq accesses(hits+misses)
1734 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 134847 # number of LoadLockedReq accesses(hits+misses)
1735 system.cpu0.dcache.LoadLockedReq_accesses::total 256712 # number of LoadLockedReq accesses(hits+misses)
1736 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116995 # number of StoreCondReq accesses(hits+misses)
1737 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 130682 # number of StoreCondReq accesses(hits+misses)
1738 system.cpu0.dcache.StoreCondReq_accesses::total 247677 # number of StoreCondReq accesses(hits+misses)
1739 system.cpu0.dcache.demand_accesses::cpu0.data 12285387 # number of demand (read+write) accesses
1740 system.cpu0.dcache.demand_accesses::cpu1.data 12465869 # number of demand (read+write) accesses
1741 system.cpu0.dcache.demand_accesses::total 24751256 # number of demand (read+write) accesses
1742 system.cpu0.dcache.overall_accesses::cpu0.data 12285387 # number of overall (read+write) accesses
1743 system.cpu0.dcache.overall_accesses::cpu1.data 12465869 # number of overall (read+write) accesses
1744 system.cpu0.dcache.overall_accesses::total 24751256 # number of overall (read+write) accesses
1745 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045670 # miss rate for ReadReq accesses
1746 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057266 # miss rate for ReadReq accesses
1747 system.cpu0.dcache.ReadReq_miss_rate::total 0.051548 # miss rate for ReadReq accesses
1748 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.296802 # miss rate for WriteReq accesses
1749 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.282668 # miss rate for WriteReq accesses
1750 system.cpu0.dcache.WriteReq_miss_rate::total 0.289749 # miss rate for WriteReq accesses
1751 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses
1752 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045303 # miss rate for LoadLockedReq accesses
1753 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses
1754 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000051 # miss rate for StoreCondReq accesses
1755 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000092 # miss rate for StoreCondReq accesses
1756 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses
1757 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150374 # miss rate for demand accesses
1758 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149509 # miss rate for demand accesses
1759 system.cpu0.dcache.demand_miss_rate::total 0.149938 # miss rate for demand accesses
1760 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150374 # miss rate for overall accesses
1761 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149509 # miss rate for overall accesses
1762 system.cpu0.dcache.overall_miss_rate::total 0.149938 # miss rate for overall accesses
1763 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16074.813251 # average ReadReq miss latency
1764 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14642.808913 # average ReadReq miss latency
1765 system.cpu0.dcache.ReadReq_avg_miss_latency::total 15268.378012 # average ReadReq miss latency
1766 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50068.250403 # average WriteReq miss latency
1767 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50967.669089 # average WriteReq miss latency
1768 system.cpu0.dcache.WriteReq_avg_miss_latency::total 50506.083198 # average WriteReq miss latency
1769 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14289.066568 # average LoadLockedReq miss latency
1770 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13424.127680 # average LoadLockedReq miss latency
1771 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13898.966039 # average LoadLockedReq miss latency
1772 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency
1773 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15083.500000 # average StoreCondReq miss latency
1774 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency
1775 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency
1776 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency
1777 system.cpu0.dcache.demand_avg_miss_latency::total 43395.456864 # average overall miss latency
1778 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency
1779 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency
1780 system.cpu0.dcache.overall_avg_miss_latency::total 43395.456864 # average overall miss latency
1781 system.cpu0.dcache.blocked_cycles::no_mshrs 38322 # number of cycles access was blocked
1782 system.cpu0.dcache.blocked_cycles::no_targets 25151 # number of cycles access was blocked
1783 system.cpu0.dcache.blocked::no_mshrs 3482 # number of cycles access was blocked
1784 system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked
1785 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.005744 # average number of cycles each access was blocked
1786 system.cpu0.dcache.avg_blocked_cycles::no_targets 85.839590 # average number of cycles each access was blocked
1787 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1788 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1789 system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks
1790 system.cpu0.dcache.writebacks::total 608382 # number of writebacks
1791 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 145500 # number of ReadReq MSHR hits
1792 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217105 # number of ReadReq MSHR hits
1793 system.cpu0.dcache.ReadReq_mshr_hits::total 362605 # number of ReadReq MSHR hits
1794 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392355 # number of WriteReq MSHR hits
1795 system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1320933 # number of WriteReq MSHR hits
1796 system.cpu0.dcache.WriteReq_mshr_hits::total 2713288 # number of WriteReq MSHR hits
1797 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 723 # number of LoadLockedReq MSHR hits
1798 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 626 # number of LoadLockedReq MSHR hits
1799 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits
1800 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1537855 # number of demand (read+write) MSHR hits
1801 system.cpu0.dcache.demand_mshr_hits::cpu1.data 1538038 # number of demand (read+write) MSHR hits
1802 system.cpu0.dcache.demand_mshr_hits::total 3075893 # number of demand (read+write) MSHR hits
1803 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1537855 # number of overall MSHR hits
1804 system.cpu0.dcache.overall_mshr_hits::cpu1.data 1538038 # number of overall MSHR hits
1805 system.cpu0.dcache.overall_mshr_hits::total 3075893 # number of overall MSHR hits
1806 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181645 # number of ReadReq MSHR misses
1807 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 204625 # number of ReadReq MSHR misses
1808 system.cpu0.dcache.ReadReq_mshr_misses::total 386270 # number of ReadReq MSHR misses
1809 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127901 # number of WriteReq MSHR misses
1810 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121091 # number of WriteReq MSHR misses
1811 system.cpu0.dcache.WriteReq_mshr_misses::total 248992 # number of WriteReq MSHR misses
1812 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6713 # number of LoadLockedReq MSHR misses
1813 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5483 # number of LoadLockedReq MSHR misses
1814 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses
1815 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses
1816 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 12 # number of StoreCondReq MSHR misses
1817 system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses
1818 system.cpu0.dcache.demand_mshr_misses::cpu0.data 309546 # number of demand (read+write) MSHR misses
1819 system.cpu0.dcache.demand_mshr_misses::cpu1.data 325716 # number of demand (read+write) MSHR misses
1820 system.cpu0.dcache.demand_mshr_misses::total 635262 # number of demand (read+write) MSHR misses
1821 system.cpu0.dcache.overall_mshr_misses::cpu0.data 309546 # number of overall MSHR misses
1822 system.cpu0.dcache.overall_mshr_misses::cpu1.data 325716 # number of overall MSHR misses
1823 system.cpu0.dcache.overall_mshr_misses::total 635262 # number of overall MSHR misses
1824 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2539210775 # number of ReadReq MSHR miss cycles
1825 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2715181297 # number of ReadReq MSHR miss cycles
1826 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5254392072 # number of ReadReq MSHR miss cycles
1827 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5938244941 # number of WriteReq MSHR miss cycles
1828 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5721716845 # number of WriteReq MSHR miss cycles
1829 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11659961786 # number of WriteReq MSHR miss cycles
1830 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84451251 # number of LoadLockedReq MSHR miss cycles
1831 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63563504 # number of LoadLockedReq MSHR miss cycles
1832 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148014755 # number of LoadLockedReq MSHR miss cycles
1833 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles
1834 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 156998 # number of StoreCondReq MSHR miss cycles
1835 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 235497 # number of StoreCondReq MSHR miss cycles
1836 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8477455716 # number of demand (read+write) MSHR miss cycles
1837 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8436898142 # number of demand (read+write) MSHR miss cycles
1838 system.cpu0.dcache.demand_mshr_miss_latency::total 16914353858 # number of demand (read+write) MSHR miss cycles
1839 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8477455716 # number of overall MSHR miss cycles
1840 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8436898142 # number of overall MSHR miss cycles
1841 system.cpu0.dcache.overall_mshr_miss_latency::total 16914353858 # number of overall MSHR miss cycles
1842 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92366768250 # number of ReadReq MSHR uncacheable cycles
1843 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89963955251 # number of ReadReq MSHR uncacheable cycles
1844 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330723501 # number of ReadReq MSHR uncacheable cycles
1845 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13704367995 # number of WriteReq MSHR uncacheable cycles
1846 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13062365000 # number of WriteReq MSHR uncacheable cycles
1847 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26766732995 # number of WriteReq MSHR uncacheable cycles
1848 system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles
1849 system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles
1850 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
1851 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
1852 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles
1853 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles
1854 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles
1855 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses
1856 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses
1857 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses
1858 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses
1859 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses
1860 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses
1861 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses
1862 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses
1863 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses
1864 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses
1865 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses
1866 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses
1867 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses
1868 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses
1869 system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses
1870 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses
1871 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses
1872 system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses
1873 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency
1874 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency
1875 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency
1876 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency
1877 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency
1878 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency
1879 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency
1880 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency
1881 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency
1882 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency
1883 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency
1884 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency
1885 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency
1886 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency
1887 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency
1888 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency
1889 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency
1890 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency
1891 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1892 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1893 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1894 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1895 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1896 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1897 system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
1898 system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
1899 system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
1900 system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
1901 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1902 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1903 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1904 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1905 system.cpu1.branchPred.lookups 7299586 # Number of BP lookups
1906 system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted
1907 system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect
1908 system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups
1909 system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits
1910 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1911 system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage
1912 system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target.
1913 system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions.
1914 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1915 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1916 system.cpu1.dtb.read_hits 25535708 # DTB read hits
1917 system.cpu1.dtb.read_misses 37819 # DTB read misses
1918 system.cpu1.dtb.write_hits 5832824 # DTB write hits
1919 system.cpu1.dtb.write_misses 9748 # DTB write misses
1920 system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
1921 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1922 system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID
1923 system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
1924 system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB
1925 system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions
1926 system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch
1927 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1928 system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions
1929 system.cpu1.dtb.read_accesses 25573527 # DTB read accesses
1930 system.cpu1.dtb.write_accesses 5842572 # DTB write accesses
1931 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1932 system.cpu1.dtb.hits 31368532 # DTB hits
1933 system.cpu1.dtb.misses 47567 # DTB misses
1934 system.cpu1.dtb.accesses 31416099 # DTB accesses
1935 system.cpu1.itb.inst_hits 5790816 # ITB inst hits
1936 system.cpu1.itb.inst_misses 7158 # ITB inst misses
1937 system.cpu1.itb.read_hits 0 # DTB read hits
1938 system.cpu1.itb.read_misses 0 # DTB read misses
1939 system.cpu1.itb.write_hits 0 # DTB write hits
1940 system.cpu1.itb.write_misses 0 # DTB write misses
1941 system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
1942 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1943 system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID
1944 system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
1945 system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB
1946 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1947 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1948 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1949 system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions
1950 system.cpu1.itb.read_accesses 0 # DTB read accesses
1951 system.cpu1.itb.write_accesses 0 # DTB write accesses
1952 system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses
1953 system.cpu1.itb.hits 5790816 # DTB hits
1954 system.cpu1.itb.misses 7158 # DTB misses
1955 system.cpu1.itb.accesses 5797974 # DTB accesses
1956 system.cpu1.numCycles 235384601 # number of cpu cycles simulated
1957 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1958 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1959 system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss
1960 system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed
1961 system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered
1962 system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken
1963 system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked
1964 system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing
1965 system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb
1966 system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked
1967 system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1968 system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain
1969 system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps
1970 system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions
1971 system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR
1972 system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched
1973 system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed
1974 system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed
1975 system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total)
1976 system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total)
1977 system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total)
1978 system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1979 system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total)
1980 system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total)
1981 system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total)
1982 system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total)
1983 system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total)
1984 system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total)
1985 system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total)
1986 system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total)
1987 system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total)
1988 system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1989 system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1990 system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1991 system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total)
1992 system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle
1993 system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle
1994 system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle
1995 system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked
1996 system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running
1997 system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking
1998 system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing
1999 system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch
2000 system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction
2001 system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode
2002 system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode
2003 system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing
2004 system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle
2005 system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking
2006 system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst
2007 system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running
2008 system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking
2009 system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename
2010 system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full
2011 system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full
2012 system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full
2013 system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers
2014 system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed
2015 system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made
2016 system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups
2017 system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups
2018 system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed
2019 system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing
2020 system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed
2021 system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed
2022 system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer
2023 system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit.
2024 system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit.
2025 system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads.
2026 system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores.
2027 system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec)
2028 system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ
2029 system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued
2030 system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued
2031 system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling
2032 system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph
2033 system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed
2034 system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle
2035 system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle
2036 system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle
2037 system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2038 system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle
2039 system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle
2040 system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle
2041 system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle
2042 system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle
2043 system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle
2044 system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle
2045 system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle
2046 system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle
2047 system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2048 system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2049 system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2050 system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle
2051 system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2052 system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available
2053 system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available
2054 system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
2055 system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
2056 system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
2057 system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
2058 system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
2059 system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
2060 system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
2061 system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
2062 system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
2063 system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
2064 system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
2065 system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
2066 system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
2067 system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
2068 system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
2069 system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
2070 system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
2071 system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
2072 system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
2073 system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
2074 system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
2075 system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
2076 system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
2077 system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
2078 system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
2079 system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
2080 system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
2081 system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available
2082 system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available
2083 system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2084 system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2085 system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued
2086 system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued
2087 system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued
2088 system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued
2089 system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued
2090 system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued
2091 system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued
2092 system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued
2093 system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued
2094 system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued
2095 system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued
2096 system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued
2097 system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued
2098 system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued
2099 system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued
2100 system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued
2101 system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued
2102 system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued
2103 system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued
2104 system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued
2105 system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued
2106 system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued
2107 system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued
2108 system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued
2109 system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued
2110 system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued
2111 system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued
2112 system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued
2113 system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued
2114 system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued
2115 system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued
2116 system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued
2117 system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2118 system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2119 system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued
2120 system.cpu1.iq.rate 0.263554 # Inst issue rate
2121 system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested
2122 system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst)
2123 system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads
2124 system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes
2125 system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses
2126 system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads
2127 system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes
2128 system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses
2129 system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses
2130 system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses
2131 system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores
2132 system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2133 system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed
2134 system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed
2135 system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations
2136 system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed
2137 system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2138 system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2139 system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled
2140 system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked
2141 system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2142 system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing
2143 system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking
2144 system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking
2145 system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ
2146 system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch
2147 system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions
2148 system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions
2149 system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions
2150 system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall
2151 system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall
2152 system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations
2153 system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly
2154 system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly
2155 system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute
2156 system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions
2157 system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed
2158 system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute
2159 system.cpu1.iew.exec_swp 0 # number of swp insts executed
2160 system.cpu1.iew.exec_nop 121925 # number of nop insts executed
2161 system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed
2162 system.cpu1.iew.exec_branches 5823905 # Number of branches executed
2163 system.cpu1.iew.exec_stores 6100114 # Number of stores executed
2164 system.cpu1.iew.exec_rate 0.259152 # Inst execution rate
2165 system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit
2166 system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back
2167 system.cpu1.iew.wb_producers 24164344 # num instructions producing a value
2168 system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value
2169 system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2170 system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle
2171 system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back
2172 system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2173 system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit
2174 system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards
2175 system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted
2176 system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle
2177 system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle
2178 system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle
2179 system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2180 system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle
2181 system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle
2182 system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle
2183 system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle
2184 system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle
2185 system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle
2186 system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle
2187 system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle
2188 system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle
2189 system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2190 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2191 system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2192 system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle
2193 system.cpu1.commit.committedInsts 31143561 # Number of instructions committed
2194 system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed
2195 system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2196 system.cpu1.commit.refs 13831233 # Number of memory references committed
2197 system.cpu1.commit.loads 7959008 # Number of loads committed
2198 system.cpu1.commit.membars 199700 # Number of memory barriers committed
2199 system.cpu1.commit.branches 5073252 # Number of branches committed
2200 system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions.
2201 system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions.
2202 system.cpu1.commit.function_calls 494294 # Number of function calls committed.
2203 system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached
2204 system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
2205 system.cpu1.rob.rob_reads 121317994 # The number of ROB reads
2206 system.cpu1.rob.rob_writes 99664484 # The number of ROB writes
2207 system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself
2208 system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling
2209 system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2210 system.cpu1.committedInsts 31060678 # Number of Instructions Simulated
2211 system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated
2212 system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated
2213 system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction
2214 system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads
2215 system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle
2216 system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads
2217 system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads
2218 system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes
2219 system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads
2220 system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes
2221 system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads
2222 system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes
2223 system.iocache.tags.replacements 0 # number of replacements
2224 system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
2225 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2226 system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
2227 system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
2228 system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2229 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2230 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2231 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2232 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2233 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2234 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2235 system.iocache.fast_writes 0 # number of fast writes performed
2236 system.iocache.cache_copies 0 # number of cache copies performed
2237 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles
2238 system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles
2239 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles
2240 system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles
2241 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
2242 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2243 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
2244 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2245 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2246 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2247 system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed
2248 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2249 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
2251 ---------- End Simulation Statistics ----------
projects / gem5.git / blob