2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.904683 # Number of seconds simulated
4 sim_ticks 2904682547500 # Number of ticks simulated
5 final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 744036 # Simulator instruction rate (inst/s)
8 host_op_rate 897074 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 19213049576 # Simulator tick rate (ticks/s)
10 host_mem_usage 562336 # Number of bytes of host memory used
11 host_seconds 151.18 # Real time elapsed on the host
12 sim_insts 112485415 # Number of instructions simulated
13 sim_ops 135622211 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory
23 system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
24 system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory
25 system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory
28 system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory
29 system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
30 system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
31 system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
32 system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory
33 system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory
40 system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
41 system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory
42 system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory
43 system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
44 system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
45 system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
46 system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory
47 system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s)
57 system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s)
58 system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s)
59 system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s)
60 system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s)
61 system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
62 system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s)
63 system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s)
64 system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
66 system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
67 system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.readReqs 168816 # Number of read requests accepted
75 system.physmem.writeReqs 123423 # Number of write requests accepted
76 system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue
77 system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue
78 system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM
79 system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
80 system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM
81 system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side
82 system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side
83 system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
84 system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
85 system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write
86 system.physmem.perBankRdBursts::0 9768 # Per bank write bursts
87 system.physmem.perBankRdBursts::1 9653 # Per bank write bursts
88 system.physmem.perBankRdBursts::2 10324 # Per bank write bursts
89 system.physmem.perBankRdBursts::3 9994 # Per bank write bursts
90 system.physmem.perBankRdBursts::4 18675 # Per bank write bursts
91 system.physmem.perBankRdBursts::5 10148 # Per bank write bursts
92 system.physmem.perBankRdBursts::6 10372 # Per bank write bursts
93 system.physmem.perBankRdBursts::7 10429 # Per bank write bursts
94 system.physmem.perBankRdBursts::8 9938 # Per bank write bursts
95 system.physmem.perBankRdBursts::9 10451 # Per bank write bursts
96 system.physmem.perBankRdBursts::10 9811 # Per bank write bursts
97 system.physmem.perBankRdBursts::11 9561 # Per bank write bursts
98 system.physmem.perBankRdBursts::12 9986 # Per bank write bursts
99 system.physmem.perBankRdBursts::13 9803 # Per bank write bursts
100 system.physmem.perBankRdBursts::14 9966 # Per bank write bursts
101 system.physmem.perBankRdBursts::15 9791 # Per bank write bursts
102 system.physmem.perBankWrBursts::0 7253 # Per bank write bursts
103 system.physmem.perBankWrBursts::1 7191 # Per bank write bursts
104 system.physmem.perBankWrBursts::2 8157 # Per bank write bursts
105 system.physmem.perBankWrBursts::3 7614 # Per bank write bursts
106 system.physmem.perBankWrBursts::4 7092 # Per bank write bursts
107 system.physmem.perBankWrBursts::5 7380 # Per bank write bursts
108 system.physmem.perBankWrBursts::6 7560 # Per bank write bursts
109 system.physmem.perBankWrBursts::7 7725 # Per bank write bursts
110 system.physmem.perBankWrBursts::8 7575 # Per bank write bursts
111 system.physmem.perBankWrBursts::9 8007 # Per bank write bursts
112 system.physmem.perBankWrBursts::10 7415 # Per bank write bursts
113 system.physmem.perBankWrBursts::11 7436 # Per bank write bursts
114 system.physmem.perBankWrBursts::12 7462 # Per bank write bursts
115 system.physmem.perBankWrBursts::13 7248 # Per bank write bursts
116 system.physmem.perBankWrBursts::14 7309 # Per bank write bursts
117 system.physmem.perBankWrBursts::15 7126 # Per bank write bursts
118 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
119 system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
120 system.physmem.totGap 2904682181000 # Total gap between requests
121 system.physmem.readPktSize::0 0 # Read request sizes (log2)
122 system.physmem.readPktSize::1 0 # Read request sizes (log2)
123 system.physmem.readPktSize::2 9558 # Read request sizes (log2)
124 system.physmem.readPktSize::3 14 # Read request sizes (log2)
125 system.physmem.readPktSize::4 0 # Read request sizes (log2)
126 system.physmem.readPktSize::5 0 # Read request sizes (log2)
127 system.physmem.readPktSize::6 159244 # Read request sizes (log2)
128 system.physmem.writePktSize::0 0 # Write request sizes (log2)
129 system.physmem.writePktSize::1 0 # Write request sizes (log2)
130 system.physmem.writePktSize::2 4381 # Write request sizes (log2)
131 system.physmem.writePktSize::3 0 # Write request sizes (log2)
132 system.physmem.writePktSize::4 0 # Write request sizes (log2)
133 system.physmem.writePktSize::5 0 # Write request sizes (log2)
134 system.physmem.writePktSize::6 119042 # Write request sizes (log2)
135 system.physmem.rdQLenPdf::0 167845 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
167 system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::2 191 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::3 187 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::4 185 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::6 181 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::8 171 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::10 164 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::15 2142 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::16 2709 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::17 5948 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::18 6092 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::19 6127 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::20 6689 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::21 6919 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::22 7493 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::23 7962 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::24 8752 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::25 8130 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::26 7631 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::27 7029 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::28 6807 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::29 6096 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::30 5937 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::31 5907 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::32 5856 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::34 183 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::35 163 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::36 149 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::37 137 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::41 110 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
231 system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::stdev 335.865134 # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::256-383 5741 9.81% 71.34% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::384-511 3177 5.43% 76.77% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::512-639 2294 3.92% 80.70% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::640-767 1562 2.67% 83.37% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::total 58500 # Bytes accessed per row activation
245 system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes
246 system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes
247 system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes
248 system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes
249 system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
250 system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes
251 system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads
286 system.physmem.totQLat 1486855250 # Total ticks spent queuing
287 system.physmem.totMemAccLat 4649417750 # Total ticks spent from burst creation until serviced by the DRAM
288 system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers
289 system.physmem.avgQLat 8815.17 # Average queueing delay per DRAM burst
290 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
291 system.physmem.avgMemAccLat 27565.17 # Average memory access latency per DRAM burst
292 system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
293 system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
294 system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
295 system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
296 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
297 system.physmem.busUtil 0.05 # Data bus utilization in percentage
298 system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
299 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
300 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
301 system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing
302 system.physmem.readRowHits 139006 # Number of row buffer hits during reads
303 system.physmem.writeRowHits 90713 # Number of row buffer hits during writes
304 system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads
305 system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes
306 system.physmem.avgGap 9939406.38 # Average gap between requests
307 system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined
308 system.physmem.memoryStateTime::IDLE 2756105768250 # Time in different power states
309 system.physmem.memoryStateTime::REF 96993520000 # Time in different power states
310 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
311 system.physmem.memoryStateTime::ACT 51577106750 # Time in different power states
312 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
313 system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ)
314 system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ)
315 system.physmem.preEnergy::0 122623875 # Energy for precharge commands per rank (pJ)
316 system.physmem.preEnergy::1 118688625 # Energy for precharge commands per rank (pJ)
317 system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ)
318 system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ)
319 system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ)
320 system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ)
321 system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ)
322 system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ)
323 system.physmem.actBackEnergy::0 86946648885 # Energy for active background per rank (pJ)
324 system.physmem.actBackEnergy::1 86006740545 # Energy for active background per rank (pJ)
325 system.physmem.preBackEnergy::0 1666536838500 # Energy for precharge background per rank (pJ)
326 system.physmem.preBackEnergy::1 1667361319500 # Energy for precharge background per rank (pJ)
327 system.physmem.totalEnergy::0 1944635822460 # Total energy per rank (pJ)
328 system.physmem.totalEnergy::1 1944428242110 # Total energy per rank (pJ)
329 system.physmem.averagePower::0 669.484503 # Core power per rank (mW)
330 system.physmem.averagePower::1 669.413038 # Core power per rank (mW)
331 system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
332 system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
333 system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
334 system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
335 system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
336 system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
337 system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
338 system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
339 system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
340 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
341 system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
342 system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
343 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
344 system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
345 system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
346 system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
347 system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
348 system.cf0.dma_write_txs 631 # Number of DMA write transactions.
349 system.cpu_clk_domain.clock 500 # Clock period in ticks
350 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
351 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
352 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
353 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
354 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
355 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
356 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
357 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
358 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
359 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
360 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
361 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
362 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
363 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
364 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
365 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
366 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
367 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
368 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
369 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
370 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
371 system.cpu0.dtb.inst_hits 0 # ITB inst hits
372 system.cpu0.dtb.inst_misses 0 # ITB inst misses
373 system.cpu0.dtb.read_hits 12289553 # DTB read hits
374 system.cpu0.dtb.read_misses 5977 # DTB read misses
375 system.cpu0.dtb.write_hits 9834643 # DTB write hits
376 system.cpu0.dtb.write_misses 1047 # DTB write misses
377 system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed
378 system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA
379 system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
380 system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
381 system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB
382 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
383 system.cpu0.dtb.prefetch_faults 865 # Number of TLB faults due to prefetch
384 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
385 system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions
386 system.cpu0.dtb.read_accesses 12295530 # DTB read accesses
387 system.cpu0.dtb.write_accesses 9835690 # DTB write accesses
388 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
389 system.cpu0.dtb.hits 22124196 # DTB hits
390 system.cpu0.dtb.misses 7024 # DTB misses
391 system.cpu0.dtb.accesses 22131220 # DTB accesses
392 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
393 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
394 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
395 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
396 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
397 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
398 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
399 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
400 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
401 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
402 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
403 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
404 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
405 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
406 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
407 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
408 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
409 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
410 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
411 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
412 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
413 system.cpu0.itb.inst_hits 58032770 # ITB inst hits
414 system.cpu0.itb.inst_misses 3465 # ITB inst misses
415 system.cpu0.itb.read_hits 0 # DTB read hits
416 system.cpu0.itb.read_misses 0 # DTB read misses
417 system.cpu0.itb.write_hits 0 # DTB write hits
418 system.cpu0.itb.write_misses 0 # DTB write misses
419 system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed
420 system.cpu0.itb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA
421 system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
422 system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
423 system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB
424 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
425 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
426 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
427 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
428 system.cpu0.itb.read_accesses 0 # DTB read accesses
429 system.cpu0.itb.write_accesses 0 # DTB write accesses
430 system.cpu0.itb.inst_accesses 58036235 # ITB inst accesses
431 system.cpu0.itb.hits 58032770 # DTB hits
432 system.cpu0.itb.misses 3465 # DTB misses
433 system.cpu0.itb.accesses 58036235 # DTB accesses
434 system.cpu0.numCycles 2905319694 # number of cpu cycles simulated
435 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
436 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
437 system.cpu0.committedInsts 56513131 # Number of instructions committed
438 system.cpu0.committedOps 68067849 # Number of ops (including micro ops) committed
439 system.cpu0.num_int_alu_accesses 60172046 # Number of integer alu accesses
440 system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses
441 system.cpu0.num_func_calls 4924583 # number of times a function call or return occured
442 system.cpu0.num_conditional_control_insts 7649378 # number of instructions that are conditional controls
443 system.cpu0.num_int_insts 60172046 # number of integer instructions
444 system.cpu0.num_fp_insts 6287 # number of float instructions
445 system.cpu0.num_int_register_reads 109432768 # number of times the integer registers were read
446 system.cpu0.num_int_register_writes 41532346 # number of times the integer registers were written
447 system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read
448 system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written
449 system.cpu0.num_cc_register_reads 245794871 # number of times the CC registers were read
450 system.cpu0.num_cc_register_writes 26123486 # number of times the CC registers were written
451 system.cpu0.num_mem_refs 22763364 # number of memory refs
452 system.cpu0.num_load_insts 12450622 # Number of load instructions
453 system.cpu0.num_store_insts 10312742 # Number of store instructions
454 system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles
455 system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles
456 system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles
457 system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles
458 system.cpu0.Branches 12983457 # Number of branches fetched
459 system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction
460 system.cpu0.op_class::IntAlu 46789630 67.21% 67.21% # Class of executed instruction
461 system.cpu0.op_class::IntMult 58620 0.08% 67.30% # Class of executed instruction
462 system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction
463 system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction
464 system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction
465 system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction
466 system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction
467 system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction
468 system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction
469 system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction
470 system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction
471 system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction
472 system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction
473 system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction
474 system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction
475 system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction
476 system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction
477 system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction
478 system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction
479 system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction
480 system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction
481 system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction
482 system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction
483 system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction
484 system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction
485 system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Class of executed instruction
486 system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction
487 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction
488 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction
489 system.cpu0.op_class::MemRead 12450622 17.88% 85.19% # Class of executed instruction
490 system.cpu0.op_class::MemWrite 10312742 14.81% 100.00% # Class of executed instruction
491 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
492 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
493 system.cpu0.op_class::total 69618091 # Class of executed instruction
494 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
495 system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed
496 system.cpu0.dcache.tags.replacements 822992 # number of replacements
497 system.cpu0.dcache.tags.tagsinuse 511.850755 # Cycle average of tags in use
498 system.cpu0.dcache.tags.total_refs 43241503 # Total number of references to valid blocks.
499 system.cpu0.dcache.tags.sampled_refs 823504 # Sample count of references to valid blocks.
500 system.cpu0.dcache.tags.avg_refs 52.509160 # Average number of references to valid blocks.
501 system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
502 system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068917 # Average occupied blocks per requestor
503 system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781838 # Average occupied blocks per requestor
504 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy
505 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy
506 system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy
507 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
508 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
509 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
510 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
511 system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
512 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
513 system.cpu0.dcache.tags.tag_accesses 177151535 # Number of tag accesses
514 system.cpu0.dcache.tags.data_accesses 177151535 # Number of data accesses
515 system.cpu0.dcache.ReadReq_hits::cpu0.data 11581583 # number of ReadReq hits
516 system.cpu0.dcache.ReadReq_hits::cpu1.data 11533865 # number of ReadReq hits
517 system.cpu0.dcache.ReadReq_hits::total 23115448 # number of ReadReq hits
518 system.cpu0.dcache.WriteReq_hits::cpu0.data 9437909 # number of WriteReq hits
519 system.cpu0.dcache.WriteReq_hits::cpu1.data 9389790 # number of WriteReq hits
520 system.cpu0.dcache.WriteReq_hits::total 18827699 # number of WriteReq hits
521 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199753 # number of SoftPFReq hits
522 system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192262 # number of SoftPFReq hits
523 system.cpu0.dcache.SoftPFReq_hits::total 392015 # number of SoftPFReq hits
524 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227025 # number of LoadLockedReq hits
525 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216269 # number of LoadLockedReq hits
526 system.cpu0.dcache.LoadLockedReq_hits::total 443294 # number of LoadLockedReq hits
527 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235239 # number of StoreCondReq hits
528 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225055 # number of StoreCondReq hits
529 system.cpu0.dcache.StoreCondReq_hits::total 460294 # number of StoreCondReq hits
530 system.cpu0.dcache.demand_hits::cpu0.data 21019492 # number of demand (read+write) hits
531 system.cpu0.dcache.demand_hits::cpu1.data 20923655 # number of demand (read+write) hits
532 system.cpu0.dcache.demand_hits::total 41943147 # number of demand (read+write) hits
533 system.cpu0.dcache.overall_hits::cpu0.data 21219245 # number of overall hits
534 system.cpu0.dcache.overall_hits::cpu1.data 21115917 # number of overall hits
535 system.cpu0.dcache.overall_hits::total 42335162 # number of overall hits
536 system.cpu0.dcache.ReadReq_misses::cpu0.data 197297 # number of ReadReq misses
537 system.cpu0.dcache.ReadReq_misses::cpu1.data 205526 # number of ReadReq misses
538 system.cpu0.dcache.ReadReq_misses::total 402823 # number of ReadReq misses
539 system.cpu0.dcache.WriteReq_misses::cpu0.data 150193 # number of WriteReq misses
540 system.cpu0.dcache.WriteReq_misses::cpu1.data 148466 # number of WriteReq misses
541 system.cpu0.dcache.WriteReq_misses::total 298659 # number of WriteReq misses
542 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58530 # number of SoftPFReq misses
543 system.cpu0.dcache.SoftPFReq_misses::cpu1.data 60464 # number of SoftPFReq misses
544 system.cpu0.dcache.SoftPFReq_misses::total 118994 # number of SoftPFReq misses
545 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11127 # number of LoadLockedReq misses
546 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11645 # number of LoadLockedReq misses
547 system.cpu0.dcache.LoadLockedReq_misses::total 22772 # number of LoadLockedReq misses
548 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
549 system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
550 system.cpu0.dcache.demand_misses::cpu0.data 347490 # number of demand (read+write) misses
551 system.cpu0.dcache.demand_misses::cpu1.data 353992 # number of demand (read+write) misses
552 system.cpu0.dcache.demand_misses::total 701482 # number of demand (read+write) misses
553 system.cpu0.dcache.overall_misses::cpu0.data 406020 # number of overall misses
554 system.cpu0.dcache.overall_misses::cpu1.data 414456 # number of overall misses
555 system.cpu0.dcache.overall_misses::total 820476 # number of overall misses
556 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2868020500 # number of ReadReq miss cycles
557 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066163250 # number of ReadReq miss cycles
558 system.cpu0.dcache.ReadReq_miss_latency::total 5934183750 # number of ReadReq miss cycles
559 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744459123 # number of WriteReq miss cycles
560 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031837843 # number of WriteReq miss cycles
561 system.cpu0.dcache.WriteReq_miss_latency::total 11776296966 # number of WriteReq miss cycles
562 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 135157750 # number of LoadLockedReq miss cycles
563 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 145057500 # number of LoadLockedReq miss cycles
564 system.cpu0.dcache.LoadLockedReq_miss_latency::total 280215250 # number of LoadLockedReq miss cycles
565 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52002 # number of StoreCondReq miss cycles
566 system.cpu0.dcache.StoreCondReq_miss_latency::total 52002 # number of StoreCondReq miss cycles
567 system.cpu0.dcache.demand_miss_latency::cpu0.data 8612479623 # number of demand (read+write) miss cycles
568 system.cpu0.dcache.demand_miss_latency::cpu1.data 9098001093 # number of demand (read+write) miss cycles
569 system.cpu0.dcache.demand_miss_latency::total 17710480716 # number of demand (read+write) miss cycles
570 system.cpu0.dcache.overall_miss_latency::cpu0.data 8612479623 # number of overall miss cycles
571 system.cpu0.dcache.overall_miss_latency::cpu1.data 9098001093 # number of overall miss cycles
572 system.cpu0.dcache.overall_miss_latency::total 17710480716 # number of overall miss cycles
573 system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778880 # number of ReadReq accesses(hits+misses)
574 system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739391 # number of ReadReq accesses(hits+misses)
575 system.cpu0.dcache.ReadReq_accesses::total 23518271 # number of ReadReq accesses(hits+misses)
576 system.cpu0.dcache.WriteReq_accesses::cpu0.data 9588102 # number of WriteReq accesses(hits+misses)
577 system.cpu0.dcache.WriteReq_accesses::cpu1.data 9538256 # number of WriteReq accesses(hits+misses)
578 system.cpu0.dcache.WriteReq_accesses::total 19126358 # number of WriteReq accesses(hits+misses)
579 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258283 # number of SoftPFReq accesses(hits+misses)
580 system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 252726 # number of SoftPFReq accesses(hits+misses)
581 system.cpu0.dcache.SoftPFReq_accesses::total 511009 # number of SoftPFReq accesses(hits+misses)
582 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238152 # number of LoadLockedReq accesses(hits+misses)
583 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227914 # number of LoadLockedReq accesses(hits+misses)
584 system.cpu0.dcache.LoadLockedReq_accesses::total 466066 # number of LoadLockedReq accesses(hits+misses)
585 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235241 # number of StoreCondReq accesses(hits+misses)
586 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 225055 # number of StoreCondReq accesses(hits+misses)
587 system.cpu0.dcache.StoreCondReq_accesses::total 460296 # number of StoreCondReq accesses(hits+misses)
588 system.cpu0.dcache.demand_accesses::cpu0.data 21366982 # number of demand (read+write) accesses
589 system.cpu0.dcache.demand_accesses::cpu1.data 21277647 # number of demand (read+write) accesses
590 system.cpu0.dcache.demand_accesses::total 42644629 # number of demand (read+write) accesses
591 system.cpu0.dcache.overall_accesses::cpu0.data 21625265 # number of overall (read+write) accesses
592 system.cpu0.dcache.overall_accesses::cpu1.data 21530373 # number of overall (read+write) accesses
593 system.cpu0.dcache.overall_accesses::total 43155638 # number of overall (read+write) accesses
594 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016750 # miss rate for ReadReq accesses
595 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017507 # miss rate for ReadReq accesses
596 system.cpu0.dcache.ReadReq_miss_rate::total 0.017128 # miss rate for ReadReq accesses
597 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015665 # miss rate for WriteReq accesses
598 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015565 # miss rate for WriteReq accesses
599 system.cpu0.dcache.WriteReq_miss_rate::total 0.015615 # miss rate for WriteReq accesses
600 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226612 # miss rate for SoftPFReq accesses
601 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.239247 # miss rate for SoftPFReq accesses
602 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232861 # miss rate for SoftPFReq accesses
603 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046722 # miss rate for LoadLockedReq accesses
604 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051094 # miss rate for LoadLockedReq accesses
605 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048860 # miss rate for LoadLockedReq accesses
606 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses
607 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
608 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016263 # miss rate for demand accesses
609 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016637 # miss rate for demand accesses
610 system.cpu0.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses
611 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018775 # miss rate for overall accesses
612 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019250 # miss rate for overall accesses
613 system.cpu0.dcache.overall_miss_rate::total 0.019012 # miss rate for overall accesses
614 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.564165 # average ReadReq miss latency
615 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14918.614920 # average ReadReq miss latency
616 system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.491871 # average ReadReq miss latency
617 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38247.182778 # average WriteReq miss latency
618 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.738627 # average WriteReq miss latency
619 system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.577903 # average WriteReq miss latency
620 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12146.827537 # average LoadLockedReq miss latency
621 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12456.633748 # average LoadLockedReq miss latency
622 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12305.254260 # average LoadLockedReq miss latency
623 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26001 # average StoreCondReq miss latency
624 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26001 # average StoreCondReq miss latency
625 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24784.827255 # average overall miss latency
626 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.148876 # average overall miss latency
627 system.cpu0.dcache.demand_avg_miss_latency::total 25247.234734 # average overall miss latency
628 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21211.959073 # average overall miss latency
629 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.669400 # average overall miss latency
630 system.cpu0.dcache.overall_avg_miss_latency::total 21585.617027 # average overall miss latency
631 system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked
632 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
633 system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
634 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
635 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked
636 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
637 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
638 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
639 system.cpu0.dcache.writebacks::writebacks 686960 # number of writebacks
640 system.cpu0.dcache.writebacks::total 686960 # number of writebacks
641 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits
642 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 328 # number of ReadReq MSHR hits
643 system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits
644 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7032 # number of LoadLockedReq MSHR hits
645 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7182 # number of LoadLockedReq MSHR hits
646 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14214 # number of LoadLockedReq MSHR hits
647 system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits
648 system.cpu0.dcache.demand_mshr_hits::cpu1.data 328 # number of demand (read+write) MSHR hits
649 system.cpu0.dcache.demand_mshr_hits::total 615 # number of demand (read+write) MSHR hits
650 system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits
651 system.cpu0.dcache.overall_mshr_hits::cpu1.data 328 # number of overall MSHR hits
652 system.cpu0.dcache.overall_mshr_hits::total 615 # number of overall MSHR hits
653 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 197010 # number of ReadReq MSHR misses
654 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205198 # number of ReadReq MSHR misses
655 system.cpu0.dcache.ReadReq_mshr_misses::total 402208 # number of ReadReq MSHR misses
656 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 150193 # number of WriteReq MSHR misses
657 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148466 # number of WriteReq MSHR misses
658 system.cpu0.dcache.WriteReq_mshr_misses::total 298659 # number of WriteReq MSHR misses
659 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57639 # number of SoftPFReq MSHR misses
660 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 59222 # number of SoftPFReq MSHR misses
661 system.cpu0.dcache.SoftPFReq_mshr_misses::total 116861 # number of SoftPFReq MSHR misses
662 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4095 # number of LoadLockedReq MSHR misses
663 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4463 # number of LoadLockedReq MSHR misses
664 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8558 # number of LoadLockedReq MSHR misses
665 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
666 system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
667 system.cpu0.dcache.demand_mshr_misses::cpu0.data 347203 # number of demand (read+write) MSHR misses
668 system.cpu0.dcache.demand_mshr_misses::cpu1.data 353664 # number of demand (read+write) MSHR misses
669 system.cpu0.dcache.demand_mshr_misses::total 700867 # number of demand (read+write) MSHR misses
670 system.cpu0.dcache.overall_mshr_misses::cpu0.data 404842 # number of overall MSHR misses
671 system.cpu0.dcache.overall_mshr_misses::cpu1.data 412886 # number of overall MSHR misses
672 system.cpu0.dcache.overall_mshr_misses::total 817728 # number of overall MSHR misses
673 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467868750 # number of ReadReq MSHR miss cycles
674 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647702500 # number of ReadReq MSHR miss cycles
675 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115571250 # number of ReadReq MSHR miss cycles
676 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416592829 # number of WriteReq MSHR miss cycles
677 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704580119 # number of WriteReq MSHR miss cycles
678 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121172948 # number of WriteReq MSHR miss cycles
679 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles
680 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles
681 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles
682 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48274750 # number of LoadLockedReq MSHR miss cycles
683 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 # number of LoadLockedReq MSHR miss cycles
684 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles
685 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles
686 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles
687 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884461579 # number of demand (read+write) MSHR miss cycles
688 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352282619 # number of demand (read+write) MSHR miss cycles
689 system.cpu0.dcache.demand_mshr_miss_latency::total 16236744198 # number of demand (read+write) MSHR miss cycles
690 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580499829 # number of overall MSHR miss cycles
691 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094526619 # number of overall MSHR miss cycles
692 system.cpu0.dcache.overall_mshr_miss_latency::total 17675026448 # number of overall MSHR miss cycles
693 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688395000 # number of ReadReq MSHR uncacheable cycles
694 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles
695 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422500 # number of ReadReq MSHR uncacheable cycles
696 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles
697 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles
698 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles
699 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853710000 # number of overall MSHR uncacheable cycles
700 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles
701 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221225000 # number of overall MSHR uncacheable cycles
702 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016726 # mshr miss rate for ReadReq accesses
703 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses
704 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses
705 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses
706 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses
707 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses
708 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223162 # mshr miss rate for SoftPFReq accesses
709 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234333 # mshr miss rate for SoftPFReq accesses
710 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228687 # mshr miss rate for SoftPFReq accesses
711 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses
712 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses
713 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses
714 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses
715 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
716 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses
717 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses
718 system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses
719 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses
720 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses
721 system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses
722 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.616669 # average ReadReq mshr miss latency
723 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.159388 # average ReadReq mshr miss latency
724 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12718.720786 # average ReadReq mshr miss latency
725 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36064.216235 # average WriteReq mshr miss latency
726 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.478231 # average WriteReq mshr miss latency
727 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37237.026000 # average WriteReq mshr miss latency
728 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency
729 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency
730 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency
731 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency
732 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency
733 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency
734 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency
735 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency
736 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.506490 # average overall mshr miss latency
737 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.434296 # average overall mshr miss latency
738 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.655297 # average overall mshr miss latency
739 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.687876 # average overall mshr miss latency
740 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22026.725583 # average overall mshr miss latency
741 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.799112 # average overall mshr miss latency
742 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
743 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
744 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
745 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
746 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
747 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
748 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
749 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
750 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
751 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
752 system.cpu0.icache.tags.replacements 1698167 # number of replacements
753 system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use
754 system.cpu0.icache.tags.total_refs 113885267 # Total number of references to valid blocks.
755 system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks.
756 system.cpu0.icache.tags.avg_refs 67.043430 # Average number of references to valid blocks.
757 system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit.
758 system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089773 # Average occupied blocks per requestor
759 system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685075 # Average occupied blocks per requestor
760 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy
761 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy
762 system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy
763 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
764 system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
765 system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
766 system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
767 system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
768 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
769 system.cpu0.icache.tags.tag_accesses 117282637 # Number of tag accesses
770 system.cpu0.icache.tags.data_accesses 117282637 # Number of data accesses
771 system.cpu0.icache.ReadReq_hits::cpu0.inst 57188138 # number of ReadReq hits
772 system.cpu0.icache.ReadReq_hits::cpu1.inst 56697129 # number of ReadReq hits
773 system.cpu0.icache.ReadReq_hits::total 113885267 # number of ReadReq hits
774 system.cpu0.icache.demand_hits::cpu0.inst 57188138 # number of demand (read+write) hits
775 system.cpu0.icache.demand_hits::cpu1.inst 56697129 # number of demand (read+write) hits
776 system.cpu0.icache.demand_hits::total 113885267 # number of demand (read+write) hits
777 system.cpu0.icache.overall_hits::cpu0.inst 57188138 # number of overall hits
778 system.cpu0.icache.overall_hits::cpu1.inst 56697129 # number of overall hits
779 system.cpu0.icache.overall_hits::total 113885267 # number of overall hits
780 system.cpu0.icache.ReadReq_misses::cpu0.inst 844632 # number of ReadReq misses
781 system.cpu0.icache.ReadReq_misses::cpu1.inst 854053 # number of ReadReq misses
782 system.cpu0.icache.ReadReq_misses::total 1698685 # number of ReadReq misses
783 system.cpu0.icache.demand_misses::cpu0.inst 844632 # number of demand (read+write) misses
784 system.cpu0.icache.demand_misses::cpu1.inst 854053 # number of demand (read+write) misses
785 system.cpu0.icache.demand_misses::total 1698685 # number of demand (read+write) misses
786 system.cpu0.icache.overall_misses::cpu0.inst 844632 # number of overall misses
787 system.cpu0.icache.overall_misses::cpu1.inst 854053 # number of overall misses
788 system.cpu0.icache.overall_misses::total 1698685 # number of overall misses
789 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11522232749 # number of ReadReq miss cycles
790 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11755811000 # number of ReadReq miss cycles
791 system.cpu0.icache.ReadReq_miss_latency::total 23278043749 # number of ReadReq miss cycles
792 system.cpu0.icache.demand_miss_latency::cpu0.inst 11522232749 # number of demand (read+write) miss cycles
793 system.cpu0.icache.demand_miss_latency::cpu1.inst 11755811000 # number of demand (read+write) miss cycles
794 system.cpu0.icache.demand_miss_latency::total 23278043749 # number of demand (read+write) miss cycles
795 system.cpu0.icache.overall_miss_latency::cpu0.inst 11522232749 # number of overall miss cycles
796 system.cpu0.icache.overall_miss_latency::cpu1.inst 11755811000 # number of overall miss cycles
797 system.cpu0.icache.overall_miss_latency::total 23278043749 # number of overall miss cycles
798 system.cpu0.icache.ReadReq_accesses::cpu0.inst 58032770 # number of ReadReq accesses(hits+misses)
799 system.cpu0.icache.ReadReq_accesses::cpu1.inst 57551182 # number of ReadReq accesses(hits+misses)
800 system.cpu0.icache.ReadReq_accesses::total 115583952 # number of ReadReq accesses(hits+misses)
801 system.cpu0.icache.demand_accesses::cpu0.inst 58032770 # number of demand (read+write) accesses
802 system.cpu0.icache.demand_accesses::cpu1.inst 57551182 # number of demand (read+write) accesses
803 system.cpu0.icache.demand_accesses::total 115583952 # number of demand (read+write) accesses
804 system.cpu0.icache.overall_accesses::cpu0.inst 58032770 # number of overall (read+write) accesses
805 system.cpu0.icache.overall_accesses::cpu1.inst 57551182 # number of overall (read+write) accesses
806 system.cpu0.icache.overall_accesses::total 115583952 # number of overall (read+write) accesses
807 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014554 # miss rate for ReadReq accesses
808 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014840 # miss rate for ReadReq accesses
809 system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses
810 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014554 # miss rate for demand accesses
811 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014840 # miss rate for demand accesses
812 system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses
813 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014554 # miss rate for overall accesses
814 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014840 # miss rate for overall accesses
815 system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses
816 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.719410 # average ReadReq miss latency
817 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.732400 # average ReadReq miss latency
818 system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.567023 # average ReadReq miss latency
819 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency
820 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency
821 system.cpu0.icache.demand_avg_miss_latency::total 13703.567023 # average overall miss latency
822 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency
823 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency
824 system.cpu0.icache.overall_avg_miss_latency::total 13703.567023 # average overall miss latency
825 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
826 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
827 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
828 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
829 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
830 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
831 system.cpu0.icache.fast_writes 0 # number of fast writes performed
832 system.cpu0.icache.cache_copies 0 # number of cache copies performed
833 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844632 # number of ReadReq MSHR misses
834 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854053 # number of ReadReq MSHR misses
835 system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses
836 system.cpu0.icache.demand_mshr_misses::cpu0.inst 844632 # number of demand (read+write) MSHR misses
837 system.cpu0.icache.demand_mshr_misses::cpu1.inst 854053 # number of demand (read+write) MSHR misses
838 system.cpu0.icache.demand_mshr_misses::total 1698685 # number of demand (read+write) MSHR misses
839 system.cpu0.icache.overall_mshr_misses::cpu0.inst 844632 # number of overall MSHR misses
840 system.cpu0.icache.overall_mshr_misses::cpu1.inst 854053 # number of overall MSHR misses
841 system.cpu0.icache.overall_mshr_misses::total 1698685 # number of overall MSHR misses
842 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9830027251 # number of ReadReq MSHR miss cycles
843 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10044094000 # number of ReadReq MSHR miss cycles
844 system.cpu0.icache.ReadReq_mshr_miss_latency::total 19874121251 # number of ReadReq MSHR miss cycles
845 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9830027251 # number of demand (read+write) MSHR miss cycles
846 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10044094000 # number of demand (read+write) MSHR miss cycles
847 system.cpu0.icache.demand_mshr_miss_latency::total 19874121251 # number of demand (read+write) MSHR miss cycles
848 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830027251 # number of overall MSHR miss cycles
849 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044094000 # number of overall MSHR miss cycles
850 system.cpu0.icache.overall_mshr_miss_latency::total 19874121251 # number of overall MSHR miss cycles
851 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles
852 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
853 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles
854 system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
855 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses
856 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses
857 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses
858 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for demand accesses
859 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for demand accesses
860 system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses
861 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for overall accesses
862 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for overall accesses
863 system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses
864 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average ReadReq mshr miss latency
865 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average ReadReq mshr miss latency
866 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.709629 # average ReadReq mshr miss latency
867 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency
868 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency
869 system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency
870 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency
871 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency
872 system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency
873 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
874 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
875 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
876 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
877 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
878 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
879 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
880 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
881 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
882 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
883 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
884 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
885 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
886 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
887 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
888 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
889 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
890 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
891 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
892 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
893 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
894 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
895 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
896 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
897 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
898 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
899 system.cpu1.dtb.inst_hits 0 # ITB inst hits
900 system.cpu1.dtb.inst_misses 0 # ITB inst misses
901 system.cpu1.dtb.read_hits 12236392 # DTB read hits
902 system.cpu1.dtb.read_misses 5657 # DTB read misses
903 system.cpu1.dtb.write_hits 9775692 # DTB write hits
904 system.cpu1.dtb.write_misses 790 # DTB write misses
905 system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed
906 system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
907 system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
908 system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
909 system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB
910 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
911 system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch
912 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
913 system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
914 system.cpu1.dtb.read_accesses 12242049 # DTB read accesses
915 system.cpu1.dtb.write_accesses 9776482 # DTB write accesses
916 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
917 system.cpu1.dtb.hits 22012084 # DTB hits
918 system.cpu1.dtb.misses 6447 # DTB misses
919 system.cpu1.dtb.accesses 22018531 # DTB accesses
920 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
921 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
922 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
923 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
924 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
925 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
926 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
927 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
928 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
929 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
930 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
931 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
932 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
933 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
934 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
935 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
936 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
937 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
938 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
939 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
940 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
941 system.cpu1.itb.inst_hits 57551182 # ITB inst hits
942 system.cpu1.itb.inst_misses 3277 # ITB inst misses
943 system.cpu1.itb.read_hits 0 # DTB read hits
944 system.cpu1.itb.read_misses 0 # DTB read misses
945 system.cpu1.itb.write_hits 0 # DTB write hits
946 system.cpu1.itb.write_misses 0 # DTB write misses
947 system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed
948 system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
949 system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
950 system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
951 system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
952 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
953 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
954 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
955 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
956 system.cpu1.itb.read_accesses 0 # DTB read accesses
957 system.cpu1.itb.write_accesses 0 # DTB write accesses
958 system.cpu1.itb.inst_accesses 57554459 # ITB inst accesses
959 system.cpu1.itb.hits 57551182 # DTB hits
960 system.cpu1.itb.misses 3277 # DTB misses
961 system.cpu1.itb.accesses 57554459 # DTB accesses
962 system.cpu1.numCycles 2904045401 # number of cpu cycles simulated
963 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
964 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
965 system.cpu1.committedInsts 55972284 # Number of instructions committed
966 system.cpu1.committedOps 67554362 # Number of ops (including micro ops) committed
967 system.cpu1.num_int_alu_accesses 59752131 # Number of integer alu accesses
968 system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses
969 system.cpu1.num_func_calls 4972365 # number of times a function call or return occured
970 system.cpu1.num_conditional_control_insts 7584533 # number of instructions that are conditional controls
971 system.cpu1.num_int_insts 59752131 # number of integer instructions
972 system.cpu1.num_fp_insts 5003 # number of float instructions
973 system.cpu1.num_int_register_reads 108688988 # number of times the integer registers were read
974 system.cpu1.num_int_register_writes 41135378 # number of times the integer registers were written
975 system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read
976 system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written
977 system.cpu1.num_cc_register_reads 244071190 # number of times the CC registers were read
978 system.cpu1.num_cc_register_writes 25783552 # number of times the CC registers were written
979 system.cpu1.num_mem_refs 22653716 # number of memory refs
980 system.cpu1.num_load_insts 12397911 # Number of load instructions
981 system.cpu1.num_store_insts 10255805 # Number of store instructions
982 system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles
983 system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles
984 system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles
985 system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles
986 system.cpu1.Branches 12941389 # Number of branches fetched
987 system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction
988 system.cpu1.op_class::IntAlu 46411475 67.14% 67.14% # Class of executed instruction
989 system.cpu1.op_class::IntMult 56055 0.08% 67.22% # Class of executed instruction
990 system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction
991 system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction
992 system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction
993 system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction
994 system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction
995 system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction
996 system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction
997 system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction
998 system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction
999 system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction
1000 system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction
1001 system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction
1002 system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction
1003 system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction
1004 system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction
1005 system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction
1006 system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction
1007 system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction
1008 system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction
1009 system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction
1010 system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction
1011 system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction
1012 system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction
1013 system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction
1014 system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction
1015 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction
1016 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction
1017 system.cpu1.op_class::MemRead 12397911 17.94% 85.16% # Class of executed instruction
1018 system.cpu1.op_class::MemWrite 10255805 14.84% 100.00% # Class of executed instruction
1019 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1020 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1021 system.cpu1.op_class::total 69125543 # Class of executed instruction
1022 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1023 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1024 system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
1025 system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
1026 system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
1027 system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
1028 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
1029 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1030 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1031 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1032 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1033 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1034 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1035 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1036 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1037 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1038 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
1039 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1040 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1041 system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1042 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1043 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1044 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1045 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1046 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1047 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1048 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1049 system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
1050 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
1051 system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
1052 system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
1053 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
1054 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1055 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1056 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1057 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1058 system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1059 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1060 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1061 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1062 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1063 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
1064 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1065 system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1066 system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1067 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1068 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1069 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1070 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
1071 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1072 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
1073 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1074 system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
1075 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
1076 system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
1077 system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
1078 system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
1079 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1080 system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
1081 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1082 system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
1083 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1084 system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
1085 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1086 system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
1087 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1088 system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
1089 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1090 system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
1091 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1092 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1093 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1094 system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1095 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1096 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1097 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1098 system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
1099 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1100 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1101 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1102 system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
1103 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1104 system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
1105 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1106 system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
1107 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1108 system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
1109 system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1110 system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
1111 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1112 system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
1113 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1114 system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
1115 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1116 system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
1117 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1118 system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
1119 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1120 system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1121 system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1122 system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
1123 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1124 system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks)
1125 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1126 system.iocache.tags.replacements 36424 # number of replacements
1127 system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use
1128 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1129 system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1130 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1131 system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit.
1132 system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor
1133 system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy
1134 system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy
1135 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1136 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1137 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1138 system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1139 system.iocache.tags.data_accesses 328122 # Number of data accesses
1140 system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
1141 system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
1142 system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1143 system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1144 system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
1145 system.iocache.demand_misses::total 234 # number of demand (read+write) misses
1146 system.iocache.overall_misses::realview.ide 234 # number of overall misses
1147 system.iocache.overall_misses::total 234 # number of overall misses
1148 system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles
1149 system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles
1150 system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles
1151 system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles
1152 system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles
1153 system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles
1154 system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
1155 system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
1156 system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
1157 system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
1158 system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
1159 system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
1160 system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
1161 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
1162 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1163 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1164 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1165 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1166 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1167 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1168 system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency
1169 system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency
1170 system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
1171 system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency
1172 system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
1173 system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency
1174 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1175 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1176 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1177 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1178 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1179 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1180 system.iocache.fast_writes 36224 # number of fast writes performed
1181 system.iocache.cache_copies 0 # number of cache copies performed
1182 system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
1183 system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
1184 system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
1185 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
1186 system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
1187 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
1188 system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles
1189 system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles
1190 system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles
1191 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles
1192 system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles
1193 system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles
1194 system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles
1195 system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles
1196 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1197 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1198 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1199 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1200 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1201 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1202 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency
1203 system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency
1204 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
1205 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1206 system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
1207 system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
1208 system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
1209 system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
1210 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1211 system.l2c.tags.replacements 89435 # number of replacements
1212 system.l2c.tags.tagsinuse 64928.071220 # Cycle average of tags in use
1213 system.l2c.tags.total_refs 2766032 # Total number of references to valid blocks.
1214 system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks.
1215 system.l2c.tags.avg_refs 17.882748 # Average number of references to valid blocks.
1216 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1217 system.l2c.tags.occ_blocks::writebacks 50556.019197 # Average occupied blocks per requestor
1218 system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor
1219 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor
1220 system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor
1221 system.l2c.tags.occ_blocks::cpu0.data 2064.899938 # Average occupied blocks per requestor
1222 system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor
1223 system.l2c.tags.occ_blocks::cpu1.inst 5760.330465 # Average occupied blocks per requestor
1224 system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor
1225 system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy
1226 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy
1227 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
1228 system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy
1229 system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy
1230 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy
1231 system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy
1232 system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy
1233 system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy
1234 system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
1235 system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id
1236 system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
1237 system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
1238 system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
1239 system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id
1240 system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id
1241 system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id
1242 system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
1243 system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id
1244 system.l2c.tags.tag_accesses 26292076 # Number of tag accesses
1245 system.l2c.tags.data_accesses 26292076 # Number of data accesses
1246 system.l2c.ReadReq_hits::cpu0.dtb.walker 6208 # number of ReadReq hits
1247 system.l2c.ReadReq_hits::cpu0.itb.walker 3383 # number of ReadReq hits
1248 system.l2c.ReadReq_hits::cpu0.inst 836467 # number of ReadReq hits
1249 system.l2c.ReadReq_hits::cpu0.data 253621 # number of ReadReq hits
1250 system.l2c.ReadReq_hits::cpu1.dtb.walker 5323 # number of ReadReq hits
1251 system.l2c.ReadReq_hits::cpu1.itb.walker 2799 # number of ReadReq hits
1252 system.l2c.ReadReq_hits::cpu1.inst 844177 # number of ReadReq hits
1253 system.l2c.ReadReq_hits::cpu1.data 261864 # number of ReadReq hits
1254 system.l2c.ReadReq_hits::total 2213842 # number of ReadReq hits
1255 system.l2c.Writeback_hits::writebacks 686960 # number of Writeback hits
1256 system.l2c.Writeback_hits::total 686960 # number of Writeback hits
1257 system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits
1258 system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits
1259 system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits
1260 system.l2c.ReadExReq_hits::cpu0.data 86549 # number of ReadExReq hits
1261 system.l2c.ReadExReq_hits::cpu1.data 78519 # number of ReadExReq hits
1262 system.l2c.ReadExReq_hits::total 165068 # number of ReadExReq hits
1263 system.l2c.demand_hits::cpu0.dtb.walker 6208 # number of demand (read+write) hits
1264 system.l2c.demand_hits::cpu0.itb.walker 3383 # number of demand (read+write) hits
1265 system.l2c.demand_hits::cpu0.inst 836467 # number of demand (read+write) hits
1266 system.l2c.demand_hits::cpu0.data 340170 # number of demand (read+write) hits
1267 system.l2c.demand_hits::cpu1.dtb.walker 5323 # number of demand (read+write) hits
1268 system.l2c.demand_hits::cpu1.itb.walker 2799 # number of demand (read+write) hits
1269 system.l2c.demand_hits::cpu1.inst 844177 # number of demand (read+write) hits
1270 system.l2c.demand_hits::cpu1.data 340383 # number of demand (read+write) hits
1271 system.l2c.demand_hits::total 2378910 # number of demand (read+write) hits
1272 system.l2c.overall_hits::cpu0.dtb.walker 6208 # number of overall hits
1273 system.l2c.overall_hits::cpu0.itb.walker 3383 # number of overall hits
1274 system.l2c.overall_hits::cpu0.inst 836467 # number of overall hits
1275 system.l2c.overall_hits::cpu0.data 340170 # number of overall hits
1276 system.l2c.overall_hits::cpu1.dtb.walker 5323 # number of overall hits
1277 system.l2c.overall_hits::cpu1.itb.walker 2799 # number of overall hits
1278 system.l2c.overall_hits::cpu1.inst 844177 # number of overall hits
1279 system.l2c.overall_hits::cpu1.data 340383 # number of overall hits
1280 system.l2c.overall_hits::total 2378910 # number of overall hits
1281 system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
1282 system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
1283 system.l2c.ReadReq_misses::cpu0.inst 8151 # number of ReadReq misses
1284 system.l2c.ReadReq_misses::cpu0.data 5123 # number of ReadReq misses
1285 system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses
1286 system.l2c.ReadReq_misses::cpu1.inst 9868 # number of ReadReq misses
1287 system.l2c.ReadReq_misses::cpu1.data 7019 # number of ReadReq misses
1288 system.l2c.ReadReq_misses::total 30170 # number of ReadReq misses
1289 system.l2c.UpgradeReq_misses::cpu0.data 1297 # number of UpgradeReq misses
1290 system.l2c.UpgradeReq_misses::cpu1.data 1431 # number of UpgradeReq misses
1291 system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
1292 system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
1293 system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
1294 system.l2c.ReadExReq_misses::cpu0.data 62336 # number of ReadExReq misses
1295 system.l2c.ReadExReq_misses::cpu1.data 68504 # number of ReadExReq misses
1296 system.l2c.ReadExReq_misses::total 130840 # number of ReadExReq misses
1297 system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
1298 system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
1299 system.l2c.demand_misses::cpu0.inst 8151 # number of demand (read+write) misses
1300 system.l2c.demand_misses::cpu0.data 67459 # number of demand (read+write) misses
1301 system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses
1302 system.l2c.demand_misses::cpu1.inst 9868 # number of demand (read+write) misses
1303 system.l2c.demand_misses::cpu1.data 75523 # number of demand (read+write) misses
1304 system.l2c.demand_misses::total 161010 # number of demand (read+write) misses
1305 system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
1306 system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
1307 system.l2c.overall_misses::cpu0.inst 8151 # number of overall misses
1308 system.l2c.overall_misses::cpu0.data 67459 # number of overall misses
1309 system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses
1310 system.l2c.overall_misses::cpu1.inst 9868 # number of overall misses
1311 system.l2c.overall_misses::cpu1.data 75523 # number of overall misses
1312 system.l2c.overall_misses::total 161010 # number of overall misses
1313 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 74500 # number of ReadReq miss cycles
1314 system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles
1315 system.l2c.ReadReq_miss_latency::cpu0.inst 591607750 # number of ReadReq miss cycles
1316 system.l2c.ReadReq_miss_latency::cpu0.data 390910500 # number of ReadReq miss cycles
1317 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 566500 # number of ReadReq miss cycles
1318 system.l2c.ReadReq_miss_latency::cpu1.inst 717676500 # number of ReadReq miss cycles
1319 system.l2c.ReadReq_miss_latency::cpu1.data 528864500 # number of ReadReq miss cycles
1320 system.l2c.ReadReq_miss_latency::total 2229775250 # number of ReadReq miss cycles
1321 system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles
1322 system.l2c.UpgradeReq_miss_latency::cpu1.data 231490 # number of UpgradeReq miss cycles
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1548 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for demand accesses
1549 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for demand accesses
1550 system.l2c.demand_mshr_miss_rate::cpu0.data 0.165491 # mshr miss rate for demand accesses
1551 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for demand accesses
1552 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for demand accesses
1553 system.l2c.demand_mshr_miss_rate::cpu1.data 0.181587 # mshr miss rate for demand accesses
1554 system.l2c.demand_mshr_miss_rate::total 0.063392 # mshr miss rate for demand accesses
1555 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for overall accesses
1556 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for overall accesses
1557 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for overall accesses
1558 system.l2c.overall_mshr_miss_rate::cpu0.data 0.165491 # mshr miss rate for overall accesses
1559 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for overall accesses
1560 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for overall accesses
1561 system.l2c.overall_mshr_miss_rate::cpu1.data 0.181587 # mshr miss rate for overall accesses
1562 system.l2c.overall_mshr_miss_rate::total 0.063392 # mshr miss rate for overall accesses
1563 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency
1564 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
1565 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average ReadReq mshr miss latency
1566 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63830.860824 # average ReadReq mshr miss latency
1567 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency
1568 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average ReadReq mshr miss latency
1569 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62861.376264 # average ReadReq mshr miss latency
1570 system.l2c.ReadReq_avg_mshr_miss_latency::total 61330.336427 # average ReadReq mshr miss latency
1571 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535 # average UpgradeReq mshr miss latency
1572 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 # average UpgradeReq mshr miss latency
1573 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency
1574 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
1575 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
1576 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56856.845964 # average ReadExReq mshr miss latency
1577 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55979.022115 # average ReadExReq mshr miss latency
1578 system.l2c.ReadExReq_avg_mshr_miss_latency::total 56397.243053 # average ReadExReq mshr miss latency
1579 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
1580 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
1581 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency
1582 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency
1583 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
1584 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency
1585 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency
1586 system.l2c.demand_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency
1587 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
1588 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
1589 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency
1590 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency
1591 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
1592 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency
1593 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency
1594 system.l2c.overall_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency
1595 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1596 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1597 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1598 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1599 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1600 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1601 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1602 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1603 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1604 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1605 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1606 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1607 system.membus.trans_dist::ReadReq 70576 # Transaction distribution
1608 system.membus.trans_dist::ReadResp 70576 # Transaction distribution
1609 system.membus.trans_dist::WriteReq 27613 # Transaction distribution
1610 system.membus.trans_dist::WriteResp 27613 # Transaction distribution
1611 system.membus.trans_dist::Writeback 82818 # Transaction distribution
1612 system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
1613 system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1614 system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution
1615 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1616 system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution
1617 system.membus.trans_dist::ReadExReq 129059 # Transaction distribution
1618 system.membus.trans_dist::ReadExResp 129059 # Transaction distribution
1619 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
1620 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
1621 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
1622 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438204 # Packet count per connected master and slave (bytes)
1623 system.membus.pkt_count_system.l2c.mem_side::total 545868 # Packet count per connected master and slave (bytes)
1624 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
1625 system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
1626 system.membus.pkt_count::total 618565 # Packet count per connected master and slave (bytes)
1627 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
1628 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
1629 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
1630 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes)
1631 system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes)
1632 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
1633 system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
1634 system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes)
1635 system.membus.snoops 219 # Total snoops (count)
1636 system.membus.snoop_fanout::samples 283019 # Request fanout histogram
1637 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1638 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1639 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1640 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1641 system.membus.snoop_fanout::1 283019 100.00% 100.00% # Request fanout histogram
1642 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1643 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1644 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1645 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1646 system.membus.snoop_fanout::total 283019 # Request fanout histogram
1647 system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks)
1648 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1649 system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
1650 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1651 system.membus.reqLayer2.occupancy 1736000 # Layer occupancy (ticks)
1652 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1653 system.membus.reqLayer5.occupancy 1336695000 # Layer occupancy (ticks)
1654 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1655 system.membus.respLayer2.occupancy 1640329489 # Layer occupancy (ticks)
1656 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
1657 system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks)
1658 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1659 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1660 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1661 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1662 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1663 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1664 system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1665 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1666 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1667 system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1668 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1669 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1670 system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1671 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1672 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1673 system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1674 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1675 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1676 system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1677 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1678 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1679 system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1680 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1681 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1682 system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1683 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1684 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1685 system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1686 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1687 system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1688 system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1689 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1690 system.toL2Bus.trans_dist::ReadReq 2301469 # Transaction distribution
1691 system.toL2Bus.trans_dist::ReadResp 2301454 # Transaction distribution
1692 system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution
1693 system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution
1694 system.toL2Bus.trans_dist::Writeback 686960 # Transaction distribution
1695 system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution
1696 system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution
1697 system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1698 system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution
1699 system.toL2Bus.trans_dist::ReadExReq 295908 # Transaction distribution
1700 system.toL2Bus.trans_dist::ReadExResp 295908 # Transaction distribution
1701 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes)
1702 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457281 # Packet count per connected master and slave (bytes)
1703 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes)
1704 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34351 # Packet count per connected master and slave (bytes)
1705 system.toL2Bus.pkt_count::total 5925146 # Packet count per connected master and slave (bytes)
1706 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes)
1707 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868901 # Cumulative packet size per connected master and slave (bytes)
1708 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes)
1709 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46156 # Cumulative packet size per connected master and slave (bytes)
1710 system.toL2Bus.pkt_size::total 205690309 # Cumulative packet size per connected master and slave (bytes)
1711 system.toL2Bus.snoops 53730 # Total snoops (count)
1712 system.toL2Bus.snoop_fanout::samples 3283144 # Request fanout histogram
1713 system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram
1714 system.toL2Bus.snoop_fanout::stdev 0.104794 # Request fanout histogram
1715 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1716 system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1717 system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1718 system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1719 system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1720 system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1721 system.toL2Bus.snoop_fanout::5 3246684 98.89% 98.89% # Request fanout histogram
1722 system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram
1723 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1724 system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1725 system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1726 system.toL2Bus.snoop_fanout::total 3283144 # Request fanout histogram
1727 system.toL2Bus.reqLayer0.occupancy 4418882248 # Layer occupancy (ticks)
1728 system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1729 system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks)
1730 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1731 system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks)
1732 system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
1733 system.toL2Bus.respLayer1.occupancy 3782924511 # Layer occupancy (ticks)
1734 system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1735 system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks)
1736 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1737 system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks)
1738 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1740 ---------- End Simulation Statistics ----------
projects / gem5.git / blob