2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.609477 # Number of seconds simulated
4 sim_ticks 2609476867000 # Number of ticks simulated
5 final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 397155 # Simulator instruction rate (inst/s)
8 host_op_rate 505377 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 17213891867 # Simulator tick rate (ticks/s)
10 host_mem_usage 448796 # Number of bytes of host memory used
11 host_seconds 151.59 # Real time elapsed on the host
12 sim_insts 60205243 # Number of instructions simulated
13 sim_ops 76610733 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.inst 349152 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.data 4456460 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.inst 356032 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.data 4588440 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 132433668 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu0.inst 349152 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::cpu1.inst 356032 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory
25 system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory
26 system.physmem.bytes_written::cpu0.data 1522768 # Number of bytes written to this memory
27 system.physmem.bytes_written::cpu1.data 1493500 # Number of bytes written to this memory
28 system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory
29 system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu0.inst 11658 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu0.data 69665 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu1.inst 5563 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu1.data 71715 # Number of read requests responded to by this memory
36 system.physmem.num_reads::total 15494028 # Number of read requests responded to by this memory
37 system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory
38 system.physmem.num_writes::cpu0.data 380692 # Number of write requests responded to by this memory
39 system.physmem.num_writes::cpu1.data 373375 # Number of write requests responded to by this memory
40 system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory
41 system.physmem.bw_read::realview.clcd 47014554 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu0.inst 133802 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu0.data 1707798 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu1.inst 136438 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::cpu1.data 1758375 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::total 50751041 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_inst_read::cpu0.inst 133802 # Instruction read bandwidth from this memory (bytes/s)
50 system.physmem.bw_inst_read::cpu1.inst 136438 # Instruction read bandwidth from this memory (bytes/s)
51 system.physmem.bw_inst_read::total 270240 # Instruction read bandwidth from this memory (bytes/s)
52 system.physmem.bw_write::writebacks 1407424 # Write bandwidth from this memory (bytes/s)
53 system.physmem.bw_write::cpu0.data 583553 # Write bandwidth from this memory (bytes/s)
54 system.physmem.bw_write::cpu1.data 572337 # Write bandwidth from this memory (bytes/s)
55 system.physmem.bw_write::total 2563314 # Write bandwidth from this memory (bytes/s)
56 system.physmem.bw_total::writebacks 1407424 # Total bandwidth to/from this memory (bytes/s)
57 system.physmem.bw_total::realview.clcd 47014554 # Total bandwidth to/from this memory (bytes/s)
58 system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::cpu0.inst 133802 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::cpu0.data 2291351 # Total bandwidth to/from this memory (bytes/s)
62 system.physmem.bw_total::cpu1.inst 136438 # Total bandwidth to/from this memory (bytes/s)
63 system.physmem.bw_total::cpu1.data 2330712 # Total bandwidth to/from this memory (bytes/s)
64 system.physmem.bw_total::total 53314355 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.readReqs 15494028 # Total number of read requests seen
66 system.physmem.writeReqs 811452 # Total number of write requests seen
67 system.physmem.cpureqs 213833 # Reqs generatd by CPU via cache - shady
68 system.physmem.bytesRead 991617792 # Total number of bytes read from memory
69 system.physmem.bytesWritten 51932928 # Total number of bytes written to memory
70 system.physmem.bytesConsumedRd 132433668 # bytesRead derated as per pkt->getSize()
71 system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize()
72 system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
73 system.physmem.neitherReadNorWrite 4517 # Reqs where no action is needed
74 system.physmem.perBankRdReqs::0 968202 # Track reads on a per bank basis
75 system.physmem.perBankRdReqs::1 968429 # Track reads on a per bank basis
76 system.physmem.perBankRdReqs::2 967970 # Track reads on a per bank basis
77 system.physmem.perBankRdReqs::3 967933 # Track reads on a per bank basis
78 system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis
79 system.physmem.perBankRdReqs::5 967536 # Track reads on a per bank basis
80 system.physmem.perBankRdReqs::6 967538 # Track reads on a per bank basis
81 system.physmem.perBankRdReqs::7 967708 # Track reads on a per bank basis
82 system.physmem.perBankRdReqs::8 974536 # Track reads on a per bank basis
83 system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis
84 system.physmem.perBankRdReqs::10 968050 # Track reads on a per bank basis
85 system.physmem.perBankRdReqs::11 968032 # Track reads on a per bank basis
86 system.physmem.perBankRdReqs::12 968173 # Track reads on a per bank basis
87 system.physmem.perBankRdReqs::13 968196 # Track reads on a per bank basis
88 system.physmem.perBankRdReqs::14 968244 # Track reads on a per bank basis
89 system.physmem.perBankRdReqs::15 967963 # Track reads on a per bank basis
90 system.physmem.perBankWrReqs::0 50183 # Track writes on a per bank basis
91 system.physmem.perBankWrReqs::1 50348 # Track writes on a per bank basis
92 system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
93 system.physmem.perBankWrReqs::3 49920 # Track writes on a per bank basis
94 system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis
95 system.physmem.perBankWrReqs::5 50585 # Track writes on a per bank basis
96 system.physmem.perBankWrReqs::6 50546 # Track writes on a per bank basis
97 system.physmem.perBankWrReqs::7 50745 # Track writes on a per bank basis
98 system.physmem.perBankWrReqs::8 50919 # Track writes on a per bank basis
99 system.physmem.perBankWrReqs::9 50958 # Track writes on a per bank basis
100 system.physmem.perBankWrReqs::10 50981 # Track writes on a per bank basis
101 system.physmem.perBankWrReqs::11 51015 # Track writes on a per bank basis
102 system.physmem.perBankWrReqs::12 51209 # Track writes on a per bank basis
103 system.physmem.perBankWrReqs::13 51186 # Track writes on a per bank basis
104 system.physmem.perBankWrReqs::14 51259 # Track writes on a per bank basis
105 system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis
106 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
107 system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
108 system.physmem.totGap 2609472479500 # Total gap between requests
109 system.physmem.readPktSize::0 0 # Categorize read packet sizes
110 system.physmem.readPktSize::1 0 # Categorize read packet sizes
111 system.physmem.readPktSize::2 6673 # Categorize read packet sizes
112 system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
113 system.physmem.readPktSize::4 0 # Categorize read packet sizes
114 system.physmem.readPktSize::5 0 # Categorize read packet sizes
115 system.physmem.readPktSize::6 151931 # Categorize read packet sizes
116 system.physmem.readPktSize::7 0 # Categorize read packet sizes
117 system.physmem.readPktSize::8 0 # Categorize read packet sizes
118 system.physmem.writePktSize::0 0 # categorize write packet sizes
119 system.physmem.writePktSize::1 0 # categorize write packet sizes
120 system.physmem.writePktSize::2 754067 # categorize write packet sizes
121 system.physmem.writePktSize::3 0 # categorize write packet sizes
122 system.physmem.writePktSize::4 0 # categorize write packet sizes
123 system.physmem.writePktSize::5 0 # categorize write packet sizes
124 system.physmem.writePktSize::6 57385 # categorize write packet sizes
125 system.physmem.writePktSize::7 0 # categorize write packet sizes
126 system.physmem.writePktSize::8 0 # categorize write packet sizes
127 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
128 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
129 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
130 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
131 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
132 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
133 system.physmem.neitherpktsize::6 4517 # categorize neither packet sizes
134 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
135 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
136 system.physmem.rdQLenPdf::0 1117981 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::1 962159 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::2 962420 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::3 998543 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::4 2811240 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::5 2816443 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::6 5545406 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::7 36112 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::8 30744 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::9 30521 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::10 30516 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::11 58787 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::12 30559 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::13 58397 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::14 2158 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::15 1941 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
169 system.physmem.wrQLenPdf::0 35453 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::1 35426 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::2 35407 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::3 35396 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::4 35377 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::5 35365 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::6 35352 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::7 35336 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::8 35316 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::10 35296 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::12 35269 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::14 35242 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::15 35230 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::16 35218 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::17 35202 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::18 35180 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::20 35144 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::21 35125 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::22 35114 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
202 system.physmem.totQLat 286738639625 # Total cycles spent in queuing delays
203 system.physmem.totMemAccLat 365542479625 # Sum of mem lat for all requests
204 system.physmem.totBusLat 61976008000 # Total cycles spent in databus access
205 system.physmem.totBankLat 16827832000 # Total cycles spent in bank access
206 system.physmem.avgQLat 18506.43 # Average queueing delay per request
207 system.physmem.avgBankLat 1086.09 # Average bank access latency per request
208 system.physmem.avgBusLat 4000.00 # Average bus latency per request
209 system.physmem.avgMemAccLat 23592.52 # Average memory access latency
210 system.physmem.avgRdBW 380.01 # Average achieved read bandwidth in MB/s
211 system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s
212 system.physmem.avgConsumedRdBW 50.75 # Average consumed read bandwidth in MB/s
213 system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s
214 system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
215 system.physmem.busUtil 2.50 # Data bus utilization in percentage
216 system.physmem.avgRdQLen 0.14 # Average read queue length over time
217 system.physmem.avgWrQLen 1.25 # Average write queue length over time
218 system.physmem.readRowHits 15452119 # Number of row buffer hits during reads
219 system.physmem.writeRowHits 785190 # Number of row buffer hits during writes
220 system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
221 system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes
222 system.physmem.avgGap 160036.53 # Average gap between requests
223 system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
224 system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
225 system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
226 system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
227 system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
228 system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
229 system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
230 system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
231 system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
232 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
233 system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
234 system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
235 system.l2c.replacements 61820 # number of replacements
236 system.l2c.tagsinuse 50921.903557 # Cycle average of tags in use
237 system.l2c.total_refs 1697937 # Total number of references to valid blocks.
238 system.l2c.sampled_refs 127204 # Sample count of references to valid blocks.
239 system.l2c.avg_refs 13.348142 # Average number of references to valid blocks.
240 system.l2c.warmup_cycle 2557805301500 # Cycle when the warmup percentage was hit.
241 system.l2c.occ_blocks::writebacks 37911.972595 # Average occupied blocks per requestor
242 system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor
243 system.l2c.occ_blocks::cpu0.itb.walker 0.000639 # Average occupied blocks per requestor
244 system.l2c.occ_blocks::cpu0.inst 3578.783807 # Average occupied blocks per requestor
245 system.l2c.occ_blocks::cpu0.data 2862.372936 # Average occupied blocks per requestor
246 system.l2c.occ_blocks::cpu1.inst 3416.906879 # Average occupied blocks per requestor
247 system.l2c.occ_blocks::cpu1.data 3151.866517 # Average occupied blocks per requestor
248 system.l2c.occ_percent::writebacks 0.578491 # Average percentage of cache occupancy
249 system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
250 system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
251 system.l2c.occ_percent::cpu0.inst 0.054608 # Average percentage of cache occupancy
252 system.l2c.occ_percent::cpu0.data 0.043676 # Average percentage of cache occupancy
253 system.l2c.occ_percent::cpu1.inst 0.052138 # Average percentage of cache occupancy
254 system.l2c.occ_percent::cpu1.data 0.048094 # Average percentage of cache occupancy
255 system.l2c.occ_percent::total 0.777007 # Average percentage of cache occupancy
256 system.l2c.ReadReq_hits::cpu0.dtb.walker 9713 # number of ReadReq hits
257 system.l2c.ReadReq_hits::cpu0.itb.walker 3454 # number of ReadReq hits
258 system.l2c.ReadReq_hits::cpu0.inst 390514 # number of ReadReq hits
259 system.l2c.ReadReq_hits::cpu0.data 186540 # number of ReadReq hits
260 system.l2c.ReadReq_hits::cpu1.dtb.walker 9847 # number of ReadReq hits
261 system.l2c.ReadReq_hits::cpu1.itb.walker 3624 # number of ReadReq hits
262 system.l2c.ReadReq_hits::cpu1.inst 453502 # number of ReadReq hits
263 system.l2c.ReadReq_hits::cpu1.data 184024 # number of ReadReq hits
264 system.l2c.ReadReq_hits::total 1241218 # number of ReadReq hits
265 system.l2c.Writeback_hits::writebacks 596393 # number of Writeback hits
266 system.l2c.Writeback_hits::total 596393 # number of Writeback hits
267 system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
268 system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits
269 system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
270 system.l2c.ReadExReq_hits::cpu0.data 55901 # number of ReadExReq hits
271 system.l2c.ReadExReq_hits::cpu1.data 58662 # number of ReadExReq hits
272 system.l2c.ReadExReq_hits::total 114563 # number of ReadExReq hits
273 system.l2c.demand_hits::cpu0.dtb.walker 9713 # number of demand (read+write) hits
274 system.l2c.demand_hits::cpu0.itb.walker 3454 # number of demand (read+write) hits
275 system.l2c.demand_hits::cpu0.inst 390514 # number of demand (read+write) hits
276 system.l2c.demand_hits::cpu0.data 242441 # number of demand (read+write) hits
277 system.l2c.demand_hits::cpu1.dtb.walker 9847 # number of demand (read+write) hits
278 system.l2c.demand_hits::cpu1.itb.walker 3624 # number of demand (read+write) hits
279 system.l2c.demand_hits::cpu1.inst 453502 # number of demand (read+write) hits
280 system.l2c.demand_hits::cpu1.data 242686 # number of demand (read+write) hits
281 system.l2c.demand_hits::total 1355781 # number of demand (read+write) hits
282 system.l2c.overall_hits::cpu0.dtb.walker 9713 # number of overall hits
283 system.l2c.overall_hits::cpu0.itb.walker 3454 # number of overall hits
284 system.l2c.overall_hits::cpu0.inst 390514 # number of overall hits
285 system.l2c.overall_hits::cpu0.data 242441 # number of overall hits
286 system.l2c.overall_hits::cpu1.dtb.walker 9847 # number of overall hits
287 system.l2c.overall_hits::cpu1.itb.walker 3624 # number of overall hits
288 system.l2c.overall_hits::cpu1.inst 453502 # number of overall hits
289 system.l2c.overall_hits::cpu1.data 242686 # number of overall hits
290 system.l2c.overall_hits::total 1355781 # number of overall hits
291 system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
292 system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
293 system.l2c.ReadReq_misses::cpu0.inst 5042 # number of ReadReq misses
294 system.l2c.ReadReq_misses::cpu0.data 5096 # number of ReadReq misses
295 system.l2c.ReadReq_misses::cpu1.inst 5563 # number of ReadReq misses
296 system.l2c.ReadReq_misses::cpu1.data 4755 # number of ReadReq misses
297 system.l2c.ReadReq_misses::total 20459 # number of ReadReq misses
298 system.l2c.UpgradeReq_misses::cpu0.data 1441 # number of UpgradeReq misses
299 system.l2c.UpgradeReq_misses::cpu1.data 1437 # number of UpgradeReq misses
300 system.l2c.UpgradeReq_misses::total 2878 # number of UpgradeReq misses
301 system.l2c.ReadExReq_misses::cpu0.data 65351 # number of ReadExReq misses
302 system.l2c.ReadExReq_misses::cpu1.data 67760 # number of ReadExReq misses
303 system.l2c.ReadExReq_misses::total 133111 # number of ReadExReq misses
304 system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
305 system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
306 system.l2c.demand_misses::cpu0.inst 5042 # number of demand (read+write) misses
307 system.l2c.demand_misses::cpu0.data 70447 # number of demand (read+write) misses
308 system.l2c.demand_misses::cpu1.inst 5563 # number of demand (read+write) misses
309 system.l2c.demand_misses::cpu1.data 72515 # number of demand (read+write) misses
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544 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average ReadReq mshr miss latency
545 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40326.698212 # average ReadReq mshr miss latency
546 system.l2c.ReadReq_avg_mshr_miss_latency::total 37865.104844 # average ReadReq mshr miss latency
547 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10039.147814 # average UpgradeReq mshr miss latency
548 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
549 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10020.100417 # average UpgradeReq mshr miss latency
550 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32093.452832 # average ReadExReq mshr miss latency
551 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33289.629413 # average ReadExReq mshr miss latency
552 system.l2c.ReadExReq_avg_mshr_miss_latency::total 32702.365131 # average ReadExReq mshr miss latency
553 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
554 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
555 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36625.253868 # average overall mshr miss latency
556 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32501.786804 # average overall mshr miss latency
557 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average overall mshr miss latency
558 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33751.068593 # average overall mshr miss latency
559 system.l2c.demand_avg_mshr_miss_latency::total 33390.158918 # average overall mshr miss latency
560 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
561 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
562 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36625.253868 # average overall mshr miss latency
563 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32501.786804 # average overall mshr miss latency
564 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average overall mshr miss latency
565 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33751.068593 # average overall mshr miss latency
566 system.l2c.overall_avg_mshr_miss_latency::total 33390.158918 # average overall mshr miss latency
567 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
568 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
569 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
570 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
571 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
572 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
573 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
574 system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
575 system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
576 system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
577 system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
578 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
579 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
580 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
581 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
582 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
583 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
584 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
585 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
586 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
587 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
588 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
589 system.cpu0.dtb.inst_hits 0 # ITB inst hits
590 system.cpu0.dtb.inst_misses 0 # ITB inst misses
591 system.cpu0.dtb.read_hits 7346324 # DTB read hits
592 system.cpu0.dtb.read_misses 6876 # DTB read misses
593 system.cpu0.dtb.write_hits 5393725 # DTB write hits
594 system.cpu0.dtb.write_misses 1788 # DTB write misses
595 system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed
596 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
597 system.cpu0.dtb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID
598 system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
599 system.cpu0.dtb.flush_entries 6380 # Number of entries that have been flushed from TLB
600 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
601 system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
602 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
603 system.cpu0.dtb.perms_faults 236 # Number of TLB faults due to permissions restrictions
604 system.cpu0.dtb.read_accesses 7353200 # DTB read accesses
605 system.cpu0.dtb.write_accesses 5395513 # DTB write accesses
606 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
607 system.cpu0.dtb.hits 12740049 # DTB hits
608 system.cpu0.dtb.misses 8664 # DTB misses
609 system.cpu0.dtb.accesses 12748713 # DTB accesses
610 system.cpu0.itb.inst_hits 30077314 # ITB inst hits
611 system.cpu0.itb.inst_misses 3618 # ITB inst misses
612 system.cpu0.itb.read_hits 0 # DTB read hits
613 system.cpu0.itb.read_misses 0 # DTB read misses
614 system.cpu0.itb.write_hits 0 # DTB write hits
615 system.cpu0.itb.write_misses 0 # DTB write misses
616 system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed
617 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
618 system.cpu0.itb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID
619 system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
620 system.cpu0.itb.flush_entries 2643 # Number of entries that have been flushed from TLB
621 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
622 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
623 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
624 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
625 system.cpu0.itb.read_accesses 0 # DTB read accesses
626 system.cpu0.itb.write_accesses 0 # DTB write accesses
627 system.cpu0.itb.inst_accesses 30080932 # ITB inst accesses
628 system.cpu0.itb.hits 30077314 # DTB hits
629 system.cpu0.itb.misses 3618 # DTB misses
630 system.cpu0.itb.accesses 30080932 # DTB accesses
631 system.cpu0.numCycles 2667978103 # number of cpu cycles simulated
632 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
633 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
634 system.cpu0.committedInsts 29443364 # Number of instructions committed
635 system.cpu0.committedOps 37313873 # Number of ops (including micro ops) committed
636 system.cpu0.num_int_alu_accesses 33552683 # Number of integer alu accesses
637 system.cpu0.num_fp_alu_accesses 4308 # Number of float alu accesses
638 system.cpu0.num_func_calls 997498 # number of times a function call or return occured
639 system.cpu0.num_conditional_control_insts 3872350 # number of instructions that are conditional controls
640 system.cpu0.num_int_insts 33552683 # number of integer instructions
641 system.cpu0.num_fp_insts 4308 # number of float instructions
642 system.cpu0.num_int_register_reads 192457043 # number of times the integer registers were read
643 system.cpu0.num_int_register_writes 36187608 # number of times the integer registers were written
644 system.cpu0.num_fp_register_reads 3214 # number of times the floating registers were read
645 system.cpu0.num_fp_register_writes 1096 # number of times the floating registers were written
646 system.cpu0.num_mem_refs 13317945 # number of memory refs
647 system.cpu0.num_load_insts 7675788 # Number of load instructions
648 system.cpu0.num_store_insts 5642157 # Number of store instructions
649 system.cpu0.num_idle_cycles 1511306252.685236 # Number of idle cycles
650 system.cpu0.num_busy_cycles 1156671850.314764 # Number of busy cycles
651 system.cpu0.not_idle_fraction 0.433539 # Percentage of non-idle cycles
652 system.cpu0.idle_fraction 0.566461 # Percentage of idle cycles
653 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
654 system.cpu0.kern.inst.quiesce 83014 # number of quiesce instructions executed
655 system.cpu0.icache.replacements 855749 # number of replacements
656 system.cpu0.icache.tagsinuse 510.984146 # Cycle average of tags in use
657 system.cpu0.icache.total_refs 60643040 # Total number of references to valid blocks.
658 system.cpu0.icache.sampled_refs 856261 # Sample count of references to valid blocks.
659 system.cpu0.icache.avg_refs 70.823078 # Average number of references to valid blocks.
660 system.cpu0.icache.warmup_cycle 18731806000 # Cycle when the warmup percentage was hit.
661 system.cpu0.icache.occ_blocks::cpu0.inst 165.100321 # Average occupied blocks per requestor
662 system.cpu0.icache.occ_blocks::cpu1.inst 345.883825 # Average occupied blocks per requestor
663 system.cpu0.icache.occ_percent::cpu0.inst 0.322462 # Average percentage of cache occupancy
664 system.cpu0.icache.occ_percent::cpu1.inst 0.675554 # Average percentage of cache occupancy
665 system.cpu0.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy
666 system.cpu0.icache.ReadReq_hits::cpu0.inst 29681003 # number of ReadReq hits
667 system.cpu0.icache.ReadReq_hits::cpu1.inst 30962037 # number of ReadReq hits
668 system.cpu0.icache.ReadReq_hits::total 60643040 # number of ReadReq hits
669 system.cpu0.icache.demand_hits::cpu0.inst 29681003 # number of demand (read+write) hits
670 system.cpu0.icache.demand_hits::cpu1.inst 30962037 # number of demand (read+write) hits
671 system.cpu0.icache.demand_hits::total 60643040 # number of demand (read+write) hits
672 system.cpu0.icache.overall_hits::cpu0.inst 29681003 # number of overall hits
673 system.cpu0.icache.overall_hits::cpu1.inst 30962037 # number of overall hits
674 system.cpu0.icache.overall_hits::total 60643040 # number of overall hits
675 system.cpu0.icache.ReadReq_misses::cpu0.inst 396311 # number of ReadReq misses
676 system.cpu0.icache.ReadReq_misses::cpu1.inst 459950 # number of ReadReq misses
677 system.cpu0.icache.ReadReq_misses::total 856261 # number of ReadReq misses
678 system.cpu0.icache.demand_misses::cpu0.inst 396311 # number of demand (read+write) misses
679 system.cpu0.icache.demand_misses::cpu1.inst 459950 # number of demand (read+write) misses
680 system.cpu0.icache.demand_misses::total 856261 # number of demand (read+write) misses
681 system.cpu0.icache.overall_misses::cpu0.inst 396311 # number of overall misses
682 system.cpu0.icache.overall_misses::cpu1.inst 459950 # number of overall misses
683 system.cpu0.icache.overall_misses::total 856261 # number of overall misses
684 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5359552000 # number of ReadReq miss cycles
685 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6210691500 # number of ReadReq miss cycles
686 system.cpu0.icache.ReadReq_miss_latency::total 11570243500 # number of ReadReq miss cycles
687 system.cpu0.icache.demand_miss_latency::cpu0.inst 5359552000 # number of demand (read+write) miss cycles
688 system.cpu0.icache.demand_miss_latency::cpu1.inst 6210691500 # number of demand (read+write) miss cycles
689 system.cpu0.icache.demand_miss_latency::total 11570243500 # number of demand (read+write) miss cycles
690 system.cpu0.icache.overall_miss_latency::cpu0.inst 5359552000 # number of overall miss cycles
691 system.cpu0.icache.overall_miss_latency::cpu1.inst 6210691500 # number of overall miss cycles
692 system.cpu0.icache.overall_miss_latency::total 11570243500 # number of overall miss cycles
693 system.cpu0.icache.ReadReq_accesses::cpu0.inst 30077314 # number of ReadReq accesses(hits+misses)
694 system.cpu0.icache.ReadReq_accesses::cpu1.inst 31421987 # number of ReadReq accesses(hits+misses)
695 system.cpu0.icache.ReadReq_accesses::total 61499301 # number of ReadReq accesses(hits+misses)
696 system.cpu0.icache.demand_accesses::cpu0.inst 30077314 # number of demand (read+write) accesses
697 system.cpu0.icache.demand_accesses::cpu1.inst 31421987 # number of demand (read+write) accesses
698 system.cpu0.icache.demand_accesses::total 61499301 # number of demand (read+write) accesses
699 system.cpu0.icache.overall_accesses::cpu0.inst 30077314 # number of overall (read+write) accesses
700 system.cpu0.icache.overall_accesses::cpu1.inst 31421987 # number of overall (read+write) accesses
701 system.cpu0.icache.overall_accesses::total 61499301 # number of overall (read+write) accesses
702 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013176 # miss rate for ReadReq accesses
703 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014638 # miss rate for ReadReq accesses
704 system.cpu0.icache.ReadReq_miss_rate::total 0.013923 # miss rate for ReadReq accesses
705 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013176 # miss rate for demand accesses
706 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014638 # miss rate for demand accesses
707 system.cpu0.icache.demand_miss_rate::total 0.013923 # miss rate for demand accesses
708 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013176 # miss rate for overall accesses
709 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014638 # miss rate for overall accesses
710 system.cpu0.icache.overall_miss_rate::total 0.013923 # miss rate for overall accesses
711 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13523.601414 # average ReadReq miss latency
712 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13502.970975 # average ReadReq miss latency
713 system.cpu0.icache.ReadReq_avg_miss_latency::total 13512.519547 # average ReadReq miss latency
714 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency
715 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency
716 system.cpu0.icache.demand_avg_miss_latency::total 13512.519547 # average overall miss latency
717 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency
718 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency
719 system.cpu0.icache.overall_avg_miss_latency::total 13512.519547 # average overall miss latency
720 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
721 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
722 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
723 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
724 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
725 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
726 system.cpu0.icache.fast_writes 0 # number of fast writes performed
727 system.cpu0.icache.cache_copies 0 # number of cache copies performed
728 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 396311 # number of ReadReq MSHR misses
729 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 459950 # number of ReadReq MSHR misses
730 system.cpu0.icache.ReadReq_mshr_misses::total 856261 # number of ReadReq MSHR misses
731 system.cpu0.icache.demand_mshr_misses::cpu0.inst 396311 # number of demand (read+write) MSHR misses
732 system.cpu0.icache.demand_mshr_misses::cpu1.inst 459950 # number of demand (read+write) MSHR misses
733 system.cpu0.icache.demand_mshr_misses::total 856261 # number of demand (read+write) MSHR misses
734 system.cpu0.icache.overall_mshr_misses::cpu0.inst 396311 # number of overall MSHR misses
735 system.cpu0.icache.overall_mshr_misses::cpu1.inst 459950 # number of overall MSHR misses
736 system.cpu0.icache.overall_mshr_misses::total 856261 # number of overall MSHR misses
737 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4566930000 # number of ReadReq MSHR miss cycles
738 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5290791500 # number of ReadReq MSHR miss cycles
739 system.cpu0.icache.ReadReq_mshr_miss_latency::total 9857721500 # number of ReadReq MSHR miss cycles
740 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4566930000 # number of demand (read+write) MSHR miss cycles
741 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5290791500 # number of demand (read+write) MSHR miss cycles
742 system.cpu0.icache.demand_mshr_miss_latency::total 9857721500 # number of demand (read+write) MSHR miss cycles
743 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4566930000 # number of overall MSHR miss cycles
744 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5290791500 # number of overall MSHR miss cycles
745 system.cpu0.icache.overall_mshr_miss_latency::total 9857721500 # number of overall MSHR miss cycles
746 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288141500 # number of ReadReq MSHR uncacheable cycles
747 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles
748 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288141500 # number of overall MSHR uncacheable cycles
749 system.cpu0.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles
750 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013176 # mshr miss rate for ReadReq accesses
751 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014638 # mshr miss rate for ReadReq accesses
752 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013923 # mshr miss rate for ReadReq accesses
753 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013176 # mshr miss rate for demand accesses
754 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014638 # mshr miss rate for demand accesses
755 system.cpu0.icache.demand_mshr_miss_rate::total 0.013923 # mshr miss rate for demand accesses
756 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013176 # mshr miss rate for overall accesses
757 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014638 # mshr miss rate for overall accesses
758 system.cpu0.icache.overall_mshr_miss_rate::total 0.013923 # mshr miss rate for overall accesses
759 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11523.601414 # average ReadReq mshr miss latency
760 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11502.970975 # average ReadReq mshr miss latency
761 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11512.519547 # average ReadReq mshr miss latency
762 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11523.601414 # average overall mshr miss latency
763 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11502.970975 # average overall mshr miss latency
764 system.cpu0.icache.demand_avg_mshr_miss_latency::total 11512.519547 # average overall mshr miss latency
765 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11523.601414 # average overall mshr miss latency
766 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11502.970975 # average overall mshr miss latency
767 system.cpu0.icache.overall_avg_mshr_miss_latency::total 11512.519547 # average overall mshr miss latency
768 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
769 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
770 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
771 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
772 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
773 system.cpu0.dcache.replacements 627576 # number of replacements
774 system.cpu0.dcache.tagsinuse 511.914984 # Cycle average of tags in use
775 system.cpu0.dcache.total_refs 23658480 # Total number of references to valid blocks.
776 system.cpu0.dcache.sampled_refs 628088 # Sample count of references to valid blocks.
777 system.cpu0.dcache.avg_refs 37.667461 # Average number of references to valid blocks.
778 system.cpu0.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
779 system.cpu0.dcache.occ_blocks::cpu0.data 142.165809 # Average occupied blocks per requestor
780 system.cpu0.dcache.occ_blocks::cpu1.data 369.749176 # Average occupied blocks per requestor
781 system.cpu0.dcache.occ_percent::cpu0.data 0.277668 # Average percentage of cache occupancy
782 system.cpu0.dcache.occ_percent::cpu1.data 0.722166 # Average percentage of cache occupancy
783 system.cpu0.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
784 system.cpu0.dcache.ReadReq_hits::cpu0.data 6448677 # number of ReadReq hits
785 system.cpu0.dcache.ReadReq_hits::cpu1.data 6748535 # number of ReadReq hits
786 system.cpu0.dcache.ReadReq_hits::total 13197212 # number of ReadReq hits
787 system.cpu0.dcache.WriteReq_hits::cpu0.data 4778089 # number of WriteReq hits
788 system.cpu0.dcache.WriteReq_hits::cpu1.data 5196213 # number of WriteReq hits
789 system.cpu0.dcache.WriteReq_hits::total 9974302 # number of WriteReq hits
790 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 105697 # number of LoadLockedReq hits
791 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 130631 # number of LoadLockedReq hits
792 system.cpu0.dcache.LoadLockedReq_hits::total 236328 # number of LoadLockedReq hits
793 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 111573 # number of StoreCondReq hits
794 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 136161 # number of StoreCondReq hits
795 system.cpu0.dcache.StoreCondReq_hits::total 247734 # number of StoreCondReq hits
796 system.cpu0.dcache.demand_hits::cpu0.data 11226766 # number of demand (read+write) hits
797 system.cpu0.dcache.demand_hits::cpu1.data 11944748 # number of demand (read+write) hits
798 system.cpu0.dcache.demand_hits::total 23171514 # number of demand (read+write) hits
799 system.cpu0.dcache.overall_hits::cpu0.data 11226766 # number of overall hits
800 system.cpu0.dcache.overall_hits::cpu1.data 11944748 # number of overall hits
801 system.cpu0.dcache.overall_hits::total 23171514 # number of overall hits
802 system.cpu0.dcache.ReadReq_misses::cpu0.data 185759 # number of ReadReq misses
803 system.cpu0.dcache.ReadReq_misses::cpu1.data 183249 # number of ReadReq misses
804 system.cpu0.dcache.ReadReq_misses::total 369008 # number of ReadReq misses
805 system.cpu0.dcache.WriteReq_misses::cpu0.data 122710 # number of WriteReq misses
806 system.cpu0.dcache.WriteReq_misses::cpu1.data 127868 # number of WriteReq misses
807 system.cpu0.dcache.WriteReq_misses::total 250578 # number of WriteReq misses
808 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5877 # number of LoadLockedReq misses
809 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5530 # number of LoadLockedReq misses
810 system.cpu0.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses
811 system.cpu0.dcache.demand_misses::cpu0.data 308469 # number of demand (read+write) misses
812 system.cpu0.dcache.demand_misses::cpu1.data 311117 # number of demand (read+write) misses
813 system.cpu0.dcache.demand_misses::total 619586 # number of demand (read+write) misses
814 system.cpu0.dcache.overall_misses::cpu0.data 308469 # number of overall misses
815 system.cpu0.dcache.overall_misses::cpu1.data 311117 # number of overall misses
816 system.cpu0.dcache.overall_misses::total 619586 # number of overall misses
817 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2627565000 # number of ReadReq miss cycles
818 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2598558000 # number of ReadReq miss cycles
819 system.cpu0.dcache.ReadReq_miss_latency::total 5226123000 # number of ReadReq miss cycles
820 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3886745500 # number of WriteReq miss cycles
821 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4117005000 # number of WriteReq miss cycles
822 system.cpu0.dcache.WriteReq_miss_latency::total 8003750500 # number of WriteReq miss cycles
823 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81831500 # number of LoadLockedReq miss cycles
824 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 73520000 # number of LoadLockedReq miss cycles
825 system.cpu0.dcache.LoadLockedReq_miss_latency::total 155351500 # number of LoadLockedReq miss cycles
826 system.cpu0.dcache.demand_miss_latency::cpu0.data 6514310500 # number of demand (read+write) miss cycles
827 system.cpu0.dcache.demand_miss_latency::cpu1.data 6715563000 # number of demand (read+write) miss cycles
828 system.cpu0.dcache.demand_miss_latency::total 13229873500 # number of demand (read+write) miss cycles
829 system.cpu0.dcache.overall_miss_latency::cpu0.data 6514310500 # number of overall miss cycles
830 system.cpu0.dcache.overall_miss_latency::cpu1.data 6715563000 # number of overall miss cycles
831 system.cpu0.dcache.overall_miss_latency::total 13229873500 # number of overall miss cycles
832 system.cpu0.dcache.ReadReq_accesses::cpu0.data 6634436 # number of ReadReq accesses(hits+misses)
833 system.cpu0.dcache.ReadReq_accesses::cpu1.data 6931784 # number of ReadReq accesses(hits+misses)
834 system.cpu0.dcache.ReadReq_accesses::total 13566220 # number of ReadReq accesses(hits+misses)
835 system.cpu0.dcache.WriteReq_accesses::cpu0.data 4900799 # number of WriteReq accesses(hits+misses)
836 system.cpu0.dcache.WriteReq_accesses::cpu1.data 5324081 # number of WriteReq accesses(hits+misses)
837 system.cpu0.dcache.WriteReq_accesses::total 10224880 # number of WriteReq accesses(hits+misses)
838 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 111574 # number of LoadLockedReq accesses(hits+misses)
839 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 136161 # number of LoadLockedReq accesses(hits+misses)
840 system.cpu0.dcache.LoadLockedReq_accesses::total 247735 # number of LoadLockedReq accesses(hits+misses)
841 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 111573 # number of StoreCondReq accesses(hits+misses)
842 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 136161 # number of StoreCondReq accesses(hits+misses)
843 system.cpu0.dcache.StoreCondReq_accesses::total 247734 # number of StoreCondReq accesses(hits+misses)
844 system.cpu0.dcache.demand_accesses::cpu0.data 11535235 # number of demand (read+write) accesses
845 system.cpu0.dcache.demand_accesses::cpu1.data 12255865 # number of demand (read+write) accesses
846 system.cpu0.dcache.demand_accesses::total 23791100 # number of demand (read+write) accesses
847 system.cpu0.dcache.overall_accesses::cpu0.data 11535235 # number of overall (read+write) accesses
848 system.cpu0.dcache.overall_accesses::cpu1.data 12255865 # number of overall (read+write) accesses
849 system.cpu0.dcache.overall_accesses::total 23791100 # number of overall (read+write) accesses
850 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027999 # miss rate for ReadReq accesses
851 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026436 # miss rate for ReadReq accesses
852 system.cpu0.dcache.ReadReq_miss_rate::total 0.027201 # miss rate for ReadReq accesses
853 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025039 # miss rate for WriteReq accesses
854 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024017 # miss rate for WriteReq accesses
855 system.cpu0.dcache.WriteReq_miss_rate::total 0.024507 # miss rate for WriteReq accesses
856 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052674 # miss rate for LoadLockedReq accesses
857 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.040614 # miss rate for LoadLockedReq accesses
858 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046045 # miss rate for LoadLockedReq accesses
859 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026741 # miss rate for demand accesses
860 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025385 # miss rate for demand accesses
861 system.cpu0.dcache.demand_miss_rate::total 0.026043 # miss rate for demand accesses
862 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026741 # miss rate for overall accesses
863 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025385 # miss rate for overall accesses
864 system.cpu0.dcache.overall_miss_rate::total 0.026043 # miss rate for overall accesses
865 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14145.021237 # average ReadReq miss latency
866 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14180.475746 # average ReadReq miss latency
867 system.cpu0.dcache.ReadReq_avg_miss_latency::total 14162.627911 # average ReadReq miss latency
868 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31674.236004 # average WriteReq miss latency
869 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32197.305033 # average WriteReq miss latency
870 system.cpu0.dcache.WriteReq_avg_miss_latency::total 31941.154052 # average WriteReq miss latency
871 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13924.025864 # average LoadLockedReq miss latency
872 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13294.755877 # average LoadLockedReq miss latency
873 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13618.962041 # average LoadLockedReq miss latency
874 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21118.201505 # average overall miss latency
875 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21585.329635 # average overall miss latency
876 system.cpu0.dcache.demand_avg_miss_latency::total 21352.763781 # average overall miss latency
877 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21118.201505 # average overall miss latency
878 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21585.329635 # average overall miss latency
879 system.cpu0.dcache.overall_avg_miss_latency::total 21352.763781 # average overall miss latency
880 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
881 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
882 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
883 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
884 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
885 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
886 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
887 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
888 system.cpu0.dcache.writebacks::writebacks 596393 # number of writebacks
889 system.cpu0.dcache.writebacks::total 596393 # number of writebacks
890 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185759 # number of ReadReq MSHR misses
891 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 183249 # number of ReadReq MSHR misses
892 system.cpu0.dcache.ReadReq_mshr_misses::total 369008 # number of ReadReq MSHR misses
893 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 122710 # number of WriteReq MSHR misses
894 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 127868 # number of WriteReq MSHR misses
895 system.cpu0.dcache.WriteReq_mshr_misses::total 250578 # number of WriteReq MSHR misses
896 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5877 # number of LoadLockedReq MSHR misses
897 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5530 # number of LoadLockedReq MSHR misses
898 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses
899 system.cpu0.dcache.demand_mshr_misses::cpu0.data 308469 # number of demand (read+write) MSHR misses
900 system.cpu0.dcache.demand_mshr_misses::cpu1.data 311117 # number of demand (read+write) MSHR misses
901 system.cpu0.dcache.demand_mshr_misses::total 619586 # number of demand (read+write) MSHR misses
902 system.cpu0.dcache.overall_mshr_misses::cpu0.data 308469 # number of overall MSHR misses
903 system.cpu0.dcache.overall_mshr_misses::cpu1.data 311117 # number of overall MSHR misses
904 system.cpu0.dcache.overall_mshr_misses::total 619586 # number of overall MSHR misses
905 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2256047000 # number of ReadReq MSHR miss cycles
906 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2232060000 # number of ReadReq MSHR miss cycles
907 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4488107000 # number of ReadReq MSHR miss cycles
908 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3641325500 # number of WriteReq MSHR miss cycles
909 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3861269000 # number of WriteReq MSHR miss cycles
910 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7502594500 # number of WriteReq MSHR miss cycles
911 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70077500 # number of LoadLockedReq MSHR miss cycles
912 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62460000 # number of LoadLockedReq MSHR miss cycles
913 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132537500 # number of LoadLockedReq MSHR miss cycles
914 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5897372500 # number of demand (read+write) MSHR miss cycles
915 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6093329000 # number of demand (read+write) MSHR miss cycles
916 system.cpu0.dcache.demand_mshr_miss_latency::total 11990701500 # number of demand (read+write) MSHR miss cycles
917 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5897372500 # number of overall MSHR miss cycles
918 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6093329000 # number of overall MSHR miss cycles
919 system.cpu0.dcache.overall_mshr_miss_latency::total 11990701500 # number of overall MSHR miss cycles
920 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92330241000 # number of ReadReq MSHR uncacheable cycles
921 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89759244500 # number of ReadReq MSHR uncacheable cycles
922 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182089485500 # number of ReadReq MSHR uncacheable cycles
923 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9446181000 # number of WriteReq MSHR uncacheable cycles
924 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9255751500 # number of WriteReq MSHR uncacheable cycles
925 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18701932500 # number of WriteReq MSHR uncacheable cycles
926 system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles
927 system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles
928 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
929 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
930 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101776422000 # number of overall MSHR uncacheable cycles
931 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99014996000 # number of overall MSHR uncacheable cycles
932 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200791418000 # number of overall MSHR uncacheable cycles
933 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027999 # mshr miss rate for ReadReq accesses
934 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026436 # mshr miss rate for ReadReq accesses
935 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses
936 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025039 # mshr miss rate for WriteReq accesses
937 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024017 # mshr miss rate for WriteReq accesses
938 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024507 # mshr miss rate for WriteReq accesses
939 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.052674 # mshr miss rate for LoadLockedReq accesses
940 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040614 # mshr miss rate for LoadLockedReq accesses
941 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046045 # mshr miss rate for LoadLockedReq accesses
942 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for demand accesses
943 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for demand accesses
944 system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses
945 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for overall accesses
946 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for overall accesses
947 system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses
948 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12145.021237 # average ReadReq mshr miss latency
949 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.475746 # average ReadReq mshr miss latency
950 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12162.627911 # average ReadReq mshr miss latency
951 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29674.236004 # average WriteReq mshr miss latency
952 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30197.305033 # average WriteReq mshr miss latency
953 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29941.154052 # average WriteReq mshr miss latency
954 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11924.025864 # average LoadLockedReq mshr miss latency
955 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11294.755877 # average LoadLockedReq mshr miss latency
956 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.962041 # average LoadLockedReq mshr miss latency
957 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency
958 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency
959 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency
960 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency
961 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency
962 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency
963 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
964 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
965 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
966 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
967 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
968 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
969 system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
970 system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
971 system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
972 system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
973 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
974 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
975 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
976 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
977 system.cpu1.dtb.inst_hits 0 # ITB inst hits
978 system.cpu1.dtb.inst_misses 0 # ITB inst misses
979 system.cpu1.dtb.read_hits 7651718 # DTB read hits
980 system.cpu1.dtb.read_misses 6996 # DTB read misses
981 system.cpu1.dtb.write_hits 5838563 # DTB write hits
982 system.cpu1.dtb.write_misses 1808 # DTB write misses
983 system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
984 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
985 system.cpu1.dtb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID
986 system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID
987 system.cpu1.dtb.flush_entries 6464 # Number of entries that have been flushed from TLB
988 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
989 system.cpu1.dtb.prefetch_faults 130 # Number of TLB faults due to prefetch
990 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
991 system.cpu1.dtb.perms_faults 216 # Number of TLB faults due to permissions restrictions
992 system.cpu1.dtb.read_accesses 7658714 # DTB read accesses
993 system.cpu1.dtb.write_accesses 5840371 # DTB write accesses
994 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
995 system.cpu1.dtb.hits 13490281 # DTB hits
996 system.cpu1.dtb.misses 8804 # DTB misses
997 system.cpu1.dtb.accesses 13499085 # DTB accesses
998 system.cpu1.itb.inst_hits 31421987 # ITB inst hits
999 system.cpu1.itb.inst_misses 3616 # ITB inst misses
1000 system.cpu1.itb.read_hits 0 # DTB read hits
1001 system.cpu1.itb.read_misses 0 # DTB read misses
1002 system.cpu1.itb.write_hits 0 # DTB write hits
1003 system.cpu1.itb.write_misses 0 # DTB write misses
1004 system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed
1005 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1006 system.cpu1.itb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID
1007 system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID
1008 system.cpu1.itb.flush_entries 2808 # Number of entries that have been flushed from TLB
1009 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1010 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1011 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1012 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1013 system.cpu1.itb.read_accesses 0 # DTB read accesses
1014 system.cpu1.itb.write_accesses 0 # DTB write accesses
1015 system.cpu1.itb.inst_accesses 31425603 # ITB inst accesses
1016 system.cpu1.itb.hits 31421987 # DTB hits
1017 system.cpu1.itb.misses 3616 # DTB misses
1018 system.cpu1.itb.accesses 31425603 # DTB accesses
1019 system.cpu1.numCycles 2550975631 # number of cpu cycles simulated
1020 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1021 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1022 system.cpu1.committedInsts 30761879 # Number of instructions committed
1023 system.cpu1.committedOps 39296860 # Number of ops (including micro ops) committed
1024 system.cpu1.num_int_alu_accesses 35324832 # Number of integer alu accesses
1025 system.cpu1.num_fp_alu_accesses 5961 # Number of float alu accesses
1026 system.cpu1.num_func_calls 1142639 # number of times a function call or return occured
1027 system.cpu1.num_conditional_control_insts 4076383 # number of instructions that are conditional controls
1028 system.cpu1.num_int_insts 35324832 # number of integer instructions
1029 system.cpu1.num_fp_insts 5961 # number of float instructions
1030 system.cpu1.num_int_register_reads 202353181 # number of times the integer registers were read
1031 system.cpu1.num_int_register_writes 37998347 # number of times the integer registers were written
1032 system.cpu1.num_fp_register_reads 4279 # number of times the floating registers were read
1033 system.cpu1.num_fp_register_writes 1684 # number of times the floating registers were written
1034 system.cpu1.num_mem_refs 14079956 # number of memory refs
1035 system.cpu1.num_load_insts 7986446 # Number of load instructions
1036 system.cpu1.num_store_insts 6093510 # Number of store instructions
1037 system.cpu1.num_idle_cycles 3341647478.137703 # Number of idle cycles
1038 system.cpu1.num_busy_cycles -790671847.137703 # Number of busy cycles
1039 system.cpu1.not_idle_fraction -0.309949 # Percentage of non-idle cycles
1040 system.cpu1.idle_fraction 1.309949 # Percentage of idle cycles
1041 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1042 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1043 system.iocache.replacements 0 # number of replacements
1044 system.iocache.tagsinuse 0 # Cycle average of tags in use
1045 system.iocache.total_refs 0 # Total number of references to valid blocks.
1046 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1047 system.iocache.avg_refs nan # Average number of references to valid blocks.
1048 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1049 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1050 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1051 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1052 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1053 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1054 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1055 system.iocache.fast_writes 0 # number of fast writes performed
1056 system.iocache.cache_copies 0 # number of cache copies performed
1057 system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of ReadReq MSHR uncacheable cycles
1058 system.iocache.ReadReq_mshr_uncacheable_latency::total 1128670778319 # number of ReadReq MSHR uncacheable cycles
1059 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of overall MSHR uncacheable cycles
1060 system.iocache.overall_mshr_uncacheable_latency::total 1128670778319 # number of overall MSHR uncacheable cycles
1061 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1062 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1063 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1064 system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1065 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1067 ---------- End Simulation Statistics ----------
projects / gem5.git / blob