2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 47.454492 # Number of seconds simulated
4 sim_ticks 47454492026000 # Number of ticks simulated
5 final_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 326065 # Simulator instruction rate (inst/s)
8 host_op_rate 383423 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 16260643539 # Simulator tick rate (ticks/s)
10 host_mem_usage 772552 # Number of bytes of host memory used
11 host_seconds 2918.37 # Real time elapsed on the host
12 sim_insts 951575519 # Number of instructions simulated
13 sim_ops 1118968402 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory
26 system.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory
27 system.physmem.bytes_read::total 82346584 # Number of bytes read from this memory
28 system.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory
31 system.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory
32 system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33 system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34 system.physmem.bytes_written::total 92942888 # Number of bytes written to this memory
35 system.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory
45 system.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory
46 system.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory
47 system.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory
48 system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49 system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50 system.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory
51 system.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.readReqs 1286691 # Number of read requests accepted
84 system.physmem.writeReqs 1454485 # Number of write requests accepted
85 system.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue
86 system.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue
87 system.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM
88 system.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue
89 system.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM
90 system.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side
91 system.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side
92 system.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue
93 system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
94 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95 system.physmem.perBankRdBursts::0 68545 # Per bank write bursts
96 system.physmem.perBankRdBursts::1 77862 # Per bank write bursts
97 system.physmem.perBankRdBursts::2 76461 # Per bank write bursts
98 system.physmem.perBankRdBursts::3 81936 # Per bank write bursts
99 system.physmem.perBankRdBursts::4 74664 # Per bank write bursts
100 system.physmem.perBankRdBursts::5 81822 # Per bank write bursts
101 system.physmem.perBankRdBursts::6 81067 # Per bank write bursts
102 system.physmem.perBankRdBursts::7 83827 # Per bank write bursts
103 system.physmem.perBankRdBursts::8 73756 # Per bank write bursts
104 system.physmem.perBankRdBursts::9 133954 # Per bank write bursts
105 system.physmem.perBankRdBursts::10 75964 # Per bank write bursts
106 system.physmem.perBankRdBursts::11 77586 # Per bank write bursts
107 system.physmem.perBankRdBursts::12 69247 # Per bank write bursts
108 system.physmem.perBankRdBursts::13 78127 # Per bank write bursts
109 system.physmem.perBankRdBursts::14 73347 # Per bank write bursts
110 system.physmem.perBankRdBursts::15 78045 # Per bank write bursts
111 system.physmem.perBankWrBursts::0 83788 # Per bank write bursts
112 system.physmem.perBankWrBursts::1 90226 # Per bank write bursts
113 system.physmem.perBankWrBursts::2 90168 # Per bank write bursts
114 system.physmem.perBankWrBursts::3 95983 # Per bank write bursts
115 system.physmem.perBankWrBursts::4 89513 # Per bank write bursts
116 system.physmem.perBankWrBursts::5 93413 # Per bank write bursts
117 system.physmem.perBankWrBursts::6 92742 # Per bank write bursts
118 system.physmem.perBankWrBursts::7 93553 # Per bank write bursts
119 system.physmem.perBankWrBursts::8 87937 # Per bank write bursts
120 system.physmem.perBankWrBursts::9 94416 # Per bank write bursts
121 system.physmem.perBankWrBursts::10 91588 # Per bank write bursts
122 system.physmem.perBankWrBursts::11 94818 # Per bank write bursts
123 system.physmem.perBankWrBursts::12 85405 # Per bank write bursts
124 system.physmem.perBankWrBursts::13 92349 # Per bank write bursts
125 system.physmem.perBankWrBursts::14 86484 # Per bank write bursts
126 system.physmem.perBankWrBursts::15 89834 # Per bank write bursts
127 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128 system.physmem.numWrRetry 36 # Number of times write queue was full causing retry
129 system.physmem.totGap 47454489913500 # Total gap between requests
130 system.physmem.readPktSize::0 0 # Read request sizes (log2)
131 system.physmem.readPktSize::1 0 # Read request sizes (log2)
132 system.physmem.readPktSize::2 0 # Read request sizes (log2)
133 system.physmem.readPktSize::3 25 # Read request sizes (log2)
134 system.physmem.readPktSize::4 5 # Read request sizes (log2)
135 system.physmem.readPktSize::5 0 # Read request sizes (log2)
136 system.physmem.readPktSize::6 1286661 # Read request sizes (log2)
137 system.physmem.writePktSize::0 0 # Write request sizes (log2)
138 system.physmem.writePktSize::1 0 # Write request sizes (log2)
139 system.physmem.writePktSize::2 2 # Write request sizes (log2)
140 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141 system.physmem.writePktSize::4 0 # Write request sizes (log2)
142 system.physmem.writePktSize::5 0 # Write request sizes (log2)
143 system.physmem.writePktSize::6 1451911 # Write request sizes (log2)
144 system.physmem.rdQLenPdf::0 827173 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::1 164897 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::2 63225 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::3 47515 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::4 40751 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::5 37481 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::6 33938 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::7 30502 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::8 26328 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::9 5741 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::10 2483 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::11 1712 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::12 1354 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::13 989 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::14 645 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::15 527 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::16 427 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::17 343 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
176 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::15 34612 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::16 41901 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::17 58265 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::18 63048 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::19 69768 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::20 73771 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::21 78937 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::22 85048 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::23 89045 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::24 90562 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::25 92833 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::26 96249 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::27 94408 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::28 95986 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::29 105469 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::30 93952 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::31 86808 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::32 83066 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::33 4836 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::34 2469 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::35 1685 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::36 1217 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::37 978 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::38 762 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::40 465 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::41 413 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::42 418 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::43 367 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::44 375 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::45 388 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::47 299 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::63 99 # What write queue length does an incoming req see
240 system.physmem.bytesPerActivate::samples 1224605 # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::mean 143.114986 # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::gmean 97.246112 # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::stdev 190.672457 # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::0-127 830563 67.82% 67.82% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::128-255 233051 19.03% 86.85% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::256-383 57759 4.72% 91.57% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::384-511 27718 2.26% 93.83% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::512-639 20623 1.68% 95.52% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::640-767 13112 1.07% 96.59% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::768-895 7173 0.59% 97.17% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::896-1023 5754 0.47% 97.64% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::1024-1151 28852 2.36% 100.00% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::total 1224605 # Bytes accessed per row activation
254 system.physmem.rdPerTurnAround::samples 77530 # Reads before turning the bus around for writes
255 system.physmem.rdPerTurnAround::mean 16.589449 # Reads before turning the bus around for writes
256 system.physmem.rdPerTurnAround::stdev 141.842916 # Reads before turning the bus around for writes
257 system.physmem.rdPerTurnAround::0-1023 77527 100.00% 100.00% # Reads before turning the bus around for writes
258 system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
259 system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
261 system.physmem.rdPerTurnAround::total 77530 # Reads before turning the bus around for writes
262 system.physmem.wrPerTurnAround::samples 77530 # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::mean 18.731033 # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::gmean 18.088703 # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::stdev 7.268543 # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::16-19 64617 83.34% 83.34% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::20-23 6035 7.78% 91.13% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::24-27 3056 3.94% 95.07% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::28-31 1620 2.09% 97.16% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::32-35 474 0.61% 97.77% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::36-39 277 0.36% 98.13% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::40-43 269 0.35% 98.48% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::44-47 83 0.11% 98.58% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::48-51 290 0.37% 98.96% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::52-55 69 0.09% 99.05% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::56-59 30 0.04% 99.08% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::60-63 52 0.07% 99.15% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::64-67 249 0.32% 99.47% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::68-71 33 0.04% 99.52% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::72-75 40 0.05% 99.57% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::76-79 110 0.14% 99.71% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::80-83 167 0.22% 99.92% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::120-123 3 0.00% 99.94% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::128-131 15 0.02% 99.96% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
299 system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
300 system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
301 system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads
302 system.physmem.wrPerTurnAround::total 77530 # Writes before turning the bus around for reads
303 system.physmem.totQLat 47048753044 # Total ticks spent queuing
304 system.physmem.totMemAccLat 71165190544 # Total ticks spent from burst creation until serviced by the DRAM
305 system.physmem.totBusLat 6431050000 # Total ticks spent in databus transfers
306 system.physmem.avgQLat 36579.37 # Average queueing delay per DRAM burst
307 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
308 system.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst
309 system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
310 system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s
311 system.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s
312 system.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s
313 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
314 system.physmem.busUtil 0.03 # Data bus utilization in percentage
315 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
316 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
317 system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
318 system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing
319 system.physmem.readRowHits 962295 # Number of row buffer hits during reads
320 system.physmem.writeRowHits 551527 # Number of row buffer hits during writes
321 system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads
322 system.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes
323 system.physmem.avgGap 17311726.76 # Average gap between requests
324 system.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined
325 system.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ)
326 system.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ)
327 system.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ)
328 system.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ)
329 system.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ)
330 system.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ)
331 system.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ)
332 system.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ)
333 system.physmem_0.averagePower 668.824424 # Core power per rank (mW)
334 system.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states
335 system.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states
336 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
337 system.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states
338 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
339 system.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ)
340 system.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ)
341 system.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ)
342 system.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ)
343 system.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ)
344 system.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ)
345 system.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ)
346 system.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ)
347 system.physmem_1.averagePower 668.833200 # Core power per rank (mW)
348 system.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states
349 system.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states
350 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
351 system.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states
352 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
353 system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
354 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
355 system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
356 system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
357 system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
358 system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
359 system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
360 system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
361 system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
362 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
363 system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
364 system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
365 system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
366 system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
367 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
368 system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
369 system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
370 system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
371 system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
372 system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
373 system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
374 system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
375 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
376 system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
377 system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
378 system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
379 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
380 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
381 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
382 system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
383 system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
384 system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
385 system.cpu0.branchPred.lookups 147959066 # Number of BP lookups
386 system.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted
387 system.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect
388 system.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups
389 system.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits
390 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
391 system.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage
392 system.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target.
393 system.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions.
394 system.cpu_clk_domain.clock 500 # Clock period in ticks
395 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
396 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
397 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
398 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
399 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
400 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
401 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
402 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
403 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
404 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
405 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
406 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
407 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
408 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
409 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
410 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
411 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
412 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
413 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
414 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
415 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
416 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
417 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
418 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
419 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
420 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
421 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
422 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
423 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
424 system.cpu0.dtb.walker.walks 300034 # Table walker walks requested
425 system.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors
426 system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate
427 system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate
428 system.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency
429 system.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency
430 system.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency
431 system.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency
432 system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency
433 system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency
434 system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency
435 system.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency
436 system.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency
437 system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency
438 system.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency
439 system.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency
440 system.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency
441 system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency
442 system.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency
443 system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
444 system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
445 system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
446 system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
447 system.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency
448 system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
449 system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
450 system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
451 system.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated
452 system.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated
453 system.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated
454 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst
455 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
456 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst
457 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst
458 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
459 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst
460 system.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst
461 system.cpu0.dtb.inst_hits 0 # ITB inst hits
462 system.cpu0.dtb.inst_misses 0 # ITB inst misses
463 system.cpu0.dtb.read_hits 94891169 # DTB read hits
464 system.cpu0.dtb.read_misses 247198 # DTB read misses
465 system.cpu0.dtb.write_hits 84318368 # DTB write hits
466 system.cpu0.dtb.write_misses 52836 # DTB write misses
467 system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
468 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
469 system.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
470 system.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
471 system.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB
472 system.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions
473 system.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch
474 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
475 system.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions
476 system.cpu0.dtb.read_accesses 95138367 # DTB read accesses
477 system.cpu0.dtb.write_accesses 84371204 # DTB write accesses
478 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
479 system.cpu0.dtb.hits 179209537 # DTB hits
480 system.cpu0.dtb.misses 300034 # DTB misses
481 system.cpu0.dtb.accesses 179509571 # DTB accesses
482 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
483 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
484 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
485 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
486 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
487 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
488 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
489 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
490 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
491 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
492 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
493 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
494 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
495 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
496 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
497 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
498 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
499 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
500 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
501 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
502 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
503 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
504 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
505 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
506 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
507 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
508 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
509 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
510 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
511 system.cpu0.itb.walker.walks 71231 # Table walker walks requested
512 system.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors
513 system.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate
514 system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate
515 system.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency
516 system.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency
517 system.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency
518 system.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency
519 system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency
520 system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency
521 system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency
522 system.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency
523 system.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency
524 system.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency
525 system.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency
526 system.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency
527 system.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency
528 system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency
529 system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
530 system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
531 system.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency
532 system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
533 system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
534 system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
535 system.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated
536 system.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated
537 system.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated
538 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
539 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst
540 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst
541 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
542 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst
543 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst
544 system.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst
545 system.cpu0.itb.inst_hits 264582301 # ITB inst hits
546 system.cpu0.itb.inst_misses 71231 # ITB inst misses
547 system.cpu0.itb.read_hits 0 # DTB read hits
548 system.cpu0.itb.read_misses 0 # DTB read misses
549 system.cpu0.itb.write_hits 0 # DTB write hits
550 system.cpu0.itb.write_misses 0 # DTB write misses
551 system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
552 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
553 system.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
554 system.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
555 system.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB
556 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
557 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
558 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
559 system.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions
560 system.cpu0.itb.read_accesses 0 # DTB read accesses
561 system.cpu0.itb.write_accesses 0 # DTB write accesses
562 system.cpu0.itb.inst_accesses 264653532 # ITB inst accesses
563 system.cpu0.itb.hits 264582301 # DTB hits
564 system.cpu0.itb.misses 71231 # DTB misses
565 system.cpu0.itb.accesses 264653532 # DTB accesses
566 system.cpu0.numCycles 1106984671 # number of cpu cycles simulated
567 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
568 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
569 system.cpu0.committedInsts 488099503 # Number of instructions committed
570 system.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed
571 system.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit
572 system.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching
573 system.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
574 system.cpu0.cpi 2.267949 # CPI: cycles per instruction
575 system.cpu0.ipc 0.440927 # IPC: instructions per cycle
576 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
577 system.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed
578 system.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked
579 system.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped
580 system.cpu0.dcache.tags.replacements 6140209 # number of replacements
581 system.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use
582 system.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks.
583 system.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks.
584 system.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks.
585 system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
586 system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor
587 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy
588 system.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy
589 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
590 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
591 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
592 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
593 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
594 system.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses
595 system.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses
596 system.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits
597 system.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits
598 system.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits
599 system.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits
600 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits
601 system.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits
602 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits
603 system.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits
604 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits
605 system.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits
606 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1943002 # number of StoreCondReq hits
607 system.cpu0.dcache.StoreCondReq_hits::total 1943002 # number of StoreCondReq hits
608 system.cpu0.dcache.demand_hits::cpu0.data 165059366 # number of demand (read+write) hits
609 system.cpu0.dcache.demand_hits::total 165059366 # number of demand (read+write) hits
610 system.cpu0.dcache.overall_hits::cpu0.data 165328284 # number of overall hits
611 system.cpu0.dcache.overall_hits::total 165328284 # number of overall hits
612 system.cpu0.dcache.ReadReq_misses::cpu0.data 3776237 # number of ReadReq misses
613 system.cpu0.dcache.ReadReq_misses::total 3776237 # number of ReadReq misses
614 system.cpu0.dcache.WriteReq_misses::cpu0.data 2642039 # number of WriteReq misses
615 system.cpu0.dcache.WriteReq_misses::total 2642039 # number of WriteReq misses
616 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 748095 # number of SoftPFReq misses
617 system.cpu0.dcache.SoftPFReq_misses::total 748095 # number of SoftPFReq misses
618 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 774634 # number of WriteLineReq misses
619 system.cpu0.dcache.WriteLineReq_misses::total 774634 # number of WriteLineReq misses
620 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 182353 # number of LoadLockedReq misses
621 system.cpu0.dcache.LoadLockedReq_misses::total 182353 # number of LoadLockedReq misses
622 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209431 # number of StoreCondReq misses
623 system.cpu0.dcache.StoreCondReq_misses::total 209431 # number of StoreCondReq misses
624 system.cpu0.dcache.demand_misses::cpu0.data 6418276 # number of demand (read+write) misses
625 system.cpu0.dcache.demand_misses::total 6418276 # number of demand (read+write) misses
626 system.cpu0.dcache.overall_misses::cpu0.data 7166371 # number of overall misses
627 system.cpu0.dcache.overall_misses::total 7166371 # number of overall misses
628 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 71342778500 # number of ReadReq miss cycles
629 system.cpu0.dcache.ReadReq_miss_latency::total 71342778500 # number of ReadReq miss cycles
630 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67996340500 # number of WriteReq miss cycles
631 system.cpu0.dcache.WriteReq_miss_latency::total 67996340500 # number of WriteReq miss cycles
632 system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46419090000 # number of WriteLineReq miss cycles
633 system.cpu0.dcache.WriteLineReq_miss_latency::total 46419090000 # number of WriteLineReq miss cycles
634 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3111811500 # number of LoadLockedReq miss cycles
635 system.cpu0.dcache.LoadLockedReq_miss_latency::total 3111811500 # number of LoadLockedReq miss cycles
636 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5902963500 # number of StoreCondReq miss cycles
637 system.cpu0.dcache.StoreCondReq_miss_latency::total 5902963500 # number of StoreCondReq miss cycles
638 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7077000 # number of StoreCondFailReq miss cycles
639 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7077000 # number of StoreCondFailReq miss cycles
640 system.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000 # number of demand (read+write) miss cycles
641 system.cpu0.dcache.demand_miss_latency::total 139339119000 # number of demand (read+write) miss cycles
642 system.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000 # number of overall miss cycles
643 system.cpu0.dcache.overall_miss_latency::total 139339119000 # number of overall miss cycles
644 system.cpu0.dcache.ReadReq_accesses::cpu0.data 90576928 # number of ReadReq accesses(hits+misses)
645 system.cpu0.dcache.ReadReq_accesses::total 90576928 # number of ReadReq accesses(hits+misses)
646 system.cpu0.dcache.WriteReq_accesses::cpu0.data 80900714 # number of WriteReq accesses(hits+misses)
647 system.cpu0.dcache.WriteReq_accesses::total 80900714 # number of WriteReq accesses(hits+misses)
648 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1017013 # number of SoftPFReq accesses(hits+misses)
649 system.cpu0.dcache.SoftPFReq_accesses::total 1017013 # number of SoftPFReq accesses(hits+misses)
650 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 902577 # number of WriteLineReq accesses(hits+misses)
651 system.cpu0.dcache.WriteLineReq_accesses::total 902577 # number of WriteLineReq accesses(hits+misses)
652 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2153872 # number of LoadLockedReq accesses(hits+misses)
653 system.cpu0.dcache.LoadLockedReq_accesses::total 2153872 # number of LoadLockedReq accesses(hits+misses)
654 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2152433 # number of StoreCondReq accesses(hits+misses)
655 system.cpu0.dcache.StoreCondReq_accesses::total 2152433 # number of StoreCondReq accesses(hits+misses)
656 system.cpu0.dcache.demand_accesses::cpu0.data 171477642 # number of demand (read+write) accesses
657 system.cpu0.dcache.demand_accesses::total 171477642 # number of demand (read+write) accesses
658 system.cpu0.dcache.overall_accesses::cpu0.data 172494655 # number of overall (read+write) accesses
659 system.cpu0.dcache.overall_accesses::total 172494655 # number of overall (read+write) accesses
660 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041691 # miss rate for ReadReq accesses
661 system.cpu0.dcache.ReadReq_miss_rate::total 0.041691 # miss rate for ReadReq accesses
662 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032658 # miss rate for WriteReq accesses
663 system.cpu0.dcache.WriteReq_miss_rate::total 0.032658 # miss rate for WriteReq accesses
664 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.735581 # miss rate for SoftPFReq accesses
665 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.735581 # miss rate for SoftPFReq accesses
666 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858247 # miss rate for WriteLineReq accesses
667 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858247 # miss rate for WriteLineReq accesses
668 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084663 # miss rate for LoadLockedReq accesses
669 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084663 # miss rate for LoadLockedReq accesses
670 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097300 # miss rate for StoreCondReq accesses
671 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097300 # miss rate for StoreCondReq accesses
672 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037429 # miss rate for demand accesses
673 system.cpu0.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses
674 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041545 # miss rate for overall accesses
675 system.cpu0.dcache.overall_miss_rate::total 0.041545 # miss rate for overall accesses
676 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518 # average ReadReq miss latency
677 system.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518 # average ReadReq miss latency
678 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182 # average WriteReq miss latency
679 system.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182 # average WriteReq miss latency
680 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545 # average WriteLineReq miss latency
681 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545 # average WriteLineReq miss latency
682 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237 # average LoadLockedReq miss latency
683 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237 # average LoadLockedReq miss latency
684 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879 # average StoreCondReq miss latency
685 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879 # average StoreCondReq miss latency
686 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
687 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
688 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21709.742460 # average overall miss latency
689 system.cpu0.dcache.demand_avg_miss_latency::total 21709.742460 # average overall miss latency
690 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19443.469924 # average overall miss latency
691 system.cpu0.dcache.overall_avg_miss_latency::total 19443.469924 # average overall miss latency
692 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
693 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
694 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
695 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
696 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
697 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
698 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
699 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
700 system.cpu0.dcache.writebacks::writebacks 6140232 # number of writebacks
701 system.cpu0.dcache.writebacks::total 6140232 # number of writebacks
702 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 470815 # number of ReadReq MSHR hits
703 system.cpu0.dcache.ReadReq_mshr_hits::total 470815 # number of ReadReq MSHR hits
704 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1099674 # number of WriteReq MSHR hits
705 system.cpu0.dcache.WriteReq_mshr_hits::total 1099674 # number of WriteReq MSHR hits
706 system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 78 # number of WriteLineReq MSHR hits
707 system.cpu0.dcache.WriteLineReq_mshr_hits::total 78 # number of WriteLineReq MSHR hits
708 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45572 # number of LoadLockedReq MSHR hits
709 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45572 # number of LoadLockedReq MSHR hits
710 system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 53 # number of StoreCondReq MSHR hits
711 system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits
712 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1570489 # number of demand (read+write) MSHR hits
713 system.cpu0.dcache.demand_mshr_hits::total 1570489 # number of demand (read+write) MSHR hits
714 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1570489 # number of overall MSHR hits
715 system.cpu0.dcache.overall_mshr_hits::total 1570489 # number of overall MSHR hits
716 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3305422 # number of ReadReq MSHR misses
717 system.cpu0.dcache.ReadReq_mshr_misses::total 3305422 # number of ReadReq MSHR misses
718 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1542365 # number of WriteReq MSHR misses
719 system.cpu0.dcache.WriteReq_mshr_misses::total 1542365 # number of WriteReq MSHR misses
720 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 746538 # number of SoftPFReq MSHR misses
721 system.cpu0.dcache.SoftPFReq_mshr_misses::total 746538 # number of SoftPFReq MSHR misses
722 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 774556 # number of WriteLineReq MSHR misses
723 system.cpu0.dcache.WriteLineReq_mshr_misses::total 774556 # number of WriteLineReq MSHR misses
724 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136781 # number of LoadLockedReq MSHR misses
725 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136781 # number of LoadLockedReq MSHR misses
726 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209378 # number of StoreCondReq MSHR misses
727 system.cpu0.dcache.StoreCondReq_mshr_misses::total 209378 # number of StoreCondReq MSHR misses
728 system.cpu0.dcache.demand_mshr_misses::cpu0.data 4847787 # number of demand (read+write) MSHR misses
729 system.cpu0.dcache.demand_mshr_misses::total 4847787 # number of demand (read+write) MSHR misses
730 system.cpu0.dcache.overall_mshr_misses::cpu0.data 5594325 # number of overall MSHR misses
731 system.cpu0.dcache.overall_mshr_misses::total 5594325 # number of overall MSHR misses
732 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable
733 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15086 # number of ReadReq MSHR uncacheable
734 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable
735 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15976 # number of WriteReq MSHR uncacheable
736 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses
737 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31062 # number of overall MSHR uncacheable misses
738 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56024435500 # number of ReadReq MSHR miss cycles
739 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56024435500 # number of ReadReq MSHR miss cycles
740 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39191815000 # number of WriteReq MSHR miss cycles
741 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39191815000 # number of WriteReq MSHR miss cycles
742 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 20208395000 # number of SoftPFReq MSHR miss cycles
743 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20208395000 # number of SoftPFReq MSHR miss cycles
744 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45637665000 # number of WriteLineReq MSHR miss cycles
745 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45637665000 # number of WriteLineReq MSHR miss cycles
746 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2043982500 # number of LoadLockedReq MSHR miss cycles
747 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2043982500 # number of LoadLockedReq MSHR miss cycles
748 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5689319500 # number of StoreCondReq MSHR miss cycles
749 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5689319500 # number of StoreCondReq MSHR miss cycles
750 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6788500 # number of StoreCondFailReq MSHR miss cycles
751 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6788500 # number of StoreCondFailReq MSHR miss cycles
752 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95216250500 # number of demand (read+write) MSHR miss cycles
753 system.cpu0.dcache.demand_mshr_miss_latency::total 95216250500 # number of demand (read+write) MSHR miss cycles
754 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115424645500 # number of overall MSHR miss cycles
755 system.cpu0.dcache.overall_mshr_miss_latency::total 115424645500 # number of overall MSHR miss cycles
756 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2640339000 # number of ReadReq MSHR uncacheable cycles
757 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2640339000 # number of ReadReq MSHR uncacheable cycles
758 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2747173500 # number of WriteReq MSHR uncacheable cycles
759 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2747173500 # number of WriteReq MSHR uncacheable cycles
760 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5387512500 # number of overall MSHR uncacheable cycles
761 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5387512500 # number of overall MSHR uncacheable cycles
762 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036493 # mshr miss rate for ReadReq accesses
763 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses
764 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019065 # mshr miss rate for WriteReq accesses
765 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019065 # mshr miss rate for WriteReq accesses
766 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.734050 # mshr miss rate for SoftPFReq accesses
767 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.734050 # mshr miss rate for SoftPFReq accesses
768 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858161 # mshr miss rate for WriteLineReq accesses
769 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858161 # mshr miss rate for WriteLineReq accesses
770 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063505 # mshr miss rate for LoadLockedReq accesses
771 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063505 # mshr miss rate for LoadLockedReq accesses
772 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097275 # mshr miss rate for StoreCondReq accesses
773 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097275 # mshr miss rate for StoreCondReq accesses
774 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028271 # mshr miss rate for demand accesses
775 system.cpu0.dcache.demand_mshr_miss_rate::total 0.028271 # mshr miss rate for demand accesses
776 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032432 # mshr miss rate for overall accesses
777 system.cpu0.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses
778 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530 # average ReadReq mshr miss latency
779 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16949.253530 # average ReadReq mshr miss latency
780 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25410.207701 # average WriteReq mshr miss latency
781 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25410.207701 # average WriteReq mshr miss latency
782 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27069.479384 # average SoftPFReq mshr miss latency
783 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384 # average SoftPFReq mshr miss latency
784 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746 # average WriteLineReq mshr miss latency
785 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58921.065746 # average WriteLineReq mshr miss latency
786 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14943.468026 # average LoadLockedReq mshr miss latency
787 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14943.468026 # average LoadLockedReq mshr miss latency
788 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27172.479917 # average StoreCondReq mshr miss latency
789 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27172.479917 # average StoreCondReq mshr miss latency
790 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
791 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
792 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19641.178645 # average overall mshr miss latency
793 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19641.178645 # average overall mshr miss latency
794 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20632.452619 # average overall mshr miss latency
795 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20632.452619 # average overall mshr miss latency
796 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175019.156834 # average ReadReq mshr uncacheable latency
797 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175019.156834 # average ReadReq mshr uncacheable latency
798 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171956.278167 # average WriteReq mshr uncacheable latency
799 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171956.278167 # average WriteReq mshr uncacheable latency
800 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173443.838130 # average overall mshr uncacheable latency
801 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173443.838130 # average overall mshr uncacheable latency
802 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
803 system.cpu0.icache.tags.replacements 9845680 # number of replacements
804 system.cpu0.icache.tags.tagsinuse 511.897003 # Cycle average of tags in use
805 system.cpu0.icache.tags.total_refs 254505668 # Total number of references to valid blocks.
806 system.cpu0.icache.tags.sampled_refs 9846192 # Sample count of references to valid blocks.
807 system.cpu0.icache.tags.avg_refs 25.848132 # Average number of references to valid blocks.
808 system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit.
809 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897003 # Average occupied blocks per requestor
810 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy
811 system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy
812 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
813 system.cpu0.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
814 system.cpu0.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
815 system.cpu0.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id
816 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
817 system.cpu0.icache.tags.tag_accesses 538549912 # Number of tag accesses
818 system.cpu0.icache.tags.data_accesses 538549912 # Number of data accesses
819 system.cpu0.icache.ReadReq_hits::cpu0.inst 254505668 # number of ReadReq hits
820 system.cpu0.icache.ReadReq_hits::total 254505668 # number of ReadReq hits
821 system.cpu0.icache.demand_hits::cpu0.inst 254505668 # number of demand (read+write) hits
822 system.cpu0.icache.demand_hits::total 254505668 # number of demand (read+write) hits
823 system.cpu0.icache.overall_hits::cpu0.inst 254505668 # number of overall hits
824 system.cpu0.icache.overall_hits::total 254505668 # number of overall hits
825 system.cpu0.icache.ReadReq_misses::cpu0.inst 9846192 # number of ReadReq misses
826 system.cpu0.icache.ReadReq_misses::total 9846192 # number of ReadReq misses
827 system.cpu0.icache.demand_misses::cpu0.inst 9846192 # number of demand (read+write) misses
828 system.cpu0.icache.demand_misses::total 9846192 # number of demand (read+write) misses
829 system.cpu0.icache.overall_misses::cpu0.inst 9846192 # number of overall misses
830 system.cpu0.icache.overall_misses::total 9846192 # number of overall misses
831 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104168962000 # number of ReadReq miss cycles
832 system.cpu0.icache.ReadReq_miss_latency::total 104168962000 # number of ReadReq miss cycles
833 system.cpu0.icache.demand_miss_latency::cpu0.inst 104168962000 # number of demand (read+write) miss cycles
834 system.cpu0.icache.demand_miss_latency::total 104168962000 # number of demand (read+write) miss cycles
835 system.cpu0.icache.overall_miss_latency::cpu0.inst 104168962000 # number of overall miss cycles
836 system.cpu0.icache.overall_miss_latency::total 104168962000 # number of overall miss cycles
837 system.cpu0.icache.ReadReq_accesses::cpu0.inst 264351860 # number of ReadReq accesses(hits+misses)
838 system.cpu0.icache.ReadReq_accesses::total 264351860 # number of ReadReq accesses(hits+misses)
839 system.cpu0.icache.demand_accesses::cpu0.inst 264351860 # number of demand (read+write) accesses
840 system.cpu0.icache.demand_accesses::total 264351860 # number of demand (read+write) accesses
841 system.cpu0.icache.overall_accesses::cpu0.inst 264351860 # number of overall (read+write) accesses
842 system.cpu0.icache.overall_accesses::total 264351860 # number of overall (read+write) accesses
843 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037247 # miss rate for ReadReq accesses
844 system.cpu0.icache.ReadReq_miss_rate::total 0.037247 # miss rate for ReadReq accesses
845 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037247 # miss rate for demand accesses
846 system.cpu0.icache.demand_miss_rate::total 0.037247 # miss rate for demand accesses
847 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037247 # miss rate for overall accesses
848 system.cpu0.icache.overall_miss_rate::total 0.037247 # miss rate for overall accesses
849 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10579.619207 # average ReadReq miss latency
850 system.cpu0.icache.ReadReq_avg_miss_latency::total 10579.619207 # average ReadReq miss latency
851 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency
852 system.cpu0.icache.demand_avg_miss_latency::total 10579.619207 # average overall miss latency
853 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency
854 system.cpu0.icache.overall_avg_miss_latency::total 10579.619207 # average overall miss latency
855 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
856 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
857 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
858 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
859 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
860 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
861 system.cpu0.icache.fast_writes 0 # number of fast writes performed
862 system.cpu0.icache.cache_copies 0 # number of cache copies performed
863 system.cpu0.icache.writebacks::writebacks 9845680 # number of writebacks
864 system.cpu0.icache.writebacks::total 9845680 # number of writebacks
865 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9846192 # number of ReadReq MSHR misses
866 system.cpu0.icache.ReadReq_mshr_misses::total 9846192 # number of ReadReq MSHR misses
867 system.cpu0.icache.demand_mshr_misses::cpu0.inst 9846192 # number of demand (read+write) MSHR misses
868 system.cpu0.icache.demand_mshr_misses::total 9846192 # number of demand (read+write) MSHR misses
869 system.cpu0.icache.overall_mshr_misses::cpu0.inst 9846192 # number of overall MSHR misses
870 system.cpu0.icache.overall_mshr_misses::total 9846192 # number of overall MSHR misses
871 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
872 system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
873 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
874 system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
875 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99245866000 # number of ReadReq MSHR miss cycles
876 system.cpu0.icache.ReadReq_mshr_miss_latency::total 99245866000 # number of ReadReq MSHR miss cycles
877 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99245866000 # number of demand (read+write) MSHR miss cycles
878 system.cpu0.icache.demand_mshr_miss_latency::total 99245866000 # number of demand (read+write) MSHR miss cycles
879 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99245866000 # number of overall MSHR miss cycles
880 system.cpu0.icache.overall_mshr_miss_latency::total 99245866000 # number of overall MSHR miss cycles
881 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles
882 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles
883 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles
884 system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles
885 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for ReadReq accesses
886 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037247 # mshr miss rate for ReadReq accesses
887 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for demand accesses
888 system.cpu0.icache.demand_mshr_miss_rate::total 0.037247 # mshr miss rate for demand accesses
889 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for overall accesses
890 system.cpu0.icache.overall_mshr_miss_rate::total 0.037247 # mshr miss rate for overall accesses
891 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average ReadReq mshr miss latency
892 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10079.619207 # average ReadReq mshr miss latency
893 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency
894 system.cpu0.icache.demand_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency
895 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency
896 system.cpu0.icache.overall_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency
897 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency
898 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency
899 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
900 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
901 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
902 system.cpu0.l2cache.prefetcher.num_hwpf_issued 8550248 # number of hwpf issued
903 system.cpu0.l2cache.prefetcher.pfIdentified 8550537 # number of prefetch candidates identified
904 system.cpu0.l2cache.prefetcher.pfBufferHit 256 # number of redundant prefetches already in prefetch queue
905 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
906 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
907 system.cpu0.l2cache.prefetcher.pfSpanPage 1111887 # number of prefetches not generated due to page crossing
908 system.cpu0.l2cache.tags.replacements 3055162 # number of replacements
909 system.cpu0.l2cache.tags.tagsinuse 16188.315469 # Cycle average of tags in use
910 system.cpu0.l2cache.tags.total_refs 24712613 # Total number of references to valid blocks.
911 system.cpu0.l2cache.tags.sampled_refs 3070855 # Sample count of references to valid blocks.
912 system.cpu0.l2cache.tags.avg_refs 8.047470 # Average number of references to valid blocks.
913 system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit.
914 system.cpu0.l2cache.tags.occ_blocks::writebacks 15276.749771 # Average occupied blocks per requestor
915 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.374129 # Average occupied blocks per requestor
916 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.193370 # Average occupied blocks per requestor
917 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 786.998198 # Average occupied blocks per requestor
918 system.cpu0.l2cache.tags.occ_percent::writebacks 0.932419 # Average percentage of cache occupancy
919 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003868 # Average percentage of cache occupancy
920 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003735 # Average percentage of cache occupancy
921 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048035 # Average percentage of cache occupancy
922 system.cpu0.l2cache.tags.occ_percent::total 0.988056 # Average percentage of cache occupancy
923 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1100 # Occupied blocks per task id
924 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
925 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14511 # Occupied blocks per task id
926 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
927 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id
928 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 849 # Occupied blocks per task id
929 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id
930 system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
931 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id
932 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id
933 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
934 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id
935 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5451 # Occupied blocks per task id
936 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id
937 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id
938 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067139 # Percentage of cache occupancy per task id
939 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
940 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885681 # Percentage of cache occupancy per task id
941 system.cpu0.l2cache.tags.tag_accesses 539634613 # Number of tag accesses
942 system.cpu0.l2cache.tags.data_accesses 539634613 # Number of data accesses
943 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 571667 # number of ReadReq hits
944 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182910 # number of ReadReq hits
945 system.cpu0.l2cache.ReadReq_hits::total 754577 # number of ReadReq hits
946 system.cpu0.l2cache.WritebackDirty_hits::writebacks 4024953 # number of WritebackDirty hits
947 system.cpu0.l2cache.WritebackDirty_hits::total 4024953 # number of WritebackDirty hits
948 system.cpu0.l2cache.WritebackClean_hits::writebacks 11958375 # number of WritebackClean hits
949 system.cpu0.l2cache.WritebackClean_hits::total 11958375 # number of WritebackClean hits
950 system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 880 # number of UpgradeReq hits
951 system.cpu0.l2cache.UpgradeReq_hits::total 880 # number of UpgradeReq hits
952 system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits
953 system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
954 system.cpu0.l2cache.ReadExReq_hits::cpu0.data 964239 # number of ReadExReq hits
955 system.cpu0.l2cache.ReadExReq_hits::total 964239 # number of ReadExReq hits
956 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9075218 # number of ReadCleanReq hits
957 system.cpu0.l2cache.ReadCleanReq_hits::total 9075218 # number of ReadCleanReq hits
958 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3054625 # number of ReadSharedReq hits
959 system.cpu0.l2cache.ReadSharedReq_hits::total 3054625 # number of ReadSharedReq hits
960 system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195729 # number of InvalidateReq hits
961 system.cpu0.l2cache.InvalidateReq_hits::total 195729 # number of InvalidateReq hits
962 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 571667 # number of demand (read+write) hits
963 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182910 # number of demand (read+write) hits
964 system.cpu0.l2cache.demand_hits::cpu0.inst 9075218 # number of demand (read+write) hits
965 system.cpu0.l2cache.demand_hits::cpu0.data 4018864 # number of demand (read+write) hits
966 system.cpu0.l2cache.demand_hits::total 13848659 # number of demand (read+write) hits
967 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 571667 # number of overall hits
968 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182910 # number of overall hits
969 system.cpu0.l2cache.overall_hits::cpu0.inst 9075218 # number of overall hits
970 system.cpu0.l2cache.overall_hits::cpu0.data 4018864 # number of overall hits
971 system.cpu0.l2cache.overall_hits::total 13848659 # number of overall hits
972 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14134 # number of ReadReq misses
973 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10093 # number of ReadReq misses
974 system.cpu0.l2cache.ReadReq_misses::total 24227 # number of ReadReq misses
975 system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
976 system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
977 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 274802 # number of UpgradeReq misses
978 system.cpu0.l2cache.UpgradeReq_misses::total 274802 # number of UpgradeReq misses
979 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 209364 # number of SCUpgradeReq misses
980 system.cpu0.l2cache.SCUpgradeReq_misses::total 209364 # number of SCUpgradeReq misses
981 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses
982 system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses
983 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 311346 # number of ReadExReq misses
984 system.cpu0.l2cache.ReadExReq_misses::total 311346 # number of ReadExReq misses
985 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 770973 # number of ReadCleanReq misses
986 system.cpu0.l2cache.ReadCleanReq_misses::total 770973 # number of ReadCleanReq misses
987 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1133829 # number of ReadSharedReq misses
988 system.cpu0.l2cache.ReadSharedReq_misses::total 1133829 # number of ReadSharedReq misses
989 system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 576566 # number of InvalidateReq misses
990 system.cpu0.l2cache.InvalidateReq_misses::total 576566 # number of InvalidateReq misses
991 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14134 # number of demand (read+write) misses
992 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10093 # number of demand (read+write) misses
993 system.cpu0.l2cache.demand_misses::cpu0.inst 770973 # number of demand (read+write) misses
994 system.cpu0.l2cache.demand_misses::cpu0.data 1445175 # number of demand (read+write) misses
995 system.cpu0.l2cache.demand_misses::total 2240375 # number of demand (read+write) misses
996 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14134 # number of overall misses
997 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10093 # number of overall misses
998 system.cpu0.l2cache.overall_misses::cpu0.inst 770973 # number of overall misses
999 system.cpu0.l2cache.overall_misses::cpu0.data 1445175 # number of overall misses
1000 system.cpu0.l2cache.overall_misses::total 2240375 # number of overall misses
1001 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 807748500 # number of ReadReq miss cycles
1002 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 660476500 # number of ReadReq miss cycles
1003 system.cpu0.l2cache.ReadReq_miss_latency::total 1468225000 # number of ReadReq miss cycles
1004 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3585176500 # number of UpgradeReq miss cycles
1005 system.cpu0.l2cache.UpgradeReq_miss_latency::total 3585176500 # number of UpgradeReq miss cycles
1006 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2077487000 # number of SCUpgradeReq miss cycles
1007 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2077487000 # number of SCUpgradeReq miss cycles
1008 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6654497 # number of SCUpgradeFailReq miss cycles
1009 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6654497 # number of SCUpgradeFailReq miss cycles
1010 system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 20598931500 # number of ReadExReq miss cycles
1011 system.cpu0.l2cache.ReadExReq_miss_latency::total 20598931500 # number of ReadExReq miss cycles
1012 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29674847500 # number of ReadCleanReq miss cycles
1013 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29674847500 # number of ReadCleanReq miss cycles
1014 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 51821822989 # number of ReadSharedReq miss cycles
1015 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 51821822989 # number of ReadSharedReq miss cycles
1016 system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 441045000 # number of InvalidateReq miss cycles
1017 system.cpu0.l2cache.InvalidateReq_miss_latency::total 441045000 # number of InvalidateReq miss cycles
1018 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 807748500 # number of demand (read+write) miss cycles
1019 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 660476500 # number of demand (read+write) miss cycles
1020 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29674847500 # number of demand (read+write) miss cycles
1021 system.cpu0.l2cache.demand_miss_latency::cpu0.data 72420754489 # number of demand (read+write) miss cycles
1022 system.cpu0.l2cache.demand_miss_latency::total 103563826989 # number of demand (read+write) miss cycles
1023 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 807748500 # number of overall miss cycles
1024 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 660476500 # number of overall miss cycles
1025 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29674847500 # number of overall miss cycles
1026 system.cpu0.l2cache.overall_miss_latency::cpu0.data 72420754489 # number of overall miss cycles
1027 system.cpu0.l2cache.overall_miss_latency::total 103563826989 # number of overall miss cycles
1028 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 585801 # number of ReadReq accesses(hits+misses)
1029 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 193003 # number of ReadReq accesses(hits+misses)
1030 system.cpu0.l2cache.ReadReq_accesses::total 778804 # number of ReadReq accesses(hits+misses)
1031 system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4024954 # number of WritebackDirty accesses(hits+misses)
1032 system.cpu0.l2cache.WritebackDirty_accesses::total 4024954 # number of WritebackDirty accesses(hits+misses)
1033 system.cpu0.l2cache.WritebackClean_accesses::writebacks 11958375 # number of WritebackClean accesses(hits+misses)
1034 system.cpu0.l2cache.WritebackClean_accesses::total 11958375 # number of WritebackClean accesses(hits+misses)
1035 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 275682 # number of UpgradeReq accesses(hits+misses)
1036 system.cpu0.l2cache.UpgradeReq_accesses::total 275682 # number of UpgradeReq accesses(hits+misses)
1037 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209367 # number of SCUpgradeReq accesses(hits+misses)
1038 system.cpu0.l2cache.SCUpgradeReq_accesses::total 209367 # number of SCUpgradeReq accesses(hits+misses)
1039 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses)
1040 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses)
1041 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1275585 # number of ReadExReq accesses(hits+misses)
1042 system.cpu0.l2cache.ReadExReq_accesses::total 1275585 # number of ReadExReq accesses(hits+misses)
1043 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9846191 # number of ReadCleanReq accesses(hits+misses)
1044 system.cpu0.l2cache.ReadCleanReq_accesses::total 9846191 # number of ReadCleanReq accesses(hits+misses)
1045 system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4188454 # number of ReadSharedReq accesses(hits+misses)
1046 system.cpu0.l2cache.ReadSharedReq_accesses::total 4188454 # number of ReadSharedReq accesses(hits+misses)
1047 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 772295 # number of InvalidateReq accesses(hits+misses)
1048 system.cpu0.l2cache.InvalidateReq_accesses::total 772295 # number of InvalidateReq accesses(hits+misses)
1049 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 585801 # number of demand (read+write) accesses
1050 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 193003 # number of demand (read+write) accesses
1051 system.cpu0.l2cache.demand_accesses::cpu0.inst 9846191 # number of demand (read+write) accesses
1052 system.cpu0.l2cache.demand_accesses::cpu0.data 5464039 # number of demand (read+write) accesses
1053 system.cpu0.l2cache.demand_accesses::total 16089034 # number of demand (read+write) accesses
1054 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 585801 # number of overall (read+write) accesses
1055 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 193003 # number of overall (read+write) accesses
1056 system.cpu0.l2cache.overall_accesses::cpu0.inst 9846191 # number of overall (read+write) accesses
1057 system.cpu0.l2cache.overall_accesses::cpu0.data 5464039 # number of overall (read+write) accesses
1058 system.cpu0.l2cache.overall_accesses::total 16089034 # number of overall (read+write) accesses
1059 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for ReadReq accesses
1060 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052295 # miss rate for ReadReq accesses
1061 system.cpu0.l2cache.ReadReq_miss_rate::total 0.031108 # miss rate for ReadReq accesses
1062 system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
1063 system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
1064 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996808 # miss rate for UpgradeReq accesses
1065 system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996808 # miss rate for UpgradeReq accesses
1066 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999986 # miss rate for SCUpgradeReq accesses
1067 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999986 # miss rate for SCUpgradeReq accesses
1068 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1069 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1070 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.244081 # miss rate for ReadExReq accesses
1071 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.244081 # miss rate for ReadExReq accesses
1072 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.078302 # miss rate for ReadCleanReq accesses
1073 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.078302 # miss rate for ReadCleanReq accesses
1074 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270703 # miss rate for ReadSharedReq accesses
1075 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270703 # miss rate for ReadSharedReq accesses
1076 system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.746562 # miss rate for InvalidateReq accesses
1077 system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.746562 # miss rate for InvalidateReq accesses
1078 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for demand accesses
1079 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052295 # miss rate for demand accesses
1080 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078302 # miss rate for demand accesses
1081 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264488 # miss rate for demand accesses
1082 system.cpu0.l2cache.demand_miss_rate::total 0.139249 # miss rate for demand accesses
1083 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for overall accesses
1084 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052295 # miss rate for overall accesses
1085 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078302 # miss rate for overall accesses
1086 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264488 # miss rate for overall accesses
1087 system.cpu0.l2cache.overall_miss_rate::total 0.139249 # miss rate for overall accesses
1088 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average ReadReq miss latency
1089 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 65439.066680 # average ReadReq miss latency
1090 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 60602.839807 # average ReadReq miss latency
1091 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13046.398862 # average UpgradeReq miss latency
1092 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13046.398862 # average UpgradeReq miss latency
1093 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9922.847290 # average SCUpgradeReq miss latency
1094 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9922.847290 # average SCUpgradeReq miss latency
1095 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 604954.272727 # average SCUpgradeFailReq miss latency
1096 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 604954.272727 # average SCUpgradeFailReq miss latency
1097 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66160.899771 # average ReadExReq miss latency
1098 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66160.899771 # average ReadExReq miss latency
1099 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38490.125465 # average ReadCleanReq miss latency
1100 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38490.125465 # average ReadCleanReq miss latency
1101 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45705.148650 # average ReadSharedReq miss latency
1102 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45705.148650 # average ReadSharedReq miss latency
1103 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 764.951454 # average InvalidateReq miss latency
1104 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 764.951454 # average InvalidateReq miss latency
1105 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average overall miss latency
1106 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 65439.066680 # average overall miss latency
1107 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38490.125465 # average overall miss latency
1108 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50112.100257 # average overall miss latency
1109 system.cpu0.l2cache.demand_avg_miss_latency::total 46226.112588 # average overall miss latency
1110 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average overall miss latency
1111 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 65439.066680 # average overall miss latency
1112 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38490.125465 # average overall miss latency
1113 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50112.100257 # average overall miss latency
1114 system.cpu0.l2cache.overall_avg_miss_latency::total 46226.112588 # average overall miss latency
1115 system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1116 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1117 system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1118 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1119 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1120 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1121 system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1122 system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1123 system.cpu0.l2cache.writebacks::writebacks 1773255 # number of writebacks
1124 system.cpu0.l2cache.writebacks::total 1773255 # number of writebacks
1125 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
1126 system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1127 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9828 # number of ReadExReq MSHR hits
1128 system.cpu0.l2cache.ReadExReq_mshr_hits::total 9828 # number of ReadExReq MSHR hits
1129 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
1130 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1131 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1247 # number of ReadSharedReq MSHR hits
1132 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1247 # number of ReadSharedReq MSHR hits
1133 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
1134 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
1135 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11075 # number of demand (read+write) MSHR hits
1136 system.cpu0.l2cache.demand_mshr_hits::total 11087 # number of demand (read+write) MSHR hits
1137 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
1138 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
1139 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11075 # number of overall MSHR hits
1140 system.cpu0.l2cache.overall_mshr_hits::total 11087 # number of overall MSHR hits
1141 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14134 # number of ReadReq MSHR misses
1142 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10090 # number of ReadReq MSHR misses
1143 system.cpu0.l2cache.ReadReq_mshr_misses::total 24224 # number of ReadReq MSHR misses
1144 system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
1145 system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
1146 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 890747 # number of HardPFReq MSHR misses
1147 system.cpu0.l2cache.HardPFReq_mshr_misses::total 890747 # number of HardPFReq MSHR misses
1148 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 274802 # number of UpgradeReq MSHR misses
1149 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 274802 # number of UpgradeReq MSHR misses
1150 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 209364 # number of SCUpgradeReq MSHR misses
1151 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 209364 # number of SCUpgradeReq MSHR misses
1152 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses
1153 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses
1154 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 301518 # number of ReadExReq MSHR misses
1155 system.cpu0.l2cache.ReadExReq_mshr_misses::total 301518 # number of ReadExReq MSHR misses
1156 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 770964 # number of ReadCleanReq MSHR misses
1157 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 770964 # number of ReadCleanReq MSHR misses
1158 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1132582 # number of ReadSharedReq MSHR misses
1159 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1132582 # number of ReadSharedReq MSHR misses
1160 system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 576566 # number of InvalidateReq MSHR misses
1161 system.cpu0.l2cache.InvalidateReq_mshr_misses::total 576566 # number of InvalidateReq MSHR misses
1162 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 14134 # number of demand (read+write) MSHR misses
1163 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10090 # number of demand (read+write) MSHR misses
1164 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 770964 # number of demand (read+write) MSHR misses
1165 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1434100 # number of demand (read+write) MSHR misses
1166 system.cpu0.l2cache.demand_mshr_misses::total 2229288 # number of demand (read+write) MSHR misses
1167 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14134 # number of overall MSHR misses
1168 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10090 # number of overall MSHR misses
1169 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 770964 # number of overall MSHR misses
1170 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1434100 # number of overall MSHR misses
1171 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 890747 # number of overall MSHR misses
1172 system.cpu0.l2cache.overall_mshr_misses::total 3120035 # number of overall MSHR misses
1173 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
1174 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable
1175 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 67395 # number of ReadReq MSHR uncacheable
1176 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable
1177 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15976 # number of WriteReq MSHR uncacheable
1178 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
1179 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses
1180 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 83371 # number of overall MSHR uncacheable misses
1181 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of ReadReq MSHR miss cycles
1182 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 599881000 # number of ReadReq MSHR miss cycles
1183 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1322825500 # number of ReadReq MSHR miss cycles
1184 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 54995868600 # number of HardPFReq MSHR miss cycles
1185 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 54995868600 # number of HardPFReq MSHR miss cycles
1186 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 8223573999 # number of UpgradeReq MSHR miss cycles
1187 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 8223573999 # number of UpgradeReq MSHR miss cycles
1188 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4114812496 # number of SCUpgradeReq MSHR miss cycles
1189 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4114812496 # number of SCUpgradeReq MSHR miss cycles
1190 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6132497 # number of SCUpgradeFailReq MSHR miss cycles
1191 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6132497 # number of SCUpgradeFailReq MSHR miss cycles
1192 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17351951000 # number of ReadExReq MSHR miss cycles
1193 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17351951000 # number of ReadExReq MSHR miss cycles
1194 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25048433000 # number of ReadCleanReq MSHR miss cycles
1195 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25048433000 # number of ReadCleanReq MSHR miss cycles
1196 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 44909041489 # number of ReadSharedReq MSHR miss cycles
1197 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 44909041489 # number of ReadSharedReq MSHR miss cycles
1198 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39596476000 # number of InvalidateReq MSHR miss cycles
1199 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39596476000 # number of InvalidateReq MSHR miss cycles
1200 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of demand (read+write) MSHR miss cycles
1201 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 599881000 # number of demand (read+write) MSHR miss cycles
1202 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25048433000 # number of demand (read+write) MSHR miss cycles
1203 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 62260992489 # number of demand (read+write) MSHR miss cycles
1204 system.cpu0.l2cache.demand_mshr_miss_latency::total 88632250989 # number of demand (read+write) MSHR miss cycles
1205 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of overall MSHR miss cycles
1206 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 599881000 # number of overall MSHR miss cycles
1207 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25048433000 # number of overall MSHR miss cycles
1208 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 62260992489 # number of overall MSHR miss cycles
1209 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 54995868600 # number of overall MSHR miss cycles
1210 system.cpu0.l2cache.overall_mshr_miss_latency::total 143628119589 # number of overall MSHR miss cycles
1211 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles
1212 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2519460500 # number of ReadReq MSHR uncacheable cycles
1213 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9515615500 # number of ReadReq MSHR uncacheable cycles
1214 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2627296000 # number of WriteReq MSHR uncacheable cycles
1215 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2627296000 # number of WriteReq MSHR uncacheable cycles
1216 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles
1217 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5146756500 # number of overall MSHR uncacheable cycles
1218 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12142911500 # number of overall MSHR uncacheable cycles
1219 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for ReadReq accesses
1220 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for ReadReq accesses
1221 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031104 # mshr miss rate for ReadReq accesses
1222 system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
1223 system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
1224 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1225 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1226 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996808 # mshr miss rate for UpgradeReq accesses
1227 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996808 # mshr miss rate for UpgradeReq accesses
1228 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999986 # mshr miss rate for SCUpgradeReq accesses
1229 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999986 # mshr miss rate for SCUpgradeReq accesses
1230 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1231 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1232 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses
1233 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses
1234 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses
1235 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses
1236 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses
1237 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses
1238 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses
1239 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses
1240 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses
1241 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses
1242 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses
1243 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses
1244 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses
1245 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses
1246 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses
1247 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses
1248 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses
1249 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1250 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses
1251 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency
1252 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency
1253 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency
1254 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency
1255 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency
1256 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency
1257 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency
1258 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency
1259 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency
1260 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency
1261 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency
1262 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency
1263 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency
1264 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency
1265 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency
1266 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency
1267 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency
1268 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency
1269 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency
1270 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency
1271 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency
1272 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency
1273 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency
1274 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency
1275 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency
1276 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency
1277 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency
1278 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency
1279 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency
1280 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency
1281 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
1282 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency
1283 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency
1284 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency
1285 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency
1286 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
1287 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency
1288 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency
1289 system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1290 system.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter.
1291 system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1292 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1293 system.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter.
1294 system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1295 system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1296 system.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution
1297 system.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution
1298 system.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution
1299 system.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution
1300 system.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution
1301 system.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution
1302 system.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution
1303 system.cpu0.toL2Bus.trans_dist::HardPFReq 1153411 # Transaction distribution
1304 system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
1305 system.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution
1306 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution
1307 system.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution
1308 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution
1309 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
1310 system.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution
1311 system.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution
1312 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution
1313 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution
1314 system.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution
1315 system.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution
1316 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes)
1317 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes)
1318 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes)
1319 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes)
1320 system.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes)
1321 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes)
1322 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes)
1323 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes)
1324 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes)
1325 system.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes)
1326 system.cpu0.toL2Bus.snoops 8071764 # Total snoops (count)
1327 system.cpu0.toL2Bus.snoop_fanout::samples 25329170 # Request fanout histogram
1328 system.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram
1329 system.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram
1330 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1331 system.cpu0.toL2Bus.snoop_fanout::0 22579237 89.14% 89.14% # Request fanout histogram
1332 system.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram
1333 system.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram
1334 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1335 system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1336 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1337 system.cpu0.toL2Bus.snoop_fanout::total 25329170 # Request fanout histogram
1338 system.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks)
1339 system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1340 system.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks)
1341 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1342 system.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks)
1343 system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1344 system.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks)
1345 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1346 system.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks)
1347 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1348 system.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks)
1349 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1350 system.cpu1.branchPred.lookups 143060728 # Number of BP lookups
1351 system.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted
1352 system.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect
1353 system.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups
1354 system.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits
1355 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1356 system.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage
1357 system.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target.
1358 system.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions.
1359 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1360 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1361 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1362 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1363 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1364 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1365 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1366 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1367 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1368 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1369 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1370 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1371 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1372 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1373 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1374 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1375 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1376 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1377 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1378 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1379 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1380 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1381 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1382 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1383 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1384 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1385 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1386 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1387 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1388 system.cpu1.dtb.walker.walks 316205 # Table walker walks requested
1389 system.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors
1390 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate
1391 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate
1392 system.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency
1393 system.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1394 system.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency
1395 system.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency
1396 system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency
1397 system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency
1398 system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency
1399 system.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency
1400 system.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency
1401 system.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency
1402 system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency
1403 system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency
1404 system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
1405 system.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency
1406 system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
1407 system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
1408 system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1409 system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1410 system.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency
1411 system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution
1412 system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution
1413 system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution
1414 system.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated
1415 system.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated
1416 system.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated
1417 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst
1418 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1419 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst
1420 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst
1421 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1422 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst
1423 system.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst
1424 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1425 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1426 system.cpu1.dtb.read_hits 90416501 # DTB read hits
1427 system.cpu1.dtb.read_misses 263668 # DTB read misses
1428 system.cpu1.dtb.write_hits 78865175 # DTB write hits
1429 system.cpu1.dtb.write_misses 52537 # DTB write misses
1430 system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1431 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1432 system.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
1433 system.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
1434 system.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB
1435 system.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions
1436 system.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch
1437 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1438 system.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions
1439 system.cpu1.dtb.read_accesses 90680169 # DTB read accesses
1440 system.cpu1.dtb.write_accesses 78917712 # DTB write accesses
1441 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1442 system.cpu1.dtb.hits 169281676 # DTB hits
1443 system.cpu1.dtb.misses 316205 # DTB misses
1444 system.cpu1.dtb.accesses 169597881 # DTB accesses
1445 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1446 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1447 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1448 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1449 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1450 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1451 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1452 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1453 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1454 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1455 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1456 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1457 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1458 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1459 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1460 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1461 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1462 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1463 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1464 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1465 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1466 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1467 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1468 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1469 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1470 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1471 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1472 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1473 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1474 system.cpu1.itb.walker.walks 61623 # Table walker walks requested
1475 system.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors
1476 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate
1477 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate
1478 system.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency
1479 system.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1480 system.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency
1481 system.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency
1482 system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency
1483 system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency
1484 system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency
1485 system.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency
1486 system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency
1487 system.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency
1488 system.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency
1489 system.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency
1490 system.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency
1491 system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
1492 system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1493 system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1494 system.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency
1495 system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution
1496 system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution
1497 system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution
1498 system.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated
1499 system.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated
1500 system.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated
1501 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1502 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst
1503 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst
1504 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1505 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst
1506 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst
1507 system.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst
1508 system.cpu1.itb.inst_hits 255703249 # ITB inst hits
1509 system.cpu1.itb.inst_misses 61623 # ITB inst misses
1510 system.cpu1.itb.read_hits 0 # DTB read hits
1511 system.cpu1.itb.read_misses 0 # DTB read misses
1512 system.cpu1.itb.write_hits 0 # DTB write hits
1513 system.cpu1.itb.write_misses 0 # DTB write misses
1514 system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1515 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1516 system.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
1517 system.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
1518 system.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB
1519 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1520 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1521 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1522 system.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions
1523 system.cpu1.itb.read_accesses 0 # DTB read accesses
1524 system.cpu1.itb.write_accesses 0 # DTB write accesses
1525 system.cpu1.itb.inst_accesses 255764872 # ITB inst accesses
1526 system.cpu1.itb.hits 255703249 # DTB hits
1527 system.cpu1.itb.misses 61623 # DTB misses
1528 system.cpu1.itb.accesses 255764872 # DTB accesses
1529 system.cpu1.numCycles 1013399126 # number of cpu cycles simulated
1530 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1531 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1532 system.cpu1.committedInsts 463476016 # Number of instructions committed
1533 system.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed
1534 system.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit
1535 system.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching
1536 system.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1537 system.cpu1.cpi 2.186519 # CPI: cycles per instruction
1538 system.cpu1.ipc 0.457348 # IPC: instructions per cycle
1539 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1540 system.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed
1541 system.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked
1542 system.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped
1543 system.cpu1.dcache.tags.replacements 5640902 # number of replacements
1544 system.cpu1.dcache.tags.tagsinuse 433.747661 # Cycle average of tags in use
1545 system.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks.
1546 system.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks.
1547 system.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks.
1548 system.cpu1.dcache.tags.warmup_cycle 8381463375500 # Cycle when the warmup percentage was hit.
1549 system.cpu1.dcache.tags.occ_blocks::cpu1.data 433.747661 # Average occupied blocks per requestor
1550 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.847163 # Average percentage of cache occupancy
1551 system.cpu1.dcache.tags.occ_percent::total 0.847163 # Average percentage of cache occupancy
1552 system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1553 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
1554 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
1555 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
1556 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1557 system.cpu1.dcache.tags.tag_accesses 341448433 # Number of tag accesses
1558 system.cpu1.dcache.tags.data_accesses 341448433 # Number of data accesses
1559 system.cpu1.dcache.ReadReq_hits::cpu1.data 82699161 # number of ReadReq hits
1560 system.cpu1.dcache.ReadReq_hits::total 82699161 # number of ReadReq hits
1561 system.cpu1.dcache.WriteReq_hits::cpu1.data 73240702 # number of WriteReq hits
1562 system.cpu1.dcache.WriteReq_hits::total 73240702 # number of WriteReq hits
1563 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 257576 # number of SoftPFReq hits
1564 system.cpu1.dcache.SoftPFReq_hits::total 257576 # number of SoftPFReq hits
1565 system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197387 # number of WriteLineReq hits
1566 system.cpu1.dcache.WriteLineReq_hits::total 197387 # number of WriteLineReq hits
1567 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1901357 # number of LoadLockedReq hits
1568 system.cpu1.dcache.LoadLockedReq_hits::total 1901357 # number of LoadLockedReq hits
1569 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1855769 # number of StoreCondReq hits
1570 system.cpu1.dcache.StoreCondReq_hits::total 1855769 # number of StoreCondReq hits
1571 system.cpu1.dcache.demand_hits::cpu1.data 155939863 # number of demand (read+write) hits
1572 system.cpu1.dcache.demand_hits::total 155939863 # number of demand (read+write) hits
1573 system.cpu1.dcache.overall_hits::cpu1.data 156197439 # number of overall hits
1574 system.cpu1.dcache.overall_hits::total 156197439 # number of overall hits
1575 system.cpu1.dcache.ReadReq_misses::cpu1.data 3585243 # number of ReadReq misses
1576 system.cpu1.dcache.ReadReq_misses::total 3585243 # number of ReadReq misses
1577 system.cpu1.dcache.WriteReq_misses::cpu1.data 2523734 # number of WriteReq misses
1578 system.cpu1.dcache.WriteReq_misses::total 2523734 # number of WriteReq misses
1579 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 738365 # number of SoftPFReq misses
1580 system.cpu1.dcache.SoftPFReq_misses::total 738365 # number of SoftPFReq misses
1581 system.cpu1.dcache.WriteLineReq_misses::cpu1.data 486988 # number of WriteLineReq misses
1582 system.cpu1.dcache.WriteLineReq_misses::total 486988 # number of WriteLineReq misses
1583 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162310 # number of LoadLockedReq misses
1584 system.cpu1.dcache.LoadLockedReq_misses::total 162310 # number of LoadLockedReq misses
1585 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206438 # number of StoreCondReq misses
1586 system.cpu1.dcache.StoreCondReq_misses::total 206438 # number of StoreCondReq misses
1587 system.cpu1.dcache.demand_misses::cpu1.data 6108977 # number of demand (read+write) misses
1588 system.cpu1.dcache.demand_misses::total 6108977 # number of demand (read+write) misses
1589 system.cpu1.dcache.overall_misses::cpu1.data 6847342 # number of overall misses
1590 system.cpu1.dcache.overall_misses::total 6847342 # number of overall misses
1591 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60530715500 # number of ReadReq miss cycles
1592 system.cpu1.dcache.ReadReq_miss_latency::total 60530715500 # number of ReadReq miss cycles
1593 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 58663605500 # number of WriteReq miss cycles
1594 system.cpu1.dcache.WriteReq_miss_latency::total 58663605500 # number of WriteReq miss cycles
1595 system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22007902000 # number of WriteLineReq miss cycles
1596 system.cpu1.dcache.WriteLineReq_miss_latency::total 22007902000 # number of WriteLineReq miss cycles
1597 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2738446000 # number of LoadLockedReq miss cycles
1598 system.cpu1.dcache.LoadLockedReq_miss_latency::total 2738446000 # number of LoadLockedReq miss cycles
1599 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5741911000 # number of StoreCondReq miss cycles
1600 system.cpu1.dcache.StoreCondReq_miss_latency::total 5741911000 # number of StoreCondReq miss cycles
1601 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7112000 # number of StoreCondFailReq miss cycles
1602 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7112000 # number of StoreCondFailReq miss cycles
1603 system.cpu1.dcache.demand_miss_latency::cpu1.data 119194321000 # number of demand (read+write) miss cycles
1604 system.cpu1.dcache.demand_miss_latency::total 119194321000 # number of demand (read+write) miss cycles
1605 system.cpu1.dcache.overall_miss_latency::cpu1.data 119194321000 # number of overall miss cycles
1606 system.cpu1.dcache.overall_miss_latency::total 119194321000 # number of overall miss cycles
1607 system.cpu1.dcache.ReadReq_accesses::cpu1.data 86284404 # number of ReadReq accesses(hits+misses)
1608 system.cpu1.dcache.ReadReq_accesses::total 86284404 # number of ReadReq accesses(hits+misses)
1609 system.cpu1.dcache.WriteReq_accesses::cpu1.data 75764436 # number of WriteReq accesses(hits+misses)
1610 system.cpu1.dcache.WriteReq_accesses::total 75764436 # number of WriteReq accesses(hits+misses)
1611 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 995941 # number of SoftPFReq accesses(hits+misses)
1612 system.cpu1.dcache.SoftPFReq_accesses::total 995941 # number of SoftPFReq accesses(hits+misses)
1613 system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 684375 # number of WriteLineReq accesses(hits+misses)
1614 system.cpu1.dcache.WriteLineReq_accesses::total 684375 # number of WriteLineReq accesses(hits+misses)
1615 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2063667 # number of LoadLockedReq accesses(hits+misses)
1616 system.cpu1.dcache.LoadLockedReq_accesses::total 2063667 # number of LoadLockedReq accesses(hits+misses)
1617 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2062207 # number of StoreCondReq accesses(hits+misses)
1618 system.cpu1.dcache.StoreCondReq_accesses::total 2062207 # number of StoreCondReq accesses(hits+misses)
1619 system.cpu1.dcache.demand_accesses::cpu1.data 162048840 # number of demand (read+write) accesses
1620 system.cpu1.dcache.demand_accesses::total 162048840 # number of demand (read+write) accesses
1621 system.cpu1.dcache.overall_accesses::cpu1.data 163044781 # number of overall (read+write) accesses
1622 system.cpu1.dcache.overall_accesses::total 163044781 # number of overall (read+write) accesses
1623 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041551 # miss rate for ReadReq accesses
1624 system.cpu1.dcache.ReadReq_miss_rate::total 0.041551 # miss rate for ReadReq accesses
1625 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033310 # miss rate for WriteReq accesses
1626 system.cpu1.dcache.WriteReq_miss_rate::total 0.033310 # miss rate for WriteReq accesses
1627 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.741374 # miss rate for SoftPFReq accesses
1628 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.741374 # miss rate for SoftPFReq accesses
1629 system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.711581 # miss rate for WriteLineReq accesses
1630 system.cpu1.dcache.WriteLineReq_miss_rate::total 0.711581 # miss rate for WriteLineReq accesses
1631 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078651 # miss rate for LoadLockedReq accesses
1632 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078651 # miss rate for LoadLockedReq accesses
1633 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100105 # miss rate for StoreCondReq accesses
1634 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100105 # miss rate for StoreCondReq accesses
1635 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037698 # miss rate for demand accesses
1636 system.cpu1.dcache.demand_miss_rate::total 0.037698 # miss rate for demand accesses
1637 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041997 # miss rate for overall accesses
1638 system.cpu1.dcache.overall_miss_rate::total 0.041997 # miss rate for overall accesses
1639 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079 # average ReadReq miss latency
1640 system.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079 # average ReadReq miss latency
1641 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692 # average WriteReq miss latency
1642 system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency
1643 system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency
1644 system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45191.877418 # average WriteLineReq miss latency
1645 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16871.702298 # average LoadLockedReq miss latency
1646 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16871.702298 # average LoadLockedReq miss latency
1647 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27814.215406 # average StoreCondReq miss latency
1648 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406 # average StoreCondReq miss latency
1649 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1650 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1651 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969 # average overall miss latency
1652 system.cpu1.dcache.demand_avg_miss_latency::total 19511.338969 # average overall miss latency
1653 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377 # average overall miss latency
1654 system.cpu1.dcache.overall_avg_miss_latency::total 17407.385377 # average overall miss latency
1655 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1656 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1657 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1658 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1659 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1660 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1661 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1662 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1663 system.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks
1664 system.cpu1.dcache.writebacks::total 5640935 # number of writebacks
1665 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits
1666 system.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits
1667 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits
1668 system.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits
1669 system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits
1670 system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits
1671 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits
1672 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits
1673 system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits
1674 system.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # number of StoreCondReq MSHR hits
1675 system.cpu1.dcache.demand_mshr_hits::cpu1.data 1472775 # number of demand (read+write) MSHR hits
1676 system.cpu1.dcache.demand_mshr_hits::total 1472775 # number of demand (read+write) MSHR hits
1677 system.cpu1.dcache.overall_mshr_hits::cpu1.data 1472775 # number of overall MSHR hits
1678 system.cpu1.dcache.overall_mshr_hits::total 1472775 # number of overall MSHR hits
1679 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3155827 # number of ReadReq MSHR misses
1680 system.cpu1.dcache.ReadReq_mshr_misses::total 3155827 # number of ReadReq MSHR misses
1681 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1480375 # number of WriteReq MSHR misses
1682 system.cpu1.dcache.WriteReq_mshr_misses::total 1480375 # number of WriteReq MSHR misses
1683 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 738082 # number of SoftPFReq MSHR misses
1684 system.cpu1.dcache.SoftPFReq_mshr_misses::total 738082 # number of SoftPFReq MSHR misses
1685 system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 486914 # number of WriteLineReq MSHR misses
1686 system.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses
1687 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses
1688 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses
1689 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses
1690 system.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses
1691 system.cpu1.dcache.demand_mshr_misses::cpu1.data 4636202 # number of demand (read+write) MSHR misses
1692 system.cpu1.dcache.demand_mshr_misses::total 4636202 # number of demand (read+write) MSHR misses
1693 system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374284 # number of overall MSHR misses
1694 system.cpu1.dcache.overall_mshr_misses::total 5374284 # number of overall MSHR misses
1695 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable
1696 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23242 # number of ReadReq MSHR uncacheable
1697 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable
1698 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable
1699 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses
1700 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 45478 # number of overall MSHR uncacheable misses
1701 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 47412877500 # number of ReadReq MSHR miss cycles
1702 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles
1703 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles
1704 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles
1705 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 19660408500 # number of SoftPFReq MSHR miss cycles
1706 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles
1707 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles
1708 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles
1709 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1774236500 # number of LoadLockedReq MSHR miss cycles
1710 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles
1711 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5529988500 # number of StoreCondReq MSHR miss cycles
1712 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles
1713 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles
1714 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles
1715 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82159871500 # number of demand (read+write) MSHR miss cycles
1716 system.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles
1717 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000 # number of overall MSHR miss cycles
1718 system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles
1719 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles
1720 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4292810500 # number of ReadReq MSHR uncacheable cycles
1721 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles
1722 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4172773000 # number of WriteReq MSHR uncacheable cycles
1723 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8465583500 # number of overall MSHR uncacheable cycles
1724 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles
1725 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses
1726 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses
1727 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses
1728 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses
1729 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses
1730 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses
1731 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses
1732 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses
1733 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses
1734 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses
1735 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses
1736 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses
1737 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028610 # mshr miss rate for demand accesses
1738 system.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses
1739 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses
1740 system.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses
1741 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency
1742 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency
1743 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency
1744 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency
1745 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency
1746 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency
1747 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency
1748 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency
1749 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency
1750 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency
1751 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency
1752 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency
1753 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1754 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1755 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414 # average overall mshr miss latency
1756 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414 # average overall mshr miss latency
1757 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668 # average overall mshr miss latency
1758 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668 # average overall mshr miss latency
1759 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635 # average ReadReq mshr uncacheable latency
1760 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635 # average ReadReq mshr uncacheable latency
1761 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769 # average WriteReq mshr uncacheable latency
1762 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769 # average WriteReq mshr uncacheable latency
1763 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259 # average overall mshr uncacheable latency
1764 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259 # average overall mshr uncacheable latency
1765 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1766 system.cpu1.icache.tags.replacements 9253909 # number of replacements
1767 system.cpu1.icache.tags.tagsinuse 506.772073 # Cycle average of tags in use
1768 system.cpu1.icache.tags.total_refs 246217857 # Total number of references to valid blocks.
1769 system.cpu1.icache.tags.sampled_refs 9254421 # Sample count of references to valid blocks.
1770 system.cpu1.icache.tags.avg_refs 26.605431 # Average number of references to valid blocks.
1771 system.cpu1.icache.tags.warmup_cycle 8381293063000 # Cycle when the warmup percentage was hit.
1772 system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.772073 # Average occupied blocks per requestor
1773 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989789 # Average percentage of cache occupancy
1774 system.cpu1.icache.tags.occ_percent::total 0.989789 # Average percentage of cache occupancy
1775 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1776 system.cpu1.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
1777 system.cpu1.icache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
1778 system.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
1779 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1780 system.cpu1.icache.tags.tag_accesses 520199009 # Number of tag accesses
1781 system.cpu1.icache.tags.data_accesses 520199009 # Number of data accesses
1782 system.cpu1.icache.ReadReq_hits::cpu1.inst 246217857 # number of ReadReq hits
1783 system.cpu1.icache.ReadReq_hits::total 246217857 # number of ReadReq hits
1784 system.cpu1.icache.demand_hits::cpu1.inst 246217857 # number of demand (read+write) hits
1785 system.cpu1.icache.demand_hits::total 246217857 # number of demand (read+write) hits
1786 system.cpu1.icache.overall_hits::cpu1.inst 246217857 # number of overall hits
1787 system.cpu1.icache.overall_hits::total 246217857 # number of overall hits
1788 system.cpu1.icache.ReadReq_misses::cpu1.inst 9254432 # number of ReadReq misses
1789 system.cpu1.icache.ReadReq_misses::total 9254432 # number of ReadReq misses
1790 system.cpu1.icache.demand_misses::cpu1.inst 9254432 # number of demand (read+write) misses
1791 system.cpu1.icache.demand_misses::total 9254432 # number of demand (read+write) misses
1792 system.cpu1.icache.overall_misses::cpu1.inst 9254432 # number of overall misses
1793 system.cpu1.icache.overall_misses::total 9254432 # number of overall misses
1794 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 97819295000 # number of ReadReq miss cycles
1795 system.cpu1.icache.ReadReq_miss_latency::total 97819295000 # number of ReadReq miss cycles
1796 system.cpu1.icache.demand_miss_latency::cpu1.inst 97819295000 # number of demand (read+write) miss cycles
1797 system.cpu1.icache.demand_miss_latency::total 97819295000 # number of demand (read+write) miss cycles
1798 system.cpu1.icache.overall_miss_latency::cpu1.inst 97819295000 # number of overall miss cycles
1799 system.cpu1.icache.overall_miss_latency::total 97819295000 # number of overall miss cycles
1800 system.cpu1.icache.ReadReq_accesses::cpu1.inst 255472289 # number of ReadReq accesses(hits+misses)
1801 system.cpu1.icache.ReadReq_accesses::total 255472289 # number of ReadReq accesses(hits+misses)
1802 system.cpu1.icache.demand_accesses::cpu1.inst 255472289 # number of demand (read+write) accesses
1803 system.cpu1.icache.demand_accesses::total 255472289 # number of demand (read+write) accesses
1804 system.cpu1.icache.overall_accesses::cpu1.inst 255472289 # number of overall (read+write) accesses
1805 system.cpu1.icache.overall_accesses::total 255472289 # number of overall (read+write) accesses
1806 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036225 # miss rate for ReadReq accesses
1807 system.cpu1.icache.ReadReq_miss_rate::total 0.036225 # miss rate for ReadReq accesses
1808 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036225 # miss rate for demand accesses
1809 system.cpu1.icache.demand_miss_rate::total 0.036225 # miss rate for demand accesses
1810 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036225 # miss rate for overall accesses
1811 system.cpu1.icache.overall_miss_rate::total 0.036225 # miss rate for overall accesses
1812 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10569.994463 # average ReadReq miss latency
1813 system.cpu1.icache.ReadReq_avg_miss_latency::total 10569.994463 # average ReadReq miss latency
1814 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency
1815 system.cpu1.icache.demand_avg_miss_latency::total 10569.994463 # average overall miss latency
1816 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency
1817 system.cpu1.icache.overall_avg_miss_latency::total 10569.994463 # average overall miss latency
1818 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1819 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1820 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1821 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1822 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1823 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1824 system.cpu1.icache.fast_writes 0 # number of fast writes performed
1825 system.cpu1.icache.cache_copies 0 # number of cache copies performed
1826 system.cpu1.icache.writebacks::writebacks 9253909 # number of writebacks
1827 system.cpu1.icache.writebacks::total 9253909 # number of writebacks
1828 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9254432 # number of ReadReq MSHR misses
1829 system.cpu1.icache.ReadReq_mshr_misses::total 9254432 # number of ReadReq MSHR misses
1830 system.cpu1.icache.demand_mshr_misses::cpu1.inst 9254432 # number of demand (read+write) MSHR misses
1831 system.cpu1.icache.demand_mshr_misses::total 9254432 # number of demand (read+write) MSHR misses
1832 system.cpu1.icache.overall_mshr_misses::cpu1.inst 9254432 # number of overall MSHR misses
1833 system.cpu1.icache.overall_mshr_misses::total 9254432 # number of overall MSHR misses
1834 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
1835 system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
1836 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
1837 system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
1838 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 93192079500 # number of ReadReq MSHR miss cycles
1839 system.cpu1.icache.ReadReq_mshr_miss_latency::total 93192079500 # number of ReadReq MSHR miss cycles
1840 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 93192079500 # number of demand (read+write) MSHR miss cycles
1841 system.cpu1.icache.demand_mshr_miss_latency::total 93192079500 # number of demand (read+write) MSHR miss cycles
1842 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 93192079500 # number of overall MSHR miss cycles
1843 system.cpu1.icache.overall_mshr_miss_latency::total 93192079500 # number of overall MSHR miss cycles
1844 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles
1845 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles
1846 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles
1847 system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles
1848 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for ReadReq accesses
1849 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036225 # mshr miss rate for ReadReq accesses
1850 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for demand accesses
1851 system.cpu1.icache.demand_mshr_miss_rate::total 0.036225 # mshr miss rate for demand accesses
1852 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for overall accesses
1853 system.cpu1.icache.overall_mshr_miss_rate::total 0.036225 # mshr miss rate for overall accesses
1854 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average ReadReq mshr miss latency
1855 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517 # average ReadReq mshr miss latency
1856 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency
1857 system.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency
1858 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency
1859 system.cpu1.icache.overall_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency
1860 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency
1861 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency
1862 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency
1863 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency
1864 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1865 system.cpu1.l2cache.prefetcher.num_hwpf_issued 7972481 # number of hwpf issued
1866 system.cpu1.l2cache.prefetcher.pfIdentified 7973767 # number of prefetch candidates identified
1867 system.cpu1.l2cache.prefetcher.pfBufferHit 1132 # number of redundant prefetches already in prefetch queue
1868 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1869 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1870 system.cpu1.l2cache.prefetcher.pfSpanPage 946401 # number of prefetches not generated due to page crossing
1871 system.cpu1.l2cache.tags.replacements 2682833 # number of replacements
1872 system.cpu1.l2cache.tags.tagsinuse 13443.137658 # Cycle average of tags in use
1873 system.cpu1.l2cache.tags.total_refs 23351564 # Total number of references to valid blocks.
1874 system.cpu1.l2cache.tags.sampled_refs 2698948 # Sample count of references to valid blocks.
1875 system.cpu1.l2cache.tags.avg_refs 8.652099 # Average number of references to valid blocks.
1876 system.cpu1.l2cache.tags.warmup_cycle 10051011039000 # Cycle when the warmup percentage was hit.
1877 system.cpu1.l2cache.tags.occ_blocks::writebacks 12664.163497 # Average occupied blocks per requestor
1878 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 64.427658 # Average occupied blocks per requestor
1879 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 52.788670 # Average occupied blocks per requestor
1880 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 661.757834 # Average occupied blocks per requestor
1881 system.cpu1.l2cache.tags.occ_percent::writebacks 0.772959 # Average percentage of cache occupancy
1882 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003932 # Average percentage of cache occupancy
1883 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003222 # Average percentage of cache occupancy
1884 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040390 # Average percentage of cache occupancy
1885 system.cpu1.l2cache.tags.occ_percent::total 0.820504 # Average percentage of cache occupancy
1886 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1261 # Occupied blocks per task id
1887 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
1888 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id
1889 system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id
1890 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id
1891 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 798 # Occupied blocks per task id
1892 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id
1893 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id
1894 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id
1895 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
1896 system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
1897 system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1053 # Occupied blocks per task id
1898 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5404 # Occupied blocks per task id
1899 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7290 # Occupied blocks per task id
1900 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 973 # Occupied blocks per task id
1901 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076965 # Percentage of cache occupancy per task id
1902 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id
1903 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id
1904 system.cpu1.l2cache.tags.tag_accesses 504035480 # Number of tag accesses
1905 system.cpu1.l2cache.tags.data_accesses 504035480 # Number of data accesses
1906 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 619167 # number of ReadReq hits
1907 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157082 # number of ReadReq hits
1908 system.cpu1.l2cache.ReadReq_hits::total 776249 # number of ReadReq hits
1909 system.cpu1.l2cache.WritebackDirty_hits::writebacks 3580112 # number of WritebackDirty hits
1910 system.cpu1.l2cache.WritebackDirty_hits::total 3580112 # number of WritebackDirty hits
1911 system.cpu1.l2cache.WritebackClean_hits::writebacks 11312106 # number of WritebackClean hits
1912 system.cpu1.l2cache.WritebackClean_hits::total 11312106 # number of WritebackClean hits
1913 system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 786 # number of UpgradeReq hits
1914 system.cpu1.l2cache.UpgradeReq_hits::total 786 # number of UpgradeReq hits
1915 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 968681 # number of ReadExReq hits
1916 system.cpu1.l2cache.ReadExReq_hits::total 968681 # number of ReadExReq hits
1917 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8504758 # number of ReadCleanReq hits
1918 system.cpu1.l2cache.ReadCleanReq_hits::total 8504758 # number of ReadCleanReq hits
1919 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2930307 # number of ReadSharedReq hits
1920 system.cpu1.l2cache.ReadSharedReq_hits::total 2930307 # number of ReadSharedReq hits
1921 system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167226 # number of InvalidateReq hits
1922 system.cpu1.l2cache.InvalidateReq_hits::total 167226 # number of InvalidateReq hits
1923 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 619167 # number of demand (read+write) hits
1924 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 157082 # number of demand (read+write) hits
1925 system.cpu1.l2cache.demand_hits::cpu1.inst 8504758 # number of demand (read+write) hits
1926 system.cpu1.l2cache.demand_hits::cpu1.data 3898988 # number of demand (read+write) hits
1927 system.cpu1.l2cache.demand_hits::total 13179995 # number of demand (read+write) hits
1928 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 619167 # number of overall hits
1929 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 157082 # number of overall hits
1930 system.cpu1.l2cache.overall_hits::cpu1.inst 8504758 # number of overall hits
1931 system.cpu1.l2cache.overall_hits::cpu1.data 3898988 # number of overall hits
1932 system.cpu1.l2cache.overall_hits::total 13179995 # number of overall hits
1933 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13008 # number of ReadReq misses
1934 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8398 # number of ReadReq misses
1935 system.cpu1.l2cache.ReadReq_misses::total 21406 # number of ReadReq misses
1936 system.cpu1.l2cache.WritebackDirty_misses::writebacks 3 # number of WritebackDirty misses
1937 system.cpu1.l2cache.WritebackDirty_misses::total 3 # number of WritebackDirty misses
1938 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 242430 # number of UpgradeReq misses
1939 system.cpu1.l2cache.UpgradeReq_misses::total 242430 # number of UpgradeReq misses
1940 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 206357 # number of SCUpgradeReq misses
1941 system.cpu1.l2cache.SCUpgradeReq_misses::total 206357 # number of SCUpgradeReq misses
1942 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses
1943 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
1944 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 271269 # number of ReadExReq misses
1945 system.cpu1.l2cache.ReadExReq_misses::total 271269 # number of ReadExReq misses
1946 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 749674 # number of ReadCleanReq misses
1947 system.cpu1.l2cache.ReadCleanReq_misses::total 749674 # number of ReadCleanReq misses
1948 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1083420 # number of ReadSharedReq misses
1949 system.cpu1.l2cache.ReadSharedReq_misses::total 1083420 # number of ReadSharedReq misses
1950 system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 317410 # number of InvalidateReq misses
1951 system.cpu1.l2cache.InvalidateReq_misses::total 317410 # number of InvalidateReq misses
1952 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13008 # number of demand (read+write) misses
1953 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8398 # number of demand (read+write) misses
1954 system.cpu1.l2cache.demand_misses::cpu1.inst 749674 # number of demand (read+write) misses
1955 system.cpu1.l2cache.demand_misses::cpu1.data 1354689 # number of demand (read+write) misses
1956 system.cpu1.l2cache.demand_misses::total 2125769 # number of demand (read+write) misses
1957 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13008 # number of overall misses
1958 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8398 # number of overall misses
1959 system.cpu1.l2cache.overall_misses::cpu1.inst 749674 # number of overall misses
1960 system.cpu1.l2cache.overall_misses::cpu1.data 1354689 # number of overall misses
1961 system.cpu1.l2cache.overall_misses::total 2125769 # number of overall misses
1962 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 644553000 # number of ReadReq miss cycles
1963 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 465440500 # number of ReadReq miss cycles
1964 system.cpu1.l2cache.ReadReq_miss_latency::total 1109993500 # number of ReadReq miss cycles
1965 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3394976000 # number of UpgradeReq miss cycles
1966 system.cpu1.l2cache.UpgradeReq_miss_latency::total 3394976000 # number of UpgradeReq miss cycles
1967 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2059365000 # number of SCUpgradeReq miss cycles
1968 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2059365000 # number of SCUpgradeReq miss cycles
1969 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6608499 # number of SCUpgradeFailReq miss cycles
1970 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6608499 # number of SCUpgradeFailReq miss cycles
1971 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 17354243497 # number of ReadExReq miss cycles
1972 system.cpu1.l2cache.ReadExReq_miss_latency::total 17354243497 # number of ReadExReq miss cycles
1973 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 27964377000 # number of ReadCleanReq miss cycles
1974 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 27964377000 # number of ReadCleanReq miss cycles
1975 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43468216991 # number of ReadSharedReq miss cycles
1976 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 43468216991 # number of ReadSharedReq miss cycles
1977 system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 430263500 # number of InvalidateReq miss cycles
1978 system.cpu1.l2cache.InvalidateReq_miss_latency::total 430263500 # number of InvalidateReq miss cycles
1979 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 644553000 # number of demand (read+write) miss cycles
1980 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 465440500 # number of demand (read+write) miss cycles
1981 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 27964377000 # number of demand (read+write) miss cycles
1982 system.cpu1.l2cache.demand_miss_latency::cpu1.data 60822460488 # number of demand (read+write) miss cycles
1983 system.cpu1.l2cache.demand_miss_latency::total 89896830988 # number of demand (read+write) miss cycles
1984 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 644553000 # number of overall miss cycles
1985 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 465440500 # number of overall miss cycles
1986 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 27964377000 # number of overall miss cycles
1987 system.cpu1.l2cache.overall_miss_latency::cpu1.data 60822460488 # number of overall miss cycles
1988 system.cpu1.l2cache.overall_miss_latency::total 89896830988 # number of overall miss cycles
1989 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 632175 # number of ReadReq accesses(hits+misses)
1990 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165480 # number of ReadReq accesses(hits+misses)
1991 system.cpu1.l2cache.ReadReq_accesses::total 797655 # number of ReadReq accesses(hits+misses)
1992 system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3580115 # number of WritebackDirty accesses(hits+misses)
1993 system.cpu1.l2cache.WritebackDirty_accesses::total 3580115 # number of WritebackDirty accesses(hits+misses)
1994 system.cpu1.l2cache.WritebackClean_accesses::writebacks 11312106 # number of WritebackClean accesses(hits+misses)
1995 system.cpu1.l2cache.WritebackClean_accesses::total 11312106 # number of WritebackClean accesses(hits+misses)
1996 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 243216 # number of UpgradeReq accesses(hits+misses)
1997 system.cpu1.l2cache.UpgradeReq_accesses::total 243216 # number of UpgradeReq accesses(hits+misses)
1998 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 206357 # number of SCUpgradeReq accesses(hits+misses)
1999 system.cpu1.l2cache.SCUpgradeReq_accesses::total 206357 # number of SCUpgradeReq accesses(hits+misses)
2000 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
2001 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
2002 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1239950 # number of ReadExReq accesses(hits+misses)
2003 system.cpu1.l2cache.ReadExReq_accesses::total 1239950 # number of ReadExReq accesses(hits+misses)
2004 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9254432 # number of ReadCleanReq accesses(hits+misses)
2005 system.cpu1.l2cache.ReadCleanReq_accesses::total 9254432 # number of ReadCleanReq accesses(hits+misses)
2006 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4013727 # number of ReadSharedReq accesses(hits+misses)
2007 system.cpu1.l2cache.ReadSharedReq_accesses::total 4013727 # number of ReadSharedReq accesses(hits+misses)
2008 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 484636 # number of InvalidateReq accesses(hits+misses)
2009 system.cpu1.l2cache.InvalidateReq_accesses::total 484636 # number of InvalidateReq accesses(hits+misses)
2010 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 632175 # number of demand (read+write) accesses
2011 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165480 # number of demand (read+write) accesses
2012 system.cpu1.l2cache.demand_accesses::cpu1.inst 9254432 # number of demand (read+write) accesses
2013 system.cpu1.l2cache.demand_accesses::cpu1.data 5253677 # number of demand (read+write) accesses
2014 system.cpu1.l2cache.demand_accesses::total 15305764 # number of demand (read+write) accesses
2015 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 632175 # number of overall (read+write) accesses
2016 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165480 # number of overall (read+write) accesses
2017 system.cpu1.l2cache.overall_accesses::cpu1.inst 9254432 # number of overall (read+write) accesses
2018 system.cpu1.l2cache.overall_accesses::cpu1.data 5253677 # number of overall (read+write) accesses
2019 system.cpu1.l2cache.overall_accesses::total 15305764 # number of overall (read+write) accesses
2020 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for ReadReq accesses
2021 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050749 # miss rate for ReadReq accesses
2022 system.cpu1.l2cache.ReadReq_miss_rate::total 0.026836 # miss rate for ReadReq accesses
2023 system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
2024 system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
2025 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996768 # miss rate for UpgradeReq accesses
2026 system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996768 # miss rate for UpgradeReq accesses
2027 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2028 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2029 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2030 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2031 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.218774 # miss rate for ReadExReq accesses
2032 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.218774 # miss rate for ReadExReq accesses
2033 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081007 # miss rate for ReadCleanReq accesses
2034 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081007 # miss rate for ReadCleanReq accesses
2035 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.269929 # miss rate for ReadSharedReq accesses
2036 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.269929 # miss rate for ReadSharedReq accesses
2037 system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.654945 # miss rate for InvalidateReq accesses
2038 system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.654945 # miss rate for InvalidateReq accesses
2039 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for demand accesses
2040 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050749 # miss rate for demand accesses
2041 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081007 # miss rate for demand accesses
2042 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.257855 # miss rate for demand accesses
2043 system.cpu1.l2cache.demand_miss_rate::total 0.138887 # miss rate for demand accesses
2044 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for overall accesses
2045 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050749 # miss rate for overall accesses
2046 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081007 # miss rate for overall accesses
2047 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.257855 # miss rate for overall accesses
2048 system.cpu1.l2cache.overall_miss_rate::total 0.138887 # miss rate for overall accesses
2049 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average ReadReq miss latency
2050 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 55422.779233 # average ReadReq miss latency
2051 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 51854.316547 # average ReadReq miss latency
2052 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14003.943406 # average UpgradeReq miss latency
2053 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14003.943406 # average UpgradeReq miss latency
2054 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9979.622693 # average SCUpgradeReq miss latency
2055 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9979.622693 # average SCUpgradeReq miss latency
2056 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 734277.666667 # average SCUpgradeFailReq miss latency
2057 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 734277.666667 # average SCUpgradeFailReq miss latency
2058 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 63974.296720 # average ReadExReq miss latency
2059 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 63974.296720 # average ReadExReq miss latency
2060 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37302.049958 # average ReadCleanReq miss latency
2061 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37302.049958 # average ReadCleanReq miss latency
2062 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40121.298288 # average ReadSharedReq miss latency
2063 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40121.298288 # average ReadSharedReq miss latency
2064 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1355.544879 # average InvalidateReq miss latency
2065 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1355.544879 # average InvalidateReq miss latency
2066 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average overall miss latency
2067 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 55422.779233 # average overall miss latency
2068 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37302.049958 # average overall miss latency
2069 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44897.729655 # average overall miss latency
2070 system.cpu1.l2cache.demand_avg_miss_latency::total 42289.087379 # average overall miss latency
2071 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average overall miss latency
2072 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 55422.779233 # average overall miss latency
2073 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37302.049958 # average overall miss latency
2074 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44897.729655 # average overall miss latency
2075 system.cpu1.l2cache.overall_avg_miss_latency::total 42289.087379 # average overall miss latency
2076 system.cpu1.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
2077 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2078 system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
2079 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2080 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
2081 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2082 system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2083 system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2084 system.cpu1.l2cache.writebacks::writebacks 1388382 # number of writebacks
2085 system.cpu1.l2cache.writebacks::total 1388382 # number of writebacks
2086 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
2087 system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
2088 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 13745 # number of ReadExReq MSHR hits
2089 system.cpu1.l2cache.ReadExReq_mshr_hits::total 13745 # number of ReadExReq MSHR hits
2090 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 8 # number of ReadCleanReq MSHR hits
2091 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
2092 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1083 # number of ReadSharedReq MSHR hits
2093 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1083 # number of ReadSharedReq MSHR hits
2094 system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits
2095 system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
2096 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
2097 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
2098 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 14828 # number of demand (read+write) MSHR hits
2099 system.cpu1.l2cache.demand_mshr_hits::total 14837 # number of demand (read+write) MSHR hits
2100 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
2101 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
2102 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 14828 # number of overall MSHR hits
2103 system.cpu1.l2cache.overall_mshr_hits::total 14837 # number of overall MSHR hits
2104 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13008 # number of ReadReq MSHR misses
2105 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8397 # number of ReadReq MSHR misses
2106 system.cpu1.l2cache.ReadReq_mshr_misses::total 21405 # number of ReadReq MSHR misses
2107 system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 3 # number of WritebackDirty MSHR misses
2108 system.cpu1.l2cache.WritebackDirty_mshr_misses::total 3 # number of WritebackDirty MSHR misses
2109 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 882624 # number of HardPFReq MSHR misses
2110 system.cpu1.l2cache.HardPFReq_mshr_misses::total 882624 # number of HardPFReq MSHR misses
2111 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 242430 # number of UpgradeReq MSHR misses
2112 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 242430 # number of UpgradeReq MSHR misses
2113 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 206357 # number of SCUpgradeReq MSHR misses
2114 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 206357 # number of SCUpgradeReq MSHR misses
2115 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses
2116 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
2117 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257524 # number of ReadExReq MSHR misses
2118 system.cpu1.l2cache.ReadExReq_mshr_misses::total 257524 # number of ReadExReq MSHR misses
2119 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 749666 # number of ReadCleanReq MSHR misses
2120 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 749666 # number of ReadCleanReq MSHR misses
2121 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1082337 # number of ReadSharedReq MSHR misses
2122 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1082337 # number of ReadSharedReq MSHR misses
2123 system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 317406 # number of InvalidateReq MSHR misses
2124 system.cpu1.l2cache.InvalidateReq_mshr_misses::total 317406 # number of InvalidateReq MSHR misses
2125 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13008 # number of demand (read+write) MSHR misses
2126 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8397 # number of demand (read+write) MSHR misses
2127 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 749666 # number of demand (read+write) MSHR misses
2128 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1339861 # number of demand (read+write) MSHR misses
2129 system.cpu1.l2cache.demand_mshr_misses::total 2110932 # number of demand (read+write) MSHR misses
2130 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13008 # number of overall MSHR misses
2131 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8397 # number of overall MSHR misses
2132 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 749666 # number of overall MSHR misses
2133 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1339861 # number of overall MSHR misses
2134 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 882624 # number of overall MSHR misses
2135 system.cpu1.l2cache.overall_mshr_misses::total 2993556 # number of overall MSHR misses
2136 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
2137 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable
2138 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23335 # number of ReadReq MSHR uncacheable
2139 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable
2140 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable
2141 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
2142 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses
2143 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 45571 # number of overall MSHR uncacheable misses
2144 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of ReadReq MSHR miss cycles
2145 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 415038000 # number of ReadReq MSHR miss cycles
2146 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 981543000 # number of ReadReq MSHR miss cycles
2147 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of HardPFReq MSHR miss cycles
2148 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 64551953809 # number of HardPFReq MSHR miss cycles
2149 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7440388995 # number of UpgradeReq MSHR miss cycles
2150 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7440388995 # number of UpgradeReq MSHR miss cycles
2151 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3978239996 # number of SCUpgradeReq MSHR miss cycles
2152 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3978239996 # number of SCUpgradeReq MSHR miss cycles
2153 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6134499 # number of SCUpgradeFailReq MSHR miss cycles
2154 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6134499 # number of SCUpgradeFailReq MSHR miss cycles
2155 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 13620219997 # number of ReadExReq MSHR miss cycles
2156 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 13620219997 # number of ReadExReq MSHR miss cycles
2157 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 23466170000 # number of ReadCleanReq MSHR miss cycles
2158 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 23466170000 # number of ReadCleanReq MSHR miss cycles
2159 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 36889013991 # number of ReadSharedReq MSHR miss cycles
2160 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 36889013991 # number of ReadSharedReq MSHR miss cycles
2161 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17653665500 # number of InvalidateReq MSHR miss cycles
2162 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17653665500 # number of InvalidateReq MSHR miss cycles
2163 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of demand (read+write) MSHR miss cycles
2164 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 415038000 # number of demand (read+write) MSHR miss cycles
2165 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 23466170000 # number of demand (read+write) MSHR miss cycles
2166 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 50509233988 # number of demand (read+write) MSHR miss cycles
2167 system.cpu1.l2cache.demand_mshr_miss_latency::total 74956946988 # number of demand (read+write) MSHR miss cycles
2168 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of overall MSHR miss cycles
2169 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 415038000 # number of overall MSHR miss cycles
2170 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 23466170000 # number of overall MSHR miss cycles
2171 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 50509233988 # number of overall MSHR miss cycles
2172 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of overall MSHR miss cycles
2173 system.cpu1.l2cache.overall_mshr_miss_latency::total 139508900797 # number of overall MSHR miss cycles
2174 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles
2175 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4106803500 # number of ReadReq MSHR uncacheable cycles
2176 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4119140500 # number of ReadReq MSHR uncacheable cycles
2177 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 4005950500 # number of WriteReq MSHR uncacheable cycles
2178 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 4005950500 # number of WriteReq MSHR uncacheable cycles
2179 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles
2180 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8112754000 # number of overall MSHR uncacheable cycles
2181 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8125091000 # number of overall MSHR uncacheable cycles
2182 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for ReadReq accesses
2183 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for ReadReq accesses
2184 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026835 # mshr miss rate for ReadReq accesses
2185 system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
2186 system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2187 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2188 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2189 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996768 # mshr miss rate for UpgradeReq accesses
2190 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996768 # mshr miss rate for UpgradeReq accesses
2191 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2192 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2193 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2194 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2195 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207689 # mshr miss rate for ReadExReq accesses
2196 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207689 # mshr miss rate for ReadExReq accesses
2197 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for ReadCleanReq accesses
2198 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081006 # mshr miss rate for ReadCleanReq accesses
2199 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.269659 # mshr miss rate for ReadSharedReq accesses
2200 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.269659 # mshr miss rate for ReadSharedReq accesses
2201 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.654937 # mshr miss rate for InvalidateReq accesses
2202 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.654937 # mshr miss rate for InvalidateReq accesses
2203 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for demand accesses
2204 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for demand accesses
2205 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for demand accesses
2206 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for demand accesses
2207 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.137917 # mshr miss rate for demand accesses
2208 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for overall accesses
2209 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for overall accesses
2210 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for overall accesses
2211 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for overall accesses
2212 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2213 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.195584 # mshr miss rate for overall accesses
2214 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average ReadReq mshr miss latency
2215 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average ReadReq mshr miss latency
2216 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45855.781359 # average ReadReq mshr miss latency
2217 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average HardPFReq mshr miss latency
2218 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 73136.413477 # average HardPFReq mshr miss latency
2219 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30690.875696 # average UpgradeReq mshr miss latency
2220 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696 # average UpgradeReq mshr miss latency
2221 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19278.434926 # average SCUpgradeReq mshr miss latency
2222 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19278.434926 # average SCUpgradeReq mshr miss latency
2223 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 681611 # average SCUpgradeFailReq mshr miss latency
2224 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 681611 # average SCUpgradeFailReq mshr miss latency
2225 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52889.128769 # average ReadExReq mshr miss latency
2226 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52889.128769 # average ReadExReq mshr miss latency
2227 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average ReadCleanReq mshr miss latency
2228 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31302.166565 # average ReadCleanReq mshr miss latency
2229 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167 # average ReadSharedReq mshr miss latency
2230 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167 # average ReadSharedReq mshr miss latency
2231 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661 # average InvalidateReq mshr miss latency
2232 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661 # average InvalidateReq mshr miss latency
2233 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency
2234 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency
2235 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency
2236 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency
2237 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910 # average overall mshr miss latency
2238 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency
2239 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency
2240 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency
2241 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency
2242 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average overall mshr miss latency
2243 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327 # average overall mshr miss latency
2244 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency
2245 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820 # average ReadReq mshr uncacheable latency
2246 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144 # average ReadReq mshr uncacheable latency
2247 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733 # average WriteReq mshr uncacheable latency
2248 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733 # average WriteReq mshr uncacheable latency
2249 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency
2250 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514 # average overall mshr uncacheable latency
2251 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency
2252 system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2253 system.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter.
2254 system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2255 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2256 system.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter.
2257 system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2258 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2259 system.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution
2260 system.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution
2261 system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
2262 system.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution
2263 system.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution
2264 system.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution
2265 system.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution
2266 system.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution
2267 system.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution
2268 system.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution
2269 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution
2270 system.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution
2271 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution
2272 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
2273 system.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution
2274 system.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution
2275 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution
2276 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution
2277 system.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution
2278 system.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution
2279 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes)
2280 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes)
2281 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes)
2282 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes)
2283 system.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes)
2284 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes)
2285 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes)
2286 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes)
2287 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes)
2288 system.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes)
2289 system.cpu1.toL2Bus.snoops 7537959 # Total snoops (count)
2290 system.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram
2291 system.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram
2292 system.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram
2293 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2294 system.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram
2295 system.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram
2296 system.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram
2297 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2298 system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2299 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2300 system.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram
2301 system.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks)
2302 system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2303 system.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks)
2304 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2305 system.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks)
2306 system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2307 system.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks)
2308 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2309 system.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks)
2310 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2311 system.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks)
2312 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2313 system.iobus.trans_dist::ReadReq 40434 # Transaction distribution
2314 system.iobus.trans_dist::ReadResp 40434 # Transaction distribution
2315 system.iobus.trans_dist::WriteReq 136979 # Transaction distribution
2316 system.iobus.trans_dist::WriteResp 136979 # Transaction distribution
2317 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes)
2318 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2319 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2320 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2321 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2322 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2323 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2324 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2325 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2326 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2327 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2328 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
2329 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2330 system.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes)
2331 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes)
2332 system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes)
2333 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2334 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2335 system.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes)
2336 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes)
2337 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2338 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2339 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2340 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2341 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2342 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2343 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2344 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2345 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2346 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2347 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
2348 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2349 system.iobus.pkt_size_system.bridge.master::total 156002 # Cumulative packet size per connected master and slave (bytes)
2350 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes)
2351 system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes)
2352 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2353 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2354 system.iobus.pkt_size::total 7513568 # Cumulative packet size per connected master and slave (bytes)
2355 system.iobus.reqLayer0.occupancy 47273505 # Layer occupancy (ticks)
2356 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2357 system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
2358 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2359 system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
2360 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2361 system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
2362 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2363 system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
2364 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2365 system.iobus.reqLayer10.occupancy 8500 # Layer occupancy (ticks)
2366 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2367 system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
2368 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2369 system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
2370 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2371 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
2372 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2373 system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
2374 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2375 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2376 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2377 system.iobus.reqLayer23.occupancy 26273501 # Layer occupancy (ticks)
2378 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2379 system.iobus.reqLayer24.occupancy 36398000 # Layer occupancy (ticks)
2380 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2381 system.iobus.reqLayer25.occupancy 568842992 # Layer occupancy (ticks)
2382 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2383 system.iobus.respLayer0.occupancy 92972000 # Layer occupancy (ticks)
2384 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2385 system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks)
2386 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2387 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2388 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2389 system.iocache.tags.replacements 115872 # number of replacements
2390 system.iocache.tags.tagsinuse 11.252872 # Cycle average of tags in use
2391 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2392 system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks.
2393 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2394 system.iocache.tags.warmup_cycle 9138217056000 # Cycle when the warmup percentage was hit.
2395 system.iocache.tags.occ_blocks::realview.ethernet 3.833219 # Average occupied blocks per requestor
2396 system.iocache.tags.occ_blocks::realview.ide 7.419652 # Average occupied blocks per requestor
2397 system.iocache.tags.occ_percent::realview.ethernet 0.239576 # Average percentage of cache occupancy
2398 system.iocache.tags.occ_percent::realview.ide 0.463728 # Average percentage of cache occupancy
2399 system.iocache.tags.occ_percent::total 0.703304 # Average percentage of cache occupancy
2400 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2401 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2402 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2403 system.iocache.tags.tag_accesses 1043376 # Number of tag accesses
2404 system.iocache.tags.data_accesses 1043376 # Number of data accesses
2405 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2406 system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses
2407 system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses
2408 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2409 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2410 system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
2411 system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2412 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2413 system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses
2414 system.iocache.demand_misses::total 8947 # number of demand (read+write) misses
2415 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2416 system.iocache.overall_misses::realview.ide 8907 # number of overall misses
2417 system.iocache.overall_misses::total 8947 # number of overall misses
2418 system.iocache.ReadReq_miss_latency::realview.ethernet 5277000 # number of ReadReq miss cycles
2419 system.iocache.ReadReq_miss_latency::realview.ide 1705079977 # number of ReadReq miss cycles
2420 system.iocache.ReadReq_miss_latency::total 1710356977 # number of ReadReq miss cycles
2421 system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2422 system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2423 system.iocache.WriteLineReq_miss_latency::realview.ide 13558851015 # number of WriteLineReq miss cycles
2424 system.iocache.WriteLineReq_miss_latency::total 13558851015 # number of WriteLineReq miss cycles
2425 system.iocache.demand_miss_latency::realview.ethernet 5646000 # number of demand (read+write) miss cycles
2426 system.iocache.demand_miss_latency::realview.ide 1705079977 # number of demand (read+write) miss cycles
2427 system.iocache.demand_miss_latency::total 1710725977 # number of demand (read+write) miss cycles
2428 system.iocache.overall_miss_latency::realview.ethernet 5646000 # number of overall miss cycles
2429 system.iocache.overall_miss_latency::realview.ide 1705079977 # number of overall miss cycles
2430 system.iocache.overall_miss_latency::total 1710725977 # number of overall miss cycles
2431 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2432 system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses)
2433 system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses)
2434 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2435 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2436 system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
2437 system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2438 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2439 system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses
2440 system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses
2441 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2442 system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses
2443 system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses
2444 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2445 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2446 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2447 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2448 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2449 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2450 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2451 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2452 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2453 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2454 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2455 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2456 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2457 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142621.621622 # average ReadReq miss latency
2458 system.iocache.ReadReq_avg_miss_latency::realview.ide 191431.455821 # average ReadReq miss latency
2459 system.iocache.ReadReq_avg_miss_latency::total 191229.536784 # average ReadReq miss latency
2460 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2461 system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2462 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126737.185140 # average WriteLineReq miss latency
2463 system.iocache.WriteLineReq_avg_miss_latency::total 126737.185140 # average WriteLineReq miss latency
2464 system.iocache.demand_avg_miss_latency::realview.ethernet 141150 # average overall miss latency
2465 system.iocache.demand_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency
2466 system.iocache.demand_avg_miss_latency::total 191206.658880 # average overall miss latency
2467 system.iocache.overall_avg_miss_latency::realview.ethernet 141150 # average overall miss latency
2468 system.iocache.overall_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency
2469 system.iocache.overall_avg_miss_latency::total 191206.658880 # average overall miss latency
2470 system.iocache.blocked_cycles::no_mshrs 35119 # number of cycles access was blocked
2471 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2472 system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked
2473 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2474 system.iocache.avg_blocked_cycles::no_mshrs 10.011117 # average number of cycles each access was blocked
2475 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2476 system.iocache.fast_writes 0 # number of fast writes performed
2477 system.iocache.cache_copies 0 # number of cache copies performed
2478 system.iocache.writebacks::writebacks 106950 # number of writebacks
2479 system.iocache.writebacks::total 106950 # number of writebacks
2480 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2481 system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses
2482 system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses
2483 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2484 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2485 system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
2486 system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2487 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2488 system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses
2489 system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses
2490 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2491 system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses
2492 system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses
2493 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3427000 # number of ReadReq MSHR miss cycles
2494 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1259729977 # number of ReadReq MSHR miss cycles
2495 system.iocache.ReadReq_mshr_miss_latency::total 1263156977 # number of ReadReq MSHR miss cycles
2496 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2497 system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2498 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203408528 # number of WriteLineReq MSHR miss cycles
2499 system.iocache.WriteLineReq_mshr_miss_latency::total 8203408528 # number of WriteLineReq MSHR miss cycles
2500 system.iocache.demand_mshr_miss_latency::realview.ethernet 3646000 # number of demand (read+write) MSHR miss cycles
2501 system.iocache.demand_mshr_miss_latency::realview.ide 1259729977 # number of demand (read+write) MSHR miss cycles
2502 system.iocache.demand_mshr_miss_latency::total 1263375977 # number of demand (read+write) MSHR miss cycles
2503 system.iocache.overall_mshr_miss_latency::realview.ethernet 3646000 # number of overall MSHR miss cycles
2504 system.iocache.overall_mshr_miss_latency::realview.ide 1259729977 # number of overall MSHR miss cycles
2505 system.iocache.overall_mshr_miss_latency::total 1263375977 # number of overall MSHR miss cycles
2506 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2507 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2508 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2509 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2510 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2511 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2512 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2513 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2514 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2515 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2516 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2517 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2518 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2519 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92621.621622 # average ReadReq mshr miss latency
2520 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141431.455821 # average ReadReq mshr miss latency
2521 system.iocache.ReadReq_avg_mshr_miss_latency::total 141229.536784 # average ReadReq mshr miss latency
2522 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2523 system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2524 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76678.835415 # average WriteLineReq mshr miss latency
2525 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76678.835415 # average WriteLineReq mshr miss latency
2526 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency
2527 system.iocache.demand_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency
2528 system.iocache.demand_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency
2529 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency
2530 system.iocache.overall_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency
2531 system.iocache.overall_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency
2532 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2533 system.l2c.tags.replacements 1736304 # number of replacements
2534 system.l2c.tags.tagsinuse 63595.107970 # Cycle average of tags in use
2535 system.l2c.tags.total_refs 7296515 # Total number of references to valid blocks.
2536 system.l2c.tags.sampled_refs 1796625 # Sample count of references to valid blocks.
2537 system.l2c.tags.avg_refs 4.061234 # Average number of references to valid blocks.
2538 system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit.
2539 system.l2c.tags.occ_blocks::writebacks 21438.357602 # Average occupied blocks per requestor
2540 system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.623523 # Average occupied blocks per requestor
2541 system.l2c.tags.occ_blocks::cpu0.itb.walker 216.352807 # Average occupied blocks per requestor
2542 system.l2c.tags.occ_blocks::cpu0.inst 5273.180907 # Average occupied blocks per requestor
2543 system.l2c.tags.occ_blocks::cpu0.data 7402.273131 # Average occupied blocks per requestor
2544 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10592.541457 # Average occupied blocks per requestor
2545 system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.822853 # Average occupied blocks per requestor
2546 system.l2c.tags.occ_blocks::cpu1.itb.walker 191.052659 # Average occupied blocks per requestor
2547 system.l2c.tags.occ_blocks::cpu1.inst 3264.316466 # Average occupied blocks per requestor
2548 system.l2c.tags.occ_blocks::cpu1.data 6229.486316 # Average occupied blocks per requestor
2549 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8664.100250 # Average occupied blocks per requestor
2550 system.l2c.tags.occ_percent::writebacks 0.327123 # Average percentage of cache occupancy
2551 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy
2552 system.l2c.tags.occ_percent::cpu0.itb.walker 0.003301 # Average percentage of cache occupancy
2553 system.l2c.tags.occ_percent::cpu0.inst 0.080462 # Average percentage of cache occupancy
2554 system.l2c.tags.occ_percent::cpu0.data 0.112950 # Average percentage of cache occupancy
2555 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.161629 # Average percentage of cache occupancy
2556 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002286 # Average percentage of cache occupancy
2557 system.l2c.tags.occ_percent::cpu1.itb.walker 0.002915 # Average percentage of cache occupancy
2558 system.l2c.tags.occ_percent::cpu1.inst 0.049810 # Average percentage of cache occupancy
2559 system.l2c.tags.occ_percent::cpu1.data 0.095054 # Average percentage of cache occupancy
2560 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132204 # Average percentage of cache occupancy
2561 system.l2c.tags.occ_percent::total 0.970384 # Average percentage of cache occupancy
2562 system.l2c.tags.occ_task_id_blocks::1022 8701 # Occupied blocks per task id
2563 system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id
2564 system.l2c.tags.occ_task_id_blocks::1024 51426 # Occupied blocks per task id
2565 system.l2c.tags.age_task_id_blocks_1022::0 62 # Occupied blocks per task id
2566 system.l2c.tags.age_task_id_blocks_1022::1 67 # Occupied blocks per task id
2567 system.l2c.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id
2568 system.l2c.tags.age_task_id_blocks_1022::3 1394 # Occupied blocks per task id
2569 system.l2c.tags.age_task_id_blocks_1022::4 6925 # Occupied blocks per task id
2570 system.l2c.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
2571 system.l2c.tags.age_task_id_blocks_1023::4 186 # Occupied blocks per task id
2572 system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
2573 system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id
2574 system.l2c.tags.age_task_id_blocks_1024::2 2651 # Occupied blocks per task id
2575 system.l2c.tags.age_task_id_blocks_1024::3 12885 # Occupied blocks per task id
2576 system.l2c.tags.age_task_id_blocks_1024::4 35470 # Occupied blocks per task id
2577 system.l2c.tags.occ_task_id_percent::1022 0.132767 # Percentage of cache occupancy per task id
2578 system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id
2579 system.l2c.tags.occ_task_id_percent::1024 0.784698 # Percentage of cache occupancy per task id
2580 system.l2c.tags.tag_accesses 90467673 # Number of tag accesses
2581 system.l2c.tags.data_accesses 90467673 # Number of data accesses
2582 system.l2c.WritebackDirty_hits::writebacks 3161640 # number of WritebackDirty hits
2583 system.l2c.WritebackDirty_hits::total 3161640 # number of WritebackDirty hits
2584 system.l2c.UpgradeReq_hits::cpu0.data 190042 # number of UpgradeReq hits
2585 system.l2c.UpgradeReq_hits::cpu1.data 150318 # number of UpgradeReq hits
2586 system.l2c.UpgradeReq_hits::total 340360 # number of UpgradeReq hits
2587 system.l2c.SCUpgradeReq_hits::cpu0.data 46175 # number of SCUpgradeReq hits
2588 system.l2c.SCUpgradeReq_hits::cpu1.data 40691 # number of SCUpgradeReq hits
2589 system.l2c.SCUpgradeReq_hits::total 86866 # number of SCUpgradeReq hits
2590 system.l2c.ReadExReq_hits::cpu0.data 66080 # number of ReadExReq hits
2591 system.l2c.ReadExReq_hits::cpu1.data 54849 # number of ReadExReq hits
2592 system.l2c.ReadExReq_hits::total 120929 # number of ReadExReq hits
2593 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7647 # number of ReadSharedReq hits
2594 system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4987 # number of ReadSharedReq hits
2595 system.l2c.ReadSharedReq_hits::cpu0.inst 699090 # number of ReadSharedReq hits
2596 system.l2c.ReadSharedReq_hits::cpu0.data 694199 # number of ReadSharedReq hits
2597 system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343045 # number of ReadSharedReq hits
2598 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6831 # number of ReadSharedReq hits
2599 system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3980 # number of ReadSharedReq hits
2600 system.l2c.ReadSharedReq_hits::cpu1.inst 688497 # number of ReadSharedReq hits
2601 system.l2c.ReadSharedReq_hits::cpu1.data 675339 # number of ReadSharedReq hits
2602 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 302251 # number of ReadSharedReq hits
2603 system.l2c.ReadSharedReq_hits::total 3425866 # number of ReadSharedReq hits
2604 system.l2c.InvalidateReq_hits::cpu0.data 143577 # number of InvalidateReq hits
2605 system.l2c.InvalidateReq_hits::cpu1.data 133038 # number of InvalidateReq hits
2606 system.l2c.InvalidateReq_hits::total 276615 # number of InvalidateReq hits
2607 system.l2c.demand_hits::cpu0.dtb.walker 7647 # number of demand (read+write) hits
2608 system.l2c.demand_hits::cpu0.itb.walker 4987 # number of demand (read+write) hits
2609 system.l2c.demand_hits::cpu0.inst 699090 # number of demand (read+write) hits
2610 system.l2c.demand_hits::cpu0.data 760279 # number of demand (read+write) hits
2611 system.l2c.demand_hits::cpu0.l2cache.prefetcher 343045 # number of demand (read+write) hits
2612 system.l2c.demand_hits::cpu1.dtb.walker 6831 # number of demand (read+write) hits
2613 system.l2c.demand_hits::cpu1.itb.walker 3980 # number of demand (read+write) hits
2614 system.l2c.demand_hits::cpu1.inst 688497 # number of demand (read+write) hits
2615 system.l2c.demand_hits::cpu1.data 730188 # number of demand (read+write) hits
2616 system.l2c.demand_hits::cpu1.l2cache.prefetcher 302251 # number of demand (read+write) hits
2617 system.l2c.demand_hits::total 3546795 # number of demand (read+write) hits
2618 system.l2c.overall_hits::cpu0.dtb.walker 7647 # number of overall hits
2619 system.l2c.overall_hits::cpu0.itb.walker 4987 # number of overall hits
2620 system.l2c.overall_hits::cpu0.inst 699090 # number of overall hits
2621 system.l2c.overall_hits::cpu0.data 760279 # number of overall hits
2622 system.l2c.overall_hits::cpu0.l2cache.prefetcher 343045 # number of overall hits
2623 system.l2c.overall_hits::cpu1.dtb.walker 6831 # number of overall hits
2624 system.l2c.overall_hits::cpu1.itb.walker 3980 # number of overall hits
2625 system.l2c.overall_hits::cpu1.inst 688497 # number of overall hits
2626 system.l2c.overall_hits::cpu1.data 730188 # number of overall hits
2627 system.l2c.overall_hits::cpu1.l2cache.prefetcher 302251 # number of overall hits
2628 system.l2c.overall_hits::total 3546795 # number of overall hits
2629 system.l2c.UpgradeReq_misses::cpu0.data 66937 # number of UpgradeReq misses
2630 system.l2c.UpgradeReq_misses::cpu1.data 62230 # number of UpgradeReq misses
2631 system.l2c.UpgradeReq_misses::total 129167 # number of UpgradeReq misses
2632 system.l2c.SCUpgradeReq_misses::cpu0.data 13492 # number of SCUpgradeReq misses
2633 system.l2c.SCUpgradeReq_misses::cpu1.data 12585 # number of SCUpgradeReq misses
2634 system.l2c.SCUpgradeReq_misses::total 26077 # number of SCUpgradeReq misses
2635 system.l2c.ReadExReq_misses::cpu0.data 88765 # number of ReadExReq misses
2636 system.l2c.ReadExReq_misses::cpu1.data 66782 # number of ReadExReq misses
2637 system.l2c.ReadExReq_misses::total 155547 # number of ReadExReq misses
2638 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3643 # number of ReadSharedReq misses
2639 system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3291 # number of ReadSharedReq misses
2640 system.l2c.ReadSharedReq_misses::cpu0.inst 71874 # number of ReadSharedReq misses
2641 system.l2c.ReadSharedReq_misses::cpu0.data 188609 # number of ReadSharedReq misses
2642 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 283713 # number of ReadSharedReq misses
2643 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2600 # number of ReadSharedReq misses
2644 system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2065 # number of ReadSharedReq misses
2645 system.l2c.ReadSharedReq_misses::cpu1.inst 61168 # number of ReadSharedReq misses
2646 system.l2c.ReadSharedReq_misses::cpu1.data 131288 # number of ReadSharedReq misses
2647 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 331034 # number of ReadSharedReq misses
2648 system.l2c.ReadSharedReq_misses::total 1079285 # number of ReadSharedReq misses
2649 system.l2c.InvalidateReq_misses::cpu0.data 420248 # number of InvalidateReq misses
2650 system.l2c.InvalidateReq_misses::cpu1.data 172062 # number of InvalidateReq misses
2651 system.l2c.InvalidateReq_misses::total 592310 # number of InvalidateReq misses
2652 system.l2c.demand_misses::cpu0.dtb.walker 3643 # number of demand (read+write) misses
2653 system.l2c.demand_misses::cpu0.itb.walker 3291 # number of demand (read+write) misses
2654 system.l2c.demand_misses::cpu0.inst 71874 # number of demand (read+write) misses
2655 system.l2c.demand_misses::cpu0.data 277374 # number of demand (read+write) misses
2656 system.l2c.demand_misses::cpu0.l2cache.prefetcher 283713 # number of demand (read+write) misses
2657 system.l2c.demand_misses::cpu1.dtb.walker 2600 # number of demand (read+write) misses
2658 system.l2c.demand_misses::cpu1.itb.walker 2065 # number of demand (read+write) misses
2659 system.l2c.demand_misses::cpu1.inst 61168 # number of demand (read+write) misses
2660 system.l2c.demand_misses::cpu1.data 198070 # number of demand (read+write) misses
2661 system.l2c.demand_misses::cpu1.l2cache.prefetcher 331034 # number of demand (read+write) misses
2662 system.l2c.demand_misses::total 1234832 # number of demand (read+write) misses
2663 system.l2c.overall_misses::cpu0.dtb.walker 3643 # number of overall misses
2664 system.l2c.overall_misses::cpu0.itb.walker 3291 # number of overall misses
2665 system.l2c.overall_misses::cpu0.inst 71874 # number of overall misses
2666 system.l2c.overall_misses::cpu0.data 277374 # number of overall misses
2667 system.l2c.overall_misses::cpu0.l2cache.prefetcher 283713 # number of overall misses
2668 system.l2c.overall_misses::cpu1.dtb.walker 2600 # number of overall misses
2669 system.l2c.overall_misses::cpu1.itb.walker 2065 # number of overall misses
2670 system.l2c.overall_misses::cpu1.inst 61168 # number of overall misses
2671 system.l2c.overall_misses::cpu1.data 198070 # number of overall misses
2672 system.l2c.overall_misses::cpu1.l2cache.prefetcher 331034 # number of overall misses
2673 system.l2c.overall_misses::total 1234832 # number of overall misses
2674 system.l2c.UpgradeReq_miss_latency::cpu0.data 1172514500 # number of UpgradeReq miss cycles
2675 system.l2c.UpgradeReq_miss_latency::cpu1.data 1079518500 # number of UpgradeReq miss cycles
2676 system.l2c.UpgradeReq_miss_latency::total 2252033000 # number of UpgradeReq miss cycles
2677 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 202156500 # number of SCUpgradeReq miss cycles
2678 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 215769000 # number of SCUpgradeReq miss cycles
2679 system.l2c.SCUpgradeReq_miss_latency::total 417925500 # number of SCUpgradeReq miss cycles
2680 system.l2c.ReadExReq_miss_latency::cpu0.data 12242204500 # number of ReadExReq miss cycles
2681 system.l2c.ReadExReq_miss_latency::cpu1.data 9216523500 # number of ReadExReq miss cycles
2682 system.l2c.ReadExReq_miss_latency::total 21458728000 # number of ReadExReq miss cycles
2683 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 512308500 # number of ReadSharedReq miss cycles
2684 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 464071000 # number of ReadSharedReq miss cycles
2685 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9761528500 # number of ReadSharedReq miss cycles
2686 system.l2c.ReadSharedReq_miss_latency::cpu0.data 26674163500 # number of ReadSharedReq miss cycles
2687 system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of ReadSharedReq miss cycles
2688 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 367906000 # number of ReadSharedReq miss cycles
2689 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 298172500 # number of ReadSharedReq miss cycles
2690 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 8283610000 # number of ReadSharedReq miss cycles
2691 system.l2c.ReadSharedReq_miss_latency::cpu1.data 18924327000 # number of ReadSharedReq miss cycles
2692 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of ReadSharedReq miss cycles
2693 system.l2c.ReadSharedReq_miss_latency::total 172936434536 # number of ReadSharedReq miss cycles
2694 system.l2c.InvalidateReq_miss_latency::cpu0.data 151369500 # number of InvalidateReq miss cycles
2695 system.l2c.InvalidateReq_miss_latency::cpu1.data 160513500 # number of InvalidateReq miss cycles
2696 system.l2c.InvalidateReq_miss_latency::total 311883000 # number of InvalidateReq miss cycles
2697 system.l2c.demand_miss_latency::cpu0.dtb.walker 512308500 # number of demand (read+write) miss cycles
2698 system.l2c.demand_miss_latency::cpu0.itb.walker 464071000 # number of demand (read+write) miss cycles
2699 system.l2c.demand_miss_latency::cpu0.inst 9761528500 # number of demand (read+write) miss cycles
2700 system.l2c.demand_miss_latency::cpu0.data 38916368000 # number of demand (read+write) miss cycles
2701 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of demand (read+write) miss cycles
2702 system.l2c.demand_miss_latency::cpu1.dtb.walker 367906000 # number of demand (read+write) miss cycles
2703 system.l2c.demand_miss_latency::cpu1.itb.walker 298172500 # number of demand (read+write) miss cycles
2704 system.l2c.demand_miss_latency::cpu1.inst 8283610000 # number of demand (read+write) miss cycles
2705 system.l2c.demand_miss_latency::cpu1.data 28140850500 # number of demand (read+write) miss cycles
2706 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of demand (read+write) miss cycles
2707 system.l2c.demand_miss_latency::total 194395162536 # number of demand (read+write) miss cycles
2708 system.l2c.overall_miss_latency::cpu0.dtb.walker 512308500 # number of overall miss cycles
2709 system.l2c.overall_miss_latency::cpu0.itb.walker 464071000 # number of overall miss cycles
2710 system.l2c.overall_miss_latency::cpu0.inst 9761528500 # number of overall miss cycles
2711 system.l2c.overall_miss_latency::cpu0.data 38916368000 # number of overall miss cycles
2712 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of overall miss cycles
2713 system.l2c.overall_miss_latency::cpu1.dtb.walker 367906000 # number of overall miss cycles
2714 system.l2c.overall_miss_latency::cpu1.itb.walker 298172500 # number of overall miss cycles
2715 system.l2c.overall_miss_latency::cpu1.inst 8283610000 # number of overall miss cycles
2716 system.l2c.overall_miss_latency::cpu1.data 28140850500 # number of overall miss cycles
2717 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of overall miss cycles
2718 system.l2c.overall_miss_latency::total 194395162536 # number of overall miss cycles
2719 system.l2c.WritebackDirty_accesses::writebacks 3161640 # number of WritebackDirty accesses(hits+misses)
2720 system.l2c.WritebackDirty_accesses::total 3161640 # number of WritebackDirty accesses(hits+misses)
2721 system.l2c.UpgradeReq_accesses::cpu0.data 256979 # number of UpgradeReq accesses(hits+misses)
2722 system.l2c.UpgradeReq_accesses::cpu1.data 212548 # number of UpgradeReq accesses(hits+misses)
2723 system.l2c.UpgradeReq_accesses::total 469527 # number of UpgradeReq accesses(hits+misses)
2724 system.l2c.SCUpgradeReq_accesses::cpu0.data 59667 # number of SCUpgradeReq accesses(hits+misses)
2725 system.l2c.SCUpgradeReq_accesses::cpu1.data 53276 # number of SCUpgradeReq accesses(hits+misses)
2726 system.l2c.SCUpgradeReq_accesses::total 112943 # number of SCUpgradeReq accesses(hits+misses)
2727 system.l2c.ReadExReq_accesses::cpu0.data 154845 # number of ReadExReq accesses(hits+misses)
2728 system.l2c.ReadExReq_accesses::cpu1.data 121631 # number of ReadExReq accesses(hits+misses)
2729 system.l2c.ReadExReq_accesses::total 276476 # number of ReadExReq accesses(hits+misses)
2730 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 11290 # number of ReadSharedReq accesses(hits+misses)
2731 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8278 # number of ReadSharedReq accesses(hits+misses)
2732 system.l2c.ReadSharedReq_accesses::cpu0.inst 770964 # number of ReadSharedReq accesses(hits+misses)
2733 system.l2c.ReadSharedReq_accesses::cpu0.data 882808 # number of ReadSharedReq accesses(hits+misses)
2734 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626758 # number of ReadSharedReq accesses(hits+misses)
2735 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9431 # number of ReadSharedReq accesses(hits+misses)
2736 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6045 # number of ReadSharedReq accesses(hits+misses)
2737 system.l2c.ReadSharedReq_accesses::cpu1.inst 749665 # number of ReadSharedReq accesses(hits+misses)
2738 system.l2c.ReadSharedReq_accesses::cpu1.data 806627 # number of ReadSharedReq accesses(hits+misses)
2739 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 633285 # number of ReadSharedReq accesses(hits+misses)
2740 system.l2c.ReadSharedReq_accesses::total 4505151 # number of ReadSharedReq accesses(hits+misses)
2741 system.l2c.InvalidateReq_accesses::cpu0.data 563825 # number of InvalidateReq accesses(hits+misses)
2742 system.l2c.InvalidateReq_accesses::cpu1.data 305100 # number of InvalidateReq accesses(hits+misses)
2743 system.l2c.InvalidateReq_accesses::total 868925 # number of InvalidateReq accesses(hits+misses)
2744 system.l2c.demand_accesses::cpu0.dtb.walker 11290 # number of demand (read+write) accesses
2745 system.l2c.demand_accesses::cpu0.itb.walker 8278 # number of demand (read+write) accesses
2746 system.l2c.demand_accesses::cpu0.inst 770964 # number of demand (read+write) accesses
2747 system.l2c.demand_accesses::cpu0.data 1037653 # number of demand (read+write) accesses
2748 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 626758 # number of demand (read+write) accesses
2749 system.l2c.demand_accesses::cpu1.dtb.walker 9431 # number of demand (read+write) accesses
2750 system.l2c.demand_accesses::cpu1.itb.walker 6045 # number of demand (read+write) accesses
2751 system.l2c.demand_accesses::cpu1.inst 749665 # number of demand (read+write) accesses
2752 system.l2c.demand_accesses::cpu1.data 928258 # number of demand (read+write) accesses
2753 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 633285 # number of demand (read+write) accesses
2754 system.l2c.demand_accesses::total 4781627 # number of demand (read+write) accesses
2755 system.l2c.overall_accesses::cpu0.dtb.walker 11290 # number of overall (read+write) accesses
2756 system.l2c.overall_accesses::cpu0.itb.walker 8278 # number of overall (read+write) accesses
2757 system.l2c.overall_accesses::cpu0.inst 770964 # number of overall (read+write) accesses
2758 system.l2c.overall_accesses::cpu0.data 1037653 # number of overall (read+write) accesses
2759 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 626758 # number of overall (read+write) accesses
2760 system.l2c.overall_accesses::cpu1.dtb.walker 9431 # number of overall (read+write) accesses
2761 system.l2c.overall_accesses::cpu1.itb.walker 6045 # number of overall (read+write) accesses
2762 system.l2c.overall_accesses::cpu1.inst 749665 # number of overall (read+write) accesses
2763 system.l2c.overall_accesses::cpu1.data 928258 # number of overall (read+write) accesses
2764 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 633285 # number of overall (read+write) accesses
2765 system.l2c.overall_accesses::total 4781627 # number of overall (read+write) accesses
2766 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260477 # miss rate for UpgradeReq accesses
2767 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.292781 # miss rate for UpgradeReq accesses
2768 system.l2c.UpgradeReq_miss_rate::total 0.275100 # miss rate for UpgradeReq accesses
2769 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.226122 # miss rate for SCUpgradeReq accesses
2770 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.236223 # miss rate for SCUpgradeReq accesses
2771 system.l2c.SCUpgradeReq_miss_rate::total 0.230886 # miss rate for SCUpgradeReq accesses
2772 system.l2c.ReadExReq_miss_rate::cpu0.data 0.573251 # miss rate for ReadExReq accesses
2773 system.l2c.ReadExReq_miss_rate::cpu1.data 0.549054 # miss rate for ReadExReq accesses
2774 system.l2c.ReadExReq_miss_rate::total 0.562606 # miss rate for ReadExReq accesses
2775 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for ReadSharedReq accesses
2776 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.397560 # miss rate for ReadSharedReq accesses
2777 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.093226 # miss rate for ReadSharedReq accesses
2778 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213647 # miss rate for ReadSharedReq accesses
2779 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for ReadSharedReq accesses
2780 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for ReadSharedReq accesses
2781 system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.341605 # miss rate for ReadSharedReq accesses
2782 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.081594 # miss rate for ReadSharedReq accesses
2783 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.162762 # miss rate for ReadSharedReq accesses
2784 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for ReadSharedReq accesses
2785 system.l2c.ReadSharedReq_miss_rate::total 0.239567 # miss rate for ReadSharedReq accesses
2786 system.l2c.InvalidateReq_miss_rate::cpu0.data 0.745352 # miss rate for InvalidateReq accesses
2787 system.l2c.InvalidateReq_miss_rate::cpu1.data 0.563953 # miss rate for InvalidateReq accesses
2788 system.l2c.InvalidateReq_miss_rate::total 0.681658 # miss rate for InvalidateReq accesses
2789 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for demand accesses
2790 system.l2c.demand_miss_rate::cpu0.itb.walker 0.397560 # miss rate for demand accesses
2791 system.l2c.demand_miss_rate::cpu0.inst 0.093226 # miss rate for demand accesses
2792 system.l2c.demand_miss_rate::cpu0.data 0.267309 # miss rate for demand accesses
2793 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for demand accesses
2794 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for demand accesses
2795 system.l2c.demand_miss_rate::cpu1.itb.walker 0.341605 # miss rate for demand accesses
2796 system.l2c.demand_miss_rate::cpu1.inst 0.081594 # miss rate for demand accesses
2797 system.l2c.demand_miss_rate::cpu1.data 0.213378 # miss rate for demand accesses
2798 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for demand accesses
2799 system.l2c.demand_miss_rate::total 0.258245 # miss rate for demand accesses
2800 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for overall accesses
2801 system.l2c.overall_miss_rate::cpu0.itb.walker 0.397560 # miss rate for overall accesses
2802 system.l2c.overall_miss_rate::cpu0.inst 0.093226 # miss rate for overall accesses
2803 system.l2c.overall_miss_rate::cpu0.data 0.267309 # miss rate for overall accesses
2804 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for overall accesses
2805 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for overall accesses
2806 system.l2c.overall_miss_rate::cpu1.itb.walker 0.341605 # miss rate for overall accesses
2807 system.l2c.overall_miss_rate::cpu1.inst 0.081594 # miss rate for overall accesses
2808 system.l2c.overall_miss_rate::cpu1.data 0.213378 # miss rate for overall accesses
2809 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for overall accesses
2810 system.l2c.overall_miss_rate::total 0.258245 # miss rate for overall accesses
2811 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17516.687333 # average UpgradeReq miss latency
2812 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17347.236060 # average UpgradeReq miss latency
2813 system.l2c.UpgradeReq_avg_miss_latency::total 17435.049200 # average UpgradeReq miss latency
2814 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14983.434628 # average SCUpgradeReq miss latency
2815 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17144.934446 # average SCUpgradeReq miss latency
2816 system.l2c.SCUpgradeReq_avg_miss_latency::total 16026.594317 # average SCUpgradeReq miss latency
2817 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 137917.022475 # average ReadExReq miss latency
2818 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 138009.096763 # average ReadExReq miss latency
2819 system.l2c.ReadExReq_avg_miss_latency::total 137956.553325 # average ReadExReq miss latency
2820 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average ReadSharedReq miss latency
2821 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141012.154360 # average ReadSharedReq miss latency
2822 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135814.460027 # average ReadSharedReq miss latency
2823 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141425.719345 # average ReadSharedReq miss latency
2824 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average ReadSharedReq miss latency
2825 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average ReadSharedReq miss latency
2826 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144393.462470 # average ReadSharedReq miss latency
2827 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135423.914465 # average ReadSharedReq miss latency
2828 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144143.615563 # average ReadSharedReq miss latency
2829 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average ReadSharedReq miss latency
2830 system.l2c.ReadSharedReq_avg_miss_latency::total 160232.408063 # average ReadSharedReq miss latency
2831 system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 360.190887 # average InvalidateReq miss latency
2832 system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 932.881752 # average InvalidateReq miss latency
2833 system.l2c.InvalidateReq_avg_miss_latency::total 526.553663 # average InvalidateReq miss latency
2834 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average overall miss latency
2835 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141012.154360 # average overall miss latency
2836 system.l2c.demand_avg_miss_latency::cpu0.inst 135814.460027 # average overall miss latency
2837 system.l2c.demand_avg_miss_latency::cpu0.data 140302.869050 # average overall miss latency
2838 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average overall miss latency
2839 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average overall miss latency
2840 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 144393.462470 # average overall miss latency
2841 system.l2c.demand_avg_miss_latency::cpu1.inst 135423.914465 # average overall miss latency
2842 system.l2c.demand_avg_miss_latency::cpu1.data 142075.278942 # average overall miss latency
2843 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average overall miss latency
2844 system.l2c.demand_avg_miss_latency::total 157426.404998 # average overall miss latency
2845 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average overall miss latency
2846 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141012.154360 # average overall miss latency
2847 system.l2c.overall_avg_miss_latency::cpu0.inst 135814.460027 # average overall miss latency
2848 system.l2c.overall_avg_miss_latency::cpu0.data 140302.869050 # average overall miss latency
2849 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average overall miss latency
2850 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average overall miss latency
2851 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144393.462470 # average overall miss latency
2852 system.l2c.overall_avg_miss_latency::cpu1.inst 135423.914465 # average overall miss latency
2853 system.l2c.overall_avg_miss_latency::cpu1.data 142075.278942 # average overall miss latency
2854 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average overall miss latency
2855 system.l2c.overall_avg_miss_latency::total 157426.404998 # average overall miss latency
2856 system.l2c.blocked_cycles::no_mshrs 1204 # number of cycles access was blocked
2857 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2858 system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
2859 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2860 system.l2c.avg_blocked_cycles::no_mshrs 240.800000 # average number of cycles each access was blocked
2861 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2862 system.l2c.fast_writes 0 # number of fast writes performed
2863 system.l2c.cache_copies 0 # number of cache copies performed
2864 system.l2c.writebacks::writebacks 1344961 # number of writebacks
2865 system.l2c.writebacks::total 1344961 # number of writebacks
2866 system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits
2867 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 474 # number of ReadSharedReq MSHR hits
2868 system.l2c.ReadSharedReq_mshr_hits::cpu0.data 106 # number of ReadSharedReq MSHR hits
2869 system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 35 # number of ReadSharedReq MSHR hits
2870 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 389 # number of ReadSharedReq MSHR hits
2871 system.l2c.ReadSharedReq_mshr_hits::cpu1.data 102 # number of ReadSharedReq MSHR hits
2872 system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadSharedReq MSHR hits
2873 system.l2c.ReadSharedReq_mshr_hits::total 1122 # number of ReadSharedReq MSHR hits
2874 system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
2875 system.l2c.demand_mshr_hits::cpu0.inst 474 # number of demand (read+write) MSHR hits
2876 system.l2c.demand_mshr_hits::cpu0.data 106 # number of demand (read+write) MSHR hits
2877 system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 35 # number of demand (read+write) MSHR hits
2878 system.l2c.demand_mshr_hits::cpu1.inst 389 # number of demand (read+write) MSHR hits
2879 system.l2c.demand_mshr_hits::cpu1.data 102 # number of demand (read+write) MSHR hits
2880 system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits
2881 system.l2c.demand_mshr_hits::total 1122 # number of demand (read+write) MSHR hits
2882 system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
2883 system.l2c.overall_mshr_hits::cpu0.inst 474 # number of overall MSHR hits
2884 system.l2c.overall_mshr_hits::cpu0.data 106 # number of overall MSHR hits
2885 system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 35 # number of overall MSHR hits
2886 system.l2c.overall_mshr_hits::cpu1.inst 389 # number of overall MSHR hits
2887 system.l2c.overall_mshr_hits::cpu1.data 102 # number of overall MSHR hits
2888 system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits
2889 system.l2c.overall_mshr_hits::total 1122 # number of overall MSHR hits
2890 system.l2c.CleanEvict_mshr_misses::writebacks 71582 # number of CleanEvict MSHR misses
2891 system.l2c.CleanEvict_mshr_misses::total 71582 # number of CleanEvict MSHR misses
2892 system.l2c.UpgradeReq_mshr_misses::cpu0.data 66937 # number of UpgradeReq MSHR misses
2893 system.l2c.UpgradeReq_mshr_misses::cpu1.data 62230 # number of UpgradeReq MSHR misses
2894 system.l2c.UpgradeReq_mshr_misses::total 129167 # number of UpgradeReq MSHR misses
2895 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13492 # number of SCUpgradeReq MSHR misses
2896 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12585 # number of SCUpgradeReq MSHR misses
2897 system.l2c.SCUpgradeReq_mshr_misses::total 26077 # number of SCUpgradeReq MSHR misses
2898 system.l2c.ReadExReq_mshr_misses::cpu0.data 88765 # number of ReadExReq MSHR misses
2899 system.l2c.ReadExReq_mshr_misses::cpu1.data 66782 # number of ReadExReq MSHR misses
2900 system.l2c.ReadExReq_mshr_misses::total 155547 # number of ReadExReq MSHR misses
2901 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3642 # number of ReadSharedReq MSHR misses
2902 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3291 # number of ReadSharedReq MSHR misses
2903 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 71400 # number of ReadSharedReq MSHR misses
2904 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 188503 # number of ReadSharedReq MSHR misses
2905 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 283678 # number of ReadSharedReq MSHR misses
2906 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2600 # number of ReadSharedReq MSHR misses
2907 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2065 # number of ReadSharedReq MSHR misses
2908 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 60779 # number of ReadSharedReq MSHR misses
2909 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 131186 # number of ReadSharedReq MSHR misses
2910 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 331019 # number of ReadSharedReq MSHR misses
2911 system.l2c.ReadSharedReq_mshr_misses::total 1078163 # number of ReadSharedReq MSHR misses
2912 system.l2c.InvalidateReq_mshr_misses::cpu0.data 420248 # number of InvalidateReq MSHR misses
2913 system.l2c.InvalidateReq_mshr_misses::cpu1.data 172062 # number of InvalidateReq MSHR misses
2914 system.l2c.InvalidateReq_mshr_misses::total 592310 # number of InvalidateReq MSHR misses
2915 system.l2c.demand_mshr_misses::cpu0.dtb.walker 3642 # number of demand (read+write) MSHR misses
2916 system.l2c.demand_mshr_misses::cpu0.itb.walker 3291 # number of demand (read+write) MSHR misses
2917 system.l2c.demand_mshr_misses::cpu0.inst 71400 # number of demand (read+write) MSHR misses
2918 system.l2c.demand_mshr_misses::cpu0.data 277268 # number of demand (read+write) MSHR misses
2919 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 283678 # number of demand (read+write) MSHR misses
2920 system.l2c.demand_mshr_misses::cpu1.dtb.walker 2600 # number of demand (read+write) MSHR misses
2921 system.l2c.demand_mshr_misses::cpu1.itb.walker 2065 # number of demand (read+write) MSHR misses
2922 system.l2c.demand_mshr_misses::cpu1.inst 60779 # number of demand (read+write) MSHR misses
2923 system.l2c.demand_mshr_misses::cpu1.data 197968 # number of demand (read+write) MSHR misses
2924 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 331019 # number of demand (read+write) MSHR misses
2925 system.l2c.demand_mshr_misses::total 1233710 # number of demand (read+write) MSHR misses
2926 system.l2c.overall_mshr_misses::cpu0.dtb.walker 3642 # number of overall MSHR misses
2927 system.l2c.overall_mshr_misses::cpu0.itb.walker 3291 # number of overall MSHR misses
2928 system.l2c.overall_mshr_misses::cpu0.inst 71400 # number of overall MSHR misses
2929 system.l2c.overall_mshr_misses::cpu0.data 277268 # number of overall MSHR misses
2930 system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 283678 # number of overall MSHR misses
2931 system.l2c.overall_mshr_misses::cpu1.dtb.walker 2600 # number of overall MSHR misses
2932 system.l2c.overall_mshr_misses::cpu1.itb.walker 2065 # number of overall MSHR misses
2933 system.l2c.overall_mshr_misses::cpu1.inst 60779 # number of overall MSHR misses
2934 system.l2c.overall_mshr_misses::cpu1.data 197968 # number of overall MSHR misses
2935 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 331019 # number of overall MSHR misses
2936 system.l2c.overall_mshr_misses::total 1233710 # number of overall MSHR misses
2937 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
2938 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable
2939 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
2940 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23240 # number of ReadReq MSHR uncacheable
2941 system.l2c.ReadReq_mshr_uncacheable::total 90728 # number of ReadReq MSHR uncacheable
2942 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable
2943 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable
2944 system.l2c.WriteReq_mshr_uncacheable::total 38212 # number of WriteReq MSHR uncacheable
2945 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
2946 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses
2947 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
2948 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 45476 # number of overall MSHR uncacheable misses
2949 system.l2c.overall_mshr_uncacheable_misses::total 128940 # number of overall MSHR uncacheable misses
2950 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4736350999 # number of UpgradeReq MSHR miss cycles
2951 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4378498495 # number of UpgradeReq MSHR miss cycles
2952 system.l2c.UpgradeReq_mshr_miss_latency::total 9114849494 # number of UpgradeReq MSHR miss cycles
2953 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 993564496 # number of SCUpgradeReq MSHR miss cycles
2954 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 925610998 # number of SCUpgradeReq MSHR miss cycles
2955 system.l2c.SCUpgradeReq_mshr_miss_latency::total 1919175494 # number of SCUpgradeReq MSHR miss cycles
2956 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 11354144726 # number of ReadExReq MSHR miss cycles
2957 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 8548403021 # number of ReadExReq MSHR miss cycles
2958 system.l2c.ReadExReq_mshr_miss_latency::total 19902547747 # number of ReadExReq MSHR miss cycles
2959 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 475745539 # number of ReadSharedReq MSHR miss cycles
2960 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 431144036 # number of ReadSharedReq MSHR miss cycles
2961 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8990432141 # number of ReadSharedReq MSHR miss cycles
2962 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 24773636898 # number of ReadSharedReq MSHR miss cycles
2963 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 45987586011 # number of ReadSharedReq MSHR miss cycles
2964 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 341894523 # number of ReadSharedReq MSHR miss cycles
2965 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 277514518 # number of ReadSharedReq MSHR miss cycles
2966 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7629341915 # number of ReadSharedReq MSHR miss cycles
2967 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17597986348 # number of ReadSharedReq MSHR miss cycles
2968 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 55505284382 # number of ReadSharedReq MSHR miss cycles
2969 system.l2c.ReadSharedReq_mshr_miss_latency::total 162010566311 # number of ReadSharedReq MSHR miss cycles
2970 system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 29454261500 # number of InvalidateReq MSHR miss cycles
2971 system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 11918839498 # number of InvalidateReq MSHR miss cycles
2972 system.l2c.InvalidateReq_mshr_miss_latency::total 41373100998 # number of InvalidateReq MSHR miss cycles
2973 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 475745539 # number of demand (read+write) MSHR miss cycles
2974 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 431144036 # number of demand (read+write) MSHR miss cycles
2975 system.l2c.demand_mshr_miss_latency::cpu0.inst 8990432141 # number of demand (read+write) MSHR miss cycles
2976 system.l2c.demand_mshr_miss_latency::cpu0.data 36127781624 # number of demand (read+write) MSHR miss cycles
2977 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 45987586011 # number of demand (read+write) MSHR miss cycles
2978 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 341894523 # number of demand (read+write) MSHR miss cycles
2979 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 277514518 # number of demand (read+write) MSHR miss cycles
2980 system.l2c.demand_mshr_miss_latency::cpu1.inst 7629341915 # number of demand (read+write) MSHR miss cycles
2981 system.l2c.demand_mshr_miss_latency::cpu1.data 26146389369 # number of demand (read+write) MSHR miss cycles
2982 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 55505284382 # number of demand (read+write) MSHR miss cycles
2983 system.l2c.demand_mshr_miss_latency::total 181913114058 # number of demand (read+write) MSHR miss cycles
2984 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 475745539 # number of overall MSHR miss cycles
2985 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 431144036 # number of overall MSHR miss cycles
2986 system.l2c.overall_mshr_miss_latency::cpu0.inst 8990432141 # number of overall MSHR miss cycles
2987 system.l2c.overall_mshr_miss_latency::cpu0.data 36127781624 # number of overall MSHR miss cycles
2988 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 45987586011 # number of overall MSHR miss cycles
2989 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 341894523 # number of overall MSHR miss cycles
2990 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 277514518 # number of overall MSHR miss cycles
2991 system.l2c.overall_mshr_miss_latency::cpu1.inst 7629341915 # number of overall MSHR miss cycles
2992 system.l2c.overall_mshr_miss_latency::cpu1.data 26146389369 # number of overall MSHR miss cycles
2993 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 55505284382 # number of overall MSHR miss cycles
2994 system.l2c.overall_mshr_miss_latency::total 181913114058 # number of overall MSHR miss cycles
2995 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles
2996 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2247697035 # number of ReadReq MSHR uncacheable cycles
2997 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10383500 # number of ReadReq MSHR uncacheable cycles
2998 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3688367522 # number of ReadReq MSHR uncacheable cycles
2999 system.l2c.ReadReq_mshr_uncacheable_latency::total 11844114057 # number of ReadReq MSHR uncacheable cycles
3000 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2355491526 # number of WriteReq MSHR uncacheable cycles
3001 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3627802114 # number of WriteReq MSHR uncacheable cycles
3002 system.l2c.WriteReq_mshr_uncacheable_latency::total 5983293640 # number of WriteReq MSHR uncacheable cycles
3003 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles
3004 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4603188561 # number of overall MSHR uncacheable cycles
3005 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10383500 # number of overall MSHR uncacheable cycles
3006 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7316169636 # number of overall MSHR uncacheable cycles
3007 system.l2c.overall_mshr_uncacheable_latency::total 17827407697 # number of overall MSHR uncacheable cycles
3008 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3009 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3010 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.260477 # mshr miss rate for UpgradeReq accesses
3011 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.292781 # mshr miss rate for UpgradeReq accesses
3012 system.l2c.UpgradeReq_mshr_miss_rate::total 0.275100 # mshr miss rate for UpgradeReq accesses
3013 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.226122 # mshr miss rate for SCUpgradeReq accesses
3014 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.236223 # mshr miss rate for SCUpgradeReq accesses
3015 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230886 # mshr miss rate for SCUpgradeReq accesses
3016 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573251 # mshr miss rate for ReadExReq accesses
3017 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.549054 # mshr miss rate for ReadExReq accesses
3018 system.l2c.ReadExReq_mshr_miss_rate::total 0.562606 # mshr miss rate for ReadExReq accesses
3019 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for ReadSharedReq accesses
3020 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for ReadSharedReq accesses
3021 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for ReadSharedReq accesses
3022 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.213527 # mshr miss rate for ReadSharedReq accesses
3023 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for ReadSharedReq accesses
3024 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for ReadSharedReq accesses
3025 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for ReadSharedReq accesses
3026 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for ReadSharedReq accesses
3027 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162635 # mshr miss rate for ReadSharedReq accesses
3028 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for ReadSharedReq accesses
3029 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.239318 # mshr miss rate for ReadSharedReq accesses
3030 system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.745352 # mshr miss rate for InvalidateReq accesses
3031 system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.563953 # mshr miss rate for InvalidateReq accesses
3032 system.l2c.InvalidateReq_mshr_miss_rate::total 0.681658 # mshr miss rate for InvalidateReq accesses
3033 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for demand accesses
3034 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for demand accesses
3035 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for demand accesses
3036 system.l2c.demand_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for demand accesses
3037 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for demand accesses
3038 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for demand accesses
3039 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for demand accesses
3040 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for demand accesses
3041 system.l2c.demand_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for demand accesses
3042 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for demand accesses
3043 system.l2c.demand_mshr_miss_rate::total 0.258011 # mshr miss rate for demand accesses
3044 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for overall accesses
3045 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for overall accesses
3046 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for overall accesses
3047 system.l2c.overall_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for overall accesses
3048 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for overall accesses
3049 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for overall accesses
3050 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for overall accesses
3051 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for overall accesses
3052 system.l2c.overall_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for overall accesses
3053 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for overall accesses
3054 system.l2c.overall_mshr_miss_rate::total 0.258011 # mshr miss rate for overall accesses
3055 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.339917 # average UpgradeReq mshr miss latency
3056 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70359.930821 # average UpgradeReq mshr miss latency
3057 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70566.394621 # average UpgradeReq mshr miss latency
3058 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73641.009191 # average SCUpgradeReq mshr miss latency
3059 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73548.748351 # average SCUpgradeReq mshr miss latency
3060 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.483261 # average SCUpgradeReq mshr miss latency
3061 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127912.406083 # average ReadExReq mshr miss latency
3062 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362 # average ReadExReq mshr miss latency
3063 system.l2c.ReadExReq_avg_mshr_miss_latency::total 127951.987161 # average ReadExReq mshr miss latency
3064 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average ReadSharedReq mshr miss latency
3065 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average ReadSharedReq mshr miss latency
3066 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average ReadSharedReq mshr miss latency
3067 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131423.037819 # average ReadSharedReq mshr miss latency
3068 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average ReadSharedReq mshr miss latency
3069 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average ReadSharedReq mshr miss latency
3070 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average ReadSharedReq mshr miss latency
3071 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average ReadSharedReq mshr miss latency
3072 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792 # average ReadSharedReq mshr miss latency
3073 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average ReadSharedReq mshr miss latency
3074 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892 # average ReadSharedReq mshr miss latency
3075 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865 # average InvalidateReq mshr miss latency
3076 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839 # average InvalidateReq mshr miss latency
3077 system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852 # average InvalidateReq mshr miss latency
3078 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency
3079 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency
3080 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency
3081 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency
3082 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency
3083 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency
3084 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency
3085 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency
3086 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency
3087 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency
3088 system.l2c.demand_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency
3089 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency
3090 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency
3091 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency
3092 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency
3093 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency
3094 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency
3095 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency
3096 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency
3097 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency
3098 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency
3099 system.l2c.overall_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency
3100 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency
3101 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785 # average ReadReq mshr uncacheable latency
3102 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency
3103 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699 # average ReadReq mshr uncacheable latency
3104 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866 # average ReadReq mshr uncacheable latency
3105 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444 # average WriteReq mshr uncacheable latency
3106 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166 # average WriteReq mshr uncacheable latency
3107 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643 # average WriteReq mshr uncacheable latency
3108 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
3109 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448 # average overall mshr uncacheable latency
3110 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency
3111 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728 # average overall mshr uncacheable latency
3112 system.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457 # average overall mshr uncacheable latency
3113 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3114 system.membus.trans_dist::ReadReq 90728 # Transaction distribution
3115 system.membus.trans_dist::ReadResp 1177835 # Transaction distribution
3116 system.membus.trans_dist::WriteReq 38212 # Transaction distribution
3117 system.membus.trans_dist::WriteResp 38212 # Transaction distribution
3118 system.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution
3119 system.membus.trans_dist::CleanEvict 312799 # Transaction distribution
3120 system.membus.trans_dist::UpgradeReq 438732 # Transaction distribution
3121 system.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution
3122 system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3123 system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
3124 system.membus.trans_dist::ReadExReq 166722 # Transaction distribution
3125 system.membus.trans_dist::ReadExResp 150087 # Transaction distribution
3126 system.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution
3127 system.membus.trans_dist::InvalidateReq 695373 # Transaction distribution
3128 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes)
3129 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
3130 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes)
3131 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes)
3132 system.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes)
3133 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes)
3134 system.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes)
3135 system.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes)
3136 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes)
3137 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
3138 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes)
3139 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes)
3140 system.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes)
3141 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes)
3142 system.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes)
3143 system.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes)
3144 system.membus.snoops 622390 # Total snoops (count)
3145 system.membus.snoop_fanout::samples 4610336 # Request fanout histogram
3146 system.membus.snoop_fanout::mean 1 # Request fanout histogram
3147 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3148 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3149 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3150 system.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram
3151 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3152 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3153 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3154 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3155 system.membus.snoop_fanout::total 4610336 # Request fanout histogram
3156 system.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks)
3157 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3158 system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
3159 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3160 system.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks)
3161 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3162 system.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks)
3163 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3164 system.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks)
3165 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3166 system.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks)
3167 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3168 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3169 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3170 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3171 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3172 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3173 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3174 system.realview.ethernet.txBytes 966 # Bytes Transmitted
3175 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3176 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3177 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3178 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3179 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3180 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3181 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3182 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3183 system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
3184 system.realview.ethernet.totPackets 3 # Total Packets
3185 system.realview.ethernet.totBytes 966 # Total Bytes
3186 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
3187 system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
3188 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
3189 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3190 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
3191 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3192 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3193 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
3194 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3195 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3196 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
3197 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3198 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3199 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
3200 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3201 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3202 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
3203 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3204 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3205 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
3206 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3207 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3208 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3209 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3210 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3211 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3212 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3213 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3214 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3215 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3216 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3217 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3218 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3219 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3220 system.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter.
3221 system.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3222 system.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3223 system.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter.
3224 system.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3225 system.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3226 system.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution
3227 system.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution
3228 system.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution
3229 system.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution
3230 system.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution
3231 system.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution
3232 system.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution
3233 system.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution
3234 system.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution
3235 system.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution
3236 system.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
3237 system.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution
3238 system.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution
3239 system.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution
3240 system.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution
3241 system.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution
3242 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes)
3243 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes)
3244 system.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes)
3245 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes)
3246 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes)
3247 system.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes)
3248 system.toL2Bus.snoops 3424368 # Total snoops (count)
3249 system.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram
3250 system.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram
3251 system.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram
3252 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3253 system.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram
3254 system.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram
3255 system.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram
3256 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3257 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3258 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3259 system.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram
3260 system.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks)
3261 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3262 system.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks)
3263 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3264 system.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks)
3265 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3266 system.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks)
3267 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3269 ---------- End Simulation Statistics ----------
projects / gem5.git / blob