2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 47.355903 # Number of seconds simulated
4 sim_ticks 47355903328000 # Number of ticks simulated
5 final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 170836 # Simulator instruction rate (inst/s)
8 host_op_rate 200933 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 9157476763 # Simulator tick rate (ticks/s)
10 host_mem_usage 772600 # Number of bytes of host memory used
11 host_seconds 5171.28 # Real time elapsed on the host
12 sim_insts 883443630 # Number of instructions simulated
13 sim_ops 1039082168 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory
26 system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory
27 system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory
28 system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory
29 system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory
31 system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory
32 system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory
33 system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34 system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35 system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory
36 system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory
46 system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory
47 system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory
48 system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory
49 system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50 system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51 system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory
52 system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s)
71 system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s)
84 system.physmem.readReqs 977362 # Number of read requests accepted
85 system.physmem.writeReqs 1184351 # Number of write requests accepted
86 system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue
87 system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue
88 system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM
89 system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue
90 system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM
91 system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side
92 system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side
93 system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue
94 system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
95 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96 system.physmem.perBankRdBursts::0 54912 # Per bank write bursts
97 system.physmem.perBankRdBursts::1 56908 # Per bank write bursts
98 system.physmem.perBankRdBursts::2 51582 # Per bank write bursts
99 system.physmem.perBankRdBursts::3 63469 # Per bank write bursts
100 system.physmem.perBankRdBursts::4 61411 # Per bank write bursts
101 system.physmem.perBankRdBursts::5 61841 # Per bank write bursts
102 system.physmem.perBankRdBursts::6 57272 # Per bank write bursts
103 system.physmem.perBankRdBursts::7 62841 # Per bank write bursts
104 system.physmem.perBankRdBursts::8 51834 # Per bank write bursts
105 system.physmem.perBankRdBursts::9 112088 # Per bank write bursts
106 system.physmem.perBankRdBursts::10 55237 # Per bank write bursts
107 system.physmem.perBankRdBursts::11 58857 # Per bank write bursts
108 system.physmem.perBankRdBursts::12 56745 # Per bank write bursts
109 system.physmem.perBankRdBursts::13 58205 # Per bank write bursts
110 system.physmem.perBankRdBursts::14 53859 # Per bank write bursts
111 system.physmem.perBankRdBursts::15 59928 # Per bank write bursts
112 system.physmem.perBankWrBursts::0 69820 # Per bank write bursts
113 system.physmem.perBankWrBursts::1 73385 # Per bank write bursts
114 system.physmem.perBankWrBursts::2 70846 # Per bank write bursts
115 system.physmem.perBankWrBursts::3 76844 # Per bank write bursts
116 system.physmem.perBankWrBursts::4 76655 # Per bank write bursts
117 system.physmem.perBankWrBursts::5 78828 # Per bank write bursts
118 system.physmem.perBankWrBursts::6 72793 # Per bank write bursts
119 system.physmem.perBankWrBursts::7 76848 # Per bank write bursts
120 system.physmem.perBankWrBursts::8 69899 # Per bank write bursts
121 system.physmem.perBankWrBursts::9 74878 # Per bank write bursts
122 system.physmem.perBankWrBursts::10 69893 # Per bank write bursts
123 system.physmem.perBankWrBursts::11 73658 # Per bank write bursts
124 system.physmem.perBankWrBursts::12 73258 # Per bank write bursts
125 system.physmem.perBankWrBursts::13 76164 # Per bank write bursts
126 system.physmem.perBankWrBursts::14 72361 # Per bank write bursts
127 system.physmem.perBankWrBursts::15 75956 # Per bank write bursts
128 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129 system.physmem.numWrRetry 28 # Number of times write queue was full causing retry
130 system.physmem.totGap 47355901307500 # Total gap between requests
131 system.physmem.readPktSize::0 0 # Read request sizes (log2)
132 system.physmem.readPktSize::1 0 # Read request sizes (log2)
133 system.physmem.readPktSize::2 0 # Read request sizes (log2)
134 system.physmem.readPktSize::3 25 # Read request sizes (log2)
135 system.physmem.readPktSize::4 5 # Read request sizes (log2)
136 system.physmem.readPktSize::5 0 # Read request sizes (log2)
137 system.physmem.readPktSize::6 977332 # Read request sizes (log2)
138 system.physmem.writePktSize::0 0 # Write request sizes (log2)
139 system.physmem.writePktSize::1 0 # Write request sizes (log2)
140 system.physmem.writePktSize::2 2 # Write request sizes (log2)
141 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142 system.physmem.writePktSize::4 0 # Write request sizes (log2)
143 system.physmem.writePktSize::5 0 # Write request sizes (log2)
144 system.physmem.writePktSize::6 1181777 # Write request sizes (log2)
145 system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
176 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
177 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see
240 system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see
241 system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation
255 system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes
256 system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes
257 system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes
258 system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes
259 system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
261 system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
262 system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes
263 system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads
299 system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads
300 system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads
301 system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads
302 system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads
303 system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads
304 system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads
305 system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads
306 system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads
307 system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads
308 system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads
309 system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads
310 system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads
311 system.physmem.totQLat 32578317305 # Total ticks spent queuing
312 system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM
313 system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers
314 system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst
315 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
316 system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst
317 system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s
318 system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s
319 system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s
320 system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s
321 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
322 system.physmem.busUtil 0.02 # Data bus utilization in percentage
323 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
324 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
325 system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
326 system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing
327 system.physmem.readRowHits 734277 # Number of row buffer hits during reads
328 system.physmem.writeRowHits 451275 # Number of row buffer hits during writes
329 system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads
330 system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes
331 system.physmem.avgGap 21906655.19 # Average gap between requests
332 system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined
333 system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ)
334 system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ)
335 system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ)
336 system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ)
337 system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ)
338 system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ)
339 system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ)
340 system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ)
341 system.physmem_0.averagePower 668.658673 # Core power per rank (mW)
342 system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states
343 system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states
344 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
345 system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states
346 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
347 system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ)
348 system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ)
349 system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ)
350 system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ)
351 system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ)
352 system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ)
353 system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ)
354 system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ)
355 system.physmem_1.averagePower 668.651183 # Core power per rank (mW)
356 system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states
357 system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states
358 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
359 system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states
360 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
361 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
362 system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
363 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
364 system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
365 system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
366 system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
367 system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
368 system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
369 system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
370 system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
371 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
372 system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
373 system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
374 system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
375 system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
376 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
377 system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
378 system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
379 system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
380 system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
381 system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
382 system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
383 system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
384 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
385 system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
386 system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
387 system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
388 system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
389 system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
390 system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
391 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
392 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
393 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
394 system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
395 system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
396 system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
397 system.cpu0.branchPred.lookups 145452632 # Number of BP lookups
398 system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted
399 system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect
400 system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups
401 system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits
402 system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
403 system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage
404 system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target.
405 system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions.
406 system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups.
407 system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits.
408 system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses.
409 system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches.
410 system.cpu_clk_domain.clock 500 # Clock period in ticks
411 system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
412 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
413 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
414 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
415 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
416 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
417 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
418 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
419 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
420 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
421 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
422 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
423 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
424 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
425 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
426 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
427 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
428 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
429 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
430 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
431 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
432 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
433 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
434 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
435 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
436 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
437 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
438 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
439 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
440 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
441 system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
442 system.cpu0.dtb.walker.walks 298304 # Table walker walks requested
443 system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors
444 system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate
445 system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate
446 system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency
447 system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency
448 system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency
449 system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency
450 system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency
451 system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency
452 system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency
453 system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency
454 system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency
455 system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency
456 system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency
457 system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency
458 system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
459 system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
460 system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
461 system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
462 system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency
463 system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution
464 system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution
465 system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution
466 system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated
467 system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated
468 system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated
469 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst
470 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
471 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst
472 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst
473 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
474 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst
475 system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst
476 system.cpu0.dtb.inst_hits 0 # ITB inst hits
477 system.cpu0.dtb.inst_misses 0 # ITB inst misses
478 system.cpu0.dtb.read_hits 93899745 # DTB read hits
479 system.cpu0.dtb.read_misses 250404 # DTB read misses
480 system.cpu0.dtb.write_hits 82108561 # DTB write hits
481 system.cpu0.dtb.write_misses 47900 # DTB write misses
482 system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
483 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
484 system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
485 system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
486 system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB
487 system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions
488 system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch
489 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
490 system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions
491 system.cpu0.dtb.read_accesses 94150149 # DTB read accesses
492 system.cpu0.dtb.write_accesses 82156461 # DTB write accesses
493 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
494 system.cpu0.dtb.hits 176008306 # DTB hits
495 system.cpu0.dtb.misses 298304 # DTB misses
496 system.cpu0.dtb.accesses 176306610 # DTB accesses
497 system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
498 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
499 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
500 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
501 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
502 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
503 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
504 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
505 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
506 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
507 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
508 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
509 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
510 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
511 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
512 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
513 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
514 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
515 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
516 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
517 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
518 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
519 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
520 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
521 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
522 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
523 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
524 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
525 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
526 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
527 system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
528 system.cpu0.itb.walker.walks 65048 # Table walker walks requested
529 system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors
530 system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate
531 system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate
532 system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency
533 system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency
534 system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency
535 system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency
536 system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency
537 system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency
538 system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency
539 system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency
540 system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency
541 system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency
542 system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency
543 system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency
544 system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency
545 system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency
546 system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency
547 system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency
548 system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency
549 system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
550 system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
551 system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
552 system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
553 system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency
554 system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution
555 system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution
556 system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution
557 system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated
558 system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated
559 system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated
560 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
561 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst
562 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst
563 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
564 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst
565 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst
566 system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst
567 system.cpu0.itb.inst_hits 259203584 # ITB inst hits
568 system.cpu0.itb.inst_misses 65048 # ITB inst misses
569 system.cpu0.itb.read_hits 0 # DTB read hits
570 system.cpu0.itb.read_misses 0 # DTB read misses
571 system.cpu0.itb.write_hits 0 # DTB write hits
572 system.cpu0.itb.write_misses 0 # DTB write misses
573 system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
574 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
575 system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
576 system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
577 system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB
578 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
579 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
580 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
581 system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions
582 system.cpu0.itb.read_accesses 0 # DTB read accesses
583 system.cpu0.itb.write_accesses 0 # DTB write accesses
584 system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses
585 system.cpu0.itb.hits 259203584 # DTB hits
586 system.cpu0.itb.misses 65048 # DTB misses
587 system.cpu0.itb.accesses 259268632 # DTB accesses
588 system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions
589 system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state
590 system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state
591 system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state
592 system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state
593 system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state
594 system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state
595 system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
596 system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
597 system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
598 system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
599 system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
600 system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state
601 system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
602 system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state
603 system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state
604 system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states
605 system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states
606 system.cpu0.numCycles 1023758481 # number of cpu cycles simulated
607 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
608 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
609 system.cpu0.committedInsts 483101155 # Number of instructions committed
610 system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed
611 system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit
612 system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching
613 system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
614 system.cpu0.cpi 2.119139 # CPI: cycles per instruction
615 system.cpu0.ipc 0.471890 # IPC: instructions per cycle
616 system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
617 system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction
618 system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction
619 system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction
620 system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
621 system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
622 system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
623 system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
624 system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
625 system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
626 system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
627 system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
628 system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
629 system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
630 system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
631 system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
632 system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
633 system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
634 system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
635 system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
636 system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
637 system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
638 system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
639 system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
640 system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
641 system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
642 system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction
643 system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction
644 system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction
645 system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction
646 system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction
647 system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction
648 system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
649 system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
650 system.cpu0.op_class_0::total 567019823 # Class of committed instruction
651 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
652 system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed
653 system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked
654 system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped
655 system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
656 system.cpu0.dcache.tags.replacements 6026209 # number of replacements
657 system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use
658 system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks.
659 system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks.
660 system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks.
661 system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit.
662 system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor
663 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy
664 system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy
665 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
666 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
667 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
668 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
669 system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
670 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
671 system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses
672 system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses
673 system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
674 system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits
675 system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits
676 system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits
677 system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits
678 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits
679 system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits
680 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits
681 system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits
682 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits
683 system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits
684 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits
685 system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits
686 system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits
687 system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits
688 system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits
689 system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits
690 system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses
691 system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses
692 system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses
693 system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses
694 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses
695 system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses
696 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses
697 system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses
698 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses
699 system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses
700 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses
701 system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses
702 system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses
703 system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses
704 system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses
705 system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses
706 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles
707 system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles
708 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles
709 system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles
710 system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles
711 system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles
712 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles
713 system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles
714 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles
715 system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles
716 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles
717 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles
718 system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles
719 system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles
720 system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles
721 system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles
722 system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses)
723 system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses)
724 system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses)
725 system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses)
726 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses)
727 system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses)
728 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses)
729 system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses)
730 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses)
731 system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses)
732 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses)
733 system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses)
734 system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses
735 system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses
736 system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses
737 system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses
738 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses
739 system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses
740 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses
741 system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses
742 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses
743 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses
744 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses
745 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses
746 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses
747 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses
748 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses
749 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses
750 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses
751 system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses
752 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses
753 system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses
754 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency
755 system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency
756 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency
757 system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency
758 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency
759 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency
760 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency
761 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency
762 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency
763 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency
764 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
765 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
766 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency
767 system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency
768 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency
769 system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency
770 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
771 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
772 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
773 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
774 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
775 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
776 system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks
777 system.cpu0.dcache.writebacks::total 6026220 # number of writebacks
778 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits
779 system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits
780 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits
781 system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits
782 system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits
783 system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits
784 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits
785 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits
786 system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits
787 system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits
788 system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits
789 system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits
790 system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits
791 system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits
792 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses
793 system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses
794 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses
795 system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses
796 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses
797 system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses
798 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses
799 system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses
800 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses
801 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses
802 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses
803 system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses
804 system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses
805 system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses
806 system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses
807 system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses
808 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable
809 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable
810 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable
811 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable
812 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses
813 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses
814 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles
815 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles
816 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles
817 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles
818 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles
819 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles
820 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles
821 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles
822 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles
823 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles
824 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles
825 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles
826 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles
827 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles
828 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles
829 system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles
830 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles
831 system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles
832 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles
833 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles
834 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles
835 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles
836 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses
837 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses
838 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses
839 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses
840 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses
841 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses
842 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses
843 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses
844 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses
845 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses
846 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses
847 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses
848 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses
849 system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses
850 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses
851 system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses
852 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency
853 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency
854 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency
855 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency
856 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency
857 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency
858 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency
859 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency
860 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency
861 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency
862 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency
863 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency
864 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
865 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
866 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency
867 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency
868 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency
869 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency
870 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency
871 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency
872 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency
873 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency
874 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
875 system.cpu0.icache.tags.replacements 9817579 # number of replacements
876 system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use
877 system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks.
878 system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks.
879 system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks.
880 system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit.
881 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor
882 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy
883 system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy
884 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
885 system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
886 system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
887 system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
888 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
889 system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses
890 system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses
891 system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
892 system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits
893 system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits
894 system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits
895 system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits
896 system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits
897 system.cpu0.icache.overall_hits::total 249208397 # number of overall hits
898 system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses
899 system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses
900 system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses
901 system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses
902 system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses
903 system.cpu0.icache.overall_misses::total 9818101 # number of overall misses
904 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles
905 system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles
906 system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles
907 system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles
908 system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles
909 system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles
910 system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses)
911 system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses)
912 system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses
913 system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses
914 system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses
915 system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses
916 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses
917 system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses
918 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses
919 system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses
920 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses
921 system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses
922 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency
923 system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency
924 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency
925 system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency
926 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency
927 system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency
928 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
929 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
930 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
931 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
932 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
933 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
934 system.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks
935 system.cpu0.icache.writebacks::total 9817579 # number of writebacks
936 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses
937 system.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses
938 system.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses
939 system.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses
940 system.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # number of overall MSHR misses
941 system.cpu0.icache.overall_mshr_misses::total 9818101 # number of overall MSHR misses
942 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable
943 system.cpu0.icache.ReadReq_mshr_uncacheable::total 52299 # number of ReadReq MSHR uncacheable
944 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses
945 system.cpu0.icache.overall_mshr_uncacheable_misses::total 52299 # number of overall MSHR uncacheable misses
946 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94093068000 # number of ReadReq MSHR miss cycles
947 system.cpu0.icache.ReadReq_mshr_miss_latency::total 94093068000 # number of ReadReq MSHR miss cycles
948 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94093068000 # number of demand (read+write) MSHR miss cycles
949 system.cpu0.icache.demand_mshr_miss_latency::total 94093068000 # number of demand (read+write) MSHR miss cycles
950 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94093068000 # number of overall MSHR miss cycles
951 system.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles
952 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of ReadReq MSHR uncacheable cycles
953 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4837195500 # number of ReadReq MSHR uncacheable cycles
954 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of overall MSHR uncacheable cycles
955 system.cpu0.icache.overall_mshr_uncacheable_latency::total 4837195500 # number of overall MSHR uncacheable cycles
956 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for ReadReq accesses
957 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037904 # mshr miss rate for ReadReq accesses
958 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for demand accesses
959 system.cpu0.icache.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses
960 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for overall accesses
961 system.cpu0.icache.overall_mshr_miss_rate::total 0.037904 # mshr miss rate for overall accesses
962 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average ReadReq mshr miss latency
963 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9583.632110 # average ReadReq mshr miss latency
964 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency
965 system.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency
966 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency
967 system.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency
968 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency
969 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency
970 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency
971 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency
972 system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
973 system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued
974 system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified
975 system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue
976 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
977 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
978 system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing
979 system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
980 system.cpu0.l2cache.tags.replacements 2829183 # number of replacements
981 system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use
982 system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks.
983 system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks.
984 system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks.
985 system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit.
986 system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor
987 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor
988 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor
989 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor
990 system.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy
991 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy
992 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy
993 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy
994 system.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy
995 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id
996 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id
997 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id
998 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id
999 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id
1000 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id
1001 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id
1002 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id
1003 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
1004 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
1005 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
1006 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id
1007 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id
1008 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id
1009 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id
1010 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id
1011 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id
1012 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id
1013 system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses
1014 system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses
1015 system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1016 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits
1017 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits
1018 system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits
1019 system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits
1020 system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits
1021 system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits
1022 system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits
1023 system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
1024 system.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits
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1026 system.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits
1027 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # number of ReadCleanReq hits
1028 system.cpu0.l2cache.ReadCleanReq_hits::total 9093916 # number of ReadCleanReq hits
1029 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3073539 # number of ReadSharedReq hits
1030 system.cpu0.l2cache.ReadSharedReq_hits::total 3073539 # number of ReadSharedReq hits
1031 system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216814 # number of InvalidateReq hits
1032 system.cpu0.l2cache.InvalidateReq_hits::total 216814 # number of InvalidateReq hits
1033 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 561309 # number of demand (read+write) hits
1034 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167224 # number of demand (read+write) hits
1035 system.cpu0.l2cache.demand_hits::cpu0.inst 9093916 # number of demand (read+write) hits
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1038 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 561309 # number of overall hits
1039 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167224 # number of overall hits
1040 system.cpu0.l2cache.overall_hits::cpu0.inst 9093916 # number of overall hits
1041 system.cpu0.l2cache.overall_hits::cpu0.data 4006713 # number of overall hits
1042 system.cpu0.l2cache.overall_hits::total 13829162 # number of overall hits
1043 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12299 # number of ReadReq misses
1044 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8468 # number of ReadReq misses
1045 system.cpu0.l2cache.ReadReq_misses::total 20767 # number of ReadReq misses
1046 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256901 # number of UpgradeReq misses
1047 system.cpu0.l2cache.UpgradeReq_misses::total 256901 # number of UpgradeReq misses
1048 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195411 # number of SCUpgradeReq misses
1049 system.cpu0.l2cache.SCUpgradeReq_misses::total 195411 # number of SCUpgradeReq misses
1050 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
1051 system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
1052 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 279617 # number of ReadExReq misses
1053 system.cpu0.l2cache.ReadExReq_misses::total 279617 # number of ReadExReq misses
1054 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 724184 # number of ReadCleanReq misses
1055 system.cpu0.l2cache.ReadCleanReq_misses::total 724184 # number of ReadCleanReq misses
1056 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1019232 # number of ReadSharedReq misses
1057 system.cpu0.l2cache.ReadSharedReq_misses::total 1019232 # number of ReadSharedReq misses
1058 system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608335 # number of InvalidateReq misses
1059 system.cpu0.l2cache.InvalidateReq_misses::total 608335 # number of InvalidateReq misses
1060 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12299 # number of demand (read+write) misses
1061 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8468 # number of demand (read+write) misses
1062 system.cpu0.l2cache.demand_misses::cpu0.inst 724184 # number of demand (read+write) misses
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1065 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12299 # number of overall misses
1066 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8468 # number of overall misses
1067 system.cpu0.l2cache.overall_misses::cpu0.inst 724184 # number of overall misses
1068 system.cpu0.l2cache.overall_misses::cpu0.data 1298849 # number of overall misses
1069 system.cpu0.l2cache.overall_misses::total 2043800 # number of overall misses
1070 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 444586500 # number of ReadReq miss cycles
1071 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 341709500 # number of ReadReq miss cycles
1072 system.cpu0.l2cache.ReadReq_miss_latency::total 786296000 # number of ReadReq miss cycles
1073 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2032659000 # number of UpgradeReq miss cycles
1074 system.cpu0.l2cache.UpgradeReq_miss_latency::total 2032659000 # number of UpgradeReq miss cycles
1075 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1558169000 # number of SCUpgradeReq miss cycles
1076 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1558169000 # number of SCUpgradeReq miss cycles
1077 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3166000 # number of SCUpgradeFailReq miss cycles
1078 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3166000 # number of SCUpgradeFailReq miss cycles
1079 system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14018472997 # number of ReadExReq miss cycles
1080 system.cpu0.l2cache.ReadExReq_miss_latency::total 14018472997 # number of ReadExReq miss cycles
1081 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24426242000 # number of ReadCleanReq miss cycles
1082 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24426242000 # number of ReadCleanReq miss cycles
1083 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35646536993 # number of ReadSharedReq miss cycles
1084 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35646536993 # number of ReadSharedReq miss cycles
1085 system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333062000 # number of InvalidateReq miss cycles
1086 system.cpu0.l2cache.InvalidateReq_miss_latency::total 333062000 # number of InvalidateReq miss cycles
1087 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 444586500 # number of demand (read+write) miss cycles
1088 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 341709500 # number of demand (read+write) miss cycles
1089 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24426242000 # number of demand (read+write) miss cycles
1090 system.cpu0.l2cache.demand_miss_latency::cpu0.data 49665009990 # number of demand (read+write) miss cycles
1091 system.cpu0.l2cache.demand_miss_latency::total 74877547990 # number of demand (read+write) miss cycles
1092 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 444586500 # number of overall miss cycles
1093 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 341709500 # number of overall miss cycles
1094 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24426242000 # number of overall miss cycles
1095 system.cpu0.l2cache.overall_miss_latency::cpu0.data 49665009990 # number of overall miss cycles
1096 system.cpu0.l2cache.overall_miss_latency::total 74877547990 # number of overall miss cycles
1097 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 573608 # number of ReadReq accesses(hits+misses)
1098 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175692 # number of ReadReq accesses(hits+misses)
1099 system.cpu0.l2cache.ReadReq_accesses::total 749300 # number of ReadReq accesses(hits+misses)
1100 system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3942058 # number of WritebackDirty accesses(hits+misses)
1101 system.cpu0.l2cache.WritebackDirty_accesses::total 3942058 # number of WritebackDirty accesses(hits+misses)
1102 system.cpu0.l2cache.WritebackClean_accesses::writebacks 11898812 # number of WritebackClean accesses(hits+misses)
1103 system.cpu0.l2cache.WritebackClean_accesses::total 11898812 # number of WritebackClean accesses(hits+misses)
1104 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257512 # number of UpgradeReq accesses(hits+misses)
1105 system.cpu0.l2cache.UpgradeReq_accesses::total 257512 # number of UpgradeReq accesses(hits+misses)
1106 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195411 # number of SCUpgradeReq accesses(hits+misses)
1107 system.cpu0.l2cache.SCUpgradeReq_accesses::total 195411 # number of SCUpgradeReq accesses(hits+misses)
1108 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
1109 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
1110 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1212791 # number of ReadExReq accesses(hits+misses)
1111 system.cpu0.l2cache.ReadExReq_accesses::total 1212791 # number of ReadExReq accesses(hits+misses)
1112 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9818100 # number of ReadCleanReq accesses(hits+misses)
1113 system.cpu0.l2cache.ReadCleanReq_accesses::total 9818100 # number of ReadCleanReq accesses(hits+misses)
1114 system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4092771 # number of ReadSharedReq accesses(hits+misses)
1115 system.cpu0.l2cache.ReadSharedReq_accesses::total 4092771 # number of ReadSharedReq accesses(hits+misses)
1116 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 825149 # number of InvalidateReq accesses(hits+misses)
1117 system.cpu0.l2cache.InvalidateReq_accesses::total 825149 # number of InvalidateReq accesses(hits+misses)
1118 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 573608 # number of demand (read+write) accesses
1119 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175692 # number of demand (read+write) accesses
1120 system.cpu0.l2cache.demand_accesses::cpu0.inst 9818100 # number of demand (read+write) accesses
1121 system.cpu0.l2cache.demand_accesses::cpu0.data 5305562 # number of demand (read+write) accesses
1122 system.cpu0.l2cache.demand_accesses::total 15872962 # number of demand (read+write) accesses
1123 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 573608 # number of overall (read+write) accesses
1124 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175692 # number of overall (read+write) accesses
1125 system.cpu0.l2cache.overall_accesses::cpu0.inst 9818100 # number of overall (read+write) accesses
1126 system.cpu0.l2cache.overall_accesses::cpu0.data 5305562 # number of overall (read+write) accesses
1127 system.cpu0.l2cache.overall_accesses::total 15872962 # number of overall (read+write) accesses
1128 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for ReadReq accesses
1129 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048198 # miss rate for ReadReq accesses
1130 system.cpu0.l2cache.ReadReq_miss_rate::total 0.027715 # miss rate for ReadReq accesses
1131 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997627 # miss rate for UpgradeReq accesses
1132 system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997627 # miss rate for UpgradeReq accesses
1133 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1134 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1135 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1136 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1137 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230557 # miss rate for ReadExReq accesses
1138 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230557 # miss rate for ReadExReq accesses
1139 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073760 # miss rate for ReadCleanReq accesses
1140 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073760 # miss rate for ReadCleanReq accesses
1141 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.249032 # miss rate for ReadSharedReq accesses
1142 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.249032 # miss rate for ReadSharedReq accesses
1143 system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.737243 # miss rate for InvalidateReq accesses
1144 system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.737243 # miss rate for InvalidateReq accesses
1145 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for demand accesses
1146 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048198 # miss rate for demand accesses
1147 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073760 # miss rate for demand accesses
1148 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.244809 # miss rate for demand accesses
1149 system.cpu0.l2cache.demand_miss_rate::total 0.128760 # miss rate for demand accesses
1150 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for overall accesses
1151 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048198 # miss rate for overall accesses
1152 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073760 # miss rate for overall accesses
1153 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.244809 # miss rate for overall accesses
1154 system.cpu0.l2cache.overall_miss_rate::total 0.128760 # miss rate for overall accesses
1155 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average ReadReq miss latency
1156 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40353.034955 # average ReadReq miss latency
1157 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37862.763038 # average ReadReq miss latency
1158 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7912.226889 # average UpgradeReq miss latency
1159 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7912.226889 # average UpgradeReq miss latency
1160 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7973.803931 # average SCUpgradeReq miss latency
1161 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7973.803931 # average SCUpgradeReq miss latency
1162 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 527666.666667 # average SCUpgradeFailReq miss latency
1163 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 527666.666667 # average SCUpgradeFailReq miss latency
1164 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50134.551894 # average ReadExReq miss latency
1165 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50134.551894 # average ReadExReq miss latency
1166 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33729.331220 # average ReadCleanReq miss latency
1167 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33729.331220 # average ReadCleanReq miss latency
1168 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34973.918591 # average ReadSharedReq miss latency
1169 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34973.918591 # average ReadSharedReq miss latency
1170 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 547.497678 # average InvalidateReq miss latency
1171 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 547.497678 # average InvalidateReq miss latency
1172 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency
1173 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency
1174 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency
1175 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency
1176 system.cpu0.l2cache.demand_avg_miss_latency::total 36636.436046 # average overall miss latency
1177 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency
1178 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency
1179 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency
1180 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency
1181 system.cpu0.l2cache.overall_avg_miss_latency::total 36636.436046 # average overall miss latency
1182 system.cpu0.l2cache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked
1183 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1184 system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1185 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1186 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked
1187 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1188 system.cpu0.l2cache.unused_prefetches 48128 # number of HardPF blocks evicted w/o reference
1189 system.cpu0.l2cache.writebacks::writebacks 1646117 # number of writebacks
1190 system.cpu0.l2cache.writebacks::total 1646117 # number of writebacks
1191 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
1192 system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1193 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9808 # number of ReadExReq MSHR hits
1194 system.cpu0.l2cache.ReadExReq_mshr_hits::total 9808 # number of ReadExReq MSHR hits
1195 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
1196 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1197 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 898 # number of ReadSharedReq MSHR hits
1198 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 898 # number of ReadSharedReq MSHR hits
1199 system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
1200 system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
1201 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
1202 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
1203 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10706 # number of demand (read+write) MSHR hits
1204 system.cpu0.l2cache.demand_mshr_hits::total 10718 # number of demand (read+write) MSHR hits
1205 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
1206 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
1207 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10706 # number of overall MSHR hits
1208 system.cpu0.l2cache.overall_mshr_hits::total 10718 # number of overall MSHR hits
1209 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12299 # number of ReadReq MSHR misses
1210 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8465 # number of ReadReq MSHR misses
1211 system.cpu0.l2cache.ReadReq_mshr_misses::total 20764 # number of ReadReq MSHR misses
1212 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of HardPFReq MSHR misses
1213 system.cpu0.l2cache.HardPFReq_mshr_misses::total 828377 # number of HardPFReq MSHR misses
1214 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 256901 # number of UpgradeReq MSHR misses
1215 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 256901 # number of UpgradeReq MSHR misses
1216 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195411 # number of SCUpgradeReq MSHR misses
1217 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195411 # number of SCUpgradeReq MSHR misses
1218 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
1219 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
1220 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269809 # number of ReadExReq MSHR misses
1221 system.cpu0.l2cache.ReadExReq_mshr_misses::total 269809 # number of ReadExReq MSHR misses
1222 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 724175 # number of ReadCleanReq MSHR misses
1223 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 724175 # number of ReadCleanReq MSHR misses
1224 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018334 # number of ReadSharedReq MSHR misses
1225 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018334 # number of ReadSharedReq MSHR misses
1226 system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 608332 # number of InvalidateReq MSHR misses
1227 system.cpu0.l2cache.InvalidateReq_mshr_misses::total 608332 # number of InvalidateReq MSHR misses
1228 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12299 # number of demand (read+write) MSHR misses
1229 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8465 # number of demand (read+write) MSHR misses
1230 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 724175 # number of demand (read+write) MSHR misses
1231 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1288143 # number of demand (read+write) MSHR misses
1232 system.cpu0.l2cache.demand_mshr_misses::total 2033082 # number of demand (read+write) MSHR misses
1233 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12299 # number of overall MSHR misses
1234 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8465 # number of overall MSHR misses
1235 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 724175 # number of overall MSHR misses
1236 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1288143 # number of overall MSHR misses
1237 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of overall MSHR misses
1238 system.cpu0.l2cache.overall_mshr_misses::total 2861459 # number of overall MSHR misses
1239 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable
1240 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable
1241 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84001 # number of ReadReq MSHR uncacheable
1242 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable
1243 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable
1244 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses
1245 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses
1246 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115226 # number of overall MSHR uncacheable misses
1247 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of ReadReq MSHR miss cycles
1248 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290829500 # number of ReadReq MSHR miss cycles
1249 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 661622000 # number of ReadReq MSHR miss cycles
1250 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of HardPFReq MSHR miss cycles
1251 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38426708957 # number of HardPFReq MSHR miss cycles
1252 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5314605493 # number of UpgradeReq MSHR miss cycles
1253 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5314605493 # number of UpgradeReq MSHR miss cycles
1254 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3216326998 # number of SCUpgradeReq MSHR miss cycles
1255 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3216326998 # number of SCUpgradeReq MSHR miss cycles
1256 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770000 # number of SCUpgradeFailReq MSHR miss cycles
1257 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770000 # number of SCUpgradeFailReq MSHR miss cycles
1258 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11196985497 # number of ReadExReq MSHR miss cycles
1259 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11196985497 # number of ReadExReq MSHR miss cycles
1260 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20080949000 # number of ReadCleanReq MSHR miss cycles
1261 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20080949000 # number of ReadCleanReq MSHR miss cycles
1262 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29451947493 # number of ReadSharedReq MSHR miss cycles
1263 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29451947493 # number of ReadSharedReq MSHR miss cycles
1264 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20309675000 # number of InvalidateReq MSHR miss cycles
1265 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20309675000 # number of InvalidateReq MSHR miss cycles
1266 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of demand (read+write) MSHR miss cycles
1267 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290829500 # number of demand (read+write) MSHR miss cycles
1268 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20080949000 # number of demand (read+write) MSHR miss cycles
1269 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 40648932990 # number of demand (read+write) MSHR miss cycles
1270 system.cpu0.l2cache.demand_mshr_miss_latency::total 61391503990 # number of demand (read+write) MSHR miss cycles
1271 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of overall MSHR miss cycles
1272 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290829500 # number of overall MSHR miss cycles
1273 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20080949000 # number of overall MSHR miss cycles
1274 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 40648932990 # number of overall MSHR miss cycles
1275 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of overall MSHR miss cycles
1276 system.cpu0.l2cache.overall_mshr_miss_latency::total 99818212947 # number of overall MSHR miss cycles
1277 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of ReadReq MSHR uncacheable cycles
1278 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5883144500 # number of ReadReq MSHR uncacheable cycles
1279 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles
1280 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles
1281 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles
1282 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles
1283 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses
1284 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses
1285 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses
1286 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1287 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1288 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses
1289 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses
1290 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1291 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1292 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1293 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1294 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses
1295 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses
1296 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses
1297 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses
1298 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses
1299 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses
1300 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses
1301 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses
1302 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses
1303 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses
1304 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses
1305 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses
1306 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses
1307 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses
1308 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses
1309 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses
1310 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses
1311 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1312 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses
1313 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency
1314 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency
1315 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency
1316 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency
1317 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency
1318 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency
1319 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency
1320 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency
1321 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency
1322 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency
1323 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency
1324 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency
1325 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency
1326 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency
1327 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency
1328 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency
1329 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency
1330 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency
1331 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency
1332 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency
1333 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency
1334 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency
1335 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency
1336 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency
1337 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency
1338 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency
1339 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency
1340 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency
1341 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency
1342 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency
1343 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency
1344 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency
1345 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency
1346 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency
1347 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency
1348 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency
1349 system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter.
1350 system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1351 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1352 system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter.
1353 system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1354 system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1355 system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1356 system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution
1357 system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution
1358 system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1359 system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution
1360 system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution
1361 system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution
1362 system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution
1363 system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution
1364 system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution
1365 system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
1366 system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution
1367 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution
1368 system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution
1369 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution
1370 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
1371 system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution
1372 system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution
1373 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution
1374 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution
1375 system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution
1376 system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution
1377 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes)
1378 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes)
1379 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes)
1380 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes)
1381 system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes)
1382 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes)
1383 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes)
1384 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes)
1385 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes)
1386 system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes)
1387 system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count)
1388 system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram
1389 system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram
1390 system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram
1391 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1392 system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram
1393 system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram
1394 system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram
1395 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1396 system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1397 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1398 system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram
1399 system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks)
1400 system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1401 system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks)
1402 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1403 system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks)
1404 system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1405 system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks)
1406 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1407 system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks)
1408 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1409 system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks)
1410 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1411 system.cpu1.branchPred.lookups 123875539 # Number of BP lookups
1412 system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted
1413 system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect
1414 system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups
1415 system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits
1416 system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1417 system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage
1418 system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target.
1419 system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions.
1420 system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups.
1421 system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits.
1422 system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses.
1423 system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches.
1424 system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1425 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1426 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1427 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1428 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1429 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1430 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1431 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1432 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1433 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1434 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1435 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1436 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1437 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1438 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1439 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1440 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1441 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1442 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1443 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1444 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1445 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1446 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1447 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1448 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1449 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1450 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1451 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1452 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1453 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1454 system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1455 system.cpu1.dtb.walker.walks 255224 # Table walker walks requested
1456 system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors
1457 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate
1458 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate
1459 system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency
1460 system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1461 system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency
1462 system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency
1463 system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency
1464 system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency
1465 system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency
1466 system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency
1467 system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency
1468 system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency
1469 system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency
1470 system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency
1471 system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency
1472 system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
1473 system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
1474 system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1475 system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency
1476 system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution
1477 system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution
1478 system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution
1479 system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated
1480 system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated
1481 system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated
1482 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst
1483 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1484 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst
1485 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst
1486 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1487 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst
1488 system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst
1489 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1490 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1491 system.cpu1.dtb.read_hits 78594683 # DTB read hits
1492 system.cpu1.dtb.read_misses 208094 # DTB read misses
1493 system.cpu1.dtb.write_hits 69544419 # DTB write hits
1494 system.cpu1.dtb.write_misses 47130 # DTB write misses
1495 system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1496 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1497 system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
1498 system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1499 system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB
1500 system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions
1501 system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch
1502 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1503 system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions
1504 system.cpu1.dtb.read_accesses 78802777 # DTB read accesses
1505 system.cpu1.dtb.write_accesses 69591549 # DTB write accesses
1506 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1507 system.cpu1.dtb.hits 148139102 # DTB hits
1508 system.cpu1.dtb.misses 255224 # DTB misses
1509 system.cpu1.dtb.accesses 148394326 # DTB accesses
1510 system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1511 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1512 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1513 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1514 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1515 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1516 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1517 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1518 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1519 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1520 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1521 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1522 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1523 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1524 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1525 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1526 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1527 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1528 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1529 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1530 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1531 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1532 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1533 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1534 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1535 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1536 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1537 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1538 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1539 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1540 system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1541 system.cpu1.itb.walker.walks 62177 # Table walker walks requested
1542 system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors
1543 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate
1544 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate
1545 system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency
1546 system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1547 system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency
1548 system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency
1549 system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency
1550 system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency
1551 system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency
1552 system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency
1553 system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency
1554 system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency
1555 system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency
1556 system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency
1557 system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency
1558 system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency
1559 system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency
1560 system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency
1561 system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
1562 system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
1563 system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
1564 system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1565 system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1566 system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency
1567 system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution
1568 system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution
1569 system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution
1570 system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated
1571 system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated
1572 system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated
1573 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1574 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst
1575 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst
1576 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1577 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst
1578 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst
1579 system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst
1580 system.cpu1.itb.inst_hits 219337574 # ITB inst hits
1581 system.cpu1.itb.inst_misses 62177 # ITB inst misses
1582 system.cpu1.itb.read_hits 0 # DTB read hits
1583 system.cpu1.itb.read_misses 0 # DTB read misses
1584 system.cpu1.itb.write_hits 0 # DTB write hits
1585 system.cpu1.itb.write_misses 0 # DTB write misses
1586 system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1587 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1588 system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
1589 system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1590 system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB
1591 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1592 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1593 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1594 system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions
1595 system.cpu1.itb.read_accesses 0 # DTB read accesses
1596 system.cpu1.itb.write_accesses 0 # DTB write accesses
1597 system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses
1598 system.cpu1.itb.hits 219337574 # DTB hits
1599 system.cpu1.itb.misses 62177 # DTB misses
1600 system.cpu1.itb.accesses 219399751 # DTB accesses
1601 system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions
1602 system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state
1603 system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state
1604 system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state
1605 system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state
1606 system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state
1607 system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state
1608 system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state
1609 system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state
1610 system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
1611 system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
1612 system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
1613 system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state
1614 system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
1615 system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state
1616 system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state
1617 system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states
1618 system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states
1619 system.cpu1.numCycles 838096745 # number of cpu cycles simulated
1620 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1621 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1622 system.cpu1.committedInsts 400342475 # Number of instructions committed
1623 system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed
1624 system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit
1625 system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching
1626 system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1627 system.cpu1.cpi 2.093449 # CPI: cycles per instruction
1628 system.cpu1.ipc 0.477681 # IPC: instructions per cycle
1629 system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1630 system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction
1631 system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction
1632 system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction
1633 system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction
1634 system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction
1635 system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction
1636 system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction
1637 system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction
1638 system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction
1639 system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction
1640 system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction
1641 system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction
1642 system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction
1643 system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction
1644 system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction
1645 system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction
1646 system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction
1647 system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction
1648 system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction
1649 system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction
1650 system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction
1651 system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction
1652 system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction
1653 system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction
1654 system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction
1655 system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction
1656 system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction
1657 system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction
1658 system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction
1659 system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction
1660 system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction
1661 system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1662 system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1663 system.cpu1.op_class_0::total 472062345 # Class of committed instruction
1664 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1665 system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed
1666 system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked
1667 system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped
1668 system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1669 system.cpu1.dcache.tags.replacements 4810857 # number of replacements
1670 system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use
1671 system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks.
1672 system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks.
1673 system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks.
1674 system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit.
1675 system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor
1676 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy
1677 system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy
1678 system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
1679 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
1680 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
1681 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
1682 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
1683 system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses
1684 system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses
1685 system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1686 system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits
1687 system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits
1688 system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits
1689 system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits
1690 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits
1691 system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits
1692 system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits
1693 system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits
1694 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits
1695 system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits
1696 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits
1697 system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits
1698 system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits
1699 system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits
1700 system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits
1701 system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits
1702 system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses
1703 system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses
1704 system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses
1705 system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses
1706 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses
1707 system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses
1708 system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses
1709 system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses
1710 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses
1711 system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses
1712 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses
1713 system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses
1714 system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses
1715 system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses
1716 system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses
1717 system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses
1718 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles
1719 system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles
1720 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles
1721 system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles
1722 system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles
1723 system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles
1724 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles
1725 system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles
1726 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles
1727 system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles
1728 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles
1729 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles
1730 system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles
1731 system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles
1732 system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles
1733 system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles
1734 system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses)
1735 system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses)
1736 system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses)
1737 system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses)
1738 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses)
1739 system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses)
1740 system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses)
1741 system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses)
1742 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses)
1743 system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses)
1744 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses)
1745 system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses)
1746 system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses
1747 system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses
1748 system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses
1749 system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses
1750 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses
1751 system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses
1752 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses
1753 system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses
1754 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses
1755 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses
1756 system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses
1757 system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses
1758 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses
1759 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses
1760 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses
1761 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses
1762 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses
1763 system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses
1764 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses
1765 system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses
1766 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency
1767 system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency
1768 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency
1769 system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency
1770 system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency
1771 system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency
1772 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency
1773 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency
1774 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency
1775 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency
1776 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1777 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1778 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency
1779 system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency
1780 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency
1781 system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency
1782 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1783 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1784 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1785 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1786 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1787 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1788 system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks
1789 system.cpu1.dcache.writebacks::total 4810864 # number of writebacks
1790 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits
1791 system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits
1792 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits
1793 system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits
1794 system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits
1795 system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits
1796 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits
1797 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits
1798 system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits
1799 system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
1800 system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits
1801 system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits
1802 system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits
1803 system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits
1804 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses
1805 system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses
1806 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses
1807 system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses
1808 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses
1809 system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses
1810 system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses
1811 system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses
1812 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses
1813 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses
1814 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses
1815 system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses
1816 system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses
1817 system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses
1818 system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses
1819 system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses
1820 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable
1821 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable
1822 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable
1823 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable
1824 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses
1825 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses
1826 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles
1827 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles
1828 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles
1829 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles
1830 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles
1831 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles
1832 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles
1833 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles
1834 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles
1835 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles
1836 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles
1837 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles
1838 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles
1839 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles
1840 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles
1841 system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles
1842 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles
1843 system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles
1844 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles
1845 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles
1846 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles
1847 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles
1848 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses
1849 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses
1850 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses
1851 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses
1852 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses
1853 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses
1854 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses
1855 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses
1856 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses
1857 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses
1858 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses
1859 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses
1860 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses
1861 system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses
1862 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses
1863 system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses
1864 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency
1865 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency
1866 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency
1867 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency
1868 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency
1869 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency
1870 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency
1871 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency
1872 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency
1873 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency
1874 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency
1875 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency
1876 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1877 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1878 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency
1879 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency
1880 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency
1881 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency
1882 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency
1883 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency
1884 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency
1885 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency
1886 system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1887 system.cpu1.icache.tags.replacements 8744967 # number of replacements
1888 system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use
1889 system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks.
1890 system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks.
1891 system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks.
1892 system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit.
1893 system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor
1894 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy
1895 system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy
1896 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1897 system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
1898 system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
1899 system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
1900 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1901 system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses
1902 system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses
1903 system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1904 system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits
1905 system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits
1906 system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits
1907 system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits
1908 system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits
1909 system.cpu1.icache.overall_hits::total 210419103 # number of overall hits
1910 system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses
1911 system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses
1912 system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses
1913 system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses
1914 system.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses
1915 system.cpu1.icache.overall_misses::total 8745479 # number of overall misses
1916 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles
1917 system.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles
1918 system.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles
1919 system.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles
1920 system.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles
1921 system.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles
1922 system.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses)
1923 system.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses)
1924 system.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses
1925 system.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses
1926 system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses
1927 system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses
1928 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses
1929 system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses
1930 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses
1931 system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses
1932 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses
1933 system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses
1934 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency
1935 system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency
1936 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency
1937 system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency
1938 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency
1939 system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency
1940 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1941 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1942 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1943 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1944 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1945 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1946 system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks
1947 system.cpu1.icache.writebacks::total 8744967 # number of writebacks
1948 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses
1949 system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses
1950 system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses
1951 system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses
1952 system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses
1953 system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses
1954 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
1955 system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
1956 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
1957 system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
1958 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles
1959 system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles
1960 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles
1961 system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles
1962 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles
1963 system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles
1964 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles
1965 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles
1966 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles
1967 system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles
1968 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses
1969 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses
1970 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses
1971 system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses
1972 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses
1973 system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses
1974 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency
1975 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency
1976 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency
1977 system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency
1978 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency
1979 system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency
1980 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency
1981 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency
1982 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency
1983 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency
1984 system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1985 system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued
1986 system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified
1987 system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue
1988 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1989 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1990 system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing
1991 system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
1992 system.cpu1.l2cache.tags.replacements 2218428 # number of replacements
1993 system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use
1994 system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks.
1995 system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks.
1996 system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks.
1997 system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit.
1998 system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor
1999 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor
2000 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor
2001 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor
2002 system.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy
2003 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy
2004 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy
2005 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy
2006 system.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy
2007 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id
2008 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id
2009 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id
2010 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id
2011 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id
2012 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id
2013 system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
2014 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id
2015 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2016 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
2017 system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
2018 system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
2019 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id
2020 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id
2021 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id
2022 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id
2023 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id
2024 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id
2025 system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses
2026 system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses
2027 system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2028 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits
2029 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits
2030 system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits
2031 system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits
2032 system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits
2033 system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits
2034 system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits
2035 system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits
2036 system.cpu1.l2cache.UpgradeReq_hits::total 434 # number of UpgradeReq hits
2037 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 789107 # number of ReadExReq hits
2038 system.cpu1.l2cache.ReadExReq_hits::total 789107 # number of ReadExReq hits
2039 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8072877 # number of ReadCleanReq hits
2040 system.cpu1.l2cache.ReadCleanReq_hits::total 8072877 # number of ReadCleanReq hits
2041 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2507088 # number of ReadSharedReq hits
2042 system.cpu1.l2cache.ReadSharedReq_hits::total 2507088 # number of ReadSharedReq hits
2043 system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 171056 # number of InvalidateReq hits
2044 system.cpu1.l2cache.InvalidateReq_hits::total 171056 # number of InvalidateReq hits
2045 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 494400 # number of demand (read+write) hits
2046 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160613 # number of demand (read+write) hits
2047 system.cpu1.l2cache.demand_hits::cpu1.inst 8072877 # number of demand (read+write) hits
2048 system.cpu1.l2cache.demand_hits::cpu1.data 3296195 # number of demand (read+write) hits
2049 system.cpu1.l2cache.demand_hits::total 12024085 # number of demand (read+write) hits
2050 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 494400 # number of overall hits
2051 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160613 # number of overall hits
2052 system.cpu1.l2cache.overall_hits::cpu1.inst 8072877 # number of overall hits
2053 system.cpu1.l2cache.overall_hits::cpu1.data 3296195 # number of overall hits
2054 system.cpu1.l2cache.overall_hits::total 12024085 # number of overall hits
2055 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11721 # number of ReadReq misses
2056 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8689 # number of ReadReq misses
2057 system.cpu1.l2cache.ReadReq_misses::total 20410 # number of ReadReq misses
2058 system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
2059 system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
2060 system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
2061 system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
2062 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 220631 # number of UpgradeReq misses
2063 system.cpu1.l2cache.UpgradeReq_misses::total 220631 # number of UpgradeReq misses
2064 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192879 # number of SCUpgradeReq misses
2065 system.cpu1.l2cache.SCUpgradeReq_misses::total 192879 # number of SCUpgradeReq misses
2066 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses
2067 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
2068 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 261966 # number of ReadExReq misses
2069 system.cpu1.l2cache.ReadExReq_misses::total 261966 # number of ReadExReq misses
2070 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 672602 # number of ReadCleanReq misses
2071 system.cpu1.l2cache.ReadCleanReq_misses::total 672602 # number of ReadCleanReq misses
2072 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 931427 # number of ReadSharedReq misses
2073 system.cpu1.l2cache.ReadSharedReq_misses::total 931427 # number of ReadSharedReq misses
2074 system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242391 # number of InvalidateReq misses
2075 system.cpu1.l2cache.InvalidateReq_misses::total 242391 # number of InvalidateReq misses
2076 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11721 # number of demand (read+write) misses
2077 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8689 # number of demand (read+write) misses
2078 system.cpu1.l2cache.demand_misses::cpu1.inst 672602 # number of demand (read+write) misses
2079 system.cpu1.l2cache.demand_misses::cpu1.data 1193393 # number of demand (read+write) misses
2080 system.cpu1.l2cache.demand_misses::total 1886405 # number of demand (read+write) misses
2081 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11721 # number of overall misses
2082 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8689 # number of overall misses
2083 system.cpu1.l2cache.overall_misses::cpu1.inst 672602 # number of overall misses
2084 system.cpu1.l2cache.overall_misses::cpu1.data 1193393 # number of overall misses
2085 system.cpu1.l2cache.overall_misses::total 1886405 # number of overall misses
2086 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 429270500 # number of ReadReq miss cycles
2087 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 326619000 # number of ReadReq miss cycles
2088 system.cpu1.l2cache.ReadReq_miss_latency::total 755889500 # number of ReadReq miss cycles
2089 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1918862500 # number of UpgradeReq miss cycles
2090 system.cpu1.l2cache.UpgradeReq_miss_latency::total 1918862500 # number of UpgradeReq miss cycles
2091 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1442678000 # number of SCUpgradeReq miss cycles
2092 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1442678000 # number of SCUpgradeReq miss cycles
2093 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2273499 # number of SCUpgradeFailReq miss cycles
2094 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2273499 # number of SCUpgradeFailReq miss cycles
2095 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10385042497 # number of ReadExReq miss cycles
2096 system.cpu1.l2cache.ReadExReq_miss_latency::total 10385042497 # number of ReadExReq miss cycles
2097 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22017991000 # number of ReadCleanReq miss cycles
2098 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22017991000 # number of ReadCleanReq miss cycles
2099 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30592821494 # number of ReadSharedReq miss cycles
2100 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30592821494 # number of ReadSharedReq miss cycles
2101 system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 352126000 # number of InvalidateReq miss cycles
2102 system.cpu1.l2cache.InvalidateReq_miss_latency::total 352126000 # number of InvalidateReq miss cycles
2103 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 429270500 # number of demand (read+write) miss cycles
2104 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 326619000 # number of demand (read+write) miss cycles
2105 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22017991000 # number of demand (read+write) miss cycles
2106 system.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles
2107 system.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles
2108 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles
2109 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles
2110 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles
2111 system.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles
2112 system.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles
2113 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses)
2114 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses)
2115 system.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses)
2116 system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses)
2117 system.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses)
2118 system.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses)
2119 system.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses)
2120 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses)
2121 system.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses)
2122 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses)
2123 system.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses)
2124 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
2125 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
2126 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051073 # number of ReadExReq accesses(hits+misses)
2127 system.cpu1.l2cache.ReadExReq_accesses::total 1051073 # number of ReadExReq accesses(hits+misses)
2128 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8745479 # number of ReadCleanReq accesses(hits+misses)
2129 system.cpu1.l2cache.ReadCleanReq_accesses::total 8745479 # number of ReadCleanReq accesses(hits+misses)
2130 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3438515 # number of ReadSharedReq accesses(hits+misses)
2131 system.cpu1.l2cache.ReadSharedReq_accesses::total 3438515 # number of ReadSharedReq accesses(hits+misses)
2132 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 413447 # number of InvalidateReq accesses(hits+misses)
2133 system.cpu1.l2cache.InvalidateReq_accesses::total 413447 # number of InvalidateReq accesses(hits+misses)
2134 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 506121 # number of demand (read+write) accesses
2135 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169302 # number of demand (read+write) accesses
2136 system.cpu1.l2cache.demand_accesses::cpu1.inst 8745479 # number of demand (read+write) accesses
2137 system.cpu1.l2cache.demand_accesses::cpu1.data 4489588 # number of demand (read+write) accesses
2138 system.cpu1.l2cache.demand_accesses::total 13910490 # number of demand (read+write) accesses
2139 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 506121 # number of overall (read+write) accesses
2140 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169302 # number of overall (read+write) accesses
2141 system.cpu1.l2cache.overall_accesses::cpu1.inst 8745479 # number of overall (read+write) accesses
2142 system.cpu1.l2cache.overall_accesses::cpu1.data 4489588 # number of overall (read+write) accesses
2143 system.cpu1.l2cache.overall_accesses::total 13910490 # number of overall (read+write) accesses
2144 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for ReadReq accesses
2145 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051322 # miss rate for ReadReq accesses
2146 system.cpu1.l2cache.ReadReq_miss_rate::total 0.030218 # miss rate for ReadReq accesses
2147 system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
2148 system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
2149 system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
2150 system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
2151 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998037 # miss rate for UpgradeReq accesses
2152 system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998037 # miss rate for UpgradeReq accesses
2153 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2154 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2155 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2156 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2157 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.249237 # miss rate for ReadExReq accesses
2158 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.249237 # miss rate for ReadExReq accesses
2159 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076909 # miss rate for ReadCleanReq accesses
2160 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076909 # miss rate for ReadCleanReq accesses
2161 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.270881 # miss rate for ReadSharedReq accesses
2162 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.270881 # miss rate for ReadSharedReq accesses
2163 system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.586269 # miss rate for InvalidateReq accesses
2164 system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.586269 # miss rate for InvalidateReq accesses
2165 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for demand accesses
2166 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051322 # miss rate for demand accesses
2167 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076909 # miss rate for demand accesses
2168 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265813 # miss rate for demand accesses
2169 system.cpu1.l2cache.demand_miss_rate::total 0.135610 # miss rate for demand accesses
2170 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for overall accesses
2171 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051322 # miss rate for overall accesses
2172 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076909 # miss rate for overall accesses
2173 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265813 # miss rate for overall accesses
2174 system.cpu1.l2cache.overall_miss_rate::total 0.135610 # miss rate for overall accesses
2175 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average ReadReq miss latency
2176 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37589.941305 # average ReadReq miss latency
2177 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37035.252327 # average ReadReq miss latency
2178 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8697.157244 # average UpgradeReq miss latency
2179 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8697.157244 # average UpgradeReq miss latency
2180 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7479.704893 # average SCUpgradeReq miss latency
2181 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7479.704893 # average SCUpgradeReq miss latency
2182 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 568374.750000 # average SCUpgradeFailReq miss latency
2183 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 568374.750000 # average SCUpgradeFailReq miss latency
2184 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39642.711256 # average ReadExReq miss latency
2185 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39642.711256 # average ReadExReq miss latency
2186 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32735.541970 # average ReadCleanReq miss latency
2187 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32735.541970 # average ReadCleanReq miss latency
2188 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32845.109165 # average ReadSharedReq miss latency
2189 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32845.109165 # average ReadSharedReq miss latency
2190 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1452.718954 # average InvalidateReq miss latency
2191 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1452.718954 # average InvalidateReq miss latency
2192 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency
2193 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency
2194 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency
2195 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency
2196 system.cpu1.l2cache.demand_avg_miss_latency::total 33795.364458 # average overall miss latency
2197 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency
2198 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency
2199 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency
2200 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency
2201 system.cpu1.l2cache.overall_avg_miss_latency::total 33795.364458 # average overall miss latency
2202 system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2203 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2204 system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2205 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2206 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2207 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2208 system.cpu1.l2cache.unused_prefetches 43661 # number of HardPF blocks evicted w/o reference
2209 system.cpu1.l2cache.writebacks::writebacks 1101410 # number of writebacks
2210 system.cpu1.l2cache.writebacks::total 1101410 # number of writebacks
2211 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
2212 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
2213 system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
2214 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4694 # number of ReadExReq MSHR hits
2215 system.cpu1.l2cache.ReadExReq_mshr_hits::total 4694 # number of ReadExReq MSHR hits
2216 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits
2217 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
2218 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 558 # number of ReadSharedReq MSHR hits
2219 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 558 # number of ReadSharedReq MSHR hits
2220 system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
2221 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
2222 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
2223 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5252 # number of demand (read+write) MSHR hits
2224 system.cpu1.l2cache.demand_mshr_hits::total 5258 # number of demand (read+write) MSHR hits
2225 system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
2226 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
2227 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
2228 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5252 # number of overall MSHR hits
2229 system.cpu1.l2cache.overall_mshr_hits::total 5258 # number of overall MSHR hits
2230 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11720 # number of ReadReq MSHR misses
2231 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8687 # number of ReadReq MSHR misses
2232 system.cpu1.l2cache.ReadReq_mshr_misses::total 20407 # number of ReadReq MSHR misses
2233 system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
2234 system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
2235 system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
2236 system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
2237 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of HardPFReq MSHR misses
2238 system.cpu1.l2cache.HardPFReq_mshr_misses::total 709103 # number of HardPFReq MSHR misses
2239 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 220631 # number of UpgradeReq MSHR misses
2240 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 220631 # number of UpgradeReq MSHR misses
2241 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192879 # number of SCUpgradeReq MSHR misses
2242 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192879 # number of SCUpgradeReq MSHR misses
2243 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses
2244 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
2245 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257272 # number of ReadExReq MSHR misses
2246 system.cpu1.l2cache.ReadExReq_mshr_misses::total 257272 # number of ReadExReq MSHR misses
2247 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 672599 # number of ReadCleanReq MSHR misses
2248 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 672599 # number of ReadCleanReq MSHR misses
2249 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 930869 # number of ReadSharedReq MSHR misses
2250 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 930869 # number of ReadSharedReq MSHR misses
2251 system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242391 # number of InvalidateReq MSHR misses
2252 system.cpu1.l2cache.InvalidateReq_mshr_misses::total 242391 # number of InvalidateReq MSHR misses
2253 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11720 # number of demand (read+write) MSHR misses
2254 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8687 # number of demand (read+write) MSHR misses
2255 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 672599 # number of demand (read+write) MSHR misses
2256 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1188141 # number of demand (read+write) MSHR misses
2257 system.cpu1.l2cache.demand_mshr_misses::total 1881147 # number of demand (read+write) MSHR misses
2258 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11720 # number of overall MSHR misses
2259 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8687 # number of overall MSHR misses
2260 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 672599 # number of overall MSHR misses
2261 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1188141 # number of overall MSHR misses
2262 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of overall MSHR misses
2263 system.cpu1.l2cache.overall_mshr_misses::total 2590250 # number of overall MSHR misses
2264 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
2265 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable
2266 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7034 # number of ReadReq MSHR uncacheable
2267 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable
2268 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable
2269 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
2270 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses
2271 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14314 # number of overall MSHR uncacheable misses
2272 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of ReadReq MSHR miss cycles
2273 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 274457000 # number of ReadReq MSHR miss cycles
2274 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 633384500 # number of ReadReq MSHR miss cycles
2275 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of HardPFReq MSHR miss cycles
2276 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 25470013765 # number of HardPFReq MSHR miss cycles
2277 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4591069994 # number of UpgradeReq MSHR miss cycles
2278 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4591069994 # number of UpgradeReq MSHR miss cycles
2279 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3129353001 # number of SCUpgradeReq MSHR miss cycles
2280 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3129353001 # number of SCUpgradeReq MSHR miss cycles
2281 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2003499 # number of SCUpgradeFailReq MSHR miss cycles
2282 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2003499 # number of SCUpgradeFailReq MSHR miss cycles
2283 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8263742497 # number of ReadExReq MSHR miss cycles
2284 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8263742497 # number of ReadExReq MSHR miss cycles
2285 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17982320500 # number of ReadCleanReq MSHR miss cycles
2286 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17982320500 # number of ReadCleanReq MSHR miss cycles
2287 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24961268994 # number of ReadSharedReq MSHR miss cycles
2288 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24961268994 # number of ReadSharedReq MSHR miss cycles
2289 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6347282500 # number of InvalidateReq MSHR miss cycles
2290 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6347282500 # number of InvalidateReq MSHR miss cycles
2291 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of demand (read+write) MSHR miss cycles
2292 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 274457000 # number of demand (read+write) MSHR miss cycles
2293 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17982320500 # number of demand (read+write) MSHR miss cycles
2294 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33225011491 # number of demand (read+write) MSHR miss cycles
2295 system.cpu1.l2cache.demand_mshr_miss_latency::total 51840716491 # number of demand (read+write) MSHR miss cycles
2296 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of overall MSHR miss cycles
2297 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 274457000 # number of overall MSHR miss cycles
2298 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17982320500 # number of overall MSHR miss cycles
2299 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33225011491 # number of overall MSHR miss cycles
2300 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of overall MSHR miss cycles
2301 system.cpu1.l2cache.overall_mshr_miss_latency::total 77310730256 # number of overall MSHR miss cycles
2302 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7706000 # number of ReadReq MSHR uncacheable cycles
2303 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 781601000 # number of ReadReq MSHR uncacheable cycles
2304 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 789307000 # number of ReadReq MSHR uncacheable cycles
2305 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7706000 # number of overall MSHR uncacheable cycles
2306 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 781601000 # number of overall MSHR uncacheable cycles
2307 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 789307000 # number of overall MSHR uncacheable cycles
2308 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for ReadReq accesses
2309 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for ReadReq accesses
2310 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030214 # mshr miss rate for ReadReq accesses
2311 system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
2312 system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
2313 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
2314 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2315 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2316 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2317 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses
2318 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses
2319 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2320 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2321 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2322 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2323 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.244771 # mshr miss rate for ReadExReq accesses
2324 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.244771 # mshr miss rate for ReadExReq accesses
2325 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for ReadCleanReq accesses
2326 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076908 # mshr miss rate for ReadCleanReq accesses
2327 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.270718 # mshr miss rate for ReadSharedReq accesses
2328 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270718 # mshr miss rate for ReadSharedReq accesses
2329 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.586269 # mshr miss rate for InvalidateReq accesses
2330 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.586269 # mshr miss rate for InvalidateReq accesses
2331 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses
2332 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses
2333 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses
2334 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses
2335 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses
2336 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses
2337 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses
2338 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses
2339 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses
2340 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2341 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses
2342 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency
2343 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency
2344 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency
2345 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency
2346 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency
2347 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency
2348 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency
2349 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency
2350 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency
2351 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency
2352 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency
2353 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency
2354 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency
2355 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency
2356 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency
2357 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency
2358 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency
2359 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency
2360 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency
2361 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency
2362 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency
2363 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency
2364 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency
2365 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency
2366 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency
2367 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency
2368 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency
2369 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency
2370 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency
2371 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency
2372 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency
2373 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency
2374 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency
2375 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency
2376 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency
2377 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency
2378 system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter.
2379 system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2380 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2381 system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter.
2382 system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2383 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2384 system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2385 system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution
2386 system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution
2387 system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution
2388 system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution
2389 system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution
2390 system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution
2391 system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution
2392 system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution
2393 system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
2394 system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution
2395 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution
2396 system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution
2397 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution
2398 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
2399 system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution
2400 system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution
2401 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution
2402 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution
2403 system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution
2404 system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution
2405 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes)
2406 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes)
2407 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes)
2408 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes)
2409 system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes)
2410 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes)
2411 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes)
2412 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes)
2413 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes)
2414 system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes)
2415 system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count)
2416 system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram
2417 system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram
2418 system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram
2419 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2420 system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram
2421 system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram
2422 system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram
2423 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2424 system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2425 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2426 system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram
2427 system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks)
2428 system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2429 system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks)
2430 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2431 system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks)
2432 system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2433 system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks)
2434 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2435 system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks)
2436 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2437 system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks)
2438 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2439 system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2440 system.iobus.trans_dist::ReadReq 40337 # Transaction distribution
2441 system.iobus.trans_dist::ReadResp 40337 # Transaction distribution
2442 system.iobus.trans_dist::WriteReq 136616 # Transaction distribution
2443 system.iobus.trans_dist::WriteResp 136616 # Transaction distribution
2444 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes)
2445 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2446 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2447 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2448 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2449 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2450 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2451 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2452 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2453 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2454 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2455 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2456 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2457 system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes)
2458 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes)
2459 system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes)
2460 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2461 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2462 system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes)
2463 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes)
2464 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2465 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2466 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2467 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2468 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2469 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2470 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2471 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2472 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2473 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2474 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2475 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2476 system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes)
2477 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes)
2478 system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes)
2479 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2480 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2481 system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes)
2482 system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks)
2483 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2484 system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
2485 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2486 system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
2487 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2488 system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2489 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2490 system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
2491 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2492 system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks)
2493 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2494 system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2495 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2496 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2497 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2498 system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2499 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2500 system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks)
2501 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2502 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2503 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2504 system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks)
2505 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2506 system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks)
2507 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2508 system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks)
2509 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2510 system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks)
2511 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2512 system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks)
2513 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2514 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2515 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2516 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2517 system.iocache.tags.replacements 115611 # number of replacements
2518 system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use
2519 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2520 system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks.
2521 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2522 system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit.
2523 system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor
2524 system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor
2525 system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy
2526 system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy
2527 system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy
2528 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2529 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2530 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2531 system.iocache.tags.tag_accesses 1040883 # Number of tag accesses
2532 system.iocache.tags.data_accesses 1040883 # Number of data accesses
2533 system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2534 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2535 system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses
2536 system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses
2537 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2538 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2539 system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2540 system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2541 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2542 system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses
2543 system.iocache.demand_misses::total 115654 # number of demand (read+write) misses
2544 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2545 system.iocache.overall_misses::realview.ide 115614 # number of overall misses
2546 system.iocache.overall_misses::total 115654 # number of overall misses
2547 system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
2548 system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles
2549 system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles
2550 system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2551 system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2552 system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles
2553 system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles
2554 system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
2555 system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles
2556 system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles
2557 system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
2558 system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles
2559 system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles
2560 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2561 system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses)
2562 system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses)
2563 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2564 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2565 system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2566 system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2567 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2568 system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses
2569 system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses
2570 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2571 system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses
2572 system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses
2573 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2574 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2575 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2576 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2577 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2578 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2579 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2580 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2581 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2582 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2583 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2584 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2585 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2586 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
2587 system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency
2588 system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency
2589 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2590 system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2591 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency
2592 system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency
2593 system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
2594 system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency
2595 system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency
2596 system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
2597 system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency
2598 system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency
2599 system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked
2600 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2601 system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked
2602 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2603 system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked
2604 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2605 system.iocache.writebacks::writebacks 106695 # number of writebacks
2606 system.iocache.writebacks::total 106695 # number of writebacks
2607 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2608 system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses
2609 system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses
2610 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2611 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2612 system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2613 system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2614 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2615 system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses
2616 system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses
2617 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2618 system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses
2619 system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses
2620 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
2621 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles
2622 system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles
2623 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2624 system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2625 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles
2626 system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles
2627 system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
2628 system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles
2629 system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles
2630 system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
2631 system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles
2632 system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles
2633 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2634 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2635 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2636 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2637 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2638 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2639 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2640 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2641 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2642 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2643 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2644 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2645 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2646 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
2647 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency
2648 system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency
2649 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2650 system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2651 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency
2652 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency
2653 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
2654 system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency
2655 system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency
2656 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
2657 system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency
2658 system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency
2659 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2660 system.l2c.tags.replacements 1371243 # number of replacements
2661 system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use
2662 system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks.
2663 system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks.
2664 system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks.
2665 system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit.
2666 system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor
2667 system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor
2668 system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor
2669 system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor
2670 system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor
2671 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor
2672 system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor
2673 system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor
2674 system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor
2675 system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor
2676 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor
2677 system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy
2678 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy
2679 system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy
2680 system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy
2681 system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy
2682 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy
2683 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy
2684 system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy
2685 system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy
2686 system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy
2687 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy
2688 system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy
2689 system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id
2690 system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id
2691 system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id
2692 system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
2693 system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id
2694 system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id
2695 system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id
2696 system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
2697 system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id
2698 system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
2699 system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
2700 system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id
2701 system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id
2702 system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id
2703 system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id
2704 system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id
2705 system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id
2706 system.l2c.tags.tag_accesses 79235647 # Number of tag accesses
2707 system.l2c.tags.data_accesses 79235647 # Number of data accesses
2708 system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
2709 system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits
2710 system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits
2711 system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
2712 system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits
2713 system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits
2714 system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits
2715 system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits
2716 system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits
2717 system.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits
2718 system.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits
2719 system.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits
2720 system.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits
2721 system.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits
2722 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits
2723 system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits
2724 system.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits
2725 system.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits
2726 system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits
2727 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits
2728 system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits
2729 system.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits
2730 system.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits
2731 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits
2732 system.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits
2733 system.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits
2734 system.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits
2735 system.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits
2736 system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits
2737 system.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits
2738 system.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits
2739 system.l2c.demand_hits::cpu0.data 672415 # number of demand (read+write) hits
2740 system.l2c.demand_hits::cpu0.l2cache.prefetcher 316694 # number of demand (read+write) hits
2741 system.l2c.demand_hits::cpu1.dtb.walker 6918 # number of demand (read+write) hits
2742 system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits
2743 system.l2c.demand_hits::cpu1.inst 620556 # number of demand (read+write) hits
2744 system.l2c.demand_hits::cpu1.data 622575 # number of demand (read+write) hits
2745 system.l2c.demand_hits::cpu1.l2cache.prefetcher 312616 # number of demand (read+write) hits
2746 system.l2c.demand_hits::total 3225225 # number of demand (read+write) hits
2747 system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits
2748 system.l2c.overall_hits::cpu0.itb.walker 3788 # number of overall hits
2749 system.l2c.overall_hits::cpu0.inst 658119 # number of overall hits
2750 system.l2c.overall_hits::cpu0.data 672415 # number of overall hits
2751 system.l2c.overall_hits::cpu0.l2cache.prefetcher 316694 # number of overall hits
2752 system.l2c.overall_hits::cpu1.dtb.walker 6918 # number of overall hits
2753 system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits
2754 system.l2c.overall_hits::cpu1.inst 620556 # number of overall hits
2755 system.l2c.overall_hits::cpu1.data 622575 # number of overall hits
2756 system.l2c.overall_hits::cpu1.l2cache.prefetcher 312616 # number of overall hits
2757 system.l2c.overall_hits::total 3225225 # number of overall hits
2758 system.l2c.UpgradeReq_misses::cpu0.data 63896 # number of UpgradeReq misses
2759 system.l2c.UpgradeReq_misses::cpu1.data 60301 # number of UpgradeReq misses
2760 system.l2c.UpgradeReq_misses::total 124197 # number of UpgradeReq misses
2761 system.l2c.SCUpgradeReq_misses::cpu0.data 12467 # number of SCUpgradeReq misses
2762 system.l2c.SCUpgradeReq_misses::cpu1.data 11210 # number of SCUpgradeReq misses
2763 system.l2c.SCUpgradeReq_misses::total 23677 # number of SCUpgradeReq misses
2764 system.l2c.ReadExReq_misses::cpu0.data 80795 # number of ReadExReq misses
2765 system.l2c.ReadExReq_misses::cpu1.data 51109 # number of ReadExReq misses
2766 system.l2c.ReadExReq_misses::total 131904 # number of ReadExReq misses
2767 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq misses
2768 system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1934 # number of ReadSharedReq misses
2769 system.l2c.ReadSharedReq_misses::cpu0.inst 66055 # number of ReadSharedReq misses
2770 system.l2c.ReadSharedReq_misses::cpu0.data 143274 # number of ReadSharedReq misses
2771 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq misses
2772 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq misses
2773 system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1578 # number of ReadSharedReq misses
2774 system.l2c.ReadSharedReq_misses::cpu1.inst 52043 # number of ReadSharedReq misses
2775 system.l2c.ReadSharedReq_misses::cpu1.data 103878 # number of ReadSharedReq misses
2776 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq misses
2777 system.l2c.ReadSharedReq_misses::total 792686 # number of ReadSharedReq misses
2778 system.l2c.InvalidateReq_misses::cpu0.data 465421 # number of InvalidateReq misses
2779 system.l2c.InvalidateReq_misses::cpu1.data 95414 # number of InvalidateReq misses
2780 system.l2c.InvalidateReq_misses::total 560835 # number of InvalidateReq misses
2781 system.l2c.demand_misses::cpu0.dtb.walker 2056 # number of demand (read+write) misses
2782 system.l2c.demand_misses::cpu0.itb.walker 1934 # number of demand (read+write) misses
2783 system.l2c.demand_misses::cpu0.inst 66055 # number of demand (read+write) misses
2784 system.l2c.demand_misses::cpu0.data 224069 # number of demand (read+write) misses
2785 system.l2c.demand_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) misses
2786 system.l2c.demand_misses::cpu1.dtb.walker 1908 # number of demand (read+write) misses
2787 system.l2c.demand_misses::cpu1.itb.walker 1578 # number of demand (read+write) misses
2788 system.l2c.demand_misses::cpu1.inst 52043 # number of demand (read+write) misses
2789 system.l2c.demand_misses::cpu1.data 154987 # number of demand (read+write) misses
2790 system.l2c.demand_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) misses
2791 system.l2c.demand_misses::total 924590 # number of demand (read+write) misses
2792 system.l2c.overall_misses::cpu0.dtb.walker 2056 # number of overall misses
2793 system.l2c.overall_misses::cpu0.itb.walker 1934 # number of overall misses
2794 system.l2c.overall_misses::cpu0.inst 66055 # number of overall misses
2795 system.l2c.overall_misses::cpu0.data 224069 # number of overall misses
2796 system.l2c.overall_misses::cpu0.l2cache.prefetcher 256484 # number of overall misses
2797 system.l2c.overall_misses::cpu1.dtb.walker 1908 # number of overall misses
2798 system.l2c.overall_misses::cpu1.itb.walker 1578 # number of overall misses
2799 system.l2c.overall_misses::cpu1.inst 52043 # number of overall misses
2800 system.l2c.overall_misses::cpu1.data 154987 # number of overall misses
2801 system.l2c.overall_misses::cpu1.l2cache.prefetcher 163476 # number of overall misses
2802 system.l2c.overall_misses::total 924590 # number of overall misses
2803 system.l2c.UpgradeReq_miss_latency::cpu0.data 446027000 # number of UpgradeReq miss cycles
2804 system.l2c.UpgradeReq_miss_latency::cpu1.data 423537000 # number of UpgradeReq miss cycles
2805 system.l2c.UpgradeReq_miss_latency::total 869564000 # number of UpgradeReq miss cycles
2806 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 79642000 # number of SCUpgradeReq miss cycles
2807 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 73423000 # number of SCUpgradeReq miss cycles
2808 system.l2c.SCUpgradeReq_miss_latency::total 153065000 # number of SCUpgradeReq miss cycles
2809 system.l2c.ReadExReq_miss_latency::cpu0.data 7209880999 # number of ReadExReq miss cycles
2810 system.l2c.ReadExReq_miss_latency::cpu1.data 4224259500 # number of ReadExReq miss cycles
2811 system.l2c.ReadExReq_miss_latency::total 11434140499 # number of ReadExReq miss cycles
2812 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 181168500 # number of ReadSharedReq miss cycles
2813 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 173308500 # number of ReadSharedReq miss cycles
2814 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5614644500 # number of ReadSharedReq miss cycles
2815 system.l2c.ReadSharedReq_miss_latency::cpu0.data 12851594000 # number of ReadSharedReq miss cycles
2816 system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of ReadSharedReq miss cycles
2817 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 174846500 # number of ReadSharedReq miss cycles
2818 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 145724500 # number of ReadSharedReq miss cycles
2819 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4416688500 # number of ReadSharedReq miss cycles
2820 system.l2c.ReadSharedReq_miss_latency::cpu1.data 9519600500 # number of ReadSharedReq miss cycles
2821 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of ReadSharedReq miss cycles
2822 system.l2c.ReadSharedReq_miss_latency::total 85697325813 # number of ReadSharedReq miss cycles
2823 system.l2c.InvalidateReq_miss_latency::cpu0.data 65788000 # number of InvalidateReq miss cycles
2824 system.l2c.InvalidateReq_miss_latency::cpu1.data 54373000 # number of InvalidateReq miss cycles
2825 system.l2c.InvalidateReq_miss_latency::total 120161000 # number of InvalidateReq miss cycles
2826 system.l2c.demand_miss_latency::cpu0.dtb.walker 181168500 # number of demand (read+write) miss cycles
2827 system.l2c.demand_miss_latency::cpu0.itb.walker 173308500 # number of demand (read+write) miss cycles
2828 system.l2c.demand_miss_latency::cpu0.inst 5614644500 # number of demand (read+write) miss cycles
2829 system.l2c.demand_miss_latency::cpu0.data 20061474999 # number of demand (read+write) miss cycles
2830 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of demand (read+write) miss cycles
2831 system.l2c.demand_miss_latency::cpu1.dtb.walker 174846500 # number of demand (read+write) miss cycles
2832 system.l2c.demand_miss_latency::cpu1.itb.walker 145724500 # number of demand (read+write) miss cycles
2833 system.l2c.demand_miss_latency::cpu1.inst 4416688500 # number of demand (read+write) miss cycles
2834 system.l2c.demand_miss_latency::cpu1.data 13743860000 # number of demand (read+write) miss cycles
2835 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of demand (read+write) miss cycles
2836 system.l2c.demand_miss_latency::total 97131466312 # number of demand (read+write) miss cycles
2837 system.l2c.overall_miss_latency::cpu0.dtb.walker 181168500 # number of overall miss cycles
2838 system.l2c.overall_miss_latency::cpu0.itb.walker 173308500 # number of overall miss cycles
2839 system.l2c.overall_miss_latency::cpu0.inst 5614644500 # number of overall miss cycles
2840 system.l2c.overall_miss_latency::cpu0.data 20061474999 # number of overall miss cycles
2841 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of overall miss cycles
2842 system.l2c.overall_miss_latency::cpu1.dtb.walker 174846500 # number of overall miss cycles
2843 system.l2c.overall_miss_latency::cpu1.itb.walker 145724500 # number of overall miss cycles
2844 system.l2c.overall_miss_latency::cpu1.inst 4416688500 # number of overall miss cycles
2845 system.l2c.overall_miss_latency::cpu1.data 13743860000 # number of overall miss cycles
2846 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of overall miss cycles
2847 system.l2c.overall_miss_latency::total 97131466312 # number of overall miss cycles
2848 system.l2c.WritebackDirty_accesses::writebacks 2747527 # number of WritebackDirty accesses(hits+misses)
2849 system.l2c.WritebackDirty_accesses::total 2747527 # number of WritebackDirty accesses(hits+misses)
2850 system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
2851 system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
2852 system.l2c.UpgradeReq_accesses::cpu0.data 234015 # number of UpgradeReq accesses(hits+misses)
2853 system.l2c.UpgradeReq_accesses::cpu1.data 192728 # number of UpgradeReq accesses(hits+misses)
2854 system.l2c.UpgradeReq_accesses::total 426743 # number of UpgradeReq accesses(hits+misses)
2855 system.l2c.SCUpgradeReq_accesses::cpu0.data 54214 # number of SCUpgradeReq accesses(hits+misses)
2856 system.l2c.SCUpgradeReq_accesses::cpu1.data 49248 # number of SCUpgradeReq accesses(hits+misses)
2857 system.l2c.SCUpgradeReq_accesses::total 103462 # number of SCUpgradeReq accesses(hits+misses)
2858 system.l2c.ReadExReq_accesses::cpu0.data 132881 # number of ReadExReq accesses(hits+misses)
2859 system.l2c.ReadExReq_accesses::cpu1.data 110166 # number of ReadExReq accesses(hits+misses)
2860 system.l2c.ReadExReq_accesses::total 243047 # number of ReadExReq accesses(hits+misses)
2861 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8404 # number of ReadSharedReq accesses(hits+misses)
2862 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5722 # number of ReadSharedReq accesses(hits+misses)
2863 system.l2c.ReadSharedReq_accesses::cpu0.inst 724174 # number of ReadSharedReq accesses(hits+misses)
2864 system.l2c.ReadSharedReq_accesses::cpu0.data 763603 # number of ReadSharedReq accesses(hits+misses)
2865 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 573178 # number of ReadSharedReq accesses(hits+misses)
2866 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8826 # number of ReadSharedReq accesses(hits+misses)
2867 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6774 # number of ReadSharedReq accesses(hits+misses)
2868 system.l2c.ReadSharedReq_accesses::cpu1.inst 672599 # number of ReadSharedReq accesses(hits+misses)
2869 system.l2c.ReadSharedReq_accesses::cpu1.data 667396 # number of ReadSharedReq accesses(hits+misses)
2870 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476092 # number of ReadSharedReq accesses(hits+misses)
2871 system.l2c.ReadSharedReq_accesses::total 3906768 # number of ReadSharedReq accesses(hits+misses)
2872 system.l2c.InvalidateReq_accesses::cpu0.data 595760 # number of InvalidateReq accesses(hits+misses)
2873 system.l2c.InvalidateReq_accesses::cpu1.data 229768 # number of InvalidateReq accesses(hits+misses)
2874 system.l2c.InvalidateReq_accesses::total 825528 # number of InvalidateReq accesses(hits+misses)
2875 system.l2c.demand_accesses::cpu0.dtb.walker 8404 # number of demand (read+write) accesses
2876 system.l2c.demand_accesses::cpu0.itb.walker 5722 # number of demand (read+write) accesses
2877 system.l2c.demand_accesses::cpu0.inst 724174 # number of demand (read+write) accesses
2878 system.l2c.demand_accesses::cpu0.data 896484 # number of demand (read+write) accesses
2879 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 573178 # number of demand (read+write) accesses
2880 system.l2c.demand_accesses::cpu1.dtb.walker 8826 # number of demand (read+write) accesses
2881 system.l2c.demand_accesses::cpu1.itb.walker 6774 # number of demand (read+write) accesses
2882 system.l2c.demand_accesses::cpu1.inst 672599 # number of demand (read+write) accesses
2883 system.l2c.demand_accesses::cpu1.data 777562 # number of demand (read+write) accesses
2884 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 476092 # number of demand (read+write) accesses
2885 system.l2c.demand_accesses::total 4149815 # number of demand (read+write) accesses
2886 system.l2c.overall_accesses::cpu0.dtb.walker 8404 # number of overall (read+write) accesses
2887 system.l2c.overall_accesses::cpu0.itb.walker 5722 # number of overall (read+write) accesses
2888 system.l2c.overall_accesses::cpu0.inst 724174 # number of overall (read+write) accesses
2889 system.l2c.overall_accesses::cpu0.data 896484 # number of overall (read+write) accesses
2890 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 573178 # number of overall (read+write) accesses
2891 system.l2c.overall_accesses::cpu1.dtb.walker 8826 # number of overall (read+write) accesses
2892 system.l2c.overall_accesses::cpu1.itb.walker 6774 # number of overall (read+write) accesses
2893 system.l2c.overall_accesses::cpu1.inst 672599 # number of overall (read+write) accesses
2894 system.l2c.overall_accesses::cpu1.data 777562 # number of overall (read+write) accesses
2895 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 476092 # number of overall (read+write) accesses
2896 system.l2c.overall_accesses::total 4149815 # number of overall (read+write) accesses
2897 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.273042 # miss rate for UpgradeReq accesses
2898 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.312881 # miss rate for UpgradeReq accesses
2899 system.l2c.UpgradeReq_miss_rate::total 0.291035 # miss rate for UpgradeReq accesses
2900 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.229959 # miss rate for SCUpgradeReq accesses
2901 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.227623 # miss rate for SCUpgradeReq accesses
2902 system.l2c.SCUpgradeReq_miss_rate::total 0.228847 # miss rate for SCUpgradeReq accesses
2903 system.l2c.ReadExReq_miss_rate::cpu0.data 0.608025 # miss rate for ReadExReq accesses
2904 system.l2c.ReadExReq_miss_rate::cpu1.data 0.463927 # miss rate for ReadExReq accesses
2905 system.l2c.ReadExReq_miss_rate::total 0.542710 # miss rate for ReadExReq accesses
2906 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for ReadSharedReq accesses
2907 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.337994 # miss rate for ReadSharedReq accesses
2908 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.091214 # miss rate for ReadSharedReq accesses
2909 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187629 # miss rate for ReadSharedReq accesses
2910 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for ReadSharedReq accesses
2911 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for ReadSharedReq accesses
2912 system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.232950 # miss rate for ReadSharedReq accesses
2913 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.077376 # miss rate for ReadSharedReq accesses
2914 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.155647 # miss rate for ReadSharedReq accesses
2915 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for ReadSharedReq accesses
2916 system.l2c.ReadSharedReq_miss_rate::total 0.202901 # miss rate for ReadSharedReq accesses
2917 system.l2c.InvalidateReq_miss_rate::cpu0.data 0.781222 # miss rate for InvalidateReq accesses
2918 system.l2c.InvalidateReq_miss_rate::cpu1.data 0.415262 # miss rate for InvalidateReq accesses
2919 system.l2c.InvalidateReq_miss_rate::total 0.679365 # miss rate for InvalidateReq accesses
2920 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for demand accesses
2921 system.l2c.demand_miss_rate::cpu0.itb.walker 0.337994 # miss rate for demand accesses
2922 system.l2c.demand_miss_rate::cpu0.inst 0.091214 # miss rate for demand accesses
2923 system.l2c.demand_miss_rate::cpu0.data 0.249942 # miss rate for demand accesses
2924 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for demand accesses
2925 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for demand accesses
2926 system.l2c.demand_miss_rate::cpu1.itb.walker 0.232950 # miss rate for demand accesses
2927 system.l2c.demand_miss_rate::cpu1.inst 0.077376 # miss rate for demand accesses
2928 system.l2c.demand_miss_rate::cpu1.data 0.199324 # miss rate for demand accesses
2929 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for demand accesses
2930 system.l2c.demand_miss_rate::total 0.222803 # miss rate for demand accesses
2931 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for overall accesses
2932 system.l2c.overall_miss_rate::cpu0.itb.walker 0.337994 # miss rate for overall accesses
2933 system.l2c.overall_miss_rate::cpu0.inst 0.091214 # miss rate for overall accesses
2934 system.l2c.overall_miss_rate::cpu0.data 0.249942 # miss rate for overall accesses
2935 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for overall accesses
2936 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for overall accesses
2937 system.l2c.overall_miss_rate::cpu1.itb.walker 0.232950 # miss rate for overall accesses
2938 system.l2c.overall_miss_rate::cpu1.inst 0.077376 # miss rate for overall accesses
2939 system.l2c.overall_miss_rate::cpu1.data 0.199324 # miss rate for overall accesses
2940 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for overall accesses
2941 system.l2c.overall_miss_rate::total 0.222803 # miss rate for overall accesses
2942 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6980.515212 # average UpgradeReq miss latency
2943 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7023.714366 # average UpgradeReq miss latency
2944 system.l2c.UpgradeReq_avg_miss_latency::total 7001.489569 # average UpgradeReq miss latency
2945 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6388.224914 # average SCUpgradeReq miss latency
2946 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6549.776985 # average SCUpgradeReq miss latency
2947 system.l2c.SCUpgradeReq_avg_miss_latency::total 6464.712590 # average SCUpgradeReq miss latency
2948 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89236.722557 # average ReadExReq miss latency
2949 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82651.969320 # average ReadExReq miss latency
2950 system.l2c.ReadExReq_avg_miss_latency::total 86685.320377 # average ReadExReq miss latency
2951 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average ReadSharedReq miss latency
2952 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89611.427094 # average ReadSharedReq miss latency
2953 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 84999.538264 # average ReadSharedReq miss latency
2954 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89699.415107 # average ReadSharedReq miss latency
2955 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average ReadSharedReq miss latency
2956 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average ReadSharedReq miss latency
2957 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92347.591888 # average ReadSharedReq miss latency
2958 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84866.139538 # average ReadSharedReq miss latency
2959 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91642.123453 # average ReadSharedReq miss latency
2960 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average ReadSharedReq miss latency
2961 system.l2c.ReadSharedReq_avg_miss_latency::total 108110.053430 # average ReadSharedReq miss latency
2962 system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 141.351594 # average InvalidateReq miss latency
2963 system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 569.863961 # average InvalidateReq miss latency
2964 system.l2c.InvalidateReq_avg_miss_latency::total 214.253747 # average InvalidateReq miss latency
2965 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency
2966 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency
2967 system.l2c.demand_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency
2968 system.l2c.demand_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency
2969 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency
2970 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency
2971 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency
2972 system.l2c.demand_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency
2973 system.l2c.demand_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency
2974 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency
2975 system.l2c.demand_avg_miss_latency::total 105053.554886 # average overall miss latency
2976 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency
2977 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency
2978 system.l2c.overall_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency
2979 system.l2c.overall_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency
2980 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency
2981 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency
2982 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency
2983 system.l2c.overall_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency
2984 system.l2c.overall_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency
2985 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency
2986 system.l2c.overall_avg_miss_latency::total 105053.554886 # average overall miss latency
2987 system.l2c.blocked_cycles::no_mshrs 547 # number of cycles access was blocked
2988 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2989 system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
2990 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2991 system.l2c.avg_blocked_cycles::no_mshrs 68.375000 # average number of cycles each access was blocked
2992 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2993 system.l2c.writebacks::writebacks 1075082 # number of writebacks
2994 system.l2c.writebacks::total 1075082 # number of writebacks
2995 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 93 # number of ReadSharedReq MSHR hits
2996 system.l2c.ReadSharedReq_mshr_hits::cpu0.data 13 # number of ReadSharedReq MSHR hits
2997 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 87 # number of ReadSharedReq MSHR hits
2998 system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits
2999 system.l2c.ReadSharedReq_mshr_hits::total 210 # number of ReadSharedReq MSHR hits
3000 system.l2c.demand_mshr_hits::cpu0.inst 93 # number of demand (read+write) MSHR hits
3001 system.l2c.demand_mshr_hits::cpu0.data 13 # number of demand (read+write) MSHR hits
3002 system.l2c.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits
3003 system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits
3004 system.l2c.demand_mshr_hits::total 210 # number of demand (read+write) MSHR hits
3005 system.l2c.overall_mshr_hits::cpu0.inst 93 # number of overall MSHR hits
3006 system.l2c.overall_mshr_hits::cpu0.data 13 # number of overall MSHR hits
3007 system.l2c.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits
3008 system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits
3009 system.l2c.overall_mshr_hits::total 210 # number of overall MSHR hits
3010 system.l2c.CleanEvict_mshr_misses::writebacks 54168 # number of CleanEvict MSHR misses
3011 system.l2c.CleanEvict_mshr_misses::total 54168 # number of CleanEvict MSHR misses
3012 system.l2c.UpgradeReq_mshr_misses::cpu0.data 63896 # number of UpgradeReq MSHR misses
3013 system.l2c.UpgradeReq_mshr_misses::cpu1.data 60301 # number of UpgradeReq MSHR misses
3014 system.l2c.UpgradeReq_mshr_misses::total 124197 # number of UpgradeReq MSHR misses
3015 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12467 # number of SCUpgradeReq MSHR misses
3016 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11210 # number of SCUpgradeReq MSHR misses
3017 system.l2c.SCUpgradeReq_mshr_misses::total 23677 # number of SCUpgradeReq MSHR misses
3018 system.l2c.ReadExReq_mshr_misses::cpu0.data 80795 # number of ReadExReq MSHR misses
3019 system.l2c.ReadExReq_mshr_misses::cpu1.data 51109 # number of ReadExReq MSHR misses
3020 system.l2c.ReadExReq_mshr_misses::total 131904 # number of ReadExReq MSHR misses
3021 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq MSHR misses
3022 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1934 # number of ReadSharedReq MSHR misses
3023 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65962 # number of ReadSharedReq MSHR misses
3024 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 143261 # number of ReadSharedReq MSHR misses
3025 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq MSHR misses
3026 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq MSHR misses
3027 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1578 # number of ReadSharedReq MSHR misses
3028 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 51956 # number of ReadSharedReq MSHR misses
3029 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 103861 # number of ReadSharedReq MSHR misses
3030 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq MSHR misses
3031 system.l2c.ReadSharedReq_mshr_misses::total 792476 # number of ReadSharedReq MSHR misses
3032 system.l2c.InvalidateReq_mshr_misses::cpu0.data 465421 # number of InvalidateReq MSHR misses
3033 system.l2c.InvalidateReq_mshr_misses::cpu1.data 95414 # number of InvalidateReq MSHR misses
3034 system.l2c.InvalidateReq_mshr_misses::total 560835 # number of InvalidateReq MSHR misses
3035 system.l2c.demand_mshr_misses::cpu0.dtb.walker 2056 # number of demand (read+write) MSHR misses
3036 system.l2c.demand_mshr_misses::cpu0.itb.walker 1934 # number of demand (read+write) MSHR misses
3037 system.l2c.demand_mshr_misses::cpu0.inst 65962 # number of demand (read+write) MSHR misses
3038 system.l2c.demand_mshr_misses::cpu0.data 224056 # number of demand (read+write) MSHR misses
3039 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) MSHR misses
3040 system.l2c.demand_mshr_misses::cpu1.dtb.walker 1908 # number of demand (read+write) MSHR misses
3041 system.l2c.demand_mshr_misses::cpu1.itb.walker 1578 # number of demand (read+write) MSHR misses
3042 system.l2c.demand_mshr_misses::cpu1.inst 51956 # number of demand (read+write) MSHR misses
3043 system.l2c.demand_mshr_misses::cpu1.data 154970 # number of demand (read+write) MSHR misses
3044 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) MSHR misses
3045 system.l2c.demand_mshr_misses::total 924380 # number of demand (read+write) MSHR misses
3046 system.l2c.overall_mshr_misses::cpu0.dtb.walker 2056 # number of overall MSHR misses
3047 system.l2c.overall_mshr_misses::cpu0.itb.walker 1934 # number of overall MSHR misses
3048 system.l2c.overall_mshr_misses::cpu0.inst 65962 # number of overall MSHR misses
3049 system.l2c.overall_mshr_misses::cpu0.data 224056 # number of overall MSHR misses
3050 system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of overall MSHR misses
3051 system.l2c.overall_mshr_misses::cpu1.dtb.walker 1908 # number of overall MSHR misses
3052 system.l2c.overall_mshr_misses::cpu1.itb.walker 1578 # number of overall MSHR misses
3053 system.l2c.overall_mshr_misses::cpu1.inst 51956 # number of overall MSHR misses
3054 system.l2c.overall_mshr_misses::cpu1.data 154970 # number of overall MSHR misses
3055 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of overall MSHR misses
3056 system.l2c.overall_mshr_misses::total 924380 # number of overall MSHR misses
3057 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable
3058 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable
3059 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
3060 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6939 # number of ReadReq MSHR uncacheable
3061 system.l2c.ReadReq_mshr_uncacheable::total 91033 # number of ReadReq MSHR uncacheable
3062 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable
3063 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable
3064 system.l2c.WriteReq_mshr_uncacheable::total 38505 # number of WriteReq MSHR uncacheable
3065 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses
3066 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses
3067 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
3068 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14219 # number of overall MSHR uncacheable misses
3069 system.l2c.overall_mshr_uncacheable_misses::total 129538 # number of overall MSHR uncacheable misses
3070 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1380806993 # number of UpgradeReq MSHR miss cycles
3071 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1305380495 # number of UpgradeReq MSHR miss cycles
3072 system.l2c.UpgradeReq_mshr_miss_latency::total 2686187488 # number of UpgradeReq MSHR miss cycles
3073 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 306900998 # number of SCUpgradeReq MSHR miss cycles
3074 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 275849499 # number of SCUpgradeReq MSHR miss cycles
3075 system.l2c.SCUpgradeReq_mshr_miss_latency::total 582750497 # number of SCUpgradeReq MSHR miss cycles
3076 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6401900063 # number of ReadExReq MSHR miss cycles
3077 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3713131578 # number of ReadExReq MSHR miss cycles
3078 system.l2c.ReadExReq_mshr_miss_latency::total 10115031641 # number of ReadExReq MSHR miss cycles
3079 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of ReadSharedReq MSHR miss cycles
3080 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 153968500 # number of ReadSharedReq MSHR miss cycles
3081 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4948095074 # number of ReadSharedReq MSHR miss cycles
3082 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11417870701 # number of ReadSharedReq MSHR miss cycles
3083 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of ReadSharedReq MSHR miss cycles
3084 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of ReadSharedReq MSHR miss cycles
3085 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 129943003 # number of ReadSharedReq MSHR miss cycles
3086 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3891093570 # number of ReadSharedReq MSHR miss cycles
3087 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8479584227 # number of ReadSharedReq MSHR miss cycles
3088 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of ReadSharedReq MSHR miss cycles
3089 system.l2c.ReadSharedReq_mshr_miss_latency::total 77756673264 # number of ReadSharedReq MSHR miss cycles
3090 system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9735980999 # number of InvalidateReq MSHR miss cycles
3091 system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1980875000 # number of InvalidateReq MSHR miss cycles
3092 system.l2c.InvalidateReq_mshr_miss_latency::total 11716855999 # number of InvalidateReq MSHR miss cycles
3093 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of demand (read+write) MSHR miss cycles
3094 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 153968500 # number of demand (read+write) MSHR miss cycles
3095 system.l2c.demand_mshr_miss_latency::cpu0.inst 4948095074 # number of demand (read+write) MSHR miss cycles
3096 system.l2c.demand_mshr_miss_latency::cpu0.data 17819770764 # number of demand (read+write) MSHR miss cycles
3097 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of demand (read+write) MSHR miss cycles
3098 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of demand (read+write) MSHR miss cycles
3099 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 129943003 # number of demand (read+write) MSHR miss cycles
3100 system.l2c.demand_mshr_miss_latency::cpu1.inst 3891093570 # number of demand (read+write) MSHR miss cycles
3101 system.l2c.demand_mshr_miss_latency::cpu1.data 12192715805 # number of demand (read+write) MSHR miss cycles
3102 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of demand (read+write) MSHR miss cycles
3103 system.l2c.demand_mshr_miss_latency::total 87871704905 # number of demand (read+write) MSHR miss cycles
3104 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 160608500 # number of overall MSHR miss cycles
3105 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 153968500 # number of overall MSHR miss cycles
3106 system.l2c.overall_mshr_miss_latency::cpu0.inst 4948095074 # number of overall MSHR miss cycles
3107 system.l2c.overall_mshr_miss_latency::cpu0.data 17819770764 # number of overall MSHR miss cycles
3108 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30169861471 # number of overall MSHR miss cycles
3109 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 155763506 # number of overall MSHR miss cycles
3110 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 129943003 # number of overall MSHR miss cycles
3111 system.l2c.overall_mshr_miss_latency::cpu1.inst 3891093570 # number of overall MSHR miss cycles
3112 system.l2c.overall_mshr_miss_latency::cpu1.data 12192715805 # number of overall MSHR miss cycles
3113 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 18249884712 # number of overall MSHR miss cycles
3114 system.l2c.overall_mshr_miss_latency::total 87871704905 # number of overall MSHR miss cycles
3115 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of ReadReq MSHR uncacheable cycles
3116 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5312322505 # number of ReadReq MSHR uncacheable cycles
3117 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5752000 # number of ReadReq MSHR uncacheable cycles
3118 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 656593502 # number of ReadReq MSHR uncacheable cycles
3119 system.l2c.ReadReq_mshr_uncacheable_latency::total 9295192507 # number of ReadReq MSHR uncacheable cycles
3120 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of overall MSHR uncacheable cycles
3121 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5312322505 # number of overall MSHR uncacheable cycles
3122 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5752000 # number of overall MSHR uncacheable cycles
3123 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 656593502 # number of overall MSHR uncacheable cycles
3124 system.l2c.overall_mshr_uncacheable_latency::total 9295192507 # number of overall MSHR uncacheable cycles
3125 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3126 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3127 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.273042 # mshr miss rate for UpgradeReq accesses
3128 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses
3129 system.l2c.UpgradeReq_mshr_miss_rate::total 0.291035 # mshr miss rate for UpgradeReq accesses
3130 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.229959 # mshr miss rate for SCUpgradeReq accesses
3131 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.227623 # mshr miss rate for SCUpgradeReq accesses
3132 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SCUpgradeReq accesses
3133 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.608025 # mshr miss rate for ReadExReq accesses
3134 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463927 # mshr miss rate for ReadExReq accesses
3135 system.l2c.ReadExReq_mshr_miss_rate::total 0.542710 # mshr miss rate for ReadExReq accesses
3136 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for ReadSharedReq accesses
3137 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for ReadSharedReq accesses
3138 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for ReadSharedReq accesses
3139 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187612 # mshr miss rate for ReadSharedReq accesses
3140 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for ReadSharedReq accesses
3141 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for ReadSharedReq accesses
3142 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for ReadSharedReq accesses
3143 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses
3144 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.155621 # mshr miss rate for ReadSharedReq accesses
3145 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for ReadSharedReq accesses
3146 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202847 # mshr miss rate for ReadSharedReq accesses
3147 system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781222 # mshr miss rate for InvalidateReq accesses
3148 system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses
3149 system.l2c.InvalidateReq_mshr_miss_rate::total 0.679365 # mshr miss rate for InvalidateReq accesses
3150 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses
3151 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for demand accesses
3152 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for demand accesses
3153 system.l2c.demand_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for demand accesses
3154 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for demand accesses
3155 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for demand accesses
3156 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for demand accesses
3157 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for demand accesses
3158 system.l2c.demand_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for demand accesses
3159 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for demand accesses
3160 system.l2c.demand_mshr_miss_rate::total 0.222752 # mshr miss rate for demand accesses
3161 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for overall accesses
3162 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for overall accesses
3163 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses
3164 system.l2c.overall_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for overall accesses
3165 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for overall accesses
3166 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for overall accesses
3167 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for overall accesses
3168 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses
3169 system.l2c.overall_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for overall accesses
3170 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for overall accesses
3171 system.l2c.overall_mshr_miss_rate::total 0.222752 # mshr miss rate for overall accesses
3172 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21610.225883 # average UpgradeReq mshr miss latency
3173 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency
3174 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21628.441009 # average UpgradeReq mshr miss latency
3175 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24617.068902 # average SCUpgradeReq mshr miss latency
3176 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.448617 # average SCUpgradeReq mshr miss latency
3177 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24612.514128 # average SCUpgradeReq mshr miss latency
3178 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79236.339662 # average ReadExReq mshr miss latency
3179 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency
3180 system.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency
3181 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency
3182 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency
3183 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency
3184 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency
3185 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency
3186 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency
3187 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency
3188 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency
3189 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency
3190 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency
3191 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency
3192 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency
3193 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency
3194 system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency
3195 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency
3196 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency
3197 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency
3198 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency
3199 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency
3200 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency
3201 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency
3202 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency
3203 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency
3204 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency
3205 system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency
3206 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency
3207 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency
3208 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency
3209 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency
3210 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency
3211 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency
3212 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency
3213 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency
3214 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency
3215 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency
3216 system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency
3217 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency
3218 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency
3219 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency
3220 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency
3221 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency
3222 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency
3223 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency
3224 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency
3225 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency
3226 system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency
3227 system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter.
3228 system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3229 system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3230 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3231 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3232 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3233 system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3234 system.membus.trans_dist::ReadReq 91033 # Transaction distribution
3235 system.membus.trans_dist::ReadResp 892432 # Transaction distribution
3236 system.membus.trans_dist::WriteReq 38505 # Transaction distribution
3237 system.membus.trans_dist::WriteResp 38505 # Transaction distribution
3238 system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution
3239 system.membus.trans_dist::CleanEvict 252869 # Transaction distribution
3240 system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution
3241 system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution
3242 system.membus.trans_dist::UpgradeResp 22 # Transaction distribution
3243 system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
3244 system.membus.trans_dist::ReadExReq 143945 # Transaction distribution
3245 system.membus.trans_dist::ReadExResp 126263 # Transaction distribution
3246 system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution
3247 system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution
3248 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes)
3249 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
3250 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes)
3251 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes)
3252 system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes)
3253 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes)
3254 system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes)
3255 system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes)
3256 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes)
3257 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
3258 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes)
3259 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes)
3260 system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes)
3261 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes)
3262 system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes)
3263 system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes)
3264 system.membus.snoops 608511 # Total snoops (count)
3265 system.membus.snoop_fanout::samples 2484071 # Request fanout histogram
3266 system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram
3267 system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram
3268 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3269 system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram
3270 system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram
3271 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3272 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3273 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3274 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3275 system.membus.snoop_fanout::total 2484071 # Request fanout histogram
3276 system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks)
3277 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3278 system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
3279 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3280 system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks)
3281 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3282 system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks)
3283 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3284 system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks)
3285 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3286 system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks)
3287 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3288 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3289 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3290 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3291 system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3292 system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3293 system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3294 system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3295 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3296 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3297 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3298 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3299 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3300 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3301 system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3302 system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3303 system.realview.ethernet.txBytes 966 # Bytes Transmitted
3304 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3305 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3306 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3307 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3308 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3309 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3310 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3311 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3312 system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
3313 system.realview.ethernet.totPackets 3 # Total Packets
3314 system.realview.ethernet.totBytes 966 # Total Bytes
3315 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
3316 system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
3317 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
3318 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3319 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
3320 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3321 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3322 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
3323 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3324 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3325 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
3326 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3327 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3328 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
3329 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3330 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3331 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
3332 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3333 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3334 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
3335 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3336 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3337 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3338 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3339 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3340 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3341 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3342 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3343 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3344 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3345 system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3346 system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3347 system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3348 system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3349 system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3350 system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3351 system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3352 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3353 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3354 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3355 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3356 system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3357 system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3358 system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3359 system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3360 system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3361 system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3362 system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3363 system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3364 system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3365 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3366 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3367 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3368 system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter.
3369 system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3370 system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3371 system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter.
3372 system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3373 system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3374 system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
3375 system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution
3376 system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution
3377 system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution
3378 system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution
3379 system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution
3380 system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
3381 system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution
3382 system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution
3383 system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution
3384 system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution
3385 system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution
3386 system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
3387 system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution
3388 system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution
3389 system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution
3390 system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution
3391 system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution
3392 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes)
3393 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes)
3394 system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes)
3395 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes)
3396 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes)
3397 system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes)
3398 system.toL2Bus.snoops 2830390 # Total snoops (count)
3399 system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram
3400 system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram
3401 system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram
3402 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3403 system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram
3404 system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram
3405 system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram
3406 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3407 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3408 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3409 system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram
3410 system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks)
3411 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3412 system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks)
3413 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3414 system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks)
3415 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3416 system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks)
3417 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3419 ---------- End Simulation Statistics ----------
projects / gem5.git / blob