2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 51.277959 # Number of seconds simulated
4 sim_ticks 51277959410000 # Number of ticks simulated
5 final_tick 51277959410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 210382 # Simulator instruction rate (inst/s)
8 host_op_rate 250295 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 13357159040 # Simulator tick rate (ticks/s)
10 host_mem_usage 689664 # Number of bytes of host memory used
11 host_seconds 3838.99 # Real time elapsed on the host
12 sim_insts 807652759 # Number of instructions simulated
13 sim_ops 960879271 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.dtb.walker 253184 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 234496 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 5589856 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 47714440 # Number of bytes read from this memory
21 system.physmem.bytes_read::realview.ide 412800 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 54204776 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu.inst 5589856 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::total 5589856 # Number of instructions bytes read from this memory
25 system.physmem.bytes_written::writebacks 74605824 # Number of bytes written to this memory
26 system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
27 system.physmem.bytes_written::total 74626404 # Number of bytes written to this memory
28 system.physmem.num_reads::cpu.dtb.walker 3956 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.itb.walker 3664 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.inst 88894 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu.data 745551 # Number of read requests responded to by this memory
32 system.physmem.num_reads::realview.ide 6450 # Number of read requests responded to by this memory
33 system.physmem.num_reads::total 848515 # Number of read requests responded to by this memory
34 system.physmem.num_writes::writebacks 1165716 # Number of write requests responded to by this memory
35 system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
36 system.physmem.num_writes::total 1168289 # Number of write requests responded to by this memory
37 system.physmem.bw_read::cpu.dtb.walker 4937 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.inst 109011 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu.data 930506 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::realview.ide 8050 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::total 1057077 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::cpu.inst 109011 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_inst_read::total 109011 # Instruction read bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::writebacks 1454930 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_write::total 1455331 # Write bandwidth from this memory (bytes/s)
48 system.physmem.bw_total::writebacks 1454930 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.dtb.walker 4937 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.inst 109011 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu.data 930907 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::realview.ide 8050 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::total 2512408 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.readReqs 848516 # Number of read requests accepted
56 system.physmem.writeReqs 1168289 # Number of write requests accepted
57 system.physmem.readBursts 848516 # Number of DRAM read bursts, including those serviced by the write queue
58 system.physmem.writeBursts 1168289 # Number of DRAM write bursts, including those merged in the write queue
59 system.physmem.bytesReadDRAM 54258624 # Total number of bytes read from DRAM
60 system.physmem.bytesReadWrQ 46336 # Total number of bytes read from write queue
61 system.physmem.bytesWritten 74623296 # Total number of bytes written to DRAM
62 system.physmem.bytesReadSys 54204840 # Total read bytes from the system interface side
63 system.physmem.bytesWrittenSys 74626404 # Total written bytes from the system interface side
64 system.physmem.servicedByWrQ 724 # Number of DRAM read bursts serviced by the write queue
65 system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one
66 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67 system.physmem.perBankRdBursts::0 50870 # Per bank write bursts
68 system.physmem.perBankRdBursts::1 59107 # Per bank write bursts
69 system.physmem.perBankRdBursts::2 53673 # Per bank write bursts
70 system.physmem.perBankRdBursts::3 52283 # Per bank write bursts
71 system.physmem.perBankRdBursts::4 52009 # Per bank write bursts
72 system.physmem.perBankRdBursts::5 59846 # Per bank write bursts
73 system.physmem.perBankRdBursts::6 50421 # Per bank write bursts
74 system.physmem.perBankRdBursts::7 52784 # Per bank write bursts
75 system.physmem.perBankRdBursts::8 49319 # Per bank write bursts
76 system.physmem.perBankRdBursts::9 57871 # Per bank write bursts
77 system.physmem.perBankRdBursts::10 53663 # Per bank write bursts
78 system.physmem.perBankRdBursts::11 59850 # Per bank write bursts
79 system.physmem.perBankRdBursts::12 49313 # Per bank write bursts
80 system.physmem.perBankRdBursts::13 51526 # Per bank write bursts
81 system.physmem.perBankRdBursts::14 46865 # Per bank write bursts
82 system.physmem.perBankRdBursts::15 48391 # Per bank write bursts
83 system.physmem.perBankWrBursts::0 70028 # Per bank write bursts
84 system.physmem.perBankWrBursts::1 76221 # Per bank write bursts
85 system.physmem.perBankWrBursts::2 72051 # Per bank write bursts
86 system.physmem.perBankWrBursts::3 73117 # Per bank write bursts
87 system.physmem.perBankWrBursts::4 72572 # Per bank write bursts
88 system.physmem.perBankWrBursts::5 78772 # Per bank write bursts
89 system.physmem.perBankWrBursts::6 71408 # Per bank write bursts
90 system.physmem.perBankWrBursts::7 73272 # Per bank write bursts
91 system.physmem.perBankWrBursts::8 71515 # Per bank write bursts
92 system.physmem.perBankWrBursts::9 77080 # Per bank write bursts
93 system.physmem.perBankWrBursts::10 72838 # Per bank write bursts
94 system.physmem.perBankWrBursts::11 77780 # Per bank write bursts
95 system.physmem.perBankWrBursts::12 69170 # Per bank write bursts
96 system.physmem.perBankWrBursts::13 71642 # Per bank write bursts
97 system.physmem.perBankWrBursts::14 68698 # Per bank write bursts
98 system.physmem.perBankWrBursts::15 69825 # Per bank write bursts
99 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
100 system.physmem.numWrRetry 522 # Number of times write queue was full causing retry
101 system.physmem.totGap 51277958025500 # Total gap between requests
102 system.physmem.readPktSize::0 0 # Read request sizes (log2)
103 system.physmem.readPktSize::1 0 # Read request sizes (log2)
104 system.physmem.readPktSize::2 0 # Read request sizes (log2)
105 system.physmem.readPktSize::3 13 # Read request sizes (log2)
106 system.physmem.readPktSize::4 2072 # Read request sizes (log2)
107 system.physmem.readPktSize::5 0 # Read request sizes (log2)
108 system.physmem.readPktSize::6 846431 # Read request sizes (log2)
109 system.physmem.writePktSize::0 0 # Write request sizes (log2)
110 system.physmem.writePktSize::1 0 # Write request sizes (log2)
111 system.physmem.writePktSize::2 1 # Write request sizes (log2)
112 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
113 system.physmem.writePktSize::4 0 # Write request sizes (log2)
114 system.physmem.writePktSize::5 0 # Write request sizes (log2)
115 system.physmem.writePktSize::6 1165716 # Write request sizes (log2)
116 system.physmem.rdQLenPdf::0 541295 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::1 247060 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::2 38783 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::3 15383 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::4 573 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::5 464 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::6 597 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::8 939 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::9 638 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::10 319 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::11 277 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::12 193 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
148 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::15 18590 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::16 25743 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::17 45741 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::18 55757 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::19 63122 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::20 66457 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::21 68011 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::22 72400 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::23 75195 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::24 71101 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::25 74150 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::26 75214 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::27 67195 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::28 65816 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::29 65315 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::30 67462 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::31 61130 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::32 60486 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::34 4298 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::35 3581 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::36 2994 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::37 2748 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::38 2603 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::39 2553 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::40 2355 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::41 2335 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::42 2239 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::43 2251 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::44 2250 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::45 1876 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::46 1953 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::47 1922 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::48 1642 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::49 1940 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::50 1886 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::51 1643 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::52 1747 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::54 1729 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::55 1705 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::56 1986 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::57 1571 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::58 1442 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::59 1488 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::60 1772 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::61 1419 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::62 718 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::63 1155 # What write queue length does an incoming req see
212 system.physmem.bytesPerActivate::samples 505782 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::mean 254.816375 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::gmean 152.511846 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::stdev 294.316020 # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::0-127 218537 43.21% 43.21% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::128-255 130980 25.90% 69.10% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::256-383 46546 9.20% 78.31% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::384-511 24886 4.92% 83.23% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::512-639 16948 3.35% 86.58% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::640-767 10705 2.12% 88.69% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::768-895 8138 1.61% 90.30% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::896-1023 6857 1.36% 91.66% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::1024-1151 42185 8.34% 100.00% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::total 505782 # Bytes accessed per row activation
226 system.physmem.rdPerTurnAround::samples 52835 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::mean 16.045538 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::stdev 23.735472 # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::0-255 52822 99.98% 99.98% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::256-511 8 0.02% 99.99% # Reads before turning the bus around for writes
231 system.physmem.rdPerTurnAround::768-1023 3 0.01% 100.00% # Reads before turning the bus around for writes
232 system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes
233 system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
234 system.physmem.rdPerTurnAround::total 52835 # Reads before turning the bus around for writes
235 system.physmem.wrPerTurnAround::samples 52835 # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::mean 22.068496 # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::gmean 18.791739 # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::stdev 25.919021 # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::16-31 48708 92.19% 92.19% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::32-47 1351 2.56% 94.75% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::48-63 388 0.73% 95.48% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::64-79 806 1.53% 97.01% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::80-95 454 0.86% 97.87% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::96-111 263 0.50% 98.36% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::112-127 370 0.70% 99.06% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::128-143 158 0.30% 99.36% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::144-159 43 0.08% 99.44% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::160-175 52 0.10% 99.54% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::176-191 56 0.11% 99.65% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::192-207 28 0.05% 99.70% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::208-223 16 0.03% 99.73% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::224-239 21 0.04% 99.77% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::240-255 12 0.02% 99.79% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::256-271 27 0.05% 99.84% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::272-287 19 0.04% 99.88% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::288-303 15 0.03% 99.91% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::320-335 5 0.01% 99.92% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::336-351 1 0.00% 99.93% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::352-367 4 0.01% 99.93% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::368-383 8 0.02% 99.95% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::384-399 3 0.01% 99.95% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::448-463 1 0.00% 99.96% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::480-495 2 0.00% 99.96% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::496-511 1 0.00% 99.96% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::512-527 2 0.00% 99.97% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::528-543 2 0.00% 99.97% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::544-559 1 0.00% 99.97% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::592-607 1 0.00% 99.98% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::608-623 2 0.00% 99.98% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::624-639 1 0.00% 99.98% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::640-655 4 0.01% 99.99% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::704-719 1 0.00% 99.99% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::880-895 1 0.00% 100.00% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::992-1007 1 0.00% 100.00% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::total 52835 # Writes before turning the bus around for reads
281 system.physmem.totQLat 32888008041 # Total ticks spent queuing
282 system.physmem.totMemAccLat 48784089291 # Total ticks spent from burst creation until serviced by the DRAM
283 system.physmem.totBusLat 4238955000 # Total ticks spent in databus transfers
284 system.physmem.avgQLat 38792.54 # Average queueing delay per DRAM burst
285 system.physmem.avgBusLat 4999.99 # Average bus latency per DRAM burst
286 system.physmem.avgMemAccLat 57542.52 # Average memory access latency per DRAM burst
287 system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s
288 system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s
289 system.physmem.avgRdBWSys 1.06 # Average system read bandwidth in MiByte/s
290 system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s
291 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
292 system.physmem.busUtil 0.02 # Data bus utilization in percentage
293 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
294 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
295 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
296 system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing
297 system.physmem.readRowHits 648292 # Number of row buffer hits during reads
298 system.physmem.writeRowHits 859704 # Number of row buffer hits during writes
299 system.physmem.readRowHitRate 76.47 # Row buffer hit rate for reads
300 system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes
301 system.physmem.avgGap 25425342.57 # Average gap between requests
302 system.physmem.pageHitRate 74.88 # Row buffer hit rate, read and write combined
303 system.physmem_0.actEnergy 1849802640 # Energy for activate commands per rank (pJ)
304 system.physmem_0.preEnergy 983185830 # Energy for precharge commands per rank (pJ)
305 system.physmem_0.readEnergy 3077290020 # Energy for read commands per rank (pJ)
306 system.physmem_0.writeEnergy 3066442020 # Energy for write commands per rank (pJ)
307 system.physmem_0.refreshEnergy 32858039760.000008 # Energy for refresh commands per rank (pJ)
308 system.physmem_0.actBackEnergy 30159163980 # Energy for active background per rank (pJ)
309 system.physmem_0.preBackEnergy 1958344800 # Energy for precharge background per rank (pJ)
310 system.physmem_0.actPowerDownEnergy 66073114650 # Energy for active power-down per rank (pJ)
311 system.physmem_0.prePowerDownEnergy 46519620000 # Energy for precharge power-down per rank (pJ)
312 system.physmem_0.selfRefreshEnergy 12231781860420 # Energy for self refresh per rank (pJ)
313 system.physmem_0.totalEnergy 12418342348350 # Total energy per rank (pJ)
314 system.physmem_0.averagePower 242.176999 # Core power per rank (mW)
315 system.physmem_0.totalIdleTime 51206686329778 # Total Idle time Per DRAM Rank
316 system.physmem_0.memoryStateTime::IDLE 3544531992 # Time in different power states
317 system.physmem_0.memoryStateTime::REF 13966174000 # Time in different power states
318 system.physmem_0.memoryStateTime::SREF 50940644588000 # Time in different power states
319 system.physmem_0.memoryStateTime::PRE_PDN 121144747142 # Time in different power states
320 system.physmem_0.memoryStateTime::ACT 53762327980 # Time in different power states
321 system.physmem_0.memoryStateTime::ACT_PDN 144897040886 # Time in different power states
322 system.physmem_1.actEnergy 1761495120 # Energy for activate commands per rank (pJ)
323 system.physmem_1.preEnergy 936256860 # Energy for precharge commands per rank (pJ)
324 system.physmem_1.readEnergy 2975937720 # Energy for read commands per rank (pJ)
325 system.physmem_1.writeEnergy 3020020560 # Energy for write commands per rank (pJ)
326 system.physmem_1.refreshEnergy 32012909760.000008 # Energy for refresh commands per rank (pJ)
327 system.physmem_1.actBackEnergy 29684228010 # Energy for active background per rank (pJ)
328 system.physmem_1.preBackEnergy 1902447840 # Energy for precharge background per rank (pJ)
329 system.physmem_1.actPowerDownEnergy 63461801580 # Energy for active power-down per rank (pJ)
330 system.physmem_1.prePowerDownEnergy 45299969760 # Energy for precharge power-down per rank (pJ)
331 system.physmem_1.selfRefreshEnergy 12234156504570 # Energy for self refresh per rank (pJ)
332 system.physmem_1.totalEnergy 12415225828860 # Total energy per rank (pJ)
333 system.physmem_1.averagePower 242.116222 # Core power per rank (mW)
334 system.physmem_1.totalIdleTime 51207876412176 # Total Idle time Per DRAM Rank
335 system.physmem_1.memoryStateTime::IDLE 3424177242 # Time in different power states
336 system.physmem_1.memoryStateTime::REF 13608086000 # Time in different power states
337 system.physmem_1.memoryStateTime::SREF 50950737151500 # Time in different power states
338 system.physmem_1.memoryStateTime::PRE_PDN 117968786503 # Time in different power states
339 system.physmem_1.memoryStateTime::ACT 53050734582 # Time in different power states
340 system.physmem_1.memoryStateTime::ACT_PDN 139170474173 # Time in different power states
341 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
342 system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
343 system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
344 system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
345 system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
346 system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
347 system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
348 system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
349 system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
350 system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
351 system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
352 system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
353 system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
354 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
355 system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
356 system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
357 system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
358 system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
359 system.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
360 system.bridge.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
361 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
362 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
363 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
364 system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
365 system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
366 system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
367 system.cpu.branchPred.lookups 214792288 # Number of BP lookups
368 system.cpu.branchPred.condPredicted 137846282 # Number of conditional branches predicted
369 system.cpu.branchPred.condIncorrect 12464803 # Number of conditional branches incorrect
370 system.cpu.branchPred.BTBLookups 146135265 # Number of BTB lookups
371 system.cpu.branchPred.BTBHits 84448125 # Number of BTB hits
372 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
373 system.cpu.branchPred.BTBHitPct 57.787643 # BTB Hit Percentage
374 system.cpu.branchPred.usedRAS 31594768 # Number of times the RAS was used to get a target.
375 system.cpu.branchPred.RASInCorrect 349324 # Number of incorrect RAS predictions.
376 system.cpu.branchPred.indirectLookups 6874034 # Number of indirect predictor lookups.
377 system.cpu.branchPred.indirectHits 4883721 # Number of indirect target hits.
378 system.cpu.branchPred.indirectMisses 1990313 # Number of indirect misses.
379 system.cpu.branchPredindirectMispredicted 771971 # Number of mispredicted indirect branches.
380 system.cpu_clk_domain.clock 500 # Clock period in ticks
381 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
382 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
383 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
384 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
385 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
386 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
387 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
388 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
389 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
390 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
391 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
392 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
393 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
394 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
395 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
396 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
397 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
398 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
399 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
400 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
401 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
402 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
403 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
404 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
405 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
406 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
407 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
408 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
409 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
410 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
411 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
412 system.cpu.dtb.walker.walks 970467 # Table walker walks requested
413 system.cpu.dtb.walker.walksLong 970467 # Table walker walks initiated with long descriptors
414 system.cpu.dtb.walker.walksLongTerminationLevel::Level2 18061 # Level at which table walker walks with long descriptors terminate
415 system.cpu.dtb.walker.walksLongTerminationLevel::Level3 162102 # Level at which table walker walks with long descriptors terminate
416 system.cpu.dtb.walker.walksSquashedBefore 433748 # Table walks squashed before starting
417 system.cpu.dtb.walker.walkWaitTime::samples 536719 # Table walker wait (enqueue to first request) latency
418 system.cpu.dtb.walker.walkWaitTime::mean 2148.778970 # Table walker wait (enqueue to first request) latency
419 system.cpu.dtb.walker.walkWaitTime::stdev 14488.438649 # Table walker wait (enqueue to first request) latency
420 system.cpu.dtb.walker.walkWaitTime::0-65535 533045 99.32% 99.32% # Table walker wait (enqueue to first request) latency
421 system.cpu.dtb.walker.walkWaitTime::65536-131071 2702 0.50% 99.82% # Table walker wait (enqueue to first request) latency
422 system.cpu.dtb.walker.walkWaitTime::131072-196607 468 0.09% 99.91% # Table walker wait (enqueue to first request) latency
423 system.cpu.dtb.walker.walkWaitTime::196608-262143 229 0.04% 99.95% # Table walker wait (enqueue to first request) latency
424 system.cpu.dtb.walker.walkWaitTime::262144-327679 124 0.02% 99.97% # Table walker wait (enqueue to first request) latency
425 system.cpu.dtb.walker.walkWaitTime::327680-393215 18 0.00% 99.98% # Table walker wait (enqueue to first request) latency
426 system.cpu.dtb.walker.walkWaitTime::393216-458751 94 0.02% 99.99% # Table walker wait (enqueue to first request) latency
427 system.cpu.dtb.walker.walkWaitTime::458752-524287 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency
428 system.cpu.dtb.walker.walkWaitTime::524288-589823 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
429 system.cpu.dtb.walker.walkWaitTime::589824-655359 22 0.00% 100.00% # Table walker wait (enqueue to first request) latency
430 system.cpu.dtb.walker.walkWaitTime::total 536719 # Table walker wait (enqueue to first request) latency
431 system.cpu.dtb.walker.walkCompletionTime::samples 489559 # Table walker service (enqueue to completion) latency
432 system.cpu.dtb.walker.walkCompletionTime::mean 21856.142978 # Table walker service (enqueue to completion) latency
433 system.cpu.dtb.walker.walkCompletionTime::gmean 16984.908569 # Table walker service (enqueue to completion) latency
434 system.cpu.dtb.walker.walkCompletionTime::stdev 19510.602702 # Table walker service (enqueue to completion) latency
435 system.cpu.dtb.walker.walkCompletionTime::0-65535 478829 97.81% 97.81% # Table walker service (enqueue to completion) latency
436 system.cpu.dtb.walker.walkCompletionTime::65536-131071 9216 1.88% 99.69% # Table walker service (enqueue to completion) latency
437 system.cpu.dtb.walker.walkCompletionTime::131072-196607 680 0.14% 99.83% # Table walker service (enqueue to completion) latency
438 system.cpu.dtb.walker.walkCompletionTime::196608-262143 491 0.10% 99.93% # Table walker service (enqueue to completion) latency
439 system.cpu.dtb.walker.walkCompletionTime::262144-327679 167 0.03% 99.96% # Table walker service (enqueue to completion) latency
440 system.cpu.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.97% # Table walker service (enqueue to completion) latency
441 system.cpu.dtb.walker.walkCompletionTime::393216-458751 18 0.00% 99.97% # Table walker service (enqueue to completion) latency
442 system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 99.98% # Table walker service (enqueue to completion) latency
443 system.cpu.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 99.98% # Table walker service (enqueue to completion) latency
444 system.cpu.dtb.walker.walkCompletionTime::589824-655359 87 0.02% 100.00% # Table walker service (enqueue to completion) latency
445 system.cpu.dtb.walker.walkCompletionTime::655360-720895 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
446 system.cpu.dtb.walker.walkCompletionTime::total 489559 # Table walker service (enqueue to completion) latency
447 system.cpu.dtb.walker.walksPending::samples 687539152416 # Table walker pending requests distribution
448 system.cpu.dtb.walker.walksPending::mean 0.766147 # Table walker pending requests distribution
449 system.cpu.dtb.walker.walksPending::stdev 0.508794 # Table walker pending requests distribution
450 system.cpu.dtb.walker.walksPending::0-1 685391448916 99.69% 99.69% # Table walker pending requests distribution
451 system.cpu.dtb.walker.walksPending::2-3 1144327500 0.17% 99.85% # Table walker pending requests distribution
452 system.cpu.dtb.walker.walksPending::4-5 477284500 0.07% 99.92% # Table walker pending requests distribution
453 system.cpu.dtb.walker.walksPending::6-7 191925000 0.03% 99.95% # Table walker pending requests distribution
454 system.cpu.dtb.walker.walksPending::8-9 139963500 0.02% 99.97% # Table walker pending requests distribution
455 system.cpu.dtb.walker.walksPending::10-11 102241500 0.01% 99.99% # Table walker pending requests distribution
456 system.cpu.dtb.walker.walksPending::12-13 33074500 0.00% 99.99% # Table walker pending requests distribution
457 system.cpu.dtb.walker.walksPending::14-15 56365000 0.01% 100.00% # Table walker pending requests distribution
458 system.cpu.dtb.walker.walksPending::16-17 2522000 0.00% 100.00% # Table walker pending requests distribution
459 system.cpu.dtb.walker.walksPending::total 687539152416 # Table walker pending requests distribution
460 system.cpu.dtb.walker.walkPageSizes::4K 162103 89.98% 89.98% # Table walker page sizes translated
461 system.cpu.dtb.walker.walkPageSizes::2M 18061 10.02% 100.00% # Table walker page sizes translated
462 system.cpu.dtb.walker.walkPageSizes::total 180164 # Table walker page sizes translated
463 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 970467 # Table walker requests started/completed, data/inst
464 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
465 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 970467 # Table walker requests started/completed, data/inst
466 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 180164 # Table walker requests started/completed, data/inst
467 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
468 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 180164 # Table walker requests started/completed, data/inst
469 system.cpu.dtb.walker.walkRequestOrigin::total 1150631 # Table walker requests started/completed, data/inst
470 system.cpu.dtb.inst_hits 0 # ITB inst hits
471 system.cpu.dtb.inst_misses 0 # ITB inst misses
472 system.cpu.dtb.read_hits 174485449 # DTB read hits
473 system.cpu.dtb.read_misses 696020 # DTB read misses
474 system.cpu.dtb.write_hits 152010399 # DTB write hits
475 system.cpu.dtb.write_misses 274447 # DTB write misses
476 system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
477 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
478 system.cpu.dtb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID
479 system.cpu.dtb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID
480 system.cpu.dtb.flush_entries 74778 # Number of entries that have been flushed from TLB
481 system.cpu.dtb.align_faults 103 # Number of TLB faults due to alignment restrictions
482 system.cpu.dtb.prefetch_faults 10363 # Number of TLB faults due to prefetch
483 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
484 system.cpu.dtb.perms_faults 69607 # Number of TLB faults due to permissions restrictions
485 system.cpu.dtb.read_accesses 175181469 # DTB read accesses
486 system.cpu.dtb.write_accesses 152284846 # DTB write accesses
487 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
488 system.cpu.dtb.hits 326495848 # DTB hits
489 system.cpu.dtb.misses 970467 # DTB misses
490 system.cpu.dtb.accesses 327466315 # DTB accesses
491 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
492 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
493 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
494 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
495 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
496 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
497 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
498 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
499 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
500 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
501 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
502 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
503 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
504 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
505 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
506 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
507 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
508 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
509 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
510 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
511 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
512 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
513 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
514 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
515 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
516 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
517 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
518 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
519 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
520 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
521 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
522 system.cpu.itb.walker.walks 166329 # Table walker walks requested
523 system.cpu.itb.walker.walksLong 166329 # Table walker walks initiated with long descriptors
524 system.cpu.itb.walker.walksLongTerminationLevel::Level2 1543 # Level at which table walker walks with long descriptors terminate
525 system.cpu.itb.walker.walksLongTerminationLevel::Level3 121824 # Level at which table walker walks with long descriptors terminate
526 system.cpu.itb.walker.walksSquashedBefore 18039 # Table walks squashed before starting
527 system.cpu.itb.walker.walkWaitTime::samples 148290 # Table walker wait (enqueue to first request) latency
528 system.cpu.itb.walker.walkWaitTime::mean 1030.507789 # Table walker wait (enqueue to first request) latency
529 system.cpu.itb.walker.walkWaitTime::stdev 10121.197556 # Table walker wait (enqueue to first request) latency
530 system.cpu.itb.walker.walkWaitTime::0-65535 147791 99.66% 99.66% # Table walker wait (enqueue to first request) latency
531 system.cpu.itb.walker.walkWaitTime::65536-131071 435 0.29% 99.96% # Table walker wait (enqueue to first request) latency
532 system.cpu.itb.walker.walkWaitTime::131072-196607 25 0.02% 99.97% # Table walker wait (enqueue to first request) latency
533 system.cpu.itb.walker.walkWaitTime::196608-262143 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency
534 system.cpu.itb.walker.walkWaitTime::262144-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
535 system.cpu.itb.walker.walkWaitTime::327680-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
536 system.cpu.itb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
537 system.cpu.itb.walker.walkWaitTime::524288-589823 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
538 system.cpu.itb.walker.walkWaitTime::589824-655359 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
539 system.cpu.itb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
540 system.cpu.itb.walker.walkWaitTime::total 148290 # Table walker wait (enqueue to first request) latency
541 system.cpu.itb.walker.walkCompletionTime::samples 141406 # Table walker service (enqueue to completion) latency
542 system.cpu.itb.walker.walkCompletionTime::mean 26889.721794 # Table walker service (enqueue to completion) latency
543 system.cpu.itb.walker.walkCompletionTime::gmean 22183.567838 # Table walker service (enqueue to completion) latency
544 system.cpu.itb.walker.walkCompletionTime::stdev 21940.142141 # Table walker service (enqueue to completion) latency
545 system.cpu.itb.walker.walkCompletionTime::0-65535 138369 97.85% 97.85% # Table walker service (enqueue to completion) latency
546 system.cpu.itb.walker.walkCompletionTime::65536-131071 2580 1.82% 99.68% # Table walker service (enqueue to completion) latency
547 system.cpu.itb.walker.walkCompletionTime::131072-196607 191 0.14% 99.81% # Table walker service (enqueue to completion) latency
548 system.cpu.itb.walker.walkCompletionTime::196608-262143 150 0.11% 99.92% # Table walker service (enqueue to completion) latency
549 system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.03% 99.95% # Table walker service (enqueue to completion) latency
550 system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.96% # Table walker service (enqueue to completion) latency
551 system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.96% # Table walker service (enqueue to completion) latency
552 system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency
553 system.cpu.itb.walker.walkCompletionTime::589824-655359 49 0.03% 100.00% # Table walker service (enqueue to completion) latency
554 system.cpu.itb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
555 system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
556 system.cpu.itb.walker.walkCompletionTime::total 141406 # Table walker service (enqueue to completion) latency
557 system.cpu.itb.walker.walksPending::samples 580161918016 # Table walker pending requests distribution
558 system.cpu.itb.walker.walksPending::mean 0.951845 # Table walker pending requests distribution
559 system.cpu.itb.walker.walksPending::stdev 0.214419 # Table walker pending requests distribution
560 system.cpu.itb.walker.walksPending::0 27974300560 4.82% 4.82% # Table walker pending requests distribution
561 system.cpu.itb.walker.walksPending::1 552153156456 95.17% 99.99% # Table walker pending requests distribution
562 system.cpu.itb.walker.walksPending::2 33290000 0.01% 100.00% # Table walker pending requests distribution
563 system.cpu.itb.walker.walksPending::3 609500 0.00% 100.00% # Table walker pending requests distribution
564 system.cpu.itb.walker.walksPending::4 49000 0.00% 100.00% # Table walker pending requests distribution
565 system.cpu.itb.walker.walksPending::5 512500 0.00% 100.00% # Table walker pending requests distribution
566 system.cpu.itb.walker.walksPending::total 580161918016 # Table walker pending requests distribution
567 system.cpu.itb.walker.walkPageSizes::4K 121824 98.75% 98.75% # Table walker page sizes translated
568 system.cpu.itb.walker.walkPageSizes::2M 1543 1.25% 100.00% # Table walker page sizes translated
569 system.cpu.itb.walker.walkPageSizes::total 123367 # Table walker page sizes translated
570 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
571 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 166329 # Table walker requests started/completed, data/inst
572 system.cpu.itb.walker.walkRequestOrigin_Requested::total 166329 # Table walker requests started/completed, data/inst
573 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
574 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123367 # Table walker requests started/completed, data/inst
575 system.cpu.itb.walker.walkRequestOrigin_Completed::total 123367 # Table walker requests started/completed, data/inst
576 system.cpu.itb.walker.walkRequestOrigin::total 289696 # Table walker requests started/completed, data/inst
577 system.cpu.itb.inst_hits 333977355 # ITB inst hits
578 system.cpu.itb.inst_misses 166329 # ITB inst misses
579 system.cpu.itb.read_hits 0 # DTB read hits
580 system.cpu.itb.read_misses 0 # DTB read misses
581 system.cpu.itb.write_hits 0 # DTB write hits
582 system.cpu.itb.write_misses 0 # DTB write misses
583 system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
584 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
585 system.cpu.itb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID
586 system.cpu.itb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID
587 system.cpu.itb.flush_entries 54464 # Number of entries that have been flushed from TLB
588 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
589 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
590 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
591 system.cpu.itb.perms_faults 373131 # Number of TLB faults due to permissions restrictions
592 system.cpu.itb.read_accesses 0 # DTB read accesses
593 system.cpu.itb.write_accesses 0 # DTB write accesses
594 system.cpu.itb.inst_accesses 334143684 # ITB inst accesses
595 system.cpu.itb.hits 333977355 # DTB hits
596 system.cpu.itb.misses 166329 # DTB misses
597 system.cpu.itb.accesses 334143684 # DTB accesses
598 system.cpu.numPwrStateTransitions 32546 # Number of power state transitions
599 system.cpu.pwrStateClkGateDist::samples 16273 # Distribution of time spent in the clock gated state
600 system.cpu.pwrStateClkGateDist::mean 3107516335.044798 # Distribution of time spent in the clock gated state
601 system.cpu.pwrStateClkGateDist::stdev 60196725189.485252 # Distribution of time spent in the clock gated state
602 system.cpu.pwrStateClkGateDist::underflows 6948 42.70% 42.70% # Distribution of time spent in the clock gated state
603 system.cpu.pwrStateClkGateDist::1000-5e+10 9289 57.08% 99.78% # Distribution of time spent in the clock gated state
604 system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
605 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
606 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
607 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
608 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
609 system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
610 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
611 system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
612 system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
613 system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
614 system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
615 system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
616 system.cpu.pwrStateClkGateDist::total 16273 # Distribution of time spent in the clock gated state
617 system.cpu.pwrStateResidencyTicks::ON 709346089816 # Cumulative time (in ticks) in various power states
618 system.cpu.pwrStateResidencyTicks::CLK_GATED 50568613320184 # Cumulative time (in ticks) in various power states
619 system.cpu.numCycles 1418701600 # number of cpu cycles simulated
620 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
621 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
622 system.cpu.fetch.icacheStallCycles 626970761 # Number of cycles fetch is stalled on an Icache miss
623 system.cpu.fetch.Insts 964955706 # Number of instructions fetch has processed
624 system.cpu.fetch.Branches 214792288 # Number of branches that fetch encountered
625 system.cpu.fetch.predictedBranches 120926614 # Number of branches that fetch has predicted taken
626 system.cpu.fetch.Cycles 712354427 # Number of cycles fetch has run and was not squashing or blocked
627 system.cpu.fetch.SquashCycles 26627776 # Number of cycles fetch has spent squashing
628 system.cpu.fetch.TlbCycles 3832226 # Number of cycles fetch has spent waiting for tlb
629 system.cpu.fetch.MiscStallCycles 25955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
630 system.cpu.fetch.PendingTrapStallCycles 9044924 # Number of stall cycles due to pending traps
631 system.cpu.fetch.PendingQuiesceStallCycles 1035738 # Number of stall cycles due to pending quiesce instructions
632 system.cpu.fetch.IcacheWaitRetryStallCycles 1059 # Number of stall cycles due to full MSHR
633 system.cpu.fetch.CacheLines 333569052 # Number of cache lines fetched
634 system.cpu.fetch.IcacheSquashes 6336680 # Number of outstanding Icache misses that were squashed
635 system.cpu.fetch.ItlbSquashes 48713 # Number of outstanding ITLB misses that were squashed
636 system.cpu.fetch.rateDist::samples 1366578978 # Number of instructions fetched each cycle (Total)
637 system.cpu.fetch.rateDist::mean 0.835386 # Number of instructions fetched each cycle (Total)
638 system.cpu.fetch.rateDist::stdev 1.187527 # Number of instructions fetched each cycle (Total)
639 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
640 system.cpu.fetch.rateDist::0 828034594 60.59% 60.59% # Number of instructions fetched each cycle (Total)
641 system.cpu.fetch.rateDist::1 202016384 14.78% 75.37% # Number of instructions fetched each cycle (Total)
642 system.cpu.fetch.rateDist::2 69979562 5.12% 80.50% # Number of instructions fetched each cycle (Total)
643 system.cpu.fetch.rateDist::3 266548438 19.50% 100.00% # Number of instructions fetched each cycle (Total)
644 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
645 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
646 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
647 system.cpu.fetch.rateDist::total 1366578978 # Number of instructions fetched each cycle (Total)
648 system.cpu.fetch.branchRate 0.151401 # Number of branch fetches per cycle
649 system.cpu.fetch.rate 0.680168 # Number of inst fetches per cycle
650 system.cpu.decode.IdleCycles 523831535 # Number of cycles decode is idle
651 system.cpu.decode.BlockedCycles 358407215 # Number of cycles decode is blocked
652 system.cpu.decode.RunCycles 444986242 # Number of cycles decode is running
653 system.cpu.decode.UnblockCycles 29823356 # Number of cycles decode is unblocking
654 system.cpu.decode.SquashCycles 9530630 # Number of cycles decode is squashing
655 system.cpu.decode.BranchResolved 82997397 # Number of times decode resolved a branch
656 system.cpu.decode.BranchMispred 3840205 # Number of times decode detected a branch misprediction
657 system.cpu.decode.DecodedInsts 1051662188 # Number of instructions handled by decode
658 system.cpu.decode.SquashedInsts 29872784 # Number of squashed instructions handled by decode
659 system.cpu.rename.SquashCycles 9530630 # Number of cycles rename is squashing
660 system.cpu.rename.IdleCycles 559062030 # Number of cycles rename is idle
661 system.cpu.rename.BlockCycles 58275029 # Number of cycles rename is blocking
662 system.cpu.rename.serializeStallCycles 221284587 # count of cycles rename stalled for serializing inst
663 system.cpu.rename.RunCycles 439543391 # Number of cycles rename is running
664 system.cpu.rename.UnblockCycles 78883311 # Number of cycles rename is unblocking
665 system.cpu.rename.RenamedInsts 1030946151 # Number of instructions processed by rename
666 system.cpu.rename.SquashedInsts 7084405 # Number of squashed instructions processed by rename
667 system.cpu.rename.ROBFullEvents 5220432 # Number of times rename has blocked due to ROB full
668 system.cpu.rename.IQFullEvents 401053 # Number of times rename has blocked due to IQ full
669 system.cpu.rename.LQFullEvents 689601 # Number of times rename has blocked due to LQ full
670 system.cpu.rename.SQFullEvents 52909282 # Number of times rename has blocked due to SQ full
671 system.cpu.rename.FullRegisterEvents 20659 # Number of times there has been no free registers
672 system.cpu.rename.RenamedOperands 944726342 # Number of destination operands rename has renamed
673 system.cpu.rename.RenameLookups 1460373617 # Number of register rename lookups that rename has made
674 system.cpu.rename.int_rename_lookups 1214391439 # Number of integer rename lookups
675 system.cpu.rename.fp_rename_lookups 1466073 # Number of floating rename lookups
676 system.cpu.rename.CommittedMaps 877604087 # Number of HB maps that are committed
677 system.cpu.rename.UndoneMaps 67122252 # Number of HB maps that are undone due to squashing
678 system.cpu.rename.serializingInsts 11621737 # count of serializing insts renamed
679 system.cpu.rename.tempSerializingInsts 7877357 # count of temporary serializing insts renamed
680 system.cpu.rename.skidInsts 58456344 # count of insts added to the skid buffer
681 system.cpu.memDep0.insertedLoads 178961087 # Number of loads inserted to the mem dependence unit.
682 system.cpu.memDep0.insertedStores 155538156 # Number of stores inserted to the mem dependence unit.
683 system.cpu.memDep0.conflictingLoads 10194150 # Number of conflicting loads.
684 system.cpu.memDep0.conflictingStores 9195511 # Number of conflicting stores.
685 system.cpu.iq.iqInstsAdded 1010975595 # Number of instructions added to the IQ (excludes non-spec)
686 system.cpu.iq.iqNonSpecInstsAdded 11936880 # Number of non-speculative instructions added to the IQ
687 system.cpu.iq.iqInstsIssued 1010573430 # Number of instructions issued
688 system.cpu.iq.iqSquashedInstsIssued 3406540 # Number of squashed instructions issued
689 system.cpu.iq.iqSquashedInstsExamined 62033200 # Number of squashed instructions iterated over during squash; mainly for profiling
690 system.cpu.iq.iqSquashedOperandsExamined 34713553 # Number of squashed operands that are examined and possibly removed from graph
691 system.cpu.iq.iqSquashedNonSpecRemoved 312805 # Number of squashed non-spec instructions that were removed
692 system.cpu.iq.issued_per_cycle::samples 1366578978 # Number of insts issued each cycle
693 system.cpu.iq.issued_per_cycle::mean 0.739491 # Number of insts issued each cycle
694 system.cpu.iq.issued_per_cycle::stdev 0.966076 # Number of insts issued each cycle
695 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
696 system.cpu.iq.issued_per_cycle::0 766524619 56.09% 56.09% # Number of insts issued each cycle
697 system.cpu.iq.issued_per_cycle::1 278054062 20.35% 76.44% # Number of insts issued each cycle
698 system.cpu.iq.issued_per_cycle::2 240507320 17.60% 94.04% # Number of insts issued each cycle
699 system.cpu.iq.issued_per_cycle::3 74487645 5.45% 99.49% # Number of insts issued each cycle
700 system.cpu.iq.issued_per_cycle::4 6984867 0.51% 100.00% # Number of insts issued each cycle
701 system.cpu.iq.issued_per_cycle::5 20465 0.00% 100.00% # Number of insts issued each cycle
702 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
703 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
704 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
705 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
706 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
707 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
708 system.cpu.iq.issued_per_cycle::total 1366578978 # Number of insts issued each cycle
709 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
710 system.cpu.iq.fu_full::IntAlu 59327643 34.80% 34.80% # attempts to use FU when none available
711 system.cpu.iq.fu_full::IntMult 97860 0.06% 34.86% # attempts to use FU when none available
712 system.cpu.iq.fu_full::IntDiv 26629 0.02% 34.87% # attempts to use FU when none available
713 system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.87% # attempts to use FU when none available
714 system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.87% # attempts to use FU when none available
715 system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.87% # attempts to use FU when none available
716 system.cpu.iq.fu_full::FloatMult 0 0.00% 34.87% # attempts to use FU when none available
717 system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available
718 system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.87% # attempts to use FU when none available
719 system.cpu.iq.fu_full::FloatMisc 606 0.00% 34.87% # attempts to use FU when none available
720 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.87% # attempts to use FU when none available
721 system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.87% # attempts to use FU when none available
722 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.87% # attempts to use FU when none available
723 system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.87% # attempts to use FU when none available
724 system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.87% # attempts to use FU when none available
725 system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.87% # attempts to use FU when none available
726 system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.87% # attempts to use FU when none available
727 system.cpu.iq.fu_full::SimdMult 0 0.00% 34.87% # attempts to use FU when none available
728 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.87% # attempts to use FU when none available
729 system.cpu.iq.fu_full::SimdShift 0 0.00% 34.87% # attempts to use FU when none available
730 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.87% # attempts to use FU when none available
731 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.87% # attempts to use FU when none available
732 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.87% # attempts to use FU when none available
733 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.87% # attempts to use FU when none available
734 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.87% # attempts to use FU when none available
735 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.87% # attempts to use FU when none available
736 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.87% # attempts to use FU when none available
737 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.87% # attempts to use FU when none available
738 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.87% # attempts to use FU when none available
739 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available
740 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.87% # attempts to use FU when none available
741 system.cpu.iq.fu_full::MemRead 45774518 26.85% 61.72% # attempts to use FU when none available
742 system.cpu.iq.fu_full::MemWrite 64550245 37.86% 99.58% # attempts to use FU when none available
743 system.cpu.iq.fu_full::FloatMemRead 65013 0.04% 99.62% # attempts to use FU when none available
744 system.cpu.iq.fu_full::FloatMemWrite 650262 0.38% 100.00% # attempts to use FU when none available
745 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
746 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
747 system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
748 system.cpu.iq.FU_type_0::IntAlu 675222587 66.82% 66.82% # Type of FU issued
749 system.cpu.iq.FU_type_0::IntMult 2579661 0.26% 67.07% # Type of FU issued
750 system.cpu.iq.FU_type_0::IntDiv 123552 0.01% 67.08% # Type of FU issued
751 system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 67.08% # Type of FU issued
752 system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 67.08% # Type of FU issued
753 system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 67.08% # Type of FU issued
754 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued
755 system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued
756 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued
757 system.cpu.iq.FU_type_0::FloatMisc 118042 0.01% 67.10% # Type of FU issued
758 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued
759 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued
760 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued
761 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued
762 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued
763 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued
764 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued
765 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued
766 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued
767 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued
768 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued
769 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued
770 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued
771 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued
772 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued
773 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued
774 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued
775 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued
776 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
777 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
778 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
779 system.cpu.iq.FU_type_0::MemRead 178525210 17.67% 84.76% # Type of FU issued
780 system.cpu.iq.FU_type_0::MemWrite 153211297 15.16% 99.92% # Type of FU issued
781 system.cpu.iq.FU_type_0::FloatMemRead 117761 0.01% 99.93% # Type of FU issued
782 system.cpu.iq.FU_type_0::FloatMemWrite 674889 0.07% 100.00% # Type of FU issued
783 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
784 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
785 system.cpu.iq.FU_type_0::total 1010573430 # Type of FU issued
786 system.cpu.iq.rate 0.712323 # Inst issue rate
787 system.cpu.iq.fu_busy_cnt 170492776 # FU busy when requested
788 system.cpu.iq.fu_busy_rate 0.168709 # FU busy rate (busy events/executed inst)
789 system.cpu.iq.int_inst_queue_reads 3559085350 # Number of integer instruction queue reads
790 system.cpu.iq.int_inst_queue_writes 1084154908 # Number of integer instruction queue writes
791 system.cpu.iq.int_inst_queue_wakeup_accesses 991977756 # Number of integer instruction queue wakeup accesses
792 system.cpu.iq.fp_inst_queue_reads 2539803 # Number of floating instruction queue reads
793 system.cpu.iq.fp_inst_queue_writes 933979 # Number of floating instruction queue writes
794 system.cpu.iq.fp_inst_queue_wakeup_accesses 905255 # Number of floating instruction queue wakeup accesses
795 system.cpu.iq.int_alu_accesses 1179439202 # Number of integer alu accesses
796 system.cpu.iq.fp_alu_accesses 1626993 # Number of floating point alu accesses
797 system.cpu.iew.lsq.thread0.forwLoads 4435926 # Number of loads that had data forwarded from stores
798 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
799 system.cpu.iew.lsq.thread0.squashedLoads 14385160 # Number of loads squashed
800 system.cpu.iew.lsq.thread0.ignoredResponses 15174 # Number of memory responses ignored because the instruction is squashed
801 system.cpu.iew.lsq.thread0.memOrderViolation 144472 # Number of memory ordering violations
802 system.cpu.iew.lsq.thread0.squashedStores 6174251 # Number of stores squashed
803 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
804 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
805 system.cpu.iew.lsq.thread0.rescheduledLoads 2629445 # Number of loads that were rescheduled
806 system.cpu.iew.lsq.thread0.cacheBlocked 1524875 # Number of times an access to memory failed due to the cache being blocked
807 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
808 system.cpu.iew.iewSquashCycles 9530630 # Number of cycles IEW is squashing
809 system.cpu.iew.iewBlockCycles 7210038 # Number of cycles IEW is blocking
810 system.cpu.iew.iewUnblockCycles 4323845 # Number of cycles IEW is unblocking
811 system.cpu.iew.iewDispatchedInsts 1023153770 # Number of instructions dispatched to IQ
812 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
813 system.cpu.iew.iewDispLoadInsts 178961087 # Number of dispatched load instructions
814 system.cpu.iew.iewDispStoreInsts 155538156 # Number of dispatched store instructions
815 system.cpu.iew.iewDispNonSpecInsts 7437223 # Number of dispatched non-speculative instructions
816 system.cpu.iew.iewIQFullEvents 69213 # Number of times the IQ has become full, causing a stall
817 system.cpu.iew.iewLSQFullEvents 4169498 # Number of times the LSQ has become full, causing a stall
818 system.cpu.iew.memOrderViolationEvents 144472 # Number of memory order violations
819 system.cpu.iew.predictedTakenIncorrect 3542728 # Number of branches that were predicted taken incorrectly
820 system.cpu.iew.predictedNotTakenIncorrect 5585702 # Number of branches that were predicted not taken incorrectly
821 system.cpu.iew.branchMispredicts 9128430 # Number of branch mispredicts detected at execute
822 system.cpu.iew.iewExecutedInsts 998939859 # Number of executed instructions
823 system.cpu.iew.iewExecLoadInsts 174475303 # Number of load instructions executed
824 system.cpu.iew.iewExecSquashedInsts 10677060 # Number of squashed instructions skipped in execute
825 system.cpu.iew.exec_swp 0 # number of swp insts executed
826 system.cpu.iew.exec_nop 241295 # number of nop insts executed
827 system.cpu.iew.exec_refs 326482764 # number of memory reference insts executed
828 system.cpu.iew.exec_branches 185483896 # Number of branches executed
829 system.cpu.iew.exec_stores 152007461 # Number of stores executed
830 system.cpu.iew.exec_rate 0.704123 # Inst execution rate
831 system.cpu.iew.wb_sent 993723823 # cumulative count of insts sent to commit
832 system.cpu.iew.wb_count 992883011 # cumulative count of insts written-back
833 system.cpu.iew.wb_producers 420701773 # num instructions producing a value
834 system.cpu.iew.wb_consumers 671731184 # num instructions consuming a value
835 system.cpu.iew.wb_rate 0.699853 # insts written-back per cycle
836 system.cpu.iew.wb_fanout 0.626295 # average fanout of values written-back
837 system.cpu.commit.commitSquashedInsts 52581924 # The number of squashed insts skipped by commit
838 system.cpu.commit.commitNonSpecStalls 11624075 # The number of times commit has been forced to stall to communicate backwards
839 system.cpu.commit.branchMispredicts 8681545 # The number of times a branch was mispredicted
840 system.cpu.commit.committed_per_cycle::samples 1354317292 # Number of insts commited each cycle
841 system.cpu.commit.committed_per_cycle::mean 0.709493 # Number of insts commited each cycle
842 system.cpu.commit.committed_per_cycle::stdev 1.365584 # Number of insts commited each cycle
843 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
844 system.cpu.commit.committed_per_cycle::0 893350952 65.96% 65.96% # Number of insts commited each cycle
845 system.cpu.commit.committed_per_cycle::1 231145639 17.07% 83.03% # Number of insts commited each cycle
846 system.cpu.commit.committed_per_cycle::2 123165028 9.09% 92.12% # Number of insts commited each cycle
847 system.cpu.commit.committed_per_cycle::3 37514552 2.77% 94.89% # Number of insts commited each cycle
848 system.cpu.commit.committed_per_cycle::4 29252763 2.16% 97.05% # Number of insts commited each cycle
849 system.cpu.commit.committed_per_cycle::5 14325561 1.06% 98.11% # Number of insts commited each cycle
850 system.cpu.commit.committed_per_cycle::6 8938173 0.66% 98.77% # Number of insts commited each cycle
851 system.cpu.commit.committed_per_cycle::7 4404967 0.33% 99.10% # Number of insts commited each cycle
852 system.cpu.commit.committed_per_cycle::8 12219657 0.90% 100.00% # Number of insts commited each cycle
853 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
854 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
855 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
856 system.cpu.commit.committed_per_cycle::total 1354317292 # Number of insts commited each cycle
857 system.cpu.commit.committedInsts 807652759 # Number of instructions committed
858 system.cpu.commit.committedOps 960879271 # Number of ops (including micro ops) committed
859 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
860 system.cpu.commit.refs 313939831 # Number of memory references committed
861 system.cpu.commit.loads 164575926 # Number of loads committed
862 system.cpu.commit.membars 7185354 # Number of memory barriers committed
863 system.cpu.commit.branches 178524482 # Number of branches committed
864 system.cpu.commit.fp_insts 893967 # Number of committed floating point instructions.
865 system.cpu.commit.int_insts 893684330 # Number of committed integer instructions.
866 system.cpu.commit.function_calls 25910780 # Number of function calls committed.
867 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
868 system.cpu.commit.op_class_0::IntAlu 644536442 67.08% 67.08% # Class of committed instruction
869 system.cpu.commit.op_class_0::IntMult 2193608 0.23% 67.31% # Class of committed instruction
870 system.cpu.commit.op_class_0::IntDiv 98465 0.01% 67.32% # Class of committed instruction
871 system.cpu.commit.op_class_0::FloatAdd 8 0.00% 67.32% # Class of committed instruction
872 system.cpu.commit.op_class_0::FloatCmp 13 0.00% 67.32% # Class of committed instruction
873 system.cpu.commit.op_class_0::FloatCvt 21 0.00% 67.32% # Class of committed instruction
874 system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.32% # Class of committed instruction
875 system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.32% # Class of committed instruction
876 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.32% # Class of committed instruction
877 system.cpu.commit.op_class_0::FloatMisc 110883 0.01% 67.33% # Class of committed instruction
878 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.33% # Class of committed instruction
879 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.33% # Class of committed instruction
880 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.33% # Class of committed instruction
881 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.33% # Class of committed instruction
882 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.33% # Class of committed instruction
883 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.33% # Class of committed instruction
884 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.33% # Class of committed instruction
885 system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.33% # Class of committed instruction
886 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.33% # Class of committed instruction
887 system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.33% # Class of committed instruction
888 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.33% # Class of committed instruction
889 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.33% # Class of committed instruction
890 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.33% # Class of committed instruction
891 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.33% # Class of committed instruction
892 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.33% # Class of committed instruction
893 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.33% # Class of committed instruction
894 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.33% # Class of committed instruction
895 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.33% # Class of committed instruction
896 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.33% # Class of committed instruction
897 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.33% # Class of committed instruction
898 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.33% # Class of committed instruction
899 system.cpu.commit.op_class_0::MemRead 164464107 17.12% 84.44% # Class of committed instruction
900 system.cpu.commit.op_class_0::MemWrite 148692682 15.47% 99.92% # Class of committed instruction
901 system.cpu.commit.op_class_0::FloatMemRead 111819 0.01% 99.93% # Class of committed instruction
902 system.cpu.commit.op_class_0::FloatMemWrite 671223 0.07% 100.00% # Class of committed instruction
903 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
904 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
905 system.cpu.commit.op_class_0::total 960879271 # Class of committed instruction
906 system.cpu.commit.bw_lim_events 12219657 # number cycles where commit BW limit reached
907 system.cpu.rob.rob_reads 2347791153 # The number of ROB reads
908 system.cpu.rob.rob_writes 2039089805 # The number of ROB writes
909 system.cpu.timesIdled 8233460 # Number of times that the entire CPU went into an idle state and unscheduled itself
910 system.cpu.idleCycles 52122622 # Total number of cycles that the CPU has spent unscheduled due to idling
911 system.cpu.quiesceCycles 101137217350 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
912 system.cpu.committedInsts 807652759 # Number of Instructions Simulated
913 system.cpu.committedOps 960879271 # Number of Ops (including micro ops) Simulated
914 system.cpu.cpi 1.756574 # CPI: Cycles Per Instruction
915 system.cpu.cpi_total 1.756574 # CPI: Total CPI of All Threads
916 system.cpu.ipc 0.569290 # IPC: Instructions Per Cycle
917 system.cpu.ipc_total 0.569290 # IPC: Total IPC of All Threads
918 system.cpu.int_regfile_reads 1178021092 # number of integer regfile reads
919 system.cpu.int_regfile_writes 719548586 # number of integer regfile writes
920 system.cpu.fp_regfile_reads 1455011 # number of floating regfile reads
921 system.cpu.fp_regfile_writes 777624 # number of floating regfile writes
922 system.cpu.cc_regfile_reads 183031164 # number of cc regfile reads
923 system.cpu.cc_regfile_writes 183683629 # number of cc regfile writes
924 system.cpu.misc_regfile_reads 2245464732 # number of misc regfile reads
925 system.cpu.misc_regfile_writes 11742996 # number of misc regfile writes
926 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
927 system.cpu.dcache.tags.replacements 10097387 # number of replacements
928 system.cpu.dcache.tags.tagsinuse 511.998168 # Cycle average of tags in use
929 system.cpu.dcache.tags.total_refs 291447803 # Total number of references to valid blocks.
930 system.cpu.dcache.tags.sampled_refs 10097899 # Sample count of references to valid blocks.
931 system.cpu.dcache.tags.avg_refs 28.862222 # Average number of references to valid blocks.
932 system.cpu.dcache.tags.warmup_cycle 194046500 # Cycle when the warmup percentage was hit.
933 system.cpu.dcache.tags.occ_blocks::cpu.data 511.998168 # Average occupied blocks per requestor
934 system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
935 system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
936 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
937 system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
938 system.cpu.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
939 system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
940 system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
941 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
942 system.cpu.dcache.tags.tag_accesses 1275104379 # Number of tag accesses
943 system.cpu.dcache.tags.data_accesses 1275104379 # Number of data accesses
944 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
945 system.cpu.dcache.ReadReq_hits::cpu.data 151424979 # number of ReadReq hits
946 system.cpu.dcache.ReadReq_hits::total 151424979 # number of ReadReq hits
947 system.cpu.dcache.WriteReq_hits::cpu.data 131950159 # number of WriteReq hits
948 system.cpu.dcache.WriteReq_hits::total 131950159 # number of WriteReq hits
949 system.cpu.dcache.SoftPFReq_hits::cpu.data 388682 # number of SoftPFReq hits
950 system.cpu.dcache.SoftPFReq_hits::total 388682 # number of SoftPFReq hits
951 system.cpu.dcache.WriteLineReq_hits::cpu.data 326177 # number of WriteLineReq hits
952 system.cpu.dcache.WriteLineReq_hits::total 326177 # number of WriteLineReq hits
953 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3459521 # number of LoadLockedReq hits
954 system.cpu.dcache.LoadLockedReq_hits::total 3459521 # number of LoadLockedReq hits
955 system.cpu.dcache.StoreCondReq_hits::cpu.data 3868336 # number of StoreCondReq hits
956 system.cpu.dcache.StoreCondReq_hits::total 3868336 # number of StoreCondReq hits
957 system.cpu.dcache.demand_hits::cpu.data 283701315 # number of demand (read+write) hits
958 system.cpu.dcache.demand_hits::total 283701315 # number of demand (read+write) hits
959 system.cpu.dcache.overall_hits::cpu.data 284089997 # number of overall hits
960 system.cpu.dcache.overall_hits::total 284089997 # number of overall hits
961 system.cpu.dcache.ReadReq_misses::cpu.data 9913119 # number of ReadReq misses
962 system.cpu.dcache.ReadReq_misses::total 9913119 # number of ReadReq misses
963 system.cpu.dcache.WriteReq_misses::cpu.data 11970495 # number of WriteReq misses
964 system.cpu.dcache.WriteReq_misses::total 11970495 # number of WriteReq misses
965 system.cpu.dcache.SoftPFReq_misses::cpu.data 1253745 # number of SoftPFReq misses
966 system.cpu.dcache.SoftPFReq_misses::total 1253745 # number of SoftPFReq misses
967 system.cpu.dcache.WriteLineReq_misses::cpu.data 1236891 # number of WriteLineReq misses
968 system.cpu.dcache.WriteLineReq_misses::total 1236891 # number of WriteLineReq misses
969 system.cpu.dcache.LoadLockedReq_misses::cpu.data 459501 # number of LoadLockedReq misses
970 system.cpu.dcache.LoadLockedReq_misses::total 459501 # number of LoadLockedReq misses
971 system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses
972 system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
973 system.cpu.dcache.demand_misses::cpu.data 23120505 # number of demand (read+write) misses
974 system.cpu.dcache.demand_misses::total 23120505 # number of demand (read+write) misses
975 system.cpu.dcache.overall_misses::cpu.data 24374250 # number of overall misses
976 system.cpu.dcache.overall_misses::total 24374250 # number of overall misses
977 system.cpu.dcache.ReadReq_miss_latency::cpu.data 163455721000 # number of ReadReq miss cycles
978 system.cpu.dcache.ReadReq_miss_latency::total 163455721000 # number of ReadReq miss cycles
979 system.cpu.dcache.WriteReq_miss_latency::cpu.data 418494791659 # number of WriteReq miss cycles
980 system.cpu.dcache.WriteReq_miss_latency::total 418494791659 # number of WriteReq miss cycles
981 system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27820801905 # number of WriteLineReq miss cycles
982 system.cpu.dcache.WriteLineReq_miss_latency::total 27820801905 # number of WriteLineReq miss cycles
983 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6946845500 # number of LoadLockedReq miss cycles
984 system.cpu.dcache.LoadLockedReq_miss_latency::total 6946845500 # number of LoadLockedReq miss cycles
985 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 284500 # number of StoreCondReq miss cycles
986 system.cpu.dcache.StoreCondReq_miss_latency::total 284500 # number of StoreCondReq miss cycles
987 system.cpu.dcache.demand_miss_latency::cpu.data 609771314564 # number of demand (read+write) miss cycles
988 system.cpu.dcache.demand_miss_latency::total 609771314564 # number of demand (read+write) miss cycles
989 system.cpu.dcache.overall_miss_latency::cpu.data 609771314564 # number of overall miss cycles
990 system.cpu.dcache.overall_miss_latency::total 609771314564 # number of overall miss cycles
991 system.cpu.dcache.ReadReq_accesses::cpu.data 161338098 # number of ReadReq accesses(hits+misses)
992 system.cpu.dcache.ReadReq_accesses::total 161338098 # number of ReadReq accesses(hits+misses)
993 system.cpu.dcache.WriteReq_accesses::cpu.data 143920654 # number of WriteReq accesses(hits+misses)
994 system.cpu.dcache.WriteReq_accesses::total 143920654 # number of WriteReq accesses(hits+misses)
995 system.cpu.dcache.SoftPFReq_accesses::cpu.data 1642427 # number of SoftPFReq accesses(hits+misses)
996 system.cpu.dcache.SoftPFReq_accesses::total 1642427 # number of SoftPFReq accesses(hits+misses)
997 system.cpu.dcache.WriteLineReq_accesses::cpu.data 1563068 # number of WriteLineReq accesses(hits+misses)
998 system.cpu.dcache.WriteLineReq_accesses::total 1563068 # number of WriteLineReq accesses(hits+misses)
999 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919022 # number of LoadLockedReq accesses(hits+misses)
1000 system.cpu.dcache.LoadLockedReq_accesses::total 3919022 # number of LoadLockedReq accesses(hits+misses)
1001 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3868345 # number of StoreCondReq accesses(hits+misses)
1002 system.cpu.dcache.StoreCondReq_accesses::total 3868345 # number of StoreCondReq accesses(hits+misses)
1003 system.cpu.dcache.demand_accesses::cpu.data 306821820 # number of demand (read+write) accesses
1004 system.cpu.dcache.demand_accesses::total 306821820 # number of demand (read+write) accesses
1005 system.cpu.dcache.overall_accesses::cpu.data 308464247 # number of overall (read+write) accesses
1006 system.cpu.dcache.overall_accesses::total 308464247 # number of overall (read+write) accesses
1007 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061443 # miss rate for ReadReq accesses
1008 system.cpu.dcache.ReadReq_miss_rate::total 0.061443 # miss rate for ReadReq accesses
1009 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083174 # miss rate for WriteReq accesses
1010 system.cpu.dcache.WriteReq_miss_rate::total 0.083174 # miss rate for WriteReq accesses
1011 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.763349 # miss rate for SoftPFReq accesses
1012 system.cpu.dcache.SoftPFReq_miss_rate::total 0.763349 # miss rate for SoftPFReq accesses
1013 system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791323 # miss rate for WriteLineReq accesses
1014 system.cpu.dcache.WriteLineReq_miss_rate::total 0.791323 # miss rate for WriteLineReq accesses
1015 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.117249 # miss rate for LoadLockedReq accesses
1016 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.117249 # miss rate for LoadLockedReq accesses
1017 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
1018 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
1019 system.cpu.dcache.demand_miss_rate::cpu.data 0.075355 # miss rate for demand accesses
1020 system.cpu.dcache.demand_miss_rate::total 0.075355 # miss rate for demand accesses
1021 system.cpu.dcache.overall_miss_rate::cpu.data 0.079018 # miss rate for overall accesses
1022 system.cpu.dcache.overall_miss_rate::total 0.079018 # miss rate for overall accesses
1023 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16488.828693 # average ReadReq miss latency
1024 system.cpu.dcache.ReadReq_avg_miss_latency::total 16488.828693 # average ReadReq miss latency
1025 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34960.525163 # average WriteReq miss latency
1026 system.cpu.dcache.WriteReq_avg_miss_latency::total 34960.525163 # average WriteReq miss latency
1027 system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22492.525134 # average WriteLineReq miss latency
1028 system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22492.525134 # average WriteLineReq miss latency
1029 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15118.238045 # average LoadLockedReq miss latency
1030 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15118.238045 # average LoadLockedReq miss latency
1031 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 31611.111111 # average StoreCondReq miss latency
1032 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 31611.111111 # average StoreCondReq miss latency
1033 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26373.615739 # average overall miss latency
1034 system.cpu.dcache.demand_avg_miss_latency::total 26373.615739 # average overall miss latency
1035 system.cpu.dcache.overall_avg_miss_latency::cpu.data 25017.028814 # average overall miss latency
1036 system.cpu.dcache.overall_avg_miss_latency::total 25017.028814 # average overall miss latency
1037 system.cpu.dcache.blocked_cycles::no_mshrs 19489299 # number of cycles access was blocked
1038 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1039 system.cpu.dcache.blocked::no_mshrs 1643530 # number of cycles access was blocked
1040 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1041 system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.858195 # average number of cycles each access was blocked
1042 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1043 system.cpu.dcache.writebacks::writebacks 7764980 # number of writebacks
1044 system.cpu.dcache.writebacks::total 7764980 # number of writebacks
1045 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4590646 # number of ReadReq MSHR hits
1046 system.cpu.dcache.ReadReq_mshr_hits::total 4590646 # number of ReadReq MSHR hits
1047 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9875948 # number of WriteReq MSHR hits
1048 system.cpu.dcache.WriteReq_mshr_hits::total 9875948 # number of WriteReq MSHR hits
1049 system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6846 # number of WriteLineReq MSHR hits
1050 system.cpu.dcache.WriteLineReq_mshr_hits::total 6846 # number of WriteLineReq MSHR hits
1051 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 225673 # number of LoadLockedReq MSHR hits
1052 system.cpu.dcache.LoadLockedReq_mshr_hits::total 225673 # number of LoadLockedReq MSHR hits
1053 system.cpu.dcache.demand_mshr_hits::cpu.data 14473440 # number of demand (read+write) MSHR hits
1054 system.cpu.dcache.demand_mshr_hits::total 14473440 # number of demand (read+write) MSHR hits
1055 system.cpu.dcache.overall_mshr_hits::cpu.data 14473440 # number of overall MSHR hits
1056 system.cpu.dcache.overall_mshr_hits::total 14473440 # number of overall MSHR hits
1057 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5322473 # number of ReadReq MSHR misses
1058 system.cpu.dcache.ReadReq_mshr_misses::total 5322473 # number of ReadReq MSHR misses
1059 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2094547 # number of WriteReq MSHR misses
1060 system.cpu.dcache.WriteReq_mshr_misses::total 2094547 # number of WriteReq MSHR misses
1061 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1246940 # number of SoftPFReq MSHR misses
1062 system.cpu.dcache.SoftPFReq_mshr_misses::total 1246940 # number of SoftPFReq MSHR misses
1063 system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1230045 # number of WriteLineReq MSHR misses
1064 system.cpu.dcache.WriteLineReq_mshr_misses::total 1230045 # number of WriteLineReq MSHR misses
1065 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233828 # number of LoadLockedReq MSHR misses
1066 system.cpu.dcache.LoadLockedReq_mshr_misses::total 233828 # number of LoadLockedReq MSHR misses
1067 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses
1068 system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
1069 system.cpu.dcache.demand_mshr_misses::cpu.data 8647065 # number of demand (read+write) MSHR misses
1070 system.cpu.dcache.demand_mshr_misses::total 8647065 # number of demand (read+write) MSHR misses
1071 system.cpu.dcache.overall_mshr_misses::cpu.data 9894005 # number of overall MSHR misses
1072 system.cpu.dcache.overall_mshr_misses::total 9894005 # number of overall MSHR misses
1073 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable
1074 system.cpu.dcache.ReadReq_mshr_uncacheable::total 33590 # number of ReadReq MSHR uncacheable
1075 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable
1076 system.cpu.dcache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable
1077 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses
1078 system.cpu.dcache.overall_mshr_uncacheable_misses::total 67199 # number of overall MSHR uncacheable misses
1079 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84299556500 # number of ReadReq MSHR miss cycles
1080 system.cpu.dcache.ReadReq_mshr_miss_latency::total 84299556500 # number of ReadReq MSHR miss cycles
1081 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 70150658430 # number of WriteReq MSHR miss cycles
1082 system.cpu.dcache.WriteReq_mshr_miss_latency::total 70150658430 # number of WriteReq MSHR miss cycles
1083 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22795031000 # number of SoftPFReq MSHR miss cycles
1084 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22795031000 # number of SoftPFReq MSHR miss cycles
1085 system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26312863405 # number of WriteLineReq MSHR miss cycles
1086 system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26312863405 # number of WriteLineReq MSHR miss cycles
1087 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3251889000 # number of LoadLockedReq MSHR miss cycles
1088 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3251889000 # number of LoadLockedReq MSHR miss cycles
1089 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 275500 # number of StoreCondReq MSHR miss cycles
1090 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 275500 # number of StoreCondReq MSHR miss cycles
1091 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 180763078335 # number of demand (read+write) MSHR miss cycles
1092 system.cpu.dcache.demand_mshr_miss_latency::total 180763078335 # number of demand (read+write) MSHR miss cycles
1093 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203558109335 # number of overall MSHR miss cycles
1094 system.cpu.dcache.overall_mshr_miss_latency::total 203558109335 # number of overall MSHR miss cycles
1095 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6204454000 # number of ReadReq MSHR uncacheable cycles
1096 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6204454000 # number of ReadReq MSHR uncacheable cycles
1097 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6204454000 # number of overall MSHR uncacheable cycles
1098 system.cpu.dcache.overall_mshr_uncacheable_latency::total 6204454000 # number of overall MSHR uncacheable cycles
1099 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032990 # mshr miss rate for ReadReq accesses
1100 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032990 # mshr miss rate for ReadReq accesses
1101 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014553 # mshr miss rate for WriteReq accesses
1102 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses
1103 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.759206 # mshr miss rate for SoftPFReq accesses
1104 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.759206 # mshr miss rate for SoftPFReq accesses
1105 system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786943 # mshr miss rate for WriteLineReq accesses
1106 system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786943 # mshr miss rate for WriteLineReq accesses
1107 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059665 # mshr miss rate for LoadLockedReq accesses
1108 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059665 # mshr miss rate for LoadLockedReq accesses
1109 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
1110 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
1111 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028183 # mshr miss rate for demand accesses
1112 system.cpu.dcache.demand_mshr_miss_rate::total 0.028183 # mshr miss rate for demand accesses
1113 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032075 # mshr miss rate for overall accesses
1114 system.cpu.dcache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses
1115 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15838.418814 # average ReadReq mshr miss latency
1116 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15838.418814 # average ReadReq mshr miss latency
1117 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33492.043115 # average WriteReq mshr miss latency
1118 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33492.043115 # average WriteReq mshr miss latency
1119 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18280.776140 # average SoftPFReq mshr miss latency
1120 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18280.776140 # average SoftPFReq mshr miss latency
1121 system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21391.789248 # average WriteLineReq mshr miss latency
1122 system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21391.789248 # average WriteLineReq mshr miss latency
1123 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13907.183913 # average LoadLockedReq mshr miss latency
1124 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13907.183913 # average LoadLockedReq mshr miss latency
1125 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 30611.111111 # average StoreCondReq mshr miss latency
1126 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 30611.111111 # average StoreCondReq mshr miss latency
1127 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20904.558753 # average overall mshr miss latency
1128 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20904.558753 # average overall mshr miss latency
1129 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20573.883815 # average overall mshr miss latency
1130 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20573.883815 # average overall mshr miss latency
1131 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184711.342662 # average ReadReq mshr uncacheable latency
1132 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184711.342662 # average ReadReq mshr uncacheable latency
1133 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92329.558476 # average overall mshr uncacheable latency
1134 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92329.558476 # average overall mshr uncacheable latency
1135 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1136 system.cpu.icache.tags.replacements 15304958 # number of replacements
1137 system.cpu.icache.tags.tagsinuse 511.969276 # Cycle average of tags in use
1138 system.cpu.icache.tags.total_refs 317502771 # Total number of references to valid blocks.
1139 system.cpu.icache.tags.sampled_refs 15305470 # Sample count of references to valid blocks.
1140 system.cpu.icache.tags.avg_refs 20.744399 # Average number of references to valid blocks.
1141 system.cpu.icache.tags.warmup_cycle 12156673500 # Cycle when the warmup percentage was hit.
1142 system.cpu.icache.tags.occ_blocks::cpu.inst 511.969276 # Average occupied blocks per requestor
1143 system.cpu.icache.tags.occ_percent::cpu.inst 0.999940 # Average percentage of cache occupancy
1144 system.cpu.icache.tags.occ_percent::total 0.999940 # Average percentage of cache occupancy
1145 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1146 system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
1147 system.cpu.icache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
1148 system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
1149 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1150 system.cpu.icache.tags.tag_accesses 348872656 # Number of tag accesses
1151 system.cpu.icache.tags.data_accesses 348872656 # Number of data accesses
1152 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1153 system.cpu.icache.ReadReq_hits::cpu.inst 317502771 # number of ReadReq hits
1154 system.cpu.icache.ReadReq_hits::total 317502771 # number of ReadReq hits
1155 system.cpu.icache.demand_hits::cpu.inst 317502771 # number of demand (read+write) hits
1156 system.cpu.icache.demand_hits::total 317502771 # number of demand (read+write) hits
1157 system.cpu.icache.overall_hits::cpu.inst 317502771 # number of overall hits
1158 system.cpu.icache.overall_hits::total 317502771 # number of overall hits
1159 system.cpu.icache.ReadReq_misses::cpu.inst 16064183 # number of ReadReq misses
1160 system.cpu.icache.ReadReq_misses::total 16064183 # number of ReadReq misses
1161 system.cpu.icache.demand_misses::cpu.inst 16064183 # number of demand (read+write) misses
1162 system.cpu.icache.demand_misses::total 16064183 # number of demand (read+write) misses
1163 system.cpu.icache.overall_misses::cpu.inst 16064183 # number of overall misses
1164 system.cpu.icache.overall_misses::total 16064183 # number of overall misses
1165 system.cpu.icache.ReadReq_miss_latency::cpu.inst 215226774877 # number of ReadReq miss cycles
1166 system.cpu.icache.ReadReq_miss_latency::total 215226774877 # number of ReadReq miss cycles
1167 system.cpu.icache.demand_miss_latency::cpu.inst 215226774877 # number of demand (read+write) miss cycles
1168 system.cpu.icache.demand_miss_latency::total 215226774877 # number of demand (read+write) miss cycles
1169 system.cpu.icache.overall_miss_latency::cpu.inst 215226774877 # number of overall miss cycles
1170 system.cpu.icache.overall_miss_latency::total 215226774877 # number of overall miss cycles
1171 system.cpu.icache.ReadReq_accesses::cpu.inst 333566954 # number of ReadReq accesses(hits+misses)
1172 system.cpu.icache.ReadReq_accesses::total 333566954 # number of ReadReq accesses(hits+misses)
1173 system.cpu.icache.demand_accesses::cpu.inst 333566954 # number of demand (read+write) accesses
1174 system.cpu.icache.demand_accesses::total 333566954 # number of demand (read+write) accesses
1175 system.cpu.icache.overall_accesses::cpu.inst 333566954 # number of overall (read+write) accesses
1176 system.cpu.icache.overall_accesses::total 333566954 # number of overall (read+write) accesses
1177 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.048159 # miss rate for ReadReq accesses
1178 system.cpu.icache.ReadReq_miss_rate::total 0.048159 # miss rate for ReadReq accesses
1179 system.cpu.icache.demand_miss_rate::cpu.inst 0.048159 # miss rate for demand accesses
1180 system.cpu.icache.demand_miss_rate::total 0.048159 # miss rate for demand accesses
1181 system.cpu.icache.overall_miss_rate::cpu.inst 0.048159 # miss rate for overall accesses
1182 system.cpu.icache.overall_miss_rate::total 0.048159 # miss rate for overall accesses
1183 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13397.928477 # average ReadReq miss latency
1184 system.cpu.icache.ReadReq_avg_miss_latency::total 13397.928477 # average ReadReq miss latency
1185 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13397.928477 # average overall miss latency
1186 system.cpu.icache.demand_avg_miss_latency::total 13397.928477 # average overall miss latency
1187 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13397.928477 # average overall miss latency
1188 system.cpu.icache.overall_avg_miss_latency::total 13397.928477 # average overall miss latency
1189 system.cpu.icache.blocked_cycles::no_mshrs 20885 # number of cycles access was blocked
1190 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1191 system.cpu.icache.blocked::no_mshrs 1543 # number of cycles access was blocked
1192 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1193 system.cpu.icache.avg_blocked_cycles::no_mshrs 13.535321 # average number of cycles each access was blocked
1194 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1195 system.cpu.icache.writebacks::writebacks 15304958 # number of writebacks
1196 system.cpu.icache.writebacks::total 15304958 # number of writebacks
1197 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 758480 # number of ReadReq MSHR hits
1198 system.cpu.icache.ReadReq_mshr_hits::total 758480 # number of ReadReq MSHR hits
1199 system.cpu.icache.demand_mshr_hits::cpu.inst 758480 # number of demand (read+write) MSHR hits
1200 system.cpu.icache.demand_mshr_hits::total 758480 # number of demand (read+write) MSHR hits
1201 system.cpu.icache.overall_mshr_hits::cpu.inst 758480 # number of overall MSHR hits
1202 system.cpu.icache.overall_mshr_hits::total 758480 # number of overall MSHR hits
1203 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15305703 # number of ReadReq MSHR misses
1204 system.cpu.icache.ReadReq_mshr_misses::total 15305703 # number of ReadReq MSHR misses
1205 system.cpu.icache.demand_mshr_misses::cpu.inst 15305703 # number of demand (read+write) MSHR misses
1206 system.cpu.icache.demand_mshr_misses::total 15305703 # number of demand (read+write) MSHR misses
1207 system.cpu.icache.overall_mshr_misses::cpu.inst 15305703 # number of overall MSHR misses
1208 system.cpu.icache.overall_mshr_misses::total 15305703 # number of overall MSHR misses
1209 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable
1210 system.cpu.icache.ReadReq_mshr_uncacheable::total 2094 # number of ReadReq MSHR uncacheable
1211 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses
1212 system.cpu.icache.overall_mshr_uncacheable_misses::total 2094 # number of overall MSHR uncacheable misses
1213 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193058693887 # number of ReadReq MSHR miss cycles
1214 system.cpu.icache.ReadReq_mshr_miss_latency::total 193058693887 # number of ReadReq MSHR miss cycles
1215 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193058693887 # number of demand (read+write) MSHR miss cycles
1216 system.cpu.icache.demand_mshr_miss_latency::total 193058693887 # number of demand (read+write) MSHR miss cycles
1217 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193058693887 # number of overall MSHR miss cycles
1218 system.cpu.icache.overall_mshr_miss_latency::total 193058693887 # number of overall MSHR miss cycles
1219 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 174071500 # number of ReadReq MSHR uncacheable cycles
1220 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 174071500 # number of ReadReq MSHR uncacheable cycles
1221 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 174071500 # number of overall MSHR uncacheable cycles
1222 system.cpu.icache.overall_mshr_uncacheable_latency::total 174071500 # number of overall MSHR uncacheable cycles
1223 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for ReadReq accesses
1224 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.045885 # mshr miss rate for ReadReq accesses
1225 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for demand accesses
1226 system.cpu.icache.demand_mshr_miss_rate::total 0.045885 # mshr miss rate for demand accesses
1227 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for overall accesses
1228 system.cpu.icache.overall_mshr_miss_rate::total 0.045885 # mshr miss rate for overall accesses
1229 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12613.513661 # average ReadReq mshr miss latency
1230 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12613.513661 # average ReadReq mshr miss latency
1231 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency
1232 system.cpu.icache.demand_avg_mshr_miss_latency::total 12613.513661 # average overall mshr miss latency
1233 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency
1234 system.cpu.icache.overall_avg_mshr_miss_latency::total 12613.513661 # average overall mshr miss latency
1235 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 83128.701051 # average ReadReq mshr uncacheable latency
1236 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 83128.701051 # average ReadReq mshr uncacheable latency
1237 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 83128.701051 # average overall mshr uncacheable latency
1238 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 83128.701051 # average overall mshr uncacheable latency
1239 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1240 system.cpu.l2cache.tags.replacements 1248689 # number of replacements
1241 system.cpu.l2cache.tags.tagsinuse 65406.058647 # Cycle average of tags in use
1242 system.cpu.l2cache.tags.total_refs 49295549 # Total number of references to valid blocks.
1243 system.cpu.l2cache.tags.sampled_refs 1311963 # Sample count of references to valid blocks.
1244 system.cpu.l2cache.tags.avg_refs 37.573887 # Average number of references to valid blocks.
1245 system.cpu.l2cache.tags.warmup_cycle 1068241000 # Cycle when the warmup percentage was hit.
1246 system.cpu.l2cache.tags.occ_blocks::writebacks 9667.637617 # Average occupied blocks per requestor
1247 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 499.308772 # Average occupied blocks per requestor
1248 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 609.219516 # Average occupied blocks per requestor
1249 system.cpu.l2cache.tags.occ_blocks::cpu.inst 6963.202905 # Average occupied blocks per requestor
1250 system.cpu.l2cache.tags.occ_blocks::cpu.data 47666.689838 # Average occupied blocks per requestor
1251 system.cpu.l2cache.tags.occ_percent::writebacks 0.147516 # Average percentage of cache occupancy
1252 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007619 # Average percentage of cache occupancy
1253 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.009296 # Average percentage of cache occupancy
1254 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106250 # Average percentage of cache occupancy
1255 system.cpu.l2cache.tags.occ_percent::cpu.data 0.727336 # Average percentage of cache occupancy
1256 system.cpu.l2cache.tags.occ_percent::total 0.998017 # Average percentage of cache occupancy
1257 system.cpu.l2cache.tags.occ_task_id_blocks::1023 512 # Occupied blocks per task id
1258 system.cpu.l2cache.tags.occ_task_id_blocks::1024 62762 # Occupied blocks per task id
1259 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 512 # Occupied blocks per task id
1260 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
1261 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
1262 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1132 # Occupied blocks per task id
1263 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5479 # Occupied blocks per task id
1264 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55729 # Occupied blocks per task id
1265 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007812 # Percentage of cache occupancy per task id
1266 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957672 # Percentage of cache occupancy per task id
1267 system.cpu.l2cache.tags.tag_accesses 417429422 # Number of tag accesses
1268 system.cpu.l2cache.tags.data_accesses 417429422 # Number of data accesses
1269 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1270 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 796619 # number of ReadReq hits
1271 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283100 # number of ReadReq hits
1272 system.cpu.l2cache.ReadReq_hits::total 1079719 # number of ReadReq hits
1273 system.cpu.l2cache.WritebackDirty_hits::writebacks 7764980 # number of WritebackDirty hits
1274 system.cpu.l2cache.WritebackDirty_hits::total 7764980 # number of WritebackDirty hits
1275 system.cpu.l2cache.WritebackClean_hits::writebacks 15302294 # number of WritebackClean hits
1276 system.cpu.l2cache.WritebackClean_hits::total 15302294 # number of WritebackClean hits
1277 system.cpu.l2cache.UpgradeReq_hits::cpu.data 25817 # number of UpgradeReq hits
1278 system.cpu.l2cache.UpgradeReq_hits::total 25817 # number of UpgradeReq hits
1279 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 6 # number of SCUpgradeReq hits
1280 system.cpu.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits
1281 system.cpu.l2cache.ReadExReq_hits::cpu.data 1591016 # number of ReadExReq hits
1282 system.cpu.l2cache.ReadExReq_hits::total 1591016 # number of ReadExReq hits
1283 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15218653 # number of ReadCleanReq hits
1284 system.cpu.l2cache.ReadCleanReq_hits::total 15218653 # number of ReadCleanReq hits
1285 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6530102 # number of ReadSharedReq hits
1286 system.cpu.l2cache.ReadSharedReq_hits::total 6530102 # number of ReadSharedReq hits
1287 system.cpu.l2cache.InvalidateReq_hits::cpu.data 728891 # number of InvalidateReq hits
1288 system.cpu.l2cache.InvalidateReq_hits::total 728891 # number of InvalidateReq hits
1289 system.cpu.l2cache.demand_hits::cpu.dtb.walker 796619 # number of demand (read+write) hits
1290 system.cpu.l2cache.demand_hits::cpu.itb.walker 283100 # number of demand (read+write) hits
1291 system.cpu.l2cache.demand_hits::cpu.inst 15218653 # number of demand (read+write) hits
1292 system.cpu.l2cache.demand_hits::cpu.data 8121118 # number of demand (read+write) hits
1293 system.cpu.l2cache.demand_hits::total 24419490 # number of demand (read+write) hits
1294 system.cpu.l2cache.overall_hits::cpu.dtb.walker 796619 # number of overall hits
1295 system.cpu.l2cache.overall_hits::cpu.itb.walker 283100 # number of overall hits
1296 system.cpu.l2cache.overall_hits::cpu.inst 15218653 # number of overall hits
1297 system.cpu.l2cache.overall_hits::cpu.data 8121118 # number of overall hits
1298 system.cpu.l2cache.overall_hits::total 24419490 # number of overall hits
1299 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3956 # number of ReadReq misses
1300 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3665 # number of ReadReq misses
1301 system.cpu.l2cache.ReadReq_misses::total 7621 # number of ReadReq misses
1302 system.cpu.l2cache.UpgradeReq_misses::cpu.data 4094 # number of UpgradeReq misses
1303 system.cpu.l2cache.UpgradeReq_misses::total 4094 # number of UpgradeReq misses
1304 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
1305 system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
1306 system.cpu.l2cache.ReadExReq_misses::cpu.data 478353 # number of ReadExReq misses
1307 system.cpu.l2cache.ReadExReq_misses::total 478353 # number of ReadExReq misses
1308 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 86839 # number of ReadCleanReq misses
1309 system.cpu.l2cache.ReadCleanReq_misses::total 86839 # number of ReadCleanReq misses
1310 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 268407 # number of ReadSharedReq misses
1311 system.cpu.l2cache.ReadSharedReq_misses::total 268407 # number of ReadSharedReq misses
1312 system.cpu.l2cache.InvalidateReq_misses::cpu.data 501154 # number of InvalidateReq misses
1313 system.cpu.l2cache.InvalidateReq_misses::total 501154 # number of InvalidateReq misses
1314 system.cpu.l2cache.demand_misses::cpu.dtb.walker 3956 # number of demand (read+write) misses
1315 system.cpu.l2cache.demand_misses::cpu.itb.walker 3665 # number of demand (read+write) misses
1316 system.cpu.l2cache.demand_misses::cpu.inst 86839 # number of demand (read+write) misses
1317 system.cpu.l2cache.demand_misses::cpu.data 746760 # number of demand (read+write) misses
1318 system.cpu.l2cache.demand_misses::total 841220 # number of demand (read+write) misses
1319 system.cpu.l2cache.overall_misses::cpu.dtb.walker 3956 # number of overall misses
1320 system.cpu.l2cache.overall_misses::cpu.itb.walker 3665 # number of overall misses
1321 system.cpu.l2cache.overall_misses::cpu.inst 86839 # number of overall misses
1322 system.cpu.l2cache.overall_misses::cpu.data 746760 # number of overall misses
1323 system.cpu.l2cache.overall_misses::total 841220 # number of overall misses
1324 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 431772500 # number of ReadReq miss cycles
1325 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 382599000 # number of ReadReq miss cycles
1326 system.cpu.l2cache.ReadReq_miss_latency::total 814371500 # number of ReadReq miss cycles
1327 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72848000 # number of UpgradeReq miss cycles
1328 system.cpu.l2cache.UpgradeReq_miss_latency::total 72848000 # number of UpgradeReq miss cycles
1329 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles
1330 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles
1331 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 49637800000 # number of ReadExReq miss cycles
1332 system.cpu.l2cache.ReadExReq_miss_latency::total 49637800000 # number of ReadExReq miss cycles
1333 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9658072000 # number of ReadCleanReq miss cycles
1334 system.cpu.l2cache.ReadCleanReq_miss_latency::total 9658072000 # number of ReadCleanReq miss cycles
1335 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30942623000 # number of ReadSharedReq miss cycles
1336 system.cpu.l2cache.ReadSharedReq_miss_latency::total 30942623000 # number of ReadSharedReq miss cycles
1337 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 431772500 # number of demand (read+write) miss cycles
1338 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 382599000 # number of demand (read+write) miss cycles
1339 system.cpu.l2cache.demand_miss_latency::cpu.inst 9658072000 # number of demand (read+write) miss cycles
1340 system.cpu.l2cache.demand_miss_latency::cpu.data 80580423000 # number of demand (read+write) miss cycles
1341 system.cpu.l2cache.demand_miss_latency::total 91052866500 # number of demand (read+write) miss cycles
1342 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 431772500 # number of overall miss cycles
1343 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 382599000 # number of overall miss cycles
1344 system.cpu.l2cache.overall_miss_latency::cpu.inst 9658072000 # number of overall miss cycles
1345 system.cpu.l2cache.overall_miss_latency::cpu.data 80580423000 # number of overall miss cycles
1346 system.cpu.l2cache.overall_miss_latency::total 91052866500 # number of overall miss cycles
1347 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 800575 # number of ReadReq accesses(hits+misses)
1348 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286765 # number of ReadReq accesses(hits+misses)
1349 system.cpu.l2cache.ReadReq_accesses::total 1087340 # number of ReadReq accesses(hits+misses)
1350 system.cpu.l2cache.WritebackDirty_accesses::writebacks 7764980 # number of WritebackDirty accesses(hits+misses)
1351 system.cpu.l2cache.WritebackDirty_accesses::total 7764980 # number of WritebackDirty accesses(hits+misses)
1352 system.cpu.l2cache.WritebackClean_accesses::writebacks 15302294 # number of WritebackClean accesses(hits+misses)
1353 system.cpu.l2cache.WritebackClean_accesses::total 15302294 # number of WritebackClean accesses(hits+misses)
1354 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29911 # number of UpgradeReq accesses(hits+misses)
1355 system.cpu.l2cache.UpgradeReq_accesses::total 29911 # number of UpgradeReq accesses(hits+misses)
1356 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses)
1357 system.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses)
1358 system.cpu.l2cache.ReadExReq_accesses::cpu.data 2069369 # number of ReadExReq accesses(hits+misses)
1359 system.cpu.l2cache.ReadExReq_accesses::total 2069369 # number of ReadExReq accesses(hits+misses)
1360 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15305492 # number of ReadCleanReq accesses(hits+misses)
1361 system.cpu.l2cache.ReadCleanReq_accesses::total 15305492 # number of ReadCleanReq accesses(hits+misses)
1362 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6798509 # number of ReadSharedReq accesses(hits+misses)
1363 system.cpu.l2cache.ReadSharedReq_accesses::total 6798509 # number of ReadSharedReq accesses(hits+misses)
1364 system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1230045 # number of InvalidateReq accesses(hits+misses)
1365 system.cpu.l2cache.InvalidateReq_accesses::total 1230045 # number of InvalidateReq accesses(hits+misses)
1366 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 800575 # number of demand (read+write) accesses
1367 system.cpu.l2cache.demand_accesses::cpu.itb.walker 286765 # number of demand (read+write) accesses
1368 system.cpu.l2cache.demand_accesses::cpu.inst 15305492 # number of demand (read+write) accesses
1369 system.cpu.l2cache.demand_accesses::cpu.data 8867878 # number of demand (read+write) accesses
1370 system.cpu.l2cache.demand_accesses::total 25260710 # number of demand (read+write) accesses
1371 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 800575 # number of overall (read+write) accesses
1372 system.cpu.l2cache.overall_accesses::cpu.itb.walker 286765 # number of overall (read+write) accesses
1373 system.cpu.l2cache.overall_accesses::cpu.inst 15305492 # number of overall (read+write) accesses
1374 system.cpu.l2cache.overall_accesses::cpu.data 8867878 # number of overall (read+write) accesses
1375 system.cpu.l2cache.overall_accesses::total 25260710 # number of overall (read+write) accesses
1376 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004941 # miss rate for ReadReq accesses
1377 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.012780 # miss rate for ReadReq accesses
1378 system.cpu.l2cache.ReadReq_miss_rate::total 0.007009 # miss rate for ReadReq accesses
1379 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.136873 # miss rate for UpgradeReq accesses
1380 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.136873 # miss rate for UpgradeReq accesses
1381 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses
1382 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses
1383 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231159 # miss rate for ReadExReq accesses
1384 system.cpu.l2cache.ReadExReq_miss_rate::total 0.231159 # miss rate for ReadExReq accesses
1385 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005674 # miss rate for ReadCleanReq accesses
1386 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005674 # miss rate for ReadCleanReq accesses
1387 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039480 # miss rate for ReadSharedReq accesses
1388 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039480 # miss rate for ReadSharedReq accesses
1389 system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.407427 # miss rate for InvalidateReq accesses
1390 system.cpu.l2cache.InvalidateReq_miss_rate::total 0.407427 # miss rate for InvalidateReq accesses
1391 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004941 # miss rate for demand accesses
1392 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.012780 # miss rate for demand accesses
1393 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005674 # miss rate for demand accesses
1394 system.cpu.l2cache.demand_miss_rate::cpu.data 0.084210 # miss rate for demand accesses
1395 system.cpu.l2cache.demand_miss_rate::total 0.033302 # miss rate for demand accesses
1396 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004941 # miss rate for overall accesses
1397 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.012780 # miss rate for overall accesses
1398 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005674 # miss rate for overall accesses
1399 system.cpu.l2cache.overall_miss_rate::cpu.data 0.084210 # miss rate for overall accesses
1400 system.cpu.l2cache.overall_miss_rate::total 0.033302 # miss rate for overall accesses
1401 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 109143.705763 # average ReadReq miss latency
1402 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 104392.633015 # average ReadReq miss latency
1403 system.cpu.l2cache.ReadReq_avg_miss_latency::total 106858.876788 # average ReadReq miss latency
1404 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17793.844651 # average UpgradeReq miss latency
1405 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17793.844651 # average UpgradeReq miss latency
1406 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54166.666667 # average SCUpgradeReq miss latency
1407 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54166.666667 # average SCUpgradeReq miss latency
1408 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103768.137756 # average ReadExReq miss latency
1409 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103768.137756 # average ReadExReq miss latency
1410 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111218.139315 # average ReadCleanReq miss latency
1411 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111218.139315 # average ReadCleanReq miss latency
1412 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115282.474004 # average ReadSharedReq miss latency
1413 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115282.474004 # average ReadSharedReq miss latency
1414 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 109143.705763 # average overall miss latency
1415 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 104392.633015 # average overall miss latency
1416 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111218.139315 # average overall miss latency
1417 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 107906.721035 # average overall miss latency
1418 system.cpu.l2cache.demand_avg_miss_latency::total 108239.065286 # average overall miss latency
1419 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 109143.705763 # average overall miss latency
1420 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 104392.633015 # average overall miss latency
1421 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111218.139315 # average overall miss latency
1422 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 107906.721035 # average overall miss latency
1423 system.cpu.l2cache.overall_avg_miss_latency::total 108239.065286 # average overall miss latency
1424 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1425 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1426 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1427 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1428 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1429 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1430 system.cpu.l2cache.writebacks::writebacks 1059086 # number of writebacks
1431 system.cpu.l2cache.writebacks::total 1059086 # number of writebacks
1432 system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits
1433 system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1434 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
1435 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
1436 system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits
1437 system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
1438 system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
1439 system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits
1440 system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
1441 system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
1442 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3956 # number of ReadReq MSHR misses
1443 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3664 # number of ReadReq MSHR misses
1444 system.cpu.l2cache.ReadReq_mshr_misses::total 7620 # number of ReadReq MSHR misses
1445 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
1446 system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
1447 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4094 # number of UpgradeReq MSHR misses
1448 system.cpu.l2cache.UpgradeReq_mshr_misses::total 4094 # number of UpgradeReq MSHR misses
1449 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
1450 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
1451 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 478353 # number of ReadExReq MSHR misses
1452 system.cpu.l2cache.ReadExReq_mshr_misses::total 478353 # number of ReadExReq MSHR misses
1453 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 86839 # number of ReadCleanReq MSHR misses
1454 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 86839 # number of ReadCleanReq MSHR misses
1455 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 268386 # number of ReadSharedReq MSHR misses
1456 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 268386 # number of ReadSharedReq MSHR misses
1457 system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 501154 # number of InvalidateReq MSHR misses
1458 system.cpu.l2cache.InvalidateReq_mshr_misses::total 501154 # number of InvalidateReq MSHR misses
1459 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3956 # number of demand (read+write) MSHR misses
1460 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3664 # number of demand (read+write) MSHR misses
1461 system.cpu.l2cache.demand_mshr_misses::cpu.inst 86839 # number of demand (read+write) MSHR misses
1462 system.cpu.l2cache.demand_mshr_misses::cpu.data 746739 # number of demand (read+write) MSHR misses
1463 system.cpu.l2cache.demand_mshr_misses::total 841198 # number of demand (read+write) MSHR misses
1464 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3956 # number of overall MSHR misses
1465 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3664 # number of overall MSHR misses
1466 system.cpu.l2cache.overall_mshr_misses::cpu.inst 86839 # number of overall MSHR misses
1467 system.cpu.l2cache.overall_mshr_misses::cpu.data 746739 # number of overall MSHR misses
1468 system.cpu.l2cache.overall_mshr_misses::total 841198 # number of overall MSHR misses
1469 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable
1470 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable
1471 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 35684 # number of ReadReq MSHR uncacheable
1472 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable
1473 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable
1474 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses
1475 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses
1476 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 69293 # number of overall MSHR uncacheable misses
1477 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 392212500 # number of ReadReq MSHR miss cycles
1478 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 345880000 # number of ReadReq MSHR miss cycles
1479 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 738092500 # number of ReadReq MSHR miss cycles
1480 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 78102500 # number of UpgradeReq MSHR miss cycles
1481 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 78102500 # number of UpgradeReq MSHR miss cycles
1482 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles
1483 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles
1484 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44854250540 # number of ReadExReq MSHR miss cycles
1485 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44854250540 # number of ReadExReq MSHR miss cycles
1486 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8789667055 # number of ReadCleanReq MSHR miss cycles
1487 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8789667055 # number of ReadCleanReq MSHR miss cycles
1488 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28257377566 # number of ReadSharedReq MSHR miss cycles
1489 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28257377566 # number of ReadSharedReq MSHR miss cycles
1490 system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 10480376502 # number of InvalidateReq MSHR miss cycles
1491 system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 10480376502 # number of InvalidateReq MSHR miss cycles
1492 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 392212500 # number of demand (read+write) MSHR miss cycles
1493 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 345880000 # number of demand (read+write) MSHR miss cycles
1494 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8789667055 # number of demand (read+write) MSHR miss cycles
1495 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73111628106 # number of demand (read+write) MSHR miss cycles
1496 system.cpu.l2cache.demand_mshr_miss_latency::total 82639387661 # number of demand (read+write) MSHR miss cycles
1497 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 392212500 # number of overall MSHR miss cycles
1498 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 345880000 # number of overall MSHR miss cycles
1499 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8789667055 # number of overall MSHR miss cycles
1500 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73111628106 # number of overall MSHR miss cycles
1501 system.cpu.l2cache.overall_mshr_miss_latency::total 82639387661 # number of overall MSHR miss cycles
1502 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 147896500 # number of ReadReq MSHR uncacheable cycles
1503 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5784421000 # number of ReadReq MSHR uncacheable cycles
1504 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5932317500 # number of ReadReq MSHR uncacheable cycles
1505 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 147896500 # number of overall MSHR uncacheable cycles
1506 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5784421000 # number of overall MSHR uncacheable cycles
1507 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 5932317500 # number of overall MSHR uncacheable cycles
1508 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for ReadReq accesses
1509 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for ReadReq accesses
1510 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007008 # mshr miss rate for ReadReq accesses
1511 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1512 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1513 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136873 # mshr miss rate for UpgradeReq accesses
1514 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136873 # mshr miss rate for UpgradeReq accesses
1515 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
1516 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses
1517 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231159 # mshr miss rate for ReadExReq accesses
1518 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231159 # mshr miss rate for ReadExReq accesses
1519 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for ReadCleanReq accesses
1520 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005674 # mshr miss rate for ReadCleanReq accesses
1521 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039477 # mshr miss rate for ReadSharedReq accesses
1522 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039477 # mshr miss rate for ReadSharedReq accesses
1523 system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407427 # mshr miss rate for InvalidateReq accesses
1524 system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407427 # mshr miss rate for InvalidateReq accesses
1525 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for demand accesses
1526 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for demand accesses
1527 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for demand accesses
1528 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for demand accesses
1529 system.cpu.l2cache.demand_mshr_miss_rate::total 0.033301 # mshr miss rate for demand accesses
1530 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for overall accesses
1531 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for overall accesses
1532 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for overall accesses
1533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for overall accesses
1534 system.cpu.l2cache.overall_mshr_miss_rate::total 0.033301 # mshr miss rate for overall accesses
1535 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average ReadReq mshr miss latency
1536 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average ReadReq mshr miss latency
1537 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 96862.532808 # average ReadReq mshr miss latency
1538 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19077.308256 # average UpgradeReq mshr miss latency
1539 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19077.308256 # average UpgradeReq mshr miss latency
1540 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency
1541 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency
1542 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93768.097075 # average ReadExReq mshr miss latency
1543 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93768.097075 # average ReadExReq mshr miss latency
1544 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101217.967215 # average ReadCleanReq mshr miss latency
1545 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101217.967215 # average ReadCleanReq mshr miss latency
1546 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105286.332245 # average ReadSharedReq mshr miss latency
1547 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105286.332245 # average ReadSharedReq mshr miss latency
1548 system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20912.486984 # average InvalidateReq mshr miss latency
1549 system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20912.486984 # average InvalidateReq mshr miss latency
1550 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency
1551 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency
1552 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency
1553 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency
1554 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency
1555 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency
1556 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency
1557 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency
1558 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency
1559 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency
1560 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average ReadReq mshr uncacheable latency
1561 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172206.638881 # average ReadReq mshr uncacheable latency
1562 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166245.866495 # average ReadReq mshr uncacheable latency
1563 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average overall mshr uncacheable latency
1564 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86078.974389 # average overall mshr uncacheable latency
1565 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85612.074813 # average overall mshr uncacheable latency
1566 system.cpu.toL2Bus.snoop_filter.tot_requests 51553426 # Total number of requests made to the snoop filter.
1567 system.cpu.toL2Bus.snoop_filter.hit_single_requests 26149596 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1568 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7713 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1569 system.cpu.toL2Bus.snoop_filter.tot_snoops 1993 # Total number of snoops made to the snoop filter.
1570 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1993 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1571 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1572 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1573 system.cpu.toL2Bus.trans_dist::ReadReq 1662998 # Transaction distribution
1574 system.cpu.toL2Bus.trans_dist::ReadResp 23767979 # Transaction distribution
1575 system.cpu.toL2Bus.trans_dist::WriteReq 33609 # Transaction distribution
1576 system.cpu.toL2Bus.trans_dist::WriteResp 33609 # Transaction distribution
1577 system.cpu.toL2Bus.trans_dist::WritebackDirty 8824066 # Transaction distribution
1578 system.cpu.toL2Bus.trans_dist::WritebackClean 15304958 # Transaction distribution
1579 system.cpu.toL2Bus.trans_dist::CleanEvict 2522010 # Transaction distribution
1580 system.cpu.toL2Bus.trans_dist::UpgradeReq 29914 # Transaction distribution
1581 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
1582 system.cpu.toL2Bus.trans_dist::UpgradeResp 29923 # Transaction distribution
1583 system.cpu.toL2Bus.trans_dist::ReadExReq 2069369 # Transaction distribution
1584 system.cpu.toL2Bus.trans_dist::ReadExResp 2069369 # Transaction distribution
1585 system.cpu.toL2Bus.trans_dist::ReadCleanReq 15305703 # Transaction distribution
1586 system.cpu.toL2Bus.trans_dist::ReadSharedReq 6801111 # Transaction distribution
1587 system.cpu.toL2Bus.trans_dist::InvalidateReq 1260813 # Transaction distribution
1588 system.cpu.toL2Bus.trans_dist::InvalidateResp 1230062 # Transaction distribution
1589 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45920340 # Packet count per connected master and slave (bytes)
1590 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30488261 # Packet count per connected master and slave (bytes)
1591 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 721887 # Packet count per connected master and slave (bytes)
1592 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1992767 # Packet count per connected master and slave (bytes)
1593 system.cpu.toL2Bus.pkt_count::total 79123255 # Packet count per connected master and slave (bytes)
1594 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959102240 # Cumulative packet size per connected master and slave (bytes)
1595 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1064742138 # Cumulative packet size per connected master and slave (bytes)
1596 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2294120 # Cumulative packet size per connected master and slave (bytes)
1597 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6404600 # Cumulative packet size per connected master and slave (bytes)
1598 system.cpu.toL2Bus.pkt_size::total 3032543098 # Cumulative packet size per connected master and slave (bytes)
1599 system.cpu.toL2Bus.snoops 1823037 # Total snoops (count)
1600 system.cpu.toL2Bus.snoopTraffic 72164080 # Total snoop traffic (bytes)
1601 system.cpu.toL2Bus.snoop_fanout::samples 28412224 # Request fanout histogram
1602 system.cpu.toL2Bus.snoop_fanout::mean 0.025596 # Request fanout histogram
1603 system.cpu.toL2Bus.snoop_fanout::stdev 0.157926 # Request fanout histogram
1604 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1605 system.cpu.toL2Bus.snoop_fanout::0 27684996 97.44% 97.44% # Request fanout histogram
1606 system.cpu.toL2Bus.snoop_fanout::1 727226 2.56% 100.00% # Request fanout histogram
1607 system.cpu.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram
1608 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1609 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1610 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1611 system.cpu.toL2Bus.snoop_fanout::total 28412224 # Request fanout histogram
1612 system.cpu.toL2Bus.reqLayer0.occupancy 49353009980 # Layer occupancy (ticks)
1613 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1614 system.cpu.toL2Bus.snoopLayer0.occupancy 1469889 # Layer occupancy (ticks)
1615 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1616 system.cpu.toL2Bus.respLayer0.occupancy 22969214259 # Layer occupancy (ticks)
1617 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1618 system.cpu.toL2Bus.respLayer1.occupancy 13985386089 # Layer occupancy (ticks)
1619 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1620 system.cpu.toL2Bus.respLayer2.occupancy 435462274 # Layer occupancy (ticks)
1621 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1622 system.cpu.toL2Bus.respLayer3.occupancy 1192643074 # Layer occupancy (ticks)
1623 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1624 system.iobus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1625 system.iobus.trans_dist::ReadReq 40205 # Transaction distribution
1626 system.iobus.trans_dist::ReadResp 40205 # Transaction distribution
1627 system.iobus.trans_dist::WriteReq 136485 # Transaction distribution
1628 system.iobus.trans_dist::WriteResp 136485 # Transaction distribution
1629 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes)
1630 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1631 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1632 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1633 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1634 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1635 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1636 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1637 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1638 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1639 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1640 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1641 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1642 system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes)
1643 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes)
1644 system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes)
1645 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1646 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1647 system.iobus.pkt_count::total 353380 # Packet count per connected master and slave (bytes)
1648 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes)
1649 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1650 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
1651 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1652 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1653 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1654 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1655 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1656 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1657 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1658 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1659 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1660 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1661 system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes)
1662 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes)
1663 system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes)
1664 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1665 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1666 system.iobus.pkt_size::total 7491768 # Cumulative packet size per connected master and slave (bytes)
1667 system.iobus.reqLayer0.occupancy 41589500 # Layer occupancy (ticks)
1668 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1669 system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
1670 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1671 system.iobus.reqLayer2.occupancy 341500 # Layer occupancy (ticks)
1672 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1673 system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
1674 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1675 system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
1676 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1677 system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
1678 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1679 system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
1680 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1681 system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
1682 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1683 system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
1684 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1685 system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
1686 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1687 system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
1688 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1689 system.iobus.reqLayer23.occupancy 25178000 # Layer occupancy (ticks)
1690 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1691 system.iobus.reqLayer24.occupancy 36502000 # Layer occupancy (ticks)
1692 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1693 system.iobus.reqLayer25.occupancy 568968268 # Layer occupancy (ticks)
1694 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1695 system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks)
1696 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1697 system.iobus.respLayer3.occupancy 147700000 # Layer occupancy (ticks)
1698 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1699 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1700 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1701 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1702 system.iocache.tags.replacements 115451 # number of replacements
1703 system.iocache.tags.tagsinuse 10.420620 # Cycle average of tags in use
1704 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1705 system.iocache.tags.sampled_refs 115467 # Sample count of references to valid blocks.
1706 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1707 system.iocache.tags.warmup_cycle 13090295539000 # Cycle when the warmup percentage was hit.
1708 system.iocache.tags.occ_blocks::realview.ethernet 3.547144 # Average occupied blocks per requestor
1709 system.iocache.tags.occ_blocks::realview.ide 6.873475 # Average occupied blocks per requestor
1710 system.iocache.tags.occ_percent::realview.ethernet 0.221697 # Average percentage of cache occupancy
1711 system.iocache.tags.occ_percent::realview.ide 0.429592 # Average percentage of cache occupancy
1712 system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy
1713 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1714 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1715 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1716 system.iocache.tags.tag_accesses 1039587 # Number of tag accesses
1717 system.iocache.tags.data_accesses 1039587 # Number of data accesses
1718 system.iocache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1719 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1720 system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses
1721 system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses
1722 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1723 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1724 system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1725 system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1726 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1727 system.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses
1728 system.iocache.demand_misses::total 115510 # number of demand (read+write) misses
1729 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1730 system.iocache.overall_misses::realview.ide 115470 # number of overall misses
1731 system.iocache.overall_misses::total 115510 # number of overall misses
1732 system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
1733 system.iocache.ReadReq_miss_latency::realview.ide 1876442585 # number of ReadReq miss cycles
1734 system.iocache.ReadReq_miss_latency::total 1881528585 # number of ReadReq miss cycles
1735 system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
1736 system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
1737 system.iocache.WriteLineReq_miss_latency::realview.ide 13387619683 # number of WriteLineReq miss cycles
1738 system.iocache.WriteLineReq_miss_latency::total 13387619683 # number of WriteLineReq miss cycles
1739 system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
1740 system.iocache.demand_miss_latency::realview.ide 15264062268 # number of demand (read+write) miss cycles
1741 system.iocache.demand_miss_latency::total 15269499268 # number of demand (read+write) miss cycles
1742 system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
1743 system.iocache.overall_miss_latency::realview.ide 15264062268 # number of overall miss cycles
1744 system.iocache.overall_miss_latency::total 15269499268 # number of overall miss cycles
1745 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1746 system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses)
1747 system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses)
1748 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1749 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1750 system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
1751 system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
1752 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1753 system.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses
1754 system.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses
1755 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1756 system.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses
1757 system.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses
1758 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1759 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1760 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1761 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1762 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1763 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1764 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1765 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1766 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1767 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1768 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1769 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1770 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1771 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
1772 system.iocache.ReadReq_avg_miss_latency::realview.ide 213086.825460 # average ReadReq miss latency
1773 system.iocache.ReadReq_avg_miss_latency::total 212770.392966 # average ReadReq miss latency
1774 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
1775 system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
1776 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125512.072330 # average WriteLineReq miss latency
1777 system.iocache.WriteLineReq_avg_miss_latency::total 125512.072330 # average WriteLineReq miss latency
1778 system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
1779 system.iocache.demand_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency
1780 system.iocache.demand_avg_miss_latency::total 132192.011670 # average overall miss latency
1781 system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
1782 system.iocache.overall_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency
1783 system.iocache.overall_avg_miss_latency::total 132192.011670 # average overall miss latency
1784 system.iocache.blocked_cycles::no_mshrs 45104 # number of cycles access was blocked
1785 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1786 system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked
1787 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1788 system.iocache.avg_blocked_cycles::no_mshrs 13.176746 # average number of cycles each access was blocked
1789 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1790 system.iocache.writebacks::writebacks 106630 # number of writebacks
1791 system.iocache.writebacks::total 106630 # number of writebacks
1792 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1793 system.iocache.ReadReq_mshr_misses::realview.ide 8806 # number of ReadReq MSHR misses
1794 system.iocache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses
1795 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1796 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1797 system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
1798 system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
1799 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1800 system.iocache.demand_mshr_misses::realview.ide 115470 # number of demand (read+write) MSHR misses
1801 system.iocache.demand_mshr_misses::total 115510 # number of demand (read+write) MSHR misses
1802 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1803 system.iocache.overall_mshr_misses::realview.ide 115470 # number of overall MSHR misses
1804 system.iocache.overall_mshr_misses::total 115510 # number of overall MSHR misses
1805 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
1806 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1436142585 # number of ReadReq MSHR miss cycles
1807 system.iocache.ReadReq_mshr_miss_latency::total 1439378585 # number of ReadReq MSHR miss cycles
1808 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
1809 system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
1810 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8048941203 # number of WriteLineReq MSHR miss cycles
1811 system.iocache.WriteLineReq_mshr_miss_latency::total 8048941203 # number of WriteLineReq MSHR miss cycles
1812 system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
1813 system.iocache.demand_mshr_miss_latency::realview.ide 9485083788 # number of demand (read+write) MSHR miss cycles
1814 system.iocache.demand_mshr_miss_latency::total 9488520788 # number of demand (read+write) MSHR miss cycles
1815 system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
1816 system.iocache.overall_mshr_miss_latency::realview.ide 9485083788 # number of overall MSHR miss cycles
1817 system.iocache.overall_mshr_miss_latency::total 9488520788 # number of overall MSHR miss cycles
1818 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1819 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1820 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1821 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1822 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1823 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1824 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1825 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1826 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1827 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1828 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1829 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1830 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1831 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
1832 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163086.825460 # average ReadReq mshr miss latency
1833 system.iocache.ReadReq_avg_mshr_miss_latency::total 162770.392966 # average ReadReq mshr miss latency
1834 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
1835 system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
1836 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75460.710296 # average WriteLineReq mshr miss latency
1837 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75460.710296 # average WriteLineReq mshr miss latency
1838 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
1839 system.iocache.demand_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency
1840 system.iocache.demand_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency
1841 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
1842 system.iocache.overall_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency
1843 system.iocache.overall_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency
1844 system.membus.snoop_filter.tot_requests 2825507 # Total number of requests made to the snoop filter.
1845 system.membus.snoop_filter.hit_single_requests 1398744 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1846 system.membus.snoop_filter.hit_multi_requests 3574 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1847 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1848 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1849 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1850 system.membus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1851 system.membus.trans_dist::ReadReq 35684 # Transaction distribution
1852 system.membus.trans_dist::ReadResp 407371 # Transaction distribution
1853 system.membus.trans_dist::WriteReq 33609 # Transaction distribution
1854 system.membus.trans_dist::WriteResp 33609 # Transaction distribution
1855 system.membus.trans_dist::WritebackDirty 1165716 # Transaction distribution
1856 system.membus.trans_dist::CleanEvict 197310 # Transaction distribution
1857 system.membus.trans_dist::UpgradeReq 4655 # Transaction distribution
1858 system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
1859 system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
1860 system.membus.trans_dist::ReadExReq 477795 # Transaction distribution
1861 system.membus.trans_dist::ReadExResp 477795 # Transaction distribution
1862 system.membus.trans_dist::ReadSharedReq 371688 # Transaction distribution
1863 system.membus.trans_dist::InvalidateReq 607818 # Transaction distribution
1864 system.membus.trans_dist::InvalidateResp 30461 # Transaction distribution
1865 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes)
1866 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
1867 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes)
1868 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3443320 # Packet count per connected master and slave (bytes)
1869 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3572590 # Packet count per connected master and slave (bytes)
1870 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237411 # Packet count per connected master and slave (bytes)
1871 system.membus.pkt_count_system.iocache.mem_side::total 237411 # Packet count per connected master and slave (bytes)
1872 system.membus.pkt_count::total 3810001 # Packet count per connected master and slave (bytes)
1873 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes)
1874 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
1875 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes)
1876 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 121594060 # Cumulative packet size per connected master and slave (bytes)
1877 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 121763674 # Cumulative packet size per connected master and slave (bytes)
1878 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237120 # Cumulative packet size per connected master and slave (bytes)
1879 system.membus.pkt_size_system.iocache.mem_side::total 7237120 # Cumulative packet size per connected master and slave (bytes)
1880 system.membus.pkt_size::total 129000794 # Cumulative packet size per connected master and slave (bytes)
1881 system.membus.snoops 33521 # Total snoops (count)
1882 system.membus.snoopTraffic 195328 # Total snoop traffic (bytes)
1883 system.membus.snoop_fanout::samples 1531252 # Request fanout histogram
1884 system.membus.snoop_fanout::mean 0.022242 # Request fanout histogram
1885 system.membus.snoop_fanout::stdev 0.147469 # Request fanout histogram
1886 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1887 system.membus.snoop_fanout::0 1497194 97.78% 97.78% # Request fanout histogram
1888 system.membus.snoop_fanout::1 34058 2.22% 100.00% # Request fanout histogram
1889 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1890 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1891 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1892 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1893 system.membus.snoop_fanout::total 1531252 # Request fanout histogram
1894 system.membus.reqLayer0.occupancy 103704000 # Layer occupancy (ticks)
1895 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1896 system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
1897 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1898 system.membus.reqLayer2.occupancy 5582500 # Layer occupancy (ticks)
1899 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1900 system.membus.reqLayer5.occupancy 7711716413 # Layer occupancy (ticks)
1901 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1902 system.membus.respLayer2.occupancy 4552014688 # Layer occupancy (ticks)
1903 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1904 system.membus.respLayer3.occupancy 76660254 # Layer occupancy (ticks)
1905 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1906 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1907 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1908 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1909 system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1910 system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1911 system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1912 system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1913 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1914 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1915 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1916 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1917 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1918 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1919 system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1920 system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1921 system.realview.ethernet.txBytes 966 # Bytes Transmitted
1922 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1923 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1924 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1925 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1926 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1927 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1928 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1929 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1930 system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
1931 system.realview.ethernet.totPackets 3 # Total Packets
1932 system.realview.ethernet.totBytes 966 # Total Bytes
1933 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
1934 system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
1935 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
1936 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1937 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
1938 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1939 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1940 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
1941 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1942 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1943 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
1944 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1945 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1946 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
1947 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1948 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1949 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
1950 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1951 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1952 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
1953 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1954 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1955 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1956 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1957 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1958 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1959 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1960 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1961 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1962 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1963 system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1964 system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1965 system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1966 system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1967 system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1968 system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1969 system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1970 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1971 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1972 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1973 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1974 system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1975 system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1976 system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1977 system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1978 system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1979 system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1980 system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1981 system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1982 system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1983 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1984 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1985 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states
1986 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1987 system.cpu.kern.inst.quiesce 16273 # number of quiesce instructions executed
1989 ---------- End Simulation Statistics ----------
projects / gem5.git / blob