2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 51.558015 # Number of seconds simulated
4 sim_ticks 51558014828000 # Number of ticks simulated
5 final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 133865 # Simulator instruction rate (inst/s)
8 host_op_rate 157345 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 6235119796 # Simulator tick rate (ticks/s)
10 host_mem_usage 696436 # Number of bytes of host memory used
11 host_seconds 8268.97 # Real time elapsed on the host
12 sim_insts 1106923026 # Number of instructions simulated
13 sim_ops 1301083589 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory
21 system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory
22 system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory
23 system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory
24 system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory
25 system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory
26 system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
27 system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory
28 system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory
32 system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory
33 system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory
34 system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory
35 system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
36 system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory
37 system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s)
48 system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s)
55 system.physmem.readReqs 1904301 # Number of read requests accepted
56 system.physmem.writeReqs 2205028 # Number of write requests accepted
57 system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue
58 system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue
59 system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM
60 system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue
61 system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM
62 system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side
63 system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side
64 system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue
65 system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
66 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67 system.physmem.perBankRdBursts::0 114327 # Per bank write bursts
68 system.physmem.perBankRdBursts::1 123692 # Per bank write bursts
69 system.physmem.perBankRdBursts::2 118245 # Per bank write bursts
70 system.physmem.perBankRdBursts::3 117057 # Per bank write bursts
71 system.physmem.perBankRdBursts::4 115229 # Per bank write bursts
72 system.physmem.perBankRdBursts::5 125268 # Per bank write bursts
73 system.physmem.perBankRdBursts::6 115683 # Per bank write bursts
74 system.physmem.perBankRdBursts::7 119593 # Per bank write bursts
75 system.physmem.perBankRdBursts::8 115543 # Per bank write bursts
76 system.physmem.perBankRdBursts::9 144676 # Per bank write bursts
77 system.physmem.perBankRdBursts::10 112600 # Per bank write bursts
78 system.physmem.perBankRdBursts::11 120122 # Per bank write bursts
79 system.physmem.perBankRdBursts::12 113965 # Per bank write bursts
80 system.physmem.perBankRdBursts::13 118266 # Per bank write bursts
81 system.physmem.perBankRdBursts::14 113146 # Per bank write bursts
82 system.physmem.perBankRdBursts::15 116309 # Per bank write bursts
83 system.physmem.perBankWrBursts::0 135142 # Per bank write bursts
84 system.physmem.perBankWrBursts::1 141643 # Per bank write bursts
85 system.physmem.perBankWrBursts::2 136917 # Per bank write bursts
86 system.physmem.perBankWrBursts::3 137997 # Per bank write bursts
87 system.physmem.perBankWrBursts::4 135684 # Per bank write bursts
88 system.physmem.perBankWrBursts::5 143871 # Per bank write bursts
89 system.physmem.perBankWrBursts::6 135153 # Per bank write bursts
90 system.physmem.perBankWrBursts::7 138864 # Per bank write bursts
91 system.physmem.perBankWrBursts::8 135935 # Per bank write bursts
92 system.physmem.perBankWrBursts::9 142790 # Per bank write bursts
93 system.physmem.perBankWrBursts::10 134947 # Per bank write bursts
94 system.physmem.perBankWrBursts::11 140191 # Per bank write bursts
95 system.physmem.perBankWrBursts::12 134987 # Per bank write bursts
96 system.physmem.perBankWrBursts::13 137976 # Per bank write bursts
97 system.physmem.perBankWrBursts::14 134592 # Per bank write bursts
98 system.physmem.perBankWrBursts::15 136075 # Per bank write bursts
99 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
100 system.physmem.numWrRetry 125 # Number of times write queue was full causing retry
101 system.physmem.totGap 51558013451500 # Total gap between requests
102 system.physmem.readPktSize::0 0 # Read request sizes (log2)
103 system.physmem.readPktSize::1 0 # Read request sizes (log2)
104 system.physmem.readPktSize::2 0 # Read request sizes (log2)
105 system.physmem.readPktSize::3 13 # Read request sizes (log2)
106 system.physmem.readPktSize::4 21272 # Read request sizes (log2)
107 system.physmem.readPktSize::5 0 # Read request sizes (log2)
108 system.physmem.readPktSize::6 1883016 # Read request sizes (log2)
109 system.physmem.writePktSize::0 0 # Write request sizes (log2)
110 system.physmem.writePktSize::1 0 # Write request sizes (log2)
111 system.physmem.writePktSize::2 1 # Write request sizes (log2)
112 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
113 system.physmem.writePktSize::4 0 # Write request sizes (log2)
114 system.physmem.writePktSize::5 0 # Write request sizes (log2)
115 system.physmem.writePktSize::6 2202455 # Write request sizes (log2)
116 system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
148 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see
212 system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation
226 system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes
231 system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
232 system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
233 system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes
234 system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads
276 system.physmem.totQLat 42075497859 # Total ticks spent queuing
277 system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM
278 system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers
279 system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst
280 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
281 system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst
282 system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s
283 system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s
284 system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s
285 system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s
286 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
287 system.physmem.busUtil 0.04 # Data bus utilization in percentage
288 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
289 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
290 system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
291 system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing
292 system.physmem.readRowHits 1533744 # Number of row buffer hits during reads
293 system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes
294 system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads
295 system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes
296 system.physmem.avgGap 12546577.18 # Average gap between requests
297 system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined
298 system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ)
299 system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ)
300 system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ)
301 system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ)
302 system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ)
303 system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ)
304 system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ)
305 system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ)
306 system.physmem_0.averagePower 668.831109 # Core power per rank (mW)
307 system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states
308 system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states
309 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
310 system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states
311 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
312 system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ)
313 system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ)
314 system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ)
315 system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ)
316 system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ)
317 system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ)
318 system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ)
319 system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ)
320 system.physmem_1.averagePower 668.833118 # Core power per rank (mW)
321 system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states
322 system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states
323 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
324 system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states
325 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
326 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
327 system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
328 system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
329 system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
330 system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
331 system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
332 system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
333 system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
334 system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
335 system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
336 system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
337 system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
338 system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
339 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
340 system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
341 system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
342 system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
343 system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
344 system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
345 system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
346 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
347 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
348 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
349 system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
350 system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
351 system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
352 system.cpu.branchPred.lookups 290131106 # Number of BP lookups
353 system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted
354 system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect
355 system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups
356 system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits
357 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
358 system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage
359 system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target.
360 system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions.
361 system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups.
362 system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits.
363 system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses.
364 system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches.
365 system.cpu_clk_domain.clock 500 # Clock period in ticks
366 system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
367 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
368 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
369 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
370 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
371 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
372 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
373 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
374 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
375 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
376 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
377 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
378 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
379 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
380 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
381 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
382 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
383 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
384 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
385 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
386 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
387 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
388 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
389 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
390 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
391 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
392 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
393 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
394 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
395 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
396 system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
397 system.cpu.dtb.walker.walks 1423094 # Table walker walks requested
398 system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors
399 system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate
400 system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate
401 system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting
402 system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency
403 system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency
404 system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency
405 system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency
406 system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency
407 system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency
408 system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency
409 system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency
410 system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency
411 system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency
412 system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
413 system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
414 system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
415 system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency
416 system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency
417 system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency
418 system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency
419 system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency
420 system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency
421 system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency
422 system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency
423 system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency
424 system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency
425 system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency
426 system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency
427 system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
428 system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
429 system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
430 system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency
431 system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution
432 system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution
433 system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution
434 system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution
435 system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution
436 system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution
437 system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution
438 system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution
439 system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution
440 system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution
441 system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution
442 system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution
443 system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution
444 system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution
445 system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution
446 system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated
447 system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated
448 system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated
449 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst
450 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
451 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst
452 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst
453 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
454 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst
455 system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst
456 system.cpu.dtb.inst_hits 0 # ITB inst hits
457 system.cpu.dtb.inst_misses 0 # ITB inst misses
458 system.cpu.dtb.read_hits 217549636 # DTB read hits
459 system.cpu.dtb.read_misses 1002675 # DTB read misses
460 system.cpu.dtb.write_hits 192429615 # DTB write hits
461 system.cpu.dtb.write_misses 420419 # DTB write misses
462 system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
463 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
464 system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID
465 system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
466 system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB
467 system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
468 system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch
469 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
470 system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions
471 system.cpu.dtb.read_accesses 218552311 # DTB read accesses
472 system.cpu.dtb.write_accesses 192850034 # DTB write accesses
473 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
474 system.cpu.dtb.hits 409979251 # DTB hits
475 system.cpu.dtb.misses 1423094 # DTB misses
476 system.cpu.dtb.accesses 411402345 # DTB accesses
477 system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
478 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
479 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
481 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
482 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
484 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
485 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
486 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
487 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
488 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
489 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
490 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
491 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
492 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
493 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
494 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
495 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
496 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
497 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
498 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
499 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
500 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
501 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
502 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
503 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
504 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
505 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
506 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
507 system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
508 system.cpu.itb.walker.walks 177767 # Table walker walks requested
509 system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors
510 system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate
511 system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate
512 system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting
513 system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency
514 system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency
515 system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency
516 system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency
517 system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency
518 system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency
519 system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency
520 system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency
521 system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency
522 system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
523 system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
524 system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
525 system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
526 system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
527 system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
528 system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency
529 system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency
530 system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency
531 system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency
532 system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency
533 system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency
534 system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency
535 system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency
536 system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency
537 system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency
538 system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency
539 system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
540 system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
541 system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
542 system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency
543 system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution
544 system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution
545 system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution
546 system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution
547 system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution
548 system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution
549 system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution
550 system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
551 system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution
552 system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated
553 system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated
554 system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated
555 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
556 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst
557 system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst
558 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
559 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst
560 system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst
561 system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst
562 system.cpu.itb.inst_hits 462600046 # ITB inst hits
563 system.cpu.itb.inst_misses 177767 # ITB inst misses
564 system.cpu.itb.read_hits 0 # DTB read hits
565 system.cpu.itb.read_misses 0 # DTB read misses
566 system.cpu.itb.write_hits 0 # DTB write hits
567 system.cpu.itb.write_misses 0 # DTB write misses
568 system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
569 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
570 system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID
571 system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
572 system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB
573 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
574 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
575 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
576 system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions
577 system.cpu.itb.read_accesses 0 # DTB read accesses
578 system.cpu.itb.write_accesses 0 # DTB write accesses
579 system.cpu.itb.inst_accesses 462777813 # ITB inst accesses
580 system.cpu.itb.hits 462600046 # DTB hits
581 system.cpu.itb.misses 177767 # DTB misses
582 system.cpu.itb.accesses 462777813 # DTB accesses
583 system.cpu.numPwrStateTransitions 34262 # Number of power state transitions
584 system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state
585 system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state
586 system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state
587 system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state
588 system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state
589 system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state
590 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
591 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
592 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
593 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
594 system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
595 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
596 system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
597 system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state
598 system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
599 system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
600 system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
601 system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state
602 system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states
603 system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states
604 system.cpu.numCycles 2131080190 # number of cpu cycles simulated
605 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
606 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
607 system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss
608 system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed
609 system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered
610 system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken
611 system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked
612 system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing
613 system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb
614 system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
615 system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps
616 system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions
617 system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR
618 system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched
619 system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed
620 system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed
621 system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total)
622 system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total)
623 system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total)
624 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
625 system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total)
626 system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total)
627 system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total)
628 system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total)
629 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
630 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
631 system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
632 system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total)
633 system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle
634 system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle
635 system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle
636 system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked
637 system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running
638 system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking
639 system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing
640 system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch
641 system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction
642 system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode
643 system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode
644 system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing
645 system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle
646 system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking
647 system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst
648 system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running
649 system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking
650 system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename
651 system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename
652 system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full
653 system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full
654 system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full
655 system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full
656 system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers
657 system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed
658 system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made
659 system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups
660 system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups
661 system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed
662 system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing
663 system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed
664 system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed
665 system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer
666 system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit.
667 system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit.
668 system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads.
669 system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores.
670 system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec)
671 system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ
672 system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued
673 system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued
674 system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling
675 system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph
676 system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed
677 system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle
678 system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle
679 system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle
680 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
681 system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle
682 system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle
683 system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle
684 system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle
685 system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle
686 system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle
687 system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
688 system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
689 system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
690 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
691 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
692 system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
693 system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle
694 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
695 system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available
696 system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available
697 system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available
698 system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available
699 system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available
700 system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available
701 system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available
702 system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available
703 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available
704 system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available
705 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available
706 system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available
707 system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available
708 system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available
709 system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available
710 system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available
711 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available
712 system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available
713 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available
714 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available
715 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available
716 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available
717 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available
718 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available
719 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available
720 system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available
721 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available
722 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available
723 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available
724 system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available
725 system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available
726 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
727 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
728 system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued
729 system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued
730 system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued
731 system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued
732 system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued
733 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued
734 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued
735 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued
736 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued
737 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued
738 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued
739 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued
740 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued
741 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued
742 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued
743 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued
744 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued
745 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued
746 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued
747 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued
748 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued
749 system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued
750 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued
751 system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued
752 system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued
753 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued
754 system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued
755 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued
756 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued
757 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued
758 system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued
759 system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued
760 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
761 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
762 system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued
763 system.cpu.iq.rate 0.638398 # Inst issue rate
764 system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested
765 system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst)
766 system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads
767 system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes
768 system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses
769 system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads
770 system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes
771 system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses
772 system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses
773 system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses
774 system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores
775 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
776 system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed
777 system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed
778 system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations
779 system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed
780 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
781 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
782 system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled
783 system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked
784 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
785 system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing
786 system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking
787 system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking
788 system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ
789 system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
790 system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions
791 system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions
792 system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions
793 system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall
794 system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall
795 system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations
796 system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly
797 system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly
798 system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute
799 system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions
800 system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed
801 system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute
802 system.cpu.iew.exec_swp 0 # number of swp insts executed
803 system.cpu.iew.exec_nop 285536 # number of nop insts executed
804 system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed
805 system.cpu.iew.exec_branches 255680172 # Number of branches executed
806 system.cpu.iew.exec_stores 192439435 # Number of stores executed
807 system.cpu.iew.exec_rate 0.631996 # Inst execution rate
808 system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit
809 system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back
810 system.cpu.iew.wb_producers 574929948 # num instructions producing a value
811 system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value
812 system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle
813 system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back
814 system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit
815 system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards
816 system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted
817 system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle
818 system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle
819 system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle
820 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
821 system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle
822 system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle
823 system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle
824 system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle
825 system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle
826 system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle
827 system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle
828 system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle
829 system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle
830 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
831 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
832 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
833 system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle
834 system.cpu.commit.committedInsts 1106923026 # Number of instructions committed
835 system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed
836 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
837 system.cpu.commit.refs 394099255 # Number of memory references committed
838 system.cpu.commit.loads 205210646 # Number of loads committed
839 system.cpu.commit.membars 9122435 # Number of memory barriers committed
840 system.cpu.commit.branches 247396089 # Number of branches committed
841 system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions.
842 system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions.
843 system.cpu.commit.function_calls 30973786 # Number of function calls committed.
844 system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
845 system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction
846 system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction
847 system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction
848 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
849 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
850 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
851 system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction
852 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction
853 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
854 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
855 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
856 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
857 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
858 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
859 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
860 system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
861 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
862 system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
863 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
864 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
865 system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction
866 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
867 system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction
868 system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction
869 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
870 system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction
871 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction
872 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction
873 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction
874 system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction
875 system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction
876 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
877 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
878 system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction
879 system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached
880 system.cpu.rob.rob_reads 3398675710 # The number of ROB reads
881 system.cpu.rob.rob_writes 2741957858 # The number of ROB writes
882 system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself
883 system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling
884 system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
885 system.cpu.committedInsts 1106923026 # Number of Instructions Simulated
886 system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated
887 system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction
888 system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads
889 system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle
890 system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads
891 system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads
892 system.cpu.int_regfile_writes 942915680 # number of integer regfile writes
893 system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads
894 system.cpu.fp_regfile_writes 762380 # number of floating regfile writes
895 system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads
896 system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes
897 system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads
898 system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes
899 system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
900 system.cpu.dcache.tags.replacements 13662519 # number of replacements
901 system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use
902 system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks.
903 system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks.
904 system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks.
905 system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit.
906 system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor
907 system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
908 system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
909 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
910 system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
911 system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
912 system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
913 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
914 system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses
915 system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses
916 system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
917 system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits
918 system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits
919 system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits
920 system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits
921 system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits
922 system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits
923 system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits
924 system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits
925 system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits
926 system.cpu.dcache.LoadLockedReq_hits::total 4793284 # number of LoadLockedReq hits
927 system.cpu.dcache.StoreCondReq_hits::cpu.data 5278947 # number of StoreCondReq hits
928 system.cpu.dcache.StoreCondReq_hits::total 5278947 # number of StoreCondReq hits
929 system.cpu.dcache.demand_hits::cpu.data 350624733 # number of demand (read+write) hits
930 system.cpu.dcache.demand_hits::total 350624733 # number of demand (read+write) hits
931 system.cpu.dcache.overall_hits::cpu.data 351088116 # number of overall hits
932 system.cpu.dcache.overall_hits::total 351088116 # number of overall hits
933 system.cpu.dcache.ReadReq_misses::cpu.data 12788061 # number of ReadReq misses
934 system.cpu.dcache.ReadReq_misses::total 12788061 # number of ReadReq misses
935 system.cpu.dcache.WriteReq_misses::cpu.data 18648516 # number of WriteReq misses
936 system.cpu.dcache.WriteReq_misses::total 18648516 # number of WriteReq misses
937 system.cpu.dcache.SoftPFReq_misses::cpu.data 2041461 # number of SoftPFReq misses
938 system.cpu.dcache.SoftPFReq_misses::total 2041461 # number of SoftPFReq misses
939 system.cpu.dcache.WriteLineReq_misses::cpu.data 1270506 # number of WriteLineReq misses
940 system.cpu.dcache.WriteLineReq_misses::total 1270506 # number of WriteLineReq misses
941 system.cpu.dcache.LoadLockedReq_misses::cpu.data 548369 # number of LoadLockedReq misses
942 system.cpu.dcache.LoadLockedReq_misses::total 548369 # number of LoadLockedReq misses
943 system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses
944 system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
945 system.cpu.dcache.demand_misses::cpu.data 32707083 # number of demand (read+write) misses
946 system.cpu.dcache.demand_misses::total 32707083 # number of demand (read+write) misses
947 system.cpu.dcache.overall_misses::cpu.data 34748544 # number of overall misses
948 system.cpu.dcache.overall_misses::total 34748544 # number of overall misses
949 system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000 # number of ReadReq miss cycles
950 system.cpu.dcache.ReadReq_miss_latency::total 205827865000 # number of ReadReq miss cycles
951 system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741 # number of WriteReq miss cycles
952 system.cpu.dcache.WriteReq_miss_latency::total 1003464059741 # number of WriteReq miss cycles
953 system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 29968640002 # number of WriteLineReq miss cycles
954 system.cpu.dcache.WriteLineReq_miss_latency::total 29968640002 # number of WriteLineReq miss cycles
955 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8933513500 # number of LoadLockedReq miss cycles
956 system.cpu.dcache.LoadLockedReq_miss_latency::total 8933513500 # number of LoadLockedReq miss cycles
957 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 300500 # number of StoreCondReq miss cycles
958 system.cpu.dcache.StoreCondReq_miss_latency::total 300500 # number of StoreCondReq miss cycles
959 system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743 # number of demand (read+write) miss cycles
960 system.cpu.dcache.demand_miss_latency::total 1239260564743 # number of demand (read+write) miss cycles
961 system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743 # number of overall miss cycles
962 system.cpu.dcache.overall_miss_latency::total 1239260564743 # number of overall miss cycles
963 system.cpu.dcache.ReadReq_accesses::cpu.data 199734647 # number of ReadReq accesses(hits+misses)
964 system.cpu.dcache.ReadReq_accesses::total 199734647 # number of ReadReq accesses(hits+misses)
965 system.cpu.dcache.WriteReq_accesses::cpu.data 181992675 # number of WriteReq accesses(hits+misses)
966 system.cpu.dcache.WriteReq_accesses::total 181992675 # number of WriteReq accesses(hits+misses)
967 system.cpu.dcache.SoftPFReq_accesses::cpu.data 2504844 # number of SoftPFReq accesses(hits+misses)
968 system.cpu.dcache.SoftPFReq_accesses::total 2504844 # number of SoftPFReq accesses(hits+misses)
969 system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses)
970 system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses)
971 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5341653 # number of LoadLockedReq accesses(hits+misses)
972 system.cpu.dcache.LoadLockedReq_accesses::total 5341653 # number of LoadLockedReq accesses(hits+misses)
973 system.cpu.dcache.StoreCondReq_accesses::cpu.data 5278956 # number of StoreCondReq accesses(hits+misses)
974 system.cpu.dcache.StoreCondReq_accesses::total 5278956 # number of StoreCondReq accesses(hits+misses)
975 system.cpu.dcache.demand_accesses::cpu.data 383331816 # number of demand (read+write) accesses
976 system.cpu.dcache.demand_accesses::total 383331816 # number of demand (read+write) accesses
977 system.cpu.dcache.overall_accesses::cpu.data 385836660 # number of overall (read+write) accesses
978 system.cpu.dcache.overall_accesses::total 385836660 # number of overall (read+write) accesses
979 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064025 # miss rate for ReadReq accesses
980 system.cpu.dcache.ReadReq_miss_rate::total 0.064025 # miss rate for ReadReq accesses
981 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102468 # miss rate for WriteReq accesses
982 system.cpu.dcache.WriteReq_miss_rate::total 0.102468 # miss rate for WriteReq accesses
983 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.815005 # miss rate for SoftPFReq accesses
984 system.cpu.dcache.SoftPFReq_miss_rate::total 0.815005 # miss rate for SoftPFReq accesses
985 system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791842 # miss rate for WriteLineReq accesses
986 system.cpu.dcache.WriteLineReq_miss_rate::total 0.791842 # miss rate for WriteLineReq accesses
987 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102659 # miss rate for LoadLockedReq accesses
988 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102659 # miss rate for LoadLockedReq accesses
989 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
990 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
991 system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses
992 system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses
993 system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses
994 system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses
995 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency
996 system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency
997 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency
998 system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency
999 system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency
1000 system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency
1001 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency
1002 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency
1003 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency
1004 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency
1005 system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency
1006 system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency
1007 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency
1008 system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency
1009 system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked
1010 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1011 system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked
1012 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1013 system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked
1014 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1015 system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks
1016 system.cpu.dcache.writebacks::total 10319802 # number of writebacks
1017 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits
1018 system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits
1019 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits
1020 system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits
1021 system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits
1022 system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits
1023 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits
1024 system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits
1025 system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits
1026 system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits
1027 system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits
1028 system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits
1029 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses
1030 system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses
1031 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses
1032 system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses
1033 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses
1034 system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses
1035 system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses
1036 system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses
1037 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses
1038 system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses
1039 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses
1040 system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
1041 system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses
1042 system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses
1043 system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses
1044 system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses
1045 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
1046 system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable
1047 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
1048 system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
1049 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
1050 system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses
1051 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles
1052 system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles
1053 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles
1054 system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles
1055 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles
1056 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles
1057 system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles
1058 system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles
1059 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles
1060 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles
1061 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles
1062 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles
1063 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles
1064 system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles
1065 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles
1066 system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles
1067 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles
1068 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles
1069 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles
1070 system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles
1071 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses
1072 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses
1073 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses
1074 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses
1075 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses
1076 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses
1077 system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses
1078 system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses
1079 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses
1080 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses
1081 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
1082 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
1083 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses
1084 system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses
1085 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses
1086 system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses
1087 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency
1088 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency
1089 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency
1090 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency
1091 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency
1092 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency
1093 system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency
1094 system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency
1095 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency
1096 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency
1097 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency
1098 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency
1099 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency
1100 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency
1101 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency
1102 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency
1103 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency
1104 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency
1105 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency
1106 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency
1107 system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1108 system.cpu.icache.tags.replacements 16891256 # number of replacements
1109 system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use
1110 system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks.
1111 system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks.
1112 system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks.
1113 system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit.
1114 system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor
1115 system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy
1116 system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy
1117 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1118 system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
1119 system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
1120 system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id
1121 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1122 system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses
1123 system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses
1124 system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1125 system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits
1126 system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits
1127 system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits
1128 system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits
1129 system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits
1130 system.cpu.icache.overall_hits::total 444441322 # number of overall hits
1131 system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses
1132 system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses
1133 system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses
1134 system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses
1135 system.cpu.icache.overall_misses::cpu.inst 17679342 # number of overall misses
1136 system.cpu.icache.overall_misses::total 17679342 # number of overall misses
1137 system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389 # number of ReadReq miss cycles
1138 system.cpu.icache.ReadReq_miss_latency::total 234300237389 # number of ReadReq miss cycles
1139 system.cpu.icache.demand_miss_latency::cpu.inst 234300237389 # number of demand (read+write) miss cycles
1140 system.cpu.icache.demand_miss_latency::total 234300237389 # number of demand (read+write) miss cycles
1141 system.cpu.icache.overall_miss_latency::cpu.inst 234300237389 # number of overall miss cycles
1142 system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles
1143 system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses)
1144 system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses)
1145 system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses
1146 system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses
1147 system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses
1148 system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses
1149 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses
1150 system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses
1151 system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses
1152 system.cpu.icache.demand_miss_rate::total 0.038257 # miss rate for demand accesses
1153 system.cpu.icache.overall_miss_rate::cpu.inst 0.038257 # miss rate for overall accesses
1154 system.cpu.icache.overall_miss_rate::total 0.038257 # miss rate for overall accesses
1155 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101 # average ReadReq miss latency
1156 system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101 # average ReadReq miss latency
1157 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency
1158 system.cpu.icache.demand_avg_miss_latency::total 13252.769101 # average overall miss latency
1159 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency
1160 system.cpu.icache.overall_avg_miss_latency::total 13252.769101 # average overall miss latency
1161 system.cpu.icache.blocked_cycles::no_mshrs 16371 # number of cycles access was blocked
1162 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1163 system.cpu.icache.blocked::no_mshrs 1212 # number of cycles access was blocked
1164 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1165 system.cpu.icache.avg_blocked_cycles::no_mshrs 13.507426 # average number of cycles each access was blocked
1166 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1167 system.cpu.icache.writebacks::writebacks 16891256 # number of writebacks
1168 system.cpu.icache.writebacks::total 16891256 # number of writebacks
1169 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 787348 # number of ReadReq MSHR hits
1170 system.cpu.icache.ReadReq_mshr_hits::total 787348 # number of ReadReq MSHR hits
1171 system.cpu.icache.demand_mshr_hits::cpu.inst 787348 # number of demand (read+write) MSHR hits
1172 system.cpu.icache.demand_mshr_hits::total 787348 # number of demand (read+write) MSHR hits
1173 system.cpu.icache.overall_mshr_hits::cpu.inst 787348 # number of overall MSHR hits
1174 system.cpu.icache.overall_mshr_hits::total 787348 # number of overall MSHR hits
1175 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16891994 # number of ReadReq MSHR misses
1176 system.cpu.icache.ReadReq_mshr_misses::total 16891994 # number of ReadReq MSHR misses
1177 system.cpu.icache.demand_mshr_misses::cpu.inst 16891994 # number of demand (read+write) MSHR misses
1178 system.cpu.icache.demand_mshr_misses::total 16891994 # number of demand (read+write) MSHR misses
1179 system.cpu.icache.overall_mshr_misses::cpu.inst 16891994 # number of overall MSHR misses
1180 system.cpu.icache.overall_mshr_misses::total 16891994 # number of overall MSHR misses
1181 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
1182 system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
1183 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
1184 system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
1185 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398 # number of ReadReq MSHR miss cycles
1186 system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398 # number of ReadReq MSHR miss cycles
1187 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398 # number of demand (read+write) MSHR miss cycles
1188 system.cpu.icache.demand_mshr_miss_latency::total 210691534398 # number of demand (read+write) MSHR miss cycles
1189 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398 # number of overall MSHR miss cycles
1190 system.cpu.icache.overall_mshr_miss_latency::total 210691534398 # number of overall MSHR miss cycles
1191 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1610722500 # number of ReadReq MSHR uncacheable cycles
1192 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1610722500 # number of ReadReq MSHR uncacheable cycles
1193 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1610722500 # number of overall MSHR uncacheable cycles
1194 system.cpu.icache.overall_mshr_uncacheable_latency::total 1610722500 # number of overall MSHR uncacheable cycles
1195 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for ReadReq accesses
1196 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036553 # mshr miss rate for ReadReq accesses
1197 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for demand accesses
1198 system.cpu.icache.demand_mshr_miss_rate::total 0.036553 # mshr miss rate for demand accesses
1199 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for overall accesses
1200 system.cpu.icache.overall_mshr_miss_rate::total 0.036553 # mshr miss rate for overall accesses
1201 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440 # average ReadReq mshr miss latency
1202 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440 # average ReadReq mshr miss latency
1203 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency
1204 system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency
1205 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency
1206 system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency
1207 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency
1208 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency
1209 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency
1210 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency
1211 system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1212 system.cpu.l2cache.tags.replacements 2372905 # number of replacements
1213 system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use
1214 system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks.
1215 system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks.
1216 system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks.
1217 system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit.
1218 system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor
1219 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor
1220 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor
1221 system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor
1222 system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor
1223 system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy
1224 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy
1225 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy
1226 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy
1227 system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy
1228 system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy
1229 system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id
1230 system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id
1231 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id
1232 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
1233 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id
1234 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
1235 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id
1236 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id
1237 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id
1238 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # Percentage of cache occupancy per task id
1239 system.cpu.l2cache.tags.tag_accesses 505094110 # Number of tag accesses
1240 system.cpu.l2cache.tags.data_accesses 505094110 # Number of data accesses
1241 system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1242 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1274032 # number of ReadReq hits
1243 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 302472 # number of ReadReq hits
1244 system.cpu.l2cache.ReadReq_hits::total 1576504 # number of ReadReq hits
1245 system.cpu.l2cache.WritebackDirty_hits::writebacks 10319802 # number of WritebackDirty hits
1246 system.cpu.l2cache.WritebackDirty_hits::total 10319802 # number of WritebackDirty hits
1247 system.cpu.l2cache.WritebackClean_hits::writebacks 16888637 # number of WritebackClean hits
1248 system.cpu.l2cache.WritebackClean_hits::total 16888637 # number of WritebackClean hits
1249 system.cpu.l2cache.UpgradeReq_hits::cpu.data 38922 # number of UpgradeReq hits
1250 system.cpu.l2cache.UpgradeReq_hits::total 38922 # number of UpgradeReq hits
1251 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits
1252 system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
1253 system.cpu.l2cache.ReadExReq_hits::cpu.data 1712070 # number of ReadExReq hits
1254 system.cpu.l2cache.ReadExReq_hits::total 1712070 # number of ReadExReq hits
1255 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16794801 # number of ReadCleanReq hits
1256 system.cpu.l2cache.ReadCleanReq_hits::total 16794801 # number of ReadCleanReq hits
1257 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8925946 # number of ReadSharedReq hits
1258 system.cpu.l2cache.ReadSharedReq_hits::total 8925946 # number of ReadSharedReq hits
1259 system.cpu.l2cache.InvalidateReq_hits::cpu.data 673558 # number of InvalidateReq hits
1260 system.cpu.l2cache.InvalidateReq_hits::total 673558 # number of InvalidateReq hits
1261 system.cpu.l2cache.demand_hits::cpu.dtb.walker 1274032 # number of demand (read+write) hits
1262 system.cpu.l2cache.demand_hits::cpu.itb.walker 302472 # number of demand (read+write) hits
1263 system.cpu.l2cache.demand_hits::cpu.inst 16794801 # number of demand (read+write) hits
1264 system.cpu.l2cache.demand_hits::cpu.data 10638016 # number of demand (read+write) hits
1265 system.cpu.l2cache.demand_hits::total 29009321 # number of demand (read+write) hits
1266 system.cpu.l2cache.overall_hits::cpu.dtb.walker 1274032 # number of overall hits
1267 system.cpu.l2cache.overall_hits::cpu.itb.walker 302472 # number of overall hits
1268 system.cpu.l2cache.overall_hits::cpu.inst 16794801 # number of overall hits
1269 system.cpu.l2cache.overall_hits::cpu.data 10638016 # number of overall hits
1270 system.cpu.l2cache.overall_hits::total 29009321 # number of overall hits
1271 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10437 # number of ReadReq misses
1272 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8742 # number of ReadReq misses
1273 system.cpu.l2cache.ReadReq_misses::total 19179 # number of ReadReq misses
1274 system.cpu.l2cache.UpgradeReq_misses::cpu.data 4078 # number of UpgradeReq misses
1275 system.cpu.l2cache.UpgradeReq_misses::total 4078 # number of UpgradeReq misses
1276 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
1277 system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
1278 system.cpu.l2cache.ReadExReq_misses::cpu.data 1333352 # number of ReadExReq misses
1279 system.cpu.l2cache.ReadExReq_misses::total 1333352 # number of ReadExReq misses
1280 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 96984 # number of ReadCleanReq misses
1281 system.cpu.l2cache.ReadCleanReq_misses::total 96984 # number of ReadCleanReq misses
1282 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 428025 # number of ReadSharedReq misses
1283 system.cpu.l2cache.ReadSharedReq_misses::total 428025 # number of ReadSharedReq misses
1284 system.cpu.l2cache.InvalidateReq_misses::cpu.data 590099 # number of InvalidateReq misses
1285 system.cpu.l2cache.InvalidateReq_misses::total 590099 # number of InvalidateReq misses
1286 system.cpu.l2cache.demand_misses::cpu.dtb.walker 10437 # number of demand (read+write) misses
1287 system.cpu.l2cache.demand_misses::cpu.itb.walker 8742 # number of demand (read+write) misses
1288 system.cpu.l2cache.demand_misses::cpu.inst 96984 # number of demand (read+write) misses
1289 system.cpu.l2cache.demand_misses::cpu.data 1761377 # number of demand (read+write) misses
1290 system.cpu.l2cache.demand_misses::total 1877540 # number of demand (read+write) misses
1291 system.cpu.l2cache.overall_misses::cpu.dtb.walker 10437 # number of overall misses
1292 system.cpu.l2cache.overall_misses::cpu.itb.walker 8742 # number of overall misses
1293 system.cpu.l2cache.overall_misses::cpu.inst 96984 # number of overall misses
1294 system.cpu.l2cache.overall_misses::cpu.data 1761377 # number of overall misses
1295 system.cpu.l2cache.overall_misses::total 1877540 # number of overall misses
1296 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 936727000 # number of ReadReq miss cycles
1297 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 780169000 # number of ReadReq miss cycles
1298 system.cpu.l2cache.ReadReq_miss_latency::total 1716896000 # number of ReadReq miss cycles
1299 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73235500 # number of UpgradeReq miss cycles
1300 system.cpu.l2cache.UpgradeReq_miss_latency::total 73235500 # number of UpgradeReq miss cycles
1301 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles
1302 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles
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1304 system.cpu.l2cache.ReadExReq_miss_latency::total 123861773500 # number of ReadExReq miss cycles
1305 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8301693500 # number of ReadCleanReq miss cycles
1306 system.cpu.l2cache.ReadCleanReq_miss_latency::total 8301693500 # number of ReadCleanReq miss cycles
1307 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38723437000 # number of ReadSharedReq miss cycles
1308 system.cpu.l2cache.ReadSharedReq_miss_latency::total 38723437000 # number of ReadSharedReq miss cycles
1309 system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 483000 # number of InvalidateReq miss cycles
1310 system.cpu.l2cache.InvalidateReq_miss_latency::total 483000 # number of InvalidateReq miss cycles
1311 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 936727000 # number of demand (read+write) miss cycles
1312 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 780169000 # number of demand (read+write) miss cycles
1313 system.cpu.l2cache.demand_miss_latency::cpu.inst 8301693500 # number of demand (read+write) miss cycles
1314 system.cpu.l2cache.demand_miss_latency::cpu.data 162585210500 # number of demand (read+write) miss cycles
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1316 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 936727000 # number of overall miss cycles
1317 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 780169000 # number of overall miss cycles
1318 system.cpu.l2cache.overall_miss_latency::cpu.inst 8301693500 # number of overall miss cycles
1319 system.cpu.l2cache.overall_miss_latency::cpu.data 162585210500 # number of overall miss cycles
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1321 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1284469 # number of ReadReq accesses(hits+misses)
1322 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 311214 # number of ReadReq accesses(hits+misses)
1323 system.cpu.l2cache.ReadReq_accesses::total 1595683 # number of ReadReq accesses(hits+misses)
1324 system.cpu.l2cache.WritebackDirty_accesses::writebacks 10319802 # number of WritebackDirty accesses(hits+misses)
1325 system.cpu.l2cache.WritebackDirty_accesses::total 10319802 # number of WritebackDirty accesses(hits+misses)
1326 system.cpu.l2cache.WritebackClean_accesses::writebacks 16888637 # number of WritebackClean accesses(hits+misses)
1327 system.cpu.l2cache.WritebackClean_accesses::total 16888637 # number of WritebackClean accesses(hits+misses)
1328 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43000 # number of UpgradeReq accesses(hits+misses)
1329 system.cpu.l2cache.UpgradeReq_accesses::total 43000 # number of UpgradeReq accesses(hits+misses)
1330 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses)
1331 system.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses)
1332 system.cpu.l2cache.ReadExReq_accesses::cpu.data 3045422 # number of ReadExReq accesses(hits+misses)
1333 system.cpu.l2cache.ReadExReq_accesses::total 3045422 # number of ReadExReq accesses(hits+misses)
1334 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16891785 # number of ReadCleanReq accesses(hits+misses)
1335 system.cpu.l2cache.ReadCleanReq_accesses::total 16891785 # number of ReadCleanReq accesses(hits+misses)
1336 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9353971 # number of ReadSharedReq accesses(hits+misses)
1337 system.cpu.l2cache.ReadSharedReq_accesses::total 9353971 # number of ReadSharedReq accesses(hits+misses)
1338 system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263657 # number of InvalidateReq accesses(hits+misses)
1339 system.cpu.l2cache.InvalidateReq_accesses::total 1263657 # number of InvalidateReq accesses(hits+misses)
1340 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1284469 # number of demand (read+write) accesses
1341 system.cpu.l2cache.demand_accesses::cpu.itb.walker 311214 # number of demand (read+write) accesses
1342 system.cpu.l2cache.demand_accesses::cpu.inst 16891785 # number of demand (read+write) accesses
1343 system.cpu.l2cache.demand_accesses::cpu.data 12399393 # number of demand (read+write) accesses
1344 system.cpu.l2cache.demand_accesses::total 30886861 # number of demand (read+write) accesses
1345 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1284469 # number of overall (read+write) accesses
1346 system.cpu.l2cache.overall_accesses::cpu.itb.walker 311214 # number of overall (read+write) accesses
1347 system.cpu.l2cache.overall_accesses::cpu.inst 16891785 # number of overall (read+write) accesses
1348 system.cpu.l2cache.overall_accesses::cpu.data 12399393 # number of overall (read+write) accesses
1349 system.cpu.l2cache.overall_accesses::total 30886861 # number of overall (read+write) accesses
1350 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008126 # miss rate for ReadReq accesses
1351 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028090 # miss rate for ReadReq accesses
1352 system.cpu.l2cache.ReadReq_miss_rate::total 0.012019 # miss rate for ReadReq accesses
1353 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.094837 # miss rate for UpgradeReq accesses
1354 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.094837 # miss rate for UpgradeReq accesses
1355 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.444444 # miss rate for SCUpgradeReq accesses
1356 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.444444 # miss rate for SCUpgradeReq accesses
1357 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437822 # miss rate for ReadExReq accesses
1358 system.cpu.l2cache.ReadExReq_miss_rate::total 0.437822 # miss rate for ReadExReq accesses
1359 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005741 # miss rate for ReadCleanReq accesses
1360 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005741 # miss rate for ReadCleanReq accesses
1361 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045759 # miss rate for ReadSharedReq accesses
1362 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045759 # miss rate for ReadSharedReq accesses
1363 system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.466977 # miss rate for InvalidateReq accesses
1364 system.cpu.l2cache.InvalidateReq_miss_rate::total 0.466977 # miss rate for InvalidateReq accesses
1365 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008126 # miss rate for demand accesses
1366 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028090 # miss rate for demand accesses
1367 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005741 # miss rate for demand accesses
1368 system.cpu.l2cache.demand_miss_rate::cpu.data 0.142053 # miss rate for demand accesses
1369 system.cpu.l2cache.demand_miss_rate::total 0.060788 # miss rate for demand accesses
1370 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008126 # miss rate for overall accesses
1371 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028090 # miss rate for overall accesses
1372 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005741 # miss rate for overall accesses
1373 system.cpu.l2cache.overall_miss_rate::cpu.data 0.142053 # miss rate for overall accesses
1374 system.cpu.l2cache.overall_miss_rate::total 0.060788 # miss rate for overall accesses
1375 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89750.598831 # average ReadReq miss latency
1376 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89243.765729 # average ReadReq miss latency
1377 system.cpu.l2cache.ReadReq_avg_miss_latency::total 89519.578706 # average ReadReq miss latency
1378 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17958.680726 # average UpgradeReq miss latency
1379 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17958.680726 # average UpgradeReq miss latency
1380 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency
1381 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency
1382 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92895.029595 # average ReadExReq miss latency
1383 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92895.029595 # average ReadExReq miss latency
1384 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427 # average ReadCleanReq miss latency
1385 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427 # average ReadCleanReq miss latency
1386 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629 # average ReadSharedReq miss latency
1387 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629 # average ReadSharedReq miss latency
1388 system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.818507 # average InvalidateReq miss latency
1389 system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.818507 # average InvalidateReq miss latency
1390 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency
1391 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency
1392 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency
1393 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency
1394 system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377 # average overall miss latency
1395 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency
1396 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency
1397 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency
1398 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency
1399 system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377 # average overall miss latency
1400 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1401 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1402 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1403 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1404 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1405 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1406 system.cpu.l2cache.writebacks::writebacks 2095825 # number of writebacks
1407 system.cpu.l2cache.writebacks::total 2095825 # number of writebacks
1408 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
1409 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
1410 system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
1411 system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
1412 system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
1413 system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
1414 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10437 # number of ReadReq MSHR misses
1415 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8742 # number of ReadReq MSHR misses
1416 system.cpu.l2cache.ReadReq_mshr_misses::total 19179 # number of ReadReq MSHR misses
1417 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses
1418 system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses
1419 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4078 # number of UpgradeReq MSHR misses
1420 system.cpu.l2cache.UpgradeReq_mshr_misses::total 4078 # number of UpgradeReq MSHR misses
1421 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
1422 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
1423 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1333352 # number of ReadExReq MSHR misses
1424 system.cpu.l2cache.ReadExReq_mshr_misses::total 1333352 # number of ReadExReq MSHR misses
1425 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 96984 # number of ReadCleanReq MSHR misses
1426 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 96984 # number of ReadCleanReq MSHR misses
1427 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 428004 # number of ReadSharedReq MSHR misses
1428 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 428004 # number of ReadSharedReq MSHR misses
1429 system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590099 # number of InvalidateReq MSHR misses
1430 system.cpu.l2cache.InvalidateReq_mshr_misses::total 590099 # number of InvalidateReq MSHR misses
1431 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10437 # number of demand (read+write) MSHR misses
1432 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8742 # number of demand (read+write) MSHR misses
1433 system.cpu.l2cache.demand_mshr_misses::cpu.inst 96984 # number of demand (read+write) MSHR misses
1434 system.cpu.l2cache.demand_mshr_misses::cpu.data 1761356 # number of demand (read+write) MSHR misses
1435 system.cpu.l2cache.demand_mshr_misses::total 1877519 # number of demand (read+write) MSHR misses
1436 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10437 # number of overall MSHR misses
1437 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8742 # number of overall MSHR misses
1438 system.cpu.l2cache.overall_mshr_misses::cpu.inst 96984 # number of overall MSHR misses
1439 system.cpu.l2cache.overall_mshr_misses::cpu.data 1761356 # number of overall MSHR misses
1440 system.cpu.l2cache.overall_mshr_misses::total 1877519 # number of overall MSHR misses
1441 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
1442 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
1443 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable
1444 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
1445 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
1446 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
1447 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
1448 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses
1449 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 832356501 # number of ReadReq MSHR miss cycles
1450 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 692749000 # number of ReadReq MSHR miss cycles
1451 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1525105501 # number of ReadReq MSHR miss cycles
1452 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77850000 # number of UpgradeReq MSHR miss cycles
1453 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77850000 # number of UpgradeReq MSHR miss cycles
1454 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles
1455 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles
1456 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195 # number of ReadExReq MSHR miss cycles
1457 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195 # number of ReadExReq MSHR miss cycles
1458 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7331831049 # number of ReadCleanReq MSHR miss cycles
1459 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7331831049 # number of ReadCleanReq MSHR miss cycles
1460 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34442081593 # number of ReadSharedReq MSHR miss cycles
1461 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34442081593 # number of ReadSharedReq MSHR miss cycles
1462 system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12207320002 # number of InvalidateReq MSHR miss cycles
1463 system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12207320002 # number of InvalidateReq MSHR miss cycles
1464 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 832356501 # number of demand (read+write) MSHR miss cycles
1465 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 692749000 # number of demand (read+write) MSHR miss cycles
1466 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7331831049 # number of demand (read+write) MSHR miss cycles
1467 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788 # number of demand (read+write) MSHR miss cycles
1468 system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338 # number of demand (read+write) MSHR miss cycles
1469 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 832356501 # number of overall MSHR miss cycles
1470 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 692749000 # number of overall MSHR miss cycles
1471 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7331831049 # number of overall MSHR miss cycles
1472 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788 # number of overall MSHR miss cycles
1473 system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles
1474 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles
1475 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles
1476 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles
1477 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles
1478 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles
1479 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles
1480 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses
1481 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses
1482 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses
1483 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1484 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1485 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses
1486 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses
1487 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses
1488 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses
1489 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses
1490 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses
1491 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses
1492 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses
1493 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses
1494 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses
1495 system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses
1496 system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses
1497 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses
1498 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses
1499 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses
1500 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses
1501 system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses
1502 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses
1503 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses
1504 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses
1505 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses
1506 system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses
1507 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency
1508 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency
1509 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency
1510 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency
1511 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency
1512 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency
1513 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency
1514 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency
1515 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency
1516 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency
1517 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency
1518 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency
1519 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency
1520 system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency
1521 system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency
1522 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency
1523 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency
1524 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency
1525 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency
1526 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency
1527 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency
1528 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency
1529 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency
1530 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency
1531 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency
1532 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency
1533 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency
1534 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency
1535 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency
1536 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency
1537 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency
1538 system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter.
1539 system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1540 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1541 system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter.
1542 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1543 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1544 system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1545 system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution
1546 system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution
1547 system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution
1548 system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution
1549 system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution
1550 system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution
1551 system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution
1552 system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution
1553 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
1554 system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution
1555 system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution
1556 system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution
1557 system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution
1558 system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution
1559 system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution
1560 system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution
1561 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes)
1562 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes)
1563 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes)
1564 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes)
1565 system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes)
1566 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes)
1567 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes)
1568 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes)
1569 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes)
1570 system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes)
1571 system.cpu.toL2Bus.snoops 2999840 # Total snoops (count)
1572 system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes)
1573 system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram
1574 system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram
1575 system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram
1576 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1577 system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram
1578 system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram
1579 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1580 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1581 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1582 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1583 system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram
1584 system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks)
1585 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1586 system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks)
1587 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1588 system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks)
1589 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1590 system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks)
1591 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1592 system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks)
1593 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1594 system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks)
1595 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1596 system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1597 system.iobus.trans_dist::ReadReq 40300 # Transaction distribution
1598 system.iobus.trans_dist::ReadResp 40300 # Transaction distribution
1599 system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1600 system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1601 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1602 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1603 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1604 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1605 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1606 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1607 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1608 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1609 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1610 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1611 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1612 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1613 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1614 system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1615 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes)
1616 system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes)
1617 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1618 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1619 system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes)
1620 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1621 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1622 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
1623 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1624 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1625 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1626 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1627 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1628 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1629 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1630 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1631 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1632 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1633 system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1634 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes)
1635 system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes)
1636 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1637 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1638 system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes)
1639 system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks)
1640 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1641 system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
1642 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1643 system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks)
1644 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1645 system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
1646 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1647 system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
1648 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1649 system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
1650 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1651 system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
1652 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1653 system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
1654 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1655 system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
1656 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1657 system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
1658 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1659 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
1660 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1661 system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks)
1662 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1663 system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks)
1664 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1665 system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks)
1666 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1667 system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1668 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1669 system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks)
1670 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1671 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1672 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1673 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1674 system.iocache.tags.replacements 115465 # number of replacements
1675 system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use
1676 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1677 system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks.
1678 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1679 system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit.
1680 system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor
1681 system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor
1682 system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy
1683 system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy
1684 system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy
1685 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1686 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1687 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1688 system.iocache.tags.tag_accesses 1039668 # Number of tag accesses
1689 system.iocache.tags.data_accesses 1039668 # Number of data accesses
1690 system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1691 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1692 system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses
1693 system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses
1694 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1695 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1696 system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1697 system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1698 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1699 system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses
1700 system.iocache.demand_misses::total 115519 # number of demand (read+write) misses
1701 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1702 system.iocache.overall_misses::realview.ide 115479 # number of overall misses
1703 system.iocache.overall_misses::total 115519 # number of overall misses
1704 system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
1705 system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles
1706 system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles
1707 system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
1708 system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
1709 system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles
1710 system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles
1711 system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
1712 system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles
1713 system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles
1714 system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
1715 system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles
1716 system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles
1717 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1718 system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses)
1719 system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses)
1720 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1721 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1722 system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
1723 system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
1724 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1725 system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses
1726 system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses
1727 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1728 system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses
1729 system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses
1730 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1731 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1732 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1733 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1734 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1735 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1736 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1737 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1738 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1739 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1740 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1741 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1742 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1743 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
1744 system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency
1745 system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency
1746 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
1747 system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
1748 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency
1749 system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency
1750 system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
1751 system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency
1752 system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency
1753 system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
1754 system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency
1755 system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency
1756 system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked
1757 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1758 system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked
1759 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1760 system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked
1761 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1762 system.iocache.writebacks::writebacks 106630 # number of writebacks
1763 system.iocache.writebacks::total 106630 # number of writebacks
1764 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1765 system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses
1766 system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses
1767 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1768 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1769 system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
1770 system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
1771 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1772 system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses
1773 system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses
1774 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1775 system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses
1776 system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses
1777 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
1778 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles
1779 system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles
1780 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
1781 system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
1782 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles
1783 system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles
1784 system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
1785 system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles
1786 system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles
1787 system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
1788 system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles
1789 system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles
1790 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1791 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1792 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1793 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1794 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1795 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1796 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1797 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1798 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1799 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1800 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1801 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1802 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1803 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
1804 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency
1805 system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency
1806 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
1807 system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
1808 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency
1809 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency
1810 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
1811 system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency
1812 system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency
1813 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
1814 system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency
1815 system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency
1816 system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter.
1817 system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1818 system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1819 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1820 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1821 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1822 system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1823 system.membus.trans_dist::ReadReq 54986 # Transaction distribution
1824 system.membus.trans_dist::ReadResp 608005 # Transaction distribution
1825 system.membus.trans_dist::WriteReq 33703 # Transaction distribution
1826 system.membus.trans_dist::WriteResp 33703 # Transaction distribution
1827 system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution
1828 system.membus.trans_dist::CleanEvict 284620 # Transaction distribution
1829 system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution
1830 system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
1831 system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
1832 system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution
1833 system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution
1834 system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution
1835 system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution
1836 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1837 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
1838 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
1839 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes)
1840 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes)
1841 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes)
1842 system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes)
1843 system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes)
1844 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1845 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
1846 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
1847 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes)
1848 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes)
1849 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes)
1850 system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes)
1851 system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes)
1852 system.membus.snoops 2809 # Total snoops (count)
1853 system.membus.snoopTraffic 179264 # Total snoop traffic (bytes)
1854 system.membus.snoop_fanout::samples 2675908 # Request fanout histogram
1855 system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram
1856 system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram
1857 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1858 system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram
1859 system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram
1860 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1861 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1862 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1863 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1864 system.membus.snoop_fanout::total 2675908 # Request fanout histogram
1865 system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks)
1866 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1867 system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
1868 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1869 system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks)
1870 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1871 system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks)
1872 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1873 system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks)
1874 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1875 system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks)
1876 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1877 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1878 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1879 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1880 system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1881 system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1882 system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1883 system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1884 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1885 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1886 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1887 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1888 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1889 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1890 system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1891 system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1892 system.realview.ethernet.txBytes 966 # Bytes Transmitted
1893 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1894 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1895 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1896 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1897 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1898 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1899 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1900 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1901 system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
1902 system.realview.ethernet.totPackets 3 # Total Packets
1903 system.realview.ethernet.totBytes 966 # Total Bytes
1904 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
1905 system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
1906 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
1907 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1908 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
1909 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1910 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1911 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
1912 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1913 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1914 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
1915 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1916 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1917 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
1918 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1919 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1920 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
1921 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1922 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1923 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
1924 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1925 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1926 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1927 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1928 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1929 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1930 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1931 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1932 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1933 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1934 system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1935 system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1936 system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1937 system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1938 system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1939 system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1940 system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1941 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1942 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1943 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1944 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1945 system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1946 system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1947 system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1948 system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1949 system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1950 system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1951 system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1952 system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1953 system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1954 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1955 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1956 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
1957 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1958 system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed
1960 ---------- End Simulation Statistics ----------
projects / gem5.git / blob