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d65c44016178d681839ee786e40b139d8393ded8
[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview64-o3-dual / config.ini
1 [root]
2 type=Root
3 children=system
4 eventq_index=0
5 full_system=true
6 sim_quantum=0
7 time_sync_enable=false
8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
10
11 [system]
12 type=LinuxArmSystem
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14 atags_addr=134217728
15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17 cache_line_size=64
18 clk_domain=system.clk_domain
19 default_p_state=UNDEFINED
20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
21 early_kernel_symbols=false
22 enable_context_switch_stats_dump=false
23 eventq_index=0
24 exit_on_work_items=false
25 flags_addr=469827632
26 gic_cpu_addr=738205696
27 have_large_asid_64=false
28 have_lpae=true
29 have_security=false
30 have_virtualization=false
31 highest_el_is_64=false
32 init_param=0
33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
34 kernel_addr_check=true
35 load_addr_mask=268435455
36 load_offset=2147483648
37 machine_type=VExpress_EMM64
38 mem_mode=timing
39 mem_ranges=2147483648:2415919103:0:0:0:0
40 memories=system.physmem system.realview.nvmem system.realview.vram
41 mmap_using_noreserve=false
42 multi_proc=true
43 multi_thread=false
44 num_work_ids=16
45 p_state_clk_gate_bins=20
46 p_state_clk_gate_max=1000000000000
47 p_state_clk_gate_min=1000
48 panic_on_oops=true
49 panic_on_panic=true
50 phys_addr_range_64=40
51 power_model=Null
52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
53 reset_addr_64=0
54 symbolfile=
55 thermal_components=
56 thermal_model=Null
57 work_begin_ckpt_count=0
58 work_begin_cpu_id_exit=-1
59 work_begin_exit_count=0
60 work_cpus_ckpt_count=0
61 work_end_ckpt_count=0
62 work_end_exit_count=0
63 work_item_id=-1
64 system_port=system.membus.slave[1]
65
66 [system.bridge]
67 type=Bridge
68 clk_domain=system.clk_domain
69 default_p_state=UNDEFINED
70 delay=50000
71 eventq_index=0
72 p_state_clk_gate_bins=20
73 p_state_clk_gate_max=1000000000000
74 p_state_clk_gate_min=1000
75 power_model=Null
76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
77 req_size=16
78 resp_size=16
79 master=system.iobus.slave[0]
80 slave=system.membus.master[0]
81
82 [system.cf0]
83 type=IdeDisk
84 children=image
85 delay=1000000
86 driveID=master
87 eventq_index=0
88 image=system.cf0.image
89
90 [system.cf0.image]
91 type=CowDiskImage
92 children=child
93 child=system.cf0.image.child
94 eventq_index=0
95 image_file=
96 read_only=false
97 table_size=65536
98
99 [system.cf0.image.child]
100 type=RawDiskImage
101 eventq_index=0
102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
103 read_only=true
104
105 [system.clk_domain]
106 type=SrcClockDomain
107 clock=1000
108 domain_id=-1
109 eventq_index=0
110 init_perf_level=0
111 voltage_domain=system.voltage_domain
112
113 [system.cpu0]
114 type=DerivO3CPU
115 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
116 LFSTSize=1024
117 LQEntries=16
118 LSQCheckLoads=true
119 LSQDepCheckShift=0
120 SQEntries=16
121 SSITSize=1024
122 activity=0
123 backComSize=5
124 branchPred=system.cpu0.branchPred
125 cachePorts=200
126 checker=Null
127 clk_domain=system.cpu_clk_domain
128 commitToDecodeDelay=1
129 commitToFetchDelay=1
130 commitToIEWDelay=1
131 commitToRenameDelay=1
132 commitWidth=8
133 cpu_id=0
134 decodeToFetchDelay=1
135 decodeToRenameDelay=2
136 decodeWidth=3
137 default_p_state=UNDEFINED
138 dispatchWidth=6
139 do_checkpoint_insts=true
140 do_quiesce=true
141 do_statistics_insts=true
142 dstage2_mmu=system.cpu0.dstage2_mmu
143 dtb=system.cpu0.dtb
144 eventq_index=0
145 fetchBufferSize=16
146 fetchQueueSize=32
147 fetchToDecodeDelay=3
148 fetchTrapLatency=1
149 fetchWidth=3
150 forwardComSize=5
151 fuPool=system.cpu0.fuPool
152 function_trace=false
153 function_trace_start=0
154 iewToCommitDelay=1
155 iewToDecodeDelay=1
156 iewToFetchDelay=1
157 iewToRenameDelay=1
158 interrupts=system.cpu0.interrupts
159 isa=system.cpu0.isa
160 issueToExecuteDelay=1
161 issueWidth=8
162 istage2_mmu=system.cpu0.istage2_mmu
163 itb=system.cpu0.itb
164 max_insts_all_threads=0
165 max_insts_any_thread=0
166 max_loads_all_threads=0
167 max_loads_any_thread=0
168 needsTSO=false
169 numIQEntries=32
170 numPhysCCRegs=640
171 numPhysFloatRegs=192
172 numPhysIntRegs=128
173 numROBEntries=40
174 numRobs=1
175 numThreads=1
176 p_state_clk_gate_bins=20
177 p_state_clk_gate_max=1000000000000
178 p_state_clk_gate_min=1000
179 power_model=Null
180 profile=0
181 progress_interval=0
182 renameToDecodeDelay=1
183 renameToFetchDelay=1
184 renameToIEWDelay=1
185 renameToROBDelay=1
186 renameWidth=3
187 simpoint_start_insts=
188 smtCommitPolicy=RoundRobin
189 smtFetchPolicy=SingleThread
190 smtIQPolicy=Partitioned
191 smtIQThreshold=100
192 smtLSQPolicy=Partitioned
193 smtLSQThreshold=100
194 smtNumFetchingThreads=1
195 smtROBPolicy=Partitioned
196 smtROBThreshold=100
197 socket_id=0
198 squashWidth=8
199 store_set_clear_period=250000
200 switched_out=false
201 system=system
202 tracer=system.cpu0.tracer
203 trapLatency=13
204 wbWidth=8
205 workload=
206 dcache_port=system.cpu0.dcache.cpu_side
207 icache_port=system.cpu0.icache.cpu_side
208
209 [system.cpu0.branchPred]
210 type=BiModeBP
211 BTBEntries=2048
212 BTBTagSize=18
213 RASSize=16
214 choiceCtrBits=2
215 choicePredictorSize=8192
216 eventq_index=0
217 globalCtrBits=2
218 globalPredictorSize=8192
219 indirectHashGHR=true
220 indirectHashTargets=true
221 indirectPathLength=3
222 indirectSets=256
223 indirectTagSize=16
224 indirectWays=2
225 instShiftAmt=2
226 numThreads=1
227 useIndirect=true
228
229 [system.cpu0.dcache]
230 type=Cache
231 children=tags
232 addr_ranges=0:18446744073709551615:0:0:0:0
233 assoc=2
234 clk_domain=system.cpu_clk_domain
235 clusivity=mostly_incl
236 default_p_state=UNDEFINED
237 demand_mshr_reserve=1
238 eventq_index=0
239 hit_latency=2
240 is_read_only=false
241 max_miss_count=0
242 mshrs=6
243 p_state_clk_gate_bins=20
244 p_state_clk_gate_max=1000000000000
245 p_state_clk_gate_min=1000
246 power_model=Null
247 prefetch_on_access=false
248 prefetcher=Null
249 response_latency=2
250 sequential_access=false
251 size=32768
252 system=system
253 tags=system.cpu0.dcache.tags
254 tgts_per_mshr=8
255 write_buffers=16
256 writeback_clean=true
257 cpu_side=system.cpu0.dcache_port
258 mem_side=system.cpu0.toL2Bus.slave[1]
259
260 [system.cpu0.dcache.tags]
261 type=LRU
262 assoc=2
263 block_size=64
264 clk_domain=system.cpu_clk_domain
265 default_p_state=UNDEFINED
266 eventq_index=0
267 hit_latency=2
268 p_state_clk_gate_bins=20
269 p_state_clk_gate_max=1000000000000
270 p_state_clk_gate_min=1000
271 power_model=Null
272 sequential_access=false
273 size=32768
274
275 [system.cpu0.dstage2_mmu]
276 type=ArmStage2MMU
277 children=stage2_tlb
278 eventq_index=0
279 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
280 sys=system
281 tlb=system.cpu0.dtb
282
283 [system.cpu0.dstage2_mmu.stage2_tlb]
284 type=ArmTLB
285 children=walker
286 eventq_index=0
287 is_stage2=true
288 size=32
289 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
290
291 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
292 type=ArmTableWalker
293 clk_domain=system.cpu_clk_domain
294 default_p_state=UNDEFINED
295 eventq_index=0
296 is_stage2=true
297 num_squash_per_cycle=2
298 p_state_clk_gate_bins=20
299 p_state_clk_gate_max=1000000000000
300 p_state_clk_gate_min=1000
301 power_model=Null
302 sys=system
303
304 [system.cpu0.dtb]
305 type=ArmTLB
306 children=walker
307 eventq_index=0
308 is_stage2=false
309 size=64
310 walker=system.cpu0.dtb.walker
311
312 [system.cpu0.dtb.walker]
313 type=ArmTableWalker
314 clk_domain=system.cpu_clk_domain
315 default_p_state=UNDEFINED
316 eventq_index=0
317 is_stage2=false
318 num_squash_per_cycle=2
319 p_state_clk_gate_bins=20
320 p_state_clk_gate_max=1000000000000
321 p_state_clk_gate_min=1000
322 power_model=Null
323 sys=system
324 port=system.cpu0.toL2Bus.slave[3]
325
326 [system.cpu0.fuPool]
327 type=FUPool
328 children=FUList0 FUList1 FUList2 FUList3 FUList4
329 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4
330 eventq_index=0
331
332 [system.cpu0.fuPool.FUList0]
333 type=FUDesc
334 children=opList
335 count=2
336 eventq_index=0
337 opList=system.cpu0.fuPool.FUList0.opList
338
339 [system.cpu0.fuPool.FUList0.opList]
340 type=OpDesc
341 eventq_index=0
342 opClass=IntAlu
343 opLat=1
344 pipelined=true
345
346 [system.cpu0.fuPool.FUList1]
347 type=FUDesc
348 children=opList0 opList1 opList2
349 count=1
350 eventq_index=0
351 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2
352
353 [system.cpu0.fuPool.FUList1.opList0]
354 type=OpDesc
355 eventq_index=0
356 opClass=IntMult
357 opLat=3
358 pipelined=true
359
360 [system.cpu0.fuPool.FUList1.opList1]
361 type=OpDesc
362 eventq_index=0
363 opClass=IntDiv
364 opLat=12
365 pipelined=false
366
367 [system.cpu0.fuPool.FUList1.opList2]
368 type=OpDesc
369 eventq_index=0
370 opClass=IprAccess
371 opLat=3
372 pipelined=true
373
374 [system.cpu0.fuPool.FUList2]
375 type=FUDesc
376 children=opList
377 count=1
378 eventq_index=0
379 opList=system.cpu0.fuPool.FUList2.opList
380
381 [system.cpu0.fuPool.FUList2.opList]
382 type=OpDesc
383 eventq_index=0
384 opClass=MemRead
385 opLat=2
386 pipelined=true
387
388 [system.cpu0.fuPool.FUList3]
389 type=FUDesc
390 children=opList
391 count=1
392 eventq_index=0
393 opList=system.cpu0.fuPool.FUList3.opList
394
395 [system.cpu0.fuPool.FUList3.opList]
396 type=OpDesc
397 eventq_index=0
398 opClass=MemWrite
399 opLat=2
400 pipelined=true
401
402 [system.cpu0.fuPool.FUList4]
403 type=FUDesc
404 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
405 count=2
406 eventq_index=0
407 opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
408
409 [system.cpu0.fuPool.FUList4.opList00]
410 type=OpDesc
411 eventq_index=0
412 opClass=SimdAdd
413 opLat=4
414 pipelined=true
415
416 [system.cpu0.fuPool.FUList4.opList01]
417 type=OpDesc
418 eventq_index=0
419 opClass=SimdAddAcc
420 opLat=4
421 pipelined=true
422
423 [system.cpu0.fuPool.FUList4.opList02]
424 type=OpDesc
425 eventq_index=0
426 opClass=SimdAlu
427 opLat=4
428 pipelined=true
429
430 [system.cpu0.fuPool.FUList4.opList03]
431 type=OpDesc
432 eventq_index=0
433 opClass=SimdCmp
434 opLat=4
435 pipelined=true
436
437 [system.cpu0.fuPool.FUList4.opList04]
438 type=OpDesc
439 eventq_index=0
440 opClass=SimdCvt
441 opLat=3
442 pipelined=true
443
444 [system.cpu0.fuPool.FUList4.opList05]
445 type=OpDesc
446 eventq_index=0
447 opClass=SimdMisc
448 opLat=3
449 pipelined=true
450
451 [system.cpu0.fuPool.FUList4.opList06]
452 type=OpDesc
453 eventq_index=0
454 opClass=SimdMult
455 opLat=5
456 pipelined=true
457
458 [system.cpu0.fuPool.FUList4.opList07]
459 type=OpDesc
460 eventq_index=0
461 opClass=SimdMultAcc
462 opLat=5
463 pipelined=true
464
465 [system.cpu0.fuPool.FUList4.opList08]
466 type=OpDesc
467 eventq_index=0
468 opClass=SimdShift
469 opLat=3
470 pipelined=true
471
472 [system.cpu0.fuPool.FUList4.opList09]
473 type=OpDesc
474 eventq_index=0
475 opClass=SimdShiftAcc
476 opLat=3
477 pipelined=true
478
479 [system.cpu0.fuPool.FUList4.opList10]
480 type=OpDesc
481 eventq_index=0
482 opClass=SimdSqrt
483 opLat=9
484 pipelined=true
485
486 [system.cpu0.fuPool.FUList4.opList11]
487 type=OpDesc
488 eventq_index=0
489 opClass=SimdFloatAdd
490 opLat=5
491 pipelined=true
492
493 [system.cpu0.fuPool.FUList4.opList12]
494 type=OpDesc
495 eventq_index=0
496 opClass=SimdFloatAlu
497 opLat=5
498 pipelined=true
499
500 [system.cpu0.fuPool.FUList4.opList13]
501 type=OpDesc
502 eventq_index=0
503 opClass=SimdFloatCmp
504 opLat=3
505 pipelined=true
506
507 [system.cpu0.fuPool.FUList4.opList14]
508 type=OpDesc
509 eventq_index=0
510 opClass=SimdFloatCvt
511 opLat=3
512 pipelined=true
513
514 [system.cpu0.fuPool.FUList4.opList15]
515 type=OpDesc
516 eventq_index=0
517 opClass=SimdFloatDiv
518 opLat=3
519 pipelined=true
520
521 [system.cpu0.fuPool.FUList4.opList16]
522 type=OpDesc
523 eventq_index=0
524 opClass=SimdFloatMisc
525 opLat=3
526 pipelined=true
527
528 [system.cpu0.fuPool.FUList4.opList17]
529 type=OpDesc
530 eventq_index=0
531 opClass=SimdFloatMult
532 opLat=3
533 pipelined=true
534
535 [system.cpu0.fuPool.FUList4.opList18]
536 type=OpDesc
537 eventq_index=0
538 opClass=SimdFloatMultAcc
539 opLat=1
540 pipelined=true
541
542 [system.cpu0.fuPool.FUList4.opList19]
543 type=OpDesc
544 eventq_index=0
545 opClass=SimdFloatSqrt
546 opLat=9
547 pipelined=true
548
549 [system.cpu0.fuPool.FUList4.opList20]
550 type=OpDesc
551 eventq_index=0
552 opClass=FloatAdd
553 opLat=5
554 pipelined=true
555
556 [system.cpu0.fuPool.FUList4.opList21]
557 type=OpDesc
558 eventq_index=0
559 opClass=FloatCmp
560 opLat=5
561 pipelined=true
562
563 [system.cpu0.fuPool.FUList4.opList22]
564 type=OpDesc
565 eventq_index=0
566 opClass=FloatCvt
567 opLat=5
568 pipelined=true
569
570 [system.cpu0.fuPool.FUList4.opList23]
571 type=OpDesc
572 eventq_index=0
573 opClass=FloatDiv
574 opLat=9
575 pipelined=false
576
577 [system.cpu0.fuPool.FUList4.opList24]
578 type=OpDesc
579 eventq_index=0
580 opClass=FloatSqrt
581 opLat=33
582 pipelined=false
583
584 [system.cpu0.fuPool.FUList4.opList25]
585 type=OpDesc
586 eventq_index=0
587 opClass=FloatMult
588 opLat=4
589 pipelined=true
590
591 [system.cpu0.icache]
592 type=Cache
593 children=tags
594 addr_ranges=0:18446744073709551615:0:0:0:0
595 assoc=2
596 clk_domain=system.cpu_clk_domain
597 clusivity=mostly_incl
598 default_p_state=UNDEFINED
599 demand_mshr_reserve=1
600 eventq_index=0
601 hit_latency=1
602 is_read_only=true
603 max_miss_count=0
604 mshrs=2
605 p_state_clk_gate_bins=20
606 p_state_clk_gate_max=1000000000000
607 p_state_clk_gate_min=1000
608 power_model=Null
609 prefetch_on_access=false
610 prefetcher=Null
611 response_latency=1
612 sequential_access=false
613 size=32768
614 system=system
615 tags=system.cpu0.icache.tags
616 tgts_per_mshr=8
617 write_buffers=8
618 writeback_clean=true
619 cpu_side=system.cpu0.icache_port
620 mem_side=system.cpu0.toL2Bus.slave[0]
621
622 [system.cpu0.icache.tags]
623 type=LRU
624 assoc=2
625 block_size=64
626 clk_domain=system.cpu_clk_domain
627 default_p_state=UNDEFINED
628 eventq_index=0
629 hit_latency=1
630 p_state_clk_gate_bins=20
631 p_state_clk_gate_max=1000000000000
632 p_state_clk_gate_min=1000
633 power_model=Null
634 sequential_access=false
635 size=32768
636
637 [system.cpu0.interrupts]
638 type=ArmInterrupts
639 eventq_index=0
640
641 [system.cpu0.isa]
642 type=ArmISA
643 decoderFlavour=Generic
644 eventq_index=0
645 fpsid=1090793632
646 id_aa64afr0_el1=0
647 id_aa64afr1_el1=0
648 id_aa64dfr0_el1=1052678
649 id_aa64dfr1_el1=0
650 id_aa64isar0_el1=0
651 id_aa64isar1_el1=0
652 id_aa64mmfr0_el1=15728642
653 id_aa64mmfr1_el1=0
654 id_aa64pfr0_el1=34
655 id_aa64pfr1_el1=0
656 id_isar0=34607377
657 id_isar1=34677009
658 id_isar2=555950401
659 id_isar3=17899825
660 id_isar4=268501314
661 id_isar5=0
662 id_mmfr0=270536963
663 id_mmfr1=0
664 id_mmfr2=19070976
665 id_mmfr3=34611729
666 id_pfr0=49
667 id_pfr1=4113
668 midr=1091551472
669 pmu=Null
670 system=system
671
672 [system.cpu0.istage2_mmu]
673 type=ArmStage2MMU
674 children=stage2_tlb
675 eventq_index=0
676 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
677 sys=system
678 tlb=system.cpu0.itb
679
680 [system.cpu0.istage2_mmu.stage2_tlb]
681 type=ArmTLB
682 children=walker
683 eventq_index=0
684 is_stage2=true
685 size=32
686 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
687
688 [system.cpu0.istage2_mmu.stage2_tlb.walker]
689 type=ArmTableWalker
690 clk_domain=system.cpu_clk_domain
691 default_p_state=UNDEFINED
692 eventq_index=0
693 is_stage2=true
694 num_squash_per_cycle=2
695 p_state_clk_gate_bins=20
696 p_state_clk_gate_max=1000000000000
697 p_state_clk_gate_min=1000
698 power_model=Null
699 sys=system
700
701 [system.cpu0.itb]
702 type=ArmTLB
703 children=walker
704 eventq_index=0
705 is_stage2=false
706 size=64
707 walker=system.cpu0.itb.walker
708
709 [system.cpu0.itb.walker]
710 type=ArmTableWalker
711 clk_domain=system.cpu_clk_domain
712 default_p_state=UNDEFINED
713 eventq_index=0
714 is_stage2=false
715 num_squash_per_cycle=2
716 p_state_clk_gate_bins=20
717 p_state_clk_gate_max=1000000000000
718 p_state_clk_gate_min=1000
719 power_model=Null
720 sys=system
721 port=system.cpu0.toL2Bus.slave[2]
722
723 [system.cpu0.l2cache]
724 type=Cache
725 children=prefetcher tags
726 addr_ranges=0:18446744073709551615:0:0:0:0
727 assoc=16
728 clk_domain=system.cpu_clk_domain
729 clusivity=mostly_excl
730 default_p_state=UNDEFINED
731 demand_mshr_reserve=1
732 eventq_index=0
733 hit_latency=12
734 is_read_only=false
735 max_miss_count=0
736 mshrs=16
737 p_state_clk_gate_bins=20
738 p_state_clk_gate_max=1000000000000
739 p_state_clk_gate_min=1000
740 power_model=Null
741 prefetch_on_access=true
742 prefetcher=system.cpu0.l2cache.prefetcher
743 response_latency=12
744 sequential_access=false
745 size=1048576
746 system=system
747 tags=system.cpu0.l2cache.tags
748 tgts_per_mshr=8
749 write_buffers=8
750 writeback_clean=false
751 cpu_side=system.cpu0.toL2Bus.master[0]
752 mem_side=system.toL2Bus.slave[0]
753
754 [system.cpu0.l2cache.prefetcher]
755 type=StridePrefetcher
756 cache_snoop=false
757 clk_domain=system.cpu_clk_domain
758 default_p_state=UNDEFINED
759 degree=8
760 eventq_index=0
761 latency=1
762 max_conf=7
763 min_conf=0
764 on_data=true
765 on_inst=true
766 on_miss=false
767 on_read=true
768 on_write=true
769 p_state_clk_gate_bins=20
770 p_state_clk_gate_max=1000000000000
771 p_state_clk_gate_min=1000
772 power_model=Null
773 queue_filter=true
774 queue_size=32
775 queue_squash=true
776 start_conf=4
777 sys=system
778 table_assoc=4
779 table_sets=16
780 tag_prefetch=true
781 thresh_conf=4
782 use_master_id=true
783
784 [system.cpu0.l2cache.tags]
785 type=RandomRepl
786 assoc=16
787 block_size=64
788 clk_domain=system.cpu_clk_domain
789 default_p_state=UNDEFINED
790 eventq_index=0
791 hit_latency=12
792 p_state_clk_gate_bins=20
793 p_state_clk_gate_max=1000000000000
794 p_state_clk_gate_min=1000
795 power_model=Null
796 sequential_access=false
797 size=1048576
798
799 [system.cpu0.toL2Bus]
800 type=CoherentXBar
801 children=snoop_filter
802 clk_domain=system.cpu_clk_domain
803 default_p_state=UNDEFINED
804 eventq_index=0
805 forward_latency=0
806 frontend_latency=1
807 p_state_clk_gate_bins=20
808 p_state_clk_gate_max=1000000000000
809 p_state_clk_gate_min=1000
810 point_of_coherency=false
811 power_model=Null
812 response_latency=1
813 snoop_filter=system.cpu0.toL2Bus.snoop_filter
814 snoop_response_latency=1
815 system=system
816 use_default_range=false
817 width=32
818 master=system.cpu0.l2cache.cpu_side
819 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
820
821 [system.cpu0.toL2Bus.snoop_filter]
822 type=SnoopFilter
823 eventq_index=0
824 lookup_latency=0
825 max_capacity=8388608
826 system=system
827
828 [system.cpu0.tracer]
829 type=ExeTracer
830 eventq_index=0
831
832 [system.cpu1]
833 type=DerivO3CPU
834 children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
835 LFSTSize=1024
836 LQEntries=16
837 LSQCheckLoads=true
838 LSQDepCheckShift=0
839 SQEntries=16
840 SSITSize=1024
841 activity=0
842 backComSize=5
843 branchPred=system.cpu1.branchPred
844 cachePorts=200
845 checker=Null
846 clk_domain=system.cpu_clk_domain
847 commitToDecodeDelay=1
848 commitToFetchDelay=1
849 commitToIEWDelay=1
850 commitToRenameDelay=1
851 commitWidth=8
852 cpu_id=1
853 decodeToFetchDelay=1
854 decodeToRenameDelay=2
855 decodeWidth=3
856 default_p_state=UNDEFINED
857 dispatchWidth=6
858 do_checkpoint_insts=true
859 do_quiesce=true
860 do_statistics_insts=true
861 dstage2_mmu=system.cpu1.dstage2_mmu
862 dtb=system.cpu1.dtb
863 eventq_index=0
864 fetchBufferSize=16
865 fetchQueueSize=32
866 fetchToDecodeDelay=3
867 fetchTrapLatency=1
868 fetchWidth=3
869 forwardComSize=5
870 fuPool=system.cpu1.fuPool
871 function_trace=false
872 function_trace_start=0
873 iewToCommitDelay=1
874 iewToDecodeDelay=1
875 iewToFetchDelay=1
876 iewToRenameDelay=1
877 interrupts=system.cpu1.interrupts
878 isa=system.cpu1.isa
879 issueToExecuteDelay=1
880 issueWidth=8
881 istage2_mmu=system.cpu1.istage2_mmu
882 itb=system.cpu1.itb
883 max_insts_all_threads=0
884 max_insts_any_thread=0
885 max_loads_all_threads=0
886 max_loads_any_thread=0
887 needsTSO=false
888 numIQEntries=32
889 numPhysCCRegs=640
890 numPhysFloatRegs=192
891 numPhysIntRegs=128
892 numROBEntries=40
893 numRobs=1
894 numThreads=1
895 p_state_clk_gate_bins=20
896 p_state_clk_gate_max=1000000000000
897 p_state_clk_gate_min=1000
898 power_model=Null
899 profile=0
900 progress_interval=0
901 renameToDecodeDelay=1
902 renameToFetchDelay=1
903 renameToIEWDelay=1
904 renameToROBDelay=1
905 renameWidth=3
906 simpoint_start_insts=
907 smtCommitPolicy=RoundRobin
908 smtFetchPolicy=SingleThread
909 smtIQPolicy=Partitioned
910 smtIQThreshold=100
911 smtLSQPolicy=Partitioned
912 smtLSQThreshold=100
913 smtNumFetchingThreads=1
914 smtROBPolicy=Partitioned
915 smtROBThreshold=100
916 socket_id=0
917 squashWidth=8
918 store_set_clear_period=250000
919 switched_out=false
920 system=system
921 tracer=system.cpu1.tracer
922 trapLatency=13
923 wbWidth=8
924 workload=
925 dcache_port=system.cpu1.dcache.cpu_side
926 icache_port=system.cpu1.icache.cpu_side
927
928 [system.cpu1.branchPred]
929 type=BiModeBP
930 BTBEntries=2048
931 BTBTagSize=18
932 RASSize=16
933 choiceCtrBits=2
934 choicePredictorSize=8192
935 eventq_index=0
936 globalCtrBits=2
937 globalPredictorSize=8192
938 indirectHashGHR=true
939 indirectHashTargets=true
940 indirectPathLength=3
941 indirectSets=256
942 indirectTagSize=16
943 indirectWays=2
944 instShiftAmt=2
945 numThreads=1
946 useIndirect=true
947
948 [system.cpu1.dcache]
949 type=Cache
950 children=tags
951 addr_ranges=0:18446744073709551615:0:0:0:0
952 assoc=2
953 clk_domain=system.cpu_clk_domain
954 clusivity=mostly_incl
955 default_p_state=UNDEFINED
956 demand_mshr_reserve=1
957 eventq_index=0
958 hit_latency=2
959 is_read_only=false
960 max_miss_count=0
961 mshrs=6
962 p_state_clk_gate_bins=20
963 p_state_clk_gate_max=1000000000000
964 p_state_clk_gate_min=1000
965 power_model=Null
966 prefetch_on_access=false
967 prefetcher=Null
968 response_latency=2
969 sequential_access=false
970 size=32768
971 system=system
972 tags=system.cpu1.dcache.tags
973 tgts_per_mshr=8
974 write_buffers=16
975 writeback_clean=true
976 cpu_side=system.cpu1.dcache_port
977 mem_side=system.cpu1.toL2Bus.slave[1]
978
979 [system.cpu1.dcache.tags]
980 type=LRU
981 assoc=2
982 block_size=64
983 clk_domain=system.cpu_clk_domain
984 default_p_state=UNDEFINED
985 eventq_index=0
986 hit_latency=2
987 p_state_clk_gate_bins=20
988 p_state_clk_gate_max=1000000000000
989 p_state_clk_gate_min=1000
990 power_model=Null
991 sequential_access=false
992 size=32768
993
994 [system.cpu1.dstage2_mmu]
995 type=ArmStage2MMU
996 children=stage2_tlb
997 eventq_index=0
998 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
999 sys=system
1000 tlb=system.cpu1.dtb
1001
1002 [system.cpu1.dstage2_mmu.stage2_tlb]
1003 type=ArmTLB
1004 children=walker
1005 eventq_index=0
1006 is_stage2=true
1007 size=32
1008 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
1009
1010 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
1011 type=ArmTableWalker
1012 clk_domain=system.cpu_clk_domain
1013 default_p_state=UNDEFINED
1014 eventq_index=0
1015 is_stage2=true
1016 num_squash_per_cycle=2
1017 p_state_clk_gate_bins=20
1018 p_state_clk_gate_max=1000000000000
1019 p_state_clk_gate_min=1000
1020 power_model=Null
1021 sys=system
1022
1023 [system.cpu1.dtb]
1024 type=ArmTLB
1025 children=walker
1026 eventq_index=0
1027 is_stage2=false
1028 size=64
1029 walker=system.cpu1.dtb.walker
1030
1031 [system.cpu1.dtb.walker]
1032 type=ArmTableWalker
1033 clk_domain=system.cpu_clk_domain
1034 default_p_state=UNDEFINED
1035 eventq_index=0
1036 is_stage2=false
1037 num_squash_per_cycle=2
1038 p_state_clk_gate_bins=20
1039 p_state_clk_gate_max=1000000000000
1040 p_state_clk_gate_min=1000
1041 power_model=Null
1042 sys=system
1043 port=system.cpu1.toL2Bus.slave[3]
1044
1045 [system.cpu1.fuPool]
1046 type=FUPool
1047 children=FUList0 FUList1 FUList2 FUList3 FUList4
1048 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
1049 eventq_index=0
1050
1051 [system.cpu1.fuPool.FUList0]
1052 type=FUDesc
1053 children=opList
1054 count=2
1055 eventq_index=0
1056 opList=system.cpu1.fuPool.FUList0.opList
1057
1058 [system.cpu1.fuPool.FUList0.opList]
1059 type=OpDesc
1060 eventq_index=0
1061 opClass=IntAlu
1062 opLat=1
1063 pipelined=true
1064
1065 [system.cpu1.fuPool.FUList1]
1066 type=FUDesc
1067 children=opList0 opList1 opList2
1068 count=1
1069 eventq_index=0
1070 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2
1071
1072 [system.cpu1.fuPool.FUList1.opList0]
1073 type=OpDesc
1074 eventq_index=0
1075 opClass=IntMult
1076 opLat=3
1077 pipelined=true
1078
1079 [system.cpu1.fuPool.FUList1.opList1]
1080 type=OpDesc
1081 eventq_index=0
1082 opClass=IntDiv
1083 opLat=12
1084 pipelined=false
1085
1086 [system.cpu1.fuPool.FUList1.opList2]
1087 type=OpDesc
1088 eventq_index=0
1089 opClass=IprAccess
1090 opLat=3
1091 pipelined=true
1092
1093 [system.cpu1.fuPool.FUList2]
1094 type=FUDesc
1095 children=opList
1096 count=1
1097 eventq_index=0
1098 opList=system.cpu1.fuPool.FUList2.opList
1099
1100 [system.cpu1.fuPool.FUList2.opList]
1101 type=OpDesc
1102 eventq_index=0
1103 opClass=MemRead
1104 opLat=2
1105 pipelined=true
1106
1107 [system.cpu1.fuPool.FUList3]
1108 type=FUDesc
1109 children=opList
1110 count=1
1111 eventq_index=0
1112 opList=system.cpu1.fuPool.FUList3.opList
1113
1114 [system.cpu1.fuPool.FUList3.opList]
1115 type=OpDesc
1116 eventq_index=0
1117 opClass=MemWrite
1118 opLat=2
1119 pipelined=true
1120
1121 [system.cpu1.fuPool.FUList4]
1122 type=FUDesc
1123 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
1124 count=2
1125 eventq_index=0
1126 opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
1127
1128 [system.cpu1.fuPool.FUList4.opList00]
1129 type=OpDesc
1130 eventq_index=0
1131 opClass=SimdAdd
1132 opLat=4
1133 pipelined=true
1134
1135 [system.cpu1.fuPool.FUList4.opList01]
1136 type=OpDesc
1137 eventq_index=0
1138 opClass=SimdAddAcc
1139 opLat=4
1140 pipelined=true
1141
1142 [system.cpu1.fuPool.FUList4.opList02]
1143 type=OpDesc
1144 eventq_index=0
1145 opClass=SimdAlu
1146 opLat=4
1147 pipelined=true
1148
1149 [system.cpu1.fuPool.FUList4.opList03]
1150 type=OpDesc
1151 eventq_index=0
1152 opClass=SimdCmp
1153 opLat=4
1154 pipelined=true
1155
1156 [system.cpu1.fuPool.FUList4.opList04]
1157 type=OpDesc
1158 eventq_index=0
1159 opClass=SimdCvt
1160 opLat=3
1161 pipelined=true
1162
1163 [system.cpu1.fuPool.FUList4.opList05]
1164 type=OpDesc
1165 eventq_index=0
1166 opClass=SimdMisc
1167 opLat=3
1168 pipelined=true
1169
1170 [system.cpu1.fuPool.FUList4.opList06]
1171 type=OpDesc
1172 eventq_index=0
1173 opClass=SimdMult
1174 opLat=5
1175 pipelined=true
1176
1177 [system.cpu1.fuPool.FUList4.opList07]
1178 type=OpDesc
1179 eventq_index=0
1180 opClass=SimdMultAcc
1181 opLat=5
1182 pipelined=true
1183
1184 [system.cpu1.fuPool.FUList4.opList08]
1185 type=OpDesc
1186 eventq_index=0
1187 opClass=SimdShift
1188 opLat=3
1189 pipelined=true
1190
1191 [system.cpu1.fuPool.FUList4.opList09]
1192 type=OpDesc
1193 eventq_index=0
1194 opClass=SimdShiftAcc
1195 opLat=3
1196 pipelined=true
1197
1198 [system.cpu1.fuPool.FUList4.opList10]
1199 type=OpDesc
1200 eventq_index=0
1201 opClass=SimdSqrt
1202 opLat=9
1203 pipelined=true
1204
1205 [system.cpu1.fuPool.FUList4.opList11]
1206 type=OpDesc
1207 eventq_index=0
1208 opClass=SimdFloatAdd
1209 opLat=5
1210 pipelined=true
1211
1212 [system.cpu1.fuPool.FUList4.opList12]
1213 type=OpDesc
1214 eventq_index=0
1215 opClass=SimdFloatAlu
1216 opLat=5
1217 pipelined=true
1218
1219 [system.cpu1.fuPool.FUList4.opList13]
1220 type=OpDesc
1221 eventq_index=0
1222 opClass=SimdFloatCmp
1223 opLat=3
1224 pipelined=true
1225
1226 [system.cpu1.fuPool.FUList4.opList14]
1227 type=OpDesc
1228 eventq_index=0
1229 opClass=SimdFloatCvt
1230 opLat=3
1231 pipelined=true
1232
1233 [system.cpu1.fuPool.FUList4.opList15]
1234 type=OpDesc
1235 eventq_index=0
1236 opClass=SimdFloatDiv
1237 opLat=3
1238 pipelined=true
1239
1240 [system.cpu1.fuPool.FUList4.opList16]
1241 type=OpDesc
1242 eventq_index=0
1243 opClass=SimdFloatMisc
1244 opLat=3
1245 pipelined=true
1246
1247 [system.cpu1.fuPool.FUList4.opList17]
1248 type=OpDesc
1249 eventq_index=0
1250 opClass=SimdFloatMult
1251 opLat=3
1252 pipelined=true
1253
1254 [system.cpu1.fuPool.FUList4.opList18]
1255 type=OpDesc
1256 eventq_index=0
1257 opClass=SimdFloatMultAcc
1258 opLat=1
1259 pipelined=true
1260
1261 [system.cpu1.fuPool.FUList4.opList19]
1262 type=OpDesc
1263 eventq_index=0
1264 opClass=SimdFloatSqrt
1265 opLat=9
1266 pipelined=true
1267
1268 [system.cpu1.fuPool.FUList4.opList20]
1269 type=OpDesc
1270 eventq_index=0
1271 opClass=FloatAdd
1272 opLat=5
1273 pipelined=true
1274
1275 [system.cpu1.fuPool.FUList4.opList21]
1276 type=OpDesc
1277 eventq_index=0
1278 opClass=FloatCmp
1279 opLat=5
1280 pipelined=true
1281
1282 [system.cpu1.fuPool.FUList4.opList22]
1283 type=OpDesc
1284 eventq_index=0
1285 opClass=FloatCvt
1286 opLat=5
1287 pipelined=true
1288
1289 [system.cpu1.fuPool.FUList4.opList23]
1290 type=OpDesc
1291 eventq_index=0
1292 opClass=FloatDiv
1293 opLat=9
1294 pipelined=false
1295
1296 [system.cpu1.fuPool.FUList4.opList24]
1297 type=OpDesc
1298 eventq_index=0
1299 opClass=FloatSqrt
1300 opLat=33
1301 pipelined=false
1302
1303 [system.cpu1.fuPool.FUList4.opList25]
1304 type=OpDesc
1305 eventq_index=0
1306 opClass=FloatMult
1307 opLat=4
1308 pipelined=true
1309
1310 [system.cpu1.icache]
1311 type=Cache
1312 children=tags
1313 addr_ranges=0:18446744073709551615:0:0:0:0
1314 assoc=2
1315 clk_domain=system.cpu_clk_domain
1316 clusivity=mostly_incl
1317 default_p_state=UNDEFINED
1318 demand_mshr_reserve=1
1319 eventq_index=0
1320 hit_latency=1
1321 is_read_only=true
1322 max_miss_count=0
1323 mshrs=2
1324 p_state_clk_gate_bins=20
1325 p_state_clk_gate_max=1000000000000
1326 p_state_clk_gate_min=1000
1327 power_model=Null
1328 prefetch_on_access=false
1329 prefetcher=Null
1330 response_latency=1
1331 sequential_access=false
1332 size=32768
1333 system=system
1334 tags=system.cpu1.icache.tags
1335 tgts_per_mshr=8
1336 write_buffers=8
1337 writeback_clean=true
1338 cpu_side=system.cpu1.icache_port
1339 mem_side=system.cpu1.toL2Bus.slave[0]
1340
1341 [system.cpu1.icache.tags]
1342 type=LRU
1343 assoc=2
1344 block_size=64
1345 clk_domain=system.cpu_clk_domain
1346 default_p_state=UNDEFINED
1347 eventq_index=0
1348 hit_latency=1
1349 p_state_clk_gate_bins=20
1350 p_state_clk_gate_max=1000000000000
1351 p_state_clk_gate_min=1000
1352 power_model=Null
1353 sequential_access=false
1354 size=32768
1355
1356 [system.cpu1.interrupts]
1357 type=ArmInterrupts
1358 eventq_index=0
1359
1360 [system.cpu1.isa]
1361 type=ArmISA
1362 decoderFlavour=Generic
1363 eventq_index=0
1364 fpsid=1090793632
1365 id_aa64afr0_el1=0
1366 id_aa64afr1_el1=0
1367 id_aa64dfr0_el1=1052678
1368 id_aa64dfr1_el1=0
1369 id_aa64isar0_el1=0
1370 id_aa64isar1_el1=0
1371 id_aa64mmfr0_el1=15728642
1372 id_aa64mmfr1_el1=0
1373 id_aa64pfr0_el1=34
1374 id_aa64pfr1_el1=0
1375 id_isar0=34607377
1376 id_isar1=34677009
1377 id_isar2=555950401
1378 id_isar3=17899825
1379 id_isar4=268501314
1380 id_isar5=0
1381 id_mmfr0=270536963
1382 id_mmfr1=0
1383 id_mmfr2=19070976
1384 id_mmfr3=34611729
1385 id_pfr0=49
1386 id_pfr1=4113
1387 midr=1091551472
1388 pmu=Null
1389 system=system
1390
1391 [system.cpu1.istage2_mmu]
1392 type=ArmStage2MMU
1393 children=stage2_tlb
1394 eventq_index=0
1395 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1396 sys=system
1397 tlb=system.cpu1.itb
1398
1399 [system.cpu1.istage2_mmu.stage2_tlb]
1400 type=ArmTLB
1401 children=walker
1402 eventq_index=0
1403 is_stage2=true
1404 size=32
1405 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1406
1407 [system.cpu1.istage2_mmu.stage2_tlb.walker]
1408 type=ArmTableWalker
1409 clk_domain=system.cpu_clk_domain
1410 default_p_state=UNDEFINED
1411 eventq_index=0
1412 is_stage2=true
1413 num_squash_per_cycle=2
1414 p_state_clk_gate_bins=20
1415 p_state_clk_gate_max=1000000000000
1416 p_state_clk_gate_min=1000
1417 power_model=Null
1418 sys=system
1419
1420 [system.cpu1.itb]
1421 type=ArmTLB
1422 children=walker
1423 eventq_index=0
1424 is_stage2=false
1425 size=64
1426 walker=system.cpu1.itb.walker
1427
1428 [system.cpu1.itb.walker]
1429 type=ArmTableWalker
1430 clk_domain=system.cpu_clk_domain
1431 default_p_state=UNDEFINED
1432 eventq_index=0
1433 is_stage2=false
1434 num_squash_per_cycle=2
1435 p_state_clk_gate_bins=20
1436 p_state_clk_gate_max=1000000000000
1437 p_state_clk_gate_min=1000
1438 power_model=Null
1439 sys=system
1440 port=system.cpu1.toL2Bus.slave[2]
1441
1442 [system.cpu1.l2cache]
1443 type=Cache
1444 children=prefetcher tags
1445 addr_ranges=0:18446744073709551615:0:0:0:0
1446 assoc=16
1447 clk_domain=system.cpu_clk_domain
1448 clusivity=mostly_excl
1449 default_p_state=UNDEFINED
1450 demand_mshr_reserve=1
1451 eventq_index=0
1452 hit_latency=12
1453 is_read_only=false
1454 max_miss_count=0
1455 mshrs=16
1456 p_state_clk_gate_bins=20
1457 p_state_clk_gate_max=1000000000000
1458 p_state_clk_gate_min=1000
1459 power_model=Null
1460 prefetch_on_access=true
1461 prefetcher=system.cpu1.l2cache.prefetcher
1462 response_latency=12
1463 sequential_access=false
1464 size=1048576
1465 system=system
1466 tags=system.cpu1.l2cache.tags
1467 tgts_per_mshr=8
1468 write_buffers=8
1469 writeback_clean=false
1470 cpu_side=system.cpu1.toL2Bus.master[0]
1471 mem_side=system.toL2Bus.slave[1]
1472
1473 [system.cpu1.l2cache.prefetcher]
1474 type=StridePrefetcher
1475 cache_snoop=false
1476 clk_domain=system.cpu_clk_domain
1477 default_p_state=UNDEFINED
1478 degree=8
1479 eventq_index=0
1480 latency=1
1481 max_conf=7
1482 min_conf=0
1483 on_data=true
1484 on_inst=true
1485 on_miss=false
1486 on_read=true
1487 on_write=true
1488 p_state_clk_gate_bins=20
1489 p_state_clk_gate_max=1000000000000
1490 p_state_clk_gate_min=1000
1491 power_model=Null
1492 queue_filter=true
1493 queue_size=32
1494 queue_squash=true
1495 start_conf=4
1496 sys=system
1497 table_assoc=4
1498 table_sets=16
1499 tag_prefetch=true
1500 thresh_conf=4
1501 use_master_id=true
1502
1503 [system.cpu1.l2cache.tags]
1504 type=RandomRepl
1505 assoc=16
1506 block_size=64
1507 clk_domain=system.cpu_clk_domain
1508 default_p_state=UNDEFINED
1509 eventq_index=0
1510 hit_latency=12
1511 p_state_clk_gate_bins=20
1512 p_state_clk_gate_max=1000000000000
1513 p_state_clk_gate_min=1000
1514 power_model=Null
1515 sequential_access=false
1516 size=1048576
1517
1518 [system.cpu1.toL2Bus]
1519 type=CoherentXBar
1520 children=snoop_filter
1521 clk_domain=system.cpu_clk_domain
1522 default_p_state=UNDEFINED
1523 eventq_index=0
1524 forward_latency=0
1525 frontend_latency=1
1526 p_state_clk_gate_bins=20
1527 p_state_clk_gate_max=1000000000000
1528 p_state_clk_gate_min=1000
1529 point_of_coherency=false
1530 power_model=Null
1531 response_latency=1
1532 snoop_filter=system.cpu1.toL2Bus.snoop_filter
1533 snoop_response_latency=1
1534 system=system
1535 use_default_range=false
1536 width=32
1537 master=system.cpu1.l2cache.cpu_side
1538 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1539
1540 [system.cpu1.toL2Bus.snoop_filter]
1541 type=SnoopFilter
1542 eventq_index=0
1543 lookup_latency=0
1544 max_capacity=8388608
1545 system=system
1546
1547 [system.cpu1.tracer]
1548 type=ExeTracer
1549 eventq_index=0
1550
1551 [system.cpu_clk_domain]
1552 type=SrcClockDomain
1553 clock=500
1554 domain_id=-1
1555 eventq_index=0
1556 init_perf_level=0
1557 voltage_domain=system.voltage_domain
1558
1559 [system.dvfs_handler]
1560 type=DVFSHandler
1561 domains=
1562 enable=false
1563 eventq_index=0
1564 sys_clk_domain=system.clk_domain
1565 transition_latency=100000000
1566
1567 [system.intrctrl]
1568 type=IntrControl
1569 eventq_index=0
1570 sys=system
1571
1572 [system.iobus]
1573 type=NoncoherentXBar
1574 clk_domain=system.clk_domain
1575 default_p_state=UNDEFINED
1576 eventq_index=0
1577 forward_latency=1
1578 frontend_latency=2
1579 p_state_clk_gate_bins=20
1580 p_state_clk_gate_max=1000000000000
1581 p_state_clk_gate_min=1000
1582 power_model=Null
1583 response_latency=2
1584 use_default_range=false
1585 width=16
1586 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
1587 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
1588
1589 [system.iocache]
1590 type=Cache
1591 children=tags
1592 addr_ranges=2147483648:2415919103:0:0:0:0
1593 assoc=8
1594 clk_domain=system.clk_domain
1595 clusivity=mostly_incl
1596 default_p_state=UNDEFINED
1597 demand_mshr_reserve=1
1598 eventq_index=0
1599 hit_latency=50
1600 is_read_only=false
1601 max_miss_count=0
1602 mshrs=20
1603 p_state_clk_gate_bins=20
1604 p_state_clk_gate_max=1000000000000
1605 p_state_clk_gate_min=1000
1606 power_model=Null
1607 prefetch_on_access=false
1608 prefetcher=Null
1609 response_latency=50
1610 sequential_access=false
1611 size=1024
1612 system=system
1613 tags=system.iocache.tags
1614 tgts_per_mshr=12
1615 write_buffers=8
1616 writeback_clean=false
1617 cpu_side=system.iobus.master[25]
1618 mem_side=system.membus.slave[3]
1619
1620 [system.iocache.tags]
1621 type=LRU
1622 assoc=8
1623 block_size=64
1624 clk_domain=system.clk_domain
1625 default_p_state=UNDEFINED
1626 eventq_index=0
1627 hit_latency=50
1628 p_state_clk_gate_bins=20
1629 p_state_clk_gate_max=1000000000000
1630 p_state_clk_gate_min=1000
1631 power_model=Null
1632 sequential_access=false
1633 size=1024
1634
1635 [system.l2c]
1636 type=Cache
1637 children=tags
1638 addr_ranges=0:18446744073709551615:0:0:0:0
1639 assoc=8
1640 clk_domain=system.cpu_clk_domain
1641 clusivity=mostly_incl
1642 default_p_state=UNDEFINED
1643 demand_mshr_reserve=1
1644 eventq_index=0
1645 hit_latency=20
1646 is_read_only=false
1647 max_miss_count=0
1648 mshrs=20
1649 p_state_clk_gate_bins=20
1650 p_state_clk_gate_max=1000000000000
1651 p_state_clk_gate_min=1000
1652 power_model=Null
1653 prefetch_on_access=false
1654 prefetcher=Null
1655 response_latency=20
1656 sequential_access=false
1657 size=4194304
1658 system=system
1659 tags=system.l2c.tags
1660 tgts_per_mshr=12
1661 write_buffers=8
1662 writeback_clean=false
1663 cpu_side=system.toL2Bus.master[0]
1664 mem_side=system.membus.slave[2]
1665
1666 [system.l2c.tags]
1667 type=LRU
1668 assoc=8
1669 block_size=64
1670 clk_domain=system.cpu_clk_domain
1671 default_p_state=UNDEFINED
1672 eventq_index=0
1673 hit_latency=20
1674 p_state_clk_gate_bins=20
1675 p_state_clk_gate_max=1000000000000
1676 p_state_clk_gate_min=1000
1677 power_model=Null
1678 sequential_access=false
1679 size=4194304
1680
1681 [system.membus]
1682 type=CoherentXBar
1683 children=badaddr_responder snoop_filter
1684 clk_domain=system.clk_domain
1685 default_p_state=UNDEFINED
1686 eventq_index=0
1687 forward_latency=4
1688 frontend_latency=3
1689 p_state_clk_gate_bins=20
1690 p_state_clk_gate_max=1000000000000
1691 p_state_clk_gate_min=1000
1692 point_of_coherency=true
1693 power_model=Null
1694 response_latency=2
1695 snoop_filter=system.membus.snoop_filter
1696 snoop_response_latency=4
1697 system=system
1698 use_default_range=false
1699 width=16
1700 default=system.membus.badaddr_responder.pio
1701 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1702 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1703
1704 [system.membus.badaddr_responder]
1705 type=IsaFake
1706 clk_domain=system.clk_domain
1707 default_p_state=UNDEFINED
1708 eventq_index=0
1709 fake_mem=false
1710 p_state_clk_gate_bins=20
1711 p_state_clk_gate_max=1000000000000
1712 p_state_clk_gate_min=1000
1713 pio_addr=0
1714 pio_latency=100000
1715 pio_size=8
1716 power_model=Null
1717 ret_bad_addr=true
1718 ret_data16=65535
1719 ret_data32=4294967295
1720 ret_data64=18446744073709551615
1721 ret_data8=255
1722 system=system
1723 update_data=false
1724 warn_access=warn
1725 pio=system.membus.default
1726
1727 [system.membus.snoop_filter]
1728 type=SnoopFilter
1729 eventq_index=0
1730 lookup_latency=1
1731 max_capacity=8388608
1732 system=system
1733
1734 [system.physmem]
1735 type=DRAMCtrl
1736 IDD0=0.055000
1737 IDD02=0.000000
1738 IDD2N=0.032000
1739 IDD2N2=0.000000
1740 IDD2P0=0.000000
1741 IDD2P02=0.000000
1742 IDD2P1=0.032000
1743 IDD2P12=0.000000
1744 IDD3N=0.038000
1745 IDD3N2=0.000000
1746 IDD3P0=0.000000
1747 IDD3P02=0.000000
1748 IDD3P1=0.038000
1749 IDD3P12=0.000000
1750 IDD4R=0.157000
1751 IDD4R2=0.000000
1752 IDD4W=0.125000
1753 IDD4W2=0.000000
1754 IDD5=0.235000
1755 IDD52=0.000000
1756 IDD6=0.020000
1757 IDD62=0.000000
1758 VDD=1.500000
1759 VDD2=0.000000
1760 activation_limit=4
1761 addr_mapping=RoRaBaCoCh
1762 bank_groups_per_rank=0
1763 banks_per_rank=8
1764 burst_length=8
1765 channels=1
1766 clk_domain=system.clk_domain
1767 conf_table_reported=true
1768 default_p_state=UNDEFINED
1769 device_bus_width=8
1770 device_rowbuffer_size=1024
1771 device_size=536870912
1772 devices_per_rank=8
1773 dll=true
1774 eventq_index=0
1775 in_addr_map=true
1776 kvm_map=true
1777 max_accesses_per_row=16
1778 mem_sched_policy=frfcfs
1779 min_writes_per_switch=16
1780 null=false
1781 p_state_clk_gate_bins=20
1782 p_state_clk_gate_max=1000000000000
1783 p_state_clk_gate_min=1000
1784 page_policy=open_adaptive
1785 power_model=Null
1786 range=2147483648:2415919103:0:0:0:0
1787 ranks_per_channel=2
1788 read_buffer_size=32
1789 static_backend_latency=10000
1790 static_frontend_latency=10000
1791 tBURST=5000
1792 tCCD_L=0
1793 tCK=1250
1794 tCL=13750
1795 tCS=2500
1796 tRAS=35000
1797 tRCD=13750
1798 tREFI=7800000
1799 tRFC=260000
1800 tRP=13750
1801 tRRD=6000
1802 tRRD_L=0
1803 tRTP=7500
1804 tRTW=2500
1805 tWR=15000
1806 tWTR=7500
1807 tXAW=30000
1808 tXP=6000
1809 tXPDLL=0
1810 tXS=270000
1811 tXSDLL=0
1812 write_buffer_size=64
1813 write_high_thresh_perc=85
1814 write_low_thresh_perc=50
1815 port=system.membus.master[5]
1816
1817 [system.realview]
1818 type=RealView
1819 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1820 eventq_index=0
1821 intrctrl=system.intrctrl
1822 system=system
1823
1824 [system.realview.aaci_fake]
1825 type=AmbaFake
1826 amba_id=0
1827 clk_domain=system.clk_domain
1828 default_p_state=UNDEFINED
1829 eventq_index=0
1830 ignore_access=false
1831 p_state_clk_gate_bins=20
1832 p_state_clk_gate_max=1000000000000
1833 p_state_clk_gate_min=1000
1834 pio_addr=470024192
1835 pio_latency=100000
1836 power_model=Null
1837 system=system
1838 pio=system.iobus.master[18]
1839
1840 [system.realview.cf_ctrl]
1841 type=IdeController
1842 BAR0=471465984
1843 BAR0LegacyIO=true
1844 BAR0Size=256
1845 BAR1=471466240
1846 BAR1LegacyIO=true
1847 BAR1Size=4096
1848 BAR2=1
1849 BAR2LegacyIO=false
1850 BAR2Size=8
1851 BAR3=1
1852 BAR3LegacyIO=false
1853 BAR3Size=4
1854 BAR4=1
1855 BAR4LegacyIO=false
1856 BAR4Size=16
1857 BAR5=1
1858 BAR5LegacyIO=false
1859 BAR5Size=0
1860 BIST=0
1861 CacheLineSize=0
1862 CapabilityPtr=0
1863 CardbusCIS=0
1864 ClassCode=1
1865 Command=1
1866 DeviceID=28945
1867 ExpansionROM=0
1868 HeaderType=0
1869 InterruptLine=31
1870 InterruptPin=1
1871 LatencyTimer=0
1872 LegacyIOBase=0
1873 MSICAPBaseOffset=0
1874 MSICAPCapId=0
1875 MSICAPMaskBits=0
1876 MSICAPMsgAddr=0
1877 MSICAPMsgCtrl=0
1878 MSICAPMsgData=0
1879 MSICAPMsgUpperAddr=0
1880 MSICAPNextCapability=0
1881 MSICAPPendingBits=0
1882 MSIXCAPBaseOffset=0
1883 MSIXCAPCapId=0
1884 MSIXCAPNextCapability=0
1885 MSIXMsgCtrl=0
1886 MSIXPbaOffset=0
1887 MSIXTableOffset=0
1888 MaximumLatency=0
1889 MinimumGrant=0
1890 PMCAPBaseOffset=0
1891 PMCAPCapId=0
1892 PMCAPCapabilities=0
1893 PMCAPCtrlStatus=0
1894 PMCAPNextCapability=0
1895 PXCAPBaseOffset=0
1896 PXCAPCapId=0
1897 PXCAPCapabilities=0
1898 PXCAPDevCap2=0
1899 PXCAPDevCapabilities=0
1900 PXCAPDevCtrl=0
1901 PXCAPDevCtrl2=0
1902 PXCAPDevStatus=0
1903 PXCAPLinkCap=0
1904 PXCAPLinkCtrl=0
1905 PXCAPLinkStatus=0
1906 PXCAPNextCapability=0
1907 ProgIF=133
1908 Revision=0
1909 Status=640
1910 SubClassCode=1
1911 SubsystemID=0
1912 SubsystemVendorID=0
1913 VendorID=32902
1914 clk_domain=system.clk_domain
1915 config_latency=20000
1916 ctrl_offset=2
1917 default_p_state=UNDEFINED
1918 disks=
1919 eventq_index=0
1920 host=system.realview.pci_host
1921 io_shift=2
1922 p_state_clk_gate_bins=20
1923 p_state_clk_gate_max=1000000000000
1924 p_state_clk_gate_min=1000
1925 pci_bus=2
1926 pci_dev=0
1927 pci_func=0
1928 pio_latency=30000
1929 power_model=Null
1930 system=system
1931 dma=system.iobus.slave[2]
1932 pio=system.iobus.master[9]
1933
1934 [system.realview.clcd]
1935 type=Pl111
1936 amba_id=1315089
1937 clk_domain=system.clk_domain
1938 default_p_state=UNDEFINED
1939 enable_capture=true
1940 eventq_index=0
1941 gic=system.realview.gic
1942 int_num=46
1943 p_state_clk_gate_bins=20
1944 p_state_clk_gate_max=1000000000000
1945 p_state_clk_gate_min=1000
1946 pio_addr=471793664
1947 pio_latency=10000
1948 pixel_clock=41667
1949 power_model=Null
1950 system=system
1951 vnc=system.vncserver
1952 dma=system.iobus.slave[1]
1953 pio=system.iobus.master[5]
1954
1955 [system.realview.dcc]
1956 type=SubSystem
1957 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1958 eventq_index=0
1959 thermal_domain=Null
1960
1961 [system.realview.dcc.osc_cpu]
1962 type=RealViewOsc
1963 dcc=0
1964 device=0
1965 eventq_index=0
1966 freq=16667
1967 parent=system.realview.realview_io
1968 position=0
1969 site=1
1970 voltage_domain=system.voltage_domain
1971
1972 [system.realview.dcc.osc_ddr]
1973 type=RealViewOsc
1974 dcc=0
1975 device=8
1976 eventq_index=0
1977 freq=25000
1978 parent=system.realview.realview_io
1979 position=0
1980 site=1
1981 voltage_domain=system.voltage_domain
1982
1983 [system.realview.dcc.osc_hsbm]
1984 type=RealViewOsc
1985 dcc=0
1986 device=4
1987 eventq_index=0
1988 freq=25000
1989 parent=system.realview.realview_io
1990 position=0
1991 site=1
1992 voltage_domain=system.voltage_domain
1993
1994 [system.realview.dcc.osc_pxl]
1995 type=RealViewOsc
1996 dcc=0
1997 device=5
1998 eventq_index=0
1999 freq=42105
2000 parent=system.realview.realview_io
2001 position=0
2002 site=1
2003 voltage_domain=system.voltage_domain
2004
2005 [system.realview.dcc.osc_smb]
2006 type=RealViewOsc
2007 dcc=0
2008 device=6
2009 eventq_index=0
2010 freq=20000
2011 parent=system.realview.realview_io
2012 position=0
2013 site=1
2014 voltage_domain=system.voltage_domain
2015
2016 [system.realview.dcc.osc_sys]
2017 type=RealViewOsc
2018 dcc=0
2019 device=7
2020 eventq_index=0
2021 freq=16667
2022 parent=system.realview.realview_io
2023 position=0
2024 site=1
2025 voltage_domain=system.voltage_domain
2026
2027 [system.realview.energy_ctrl]
2028 type=EnergyCtrl
2029 clk_domain=system.clk_domain
2030 default_p_state=UNDEFINED
2031 dvfs_handler=system.dvfs_handler
2032 eventq_index=0
2033 p_state_clk_gate_bins=20
2034 p_state_clk_gate_max=1000000000000
2035 p_state_clk_gate_min=1000
2036 pio_addr=470286336
2037 pio_latency=100000
2038 power_model=Null
2039 system=system
2040 pio=system.iobus.master[22]
2041
2042 [system.realview.ethernet]
2043 type=IGbE
2044 BAR0=0
2045 BAR0LegacyIO=false
2046 BAR0Size=131072
2047 BAR1=0
2048 BAR1LegacyIO=false
2049 BAR1Size=0
2050 BAR2=0
2051 BAR2LegacyIO=false
2052 BAR2Size=0
2053 BAR3=0
2054 BAR3LegacyIO=false
2055 BAR3Size=0
2056 BAR4=0
2057 BAR4LegacyIO=false
2058 BAR4Size=0
2059 BAR5=0
2060 BAR5LegacyIO=false
2061 BAR5Size=0
2062 BIST=0
2063 CacheLineSize=0
2064 CapabilityPtr=0
2065 CardbusCIS=0
2066 ClassCode=2
2067 Command=0
2068 DeviceID=4213
2069 ExpansionROM=0
2070 HeaderType=0
2071 InterruptLine=1
2072 InterruptPin=1
2073 LatencyTimer=0
2074 LegacyIOBase=0
2075 MSICAPBaseOffset=0
2076 MSICAPCapId=0
2077 MSICAPMaskBits=0
2078 MSICAPMsgAddr=0
2079 MSICAPMsgCtrl=0
2080 MSICAPMsgData=0
2081 MSICAPMsgUpperAddr=0
2082 MSICAPNextCapability=0
2083 MSICAPPendingBits=0
2084 MSIXCAPBaseOffset=0
2085 MSIXCAPCapId=0
2086 MSIXCAPNextCapability=0
2087 MSIXMsgCtrl=0
2088 MSIXPbaOffset=0
2089 MSIXTableOffset=0
2090 MaximumLatency=0
2091 MinimumGrant=255
2092 PMCAPBaseOffset=0
2093 PMCAPCapId=0
2094 PMCAPCapabilities=0
2095 PMCAPCtrlStatus=0
2096 PMCAPNextCapability=0
2097 PXCAPBaseOffset=0
2098 PXCAPCapId=0
2099 PXCAPCapabilities=0
2100 PXCAPDevCap2=0
2101 PXCAPDevCapabilities=0
2102 PXCAPDevCtrl=0
2103 PXCAPDevCtrl2=0
2104 PXCAPDevStatus=0
2105 PXCAPLinkCap=0
2106 PXCAPLinkCtrl=0
2107 PXCAPLinkStatus=0
2108 PXCAPNextCapability=0
2109 ProgIF=0
2110 Revision=0
2111 Status=0
2112 SubClassCode=0
2113 SubsystemID=4104
2114 SubsystemVendorID=32902
2115 VendorID=32902
2116 clk_domain=system.clk_domain
2117 config_latency=20000
2118 default_p_state=UNDEFINED
2119 eventq_index=0
2120 fetch_comp_delay=10000
2121 fetch_delay=10000
2122 hardware_address=00:90:00:00:00:01
2123 host=system.realview.pci_host
2124 p_state_clk_gate_bins=20
2125 p_state_clk_gate_max=1000000000000
2126 p_state_clk_gate_min=1000
2127 pci_bus=0
2128 pci_dev=0
2129 pci_func=0
2130 phy_epid=896
2131 phy_pid=680
2132 pio_latency=30000
2133 power_model=Null
2134 rx_desc_cache_size=64
2135 rx_fifo_size=393216
2136 rx_write_delay=0
2137 system=system
2138 tx_desc_cache_size=64
2139 tx_fifo_size=393216
2140 tx_read_delay=0
2141 wb_comp_delay=10000
2142 wb_delay=10000
2143 dma=system.iobus.slave[4]
2144 pio=system.iobus.master[24]
2145
2146 [system.realview.generic_timer]
2147 type=GenericTimer
2148 eventq_index=0
2149 gic=system.realview.gic
2150 int_phys=29
2151 int_virt=27
2152 system=system
2153
2154 [system.realview.gic]
2155 type=Pl390
2156 clk_domain=system.clk_domain
2157 cpu_addr=738205696
2158 cpu_pio_delay=10000
2159 default_p_state=UNDEFINED
2160 dist_addr=738201600
2161 dist_pio_delay=10000
2162 eventq_index=0
2163 gem5_extensions=false
2164 int_latency=10000
2165 it_lines=128
2166 p_state_clk_gate_bins=20
2167 p_state_clk_gate_max=1000000000000
2168 p_state_clk_gate_min=1000
2169 platform=system.realview
2170 power_model=Null
2171 system=system
2172 pio=system.membus.master[2]
2173
2174 [system.realview.hdlcd]
2175 type=HDLcd
2176 amba_id=1314816
2177 clk_domain=system.clk_domain
2178 default_p_state=UNDEFINED
2179 enable_capture=true
2180 eventq_index=0
2181 gic=system.realview.gic
2182 int_num=117
2183 p_state_clk_gate_bins=20
2184 p_state_clk_gate_max=1000000000000
2185 p_state_clk_gate_min=1000
2186 pio_addr=721420288
2187 pio_latency=10000
2188 pixel_buffer_size=2048
2189 pixel_chunk=32
2190 power_model=Null
2191 pxl_clk=system.realview.dcc.osc_pxl
2192 system=system
2193 vnc=system.vncserver
2194 workaround_dma_line_count=true
2195 workaround_swap_rb=true
2196 dma=system.membus.slave[0]
2197 pio=system.iobus.master[6]
2198
2199 [system.realview.ide]
2200 type=IdeController
2201 BAR0=1
2202 BAR0LegacyIO=false
2203 BAR0Size=8
2204 BAR1=1
2205 BAR1LegacyIO=false
2206 BAR1Size=4
2207 BAR2=1
2208 BAR2LegacyIO=false
2209 BAR2Size=8
2210 BAR3=1
2211 BAR3LegacyIO=false
2212 BAR3Size=4
2213 BAR4=1
2214 BAR4LegacyIO=false
2215 BAR4Size=16
2216 BAR5=1
2217 BAR5LegacyIO=false
2218 BAR5Size=0
2219 BIST=0
2220 CacheLineSize=0
2221 CapabilityPtr=0
2222 CardbusCIS=0
2223 ClassCode=1
2224 Command=0
2225 DeviceID=28945
2226 ExpansionROM=0
2227 HeaderType=0
2228 InterruptLine=2
2229 InterruptPin=2
2230 LatencyTimer=0
2231 LegacyIOBase=0
2232 MSICAPBaseOffset=0
2233 MSICAPCapId=0
2234 MSICAPMaskBits=0
2235 MSICAPMsgAddr=0
2236 MSICAPMsgCtrl=0
2237 MSICAPMsgData=0
2238 MSICAPMsgUpperAddr=0
2239 MSICAPNextCapability=0
2240 MSICAPPendingBits=0
2241 MSIXCAPBaseOffset=0
2242 MSIXCAPCapId=0
2243 MSIXCAPNextCapability=0
2244 MSIXMsgCtrl=0
2245 MSIXPbaOffset=0
2246 MSIXTableOffset=0
2247 MaximumLatency=0
2248 MinimumGrant=0
2249 PMCAPBaseOffset=0
2250 PMCAPCapId=0
2251 PMCAPCapabilities=0
2252 PMCAPCtrlStatus=0
2253 PMCAPNextCapability=0
2254 PXCAPBaseOffset=0
2255 PXCAPCapId=0
2256 PXCAPCapabilities=0
2257 PXCAPDevCap2=0
2258 PXCAPDevCapabilities=0
2259 PXCAPDevCtrl=0
2260 PXCAPDevCtrl2=0
2261 PXCAPDevStatus=0
2262 PXCAPLinkCap=0
2263 PXCAPLinkCtrl=0
2264 PXCAPLinkStatus=0
2265 PXCAPNextCapability=0
2266 ProgIF=133
2267 Revision=0
2268 Status=640
2269 SubClassCode=1
2270 SubsystemID=0
2271 SubsystemVendorID=0
2272 VendorID=32902
2273 clk_domain=system.clk_domain
2274 config_latency=20000
2275 ctrl_offset=0
2276 default_p_state=UNDEFINED
2277 disks=system.cf0
2278 eventq_index=0
2279 host=system.realview.pci_host
2280 io_shift=0
2281 p_state_clk_gate_bins=20
2282 p_state_clk_gate_max=1000000000000
2283 p_state_clk_gate_min=1000
2284 pci_bus=0
2285 pci_dev=1
2286 pci_func=0
2287 pio_latency=30000
2288 power_model=Null
2289 system=system
2290 dma=system.iobus.slave[3]
2291 pio=system.iobus.master[23]
2292
2293 [system.realview.kmi0]
2294 type=Pl050
2295 amba_id=1314896
2296 clk_domain=system.clk_domain
2297 default_p_state=UNDEFINED
2298 eventq_index=0
2299 gic=system.realview.gic
2300 int_delay=1000000
2301 int_num=44
2302 is_mouse=false
2303 p_state_clk_gate_bins=20
2304 p_state_clk_gate_max=1000000000000
2305 p_state_clk_gate_min=1000
2306 pio_addr=470155264
2307 pio_latency=100000
2308 power_model=Null
2309 system=system
2310 vnc=system.vncserver
2311 pio=system.iobus.master[7]
2312
2313 [system.realview.kmi1]
2314 type=Pl050
2315 amba_id=1314896
2316 clk_domain=system.clk_domain
2317 default_p_state=UNDEFINED
2318 eventq_index=0
2319 gic=system.realview.gic
2320 int_delay=1000000
2321 int_num=45
2322 is_mouse=true
2323 p_state_clk_gate_bins=20
2324 p_state_clk_gate_max=1000000000000
2325 p_state_clk_gate_min=1000
2326 pio_addr=470220800
2327 pio_latency=100000
2328 power_model=Null
2329 system=system
2330 vnc=system.vncserver
2331 pio=system.iobus.master[8]
2332
2333 [system.realview.l2x0_fake]
2334 type=IsaFake
2335 clk_domain=system.clk_domain
2336 default_p_state=UNDEFINED
2337 eventq_index=0
2338 fake_mem=false
2339 p_state_clk_gate_bins=20
2340 p_state_clk_gate_max=1000000000000
2341 p_state_clk_gate_min=1000
2342 pio_addr=739246080
2343 pio_latency=100000
2344 pio_size=4095
2345 power_model=Null
2346 ret_bad_addr=false
2347 ret_data16=65535
2348 ret_data32=4294967295
2349 ret_data64=18446744073709551615
2350 ret_data8=255
2351 system=system
2352 update_data=false
2353 warn_access=
2354 pio=system.iobus.master[12]
2355
2356 [system.realview.lan_fake]
2357 type=IsaFake
2358 clk_domain=system.clk_domain
2359 default_p_state=UNDEFINED
2360 eventq_index=0
2361 fake_mem=false
2362 p_state_clk_gate_bins=20
2363 p_state_clk_gate_max=1000000000000
2364 p_state_clk_gate_min=1000
2365 pio_addr=436207616
2366 pio_latency=100000
2367 pio_size=65535
2368 power_model=Null
2369 ret_bad_addr=false
2370 ret_data16=65535
2371 ret_data32=4294967295
2372 ret_data64=18446744073709551615
2373 ret_data8=255
2374 system=system
2375 update_data=false
2376 warn_access=
2377 pio=system.iobus.master[19]
2378
2379 [system.realview.local_cpu_timer]
2380 type=CpuLocalTimer
2381 clk_domain=system.clk_domain
2382 default_p_state=UNDEFINED
2383 eventq_index=0
2384 gic=system.realview.gic
2385 int_num_timer=29
2386 int_num_watchdog=30
2387 p_state_clk_gate_bins=20
2388 p_state_clk_gate_max=1000000000000
2389 p_state_clk_gate_min=1000
2390 pio_addr=738721792
2391 pio_latency=100000
2392 power_model=Null
2393 system=system
2394 pio=system.membus.master[4]
2395
2396 [system.realview.mcc]
2397 type=SubSystem
2398 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
2399 eventq_index=0
2400 thermal_domain=Null
2401
2402 [system.realview.mcc.osc_clcd]
2403 type=RealViewOsc
2404 dcc=0
2405 device=1
2406 eventq_index=0
2407 freq=42105
2408 parent=system.realview.realview_io
2409 position=0
2410 site=0
2411 voltage_domain=system.voltage_domain
2412
2413 [system.realview.mcc.osc_mcc]
2414 type=RealViewOsc
2415 dcc=0
2416 device=0
2417 eventq_index=0
2418 freq=20000
2419 parent=system.realview.realview_io
2420 position=0
2421 site=0
2422 voltage_domain=system.voltage_domain
2423
2424 [system.realview.mcc.osc_peripheral]
2425 type=RealViewOsc
2426 dcc=0
2427 device=2
2428 eventq_index=0
2429 freq=41667
2430 parent=system.realview.realview_io
2431 position=0
2432 site=0
2433 voltage_domain=system.voltage_domain
2434
2435 [system.realview.mcc.osc_system_bus]
2436 type=RealViewOsc
2437 dcc=0
2438 device=4
2439 eventq_index=0
2440 freq=41667
2441 parent=system.realview.realview_io
2442 position=0
2443 site=0
2444 voltage_domain=system.voltage_domain
2445
2446 [system.realview.mcc.temp_crtl]
2447 type=RealViewTemperatureSensor
2448 dcc=0
2449 device=0
2450 eventq_index=0
2451 parent=system.realview.realview_io
2452 position=0
2453 site=0
2454 system=system
2455
2456 [system.realview.mmc_fake]
2457 type=AmbaFake
2458 amba_id=0
2459 clk_domain=system.clk_domain
2460 default_p_state=UNDEFINED
2461 eventq_index=0
2462 ignore_access=false
2463 p_state_clk_gate_bins=20
2464 p_state_clk_gate_max=1000000000000
2465 p_state_clk_gate_min=1000
2466 pio_addr=470089728
2467 pio_latency=100000
2468 power_model=Null
2469 system=system
2470 pio=system.iobus.master[21]
2471
2472 [system.realview.nvmem]
2473 type=SimpleMemory
2474 bandwidth=73.000000
2475 clk_domain=system.clk_domain
2476 conf_table_reported=false
2477 default_p_state=UNDEFINED
2478 eventq_index=0
2479 in_addr_map=true
2480 kvm_map=true
2481 latency=30000
2482 latency_var=0
2483 null=false
2484 p_state_clk_gate_bins=20
2485 p_state_clk_gate_max=1000000000000
2486 p_state_clk_gate_min=1000
2487 power_model=Null
2488 range=0:67108863:0:0:0:0
2489 port=system.membus.master[1]
2490
2491 [system.realview.pci_host]
2492 type=GenericPciHost
2493 clk_domain=system.clk_domain
2494 conf_base=805306368
2495 conf_device_bits=12
2496 conf_size=268435456
2497 default_p_state=UNDEFINED
2498 eventq_index=0
2499 p_state_clk_gate_bins=20
2500 p_state_clk_gate_max=1000000000000
2501 p_state_clk_gate_min=1000
2502 pci_dma_base=0
2503 pci_mem_base=0
2504 pci_pio_base=788529152
2505 platform=system.realview
2506 power_model=Null
2507 system=system
2508 pio=system.iobus.master[2]
2509
2510 [system.realview.realview_io]
2511 type=RealViewCtrl
2512 clk_domain=system.clk_domain
2513 default_p_state=UNDEFINED
2514 eventq_index=0
2515 idreg=35979264
2516 p_state_clk_gate_bins=20
2517 p_state_clk_gate_max=1000000000000
2518 p_state_clk_gate_min=1000
2519 pio_addr=469827584
2520 pio_latency=100000
2521 power_model=Null
2522 proc_id0=335544320
2523 proc_id1=335544320
2524 system=system
2525 pio=system.iobus.master[1]
2526
2527 [system.realview.rtc]
2528 type=PL031
2529 amba_id=3412017
2530 clk_domain=system.clk_domain
2531 default_p_state=UNDEFINED
2532 eventq_index=0
2533 gic=system.realview.gic
2534 int_delay=100000
2535 int_num=36
2536 p_state_clk_gate_bins=20
2537 p_state_clk_gate_max=1000000000000
2538 p_state_clk_gate_min=1000
2539 pio_addr=471269376
2540 pio_latency=100000
2541 power_model=Null
2542 system=system
2543 time=Thu Jan 1 00:00:00 2009
2544 pio=system.iobus.master[10]
2545
2546 [system.realview.sp810_fake]
2547 type=AmbaFake
2548 amba_id=0
2549 clk_domain=system.clk_domain
2550 default_p_state=UNDEFINED
2551 eventq_index=0
2552 ignore_access=true
2553 p_state_clk_gate_bins=20
2554 p_state_clk_gate_max=1000000000000
2555 p_state_clk_gate_min=1000
2556 pio_addr=469893120
2557 pio_latency=100000
2558 power_model=Null
2559 system=system
2560 pio=system.iobus.master[16]
2561
2562 [system.realview.timer0]
2563 type=Sp804
2564 amba_id=1316868
2565 clk_domain=system.clk_domain
2566 clock0=1000000
2567 clock1=1000000
2568 default_p_state=UNDEFINED
2569 eventq_index=0
2570 gic=system.realview.gic
2571 int_num0=34
2572 int_num1=34
2573 p_state_clk_gate_bins=20
2574 p_state_clk_gate_max=1000000000000
2575 p_state_clk_gate_min=1000
2576 pio_addr=470876160
2577 pio_latency=100000
2578 power_model=Null
2579 system=system
2580 pio=system.iobus.master[3]
2581
2582 [system.realview.timer1]
2583 type=Sp804
2584 amba_id=1316868
2585 clk_domain=system.clk_domain
2586 clock0=1000000
2587 clock1=1000000
2588 default_p_state=UNDEFINED
2589 eventq_index=0
2590 gic=system.realview.gic
2591 int_num0=35
2592 int_num1=35
2593 p_state_clk_gate_bins=20
2594 p_state_clk_gate_max=1000000000000
2595 p_state_clk_gate_min=1000
2596 pio_addr=470941696
2597 pio_latency=100000
2598 power_model=Null
2599 system=system
2600 pio=system.iobus.master[4]
2601
2602 [system.realview.uart]
2603 type=Pl011
2604 clk_domain=system.clk_domain
2605 default_p_state=UNDEFINED
2606 end_on_eot=false
2607 eventq_index=0
2608 gic=system.realview.gic
2609 int_delay=100000
2610 int_num=37
2611 p_state_clk_gate_bins=20
2612 p_state_clk_gate_max=1000000000000
2613 p_state_clk_gate_min=1000
2614 pio_addr=470351872
2615 pio_latency=100000
2616 platform=system.realview
2617 power_model=Null
2618 system=system
2619 terminal=system.terminal
2620 pio=system.iobus.master[0]
2621
2622 [system.realview.uart1_fake]
2623 type=AmbaFake
2624 amba_id=0
2625 clk_domain=system.clk_domain
2626 default_p_state=UNDEFINED
2627 eventq_index=0
2628 ignore_access=false
2629 p_state_clk_gate_bins=20
2630 p_state_clk_gate_max=1000000000000
2631 p_state_clk_gate_min=1000
2632 pio_addr=470417408
2633 pio_latency=100000
2634 power_model=Null
2635 system=system
2636 pio=system.iobus.master[13]
2637
2638 [system.realview.uart2_fake]
2639 type=AmbaFake
2640 amba_id=0
2641 clk_domain=system.clk_domain
2642 default_p_state=UNDEFINED
2643 eventq_index=0
2644 ignore_access=false
2645 p_state_clk_gate_bins=20
2646 p_state_clk_gate_max=1000000000000
2647 p_state_clk_gate_min=1000
2648 pio_addr=470482944
2649 pio_latency=100000
2650 power_model=Null
2651 system=system
2652 pio=system.iobus.master[14]
2653
2654 [system.realview.uart3_fake]
2655 type=AmbaFake
2656 amba_id=0
2657 clk_domain=system.clk_domain
2658 default_p_state=UNDEFINED
2659 eventq_index=0
2660 ignore_access=false
2661 p_state_clk_gate_bins=20
2662 p_state_clk_gate_max=1000000000000
2663 p_state_clk_gate_min=1000
2664 pio_addr=470548480
2665 pio_latency=100000
2666 power_model=Null
2667 system=system
2668 pio=system.iobus.master[15]
2669
2670 [system.realview.usb_fake]
2671 type=IsaFake
2672 clk_domain=system.clk_domain
2673 default_p_state=UNDEFINED
2674 eventq_index=0
2675 fake_mem=false
2676 p_state_clk_gate_bins=20
2677 p_state_clk_gate_max=1000000000000
2678 p_state_clk_gate_min=1000
2679 pio_addr=452984832
2680 pio_latency=100000
2681 pio_size=131071
2682 power_model=Null
2683 ret_bad_addr=false
2684 ret_data16=65535
2685 ret_data32=4294967295
2686 ret_data64=18446744073709551615
2687 ret_data8=255
2688 system=system
2689 update_data=false
2690 warn_access=
2691 pio=system.iobus.master[20]
2692
2693 [system.realview.vgic]
2694 type=VGic
2695 clk_domain=system.clk_domain
2696 default_p_state=UNDEFINED
2697 eventq_index=0
2698 gic=system.realview.gic
2699 hv_addr=738213888
2700 p_state_clk_gate_bins=20
2701 p_state_clk_gate_max=1000000000000
2702 p_state_clk_gate_min=1000
2703 pio_delay=10000
2704 platform=system.realview
2705 power_model=Null
2706 ppint=25
2707 system=system
2708 vcpu_addr=738222080
2709 pio=system.membus.master[3]
2710
2711 [system.realview.vram]
2712 type=SimpleMemory
2713 bandwidth=73.000000
2714 clk_domain=system.clk_domain
2715 conf_table_reported=false
2716 default_p_state=UNDEFINED
2717 eventq_index=0
2718 in_addr_map=true
2719 kvm_map=true
2720 latency=30000
2721 latency_var=0
2722 null=false
2723 p_state_clk_gate_bins=20
2724 p_state_clk_gate_max=1000000000000
2725 p_state_clk_gate_min=1000
2726 power_model=Null
2727 range=402653184:436207615:0:0:0:0
2728 port=system.iobus.master[11]
2729
2730 [system.realview.watchdog_fake]
2731 type=AmbaFake
2732 amba_id=0
2733 clk_domain=system.clk_domain
2734 default_p_state=UNDEFINED
2735 eventq_index=0
2736 ignore_access=false
2737 p_state_clk_gate_bins=20
2738 p_state_clk_gate_max=1000000000000
2739 p_state_clk_gate_min=1000
2740 pio_addr=470745088
2741 pio_latency=100000
2742 power_model=Null
2743 system=system
2744 pio=system.iobus.master[17]
2745
2746 [system.terminal]
2747 type=Terminal
2748 eventq_index=0
2749 intr_control=system.intrctrl
2750 number=0
2751 output=true
2752 port=3456
2753
2754 [system.toL2Bus]
2755 type=CoherentXBar
2756 children=snoop_filter
2757 clk_domain=system.cpu_clk_domain
2758 default_p_state=UNDEFINED
2759 eventq_index=0
2760 forward_latency=0
2761 frontend_latency=1
2762 p_state_clk_gate_bins=20
2763 p_state_clk_gate_max=1000000000000
2764 p_state_clk_gate_min=1000
2765 point_of_coherency=false
2766 power_model=Null
2767 response_latency=1
2768 snoop_filter=system.toL2Bus.snoop_filter
2769 snoop_response_latency=1
2770 system=system
2771 use_default_range=false
2772 width=32
2773 master=system.l2c.cpu_side
2774 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
2775
2776 [system.toL2Bus.snoop_filter]
2777 type=SnoopFilter
2778 eventq_index=0
2779 lookup_latency=0
2780 max_capacity=8388608
2781 system=system
2782
2783 [system.vncserver]
2784 type=VncServer
2785 eventq_index=0
2786 frame_capture=false
2787 number=0
2788 port=5900
2789
2790 [system.voltage_domain]
2791 type=VoltageDomain
2792 eventq_index=0
2793 voltage=1.000000
2794