2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 51.111153 # Number of seconds simulated
4 sim_ticks 51111152682000 # Number of ticks simulated
5 final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 1040961 # Simulator instruction rate (inst/s)
8 host_op_rate 1223300 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 54038486240 # Simulator tick rate (ticks/s)
10 host_mem_usage 670940 # Number of bytes of host memory used
11 host_seconds 945.83 # Real time elapsed on the host
12 sim_insts 984570519 # Number of instructions simulated
13 sim_ops 1157031967 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory
20 system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory
27 system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory
31 system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory
34 system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s)
54 system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
55 system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
56 system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
57 system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
58 system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
59 system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
60 system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
61 system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
62 system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
63 system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
64 system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
65 system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
66 system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
67 system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
68 system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
69 system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
70 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
71 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
72 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
73 system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
74 system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
75 system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
76 system.cpu_clk_domain.clock 500 # Clock period in ticks
77 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
78 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
79 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
80 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
81 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
82 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
83 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
84 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
85 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
86 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
87 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
88 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
89 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
90 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
91 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
92 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
93 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
94 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
95 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
96 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
97 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
98 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
99 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
100 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
101 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
102 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
103 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
104 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
105 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
106 system.cpu.dtb.walker.walks 265715 # Table walker walks requested
107 system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
108 system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
109 system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
110 system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
111 system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
112 system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
113 system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
114 system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
115 system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
116 system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
117 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst
118 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
119 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst
120 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst
121 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
122 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
123 system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
124 system.cpu.dtb.inst_hits 0 # ITB inst hits
125 system.cpu.dtb.inst_misses 0 # ITB inst misses
126 system.cpu.dtb.read_hits 184014035 # DTB read hits
127 system.cpu.dtb.read_misses 194198 # DTB read misses
128 system.cpu.dtb.write_hits 168232768 # DTB write hits
129 system.cpu.dtb.write_misses 71517 # DTB write misses
130 system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
131 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
132 system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
133 system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
134 system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
135 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
136 system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
137 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
138 system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
139 system.cpu.dtb.read_accesses 184208233 # DTB read accesses
140 system.cpu.dtb.write_accesses 168304285 # DTB write accesses
141 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
142 system.cpu.dtb.hits 352246803 # DTB hits
143 system.cpu.dtb.misses 265715 # DTB misses
144 system.cpu.dtb.accesses 352512518 # DTB accesses
145 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
146 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
147 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
148 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
149 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
150 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
151 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
152 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
153 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
154 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
155 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
156 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
157 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
158 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
159 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
160 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
161 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
162 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
163 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
164 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
165 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
166 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
167 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
168 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
169 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
170 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
171 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
172 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
173 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
174 system.cpu.itb.walker.walks 126837 # Table walker walks requested
175 system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
176 system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
177 system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
178 system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
179 system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
180 system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
181 system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
182 system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
183 system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
184 system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
185 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
186 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst
187 system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst
188 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
189 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
190 system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
191 system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
192 system.cpu.itb.inst_hits 985047321 # ITB inst hits
193 system.cpu.itb.inst_misses 126837 # ITB inst misses
194 system.cpu.itb.read_hits 0 # DTB read hits
195 system.cpu.itb.read_misses 0 # DTB read misses
196 system.cpu.itb.write_hits 0 # DTB write hits
197 system.cpu.itb.write_misses 0 # DTB write misses
198 system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
199 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
200 system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
201 system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
202 system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
203 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
204 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
205 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
206 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
207 system.cpu.itb.read_accesses 0 # DTB read accesses
208 system.cpu.itb.write_accesses 0 # DTB write accesses
209 system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
210 system.cpu.itb.hits 985047321 # DTB hits
211 system.cpu.itb.misses 126837 # DTB misses
212 system.cpu.itb.accesses 985174158 # DTB accesses
213 system.cpu.numCycles 102222322140 # number of cpu cycles simulated
214 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
215 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
216 system.cpu.committedInsts 984570519 # Number of instructions committed
217 system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
218 system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
219 system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
220 system.cpu.num_func_calls 57056367 # number of times a function call or return occured
221 system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
222 system.cpu.num_int_insts 1060455466 # number of integer instructions
223 system.cpu.num_fp_insts 880805 # number of float instructions
224 system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
225 system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
226 system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
227 system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
228 system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
229 system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
230 system.cpu.num_mem_refs 352465606 # number of memory refs
231 system.cpu.num_load_insts 184180431 # Number of load instructions
232 system.cpu.num_store_insts 168285175 # Number of store instructions
233 system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
234 system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
235 system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
236 system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
237 system.cpu.Branches 220088562 # Number of branches fetched
238 system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
239 system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
240 system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction
241 system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
242 system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
243 system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
244 system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
245 system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
246 system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
247 system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
248 system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
249 system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
250 system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
251 system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
252 system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
253 system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
254 system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
255 system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
256 system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
257 system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
258 system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
259 system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
260 system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
261 system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction
262 system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
263 system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
264 system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
265 system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
266 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
267 system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
268 system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
269 system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
270 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
271 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
272 system.cpu.op_class::total 1157666593 # Class of executed instruction
273 system.cpu.kern.inst.arm 0 # number of arm instructions executed
274 system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
275 system.cpu.dcache.tags.replacements 11612141 # number of replacements
276 system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
277 system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
278 system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
279 system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
280 system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
281 system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
282 system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
283 system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
284 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
285 system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
287 system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
288 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
289 system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
290 system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
291 system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits
292 system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits
293 system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits
294 system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits
295 system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits
296 system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits
297 system.cpu.dcache.WriteLineReq_hits::cpu.data 337709 # number of WriteLineReq hits
298 system.cpu.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits
299 system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits
300 system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits
301 system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits
302 system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
303 system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits
304 system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits
305 system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits
306 system.cpu.dcache.overall_hits::total 331514149 # number of overall hits
307 system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses
308 system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses
309 system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses
310 system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses
311 system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses
312 system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses
313 system.cpu.dcache.WriteLineReq_misses::cpu.data 1245349 # number of WriteLineReq misses
314 system.cpu.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses
315 system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses
316 system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses
317 system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
318 system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
319 system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses
320 system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses
321 system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses
322 system.cpu.dcache.overall_misses::total 10164734 # number of overall misses
323 system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses)
324 system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
325 system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses)
326 system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses)
327 system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses)
328 system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses)
329 system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583058 # number of WriteLineReq accesses(hits+misses)
330 system.cpu.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses)
331 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses)
332 system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses)
333 system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses)
334 system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
335 system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses
336 system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses
337 system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses
338 system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses
339 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses
340 system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses
341 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses
342 system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
343 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses
344 system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses
345 system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786673 # miss rate for WriteLineReq accesses
346 system.cpu.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses
347 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses
348 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses
349 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
350 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
351 system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses
352 system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
353 system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses
354 system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
355 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
356 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
357 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
358 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
359 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
360 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
361 system.cpu.dcache.fast_writes 0 # number of fast writes performed
362 system.cpu.dcache.cache_copies 0 # number of cache copies performed
363 system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks
364 system.cpu.dcache.writebacks::total 8921279 # number of writebacks
365 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
366 system.cpu.icache.tags.replacements 14295641 # number of replacements
367 system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
368 system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
369 system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
370 system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
371 system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
372 system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
373 system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
374 system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
375 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
376 system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
377 system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
378 system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
379 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
380 system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses
381 system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses
382 system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits
383 system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits
384 system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits
385 system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits
386 system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits
387 system.cpu.icache.overall_hits::total 970865862 # number of overall hits
388 system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses
389 system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
390 system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses
391 system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses
392 system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses
393 system.cpu.icache.overall_misses::total 14296158 # number of overall misses
394 system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses)
395 system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
396 system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses
397 system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
398 system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses
399 system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
400 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses
401 system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
402 system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses
403 system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
404 system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses
405 system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
406 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
407 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
408 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
409 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
410 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
411 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
412 system.cpu.icache.fast_writes 0 # number of fast writes performed
413 system.cpu.icache.cache_copies 0 # number of cache copies performed
414 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
415 system.cpu.l2cache.tags.replacements 1722572 # number of replacements
416 system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use
417 system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks.
418 system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks.
419 system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks.
420 system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
421 system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor
422 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor
423 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor
424 system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor
425 system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor
426 system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy
427 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy
428 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy
429 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy
430 system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy
431 system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy
432 system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
433 system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id
434 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id
435 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
436 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
437 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id
438 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id
439 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id
440 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
441 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id
442 system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses
443 system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses
444 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
445 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits
446 system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits
447 system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits
448 system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits
449 system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits
450 system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
451 system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits
452 system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits
453 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits
454 system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits
455 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits
456 system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits
457 system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits
458 system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits
459 system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits
460 system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits
461 system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits
462 system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits
463 system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits
464 system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits
465 system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits
466 system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits
467 system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits
468 system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits
469 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses
470 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses
471 system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses
472 system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses
473 system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses
474 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
475 system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
476 system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses
477 system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses
478 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses
479 system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses
480 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses
481 system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses
482 system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses
483 system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses
484 system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses
485 system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses
486 system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses
487 system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses
488 system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses
489 system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
490 system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses
491 system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses
492 system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses
493 system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses
494 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
495 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
496 system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses)
497 system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses)
498 system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses)
499 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
500 system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
501 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
502 system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
503 system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses)
504 system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses)
505 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14296158 # number of ReadCleanReq accesses(hits+misses)
506 system.cpu.l2cache.ReadCleanReq_accesses::total 14296158 # number of ReadCleanReq accesses(hits+misses)
507 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7848198 # number of ReadSharedReq accesses(hits+misses)
508 system.cpu.l2cache.ReadSharedReq_accesses::total 7848198 # number of ReadSharedReq accesses(hits+misses)
509 system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245349 # number of InvalidateReq accesses(hits+misses)
510 system.cpu.l2cache.InvalidateReq_accesses::total 1245349 # number of InvalidateReq accesses(hits+misses)
511 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses
512 system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses
513 system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses
514 system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses
515 system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses
516 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses
517 system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses
518 system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses
519 system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses
520 system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses
521 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses
522 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022508 # miss rate for ReadReq accesses
523 system.cpu.l2cache.ReadReq_miss_rate::total 0.015917 # miss rate for ReadReq accesses
524 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses
525 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
526 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
527 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
528 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses
529 system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses
530 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses
531 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses
532 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses
533 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses
534 system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses
535 system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses
536 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
537 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses
538 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses
539 system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses
540 system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses
541 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
542 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses
543 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses
544 system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses
545 system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses
546 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
547 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
548 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
549 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
550 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
551 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
552 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
553 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
554 system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks
555 system.cpu.l2cache.writebacks::total 1503689 # number of writebacks
556 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
557 system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution
558 system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
559 system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
560 system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
561 system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
562 system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution
563 system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
564 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
565 system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
566 system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
567 system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
568 system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution
569 system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution
570 system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution
571 system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution
572 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes)
573 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes)
574 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
575 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
576 system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes)
577 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
578 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
579 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
580 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
581 system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes)
582 system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
583 system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram
584 system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram
585 system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram
586 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
587 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
588 system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram
589 system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram
590 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
591 system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
592 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
593 system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram
594 system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
595 system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
596 system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
597 system.iobus.trans_dist::WriteResp 136515 # Transaction distribution
598 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
599 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
600 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
601 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
602 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
603 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
604 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
605 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
606 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
607 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
608 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
609 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
610 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
611 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
612 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
613 system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
614 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
615 system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
616 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
617 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
618 system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
619 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
620 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
621 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
622 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
623 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
624 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
625 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
626 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
627 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
628 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
629 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
630 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
631 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
632 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
633 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
634 system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
635 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
636 system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
637 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
638 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
639 system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
640 system.iocache.tags.replacements 115463 # number of replacements
641 system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
642 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
643 system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
644 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
645 system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
646 system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
647 system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
648 system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
649 system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
650 system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
651 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
652 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
653 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
654 system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
655 system.iocache.tags.data_accesses 1039686 # Number of data accesses
656 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
657 system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
658 system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
659 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
660 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
661 system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
662 system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
663 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
664 system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
665 system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
666 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
667 system.iocache.overall_misses::realview.ide 8817 # number of overall misses
668 system.iocache.overall_misses::total 8857 # number of overall misses
669 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
670 system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
671 system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
672 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
673 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
674 system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
675 system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
676 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
677 system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
678 system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
679 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
680 system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
681 system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
682 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
683 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
684 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
685 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
686 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
687 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
688 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
689 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
690 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
691 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
692 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
693 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
694 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
695 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
696 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
697 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
698 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
699 system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
700 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
701 system.iocache.fast_writes 0 # number of fast writes performed
702 system.iocache.cache_copies 0 # number of cache copies performed
703 system.iocache.writebacks::writebacks 106631 # number of writebacks
704 system.iocache.writebacks::total 106631 # number of writebacks
705 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
706 system.membus.trans_dist::ReadReq 76679 # Transaction distribution
707 system.membus.trans_dist::ReadResp 525878 # Transaction distribution
708 system.membus.trans_dist::WriteReq 33606 # Transaction distribution
709 system.membus.trans_dist::WriteResp 33606 # Transaction distribution
710 system.membus.trans_dist::Writeback 1610320 # Transaction distribution
711 system.membus.trans_dist::CleanEvict 228940 # Transaction distribution
712 system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
713 system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
714 system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
715 system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution
716 system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution
717 system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution
718 system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
719 system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
720 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
721 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
722 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
723 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes)
724 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes)
725 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes)
726 system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes)
727 system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes)
728 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
729 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
730 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
731 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes)
732 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes)
733 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes)
734 system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
735 system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes)
736 system.membus.snoops 0 # Total snoops (count)
737 system.membus.snoop_fanout::samples 3922914 # Request fanout histogram
738 system.membus.snoop_fanout::mean 1 # Request fanout histogram
739 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
740 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
741 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
742 system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram
743 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
744 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
745 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
746 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
747 system.membus.snoop_fanout::total 3922914 # Request fanout histogram
748 system.realview.ethernet.txBytes 966 # Bytes Transmitted
749 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
750 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
751 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
752 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
753 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
754 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
755 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
756 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
757 system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
758 system.realview.ethernet.totPackets 3 # Total Packets
759 system.realview.ethernet.totBytes 966 # Total Bytes
760 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
761 system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
762 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
763 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
764 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
765 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
766 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
767 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
768 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
769 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
770 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
771 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
772 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
773 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
774 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
775 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
776 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
777 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
778 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
779 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
780 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
781 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
782 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
783 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
784 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
785 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
786 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
787 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
788 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
789 system.realview.ethernet.droppedPackets 0 # number of packets dropped
790 system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
791 system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
792 system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
793 system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
794 system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
795 system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
796 system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
797 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
798 system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
799 system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
801 ---------- End Simulation Statistics ----------
projects / gem5.git / blob