8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 default_p_state=UNDEFINED
20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
21 early_kernel_symbols=false
22 enable_context_switch_stats_dump=false
24 exit_on_work_items=false
26 gic_cpu_addr=738205696
27 have_large_asid_64=false
30 have_virtualization=false
31 highest_el_is_64=false
33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
34 kernel_addr_check=true
35 load_addr_mask=268435455
36 load_offset=2147483648
37 machine_type=VExpress_EMM64
39 mem_ranges=2147483648:2415919103
40 memories=system.physmem system.realview.nvmem system.realview.vram
41 mmap_using_noreserve=false
45 p_state_clk_gate_bins=20
46 p_state_clk_gate_max=1000000000000
47 p_state_clk_gate_min=1000
52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
57 work_begin_ckpt_count=0
58 work_begin_cpu_id_exit=-1
59 work_begin_exit_count=0
60 work_cpus_ckpt_count=0
64 system_port=system.membus.slave[1]
68 clk_domain=system.clk_domain
69 default_p_state=UNDEFINED
72 p_state_clk_gate_bins=20
73 p_state_clk_gate_max=1000000000000
74 p_state_clk_gate_min=1000
76 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
79 master=system.iobus.slave[0]
80 slave=system.membus.master[0]
88 image=system.cf0.image
93 child=system.cf0.image.child
99 [system.cf0.image.child]
102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
111 voltage_domain=system.voltage_domain
115 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
118 clk_domain=system.cpu_clk_domain
120 default_p_state=UNDEFINED
121 do_checkpoint_insts=true
123 do_statistics_insts=true
124 dstage2_mmu=system.cpu0.dstage2_mmu
129 function_trace_start=0
130 interrupts=system.cpu0.interrupts
132 istage2_mmu=system.cpu0.istage2_mmu
134 max_insts_all_threads=0
135 max_insts_any_thread=0
136 max_loads_all_threads=0
137 max_loads_any_thread=0
139 p_state_clk_gate_bins=20
140 p_state_clk_gate_max=1000000000000
141 p_state_clk_gate_min=1000
145 simpoint_start_insts=
146 simulate_data_stalls=false
147 simulate_inst_stalls=false
151 tracer=system.cpu0.tracer
154 dcache_port=system.cpu0.dcache.cpu_side
155 icache_port=system.cpu0.icache.cpu_side
160 addr_ranges=0:18446744073709551615
162 clk_domain=system.cpu_clk_domain
163 clusivity=mostly_incl
164 default_p_state=UNDEFINED
165 demand_mshr_reserve=1
171 p_state_clk_gate_bins=20
172 p_state_clk_gate_max=1000000000000
173 p_state_clk_gate_min=1000
175 prefetch_on_access=false
178 sequential_access=false
181 tags=system.cpu0.dcache.tags
185 cpu_side=system.cpu0.dcache_port
186 mem_side=system.cpu0.toL2Bus.slave[1]
188 [system.cpu0.dcache.tags]
192 clk_domain=system.cpu_clk_domain
193 default_p_state=UNDEFINED
196 p_state_clk_gate_bins=20
197 p_state_clk_gate_max=1000000000000
198 p_state_clk_gate_min=1000
200 sequential_access=false
203 [system.cpu0.dstage2_mmu]
207 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
211 [system.cpu0.dstage2_mmu.stage2_tlb]
217 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
219 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
221 clk_domain=system.cpu_clk_domain
222 default_p_state=UNDEFINED
225 num_squash_per_cycle=2
226 p_state_clk_gate_bins=20
227 p_state_clk_gate_max=1000000000000
228 p_state_clk_gate_min=1000
238 walker=system.cpu0.dtb.walker
240 [system.cpu0.dtb.walker]
242 clk_domain=system.cpu_clk_domain
243 default_p_state=UNDEFINED
246 num_squash_per_cycle=2
247 p_state_clk_gate_bins=20
248 p_state_clk_gate_max=1000000000000
249 p_state_clk_gate_min=1000
252 port=system.cpu0.toL2Bus.slave[3]
257 addr_ranges=0:18446744073709551615
259 clk_domain=system.cpu_clk_domain
260 clusivity=mostly_incl
261 default_p_state=UNDEFINED
262 demand_mshr_reserve=1
268 p_state_clk_gate_bins=20
269 p_state_clk_gate_max=1000000000000
270 p_state_clk_gate_min=1000
272 prefetch_on_access=false
275 sequential_access=false
278 tags=system.cpu0.icache.tags
282 cpu_side=system.cpu0.icache_port
283 mem_side=system.cpu0.toL2Bus.slave[0]
285 [system.cpu0.icache.tags]
289 clk_domain=system.cpu_clk_domain
290 default_p_state=UNDEFINED
293 p_state_clk_gate_bins=20
294 p_state_clk_gate_max=1000000000000
295 p_state_clk_gate_min=1000
297 sequential_access=false
300 [system.cpu0.interrupts]
306 decoderFlavour=Generic
311 id_aa64dfr0_el1=1052678
315 id_aa64mmfr0_el1=15728642
335 [system.cpu0.istage2_mmu]
339 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
343 [system.cpu0.istage2_mmu.stage2_tlb]
349 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
351 [system.cpu0.istage2_mmu.stage2_tlb.walker]
353 clk_domain=system.cpu_clk_domain
354 default_p_state=UNDEFINED
357 num_squash_per_cycle=2
358 p_state_clk_gate_bins=20
359 p_state_clk_gate_max=1000000000000
360 p_state_clk_gate_min=1000
370 walker=system.cpu0.itb.walker
372 [system.cpu0.itb.walker]
374 clk_domain=system.cpu_clk_domain
375 default_p_state=UNDEFINED
378 num_squash_per_cycle=2
379 p_state_clk_gate_bins=20
380 p_state_clk_gate_max=1000000000000
381 p_state_clk_gate_min=1000
384 port=system.cpu0.toL2Bus.slave[2]
386 [system.cpu0.l2cache]
388 children=prefetcher tags
389 addr_ranges=0:18446744073709551615
391 clk_domain=system.cpu_clk_domain
392 clusivity=mostly_excl
393 default_p_state=UNDEFINED
394 demand_mshr_reserve=1
400 p_state_clk_gate_bins=20
401 p_state_clk_gate_max=1000000000000
402 p_state_clk_gate_min=1000
404 prefetch_on_access=true
405 prefetcher=system.cpu0.l2cache.prefetcher
407 sequential_access=false
410 tags=system.cpu0.l2cache.tags
413 writeback_clean=false
414 cpu_side=system.cpu0.toL2Bus.master[0]
415 mem_side=system.toL2Bus.slave[0]
417 [system.cpu0.l2cache.prefetcher]
418 type=StridePrefetcher
420 clk_domain=system.cpu_clk_domain
421 default_p_state=UNDEFINED
432 p_state_clk_gate_bins=20
433 p_state_clk_gate_max=1000000000000
434 p_state_clk_gate_min=1000
447 [system.cpu0.l2cache.tags]
451 clk_domain=system.cpu_clk_domain
452 default_p_state=UNDEFINED
455 p_state_clk_gate_bins=20
456 p_state_clk_gate_max=1000000000000
457 p_state_clk_gate_min=1000
459 sequential_access=false
462 [system.cpu0.toL2Bus]
464 children=snoop_filter
465 clk_domain=system.cpu_clk_domain
466 default_p_state=UNDEFINED
470 p_state_clk_gate_bins=20
471 p_state_clk_gate_max=1000000000000
472 p_state_clk_gate_min=1000
473 point_of_coherency=false
476 snoop_filter=system.cpu0.toL2Bus.snoop_filter
477 snoop_response_latency=1
479 use_default_range=false
481 master=system.cpu0.l2cache.cpu_side
482 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
484 [system.cpu0.toL2Bus.snoop_filter]
497 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
500 clk_domain=system.cpu_clk_domain
502 default_p_state=UNDEFINED
503 do_checkpoint_insts=true
505 do_statistics_insts=true
506 dstage2_mmu=system.cpu1.dstage2_mmu
511 function_trace_start=0
512 interrupts=system.cpu1.interrupts
514 istage2_mmu=system.cpu1.istage2_mmu
516 max_insts_all_threads=0
517 max_insts_any_thread=0
518 max_loads_all_threads=0
519 max_loads_any_thread=0
521 p_state_clk_gate_bins=20
522 p_state_clk_gate_max=1000000000000
523 p_state_clk_gate_min=1000
527 simpoint_start_insts=
528 simulate_data_stalls=false
529 simulate_inst_stalls=false
533 tracer=system.cpu1.tracer
536 dcache_port=system.cpu1.dcache.cpu_side
537 icache_port=system.cpu1.icache.cpu_side
542 addr_ranges=0:18446744073709551615
544 clk_domain=system.cpu_clk_domain
545 clusivity=mostly_incl
546 default_p_state=UNDEFINED
547 demand_mshr_reserve=1
553 p_state_clk_gate_bins=20
554 p_state_clk_gate_max=1000000000000
555 p_state_clk_gate_min=1000
557 prefetch_on_access=false
560 sequential_access=false
563 tags=system.cpu1.dcache.tags
567 cpu_side=system.cpu1.dcache_port
568 mem_side=system.cpu1.toL2Bus.slave[1]
570 [system.cpu1.dcache.tags]
574 clk_domain=system.cpu_clk_domain
575 default_p_state=UNDEFINED
578 p_state_clk_gate_bins=20
579 p_state_clk_gate_max=1000000000000
580 p_state_clk_gate_min=1000
582 sequential_access=false
585 [system.cpu1.dstage2_mmu]
589 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
593 [system.cpu1.dstage2_mmu.stage2_tlb]
599 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
601 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
603 clk_domain=system.cpu_clk_domain
604 default_p_state=UNDEFINED
607 num_squash_per_cycle=2
608 p_state_clk_gate_bins=20
609 p_state_clk_gate_max=1000000000000
610 p_state_clk_gate_min=1000
620 walker=system.cpu1.dtb.walker
622 [system.cpu1.dtb.walker]
624 clk_domain=system.cpu_clk_domain
625 default_p_state=UNDEFINED
628 num_squash_per_cycle=2
629 p_state_clk_gate_bins=20
630 p_state_clk_gate_max=1000000000000
631 p_state_clk_gate_min=1000
634 port=system.cpu1.toL2Bus.slave[3]
639 addr_ranges=0:18446744073709551615
641 clk_domain=system.cpu_clk_domain
642 clusivity=mostly_incl
643 default_p_state=UNDEFINED
644 demand_mshr_reserve=1
650 p_state_clk_gate_bins=20
651 p_state_clk_gate_max=1000000000000
652 p_state_clk_gate_min=1000
654 prefetch_on_access=false
657 sequential_access=false
660 tags=system.cpu1.icache.tags
664 cpu_side=system.cpu1.icache_port
665 mem_side=system.cpu1.toL2Bus.slave[0]
667 [system.cpu1.icache.tags]
671 clk_domain=system.cpu_clk_domain
672 default_p_state=UNDEFINED
675 p_state_clk_gate_bins=20
676 p_state_clk_gate_max=1000000000000
677 p_state_clk_gate_min=1000
679 sequential_access=false
682 [system.cpu1.interrupts]
688 decoderFlavour=Generic
693 id_aa64dfr0_el1=1052678
697 id_aa64mmfr0_el1=15728642
717 [system.cpu1.istage2_mmu]
721 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
725 [system.cpu1.istage2_mmu.stage2_tlb]
731 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
733 [system.cpu1.istage2_mmu.stage2_tlb.walker]
735 clk_domain=system.cpu_clk_domain
736 default_p_state=UNDEFINED
739 num_squash_per_cycle=2
740 p_state_clk_gate_bins=20
741 p_state_clk_gate_max=1000000000000
742 p_state_clk_gate_min=1000
752 walker=system.cpu1.itb.walker
754 [system.cpu1.itb.walker]
756 clk_domain=system.cpu_clk_domain
757 default_p_state=UNDEFINED
760 num_squash_per_cycle=2
761 p_state_clk_gate_bins=20
762 p_state_clk_gate_max=1000000000000
763 p_state_clk_gate_min=1000
766 port=system.cpu1.toL2Bus.slave[2]
768 [system.cpu1.l2cache]
770 children=prefetcher tags
771 addr_ranges=0:18446744073709551615
773 clk_domain=system.cpu_clk_domain
774 clusivity=mostly_excl
775 default_p_state=UNDEFINED
776 demand_mshr_reserve=1
782 p_state_clk_gate_bins=20
783 p_state_clk_gate_max=1000000000000
784 p_state_clk_gate_min=1000
786 prefetch_on_access=true
787 prefetcher=system.cpu1.l2cache.prefetcher
789 sequential_access=false
792 tags=system.cpu1.l2cache.tags
795 writeback_clean=false
796 cpu_side=system.cpu1.toL2Bus.master[0]
797 mem_side=system.toL2Bus.slave[1]
799 [system.cpu1.l2cache.prefetcher]
800 type=StridePrefetcher
802 clk_domain=system.cpu_clk_domain
803 default_p_state=UNDEFINED
814 p_state_clk_gate_bins=20
815 p_state_clk_gate_max=1000000000000
816 p_state_clk_gate_min=1000
829 [system.cpu1.l2cache.tags]
833 clk_domain=system.cpu_clk_domain
834 default_p_state=UNDEFINED
837 p_state_clk_gate_bins=20
838 p_state_clk_gate_max=1000000000000
839 p_state_clk_gate_min=1000
841 sequential_access=false
844 [system.cpu1.toL2Bus]
846 children=snoop_filter
847 clk_domain=system.cpu_clk_domain
848 default_p_state=UNDEFINED
852 p_state_clk_gate_bins=20
853 p_state_clk_gate_max=1000000000000
854 p_state_clk_gate_min=1000
855 point_of_coherency=false
858 snoop_filter=system.cpu1.toL2Bus.snoop_filter
859 snoop_response_latency=1
861 use_default_range=false
863 master=system.cpu1.l2cache.cpu_side
864 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
866 [system.cpu1.toL2Bus.snoop_filter]
877 [system.cpu_clk_domain]
883 voltage_domain=system.voltage_domain
885 [system.dvfs_handler]
890 sys_clk_domain=system.clk_domain
891 transition_latency=100000000
900 clk_domain=system.clk_domain
901 default_p_state=UNDEFINED
905 p_state_clk_gate_bins=20
906 p_state_clk_gate_max=1000000000000
907 p_state_clk_gate_min=1000
910 use_default_range=false
912 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
913 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
918 addr_ranges=2147483648:2415919103
920 clk_domain=system.clk_domain
921 clusivity=mostly_incl
922 default_p_state=UNDEFINED
923 demand_mshr_reserve=1
929 p_state_clk_gate_bins=20
930 p_state_clk_gate_max=1000000000000
931 p_state_clk_gate_min=1000
933 prefetch_on_access=false
936 sequential_access=false
939 tags=system.iocache.tags
942 writeback_clean=false
943 cpu_side=system.iobus.master[25]
944 mem_side=system.membus.slave[3]
946 [system.iocache.tags]
950 clk_domain=system.clk_domain
951 default_p_state=UNDEFINED
954 p_state_clk_gate_bins=20
955 p_state_clk_gate_max=1000000000000
956 p_state_clk_gate_min=1000
958 sequential_access=false
964 addr_ranges=0:18446744073709551615
966 clk_domain=system.cpu_clk_domain
967 clusivity=mostly_incl
968 default_p_state=UNDEFINED
969 demand_mshr_reserve=1
975 p_state_clk_gate_bins=20
976 p_state_clk_gate_max=1000000000000
977 p_state_clk_gate_min=1000
979 prefetch_on_access=false
982 sequential_access=false
988 writeback_clean=false
989 cpu_side=system.toL2Bus.master[0]
990 mem_side=system.membus.slave[2]
996 clk_domain=system.cpu_clk_domain
997 default_p_state=UNDEFINED
1000 p_state_clk_gate_bins=20
1001 p_state_clk_gate_max=1000000000000
1002 p_state_clk_gate_min=1000
1004 sequential_access=false
1009 children=badaddr_responder snoop_filter
1010 clk_domain=system.clk_domain
1011 default_p_state=UNDEFINED
1015 p_state_clk_gate_bins=20
1016 p_state_clk_gate_max=1000000000000
1017 p_state_clk_gate_min=1000
1018 point_of_coherency=true
1021 snoop_filter=system.membus.snoop_filter
1022 snoop_response_latency=4
1024 use_default_range=false
1026 default=system.membus.badaddr_responder.pio
1027 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1028 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1030 [system.membus.badaddr_responder]
1032 clk_domain=system.clk_domain
1033 default_p_state=UNDEFINED
1036 p_state_clk_gate_bins=20
1037 p_state_clk_gate_max=1000000000000
1038 p_state_clk_gate_min=1000
1045 ret_data32=4294967295
1046 ret_data64=18446744073709551615
1051 pio=system.membus.default
1053 [system.membus.snoop_filter]
1057 max_capacity=8388608
1063 clk_domain=system.clk_domain
1064 conf_table_reported=true
1065 default_p_state=UNDEFINED
1071 p_state_clk_gate_bins=20
1072 p_state_clk_gate_max=1000000000000
1073 p_state_clk_gate_min=1000
1075 range=2147483648:2415919103
1076 port=system.membus.master[5]
1080 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1082 intrctrl=system.intrctrl
1085 [system.realview.aaci_fake]
1088 clk_domain=system.clk_domain
1089 default_p_state=UNDEFINED
1092 p_state_clk_gate_bins=20
1093 p_state_clk_gate_max=1000000000000
1094 p_state_clk_gate_min=1000
1099 pio=system.iobus.master[18]
1101 [system.realview.cf_ctrl]
1140 MSICAPMsgUpperAddr=0
1141 MSICAPNextCapability=0
1145 MSIXCAPNextCapability=0
1155 PMCAPNextCapability=0
1160 PXCAPDevCapabilities=0
1167 PXCAPNextCapability=0
1175 clk_domain=system.clk_domain
1176 config_latency=20000
1178 default_p_state=UNDEFINED
1181 host=system.realview.pci_host
1183 p_state_clk_gate_bins=20
1184 p_state_clk_gate_max=1000000000000
1185 p_state_clk_gate_min=1000
1192 dma=system.iobus.slave[2]
1193 pio=system.iobus.master[9]
1195 [system.realview.clcd]
1198 clk_domain=system.clk_domain
1199 default_p_state=UNDEFINED
1202 gic=system.realview.gic
1204 p_state_clk_gate_bins=20
1205 p_state_clk_gate_max=1000000000000
1206 p_state_clk_gate_min=1000
1212 vnc=system.vncserver
1213 dma=system.iobus.slave[1]
1214 pio=system.iobus.master[5]
1216 [system.realview.dcc]
1218 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1222 [system.realview.dcc.osc_cpu]
1228 parent=system.realview.realview_io
1231 voltage_domain=system.voltage_domain
1233 [system.realview.dcc.osc_ddr]
1239 parent=system.realview.realview_io
1242 voltage_domain=system.voltage_domain
1244 [system.realview.dcc.osc_hsbm]
1250 parent=system.realview.realview_io
1253 voltage_domain=system.voltage_domain
1255 [system.realview.dcc.osc_pxl]
1261 parent=system.realview.realview_io
1264 voltage_domain=system.voltage_domain
1266 [system.realview.dcc.osc_smb]
1272 parent=system.realview.realview_io
1275 voltage_domain=system.voltage_domain
1277 [system.realview.dcc.osc_sys]
1283 parent=system.realview.realview_io
1286 voltage_domain=system.voltage_domain
1288 [system.realview.energy_ctrl]
1290 clk_domain=system.clk_domain
1291 default_p_state=UNDEFINED
1292 dvfs_handler=system.dvfs_handler
1294 p_state_clk_gate_bins=20
1295 p_state_clk_gate_max=1000000000000
1296 p_state_clk_gate_min=1000
1301 pio=system.iobus.master[22]
1303 [system.realview.ethernet]
1342 MSICAPMsgUpperAddr=0
1343 MSICAPNextCapability=0
1347 MSIXCAPNextCapability=0
1357 PMCAPNextCapability=0
1362 PXCAPDevCapabilities=0
1369 PXCAPNextCapability=0
1375 SubsystemVendorID=32902
1377 clk_domain=system.clk_domain
1378 config_latency=20000
1379 default_p_state=UNDEFINED
1381 fetch_comp_delay=10000
1383 hardware_address=00:90:00:00:00:01
1384 host=system.realview.pci_host
1385 p_state_clk_gate_bins=20
1386 p_state_clk_gate_max=1000000000000
1387 p_state_clk_gate_min=1000
1395 rx_desc_cache_size=64
1399 tx_desc_cache_size=64
1404 dma=system.iobus.slave[4]
1405 pio=system.iobus.master[24]
1407 [system.realview.generic_timer]
1410 gic=system.realview.gic
1415 [system.realview.gic]
1417 clk_domain=system.clk_domain
1420 default_p_state=UNDEFINED
1422 dist_pio_delay=10000
1424 gem5_extensions=true
1427 p_state_clk_gate_bins=20
1428 p_state_clk_gate_max=1000000000000
1429 p_state_clk_gate_min=1000
1430 platform=system.realview
1433 pio=system.membus.master[2]
1435 [system.realview.hdlcd]
1438 clk_domain=system.clk_domain
1439 default_p_state=UNDEFINED
1442 gic=system.realview.gic
1444 p_state_clk_gate_bins=20
1445 p_state_clk_gate_max=1000000000000
1446 p_state_clk_gate_min=1000
1449 pixel_buffer_size=2048
1452 pxl_clk=system.realview.dcc.osc_pxl
1454 vnc=system.vncserver
1455 workaround_dma_line_count=true
1456 workaround_swap_rb=true
1457 dma=system.membus.slave[0]
1458 pio=system.iobus.master[6]
1460 [system.realview.ide]
1499 MSICAPMsgUpperAddr=0
1500 MSICAPNextCapability=0
1504 MSIXCAPNextCapability=0
1514 PMCAPNextCapability=0
1519 PXCAPDevCapabilities=0
1526 PXCAPNextCapability=0
1534 clk_domain=system.clk_domain
1535 config_latency=20000
1537 default_p_state=UNDEFINED
1540 host=system.realview.pci_host
1542 p_state_clk_gate_bins=20
1543 p_state_clk_gate_max=1000000000000
1544 p_state_clk_gate_min=1000
1551 dma=system.iobus.slave[3]
1552 pio=system.iobus.master[23]
1554 [system.realview.kmi0]
1557 clk_domain=system.clk_domain
1558 default_p_state=UNDEFINED
1560 gic=system.realview.gic
1564 p_state_clk_gate_bins=20
1565 p_state_clk_gate_max=1000000000000
1566 p_state_clk_gate_min=1000
1571 vnc=system.vncserver
1572 pio=system.iobus.master[7]
1574 [system.realview.kmi1]
1577 clk_domain=system.clk_domain
1578 default_p_state=UNDEFINED
1580 gic=system.realview.gic
1584 p_state_clk_gate_bins=20
1585 p_state_clk_gate_max=1000000000000
1586 p_state_clk_gate_min=1000
1591 vnc=system.vncserver
1592 pio=system.iobus.master[8]
1594 [system.realview.l2x0_fake]
1596 clk_domain=system.clk_domain
1597 default_p_state=UNDEFINED
1600 p_state_clk_gate_bins=20
1601 p_state_clk_gate_max=1000000000000
1602 p_state_clk_gate_min=1000
1609 ret_data32=4294967295
1610 ret_data64=18446744073709551615
1615 pio=system.iobus.master[12]
1617 [system.realview.lan_fake]
1619 clk_domain=system.clk_domain
1620 default_p_state=UNDEFINED
1623 p_state_clk_gate_bins=20
1624 p_state_clk_gate_max=1000000000000
1625 p_state_clk_gate_min=1000
1632 ret_data32=4294967295
1633 ret_data64=18446744073709551615
1638 pio=system.iobus.master[19]
1640 [system.realview.local_cpu_timer]
1642 clk_domain=system.clk_domain
1643 default_p_state=UNDEFINED
1645 gic=system.realview.gic
1648 p_state_clk_gate_bins=20
1649 p_state_clk_gate_max=1000000000000
1650 p_state_clk_gate_min=1000
1655 pio=system.membus.master[4]
1657 [system.realview.mcc]
1659 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1663 [system.realview.mcc.osc_clcd]
1669 parent=system.realview.realview_io
1672 voltage_domain=system.voltage_domain
1674 [system.realview.mcc.osc_mcc]
1680 parent=system.realview.realview_io
1683 voltage_domain=system.voltage_domain
1685 [system.realview.mcc.osc_peripheral]
1691 parent=system.realview.realview_io
1694 voltage_domain=system.voltage_domain
1696 [system.realview.mcc.osc_system_bus]
1702 parent=system.realview.realview_io
1705 voltage_domain=system.voltage_domain
1707 [system.realview.mcc.temp_crtl]
1708 type=RealViewTemperatureSensor
1712 parent=system.realview.realview_io
1717 [system.realview.mmc_fake]
1720 clk_domain=system.clk_domain
1721 default_p_state=UNDEFINED
1724 p_state_clk_gate_bins=20
1725 p_state_clk_gate_max=1000000000000
1726 p_state_clk_gate_min=1000
1731 pio=system.iobus.master[21]
1733 [system.realview.nvmem]
1736 clk_domain=system.clk_domain
1737 conf_table_reported=true
1738 default_p_state=UNDEFINED
1744 p_state_clk_gate_bins=20
1745 p_state_clk_gate_max=1000000000000
1746 p_state_clk_gate_min=1000
1749 port=system.membus.master[1]
1751 [system.realview.pci_host]
1753 clk_domain=system.clk_domain
1757 default_p_state=UNDEFINED
1759 p_state_clk_gate_bins=20
1760 p_state_clk_gate_max=1000000000000
1761 p_state_clk_gate_min=1000
1764 pci_pio_base=788529152
1765 platform=system.realview
1768 pio=system.iobus.master[2]
1770 [system.realview.realview_io]
1772 clk_domain=system.clk_domain
1773 default_p_state=UNDEFINED
1776 p_state_clk_gate_bins=20
1777 p_state_clk_gate_max=1000000000000
1778 p_state_clk_gate_min=1000
1785 pio=system.iobus.master[1]
1787 [system.realview.rtc]
1790 clk_domain=system.clk_domain
1791 default_p_state=UNDEFINED
1793 gic=system.realview.gic
1796 p_state_clk_gate_bins=20
1797 p_state_clk_gate_max=1000000000000
1798 p_state_clk_gate_min=1000
1803 time=Thu Jan 1 00:00:00 2009
1804 pio=system.iobus.master[10]
1806 [system.realview.sp810_fake]
1809 clk_domain=system.clk_domain
1810 default_p_state=UNDEFINED
1813 p_state_clk_gate_bins=20
1814 p_state_clk_gate_max=1000000000000
1815 p_state_clk_gate_min=1000
1820 pio=system.iobus.master[16]
1822 [system.realview.timer0]
1825 clk_domain=system.clk_domain
1828 default_p_state=UNDEFINED
1830 gic=system.realview.gic
1833 p_state_clk_gate_bins=20
1834 p_state_clk_gate_max=1000000000000
1835 p_state_clk_gate_min=1000
1840 pio=system.iobus.master[3]
1842 [system.realview.timer1]
1845 clk_domain=system.clk_domain
1848 default_p_state=UNDEFINED
1850 gic=system.realview.gic
1853 p_state_clk_gate_bins=20
1854 p_state_clk_gate_max=1000000000000
1855 p_state_clk_gate_min=1000
1860 pio=system.iobus.master[4]
1862 [system.realview.uart]
1864 clk_domain=system.clk_domain
1865 default_p_state=UNDEFINED
1868 gic=system.realview.gic
1871 p_state_clk_gate_bins=20
1872 p_state_clk_gate_max=1000000000000
1873 p_state_clk_gate_min=1000
1876 platform=system.realview
1879 terminal=system.terminal
1880 pio=system.iobus.master[0]
1882 [system.realview.uart1_fake]
1885 clk_domain=system.clk_domain
1886 default_p_state=UNDEFINED
1889 p_state_clk_gate_bins=20
1890 p_state_clk_gate_max=1000000000000
1891 p_state_clk_gate_min=1000
1896 pio=system.iobus.master[13]
1898 [system.realview.uart2_fake]
1901 clk_domain=system.clk_domain
1902 default_p_state=UNDEFINED
1905 p_state_clk_gate_bins=20
1906 p_state_clk_gate_max=1000000000000
1907 p_state_clk_gate_min=1000
1912 pio=system.iobus.master[14]
1914 [system.realview.uart3_fake]
1917 clk_domain=system.clk_domain
1918 default_p_state=UNDEFINED
1921 p_state_clk_gate_bins=20
1922 p_state_clk_gate_max=1000000000000
1923 p_state_clk_gate_min=1000
1928 pio=system.iobus.master[15]
1930 [system.realview.usb_fake]
1932 clk_domain=system.clk_domain
1933 default_p_state=UNDEFINED
1936 p_state_clk_gate_bins=20
1937 p_state_clk_gate_max=1000000000000
1938 p_state_clk_gate_min=1000
1945 ret_data32=4294967295
1946 ret_data64=18446744073709551615
1951 pio=system.iobus.master[20]
1953 [system.realview.vgic]
1955 clk_domain=system.clk_domain
1956 default_p_state=UNDEFINED
1958 gic=system.realview.gic
1960 p_state_clk_gate_bins=20
1961 p_state_clk_gate_max=1000000000000
1962 p_state_clk_gate_min=1000
1964 platform=system.realview
1969 pio=system.membus.master[3]
1971 [system.realview.vram]
1974 clk_domain=system.clk_domain
1975 conf_table_reported=false
1976 default_p_state=UNDEFINED
1982 p_state_clk_gate_bins=20
1983 p_state_clk_gate_max=1000000000000
1984 p_state_clk_gate_min=1000
1986 range=402653184:436207615
1987 port=system.iobus.master[11]
1989 [system.realview.watchdog_fake]
1992 clk_domain=system.clk_domain
1993 default_p_state=UNDEFINED
1996 p_state_clk_gate_bins=20
1997 p_state_clk_gate_max=1000000000000
1998 p_state_clk_gate_min=1000
2003 pio=system.iobus.master[17]
2008 intr_control=system.intrctrl
2015 children=snoop_filter
2016 clk_domain=system.cpu_clk_domain
2017 default_p_state=UNDEFINED
2021 p_state_clk_gate_bins=20
2022 p_state_clk_gate_max=1000000000000
2023 p_state_clk_gate_min=1000
2024 point_of_coherency=false
2027 snoop_filter=system.toL2Bus.snoop_filter
2028 snoop_response_latency=1
2030 use_default_range=false
2032 master=system.l2c.cpu_side
2033 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
2035 [system.toL2Bus.snoop_filter]
2039 max_capacity=8388608
2049 [system.voltage_domain]