tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM64
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu]
 114 type=TimingSimpleCPU
 115 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=Null
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 default_p_state=UNDEFINED
 121 do_checkpoint_insts=true
 122 do_quiesce=true
 123 do_statistics_insts=true
 124 dstage2_mmu=system.cpu.dstage2_mmu
 125 dtb=system.cpu.dtb
 126 eventq_index=0
 127 function_trace=false
 128 function_trace_start=0
 129 interrupts=system.cpu.interrupts
 130 isa=system.cpu.isa
 131 istage2_mmu=system.cpu.istage2_mmu
 132 itb=system.cpu.itb
 133 max_insts_all_threads=0
 134 max_insts_any_thread=0
 135 max_loads_all_threads=0
 136 max_loads_any_thread=0
 137 numThreads=1
 138 p_state_clk_gate_bins=20
 139 p_state_clk_gate_max=1000000000000
 140 p_state_clk_gate_min=1000
 141 power_model=Null
 142 profile=0
 143 progress_interval=0
 144 simpoint_start_insts=
 145 socket_id=0
 146 switched_out=false
 147 system=system
 148 tracer=system.cpu.tracer
 149 workload=
 150 dcache_port=system.cpu.dcache.cpu_side
 151 icache_port=system.cpu.icache.cpu_side
 152
 153 [system.cpu.dcache]
 154 type=Cache
 155 children=tags
 156 addr_ranges=0:18446744073709551615:0:0:0:0
 157 assoc=4
 158 clk_domain=system.cpu_clk_domain
 159 clusivity=mostly_incl
 160 default_p_state=UNDEFINED
 161 demand_mshr_reserve=1
 162 eventq_index=0
 163 hit_latency=2
 164 is_read_only=false
 165 max_miss_count=0
 166 mshrs=4
 167 p_state_clk_gate_bins=20
 168 p_state_clk_gate_max=1000000000000
 169 p_state_clk_gate_min=1000
 170 power_model=Null
 171 prefetch_on_access=false
 172 prefetcher=Null
 173 response_latency=2
 174 sequential_access=false
 175 size=32768
 176 system=system
 177 tags=system.cpu.dcache.tags
 178 tgts_per_mshr=20
 179 write_buffers=8
 180 writeback_clean=false
 181 cpu_side=system.cpu.dcache_port
 182 mem_side=system.cpu.toL2Bus.slave[1]
 183
 184 [system.cpu.dcache.tags]
 185 type=LRU
 186 assoc=4
 187 block_size=64
 188 clk_domain=system.cpu_clk_domain
 189 default_p_state=UNDEFINED
 190 eventq_index=0
 191 hit_latency=2
 192 p_state_clk_gate_bins=20
 193 p_state_clk_gate_max=1000000000000
 194 p_state_clk_gate_min=1000
 195 power_model=Null
 196 sequential_access=false
 197 size=32768
 198
 199 [system.cpu.dstage2_mmu]
 200 type=ArmStage2MMU
 201 children=stage2_tlb
 202 eventq_index=0
 203 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 204 sys=system
 205 tlb=system.cpu.dtb
 206
 207 [system.cpu.dstage2_mmu.stage2_tlb]
 208 type=ArmTLB
 209 children=walker
 210 eventq_index=0
 211 is_stage2=true
 212 size=32
 213 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 214
 215 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 216 type=ArmTableWalker
 217 clk_domain=system.cpu_clk_domain
 218 default_p_state=UNDEFINED
 219 eventq_index=0
 220 is_stage2=true
 221 num_squash_per_cycle=2
 222 p_state_clk_gate_bins=20
 223 p_state_clk_gate_max=1000000000000
 224 p_state_clk_gate_min=1000
 225 power_model=Null
 226 sys=system
 227
 228 [system.cpu.dtb]
 229 type=ArmTLB
 230 children=walker
 231 eventq_index=0
 232 is_stage2=false
 233 size=64
 234 walker=system.cpu.dtb.walker
 235
 236 [system.cpu.dtb.walker]
 237 type=ArmTableWalker
 238 clk_domain=system.cpu_clk_domain
 239 default_p_state=UNDEFINED
 240 eventq_index=0
 241 is_stage2=false
 242 num_squash_per_cycle=2
 243 p_state_clk_gate_bins=20
 244 p_state_clk_gate_max=1000000000000
 245 p_state_clk_gate_min=1000
 246 power_model=Null
 247 sys=system
 248 port=system.cpu.toL2Bus.slave[3]
 249
 250 [system.cpu.icache]
 251 type=Cache
 252 children=tags
 253 addr_ranges=0:18446744073709551615:0:0:0:0
 254 assoc=1
 255 clk_domain=system.cpu_clk_domain
 256 clusivity=mostly_incl
 257 default_p_state=UNDEFINED
 258 demand_mshr_reserve=1
 259 eventq_index=0
 260 hit_latency=2
 261 is_read_only=true
 262 max_miss_count=0
 263 mshrs=4
 264 p_state_clk_gate_bins=20
 265 p_state_clk_gate_max=1000000000000
 266 p_state_clk_gate_min=1000
 267 power_model=Null
 268 prefetch_on_access=false
 269 prefetcher=Null
 270 response_latency=2
 271 sequential_access=false
 272 size=32768
 273 system=system
 274 tags=system.cpu.icache.tags
 275 tgts_per_mshr=20
 276 write_buffers=8
 277 writeback_clean=true
 278 cpu_side=system.cpu.icache_port
 279 mem_side=system.cpu.toL2Bus.slave[0]
 280
 281 [system.cpu.icache.tags]
 282 type=LRU
 283 assoc=1
 284 block_size=64
 285 clk_domain=system.cpu_clk_domain
 286 default_p_state=UNDEFINED
 287 eventq_index=0
 288 hit_latency=2
 289 p_state_clk_gate_bins=20
 290 p_state_clk_gate_max=1000000000000
 291 p_state_clk_gate_min=1000
 292 power_model=Null
 293 sequential_access=false
 294 size=32768
 295
 296 [system.cpu.interrupts]
 297 type=ArmInterrupts
 298 eventq_index=0
 299
 300 [system.cpu.isa]
 301 type=ArmISA
 302 decoderFlavour=Generic
 303 eventq_index=0
 304 fpsid=1090793632
 305 id_aa64afr0_el1=0
 306 id_aa64afr1_el1=0
 307 id_aa64dfr0_el1=1052678
 308 id_aa64dfr1_el1=0
 309 id_aa64isar0_el1=0
 310 id_aa64isar1_el1=0
 311 id_aa64mmfr0_el1=15728642
 312 id_aa64mmfr1_el1=0
 313 id_aa64pfr0_el1=34
 314 id_aa64pfr1_el1=0
 315 id_isar0=34607377
 316 id_isar1=34677009
 317 id_isar2=555950401
 318 id_isar3=17899825
 319 id_isar4=268501314
 320 id_isar5=0
 321 id_mmfr0=270536963
 322 id_mmfr1=0
 323 id_mmfr2=19070976
 324 id_mmfr3=34611729
 325 id_pfr0=49
 326 id_pfr1=4113
 327 midr=1091551472
 328 pmu=Null
 329 system=system
 330
 331 [system.cpu.istage2_mmu]
 332 type=ArmStage2MMU
 333 children=stage2_tlb
 334 eventq_index=0
 335 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 336 sys=system
 337 tlb=system.cpu.itb
 338
 339 [system.cpu.istage2_mmu.stage2_tlb]
 340 type=ArmTLB
 341 children=walker
 342 eventq_index=0
 343 is_stage2=true
 344 size=32
 345 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 346
 347 [system.cpu.istage2_mmu.stage2_tlb.walker]
 348 type=ArmTableWalker
 349 clk_domain=system.cpu_clk_domain
 350 default_p_state=UNDEFINED
 351 eventq_index=0
 352 is_stage2=true
 353 num_squash_per_cycle=2
 354 p_state_clk_gate_bins=20
 355 p_state_clk_gate_max=1000000000000
 356 p_state_clk_gate_min=1000
 357 power_model=Null
 358 sys=system
 359
 360 [system.cpu.itb]
 361 type=ArmTLB
 362 children=walker
 363 eventq_index=0
 364 is_stage2=false
 365 size=64
 366 walker=system.cpu.itb.walker
 367
 368 [system.cpu.itb.walker]
 369 type=ArmTableWalker
 370 clk_domain=system.cpu_clk_domain
 371 default_p_state=UNDEFINED
 372 eventq_index=0
 373 is_stage2=false
 374 num_squash_per_cycle=2
 375 p_state_clk_gate_bins=20
 376 p_state_clk_gate_max=1000000000000
 377 p_state_clk_gate_min=1000
 378 power_model=Null
 379 sys=system
 380 port=system.cpu.toL2Bus.slave[2]
 381
 382 [system.cpu.l2cache]
 383 type=Cache
 384 children=tags
 385 addr_ranges=0:18446744073709551615:0:0:0:0
 386 assoc=8
 387 clk_domain=system.cpu_clk_domain
 388 clusivity=mostly_incl
 389 default_p_state=UNDEFINED
 390 demand_mshr_reserve=1
 391 eventq_index=0
 392 hit_latency=20
 393 is_read_only=false
 394 max_miss_count=0
 395 mshrs=20
 396 p_state_clk_gate_bins=20
 397 p_state_clk_gate_max=1000000000000
 398 p_state_clk_gate_min=1000
 399 power_model=Null
 400 prefetch_on_access=false
 401 prefetcher=Null
 402 response_latency=20
 403 sequential_access=false
 404 size=4194304
 405 system=system
 406 tags=system.cpu.l2cache.tags
 407 tgts_per_mshr=12
 408 write_buffers=8
 409 writeback_clean=false
 410 cpu_side=system.cpu.toL2Bus.master[0]
 411 mem_side=system.membus.slave[2]
 412
 413 [system.cpu.l2cache.tags]
 414 type=LRU
 415 assoc=8
 416 block_size=64
 417 clk_domain=system.cpu_clk_domain
 418 default_p_state=UNDEFINED
 419 eventq_index=0
 420 hit_latency=20
 421 p_state_clk_gate_bins=20
 422 p_state_clk_gate_max=1000000000000
 423 p_state_clk_gate_min=1000
 424 power_model=Null
 425 sequential_access=false
 426 size=4194304
 427
 428 [system.cpu.toL2Bus]
 429 type=CoherentXBar
 430 children=snoop_filter
 431 clk_domain=system.cpu_clk_domain
 432 default_p_state=UNDEFINED
 433 eventq_index=0
 434 forward_latency=0
 435 frontend_latency=1
 436 p_state_clk_gate_bins=20
 437 p_state_clk_gate_max=1000000000000
 438 p_state_clk_gate_min=1000
 439 point_of_coherency=false
 440 power_model=Null
 441 response_latency=1
 442 snoop_filter=system.cpu.toL2Bus.snoop_filter
 443 snoop_response_latency=1
 444 system=system
 445 use_default_range=false
 446 width=32
 447 master=system.cpu.l2cache.cpu_side
 448 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 449
 450 [system.cpu.toL2Bus.snoop_filter]
 451 type=SnoopFilter
 452 eventq_index=0
 453 lookup_latency=0
 454 max_capacity=8388608
 455 system=system
 456
 457 [system.cpu.tracer]
 458 type=ExeTracer
 459 eventq_index=0
 460
 461 [system.cpu_clk_domain]
 462 type=SrcClockDomain
 463 clock=500
 464 domain_id=-1
 465 eventq_index=0
 466 init_perf_level=0
 467 voltage_domain=system.voltage_domain
 468
 469 [system.dvfs_handler]
 470 type=DVFSHandler
 471 domains=
 472 enable=false
 473 eventq_index=0
 474 sys_clk_domain=system.clk_domain
 475 transition_latency=100000000
 476
 477 [system.intrctrl]
 478 type=IntrControl
 479 eventq_index=0
 480 sys=system
 481
 482 [system.iobus]
 483 type=NoncoherentXBar
 484 clk_domain=system.clk_domain
 485 default_p_state=UNDEFINED
 486 eventq_index=0
 487 forward_latency=1
 488 frontend_latency=2
 489 p_state_clk_gate_bins=20
 490 p_state_clk_gate_max=1000000000000
 491 p_state_clk_gate_min=1000
 492 power_model=Null
 493 response_latency=2
 494 use_default_range=false
 495 width=16
 496 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 497 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 498
 499 [system.iocache]
 500 type=Cache
 501 children=tags
 502 addr_ranges=2147483648:2415919103:0:0:0:0
 503 assoc=8
 504 clk_domain=system.clk_domain
 505 clusivity=mostly_incl
 506 default_p_state=UNDEFINED
 507 demand_mshr_reserve=1
 508 eventq_index=0
 509 hit_latency=50
 510 is_read_only=false
 511 max_miss_count=0
 512 mshrs=20
 513 p_state_clk_gate_bins=20
 514 p_state_clk_gate_max=1000000000000
 515 p_state_clk_gate_min=1000
 516 power_model=Null
 517 prefetch_on_access=false
 518 prefetcher=Null
 519 response_latency=50
 520 sequential_access=false
 521 size=1024
 522 system=system
 523 tags=system.iocache.tags
 524 tgts_per_mshr=12
 525 write_buffers=8
 526 writeback_clean=false
 527 cpu_side=system.iobus.master[25]
 528 mem_side=system.membus.slave[3]
 529
 530 [system.iocache.tags]
 531 type=LRU
 532 assoc=8
 533 block_size=64
 534 clk_domain=system.clk_domain
 535 default_p_state=UNDEFINED
 536 eventq_index=0
 537 hit_latency=50
 538 p_state_clk_gate_bins=20
 539 p_state_clk_gate_max=1000000000000
 540 p_state_clk_gate_min=1000
 541 power_model=Null
 542 sequential_access=false
 543 size=1024
 544
 545 [system.membus]
 546 type=CoherentXBar
 547 children=badaddr_responder snoop_filter
 548 clk_domain=system.clk_domain
 549 default_p_state=UNDEFINED
 550 eventq_index=0
 551 forward_latency=4
 552 frontend_latency=3
 553 p_state_clk_gate_bins=20
 554 p_state_clk_gate_max=1000000000000
 555 p_state_clk_gate_min=1000
 556 point_of_coherency=true
 557 power_model=Null
 558 response_latency=2
 559 snoop_filter=system.membus.snoop_filter
 560 snoop_response_latency=4
 561 system=system
 562 use_default_range=false
 563 width=16
 564 default=system.membus.badaddr_responder.pio
 565 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 566 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 567
 568 [system.membus.badaddr_responder]
 569 type=IsaFake
 570 clk_domain=system.clk_domain
 571 default_p_state=UNDEFINED
 572 eventq_index=0
 573 fake_mem=false
 574 p_state_clk_gate_bins=20
 575 p_state_clk_gate_max=1000000000000
 576 p_state_clk_gate_min=1000
 577 pio_addr=0
 578 pio_latency=100000
 579 pio_size=8
 580 power_model=Null
 581 ret_bad_addr=true
 582 ret_data16=65535
 583 ret_data32=4294967295
 584 ret_data64=18446744073709551615
 585 ret_data8=255
 586 system=system
 587 update_data=false
 588 warn_access=warn
 589 pio=system.membus.default
 590
 591 [system.membus.snoop_filter]
 592 type=SnoopFilter
 593 eventq_index=0
 594 lookup_latency=1
 595 max_capacity=8388608
 596 system=system
 597
 598 [system.physmem]
 599 type=DRAMCtrl
 600 IDD0=0.055000
 601 IDD02=0.000000
 602 IDD2N=0.032000
 603 IDD2N2=0.000000
 604 IDD2P0=0.000000
 605 IDD2P02=0.000000
 606 IDD2P1=0.032000
 607 IDD2P12=0.000000
 608 IDD3N=0.038000
 609 IDD3N2=0.000000
 610 IDD3P0=0.000000
 611 IDD3P02=0.000000
 612 IDD3P1=0.038000
 613 IDD3P12=0.000000
 614 IDD4R=0.157000
 615 IDD4R2=0.000000
 616 IDD4W=0.125000
 617 IDD4W2=0.000000
 618 IDD5=0.235000
 619 IDD52=0.000000
 620 IDD6=0.020000
 621 IDD62=0.000000
 622 VDD=1.500000
 623 VDD2=0.000000
 624 activation_limit=4
 625 addr_mapping=RoRaBaCoCh
 626 bank_groups_per_rank=0
 627 banks_per_rank=8
 628 burst_length=8
 629 channels=1
 630 clk_domain=system.clk_domain
 631 conf_table_reported=true
 632 default_p_state=UNDEFINED
 633 device_bus_width=8
 634 device_rowbuffer_size=1024
 635 device_size=536870912
 636 devices_per_rank=8
 637 dll=true
 638 eventq_index=0
 639 in_addr_map=true
 640 kvm_map=true
 641 max_accesses_per_row=16
 642 mem_sched_policy=frfcfs
 643 min_writes_per_switch=16
 644 null=false
 645 p_state_clk_gate_bins=20
 646 p_state_clk_gate_max=1000000000000
 647 p_state_clk_gate_min=1000
 648 page_policy=open_adaptive
 649 power_model=Null
 650 range=2147483648:2415919103:0:0:0:0
 651 ranks_per_channel=2
 652 read_buffer_size=32
 653 static_backend_latency=10000
 654 static_frontend_latency=10000
 655 tBURST=5000
 656 tCCD_L=0
 657 tCK=1250
 658 tCL=13750
 659 tCS=2500
 660 tRAS=35000
 661 tRCD=13750
 662 tREFI=7800000
 663 tRFC=260000
 664 tRP=13750
 665 tRRD=6000
 666 tRRD_L=0
 667 tRTP=7500
 668 tRTW=2500
 669 tWR=15000
 670 tWTR=7500
 671 tXAW=30000
 672 tXP=6000
 673 tXPDLL=0
 674 tXS=270000
 675 tXSDLL=0
 676 write_buffer_size=64
 677 write_high_thresh_perc=85
 678 write_low_thresh_perc=50
 679 port=system.membus.master[5]
 680
 681 [system.realview]
 682 type=RealView
 683 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 684 eventq_index=0
 685 intrctrl=system.intrctrl
 686 system=system
 687
 688 [system.realview.aaci_fake]
 689 type=AmbaFake
 690 amba_id=0
 691 clk_domain=system.clk_domain
 692 default_p_state=UNDEFINED
 693 eventq_index=0
 694 ignore_access=false
 695 p_state_clk_gate_bins=20
 696 p_state_clk_gate_max=1000000000000
 697 p_state_clk_gate_min=1000
 698 pio_addr=470024192
 699 pio_latency=100000
 700 power_model=Null
 701 system=system
 702 pio=system.iobus.master[18]
 703
 704 [system.realview.cf_ctrl]
 705 type=IdeController
 706 BAR0=471465984
 707 BAR0LegacyIO=true
 708 BAR0Size=256
 709 BAR1=471466240
 710 BAR1LegacyIO=true
 711 BAR1Size=4096
 712 BAR2=1
 713 BAR2LegacyIO=false
 714 BAR2Size=8
 715 BAR3=1
 716 BAR3LegacyIO=false
 717 BAR3Size=4
 718 BAR4=1
 719 BAR4LegacyIO=false
 720 BAR4Size=16
 721 BAR5=1
 722 BAR5LegacyIO=false
 723 BAR5Size=0
 724 BIST=0
 725 CacheLineSize=0
 726 CapabilityPtr=0
 727 CardbusCIS=0
 728 ClassCode=1
 729 Command=1
 730 DeviceID=28945
 731 ExpansionROM=0
 732 HeaderType=0
 733 InterruptLine=31
 734 InterruptPin=1
 735 LatencyTimer=0
 736 LegacyIOBase=0
 737 MSICAPBaseOffset=0
 738 MSICAPCapId=0
 739 MSICAPMaskBits=0
 740 MSICAPMsgAddr=0
 741 MSICAPMsgCtrl=0
 742 MSICAPMsgData=0
 743 MSICAPMsgUpperAddr=0
 744 MSICAPNextCapability=0
 745 MSICAPPendingBits=0
 746 MSIXCAPBaseOffset=0
 747 MSIXCAPCapId=0
 748 MSIXCAPNextCapability=0
 749 MSIXMsgCtrl=0
 750 MSIXPbaOffset=0
 751 MSIXTableOffset=0
 752 MaximumLatency=0
 753 MinimumGrant=0
 754 PMCAPBaseOffset=0
 755 PMCAPCapId=0
 756 PMCAPCapabilities=0
 757 PMCAPCtrlStatus=0
 758 PMCAPNextCapability=0
 759 PXCAPBaseOffset=0
 760 PXCAPCapId=0
 761 PXCAPCapabilities=0
 762 PXCAPDevCap2=0
 763 PXCAPDevCapabilities=0
 764 PXCAPDevCtrl=0
 765 PXCAPDevCtrl2=0
 766 PXCAPDevStatus=0
 767 PXCAPLinkCap=0
 768 PXCAPLinkCtrl=0
 769 PXCAPLinkStatus=0
 770 PXCAPNextCapability=0
 771 ProgIF=133
 772 Revision=0
 773 Status=640
 774 SubClassCode=1
 775 SubsystemID=0
 776 SubsystemVendorID=0
 777 VendorID=32902
 778 clk_domain=system.clk_domain
 779 config_latency=20000
 780 ctrl_offset=2
 781 default_p_state=UNDEFINED
 782 disks=
 783 eventq_index=0
 784 host=system.realview.pci_host
 785 io_shift=2
 786 p_state_clk_gate_bins=20
 787 p_state_clk_gate_max=1000000000000
 788 p_state_clk_gate_min=1000
 789 pci_bus=2
 790 pci_dev=0
 791 pci_func=0
 792 pio_latency=30000
 793 power_model=Null
 794 system=system
 795 dma=system.iobus.slave[2]
 796 pio=system.iobus.master[9]
 797
 798 [system.realview.clcd]
 799 type=Pl111
 800 amba_id=1315089
 801 clk_domain=system.clk_domain
 802 default_p_state=UNDEFINED
 803 enable_capture=true
 804 eventq_index=0
 805 gic=system.realview.gic
 806 int_num=46
 807 p_state_clk_gate_bins=20
 808 p_state_clk_gate_max=1000000000000
 809 p_state_clk_gate_min=1000
 810 pio_addr=471793664
 811 pio_latency=10000
 812 pixel_clock=41667
 813 power_model=Null
 814 system=system
 815 vnc=system.vncserver
 816 dma=system.iobus.slave[1]
 817 pio=system.iobus.master[5]
 818
 819 [system.realview.dcc]
 820 type=SubSystem
 821 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 822 eventq_index=0
 823 thermal_domain=Null
 824
 825 [system.realview.dcc.osc_cpu]
 826 type=RealViewOsc
 827 dcc=0
 828 device=0
 829 eventq_index=0
 830 freq=16667
 831 parent=system.realview.realview_io
 832 position=0
 833 site=1
 834 voltage_domain=system.voltage_domain
 835
 836 [system.realview.dcc.osc_ddr]
 837 type=RealViewOsc
 838 dcc=0
 839 device=8
 840 eventq_index=0
 841 freq=25000
 842 parent=system.realview.realview_io
 843 position=0
 844 site=1
 845 voltage_domain=system.voltage_domain
 846
 847 [system.realview.dcc.osc_hsbm]
 848 type=RealViewOsc
 849 dcc=0
 850 device=4
 851 eventq_index=0
 852 freq=25000
 853 parent=system.realview.realview_io
 854 position=0
 855 site=1
 856 voltage_domain=system.voltage_domain
 857
 858 [system.realview.dcc.osc_pxl]
 859 type=RealViewOsc
 860 dcc=0
 861 device=5
 862 eventq_index=0
 863 freq=42105
 864 parent=system.realview.realview_io
 865 position=0
 866 site=1
 867 voltage_domain=system.voltage_domain
 868
 869 [system.realview.dcc.osc_smb]
 870 type=RealViewOsc
 871 dcc=0
 872 device=6
 873 eventq_index=0
 874 freq=20000
 875 parent=system.realview.realview_io
 876 position=0
 877 site=1
 878 voltage_domain=system.voltage_domain
 879
 880 [system.realview.dcc.osc_sys]
 881 type=RealViewOsc
 882 dcc=0
 883 device=7
 884 eventq_index=0
 885 freq=16667
 886 parent=system.realview.realview_io
 887 position=0
 888 site=1
 889 voltage_domain=system.voltage_domain
 890
 891 [system.realview.energy_ctrl]
 892 type=EnergyCtrl
 893 clk_domain=system.clk_domain
 894 default_p_state=UNDEFINED
 895 dvfs_handler=system.dvfs_handler
 896 eventq_index=0
 897 p_state_clk_gate_bins=20
 898 p_state_clk_gate_max=1000000000000
 899 p_state_clk_gate_min=1000
 900 pio_addr=470286336
 901 pio_latency=100000
 902 power_model=Null
 903 system=system
 904 pio=system.iobus.master[22]
 905
 906 [system.realview.ethernet]
 907 type=IGbE
 908 BAR0=0
 909 BAR0LegacyIO=false
 910 BAR0Size=131072
 911 BAR1=0
 912 BAR1LegacyIO=false
 913 BAR1Size=0
 914 BAR2=0
 915 BAR2LegacyIO=false
 916 BAR2Size=0
 917 BAR3=0
 918 BAR3LegacyIO=false
 919 BAR3Size=0
 920 BAR4=0
 921 BAR4LegacyIO=false
 922 BAR4Size=0
 923 BAR5=0
 924 BAR5LegacyIO=false
 925 BAR5Size=0
 926 BIST=0
 927 CacheLineSize=0
 928 CapabilityPtr=0
 929 CardbusCIS=0
 930 ClassCode=2
 931 Command=0
 932 DeviceID=4213
 933 ExpansionROM=0
 934 HeaderType=0
 935 InterruptLine=1
 936 InterruptPin=1
 937 LatencyTimer=0
 938 LegacyIOBase=0
 939 MSICAPBaseOffset=0
 940 MSICAPCapId=0
 941 MSICAPMaskBits=0
 942 MSICAPMsgAddr=0
 943 MSICAPMsgCtrl=0
 944 MSICAPMsgData=0
 945 MSICAPMsgUpperAddr=0
 946 MSICAPNextCapability=0
 947 MSICAPPendingBits=0
 948 MSIXCAPBaseOffset=0
 949 MSIXCAPCapId=0
 950 MSIXCAPNextCapability=0
 951 MSIXMsgCtrl=0
 952 MSIXPbaOffset=0
 953 MSIXTableOffset=0
 954 MaximumLatency=0
 955 MinimumGrant=255
 956 PMCAPBaseOffset=0
 957 PMCAPCapId=0
 958 PMCAPCapabilities=0
 959 PMCAPCtrlStatus=0
 960 PMCAPNextCapability=0
 961 PXCAPBaseOffset=0
 962 PXCAPCapId=0
 963 PXCAPCapabilities=0
 964 PXCAPDevCap2=0
 965 PXCAPDevCapabilities=0
 966 PXCAPDevCtrl=0
 967 PXCAPDevCtrl2=0
 968 PXCAPDevStatus=0
 969 PXCAPLinkCap=0
 970 PXCAPLinkCtrl=0
 971 PXCAPLinkStatus=0
 972 PXCAPNextCapability=0
 973 ProgIF=0
 974 Revision=0
 975 Status=0
 976 SubClassCode=0
 977 SubsystemID=4104
 978 SubsystemVendorID=32902
 979 VendorID=32902
 980 clk_domain=system.clk_domain
 981 config_latency=20000
 982 default_p_state=UNDEFINED
 983 eventq_index=0
 984 fetch_comp_delay=10000
 985 fetch_delay=10000
 986 hardware_address=00:90:00:00:00:01
 987 host=system.realview.pci_host
 988 p_state_clk_gate_bins=20
 989 p_state_clk_gate_max=1000000000000
 990 p_state_clk_gate_min=1000
 991 pci_bus=0
 992 pci_dev=0
 993 pci_func=0
 994 phy_epid=896
 995 phy_pid=680
 996 pio_latency=30000
 997 power_model=Null
 998 rx_desc_cache_size=64
 999 rx_fifo_size=393216
1000 rx_write_delay=0
1001 system=system
1002 tx_desc_cache_size=64
1003 tx_fifo_size=393216
1004 tx_read_delay=0
1005 wb_comp_delay=10000
1006 wb_delay=10000
1007 dma=system.iobus.slave[4]
1008 pio=system.iobus.master[24]
1009
1010 [system.realview.generic_timer]
1011 type=GenericTimer
1012 eventq_index=0
1013 gic=system.realview.gic
1014 int_phys=29
1015 int_virt=27
1016 system=system
1017
1018 [system.realview.gic]
1019 type=Pl390
1020 clk_domain=system.clk_domain
1021 cpu_addr=738205696
1022 cpu_pio_delay=10000
1023 default_p_state=UNDEFINED
1024 dist_addr=738201600
1025 dist_pio_delay=10000
1026 eventq_index=0
1027 gem5_extensions=false
1028 int_latency=10000
1029 it_lines=128
1030 p_state_clk_gate_bins=20
1031 p_state_clk_gate_max=1000000000000
1032 p_state_clk_gate_min=1000
1033 platform=system.realview
1034 power_model=Null
1035 system=system
1036 pio=system.membus.master[2]
1037
1038 [system.realview.hdlcd]
1039 type=HDLcd
1040 amba_id=1314816
1041 clk_domain=system.clk_domain
1042 default_p_state=UNDEFINED
1043 enable_capture=true
1044 eventq_index=0
1045 gic=system.realview.gic
1046 int_num=117
1047 p_state_clk_gate_bins=20
1048 p_state_clk_gate_max=1000000000000
1049 p_state_clk_gate_min=1000
1050 pio_addr=721420288
1051 pio_latency=10000
1052 pixel_buffer_size=2048
1053 pixel_chunk=32
1054 power_model=Null
1055 pxl_clk=system.realview.dcc.osc_pxl
1056 system=system
1057 vnc=system.vncserver
1058 workaround_dma_line_count=true
1059 workaround_swap_rb=true
1060 dma=system.membus.slave[0]
1061 pio=system.iobus.master[6]
1062
1063 [system.realview.ide]
1064 type=IdeController
1065 BAR0=1
1066 BAR0LegacyIO=false
1067 BAR0Size=8
1068 BAR1=1
1069 BAR1LegacyIO=false
1070 BAR1Size=4
1071 BAR2=1
1072 BAR2LegacyIO=false
1073 BAR2Size=8
1074 BAR3=1
1075 BAR3LegacyIO=false
1076 BAR3Size=4
1077 BAR4=1
1078 BAR4LegacyIO=false
1079 BAR4Size=16
1080 BAR5=1
1081 BAR5LegacyIO=false
1082 BAR5Size=0
1083 BIST=0
1084 CacheLineSize=0
1085 CapabilityPtr=0
1086 CardbusCIS=0
1087 ClassCode=1
1088 Command=0
1089 DeviceID=28945
1090 ExpansionROM=0
1091 HeaderType=0
1092 InterruptLine=2
1093 InterruptPin=2
1094 LatencyTimer=0
1095 LegacyIOBase=0
1096 MSICAPBaseOffset=0
1097 MSICAPCapId=0
1098 MSICAPMaskBits=0
1099 MSICAPMsgAddr=0
1100 MSICAPMsgCtrl=0
1101 MSICAPMsgData=0
1102 MSICAPMsgUpperAddr=0
1103 MSICAPNextCapability=0
1104 MSICAPPendingBits=0
1105 MSIXCAPBaseOffset=0
1106 MSIXCAPCapId=0
1107 MSIXCAPNextCapability=0
1108 MSIXMsgCtrl=0
1109 MSIXPbaOffset=0
1110 MSIXTableOffset=0
1111 MaximumLatency=0
1112 MinimumGrant=0
1113 PMCAPBaseOffset=0
1114 PMCAPCapId=0
1115 PMCAPCapabilities=0
1116 PMCAPCtrlStatus=0
1117 PMCAPNextCapability=0
1118 PXCAPBaseOffset=0
1119 PXCAPCapId=0
1120 PXCAPCapabilities=0
1121 PXCAPDevCap2=0
1122 PXCAPDevCapabilities=0
1123 PXCAPDevCtrl=0
1124 PXCAPDevCtrl2=0
1125 PXCAPDevStatus=0
1126 PXCAPLinkCap=0
1127 PXCAPLinkCtrl=0
1128 PXCAPLinkStatus=0
1129 PXCAPNextCapability=0
1130 ProgIF=133
1131 Revision=0
1132 Status=640
1133 SubClassCode=1
1134 SubsystemID=0
1135 SubsystemVendorID=0
1136 VendorID=32902
1137 clk_domain=system.clk_domain
1138 config_latency=20000
1139 ctrl_offset=0
1140 default_p_state=UNDEFINED
1141 disks=system.cf0
1142 eventq_index=0
1143 host=system.realview.pci_host
1144 io_shift=0
1145 p_state_clk_gate_bins=20
1146 p_state_clk_gate_max=1000000000000
1147 p_state_clk_gate_min=1000
1148 pci_bus=0
1149 pci_dev=1
1150 pci_func=0
1151 pio_latency=30000
1152 power_model=Null
1153 system=system
1154 dma=system.iobus.slave[3]
1155 pio=system.iobus.master[23]
1156
1157 [system.realview.kmi0]
1158 type=Pl050
1159 amba_id=1314896
1160 clk_domain=system.clk_domain
1161 default_p_state=UNDEFINED
1162 eventq_index=0
1163 gic=system.realview.gic
1164 int_delay=1000000
1165 int_num=44
1166 is_mouse=false
1167 p_state_clk_gate_bins=20
1168 p_state_clk_gate_max=1000000000000
1169 p_state_clk_gate_min=1000
1170 pio_addr=470155264
1171 pio_latency=100000
1172 power_model=Null
1173 system=system
1174 vnc=system.vncserver
1175 pio=system.iobus.master[7]
1176
1177 [system.realview.kmi1]
1178 type=Pl050
1179 amba_id=1314896
1180 clk_domain=system.clk_domain
1181 default_p_state=UNDEFINED
1182 eventq_index=0
1183 gic=system.realview.gic
1184 int_delay=1000000
1185 int_num=45
1186 is_mouse=true
1187 p_state_clk_gate_bins=20
1188 p_state_clk_gate_max=1000000000000
1189 p_state_clk_gate_min=1000
1190 pio_addr=470220800
1191 pio_latency=100000
1192 power_model=Null
1193 system=system
1194 vnc=system.vncserver
1195 pio=system.iobus.master[8]
1196
1197 [system.realview.l2x0_fake]
1198 type=IsaFake
1199 clk_domain=system.clk_domain
1200 default_p_state=UNDEFINED
1201 eventq_index=0
1202 fake_mem=false
1203 p_state_clk_gate_bins=20
1204 p_state_clk_gate_max=1000000000000
1205 p_state_clk_gate_min=1000
1206 pio_addr=739246080
1207 pio_latency=100000
1208 pio_size=4095
1209 power_model=Null
1210 ret_bad_addr=false
1211 ret_data16=65535
1212 ret_data32=4294967295
1213 ret_data64=18446744073709551615
1214 ret_data8=255
1215 system=system
1216 update_data=false
1217 warn_access=
1218 pio=system.iobus.master[12]
1219
1220 [system.realview.lan_fake]
1221 type=IsaFake
1222 clk_domain=system.clk_domain
1223 default_p_state=UNDEFINED
1224 eventq_index=0
1225 fake_mem=false
1226 p_state_clk_gate_bins=20
1227 p_state_clk_gate_max=1000000000000
1228 p_state_clk_gate_min=1000
1229 pio_addr=436207616
1230 pio_latency=100000
1231 pio_size=65535
1232 power_model=Null
1233 ret_bad_addr=false
1234 ret_data16=65535
1235 ret_data32=4294967295
1236 ret_data64=18446744073709551615
1237 ret_data8=255
1238 system=system
1239 update_data=false
1240 warn_access=
1241 pio=system.iobus.master[19]
1242
1243 [system.realview.local_cpu_timer]
1244 type=CpuLocalTimer
1245 clk_domain=system.clk_domain
1246 default_p_state=UNDEFINED
1247 eventq_index=0
1248 gic=system.realview.gic
1249 int_num_timer=29
1250 int_num_watchdog=30
1251 p_state_clk_gate_bins=20
1252 p_state_clk_gate_max=1000000000000
1253 p_state_clk_gate_min=1000
1254 pio_addr=738721792
1255 pio_latency=100000
1256 power_model=Null
1257 system=system
1258 pio=system.membus.master[4]
1259
1260 [system.realview.mcc]
1261 type=SubSystem
1262 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1263 eventq_index=0
1264 thermal_domain=Null
1265
1266 [system.realview.mcc.osc_clcd]
1267 type=RealViewOsc
1268 dcc=0
1269 device=1
1270 eventq_index=0
1271 freq=42105
1272 parent=system.realview.realview_io
1273 position=0
1274 site=0
1275 voltage_domain=system.voltage_domain
1276
1277 [system.realview.mcc.osc_mcc]
1278 type=RealViewOsc
1279 dcc=0
1280 device=0
1281 eventq_index=0
1282 freq=20000
1283 parent=system.realview.realview_io
1284 position=0
1285 site=0
1286 voltage_domain=system.voltage_domain
1287
1288 [system.realview.mcc.osc_peripheral]
1289 type=RealViewOsc
1290 dcc=0
1291 device=2
1292 eventq_index=0
1293 freq=41667
1294 parent=system.realview.realview_io
1295 position=0
1296 site=0
1297 voltage_domain=system.voltage_domain
1298
1299 [system.realview.mcc.osc_system_bus]
1300 type=RealViewOsc
1301 dcc=0
1302 device=4
1303 eventq_index=0
1304 freq=41667
1305 parent=system.realview.realview_io
1306 position=0
1307 site=0
1308 voltage_domain=system.voltage_domain
1309
1310 [system.realview.mcc.temp_crtl]
1311 type=RealViewTemperatureSensor
1312 dcc=0
1313 device=0
1314 eventq_index=0
1315 parent=system.realview.realview_io
1316 position=0
1317 site=0
1318 system=system
1319
1320 [system.realview.mmc_fake]
1321 type=AmbaFake
1322 amba_id=0
1323 clk_domain=system.clk_domain
1324 default_p_state=UNDEFINED
1325 eventq_index=0
1326 ignore_access=false
1327 p_state_clk_gate_bins=20
1328 p_state_clk_gate_max=1000000000000
1329 p_state_clk_gate_min=1000
1330 pio_addr=470089728
1331 pio_latency=100000
1332 power_model=Null
1333 system=system
1334 pio=system.iobus.master[21]
1335
1336 [system.realview.nvmem]
1337 type=SimpleMemory
1338 bandwidth=73.000000
1339 clk_domain=system.clk_domain
1340 conf_table_reported=false
1341 default_p_state=UNDEFINED
1342 eventq_index=0
1343 in_addr_map=true
1344 kvm_map=true
1345 latency=30000
1346 latency_var=0
1347 null=false
1348 p_state_clk_gate_bins=20
1349 p_state_clk_gate_max=1000000000000
1350 p_state_clk_gate_min=1000
1351 power_model=Null
1352 range=0:67108863:0:0:0:0
1353 port=system.membus.master[1]
1354
1355 [system.realview.pci_host]
1356 type=GenericPciHost
1357 clk_domain=system.clk_domain
1358 conf_base=805306368
1359 conf_device_bits=12
1360 conf_size=268435456
1361 default_p_state=UNDEFINED
1362 eventq_index=0
1363 p_state_clk_gate_bins=20
1364 p_state_clk_gate_max=1000000000000
1365 p_state_clk_gate_min=1000
1366 pci_dma_base=0
1367 pci_mem_base=0
1368 pci_pio_base=788529152
1369 platform=system.realview
1370 power_model=Null
1371 system=system
1372 pio=system.iobus.master[2]
1373
1374 [system.realview.realview_io]
1375 type=RealViewCtrl
1376 clk_domain=system.clk_domain
1377 default_p_state=UNDEFINED
1378 eventq_index=0
1379 idreg=35979264
1380 p_state_clk_gate_bins=20
1381 p_state_clk_gate_max=1000000000000
1382 p_state_clk_gate_min=1000
1383 pio_addr=469827584
1384 pio_latency=100000
1385 power_model=Null
1386 proc_id0=335544320
1387 proc_id1=335544320
1388 system=system
1389 pio=system.iobus.master[1]
1390
1391 [system.realview.rtc]
1392 type=PL031
1393 amba_id=3412017
1394 clk_domain=system.clk_domain
1395 default_p_state=UNDEFINED
1396 eventq_index=0
1397 gic=system.realview.gic
1398 int_delay=100000
1399 int_num=36
1400 p_state_clk_gate_bins=20
1401 p_state_clk_gate_max=1000000000000
1402 p_state_clk_gate_min=1000
1403 pio_addr=471269376
1404 pio_latency=100000
1405 power_model=Null
1406 system=system
1407 time=Thu Jan  1 00:00:00 2009
1408 pio=system.iobus.master[10]
1409
1410 [system.realview.sp810_fake]
1411 type=AmbaFake
1412 amba_id=0
1413 clk_domain=system.clk_domain
1414 default_p_state=UNDEFINED
1415 eventq_index=0
1416 ignore_access=true
1417 p_state_clk_gate_bins=20
1418 p_state_clk_gate_max=1000000000000
1419 p_state_clk_gate_min=1000
1420 pio_addr=469893120
1421 pio_latency=100000
1422 power_model=Null
1423 system=system
1424 pio=system.iobus.master[16]
1425
1426 [system.realview.timer0]
1427 type=Sp804
1428 amba_id=1316868
1429 clk_domain=system.clk_domain
1430 clock0=1000000
1431 clock1=1000000
1432 default_p_state=UNDEFINED
1433 eventq_index=0
1434 gic=system.realview.gic
1435 int_num0=34
1436 int_num1=34
1437 p_state_clk_gate_bins=20
1438 p_state_clk_gate_max=1000000000000
1439 p_state_clk_gate_min=1000
1440 pio_addr=470876160
1441 pio_latency=100000
1442 power_model=Null
1443 system=system
1444 pio=system.iobus.master[3]
1445
1446 [system.realview.timer1]
1447 type=Sp804
1448 amba_id=1316868
1449 clk_domain=system.clk_domain
1450 clock0=1000000
1451 clock1=1000000
1452 default_p_state=UNDEFINED
1453 eventq_index=0
1454 gic=system.realview.gic
1455 int_num0=35
1456 int_num1=35
1457 p_state_clk_gate_bins=20
1458 p_state_clk_gate_max=1000000000000
1459 p_state_clk_gate_min=1000
1460 pio_addr=470941696
1461 pio_latency=100000
1462 power_model=Null
1463 system=system
1464 pio=system.iobus.master[4]
1465
1466 [system.realview.uart]
1467 type=Pl011
1468 clk_domain=system.clk_domain
1469 default_p_state=UNDEFINED
1470 end_on_eot=false
1471 eventq_index=0
1472 gic=system.realview.gic
1473 int_delay=100000
1474 int_num=37
1475 p_state_clk_gate_bins=20
1476 p_state_clk_gate_max=1000000000000
1477 p_state_clk_gate_min=1000
1478 pio_addr=470351872
1479 pio_latency=100000
1480 platform=system.realview
1481 power_model=Null
1482 system=system
1483 terminal=system.terminal
1484 pio=system.iobus.master[0]
1485
1486 [system.realview.uart1_fake]
1487 type=AmbaFake
1488 amba_id=0
1489 clk_domain=system.clk_domain
1490 default_p_state=UNDEFINED
1491 eventq_index=0
1492 ignore_access=false
1493 p_state_clk_gate_bins=20
1494 p_state_clk_gate_max=1000000000000
1495 p_state_clk_gate_min=1000
1496 pio_addr=470417408
1497 pio_latency=100000
1498 power_model=Null
1499 system=system
1500 pio=system.iobus.master[13]
1501
1502 [system.realview.uart2_fake]
1503 type=AmbaFake
1504 amba_id=0
1505 clk_domain=system.clk_domain
1506 default_p_state=UNDEFINED
1507 eventq_index=0
1508 ignore_access=false
1509 p_state_clk_gate_bins=20
1510 p_state_clk_gate_max=1000000000000
1511 p_state_clk_gate_min=1000
1512 pio_addr=470482944
1513 pio_latency=100000
1514 power_model=Null
1515 system=system
1516 pio=system.iobus.master[14]
1517
1518 [system.realview.uart3_fake]
1519 type=AmbaFake
1520 amba_id=0
1521 clk_domain=system.clk_domain
1522 default_p_state=UNDEFINED
1523 eventq_index=0
1524 ignore_access=false
1525 p_state_clk_gate_bins=20
1526 p_state_clk_gate_max=1000000000000
1527 p_state_clk_gate_min=1000
1528 pio_addr=470548480
1529 pio_latency=100000
1530 power_model=Null
1531 system=system
1532 pio=system.iobus.master[15]
1533
1534 [system.realview.usb_fake]
1535 type=IsaFake
1536 clk_domain=system.clk_domain
1537 default_p_state=UNDEFINED
1538 eventq_index=0
1539 fake_mem=false
1540 p_state_clk_gate_bins=20
1541 p_state_clk_gate_max=1000000000000
1542 p_state_clk_gate_min=1000
1543 pio_addr=452984832
1544 pio_latency=100000
1545 pio_size=131071
1546 power_model=Null
1547 ret_bad_addr=false
1548 ret_data16=65535
1549 ret_data32=4294967295
1550 ret_data64=18446744073709551615
1551 ret_data8=255
1552 system=system
1553 update_data=false
1554 warn_access=
1555 pio=system.iobus.master[20]
1556
1557 [system.realview.vgic]
1558 type=VGic
1559 clk_domain=system.clk_domain
1560 default_p_state=UNDEFINED
1561 eventq_index=0
1562 gic=system.realview.gic
1563 hv_addr=738213888
1564 p_state_clk_gate_bins=20
1565 p_state_clk_gate_max=1000000000000
1566 p_state_clk_gate_min=1000
1567 pio_delay=10000
1568 platform=system.realview
1569 power_model=Null
1570 ppint=25
1571 system=system
1572 vcpu_addr=738222080
1573 pio=system.membus.master[3]
1574
1575 [system.realview.vram]
1576 type=SimpleMemory
1577 bandwidth=73.000000
1578 clk_domain=system.clk_domain
1579 conf_table_reported=false
1580 default_p_state=UNDEFINED
1581 eventq_index=0
1582 in_addr_map=true
1583 kvm_map=true
1584 latency=30000
1585 latency_var=0
1586 null=false
1587 p_state_clk_gate_bins=20
1588 p_state_clk_gate_max=1000000000000
1589 p_state_clk_gate_min=1000
1590 power_model=Null
1591 range=402653184:436207615:0:0:0:0
1592 port=system.iobus.master[11]
1593
1594 [system.realview.watchdog_fake]
1595 type=AmbaFake
1596 amba_id=0
1597 clk_domain=system.clk_domain
1598 default_p_state=UNDEFINED
1599 eventq_index=0
1600 ignore_access=false
1601 p_state_clk_gate_bins=20
1602 p_state_clk_gate_max=1000000000000
1603 p_state_clk_gate_min=1000
1604 pio_addr=470745088
1605 pio_latency=100000
1606 power_model=Null
1607 system=system
1608 pio=system.iobus.master[17]
1609
1610 [system.terminal]
1611 type=Terminal
1612 eventq_index=0
1613 intr_control=system.intrctrl
1614 number=0
1615 output=true
1616 port=3456
1617
1618 [system.vncserver]
1619 type=VncServer
1620 eventq_index=0
1621 frame_capture=false
1622 number=0
1623 port=5900
1624
1625 [system.voltage_domain]
1626 type=VoltageDomain
1627 eventq_index=0
1628 voltage=1.000000
1629