2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 51.811400 # Number of seconds simulated
4 sim_ticks 51811399994500 # Number of ticks simulated
5 final_tick 51811399994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 805770 # Simulator instruction rate (inst/s)
8 host_op_rate 946938 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 50389185573 # Simulator tick rate (ticks/s)
10 host_mem_usage 678984 # Number of bytes of host memory used
11 host_seconds 1028.22 # Real time elapsed on the host
12 sim_insts 828512987 # Number of instructions simulated
13 sim_ops 973664549 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 141952 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 4623732 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 65034376 # Number of bytes read from this memory
20 system.physmem.bytes_read::realview.ide 398080 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 70331708 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 4623732 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 4623732 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 61230400 # Number of bytes written to this memory
25 system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 61250980 # Number of bytes written to this memory
27 system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 2218 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 112653 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 1016175 # Number of read requests responded to by this memory
31 system.physmem.num_reads::realview.ide 6220 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 1139353 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 956725 # Number of write requests responded to by this memory
34 system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 959298 # Number of write requests responded to by this memory
36 system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.itb.walker 2740 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.inst 89242 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.data 1255214 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::realview.ide 7683 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 1357456 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 89242 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 89242 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 1181794 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 1182191 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 1181794 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.itb.walker 2740 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.inst 89242 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.data 1255611 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::realview.ide 7683 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 2539647 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.readReqs 1139353 # Number of read requests accepted
55 system.physmem.writeReqs 959298 # Number of write requests accepted
56 system.physmem.readBursts 1139353 # Number of DRAM read bursts, including those serviced by the write queue
57 system.physmem.writeBursts 959298 # Number of DRAM write bursts, including those merged in the write queue
58 system.physmem.bytesReadDRAM 72868032 # Total number of bytes read from DRAM
59 system.physmem.bytesReadWrQ 50560 # Total number of bytes read from write queue
60 system.physmem.bytesWritten 61249856 # Total number of bytes written to DRAM
61 system.physmem.bytesReadSys 70331708 # Total read bytes from the system interface side
62 system.physmem.bytesWrittenSys 61250980 # Total written bytes from the system interface side
63 system.physmem.servicedByWrQ 790 # Number of DRAM read bursts serviced by the write queue
64 system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
65 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
66 system.physmem.perBankRdBursts::0 69574 # Per bank write bursts
67 system.physmem.perBankRdBursts::1 73483 # Per bank write bursts
68 system.physmem.perBankRdBursts::2 70905 # Per bank write bursts
69 system.physmem.perBankRdBursts::3 67568 # Per bank write bursts
70 system.physmem.perBankRdBursts::4 64326 # Per bank write bursts
71 system.physmem.perBankRdBursts::5 70688 # Per bank write bursts
72 system.physmem.perBankRdBursts::6 65575 # Per bank write bursts
73 system.physmem.perBankRdBursts::7 64409 # Per bank write bursts
74 system.physmem.perBankRdBursts::8 65562 # Per bank write bursts
75 system.physmem.perBankRdBursts::9 110058 # Per bank write bursts
76 system.physmem.perBankRdBursts::10 69387 # Per bank write bursts
77 system.physmem.perBankRdBursts::11 70852 # Per bank write bursts
78 system.physmem.perBankRdBursts::12 67727 # Per bank write bursts
79 system.physmem.perBankRdBursts::13 71395 # Per bank write bursts
80 system.physmem.perBankRdBursts::14 70177 # Per bank write bursts
81 system.physmem.perBankRdBursts::15 66877 # Per bank write bursts
82 system.physmem.perBankWrBursts::0 57914 # Per bank write bursts
83 system.physmem.perBankWrBursts::1 61200 # Per bank write bursts
84 system.physmem.perBankWrBursts::2 60974 # Per bank write bursts
85 system.physmem.perBankWrBursts::3 59703 # Per bank write bursts
86 system.physmem.perBankWrBursts::4 56782 # Per bank write bursts
87 system.physmem.perBankWrBursts::5 61096 # Per bank write bursts
88 system.physmem.perBankWrBursts::6 57709 # Per bank write bursts
89 system.physmem.perBankWrBursts::7 57516 # Per bank write bursts
90 system.physmem.perBankWrBursts::8 58389 # Per bank write bursts
91 system.physmem.perBankWrBursts::9 61168 # Per bank write bursts
92 system.physmem.perBankWrBursts::10 60736 # Per bank write bursts
93 system.physmem.perBankWrBursts::11 62143 # Per bank write bursts
94 system.physmem.perBankWrBursts::12 59319 # Per bank write bursts
95 system.physmem.perBankWrBursts::13 62705 # Per bank write bursts
96 system.physmem.perBankWrBursts::14 61087 # Per bank write bursts
97 system.physmem.perBankWrBursts::15 58588 # Per bank write bursts
98 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99 system.physmem.numWrRetry 61 # Number of times write queue was full causing retry
100 system.physmem.totGap 51811397057500 # Total gap between requests
101 system.physmem.readPktSize::0 0 # Read request sizes (log2)
102 system.physmem.readPktSize::1 0 # Read request sizes (log2)
103 system.physmem.readPktSize::2 43101 # Read request sizes (log2)
104 system.physmem.readPktSize::3 13 # Read request sizes (log2)
105 system.physmem.readPktSize::4 2 # Read request sizes (log2)
106 system.physmem.readPktSize::5 0 # Read request sizes (log2)
107 system.physmem.readPktSize::6 1096237 # Read request sizes (log2)
108 system.physmem.writePktSize::0 0 # Write request sizes (log2)
109 system.physmem.writePktSize::1 0 # Write request sizes (log2)
110 system.physmem.writePktSize::2 1 # Write request sizes (log2)
111 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
112 system.physmem.writePktSize::4 0 # Write request sizes (log2)
113 system.physmem.writePktSize::5 0 # Write request sizes (log2)
114 system.physmem.writePktSize::6 956725 # Write request sizes (log2)
115 system.physmem.rdQLenPdf::0 1111594 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::1 21338 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::2 395 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::3 330 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::4 485 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::5 522 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::6 535 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::7 1104 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::8 665 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::10 328 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::16 100 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::15 13396 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::16 17710 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::17 56112 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::18 55236 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::19 57047 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::20 55563 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::21 55847 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::22 56596 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::23 57293 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::24 56619 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::25 58037 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::26 60289 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::27 57688 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::28 57977 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::29 60291 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::30 57181 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::31 56145 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::32 56000 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::33 2355 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::34 794 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::35 723 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::36 518 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::37 490 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::38 507 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::42 282 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::44 324 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::46 282 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::48 222 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::50 283 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::52 289 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::53 270 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::55 188 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::56 218 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::57 220 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::59 208 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::60 220 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see
211 system.physmem.bytesPerActivate::samples 450226 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::mean 297.889433 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::gmean 171.979745 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::stdev 329.177331 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::0-127 179632 39.90% 39.90% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::128-255 110318 24.50% 64.40% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::256-383 39188 8.70% 73.11% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::384-511 22734 5.05% 78.15% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::512-639 15887 3.53% 81.68% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::640-767 11846 2.63% 84.31% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-895 9963 2.21% 86.53% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::896-1023 8722 1.94% 88.46% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1024-1151 51936 11.54% 100.00% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::total 450226 # Bytes accessed per row activation
225 system.physmem.rdPerTurnAround::samples 53627 # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::mean 21.230425 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::stdev 337.691151 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::0-4095 53625 100.00% 100.00% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
231 system.physmem.rdPerTurnAround::total 53627 # Reads before turning the bus around for writes
232 system.physmem.wrPerTurnAround::samples 53627 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::mean 17.846029 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::gmean 17.135395 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::stdev 8.325860 # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::16-19 51578 96.18% 96.18% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::20-23 290 0.54% 96.72% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::24-27 64 0.12% 96.84% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::28-31 105 0.20% 97.04% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::32-35 36 0.07% 97.10% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::36-39 101 0.19% 97.29% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::40-43 231 0.43% 97.72% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::44-47 25 0.05% 97.77% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::48-51 324 0.60% 98.37% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::52-55 70 0.13% 98.50% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::56-59 27 0.05% 98.55% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::60-63 55 0.10% 98.66% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::64-67 281 0.52% 99.18% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::68-71 24 0.04% 99.22% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::72-75 27 0.05% 99.27% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::76-79 150 0.28% 99.55% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::80-83 183 0.34% 99.90% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::124-127 3 0.01% 99.93% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::128-131 7 0.01% 99.94% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::144-147 16 0.03% 99.98% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::total 53627 # Writes before turning the bus around for reads
273 system.physmem.totQLat 14356871098 # Total ticks spent queuing
274 system.physmem.totMemAccLat 35704927348 # Total ticks spent from burst creation until serviced by the DRAM
275 system.physmem.totBusLat 5692815000 # Total ticks spent in databus transfers
276 system.physmem.avgQLat 12609.64 # Average queueing delay per DRAM burst
277 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
278 system.physmem.avgMemAccLat 31359.64 # Average memory access latency per DRAM burst
279 system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s
280 system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s
281 system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s
282 system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s
283 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
284 system.physmem.busUtil 0.02 # Data bus utilization in percentage
285 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
286 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
287 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
288 system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing
289 system.physmem.readRowHits 917761 # Number of row buffer hits during reads
290 system.physmem.writeRowHits 727604 # Number of row buffer hits during writes
291 system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
292 system.physmem.writeRowHitRate 76.03 # Row buffer hit rate for writes
293 system.physmem.avgGap 24687952.91 # Average gap between requests
294 system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined
295 system.physmem_0.actEnergy 1698338880 # Energy for activate commands per rank (pJ)
296 system.physmem_0.preEnergy 926673000 # Energy for precharge commands per rank (pJ)
297 system.physmem_0.readEnergy 4262879400 # Energy for read commands per rank (pJ)
298 system.physmem_0.writeEnergy 3064353120 # Energy for write commands per rank (pJ)
299 system.physmem_0.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ)
300 system.physmem_0.actBackEnergy 1294076187855 # Energy for active background per rank (pJ)
301 system.physmem_0.preBackEnergy 29951683866750 # Energy for precharge background per rank (pJ)
302 system.physmem_0.totalEnergy 34639780896525 # Total energy per rank (pJ)
303 system.physmem_0.averagePower 668.574535 # Core power per rank (mW)
304 system.physmem_0.memoryStateTime::IDLE 49826749097915 # Time in different power states
305 system.physmem_0.memoryStateTime::REF 1730096420000 # Time in different power states
306 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
307 system.physmem_0.memoryStateTime::ACT 254553819585 # Time in different power states
308 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
309 system.physmem_1.actEnergy 1705369680 # Energy for activate commands per rank (pJ)
310 system.physmem_1.preEnergy 930509250 # Energy for precharge commands per rank (pJ)
311 system.physmem_1.readEnergy 4617873000 # Energy for read commands per rank (pJ)
312 system.physmem_1.writeEnergy 3137194800 # Energy for write commands per rank (pJ)
313 system.physmem_1.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ)
314 system.physmem_1.actBackEnergy 1296366805530 # Energy for active background per rank (pJ)
315 system.physmem_1.preBackEnergy 29949674553000 # Energy for precharge background per rank (pJ)
316 system.physmem_1.totalEnergy 34640500902780 # Total energy per rank (pJ)
317 system.physmem_1.averagePower 668.588432 # Core power per rank (mW)
318 system.physmem_1.memoryStateTime::IDLE 49823352477739 # Time in different power states
319 system.physmem_1.memoryStateTime::REF 1730096420000 # Time in different power states
320 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
321 system.physmem_1.memoryStateTime::ACT 257948478511 # Time in different power states
322 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
323 system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
324 system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
325 system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
326 system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
327 system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
328 system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
329 system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
330 system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
331 system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
332 system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
333 system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
334 system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
335 system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
336 system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
337 system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
338 system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
339 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
340 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
341 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
342 system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
343 system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
344 system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
345 system.cpu_clk_domain.clock 500 # Clock period in ticks
346 system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
347 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
348 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
349 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
350 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
351 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
352 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
353 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
354 system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
355 system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
356 system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
357 system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
358 system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
359 system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
360 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
361 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
362 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
363 system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
364 system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
365 system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
366 system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
367 system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
368 system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
369 system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
370 system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
371 system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
372 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
373 system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
374 system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
375 system.cpu.dtb.walker.walks 185086 # Table walker walks requested
376 system.cpu.dtb.walker.walksLong 185086 # Table walker walks initiated with long descriptors
377 system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12788 # Level at which table walker walks with long descriptors terminate
378 system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144037 # Level at which table walker walks with long descriptors terminate
379 system.cpu.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting
380 system.cpu.dtb.walker.walkWaitTime::samples 185071 # Table walker wait (enqueue to first request) latency
381 system.cpu.dtb.walker.walkWaitTime::mean 0.216133 # Table walker wait (enqueue to first request) latency
382 system.cpu.dtb.walker.walkWaitTime::stdev 70.811526 # Table walker wait (enqueue to first request) latency
383 system.cpu.dtb.walker.walkWaitTime::0-2047 185069 100.00% 100.00% # Table walker wait (enqueue to first request) latency
384 system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
385 system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
386 system.cpu.dtb.walker.walkWaitTime::total 185071 # Table walker wait (enqueue to first request) latency
387 system.cpu.dtb.walker.walkCompletionTime::samples 156840 # Table walker service (enqueue to completion) latency
388 system.cpu.dtb.walker.walkCompletionTime::mean 24753.656593 # Table walker service (enqueue to completion) latency
389 system.cpu.dtb.walker.walkCompletionTime::gmean 20840.255945 # Table walker service (enqueue to completion) latency
390 system.cpu.dtb.walker.walkCompletionTime::stdev 17740.873102 # Table walker service (enqueue to completion) latency
391 system.cpu.dtb.walker.walkCompletionTime::0-65535 155696 99.27% 99.27% # Table walker service (enqueue to completion) latency
392 system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.27% # Table walker service (enqueue to completion) latency
393 system.cpu.dtb.walker.walkCompletionTime::131072-196607 981 0.63% 99.90% # Table walker service (enqueue to completion) latency
394 system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency
395 system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.96% # Table walker service (enqueue to completion) latency
396 system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.97% # Table walker service (enqueue to completion) latency
397 system.cpu.dtb.walker.walkCompletionTime::393216-458751 36 0.02% 100.00% # Table walker service (enqueue to completion) latency
398 system.cpu.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
399 system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
400 system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
401 system.cpu.dtb.walker.walkCompletionTime::total 156840 # Table walker service (enqueue to completion) latency
402 system.cpu.dtb.walker.walksPending::samples -374556148 # Table walker pending requests distribution
403 system.cpu.dtb.walker.walksPending::mean 5.053125 # Table walker pending requests distribution
404 system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
405 system.cpu.dtb.walker.walksPending::0 1518122704 -405.31% -405.31% # Table walker pending requests distribution
406 system.cpu.dtb.walker.walksPending::1 -1892678852 505.31% 100.00% # Table walker pending requests distribution
407 system.cpu.dtb.walker.walksPending::total -374556148 # Table walker pending requests distribution
408 system.cpu.dtb.walker.walkPageSizes::4K 144038 91.85% 91.85% # Table walker page sizes translated
409 system.cpu.dtb.walker.walkPageSizes::2M 12788 8.15% 100.00% # Table walker page sizes translated
410 system.cpu.dtb.walker.walkPageSizes::total 156826 # Table walker page sizes translated
411 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185086 # Table walker requests started/completed, data/inst
412 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
413 system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185086 # Table walker requests started/completed, data/inst
414 system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156826 # Table walker requests started/completed, data/inst
415 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
416 system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156826 # Table walker requests started/completed, data/inst
417 system.cpu.dtb.walker.walkRequestOrigin::total 341912 # Table walker requests started/completed, data/inst
418 system.cpu.dtb.inst_hits 0 # ITB inst hits
419 system.cpu.dtb.inst_misses 0 # ITB inst misses
420 system.cpu.dtb.read_hits 156026006 # DTB read hits
421 system.cpu.dtb.read_misses 137641 # DTB read misses
422 system.cpu.dtb.write_hits 141600690 # DTB write hits
423 system.cpu.dtb.write_misses 47445 # DTB write misses
424 system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
425 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
426 system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID
427 system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
428 system.cpu.dtb.flush_entries 70612 # Number of entries that have been flushed from TLB
429 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
430 system.cpu.dtb.prefetch_faults 6537 # Number of TLB faults due to prefetch
431 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
432 system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions
433 system.cpu.dtb.read_accesses 156163647 # DTB read accesses
434 system.cpu.dtb.write_accesses 141648135 # DTB write accesses
435 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
436 system.cpu.dtb.hits 297626696 # DTB hits
437 system.cpu.dtb.misses 185086 # DTB misses
438 system.cpu.dtb.accesses 297811782 # DTB accesses
439 system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
440 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
441 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
442 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
443 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
444 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
445 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
446 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
447 system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
448 system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
449 system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
450 system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
451 system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
452 system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
453 system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
454 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
455 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
456 system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
457 system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
458 system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
459 system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
460 system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
461 system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
462 system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
463 system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
464 system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
465 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
466 system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
467 system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
468 system.cpu.itb.walker.walks 118473 # Table walker walks requested
469 system.cpu.itb.walker.walksLong 118473 # Table walker walks initiated with long descriptors
470 system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate
471 system.cpu.itb.walker.walksLongTerminationLevel::Level3 107045 # Level at which table walker walks with long descriptors terminate
472 system.cpu.itb.walker.walkWaitTime::samples 118473 # Table walker wait (enqueue to first request) latency
473 system.cpu.itb.walker.walkWaitTime::0 118473 100.00% 100.00% # Table walker wait (enqueue to first request) latency
474 system.cpu.itb.walker.walkWaitTime::total 118473 # Table walker wait (enqueue to first request) latency
475 system.cpu.itb.walker.walkCompletionTime::samples 108155 # Table walker service (enqueue to completion) latency
476 system.cpu.itb.walker.walkCompletionTime::mean 28668.184550 # Table walker service (enqueue to completion) latency
477 system.cpu.itb.walker.walkCompletionTime::gmean 24838.617630 # Table walker service (enqueue to completion) latency
478 system.cpu.itb.walker.walkCompletionTime::stdev 20892.143337 # Table walker service (enqueue to completion) latency
479 system.cpu.itb.walker.walkCompletionTime::0-65535 106773 98.72% 98.72% # Table walker service (enqueue to completion) latency
480 system.cpu.itb.walker.walkCompletionTime::131072-196607 1223 1.13% 99.85% # Table walker service (enqueue to completion) latency
481 system.cpu.itb.walker.walkCompletionTime::196608-262143 21 0.02% 99.87% # Table walker service (enqueue to completion) latency
482 system.cpu.itb.walker.walkCompletionTime::262144-327679 63 0.06% 99.93% # Table walker service (enqueue to completion) latency
483 system.cpu.itb.walker.walkCompletionTime::327680-393215 24 0.02% 99.95% # Table walker service (enqueue to completion) latency
484 system.cpu.itb.walker.walkCompletionTime::393216-458751 37 0.03% 99.99% # Table walker service (enqueue to completion) latency
485 system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
486 system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
487 system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
488 system.cpu.itb.walker.walkCompletionTime::total 108155 # Table walker service (enqueue to completion) latency
489 system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution
490 system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution
491 system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution
492 system.cpu.itb.walker.walkPageSizes::4K 107045 98.97% 98.97% # Table walker page sizes translated
493 system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated
494 system.cpu.itb.walker.walkPageSizes::total 108155 # Table walker page sizes translated
495 system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
496 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118473 # Table walker requests started/completed, data/inst
497 system.cpu.itb.walker.walkRequestOrigin_Requested::total 118473 # Table walker requests started/completed, data/inst
498 system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
499 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108155 # Table walker requests started/completed, data/inst
500 system.cpu.itb.walker.walkRequestOrigin_Completed::total 108155 # Table walker requests started/completed, data/inst
501 system.cpu.itb.walker.walkRequestOrigin::total 226628 # Table walker requests started/completed, data/inst
502 system.cpu.itb.inst_hits 829023400 # ITB inst hits
503 system.cpu.itb.inst_misses 118473 # ITB inst misses
504 system.cpu.itb.read_hits 0 # DTB read hits
505 system.cpu.itb.read_misses 0 # DTB read misses
506 system.cpu.itb.write_hits 0 # DTB write hits
507 system.cpu.itb.write_misses 0 # DTB write misses
508 system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
509 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
510 system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID
511 system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
512 system.cpu.itb.flush_entries 50418 # Number of entries that have been flushed from TLB
513 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
514 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
515 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
516 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
517 system.cpu.itb.read_accesses 0 # DTB read accesses
518 system.cpu.itb.write_accesses 0 # DTB write accesses
519 system.cpu.itb.inst_accesses 829141873 # ITB inst accesses
520 system.cpu.itb.hits 829023400 # DTB hits
521 system.cpu.itb.misses 118473 # DTB misses
522 system.cpu.itb.accesses 829141873 # DTB accesses
523 system.cpu.numCycles 103622799989 # number of cpu cycles simulated
524 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
525 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
526 system.cpu.kern.inst.arm 0 # number of arm instructions executed
527 system.cpu.kern.inst.quiesce 15972 # number of quiesce instructions executed
528 system.cpu.committedInsts 828512987 # Number of instructions committed
529 system.cpu.committedOps 973664549 # Number of ops (including micro ops) committed
530 system.cpu.num_int_alu_accesses 895161313 # Number of integer alu accesses
531 system.cpu.num_fp_alu_accesses 899443 # Number of float alu accesses
532 system.cpu.num_func_calls 49782138 # number of times a function call or return occured
533 system.cpu.num_conditional_control_insts 125600972 # number of instructions that are conditional controls
534 system.cpu.num_int_insts 895161313 # number of integer instructions
535 system.cpu.num_fp_insts 899443 # number of float instructions
536 system.cpu.num_int_register_reads 1295047006 # number of times the integer registers were read
537 system.cpu.num_int_register_writes 709396185 # number of times the integer registers were written
538 system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read
539 system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written
540 system.cpu.num_cc_register_reads 214441530 # number of times the CC registers were read
541 system.cpu.num_cc_register_writes 213833710 # number of times the CC registers were written
542 system.cpu.num_mem_refs 297604519 # number of memory refs
543 system.cpu.num_load_insts 156015499 # Number of load instructions
544 system.cpu.num_store_insts 141589020 # Number of store instructions
545 system.cpu.num_idle_cycles 100541051528.316055 # Number of idle cycles
546 system.cpu.num_busy_cycles 3081748460.683940 # Number of busy cycles
547 system.cpu.not_idle_fraction 0.029740 # Percentage of non-idle cycles
548 system.cpu.idle_fraction 0.970260 # Percentage of idle cycles
549 system.cpu.Branches 184855625 # Number of branches fetched
550 system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
551 system.cpu.op_class::IntAlu 674284702 69.21% 69.21% # Class of executed instruction
552 system.cpu.op_class::IntMult 2119126 0.22% 69.43% # Class of executed instruction
553 system.cpu.op_class::IntDiv 97314 0.01% 69.44% # Class of executed instruction
554 system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
555 system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction
556 system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction
557 system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction
558 system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction
559 system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
560 system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction
561 system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
562 system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction
563 system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction
564 system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction
565 system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
566 system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
567 system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
568 system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
569 system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
570 system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
571 system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction
572 system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction
573 system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction
574 system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction
575 system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
576 system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction
577 system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
578 system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
579 system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
580 system.cpu.op_class::MemRead 156015499 16.01% 85.47% # Class of executed instruction
581 system.cpu.op_class::MemWrite 141589020 14.53% 100.00% # Class of executed instruction
582 system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
583 system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
584 system.cpu.op_class::total 974218086 # Class of executed instruction
585 system.cpu.dcache.tags.replacements 9250712 # number of replacements
586 system.cpu.dcache.tags.tagsinuse 511.942785 # Cycle average of tags in use
587 system.cpu.dcache.tags.total_refs 288177954 # Total number of references to valid blocks.
588 system.cpu.dcache.tags.sampled_refs 9251224 # Sample count of references to valid blocks.
589 system.cpu.dcache.tags.avg_refs 31.150251 # Average number of references to valid blocks.
590 system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit.
591 system.cpu.dcache.tags.occ_blocks::cpu.data 511.942785 # Average occupied blocks per requestor
592 system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
593 system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
594 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
595 system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
596 system.cpu.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
597 system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
598 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
599 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
600 system.cpu.dcache.tags.tag_accesses 1199424100 # Number of tag accesses
601 system.cpu.dcache.tags.data_accesses 1199424100 # Number of data accesses
602 system.cpu.dcache.ReadReq_hits::cpu.data 146113650 # number of ReadReq hits
603 system.cpu.dcache.ReadReq_hits::total 146113650 # number of ReadReq hits
604 system.cpu.dcache.WriteReq_hits::cpu.data 134461846 # number of WriteReq hits
605 system.cpu.dcache.WriteReq_hits::total 134461846 # number of WriteReq hits
606 system.cpu.dcache.SoftPFReq_hits::cpu.data 373199 # number of SoftPFReq hits
607 system.cpu.dcache.SoftPFReq_hits::total 373199 # number of SoftPFReq hits
608 system.cpu.dcache.WriteLineReq_hits::cpu.data 333438 # number of WriteLineReq hits
609 system.cpu.dcache.WriteLineReq_hits::total 333438 # number of WriteLineReq hits
610 system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286002 # number of LoadLockedReq hits
611 system.cpu.dcache.LoadLockedReq_hits::total 3286002 # number of LoadLockedReq hits
612 system.cpu.dcache.StoreCondReq_hits::cpu.data 3568410 # number of StoreCondReq hits
613 system.cpu.dcache.StoreCondReq_hits::total 3568410 # number of StoreCondReq hits
614 system.cpu.dcache.demand_hits::cpu.data 280575496 # number of demand (read+write) hits
615 system.cpu.dcache.demand_hits::total 280575496 # number of demand (read+write) hits
616 system.cpu.dcache.overall_hits::cpu.data 280948695 # number of overall hits
617 system.cpu.dcache.overall_hits::total 280948695 # number of overall hits
618 system.cpu.dcache.ReadReq_misses::cpu.data 4827178 # number of ReadReq misses
619 system.cpu.dcache.ReadReq_misses::total 4827178 # number of ReadReq misses
620 system.cpu.dcache.WriteReq_misses::cpu.data 1968166 # number of WriteReq misses
621 system.cpu.dcache.WriteReq_misses::total 1968166 # number of WriteReq misses
622 system.cpu.dcache.SoftPFReq_misses::cpu.data 1108268 # number of SoftPFReq misses
623 system.cpu.dcache.SoftPFReq_misses::total 1108268 # number of SoftPFReq misses
624 system.cpu.dcache.WriteLineReq_misses::cpu.data 1219027 # number of WriteLineReq misses
625 system.cpu.dcache.WriteLineReq_misses::total 1219027 # number of WriteLineReq misses
626 system.cpu.dcache.LoadLockedReq_misses::cpu.data 284027 # number of LoadLockedReq misses
627 system.cpu.dcache.LoadLockedReq_misses::total 284027 # number of LoadLockedReq misses
628 system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
629 system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
630 system.cpu.dcache.demand_misses::cpu.data 6795344 # number of demand (read+write) misses
631 system.cpu.dcache.demand_misses::total 6795344 # number of demand (read+write) misses
632 system.cpu.dcache.overall_misses::cpu.data 7903612 # number of overall misses
633 system.cpu.dcache.overall_misses::total 7903612 # number of overall misses
634 system.cpu.dcache.ReadReq_miss_latency::cpu.data 82868566500 # number of ReadReq miss cycles
635 system.cpu.dcache.ReadReq_miss_latency::total 82868566500 # number of ReadReq miss cycles
636 system.cpu.dcache.WriteReq_miss_latency::cpu.data 66733586000 # number of WriteReq miss cycles
637 system.cpu.dcache.WriteReq_miss_latency::total 66733586000 # number of WriteReq miss cycles
638 system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73334603500 # number of WriteLineReq miss cycles
639 system.cpu.dcache.WriteLineReq_miss_latency::total 73334603500 # number of WriteLineReq miss cycles
640 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4341861000 # number of LoadLockedReq miss cycles
641 system.cpu.dcache.LoadLockedReq_miss_latency::total 4341861000 # number of LoadLockedReq miss cycles
642 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
643 system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
644 system.cpu.dcache.demand_miss_latency::cpu.data 149602152500 # number of demand (read+write) miss cycles
645 system.cpu.dcache.demand_miss_latency::total 149602152500 # number of demand (read+write) miss cycles
646 system.cpu.dcache.overall_miss_latency::cpu.data 149602152500 # number of overall miss cycles
647 system.cpu.dcache.overall_miss_latency::total 149602152500 # number of overall miss cycles
648 system.cpu.dcache.ReadReq_accesses::cpu.data 150940828 # number of ReadReq accesses(hits+misses)
649 system.cpu.dcache.ReadReq_accesses::total 150940828 # number of ReadReq accesses(hits+misses)
650 system.cpu.dcache.WriteReq_accesses::cpu.data 136430012 # number of WriteReq accesses(hits+misses)
651 system.cpu.dcache.WriteReq_accesses::total 136430012 # number of WriteReq accesses(hits+misses)
652 system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481467 # number of SoftPFReq accesses(hits+misses)
653 system.cpu.dcache.SoftPFReq_accesses::total 1481467 # number of SoftPFReq accesses(hits+misses)
654 system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552465 # number of WriteLineReq accesses(hits+misses)
655 system.cpu.dcache.WriteLineReq_accesses::total 1552465 # number of WriteLineReq accesses(hits+misses)
656 system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570029 # number of LoadLockedReq accesses(hits+misses)
657 system.cpu.dcache.LoadLockedReq_accesses::total 3570029 # number of LoadLockedReq accesses(hits+misses)
658 system.cpu.dcache.StoreCondReq_accesses::cpu.data 3568412 # number of StoreCondReq accesses(hits+misses)
659 system.cpu.dcache.StoreCondReq_accesses::total 3568412 # number of StoreCondReq accesses(hits+misses)
660 system.cpu.dcache.demand_accesses::cpu.data 287370840 # number of demand (read+write) accesses
661 system.cpu.dcache.demand_accesses::total 287370840 # number of demand (read+write) accesses
662 system.cpu.dcache.overall_accesses::cpu.data 288852307 # number of overall (read+write) accesses
663 system.cpu.dcache.overall_accesses::total 288852307 # number of overall (read+write) accesses
664 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031981 # miss rate for ReadReq accesses
665 system.cpu.dcache.ReadReq_miss_rate::total 0.031981 # miss rate for ReadReq accesses
666 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014426 # miss rate for WriteReq accesses
667 system.cpu.dcache.WriteReq_miss_rate::total 0.014426 # miss rate for WriteReq accesses
668 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748088 # miss rate for SoftPFReq accesses
669 system.cpu.dcache.SoftPFReq_miss_rate::total 0.748088 # miss rate for SoftPFReq accesses
670 system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785220 # miss rate for WriteLineReq accesses
671 system.cpu.dcache.WriteLineReq_miss_rate::total 0.785220 # miss rate for WriteLineReq accesses
672 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079559 # miss rate for LoadLockedReq accesses
673 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079559 # miss rate for LoadLockedReq accesses
674 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
675 system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
676 system.cpu.dcache.demand_miss_rate::cpu.data 0.023647 # miss rate for demand accesses
677 system.cpu.dcache.demand_miss_rate::total 0.023647 # miss rate for demand accesses
678 system.cpu.dcache.overall_miss_rate::cpu.data 0.027362 # miss rate for overall accesses
679 system.cpu.dcache.overall_miss_rate::total 0.027362 # miss rate for overall accesses
680 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17167.083232 # average ReadReq miss latency
681 system.cpu.dcache.ReadReq_avg_miss_latency::total 17167.083232 # average ReadReq miss latency
682 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33906.482482 # average WriteReq miss latency
683 system.cpu.dcache.WriteReq_avg_miss_latency::total 33906.482482 # average WriteReq miss latency
684 system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60158.309455 # average WriteLineReq miss latency
685 system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60158.309455 # average WriteLineReq miss latency
686 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15286.789636 # average LoadLockedReq miss latency
687 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15286.789636 # average LoadLockedReq miss latency
688 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
689 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
690 system.cpu.dcache.demand_avg_miss_latency::cpu.data 22015.390612 # average overall miss latency
691 system.cpu.dcache.demand_avg_miss_latency::total 22015.390612 # average overall miss latency
692 system.cpu.dcache.overall_avg_miss_latency::cpu.data 18928.327010 # average overall miss latency
693 system.cpu.dcache.overall_avg_miss_latency::total 18928.327010 # average overall miss latency
694 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
695 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
696 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
697 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
698 system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
699 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
700 system.cpu.dcache.fast_writes 0 # number of fast writes performed
701 system.cpu.dcache.cache_copies 0 # number of cache copies performed
702 system.cpu.dcache.writebacks::writebacks 7246265 # number of writebacks
703 system.cpu.dcache.writebacks::total 7246265 # number of writebacks
704 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23319 # number of ReadReq MSHR hits
705 system.cpu.dcache.ReadReq_mshr_hits::total 23319 # number of ReadReq MSHR hits
706 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21298 # number of WriteReq MSHR hits
707 system.cpu.dcache.WriteReq_mshr_hits::total 21298 # number of WriteReq MSHR hits
708 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67614 # number of LoadLockedReq MSHR hits
709 system.cpu.dcache.LoadLockedReq_mshr_hits::total 67614 # number of LoadLockedReq MSHR hits
710 system.cpu.dcache.demand_mshr_hits::cpu.data 44617 # number of demand (read+write) MSHR hits
711 system.cpu.dcache.demand_mshr_hits::total 44617 # number of demand (read+write) MSHR hits
712 system.cpu.dcache.overall_mshr_hits::cpu.data 44617 # number of overall MSHR hits
713 system.cpu.dcache.overall_mshr_hits::total 44617 # number of overall MSHR hits
714 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4803859 # number of ReadReq MSHR misses
715 system.cpu.dcache.ReadReq_mshr_misses::total 4803859 # number of ReadReq MSHR misses
716 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1946868 # number of WriteReq MSHR misses
717 system.cpu.dcache.WriteReq_mshr_misses::total 1946868 # number of WriteReq MSHR misses
718 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106488 # number of SoftPFReq MSHR misses
719 system.cpu.dcache.SoftPFReq_mshr_misses::total 1106488 # number of SoftPFReq MSHR misses
720 system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1219027 # number of WriteLineReq MSHR misses
721 system.cpu.dcache.WriteLineReq_mshr_misses::total 1219027 # number of WriteLineReq MSHR misses
722 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216413 # number of LoadLockedReq MSHR misses
723 system.cpu.dcache.LoadLockedReq_mshr_misses::total 216413 # number of LoadLockedReq MSHR misses
724 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
725 system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
726 system.cpu.dcache.demand_mshr_misses::cpu.data 6750727 # number of demand (read+write) MSHR misses
727 system.cpu.dcache.demand_mshr_misses::total 6750727 # number of demand (read+write) MSHR misses
728 system.cpu.dcache.overall_mshr_misses::cpu.data 7857215 # number of overall MSHR misses
729 system.cpu.dcache.overall_mshr_misses::total 7857215 # number of overall MSHR misses
730 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
731 system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
732 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
733 system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
734 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
735 system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
736 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76693371000 # number of ReadReq MSHR miss cycles
737 system.cpu.dcache.ReadReq_mshr_miss_latency::total 76693371000 # number of ReadReq MSHR miss cycles
738 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63803384500 # number of WriteReq MSHR miss cycles
739 system.cpu.dcache.WriteReq_mshr_miss_latency::total 63803384500 # number of WriteReq MSHR miss cycles
740 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20983567500 # number of SoftPFReq MSHR miss cycles
741 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20983567500 # number of SoftPFReq MSHR miss cycles
742 system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72115576500 # number of WriteLineReq MSHR miss cycles
743 system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72115576500 # number of WriteLineReq MSHR miss cycles
744 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970992000 # number of LoadLockedReq MSHR miss cycles
745 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970992000 # number of LoadLockedReq MSHR miss cycles
746 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles
747 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles
748 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140496755500 # number of demand (read+write) MSHR miss cycles
749 system.cpu.dcache.demand_mshr_miss_latency::total 140496755500 # number of demand (read+write) MSHR miss cycles
750 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161480323000 # number of overall MSHR miss cycles
751 system.cpu.dcache.overall_mshr_miss_latency::total 161480323000 # number of overall MSHR miss cycles
752 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199653000 # number of ReadReq MSHR uncacheable cycles
753 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199653000 # number of ReadReq MSHR uncacheable cycles
754 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217623500 # number of WriteReq MSHR uncacheable cycles
755 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217623500 # number of WriteReq MSHR uncacheable cycles
756 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417276500 # number of overall MSHR uncacheable cycles
757 system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417276500 # number of overall MSHR uncacheable cycles
758 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031826 # mshr miss rate for ReadReq accesses
759 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031826 # mshr miss rate for ReadReq accesses
760 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014270 # mshr miss rate for WriteReq accesses
761 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014270 # mshr miss rate for WriteReq accesses
762 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746887 # mshr miss rate for SoftPFReq accesses
763 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746887 # mshr miss rate for SoftPFReq accesses
764 system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785220 # mshr miss rate for WriteLineReq accesses
765 system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785220 # mshr miss rate for WriteLineReq accesses
766 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060619 # mshr miss rate for LoadLockedReq accesses
767 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060619 # mshr miss rate for LoadLockedReq accesses
768 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
769 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
770 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023491 # mshr miss rate for demand accesses
771 system.cpu.dcache.demand_mshr_miss_rate::total 0.023491 # mshr miss rate for demand accesses
772 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027201 # mshr miss rate for overall accesses
773 system.cpu.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses
774 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15964.950470 # average ReadReq mshr miss latency
775 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15964.950470 # average ReadReq mshr miss latency
776 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32772.321750 # average WriteReq mshr miss latency
777 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32772.321750 # average WriteReq mshr miss latency
778 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18964.116647 # average SoftPFReq mshr miss latency
779 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.116647 # average SoftPFReq mshr miss latency
780 system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59158.309455 # average WriteLineReq mshr miss latency
781 system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59158.309455 # average WriteLineReq mshr miss latency
782 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13728.343491 # average LoadLockedReq mshr miss latency
783 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13728.343491 # average LoadLockedReq mshr miss latency
784 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency
785 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency
786 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20812.092609 # average overall mshr miss latency
787 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20812.092609 # average overall mshr miss latency
788 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20551.852406 # average overall mshr miss latency
789 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20551.852406 # average overall mshr miss latency
790 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.047178 # average ReadReq mshr uncacheable latency
791 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.047178 # average ReadReq mshr uncacheable latency
792 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.426012 # average WriteReq mshr uncacheable latency
793 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.426012 # average WriteReq mshr uncacheable latency
794 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.258864 # average overall mshr uncacheable latency
795 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.258864 # average overall mshr uncacheable latency
796 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
797 system.cpu.icache.tags.replacements 13387387 # number of replacements
798 system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use
799 system.cpu.icache.tags.total_refs 815635496 # Total number of references to valid blocks.
800 system.cpu.icache.tags.sampled_refs 13387899 # Sample count of references to valid blocks.
801 system.cpu.icache.tags.avg_refs 60.923338 # Average number of references to valid blocks.
802 system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit.
803 system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor
804 system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy
805 system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy
806 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
807 system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
808 system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
809 system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
810 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
811 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
812 system.cpu.icache.tags.tag_accesses 842411304 # Number of tag accesses
813 system.cpu.icache.tags.data_accesses 842411304 # Number of data accesses
814 system.cpu.icache.ReadReq_hits::cpu.inst 815635496 # number of ReadReq hits
815 system.cpu.icache.ReadReq_hits::total 815635496 # number of ReadReq hits
816 system.cpu.icache.demand_hits::cpu.inst 815635496 # number of demand (read+write) hits
817 system.cpu.icache.demand_hits::total 815635496 # number of demand (read+write) hits
818 system.cpu.icache.overall_hits::cpu.inst 815635496 # number of overall hits
819 system.cpu.icache.overall_hits::total 815635496 # number of overall hits
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821 system.cpu.icache.ReadReq_misses::total 13387904 # number of ReadReq misses
822 system.cpu.icache.demand_misses::cpu.inst 13387904 # number of demand (read+write) misses
823 system.cpu.icache.demand_misses::total 13387904 # number of demand (read+write) misses
824 system.cpu.icache.overall_misses::cpu.inst 13387904 # number of overall misses
825 system.cpu.icache.overall_misses::total 13387904 # number of overall misses
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827 system.cpu.icache.ReadReq_miss_latency::total 182784455500 # number of ReadReq miss cycles
828 system.cpu.icache.demand_miss_latency::cpu.inst 182784455500 # number of demand (read+write) miss cycles
829 system.cpu.icache.demand_miss_latency::total 182784455500 # number of demand (read+write) miss cycles
830 system.cpu.icache.overall_miss_latency::cpu.inst 182784455500 # number of overall miss cycles
831 system.cpu.icache.overall_miss_latency::total 182784455500 # number of overall miss cycles
832 system.cpu.icache.ReadReq_accesses::cpu.inst 829023400 # number of ReadReq accesses(hits+misses)
833 system.cpu.icache.ReadReq_accesses::total 829023400 # number of ReadReq accesses(hits+misses)
834 system.cpu.icache.demand_accesses::cpu.inst 829023400 # number of demand (read+write) accesses
835 system.cpu.icache.demand_accesses::total 829023400 # number of demand (read+write) accesses
836 system.cpu.icache.overall_accesses::cpu.inst 829023400 # number of overall (read+write) accesses
837 system.cpu.icache.overall_accesses::total 829023400 # number of overall (read+write) accesses
838 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016149 # miss rate for ReadReq accesses
839 system.cpu.icache.ReadReq_miss_rate::total 0.016149 # miss rate for ReadReq accesses
840 system.cpu.icache.demand_miss_rate::cpu.inst 0.016149 # miss rate for demand accesses
841 system.cpu.icache.demand_miss_rate::total 0.016149 # miss rate for demand accesses
842 system.cpu.icache.overall_miss_rate::cpu.inst 0.016149 # miss rate for overall accesses
843 system.cpu.icache.overall_miss_rate::total 0.016149 # miss rate for overall accesses
844 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13652.955347 # average ReadReq miss latency
845 system.cpu.icache.ReadReq_avg_miss_latency::total 13652.955347 # average ReadReq miss latency
846 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13652.955347 # average overall miss latency
847 system.cpu.icache.demand_avg_miss_latency::total 13652.955347 # average overall miss latency
848 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13652.955347 # average overall miss latency
849 system.cpu.icache.overall_avg_miss_latency::total 13652.955347 # average overall miss latency
850 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
851 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
852 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
853 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
854 system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
855 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
856 system.cpu.icache.fast_writes 0 # number of fast writes performed
857 system.cpu.icache.cache_copies 0 # number of cache copies performed
858 system.cpu.icache.writebacks::writebacks 13387387 # number of writebacks
859 system.cpu.icache.writebacks::total 13387387 # number of writebacks
860 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13387904 # number of ReadReq MSHR misses
861 system.cpu.icache.ReadReq_mshr_misses::total 13387904 # number of ReadReq MSHR misses
862 system.cpu.icache.demand_mshr_misses::cpu.inst 13387904 # number of demand (read+write) MSHR misses
863 system.cpu.icache.demand_mshr_misses::total 13387904 # number of demand (read+write) MSHR misses
864 system.cpu.icache.overall_mshr_misses::cpu.inst 13387904 # number of overall MSHR misses
865 system.cpu.icache.overall_mshr_misses::total 13387904 # number of overall MSHR misses
866 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
867 system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
868 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
869 system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
870 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169396551500 # number of ReadReq MSHR miss cycles
871 system.cpu.icache.ReadReq_mshr_miss_latency::total 169396551500 # number of ReadReq MSHR miss cycles
872 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169396551500 # number of demand (read+write) MSHR miss cycles
873 system.cpu.icache.demand_mshr_miss_latency::total 169396551500 # number of demand (read+write) MSHR miss cycles
874 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169396551500 # number of overall MSHR miss cycles
875 system.cpu.icache.overall_mshr_miss_latency::total 169396551500 # number of overall MSHR miss cycles
876 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles
877 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles
878 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles
879 system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles
880 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for ReadReq accesses
881 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016149 # mshr miss rate for ReadReq accesses
882 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for demand accesses
883 system.cpu.icache.demand_mshr_miss_rate::total 0.016149 # mshr miss rate for demand accesses
884 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for overall accesses
885 system.cpu.icache.overall_mshr_miss_rate::total 0.016149 # mshr miss rate for overall accesses
886 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12652.955347 # average ReadReq mshr miss latency
887 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12652.955347 # average ReadReq mshr miss latency
888 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency
889 system.cpu.icache.demand_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency
890 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency
891 system.cpu.icache.overall_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency
892 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency
893 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
894 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
895 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
896 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
897 system.cpu.l2cache.tags.replacements 999968 # number of replacements
898 system.cpu.l2cache.tags.tagsinuse 65207.127423 # Cycle average of tags in use
899 system.cpu.l2cache.tags.total_refs 41555308 # Total number of references to valid blocks.
900 system.cpu.l2cache.tags.sampled_refs 1062213 # Sample count of references to valid blocks.
901 system.cpu.l2cache.tags.avg_refs 39.121446 # Average number of references to valid blocks.
902 system.cpu.l2cache.tags.warmup_cycle 56076472500 # Cycle when the warmup percentage was hit.
903 system.cpu.l2cache.tags.occ_blocks::writebacks 37737.548410 # Average occupied blocks per requestor
904 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 210.383401 # Average occupied blocks per requestor
905 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 313.931857 # Average occupied blocks per requestor
906 system.cpu.l2cache.tags.occ_blocks::cpu.inst 8489.634618 # Average occupied blocks per requestor
907 system.cpu.l2cache.tags.occ_blocks::cpu.data 18455.629136 # Average occupied blocks per requestor
908 system.cpu.l2cache.tags.occ_percent::writebacks 0.575829 # Average percentage of cache occupancy
909 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003210 # Average percentage of cache occupancy
910 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004790 # Average percentage of cache occupancy
911 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129542 # Average percentage of cache occupancy
912 system.cpu.l2cache.tags.occ_percent::cpu.data 0.281611 # Average percentage of cache occupancy
913 system.cpu.l2cache.tags.occ_percent::total 0.994982 # Average percentage of cache occupancy
914 system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id
915 system.cpu.l2cache.tags.occ_task_id_blocks::1024 61992 # Occupied blocks per task id
916 system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
917 system.cpu.l2cache.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id
918 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
919 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id
920 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id
921 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5510 # Occupied blocks per task id
922 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53605 # Occupied blocks per task id
923 system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id
924 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945923 # Percentage of cache occupancy per task id
925 system.cpu.l2cache.tags.tag_accesses 371220882 # Number of tag accesses
926 system.cpu.l2cache.tags.data_accesses 371220882 # Number of data accesses
927 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309149 # number of ReadReq hits
928 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242072 # number of ReadReq hits
929 system.cpu.l2cache.ReadReq_hits::total 551221 # number of ReadReq hits
930 system.cpu.l2cache.WritebackDirty_hits::writebacks 7246265 # number of WritebackDirty hits
931 system.cpu.l2cache.WritebackDirty_hits::total 7246265 # number of WritebackDirty hits
932 system.cpu.l2cache.WritebackClean_hits::writebacks 13385787 # number of WritebackClean hits
933 system.cpu.l2cache.WritebackClean_hits::total 13385787 # number of WritebackClean hits
934 system.cpu.l2cache.UpgradeReq_hits::cpu.data 8844 # number of UpgradeReq hits
935 system.cpu.l2cache.UpgradeReq_hits::total 8844 # number of UpgradeReq hits
936 system.cpu.l2cache.ReadExReq_hits::cpu.data 1588762 # number of ReadExReq hits
937 system.cpu.l2cache.ReadExReq_hits::total 1588762 # number of ReadExReq hits
938 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13318339 # number of ReadCleanReq hits
939 system.cpu.l2cache.ReadCleanReq_hits::total 13318339 # number of ReadCleanReq hits
940 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5906127 # number of ReadSharedReq hits
941 system.cpu.l2cache.ReadSharedReq_hits::total 5906127 # number of ReadSharedReq hits
942 system.cpu.l2cache.InvalidateReq_hits::cpu.data 738986 # number of InvalidateReq hits
943 system.cpu.l2cache.InvalidateReq_hits::total 738986 # number of InvalidateReq hits
944 system.cpu.l2cache.demand_hits::cpu.dtb.walker 309149 # number of demand (read+write) hits
945 system.cpu.l2cache.demand_hits::cpu.itb.walker 242072 # number of demand (read+write) hits
946 system.cpu.l2cache.demand_hits::cpu.inst 13318339 # number of demand (read+write) hits
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948 system.cpu.l2cache.demand_hits::total 21364449 # number of demand (read+write) hits
949 system.cpu.l2cache.overall_hits::cpu.dtb.walker 309149 # number of overall hits
950 system.cpu.l2cache.overall_hits::cpu.itb.walker 242072 # number of overall hits
951 system.cpu.l2cache.overall_hits::cpu.inst 13318339 # number of overall hits
952 system.cpu.l2cache.overall_hits::cpu.data 7494889 # number of overall hits
953 system.cpu.l2cache.overall_hits::total 21364449 # number of overall hits
954 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2087 # number of ReadReq misses
955 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2218 # number of ReadReq misses
956 system.cpu.l2cache.ReadReq_misses::total 4305 # number of ReadReq misses
957 system.cpu.l2cache.UpgradeReq_misses::cpu.data 32563 # number of UpgradeReq misses
958 system.cpu.l2cache.UpgradeReq_misses::total 32563 # number of UpgradeReq misses
959 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
960 system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
961 system.cpu.l2cache.ReadExReq_misses::cpu.data 316699 # number of ReadExReq misses
962 system.cpu.l2cache.ReadExReq_misses::total 316699 # number of ReadExReq misses
963 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 69565 # number of ReadCleanReq misses
964 system.cpu.l2cache.ReadCleanReq_misses::total 69565 # number of ReadCleanReq misses
965 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 220633 # number of ReadSharedReq misses
966 system.cpu.l2cache.ReadSharedReq_misses::total 220633 # number of ReadSharedReq misses
967 system.cpu.l2cache.InvalidateReq_misses::cpu.data 480041 # number of InvalidateReq misses
968 system.cpu.l2cache.InvalidateReq_misses::total 480041 # number of InvalidateReq misses
969 system.cpu.l2cache.demand_misses::cpu.dtb.walker 2087 # number of demand (read+write) misses
970 system.cpu.l2cache.demand_misses::cpu.itb.walker 2218 # number of demand (read+write) misses
971 system.cpu.l2cache.demand_misses::cpu.inst 69565 # number of demand (read+write) misses
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973 system.cpu.l2cache.demand_misses::total 611202 # number of demand (read+write) misses
974 system.cpu.l2cache.overall_misses::cpu.dtb.walker 2087 # number of overall misses
975 system.cpu.l2cache.overall_misses::cpu.itb.walker 2218 # number of overall misses
976 system.cpu.l2cache.overall_misses::cpu.inst 69565 # number of overall misses
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978 system.cpu.l2cache.overall_misses::total 611202 # number of overall misses
979 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 283625500 # number of ReadReq miss cycles
980 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 302800500 # number of ReadReq miss cycles
981 system.cpu.l2cache.ReadReq_miss_latency::total 586426000 # number of ReadReq miss cycles
982 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1304021500 # number of UpgradeReq miss cycles
983 system.cpu.l2cache.UpgradeReq_miss_latency::total 1304021500 # number of UpgradeReq miss cycles
984 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
985 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
986 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41520058500 # number of ReadExReq miss cycles
987 system.cpu.l2cache.ReadExReq_miss_latency::total 41520058500 # number of ReadExReq miss cycles
988 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9207851000 # number of ReadCleanReq miss cycles
989 system.cpu.l2cache.ReadCleanReq_miss_latency::total 9207851000 # number of ReadCleanReq miss cycles
990 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29368319500 # number of ReadSharedReq miss cycles
991 system.cpu.l2cache.ReadSharedReq_miss_latency::total 29368319500 # number of ReadSharedReq miss cycles
992 system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62527677000 # number of InvalidateReq miss cycles
993 system.cpu.l2cache.InvalidateReq_miss_latency::total 62527677000 # number of InvalidateReq miss cycles
994 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 283625500 # number of demand (read+write) miss cycles
995 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 302800500 # number of demand (read+write) miss cycles
996 system.cpu.l2cache.demand_miss_latency::cpu.inst 9207851000 # number of demand (read+write) miss cycles
997 system.cpu.l2cache.demand_miss_latency::cpu.data 70888378000 # number of demand (read+write) miss cycles
998 system.cpu.l2cache.demand_miss_latency::total 80682655000 # number of demand (read+write) miss cycles
999 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 283625500 # number of overall miss cycles
1000 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 302800500 # number of overall miss cycles
1001 system.cpu.l2cache.overall_miss_latency::cpu.inst 9207851000 # number of overall miss cycles
1002 system.cpu.l2cache.overall_miss_latency::cpu.data 70888378000 # number of overall miss cycles
1003 system.cpu.l2cache.overall_miss_latency::total 80682655000 # number of overall miss cycles
1004 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 311236 # number of ReadReq accesses(hits+misses)
1005 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244290 # number of ReadReq accesses(hits+misses)
1006 system.cpu.l2cache.ReadReq_accesses::total 555526 # number of ReadReq accesses(hits+misses)
1007 system.cpu.l2cache.WritebackDirty_accesses::writebacks 7246265 # number of WritebackDirty accesses(hits+misses)
1008 system.cpu.l2cache.WritebackDirty_accesses::total 7246265 # number of WritebackDirty accesses(hits+misses)
1009 system.cpu.l2cache.WritebackClean_accesses::writebacks 13385787 # number of WritebackClean accesses(hits+misses)
1010 system.cpu.l2cache.WritebackClean_accesses::total 13385787 # number of WritebackClean accesses(hits+misses)
1011 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 41407 # number of UpgradeReq accesses(hits+misses)
1012 system.cpu.l2cache.UpgradeReq_accesses::total 41407 # number of UpgradeReq accesses(hits+misses)
1013 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
1014 system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
1015 system.cpu.l2cache.ReadExReq_accesses::cpu.data 1905461 # number of ReadExReq accesses(hits+misses)
1016 system.cpu.l2cache.ReadExReq_accesses::total 1905461 # number of ReadExReq accesses(hits+misses)
1017 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13387904 # number of ReadCleanReq accesses(hits+misses)
1018 system.cpu.l2cache.ReadCleanReq_accesses::total 13387904 # number of ReadCleanReq accesses(hits+misses)
1019 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6126760 # number of ReadSharedReq accesses(hits+misses)
1020 system.cpu.l2cache.ReadSharedReq_accesses::total 6126760 # number of ReadSharedReq accesses(hits+misses)
1021 system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1219027 # number of InvalidateReq accesses(hits+misses)
1022 system.cpu.l2cache.InvalidateReq_accesses::total 1219027 # number of InvalidateReq accesses(hits+misses)
1023 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 311236 # number of demand (read+write) accesses
1024 system.cpu.l2cache.demand_accesses::cpu.itb.walker 244290 # number of demand (read+write) accesses
1025 system.cpu.l2cache.demand_accesses::cpu.inst 13387904 # number of demand (read+write) accesses
1026 system.cpu.l2cache.demand_accesses::cpu.data 8032221 # number of demand (read+write) accesses
1027 system.cpu.l2cache.demand_accesses::total 21975651 # number of demand (read+write) accesses
1028 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 311236 # number of overall (read+write) accesses
1029 system.cpu.l2cache.overall_accesses::cpu.itb.walker 244290 # number of overall (read+write) accesses
1030 system.cpu.l2cache.overall_accesses::cpu.inst 13387904 # number of overall (read+write) accesses
1031 system.cpu.l2cache.overall_accesses::cpu.data 8032221 # number of overall (read+write) accesses
1032 system.cpu.l2cache.overall_accesses::total 21975651 # number of overall (read+write) accesses
1033 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006706 # miss rate for ReadReq accesses
1034 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009079 # miss rate for ReadReq accesses
1035 system.cpu.l2cache.ReadReq_miss_rate::total 0.007749 # miss rate for ReadReq accesses
1036 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786413 # miss rate for UpgradeReq accesses
1037 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786413 # miss rate for UpgradeReq accesses
1038 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
1039 system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1040 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.166206 # miss rate for ReadExReq accesses
1041 system.cpu.l2cache.ReadExReq_miss_rate::total 0.166206 # miss rate for ReadExReq accesses
1042 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005196 # miss rate for ReadCleanReq accesses
1043 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005196 # miss rate for ReadCleanReq accesses
1044 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036011 # miss rate for ReadSharedReq accesses
1045 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036011 # miss rate for ReadSharedReq accesses
1046 system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.393790 # miss rate for InvalidateReq accesses
1047 system.cpu.l2cache.InvalidateReq_miss_rate::total 0.393790 # miss rate for InvalidateReq accesses
1048 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006706 # miss rate for demand accesses
1049 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009079 # miss rate for demand accesses
1050 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005196 # miss rate for demand accesses
1051 system.cpu.l2cache.demand_miss_rate::cpu.data 0.066897 # miss rate for demand accesses
1052 system.cpu.l2cache.demand_miss_rate::total 0.027813 # miss rate for demand accesses
1053 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006706 # miss rate for overall accesses
1054 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009079 # miss rate for overall accesses
1055 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005196 # miss rate for overall accesses
1056 system.cpu.l2cache.overall_miss_rate::cpu.data 0.066897 # miss rate for overall accesses
1057 system.cpu.l2cache.overall_miss_rate::total 0.027813 # miss rate for overall accesses
1058 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135901.054145 # average ReadReq miss latency
1059 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136519.612263 # average ReadReq miss latency
1060 system.cpu.l2cache.ReadReq_avg_miss_latency::total 136219.744483 # average ReadReq miss latency
1061 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.110616 # average UpgradeReq miss latency
1062 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.110616 # average UpgradeReq miss latency
1063 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
1064 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
1065 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131102.587946 # average ReadExReq miss latency
1066 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131102.587946 # average ReadExReq miss latency
1067 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132363.271760 # average ReadCleanReq miss latency
1068 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132363.271760 # average ReadCleanReq miss latency
1069 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133109.369405 # average ReadSharedReq miss latency
1070 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133109.369405 # average ReadSharedReq miss latency
1071 system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130254.867813 # average InvalidateReq miss latency
1072 system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130254.867813 # average InvalidateReq miss latency
1073 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135901.054145 # average overall miss latency
1074 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136519.612263 # average overall miss latency
1075 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132363.271760 # average overall miss latency
1076 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131926.589148 # average overall miss latency
1077 system.cpu.l2cache.demand_avg_miss_latency::total 132006.529756 # average overall miss latency
1078 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135901.054145 # average overall miss latency
1079 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136519.612263 # average overall miss latency
1080 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132363.271760 # average overall miss latency
1081 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131926.589148 # average overall miss latency
1082 system.cpu.l2cache.overall_avg_miss_latency::total 132006.529756 # average overall miss latency
1083 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1084 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1085 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1086 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1087 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1088 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1089 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1090 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1091 system.cpu.l2cache.writebacks::writebacks 850095 # number of writebacks
1092 system.cpu.l2cache.writebacks::total 850095 # number of writebacks
1093 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2087 # number of ReadReq MSHR misses
1094 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2218 # number of ReadReq MSHR misses
1095 system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses
1096 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32563 # number of UpgradeReq MSHR misses
1097 system.cpu.l2cache.UpgradeReq_mshr_misses::total 32563 # number of UpgradeReq MSHR misses
1098 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1099 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1100 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 316699 # number of ReadExReq MSHR misses
1101 system.cpu.l2cache.ReadExReq_mshr_misses::total 316699 # number of ReadExReq MSHR misses
1102 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 69565 # number of ReadCleanReq MSHR misses
1103 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 69565 # number of ReadCleanReq MSHR misses
1104 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 220633 # number of ReadSharedReq MSHR misses
1105 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 220633 # number of ReadSharedReq MSHR misses
1106 system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 480041 # number of InvalidateReq MSHR misses
1107 system.cpu.l2cache.InvalidateReq_mshr_misses::total 480041 # number of InvalidateReq MSHR misses
1108 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2087 # number of demand (read+write) MSHR misses
1109 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2218 # number of demand (read+write) MSHR misses
1110 system.cpu.l2cache.demand_mshr_misses::cpu.inst 69565 # number of demand (read+write) MSHR misses
1111 system.cpu.l2cache.demand_mshr_misses::cpu.data 537332 # number of demand (read+write) MSHR misses
1112 system.cpu.l2cache.demand_mshr_misses::total 611202 # number of demand (read+write) MSHR misses
1113 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2087 # number of overall MSHR misses
1114 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2218 # number of overall MSHR misses
1115 system.cpu.l2cache.overall_mshr_misses::cpu.inst 69565 # number of overall MSHR misses
1116 system.cpu.l2cache.overall_mshr_misses::cpu.data 537332 # number of overall MSHR misses
1117 system.cpu.l2cache.overall_mshr_misses::total 611202 # number of overall MSHR misses
1118 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
1119 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
1120 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable
1121 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
1122 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
1123 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
1124 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
1125 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses
1126 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 262755500 # number of ReadReq MSHR miss cycles
1127 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280620500 # number of ReadReq MSHR miss cycles
1128 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 543376000 # number of ReadReq MSHR miss cycles
1129 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2212537500 # number of UpgradeReq MSHR miss cycles
1130 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2212537500 # number of UpgradeReq MSHR miss cycles
1131 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
1132 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
1133 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38353068500 # number of ReadExReq MSHR miss cycles
1134 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38353068500 # number of ReadExReq MSHR miss cycles
1135 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8512201000 # number of ReadCleanReq MSHR miss cycles
1136 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8512201000 # number of ReadCleanReq MSHR miss cycles
1137 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27161989500 # number of ReadSharedReq MSHR miss cycles
1138 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27161989500 # number of ReadSharedReq MSHR miss cycles
1139 system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 57727267000 # number of InvalidateReq MSHR miss cycles
1140 system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 57727267000 # number of InvalidateReq MSHR miss cycles
1141 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 262755500 # number of demand (read+write) MSHR miss cycles
1142 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280620500 # number of demand (read+write) MSHR miss cycles
1143 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8512201000 # number of demand (read+write) MSHR miss cycles
1144 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65515058000 # number of demand (read+write) MSHR miss cycles
1145 system.cpu.l2cache.demand_mshr_miss_latency::total 74570635000 # number of demand (read+write) MSHR miss cycles
1146 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 262755500 # number of overall MSHR miss cycles
1147 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280620500 # number of overall MSHR miss cycles
1148 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8512201000 # number of overall MSHR miss cycles
1149 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65515058000 # number of overall MSHR miss cycles
1150 system.cpu.l2cache.overall_mshr_miss_latency::total 74570635000 # number of overall MSHR miss cycles
1151 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles
1152 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777574500 # number of ReadReq MSHR uncacheable cycles
1153 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675299000 # number of ReadReq MSHR uncacheable cycles
1154 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829970500 # number of WriteReq MSHR uncacheable cycles
1155 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829970500 # number of WriteReq MSHR uncacheable cycles
1156 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles
1157 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607545000 # number of overall MSHR uncacheable cycles
1158 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505269500 # number of overall MSHR uncacheable cycles
1159 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for ReadReq accesses
1160 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for ReadReq accesses
1161 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007749 # mshr miss rate for ReadReq accesses
1162 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786413 # mshr miss rate for UpgradeReq accesses
1163 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786413 # mshr miss rate for UpgradeReq accesses
1164 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1165 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1166 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166206 # mshr miss rate for ReadExReq accesses
1167 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166206 # mshr miss rate for ReadExReq accesses
1168 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for ReadCleanReq accesses
1169 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005196 # mshr miss rate for ReadCleanReq accesses
1170 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036011 # mshr miss rate for ReadSharedReq accesses
1171 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036011 # mshr miss rate for ReadSharedReq accesses
1172 system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393790 # mshr miss rate for InvalidateReq accesses
1173 system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393790 # mshr miss rate for InvalidateReq accesses
1174 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for demand accesses
1175 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for demand accesses
1176 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for demand accesses
1177 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for demand accesses
1178 system.cpu.l2cache.demand_mshr_miss_rate::total 0.027813 # mshr miss rate for demand accesses
1179 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for overall accesses
1180 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for overall accesses
1181 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for overall accesses
1182 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for overall accesses
1183 system.cpu.l2cache.overall_mshr_miss_rate::total 0.027813 # mshr miss rate for overall accesses
1184 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average ReadReq mshr miss latency
1185 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average ReadReq mshr miss latency
1186 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126219.744483 # average ReadReq mshr miss latency
1187 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67946.365507 # average UpgradeReq mshr miss latency
1188 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67946.365507 # average UpgradeReq mshr miss latency
1189 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
1190 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
1191 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121102.587946 # average ReadExReq mshr miss latency
1192 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121102.587946 # average ReadExReq mshr miss latency
1193 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122363.271760 # average ReadCleanReq mshr miss latency
1194 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122363.271760 # average ReadCleanReq mshr miss latency
1195 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123109.369405 # average ReadSharedReq mshr miss latency
1196 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123109.369405 # average ReadSharedReq mshr miss latency
1197 system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120254.867813 # average InvalidateReq mshr miss latency
1198 system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120254.867813 # average InvalidateReq mshr miss latency
1199 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency
1200 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency
1201 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency
1202 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency
1203 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency
1204 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency
1205 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency
1206 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency
1207 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency
1208 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency
1209 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency
1210 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171431.205863 # average ReadReq mshr uncacheable latency
1211 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.438596 # average ReadReq mshr uncacheable latency
1212 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172955.099680 # average WriteReq mshr uncacheable latency
1213 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172955.099680 # average WriteReq mshr uncacheable latency
1214 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency
1215 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.220590 # average overall mshr uncacheable latency
1216 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.658298 # average overall mshr uncacheable latency
1217 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1218 system.cpu.toL2Bus.snoop_filter.tot_requests 45794965 # Total number of requests made to the snoop filter.
1219 system.cpu.toL2Bus.snoop_filter.hit_single_requests 23155820 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1220 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1221 system.cpu.toL2Bus.snoop_filter.tot_snoops 2699 # Total number of snoops made to the snoop filter.
1222 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2699 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1223 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1224 system.cpu.toL2Bus.trans_dist::ReadReq 972147 # Transaction distribution
1225 system.cpu.toL2Bus.trans_dist::ReadResp 20487667 # Transaction distribution
1226 system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
1227 system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
1228 system.cpu.toL2Bus.trans_dist::WritebackDirty 8203050 # Transaction distribution
1229 system.cpu.toL2Bus.trans_dist::WritebackClean 13387387 # Transaction distribution
1230 system.cpu.toL2Bus.trans_dist::CleanEvict 2163174 # Transaction distribution
1231 system.cpu.toL2Bus.trans_dist::UpgradeReq 41410 # Transaction distribution
1232 system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1233 system.cpu.toL2Bus.trans_dist::UpgradeResp 41412 # Transaction distribution
1234 system.cpu.toL2Bus.trans_dist::ReadExReq 1905461 # Transaction distribution
1235 system.cpu.toL2Bus.trans_dist::ReadExResp 1905461 # Transaction distribution
1236 system.cpu.toL2Bus.trans_dist::ReadCleanReq 13387904 # Transaction distribution
1237 system.cpu.toL2Bus.trans_dist::ReadSharedReq 6135636 # Transaction distribution
1238 system.cpu.toL2Bus.trans_dist::InvalidateReq 1325691 # Transaction distribution
1239 system.cpu.toL2Bus.trans_dist::InvalidateResp 1219027 # Transaction distribution
1240 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40249445 # Packet count per connected master and slave (bytes)
1241 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27971705 # Packet count per connected master and slave (bytes)
1242 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598323 # Packet count per connected master and slave (bytes)
1243 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 852523 # Packet count per connected master and slave (bytes)
1244 system.cpu.toL2Bus.pkt_count::total 69671996 # Packet count per connected master and slave (bytes)
1245 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1713791124 # Cumulative packet size per connected master and slave (bytes)
1246 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978068334 # Cumulative packet size per connected master and slave (bytes)
1247 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1954320 # Cumulative packet size per connected master and slave (bytes)
1248 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2489888 # Cumulative packet size per connected master and slave (bytes)
1249 system.cpu.toL2Bus.pkt_size::total 2696303666 # Cumulative packet size per connected master and slave (bytes)
1250 system.cpu.toL2Bus.snoops 1571708 # Total snoops (count)
1251 system.cpu.toL2Bus.snoop_fanout::samples 24917471 # Request fanout histogram
1252 system.cpu.toL2Bus.snoop_fanout::mean 0.019294 # Request fanout histogram
1253 system.cpu.toL2Bus.snoop_fanout::stdev 0.137557 # Request fanout histogram
1254 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1255 system.cpu.toL2Bus.snoop_fanout::0 24436707 98.07% 98.07% # Request fanout histogram
1256 system.cpu.toL2Bus.snoop_fanout::1 480764 1.93% 100.00% # Request fanout histogram
1257 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1258 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1259 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1260 system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1261 system.cpu.toL2Bus.snoop_fanout::total 24917471 # Request fanout histogram
1262 system.cpu.toL2Bus.reqLayer0.occupancy 43812763500 # Layer occupancy (ticks)
1263 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1264 system.cpu.toL2Bus.snoopLayer0.occupancy 1591387 # Layer occupancy (ticks)
1265 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1266 system.cpu.toL2Bus.respLayer0.occupancy 20124981000 # Layer occupancy (ticks)
1267 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1268 system.cpu.toL2Bus.respLayer1.occupancy 12729124462 # Layer occupancy (ticks)
1269 system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1270 system.cpu.toL2Bus.respLayer2.occupancy 354033000 # Layer occupancy (ticks)
1271 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1272 system.cpu.toL2Bus.respLayer3.occupancy 541287000 # Layer occupancy (ticks)
1273 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1274 system.iobus.trans_dist::ReadReq 40324 # Transaction distribution
1275 system.iobus.trans_dist::ReadResp 40324 # Transaction distribution
1276 system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1277 system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1278 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1279 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1280 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1281 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1282 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1283 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1284 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1285 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1286 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1287 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1288 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1289 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1290 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1291 system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1292 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes)
1293 system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes)
1294 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1295 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1296 system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes)
1297 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1298 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1299 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
1300 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1301 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1302 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1303 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1304 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1305 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1306 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1307 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1308 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1309 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1310 system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1311 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes)
1312 system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes)
1313 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1314 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1315 system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes)
1316 system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks)
1317 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1318 system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
1319 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1320 system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
1321 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1322 system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
1323 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1324 system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks)
1325 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1326 system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
1327 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1328 system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
1329 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1330 system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1331 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1332 system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
1333 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1334 system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks)
1335 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1336 system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
1337 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1338 system.iobus.reqLayer23.occupancy 25712000 # Layer occupancy (ticks)
1339 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1340 system.iobus.reqLayer24.occupancy 38603000 # Layer occupancy (ticks)
1341 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1342 system.iobus.reqLayer25.occupancy 566837671 # Layer occupancy (ticks)
1343 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1344 system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1345 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1346 system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks)
1347 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1348 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1349 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1350 system.iocache.tags.replacements 115484 # number of replacements
1351 system.iocache.tags.tagsinuse 10.446945 # Cycle average of tags in use
1352 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1353 system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks.
1354 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1355 system.iocache.tags.warmup_cycle 13183709781000 # Cycle when the warmup percentage was hit.
1356 system.iocache.tags.occ_blocks::realview.ethernet 3.511462 # Average occupied blocks per requestor
1357 system.iocache.tags.occ_blocks::realview.ide 6.935482 # Average occupied blocks per requestor
1358 system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy
1359 system.iocache.tags.occ_percent::realview.ide 0.433468 # Average percentage of cache occupancy
1360 system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy
1361 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1362 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1363 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1364 system.iocache.tags.tag_accesses 1039884 # Number of tag accesses
1365 system.iocache.tags.data_accesses 1039884 # Number of data accesses
1366 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1367 system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses
1368 system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses
1369 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1370 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1371 system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1372 system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1373 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1374 system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses
1375 system.iocache.demand_misses::total 8879 # number of demand (read+write) misses
1376 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1377 system.iocache.overall_misses::realview.ide 8839 # number of overall misses
1378 system.iocache.overall_misses::total 8879 # number of overall misses
1379 system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles
1380 system.iocache.ReadReq_miss_latency::realview.ide 1648554138 # number of ReadReq miss cycles
1381 system.iocache.ReadReq_miss_latency::total 1653624638 # number of ReadReq miss cycles
1382 system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
1383 system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
1384 system.iocache.WriteLineReq_miss_latency::realview.ide 13411902033 # number of WriteLineReq miss cycles
1385 system.iocache.WriteLineReq_miss_latency::total 13411902033 # number of WriteLineReq miss cycles
1386 system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles
1387 system.iocache.demand_miss_latency::realview.ide 1648554138 # number of demand (read+write) miss cycles
1388 system.iocache.demand_miss_latency::total 1653975638 # number of demand (read+write) miss cycles
1389 system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles
1390 system.iocache.overall_miss_latency::realview.ide 1648554138 # number of overall miss cycles
1391 system.iocache.overall_miss_latency::total 1653975638 # number of overall miss cycles
1392 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1393 system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses)
1394 system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses)
1395 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1396 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1397 system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
1398 system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
1399 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1400 system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses
1401 system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
1402 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1403 system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses
1404 system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses
1405 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1406 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1407 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1408 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1409 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1410 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1411 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1412 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1413 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1414 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1415 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1416 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1417 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1418 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency
1419 system.iocache.ReadReq_avg_miss_latency::realview.ide 186509.122978 # average ReadReq miss latency
1420 system.iocache.ReadReq_avg_miss_latency::total 186302.910996 # average ReadReq miss latency
1421 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
1422 system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
1423 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.725053 # average WriteLineReq miss latency
1424 system.iocache.WriteLineReq_avg_miss_latency::total 125739.725053 # average WriteLineReq miss latency
1425 system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
1426 system.iocache.demand_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency
1427 system.iocache.demand_avg_miss_latency::total 186279.495213 # average overall miss latency
1428 system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
1429 system.iocache.overall_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency
1430 system.iocache.overall_avg_miss_latency::total 186279.495213 # average overall miss latency
1431 system.iocache.blocked_cycles::no_mshrs 32796 # number of cycles access was blocked
1432 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1433 system.iocache.blocked::no_mshrs 3360 # number of cycles access was blocked
1434 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1435 system.iocache.avg_blocked_cycles::no_mshrs 9.760714 # average number of cycles each access was blocked
1436 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1437 system.iocache.fast_writes 0 # number of fast writes performed
1438 system.iocache.cache_copies 0 # number of cache copies performed
1439 system.iocache.writebacks::writebacks 106630 # number of writebacks
1440 system.iocache.writebacks::total 106630 # number of writebacks
1441 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1442 system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses
1443 system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses
1444 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1445 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1446 system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
1447 system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
1448 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1449 system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses
1450 system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses
1451 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1452 system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
1453 system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
1454 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles
1455 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206604138 # number of ReadReq MSHR miss cycles
1456 system.iocache.ReadReq_mshr_miss_latency::total 1209824638 # number of ReadReq MSHR miss cycles
1457 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
1458 system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
1459 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073565122 # number of WriteLineReq MSHR miss cycles
1460 system.iocache.WriteLineReq_mshr_miss_latency::total 8073565122 # number of WriteLineReq MSHR miss cycles
1461 system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles
1462 system.iocache.demand_mshr_miss_latency::realview.ide 1206604138 # number of demand (read+write) MSHR miss cycles
1463 system.iocache.demand_mshr_miss_latency::total 1210025638 # number of demand (read+write) MSHR miss cycles
1464 system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles
1465 system.iocache.overall_mshr_miss_latency::realview.ide 1206604138 # number of overall MSHR miss cycles
1466 system.iocache.overall_mshr_miss_latency::total 1210025638 # number of overall MSHR miss cycles
1467 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1468 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1469 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1470 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1471 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1472 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1473 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1474 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1475 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1476 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1477 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1478 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1479 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1480 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency
1481 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136509.122978 # average ReadReq mshr miss latency
1482 system.iocache.ReadReq_avg_mshr_miss_latency::total 136302.910996 # average ReadReq mshr miss latency
1483 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
1484 system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
1485 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.565308 # average WriteLineReq mshr miss latency
1486 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.565308 # average WriteLineReq mshr miss latency
1487 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
1488 system.iocache.demand_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency
1489 system.iocache.demand_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency
1490 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
1491 system.iocache.overall_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency
1492 system.iocache.overall_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency
1493 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1494 system.membus.trans_dist::ReadReq 76827 # Transaction distribution
1495 system.membus.trans_dist::ReadResp 380206 # Transaction distribution
1496 system.membus.trans_dist::WriteReq 33708 # Transaction distribution
1497 system.membus.trans_dist::WriteResp 33708 # Transaction distribution
1498 system.membus.trans_dist::WritebackDirty 956725 # Transaction distribution
1499 system.membus.trans_dist::CleanEvict 157718 # Transaction distribution
1500 system.membus.trans_dist::UpgradeReq 33138 # Transaction distribution
1501 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1502 system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
1503 system.membus.trans_dist::ReadExReq 796168 # Transaction distribution
1504 system.membus.trans_dist::ReadExResp 796168 # Transaction distribution
1505 system.membus.trans_dist::ReadSharedReq 303379 # Transaction distribution
1506 system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
1507 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1508 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
1509 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
1510 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3304162 # Packet count per connected master and slave (bytes)
1511 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3433854 # Packet count per connected master and slave (bytes)
1512 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237247 # Packet count per connected master and slave (bytes)
1513 system.membus.pkt_count_system.iocache.mem_side::total 237247 # Packet count per connected master and slave (bytes)
1514 system.membus.pkt_count::total 3671101 # Packet count per connected master and slave (bytes)
1515 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1516 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
1517 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
1518 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124360288 # Cumulative packet size per connected master and slave (bytes)
1519 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124530114 # Cumulative packet size per connected master and slave (bytes)
1520 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7222400 # Cumulative packet size per connected master and slave (bytes)
1521 system.membus.pkt_size_system.iocache.mem_side::total 7222400 # Cumulative packet size per connected master and slave (bytes)
1522 system.membus.pkt_size::total 131752514 # Cumulative packet size per connected master and slave (bytes)
1523 system.membus.snoops 3318 # Total snoops (count)
1524 system.membus.snoop_fanout::samples 2464390 # Request fanout histogram
1525 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1526 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1527 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1528 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1529 system.membus.snoop_fanout::1 2464390 100.00% 100.00% # Request fanout histogram
1530 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1531 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1532 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1533 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1534 system.membus.snoop_fanout::total 2464390 # Request fanout histogram
1535 system.membus.reqLayer0.occupancy 106890000 # Layer occupancy (ticks)
1536 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1537 system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
1538 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1539 system.membus.reqLayer2.occupancy 5800500 # Layer occupancy (ticks)
1540 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1541 system.membus.reqLayer5.occupancy 6292280855 # Layer occupancy (ticks)
1542 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1543 system.membus.respLayer2.occupancy 5974901047 # Layer occupancy (ticks)
1544 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1545 system.membus.respLayer3.occupancy 44724954 # Layer occupancy (ticks)
1546 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1547 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1548 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1549 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1550 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1551 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1552 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1553 system.realview.ethernet.txBytes 966 # Bytes Transmitted
1554 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1555 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1556 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1557 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1558 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1559 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1560 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1561 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1562 system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
1563 system.realview.ethernet.totPackets 3 # Total Packets
1564 system.realview.ethernet.totBytes 966 # Total Bytes
1565 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
1566 system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
1567 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
1568 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1569 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
1570 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1571 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1572 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
1573 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1574 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1575 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
1576 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1577 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1578 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
1579 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1580 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1581 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
1582 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1583 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1584 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
1585 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1586 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1587 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1588 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1589 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1590 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1591 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1592 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1593 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1594 system.realview.ethernet.droppedPackets 0 # number of packets dropped
1595 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1596 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1597 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1598 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1600 ---------- End Simulation Statistics ----------
projects / gem5.git / blob