8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
15 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
18 clk_domain=system.clk_domain
19 dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
20 early_kernel_symbols=false
21 enable_context_switch_stats_dump=false
24 gic_cpu_addr=738205696
25 have_large_asid_64=false
28 have_virtualization=false
29 highest_el_is_64=false
31 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
32 kernel_addr_check=true
33 load_addr_mask=268435455
34 load_offset=2147483648
35 machine_type=VExpress_EMM64
37 mem_ranges=2147483648:2415919103
38 memories=system.physmem system.realview.nvmem system.realview.vram
39 mmap_using_noreserve=false
45 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
48 work_begin_ckpt_count=0
49 work_begin_cpu_id_exit=-1
50 work_begin_exit_count=0
51 work_cpus_ckpt_count=0
55 system_port=system.membus.slave[1]
59 clk_domain=system.clk_domain
62 ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
65 master=system.iobus.slave[0]
66 slave=system.membus.master[0]
74 image=system.cf0.image
79 child=system.cf0.image.child
85 [system.cf0.image.child]
88 image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
97 voltage_domain=system.voltage_domain
101 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
104 clk_domain=system.cpu_clk_domain
106 do_checkpoint_insts=true
108 do_statistics_insts=true
109 dstage2_mmu=system.cpu0.dstage2_mmu
113 function_trace_start=0
114 interrupts=system.cpu0.interrupts
116 istage2_mmu=system.cpu0.istage2_mmu
118 max_insts_all_threads=0
119 max_insts_any_thread=0
120 max_loads_all_threads=0
121 max_loads_any_thread=0
125 simpoint_start_insts=
129 tracer=system.cpu0.tracer
131 dcache_port=system.cpu0.dcache.cpu_side
132 icache_port=system.cpu0.icache.cpu_side
137 addr_ranges=0:18446744073709551615
139 clk_domain=system.cpu_clk_domain
140 demand_mshr_reserve=1
147 prefetch_on_access=false
150 sequential_access=false
153 tags=system.cpu0.dcache.tags
156 cpu_side=system.cpu0.dcache_port
157 mem_side=system.cpu0.toL2Bus.slave[1]
159 [system.cpu0.dcache.tags]
163 clk_domain=system.cpu_clk_domain
166 sequential_access=false
169 [system.cpu0.dstage2_mmu]
173 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
177 [system.cpu0.dstage2_mmu.stage2_tlb]
183 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
185 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
187 clk_domain=system.cpu_clk_domain
190 num_squash_per_cycle=2
199 walker=system.cpu0.dtb.walker
201 [system.cpu0.dtb.walker]
203 clk_domain=system.cpu_clk_domain
206 num_squash_per_cycle=2
208 port=system.cpu0.toL2Bus.slave[3]
213 addr_ranges=0:18446744073709551615
215 clk_domain=system.cpu_clk_domain
216 demand_mshr_reserve=1
223 prefetch_on_access=false
226 sequential_access=false
229 tags=system.cpu0.icache.tags
232 cpu_side=system.cpu0.icache_port
233 mem_side=system.cpu0.toL2Bus.slave[0]
235 [system.cpu0.icache.tags]
239 clk_domain=system.cpu_clk_domain
242 sequential_access=false
245 [system.cpu0.interrupts]
255 id_aa64dfr0_el1=1052678
259 id_aa64mmfr0_el1=15728642
279 [system.cpu0.istage2_mmu]
283 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
287 [system.cpu0.istage2_mmu.stage2_tlb]
293 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
295 [system.cpu0.istage2_mmu.stage2_tlb.walker]
297 clk_domain=system.cpu_clk_domain
300 num_squash_per_cycle=2
309 walker=system.cpu0.itb.walker
311 [system.cpu0.itb.walker]
313 clk_domain=system.cpu_clk_domain
316 num_squash_per_cycle=2
318 port=system.cpu0.toL2Bus.slave[2]
320 [system.cpu0.l2cache]
322 children=prefetcher tags
323 addr_ranges=0:18446744073709551615
325 clk_domain=system.cpu_clk_domain
326 demand_mshr_reserve=1
333 prefetch_on_access=true
334 prefetcher=system.cpu0.l2cache.prefetcher
336 sequential_access=false
339 tags=system.cpu0.l2cache.tags
342 cpu_side=system.cpu0.toL2Bus.master[0]
343 mem_side=system.toL2Bus.slave[0]
345 [system.cpu0.l2cache.prefetcher]
346 type=StridePrefetcher
348 clk_domain=system.cpu_clk_domain
370 [system.cpu0.l2cache.tags]
374 clk_domain=system.cpu_clk_domain
377 sequential_access=false
380 [system.cpu0.toL2Bus]
382 clk_domain=system.cpu_clk_domain
388 snoop_response_latency=1
390 use_default_range=false
392 master=system.cpu0.l2cache.cpu_side
393 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
401 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
404 clk_domain=system.cpu_clk_domain
406 do_checkpoint_insts=true
408 do_statistics_insts=true
409 dstage2_mmu=system.cpu1.dstage2_mmu
413 function_trace_start=0
414 interrupts=system.cpu1.interrupts
416 istage2_mmu=system.cpu1.istage2_mmu
418 max_insts_all_threads=0
419 max_insts_any_thread=0
420 max_loads_all_threads=0
421 max_loads_any_thread=0
425 simpoint_start_insts=
429 tracer=system.cpu1.tracer
431 dcache_port=system.cpu1.dcache.cpu_side
432 icache_port=system.cpu1.icache.cpu_side
437 addr_ranges=0:18446744073709551615
439 clk_domain=system.cpu_clk_domain
440 demand_mshr_reserve=1
447 prefetch_on_access=false
450 sequential_access=false
453 tags=system.cpu1.dcache.tags
456 cpu_side=system.cpu1.dcache_port
457 mem_side=system.cpu1.toL2Bus.slave[1]
459 [system.cpu1.dcache.tags]
463 clk_domain=system.cpu_clk_domain
466 sequential_access=false
469 [system.cpu1.dstage2_mmu]
473 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
477 [system.cpu1.dstage2_mmu.stage2_tlb]
483 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
485 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
487 clk_domain=system.cpu_clk_domain
490 num_squash_per_cycle=2
499 walker=system.cpu1.dtb.walker
501 [system.cpu1.dtb.walker]
503 clk_domain=system.cpu_clk_domain
506 num_squash_per_cycle=2
508 port=system.cpu1.toL2Bus.slave[3]
513 addr_ranges=0:18446744073709551615
515 clk_domain=system.cpu_clk_domain
516 demand_mshr_reserve=1
523 prefetch_on_access=false
526 sequential_access=false
529 tags=system.cpu1.icache.tags
532 cpu_side=system.cpu1.icache_port
533 mem_side=system.cpu1.toL2Bus.slave[0]
535 [system.cpu1.icache.tags]
539 clk_domain=system.cpu_clk_domain
542 sequential_access=false
545 [system.cpu1.interrupts]
555 id_aa64dfr0_el1=1052678
559 id_aa64mmfr0_el1=15728642
579 [system.cpu1.istage2_mmu]
583 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
587 [system.cpu1.istage2_mmu.stage2_tlb]
593 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
595 [system.cpu1.istage2_mmu.stage2_tlb.walker]
597 clk_domain=system.cpu_clk_domain
600 num_squash_per_cycle=2
609 walker=system.cpu1.itb.walker
611 [system.cpu1.itb.walker]
613 clk_domain=system.cpu_clk_domain
616 num_squash_per_cycle=2
618 port=system.cpu1.toL2Bus.slave[2]
620 [system.cpu1.l2cache]
622 children=prefetcher tags
623 addr_ranges=0:18446744073709551615
625 clk_domain=system.cpu_clk_domain
626 demand_mshr_reserve=1
633 prefetch_on_access=true
634 prefetcher=system.cpu1.l2cache.prefetcher
636 sequential_access=false
639 tags=system.cpu1.l2cache.tags
642 cpu_side=system.cpu1.toL2Bus.master[0]
643 mem_side=system.toL2Bus.slave[1]
645 [system.cpu1.l2cache.prefetcher]
646 type=StridePrefetcher
648 clk_domain=system.cpu_clk_domain
670 [system.cpu1.l2cache.tags]
674 clk_domain=system.cpu_clk_domain
677 sequential_access=false
680 [system.cpu1.toL2Bus]
682 clk_domain=system.cpu_clk_domain
688 snoop_response_latency=1
690 use_default_range=false
692 master=system.cpu1.l2cache.cpu_side
693 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
699 [system.cpu_clk_domain]
705 voltage_domain=system.voltage_domain
707 [system.dvfs_handler]
712 sys_clk_domain=system.clk_domain
713 transition_latency=100000000
722 clk_domain=system.clk_domain
727 use_default_range=true
729 default=system.realview.pciconfig.pio
730 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
731 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
736 addr_ranges=2147483648:2415919103
738 clk_domain=system.clk_domain
739 demand_mshr_reserve=1
746 prefetch_on_access=false
749 sequential_access=false
752 tags=system.iocache.tags
755 cpu_side=system.iobus.master[27]
756 mem_side=system.membus.slave[3]
758 [system.iocache.tags]
762 clk_domain=system.clk_domain
765 sequential_access=false
771 addr_ranges=0:18446744073709551615
773 clk_domain=system.cpu_clk_domain
774 demand_mshr_reserve=1
781 prefetch_on_access=false
784 sequential_access=false
790 cpu_side=system.toL2Bus.master[0]
791 mem_side=system.membus.slave[2]
797 clk_domain=system.cpu_clk_domain
800 sequential_access=false
805 children=badaddr_responder
806 clk_domain=system.clk_domain
812 snoop_response_latency=4
814 use_default_range=false
816 default=system.membus.badaddr_responder.pio
817 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
818 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
820 [system.membus.badaddr_responder]
822 clk_domain=system.clk_domain
830 ret_data32=4294967295
831 ret_data64=18446744073709551615
836 pio=system.membus.default
865 addr_mapping=RoRaBaCoCh
866 bank_groups_per_rank=0
870 clk_domain=system.clk_domain
871 conf_table_reported=true
873 device_rowbuffer_size=1024
874 device_size=536870912
879 max_accesses_per_row=16
880 mem_sched_policy=frfcfs
881 min_writes_per_switch=16
883 page_policy=open_adaptive
884 range=2147483648:2415919103
887 static_backend_latency=10000
888 static_frontend_latency=10000
911 write_high_thresh_perc=85
912 write_low_thresh_perc=50
913 port=system.membus.master[5]
917 children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
919 intrctrl=system.intrctrl
920 pci_cfg_base=805306368
921 pci_cfg_gen_offsets=true
922 pci_io_base=788529152
925 [system.realview.aaci_fake]
928 clk_domain=system.clk_domain
934 pio=system.iobus.master[18]
936 [system.realview.cf_ctrl]
976 MSICAPNextCapability=0
980 MSIXCAPNextCapability=0
990 PMCAPNextCapability=0
995 PXCAPDevCapabilities=0
1002 PXCAPNextCapability=0
1010 clk_domain=system.clk_domain
1011 config_latency=20000
1020 platform=system.realview
1022 config=system.iobus.master[9]
1023 dma=system.iobus.slave[2]
1024 pio=system.iobus.master[8]
1026 [system.realview.clcd]
1029 clk_domain=system.clk_domain
1032 gic=system.realview.gic
1038 vnc=system.vncserver
1039 dma=system.iobus.slave[1]
1040 pio=system.iobus.master[4]
1042 [system.realview.energy_ctrl]
1044 clk_domain=system.clk_domain
1045 dvfs_handler=system.dvfs_handler
1050 pio=system.iobus.master[22]
1052 [system.realview.ethernet]
1091 MSICAPMsgUpperAddr=0
1092 MSICAPNextCapability=0
1096 MSIXCAPNextCapability=0
1106 PMCAPNextCapability=0
1111 PXCAPDevCapabilities=0
1118 PXCAPNextCapability=0
1124 SubsystemVendorID=32902
1126 clk_domain=system.clk_domain
1127 config_latency=20000
1129 fetch_comp_delay=10000
1131 hardware_address=00:90:00:00:00:01
1138 platform=system.realview
1139 rx_desc_cache_size=64
1143 tx_desc_cache_size=64
1148 config=system.iobus.master[26]
1149 dma=system.iobus.slave[4]
1150 pio=system.iobus.master[25]
1152 [system.realview.generic_timer]
1155 gic=system.realview.gic
1160 [system.realview.gic]
1162 clk_domain=system.clk_domain
1166 dist_pio_delay=10000
1170 platform=system.realview
1172 pio=system.membus.master[2]
1174 [system.realview.hdlcd]
1177 clk_domain=system.clk_domain
1180 gic=system.realview.gic
1186 vnc=system.vncserver
1187 workaround_swap_rb=true
1188 dma=system.membus.slave[0]
1189 pio=system.iobus.master[5]
1191 [system.realview.ide]
1230 MSICAPMsgUpperAddr=0
1231 MSICAPNextCapability=0
1235 MSIXCAPNextCapability=0
1245 PMCAPNextCapability=0
1250 PXCAPDevCapabilities=0
1257 PXCAPNextCapability=0
1265 clk_domain=system.clk_domain
1266 config_latency=20000
1275 platform=system.realview
1277 config=system.iobus.master[24]
1278 dma=system.iobus.slave[3]
1279 pio=system.iobus.master[23]
1281 [system.realview.kmi0]
1284 clk_domain=system.clk_domain
1286 gic=system.realview.gic
1293 vnc=system.vncserver
1294 pio=system.iobus.master[6]
1296 [system.realview.kmi1]
1299 clk_domain=system.clk_domain
1301 gic=system.realview.gic
1308 vnc=system.vncserver
1309 pio=system.iobus.master[7]
1311 [system.realview.l2x0_fake]
1313 clk_domain=system.clk_domain
1321 ret_data32=4294967295
1322 ret_data64=18446744073709551615
1327 pio=system.iobus.master[12]
1329 [system.realview.lan_fake]
1331 clk_domain=system.clk_domain
1339 ret_data32=4294967295
1340 ret_data64=18446744073709551615
1345 pio=system.iobus.master[19]
1347 [system.realview.local_cpu_timer]
1349 clk_domain=system.clk_domain
1351 gic=system.realview.gic
1357 pio=system.membus.master[4]
1359 [system.realview.mmc_fake]
1362 clk_domain=system.clk_domain
1368 pio=system.iobus.master[21]
1370 [system.realview.nvmem]
1373 clk_domain=system.clk_domain
1374 conf_table_reported=true
1381 port=system.membus.master[1]
1383 [system.realview.pciconfig]
1386 clk_domain=system.clk_domain
1390 platform=system.realview
1393 pio=system.iobus.default
1395 [system.realview.realview_io]
1397 clk_domain=system.clk_domain
1405 pio=system.iobus.master[1]
1407 [system.realview.rtc]
1410 clk_domain=system.clk_domain
1412 gic=system.realview.gic
1418 time=Thu Jan 1 00:00:00 2009
1419 pio=system.iobus.master[10]
1421 [system.realview.sp810_fake]
1424 clk_domain=system.clk_domain
1430 pio=system.iobus.master[16]
1432 [system.realview.timer0]
1435 clk_domain=system.clk_domain
1439 gic=system.realview.gic
1445 pio=system.iobus.master[2]
1447 [system.realview.timer1]
1450 clk_domain=system.clk_domain
1454 gic=system.realview.gic
1460 pio=system.iobus.master[3]
1462 [system.realview.uart]
1464 clk_domain=system.clk_domain
1467 gic=system.realview.gic
1472 platform=system.realview
1474 terminal=system.terminal
1475 pio=system.iobus.master[0]
1477 [system.realview.uart1_fake]
1480 clk_domain=system.clk_domain
1486 pio=system.iobus.master[13]
1488 [system.realview.uart2_fake]
1491 clk_domain=system.clk_domain
1497 pio=system.iobus.master[14]
1499 [system.realview.uart3_fake]
1502 clk_domain=system.clk_domain
1508 pio=system.iobus.master[15]
1510 [system.realview.usb_fake]
1512 clk_domain=system.clk_domain
1520 ret_data32=4294967295
1521 ret_data64=18446744073709551615
1526 pio=system.iobus.master[20]
1528 [system.realview.vgic]
1530 clk_domain=system.clk_domain
1532 gic=system.realview.gic
1535 platform=system.realview
1539 pio=system.membus.master[3]
1541 [system.realview.vram]
1544 clk_domain=system.clk_domain
1545 conf_table_reported=false
1551 range=402653184:436207615
1552 port=system.iobus.master[11]
1554 [system.realview.watchdog_fake]
1557 clk_domain=system.clk_domain
1563 pio=system.iobus.master[17]
1568 intr_control=system.intrctrl
1575 clk_domain=system.cpu_clk_domain
1581 snoop_response_latency=1
1583 use_default_range=false
1585 master=system.l2c.cpu_side
1586 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1595 [system.voltage_domain]