tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=true
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=LinuxArmSystem
  13 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
  14 atags_addr=134217728
  15 boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
  16 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
  17 cache_line_size=64
  18 clk_domain=system.clk_domain
  19 default_p_state=UNDEFINED
  20 dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
  21 early_kernel_symbols=false
  22 enable_context_switch_stats_dump=false
  23 eventq_index=0
  24 exit_on_work_items=false
  25 flags_addr=469827632
  26 gic_cpu_addr=738205696
  27 have_large_asid_64=false
  28 have_lpae=true
  29 have_security=false
  30 have_virtualization=false
  31 highest_el_is_64=false
  32 init_param=0
  33 kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
  34 kernel_addr_check=true
  35 load_addr_mask=268435455
  36 load_offset=2147483648
  37 machine_type=VExpress_EMM64
  38 mem_mode=timing
  39 mem_ranges=2147483648:2415919103:0:0:0:0
  40 memories=system.physmem system.realview.nvmem system.realview.vram
  41 mmap_using_noreserve=false
  42 multi_proc=true
  43 multi_thread=false
  44 num_work_ids=16
  45 p_state_clk_gate_bins=20
  46 p_state_clk_gate_max=1000000000000
  47 p_state_clk_gate_min=1000
  48 panic_on_oops=true
  49 panic_on_panic=true
  50 phys_addr_range_64=40
  51 power_model=Null
  52 readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
  53 reset_addr_64=0
  54 symbolfile=
  55 thermal_components=
  56 thermal_model=Null
  57 work_begin_ckpt_count=0
  58 work_begin_cpu_id_exit=-1
  59 work_begin_exit_count=0
  60 work_cpus_ckpt_count=0
  61 work_end_ckpt_count=0
  62 work_end_exit_count=0
  63 work_item_id=-1
  64 system_port=system.membus.slave[1]
  65
  66 [system.bridge]
  67 type=Bridge
  68 clk_domain=system.clk_domain
  69 default_p_state=UNDEFINED
  70 delay=50000
  71 eventq_index=0
  72 p_state_clk_gate_bins=20
  73 p_state_clk_gate_max=1000000000000
  74 p_state_clk_gate_min=1000
  75 power_model=Null
  76 ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
  77 req_size=16
  78 resp_size=16
  79 master=system.iobus.slave[0]
  80 slave=system.membus.master[0]
  81
  82 [system.cf0]
  83 type=IdeDisk
  84 children=image
  85 delay=1000000
  86 driveID=master
  87 eventq_index=0
  88 image=system.cf0.image
  89
  90 [system.cf0.image]
  91 type=CowDiskImage
  92 children=child
  93 child=system.cf0.image.child
  94 eventq_index=0
  95 image_file=
  96 read_only=false
  97 table_size=65536
  98
  99 [system.cf0.image.child]
 100 type=RawDiskImage
 101 eventq_index=0
 102 image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
 103 read_only=true
 104
 105 [system.clk_domain]
 106 type=SrcClockDomain
 107 clock=1000
 108 domain_id=-1
 109 eventq_index=0
 110 init_perf_level=0
 111 voltage_domain=system.voltage_domain
 112
 113 [system.cpu0]
 114 type=TimingSimpleCPU
 115 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 116 branchPred=Null
 117 checker=Null
 118 clk_domain=system.cpu_clk_domain
 119 cpu_id=0
 120 default_p_state=UNDEFINED
 121 do_checkpoint_insts=true
 122 do_quiesce=true
 123 do_statistics_insts=true
 124 dstage2_mmu=system.cpu0.dstage2_mmu
 125 dtb=system.cpu0.dtb
 126 eventq_index=0
 127 function_trace=false
 128 function_trace_start=0
 129 interrupts=system.cpu0.interrupts
 130 isa=system.cpu0.isa
 131 istage2_mmu=system.cpu0.istage2_mmu
 132 itb=system.cpu0.itb
 133 max_insts_all_threads=0
 134 max_insts_any_thread=0
 135 max_loads_all_threads=0
 136 max_loads_any_thread=0
 137 numThreads=1
 138 p_state_clk_gate_bins=20
 139 p_state_clk_gate_max=1000000000000
 140 p_state_clk_gate_min=1000
 141 power_model=Null
 142 profile=0
 143 progress_interval=0
 144 simpoint_start_insts=
 145 socket_id=0
 146 switched_out=false
 147 system=system
 148 tracer=system.cpu0.tracer
 149 workload=
 150 dcache_port=system.cpu0.dcache.cpu_side
 151 icache_port=system.cpu0.icache.cpu_side
 152
 153 [system.cpu0.dcache]
 154 type=Cache
 155 children=tags
 156 addr_ranges=0:18446744073709551615:0:0:0:0
 157 assoc=2
 158 clk_domain=system.cpu_clk_domain
 159 clusivity=mostly_incl
 160 default_p_state=UNDEFINED
 161 demand_mshr_reserve=1
 162 eventq_index=0
 163 hit_latency=2
 164 is_read_only=false
 165 max_miss_count=0
 166 mshrs=6
 167 p_state_clk_gate_bins=20
 168 p_state_clk_gate_max=1000000000000
 169 p_state_clk_gate_min=1000
 170 power_model=Null
 171 prefetch_on_access=false
 172 prefetcher=Null
 173 response_latency=2
 174 sequential_access=false
 175 size=32768
 176 system=system
 177 tags=system.cpu0.dcache.tags
 178 tgts_per_mshr=8
 179 write_buffers=16
 180 writeback_clean=true
 181 cpu_side=system.cpu0.dcache_port
 182 mem_side=system.cpu0.toL2Bus.slave[1]
 183
 184 [system.cpu0.dcache.tags]
 185 type=LRU
 186 assoc=2
 187 block_size=64
 188 clk_domain=system.cpu_clk_domain
 189 default_p_state=UNDEFINED
 190 eventq_index=0
 191 hit_latency=2
 192 p_state_clk_gate_bins=20
 193 p_state_clk_gate_max=1000000000000
 194 p_state_clk_gate_min=1000
 195 power_model=Null
 196 sequential_access=false
 197 size=32768
 198
 199 [system.cpu0.dstage2_mmu]
 200 type=ArmStage2MMU
 201 children=stage2_tlb
 202 eventq_index=0
 203 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
 204 sys=system
 205 tlb=system.cpu0.dtb
 206
 207 [system.cpu0.dstage2_mmu.stage2_tlb]
 208 type=ArmTLB
 209 children=walker
 210 eventq_index=0
 211 is_stage2=true
 212 size=32
 213 walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
 214
 215 [system.cpu0.dstage2_mmu.stage2_tlb.walker]
 216 type=ArmTableWalker
 217 clk_domain=system.cpu_clk_domain
 218 default_p_state=UNDEFINED
 219 eventq_index=0
 220 is_stage2=true
 221 num_squash_per_cycle=2
 222 p_state_clk_gate_bins=20
 223 p_state_clk_gate_max=1000000000000
 224 p_state_clk_gate_min=1000
 225 power_model=Null
 226 sys=system
 227
 228 [system.cpu0.dtb]
 229 type=ArmTLB
 230 children=walker
 231 eventq_index=0
 232 is_stage2=false
 233 size=64
 234 walker=system.cpu0.dtb.walker
 235
 236 [system.cpu0.dtb.walker]
 237 type=ArmTableWalker
 238 clk_domain=system.cpu_clk_domain
 239 default_p_state=UNDEFINED
 240 eventq_index=0
 241 is_stage2=false
 242 num_squash_per_cycle=2
 243 p_state_clk_gate_bins=20
 244 p_state_clk_gate_max=1000000000000
 245 p_state_clk_gate_min=1000
 246 power_model=Null
 247 sys=system
 248 port=system.cpu0.toL2Bus.slave[3]
 249
 250 [system.cpu0.icache]
 251 type=Cache
 252 children=tags
 253 addr_ranges=0:18446744073709551615:0:0:0:0
 254 assoc=2
 255 clk_domain=system.cpu_clk_domain
 256 clusivity=mostly_incl
 257 default_p_state=UNDEFINED
 258 demand_mshr_reserve=1
 259 eventq_index=0
 260 hit_latency=1
 261 is_read_only=true
 262 max_miss_count=0
 263 mshrs=2
 264 p_state_clk_gate_bins=20
 265 p_state_clk_gate_max=1000000000000
 266 p_state_clk_gate_min=1000
 267 power_model=Null
 268 prefetch_on_access=false
 269 prefetcher=Null
 270 response_latency=1
 271 sequential_access=false
 272 size=32768
 273 system=system
 274 tags=system.cpu0.icache.tags
 275 tgts_per_mshr=8
 276 write_buffers=8
 277 writeback_clean=true
 278 cpu_side=system.cpu0.icache_port
 279 mem_side=system.cpu0.toL2Bus.slave[0]
 280
 281 [system.cpu0.icache.tags]
 282 type=LRU
 283 assoc=2
 284 block_size=64
 285 clk_domain=system.cpu_clk_domain
 286 default_p_state=UNDEFINED
 287 eventq_index=0
 288 hit_latency=1
 289 p_state_clk_gate_bins=20
 290 p_state_clk_gate_max=1000000000000
 291 p_state_clk_gate_min=1000
 292 power_model=Null
 293 sequential_access=false
 294 size=32768
 295
 296 [system.cpu0.interrupts]
 297 type=ArmInterrupts
 298 eventq_index=0
 299
 300 [system.cpu0.isa]
 301 type=ArmISA
 302 decoderFlavour=Generic
 303 eventq_index=0
 304 fpsid=1090793632
 305 id_aa64afr0_el1=0
 306 id_aa64afr1_el1=0
 307 id_aa64dfr0_el1=1052678
 308 id_aa64dfr1_el1=0
 309 id_aa64isar0_el1=0
 310 id_aa64isar1_el1=0
 311 id_aa64mmfr0_el1=15728642
 312 id_aa64mmfr1_el1=0
 313 id_aa64pfr0_el1=34
 314 id_aa64pfr1_el1=0
 315 id_isar0=34607377
 316 id_isar1=34677009
 317 id_isar2=555950401
 318 id_isar3=17899825
 319 id_isar4=268501314
 320 id_isar5=0
 321 id_mmfr0=270536963
 322 id_mmfr1=0
 323 id_mmfr2=19070976
 324 id_mmfr3=34611729
 325 id_pfr0=49
 326 id_pfr1=4113
 327 midr=1091551472
 328 pmu=Null
 329 system=system
 330
 331 [system.cpu0.istage2_mmu]
 332 type=ArmStage2MMU
 333 children=stage2_tlb
 334 eventq_index=0
 335 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
 336 sys=system
 337 tlb=system.cpu0.itb
 338
 339 [system.cpu0.istage2_mmu.stage2_tlb]
 340 type=ArmTLB
 341 children=walker
 342 eventq_index=0
 343 is_stage2=true
 344 size=32
 345 walker=system.cpu0.istage2_mmu.stage2_tlb.walker
 346
 347 [system.cpu0.istage2_mmu.stage2_tlb.walker]
 348 type=ArmTableWalker
 349 clk_domain=system.cpu_clk_domain
 350 default_p_state=UNDEFINED
 351 eventq_index=0
 352 is_stage2=true
 353 num_squash_per_cycle=2
 354 p_state_clk_gate_bins=20
 355 p_state_clk_gate_max=1000000000000
 356 p_state_clk_gate_min=1000
 357 power_model=Null
 358 sys=system
 359
 360 [system.cpu0.itb]
 361 type=ArmTLB
 362 children=walker
 363 eventq_index=0
 364 is_stage2=false
 365 size=64
 366 walker=system.cpu0.itb.walker
 367
 368 [system.cpu0.itb.walker]
 369 type=ArmTableWalker
 370 clk_domain=system.cpu_clk_domain
 371 default_p_state=UNDEFINED
 372 eventq_index=0
 373 is_stage2=false
 374 num_squash_per_cycle=2
 375 p_state_clk_gate_bins=20
 376 p_state_clk_gate_max=1000000000000
 377 p_state_clk_gate_min=1000
 378 power_model=Null
 379 sys=system
 380 port=system.cpu0.toL2Bus.slave[2]
 381
 382 [system.cpu0.l2cache]
 383 type=Cache
 384 children=prefetcher tags
 385 addr_ranges=0:18446744073709551615:0:0:0:0
 386 assoc=16
 387 clk_domain=system.cpu_clk_domain
 388 clusivity=mostly_excl
 389 default_p_state=UNDEFINED
 390 demand_mshr_reserve=1
 391 eventq_index=0
 392 hit_latency=12
 393 is_read_only=false
 394 max_miss_count=0
 395 mshrs=16
 396 p_state_clk_gate_bins=20
 397 p_state_clk_gate_max=1000000000000
 398 p_state_clk_gate_min=1000
 399 power_model=Null
 400 prefetch_on_access=true
 401 prefetcher=system.cpu0.l2cache.prefetcher
 402 response_latency=12
 403 sequential_access=false
 404 size=1048576
 405 system=system
 406 tags=system.cpu0.l2cache.tags
 407 tgts_per_mshr=8
 408 write_buffers=8
 409 writeback_clean=false
 410 cpu_side=system.cpu0.toL2Bus.master[0]
 411 mem_side=system.toL2Bus.slave[0]
 412
 413 [system.cpu0.l2cache.prefetcher]
 414 type=StridePrefetcher
 415 cache_snoop=false
 416 clk_domain=system.cpu_clk_domain
 417 default_p_state=UNDEFINED
 418 degree=8
 419 eventq_index=0
 420 latency=1
 421 max_conf=7
 422 min_conf=0
 423 on_data=true
 424 on_inst=true
 425 on_miss=false
 426 on_read=true
 427 on_write=true
 428 p_state_clk_gate_bins=20
 429 p_state_clk_gate_max=1000000000000
 430 p_state_clk_gate_min=1000
 431 power_model=Null
 432 queue_filter=true
 433 queue_size=32
 434 queue_squash=true
 435 start_conf=4
 436 sys=system
 437 table_assoc=4
 438 table_sets=16
 439 tag_prefetch=true
 440 thresh_conf=4
 441 use_master_id=true
 442
 443 [system.cpu0.l2cache.tags]
 444 type=RandomRepl
 445 assoc=16
 446 block_size=64
 447 clk_domain=system.cpu_clk_domain
 448 default_p_state=UNDEFINED
 449 eventq_index=0
 450 hit_latency=12
 451 p_state_clk_gate_bins=20
 452 p_state_clk_gate_max=1000000000000
 453 p_state_clk_gate_min=1000
 454 power_model=Null
 455 sequential_access=false
 456 size=1048576
 457
 458 [system.cpu0.toL2Bus]
 459 type=CoherentXBar
 460 children=snoop_filter
 461 clk_domain=system.cpu_clk_domain
 462 default_p_state=UNDEFINED
 463 eventq_index=0
 464 forward_latency=0
 465 frontend_latency=1
 466 p_state_clk_gate_bins=20
 467 p_state_clk_gate_max=1000000000000
 468 p_state_clk_gate_min=1000
 469 point_of_coherency=false
 470 power_model=Null
 471 response_latency=1
 472 snoop_filter=system.cpu0.toL2Bus.snoop_filter
 473 snoop_response_latency=1
 474 system=system
 475 use_default_range=false
 476 width=32
 477 master=system.cpu0.l2cache.cpu_side
 478 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 479
 480 [system.cpu0.toL2Bus.snoop_filter]
 481 type=SnoopFilter
 482 eventq_index=0
 483 lookup_latency=0
 484 max_capacity=8388608
 485 system=system
 486
 487 [system.cpu0.tracer]
 488 type=ExeTracer
 489 eventq_index=0
 490
 491 [system.cpu1]
 492 type=TimingSimpleCPU
 493 children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 494 branchPred=Null
 495 checker=Null
 496 clk_domain=system.cpu_clk_domain
 497 cpu_id=1
 498 default_p_state=UNDEFINED
 499 do_checkpoint_insts=true
 500 do_quiesce=true
 501 do_statistics_insts=true
 502 dstage2_mmu=system.cpu1.dstage2_mmu
 503 dtb=system.cpu1.dtb
 504 eventq_index=0
 505 function_trace=false
 506 function_trace_start=0
 507 interrupts=system.cpu1.interrupts
 508 isa=system.cpu1.isa
 509 istage2_mmu=system.cpu1.istage2_mmu
 510 itb=system.cpu1.itb
 511 max_insts_all_threads=0
 512 max_insts_any_thread=0
 513 max_loads_all_threads=0
 514 max_loads_any_thread=0
 515 numThreads=1
 516 p_state_clk_gate_bins=20
 517 p_state_clk_gate_max=1000000000000
 518 p_state_clk_gate_min=1000
 519 power_model=Null
 520 profile=0
 521 progress_interval=0
 522 simpoint_start_insts=
 523 socket_id=0
 524 switched_out=false
 525 system=system
 526 tracer=system.cpu1.tracer
 527 workload=
 528 dcache_port=system.cpu1.dcache.cpu_side
 529 icache_port=system.cpu1.icache.cpu_side
 530
 531 [system.cpu1.dcache]
 532 type=Cache
 533 children=tags
 534 addr_ranges=0:18446744073709551615:0:0:0:0
 535 assoc=2
 536 clk_domain=system.cpu_clk_domain
 537 clusivity=mostly_incl
 538 default_p_state=UNDEFINED
 539 demand_mshr_reserve=1
 540 eventq_index=0
 541 hit_latency=2
 542 is_read_only=false
 543 max_miss_count=0
 544 mshrs=6
 545 p_state_clk_gate_bins=20
 546 p_state_clk_gate_max=1000000000000
 547 p_state_clk_gate_min=1000
 548 power_model=Null
 549 prefetch_on_access=false
 550 prefetcher=Null
 551 response_latency=2
 552 sequential_access=false
 553 size=32768
 554 system=system
 555 tags=system.cpu1.dcache.tags
 556 tgts_per_mshr=8
 557 write_buffers=16
 558 writeback_clean=true
 559 cpu_side=system.cpu1.dcache_port
 560 mem_side=system.cpu1.toL2Bus.slave[1]
 561
 562 [system.cpu1.dcache.tags]
 563 type=LRU
 564 assoc=2
 565 block_size=64
 566 clk_domain=system.cpu_clk_domain
 567 default_p_state=UNDEFINED
 568 eventq_index=0
 569 hit_latency=2
 570 p_state_clk_gate_bins=20
 571 p_state_clk_gate_max=1000000000000
 572 p_state_clk_gate_min=1000
 573 power_model=Null
 574 sequential_access=false
 575 size=32768
 576
 577 [system.cpu1.dstage2_mmu]
 578 type=ArmStage2MMU
 579 children=stage2_tlb
 580 eventq_index=0
 581 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
 582 sys=system
 583 tlb=system.cpu1.dtb
 584
 585 [system.cpu1.dstage2_mmu.stage2_tlb]
 586 type=ArmTLB
 587 children=walker
 588 eventq_index=0
 589 is_stage2=true
 590 size=32
 591 walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
 592
 593 [system.cpu1.dstage2_mmu.stage2_tlb.walker]
 594 type=ArmTableWalker
 595 clk_domain=system.cpu_clk_domain
 596 default_p_state=UNDEFINED
 597 eventq_index=0
 598 is_stage2=true
 599 num_squash_per_cycle=2
 600 p_state_clk_gate_bins=20
 601 p_state_clk_gate_max=1000000000000
 602 p_state_clk_gate_min=1000
 603 power_model=Null
 604 sys=system
 605
 606 [system.cpu1.dtb]
 607 type=ArmTLB
 608 children=walker
 609 eventq_index=0
 610 is_stage2=false
 611 size=64
 612 walker=system.cpu1.dtb.walker
 613
 614 [system.cpu1.dtb.walker]
 615 type=ArmTableWalker
 616 clk_domain=system.cpu_clk_domain
 617 default_p_state=UNDEFINED
 618 eventq_index=0
 619 is_stage2=false
 620 num_squash_per_cycle=2
 621 p_state_clk_gate_bins=20
 622 p_state_clk_gate_max=1000000000000
 623 p_state_clk_gate_min=1000
 624 power_model=Null
 625 sys=system
 626 port=system.cpu1.toL2Bus.slave[3]
 627
 628 [system.cpu1.icache]
 629 type=Cache
 630 children=tags
 631 addr_ranges=0:18446744073709551615:0:0:0:0
 632 assoc=2
 633 clk_domain=system.cpu_clk_domain
 634 clusivity=mostly_incl
 635 default_p_state=UNDEFINED
 636 demand_mshr_reserve=1
 637 eventq_index=0
 638 hit_latency=1
 639 is_read_only=true
 640 max_miss_count=0
 641 mshrs=2
 642 p_state_clk_gate_bins=20
 643 p_state_clk_gate_max=1000000000000
 644 p_state_clk_gate_min=1000
 645 power_model=Null
 646 prefetch_on_access=false
 647 prefetcher=Null
 648 response_latency=1
 649 sequential_access=false
 650 size=32768
 651 system=system
 652 tags=system.cpu1.icache.tags
 653 tgts_per_mshr=8
 654 write_buffers=8
 655 writeback_clean=true
 656 cpu_side=system.cpu1.icache_port
 657 mem_side=system.cpu1.toL2Bus.slave[0]
 658
 659 [system.cpu1.icache.tags]
 660 type=LRU
 661 assoc=2
 662 block_size=64
 663 clk_domain=system.cpu_clk_domain
 664 default_p_state=UNDEFINED
 665 eventq_index=0
 666 hit_latency=1
 667 p_state_clk_gate_bins=20
 668 p_state_clk_gate_max=1000000000000
 669 p_state_clk_gate_min=1000
 670 power_model=Null
 671 sequential_access=false
 672 size=32768
 673
 674 [system.cpu1.interrupts]
 675 type=ArmInterrupts
 676 eventq_index=0
 677
 678 [system.cpu1.isa]
 679 type=ArmISA
 680 decoderFlavour=Generic
 681 eventq_index=0
 682 fpsid=1090793632
 683 id_aa64afr0_el1=0
 684 id_aa64afr1_el1=0
 685 id_aa64dfr0_el1=1052678
 686 id_aa64dfr1_el1=0
 687 id_aa64isar0_el1=0
 688 id_aa64isar1_el1=0
 689 id_aa64mmfr0_el1=15728642
 690 id_aa64mmfr1_el1=0
 691 id_aa64pfr0_el1=34
 692 id_aa64pfr1_el1=0
 693 id_isar0=34607377
 694 id_isar1=34677009
 695 id_isar2=555950401
 696 id_isar3=17899825
 697 id_isar4=268501314
 698 id_isar5=0
 699 id_mmfr0=270536963
 700 id_mmfr1=0
 701 id_mmfr2=19070976
 702 id_mmfr3=34611729
 703 id_pfr0=49
 704 id_pfr1=4113
 705 midr=1091551472
 706 pmu=Null
 707 system=system
 708
 709 [system.cpu1.istage2_mmu]
 710 type=ArmStage2MMU
 711 children=stage2_tlb
 712 eventq_index=0
 713 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
 714 sys=system
 715 tlb=system.cpu1.itb
 716
 717 [system.cpu1.istage2_mmu.stage2_tlb]
 718 type=ArmTLB
 719 children=walker
 720 eventq_index=0
 721 is_stage2=true
 722 size=32
 723 walker=system.cpu1.istage2_mmu.stage2_tlb.walker
 724
 725 [system.cpu1.istage2_mmu.stage2_tlb.walker]
 726 type=ArmTableWalker
 727 clk_domain=system.cpu_clk_domain
 728 default_p_state=UNDEFINED
 729 eventq_index=0
 730 is_stage2=true
 731 num_squash_per_cycle=2
 732 p_state_clk_gate_bins=20
 733 p_state_clk_gate_max=1000000000000
 734 p_state_clk_gate_min=1000
 735 power_model=Null
 736 sys=system
 737
 738 [system.cpu1.itb]
 739 type=ArmTLB
 740 children=walker
 741 eventq_index=0
 742 is_stage2=false
 743 size=64
 744 walker=system.cpu1.itb.walker
 745
 746 [system.cpu1.itb.walker]
 747 type=ArmTableWalker
 748 clk_domain=system.cpu_clk_domain
 749 default_p_state=UNDEFINED
 750 eventq_index=0
 751 is_stage2=false
 752 num_squash_per_cycle=2
 753 p_state_clk_gate_bins=20
 754 p_state_clk_gate_max=1000000000000
 755 p_state_clk_gate_min=1000
 756 power_model=Null
 757 sys=system
 758 port=system.cpu1.toL2Bus.slave[2]
 759
 760 [system.cpu1.l2cache]
 761 type=Cache
 762 children=prefetcher tags
 763 addr_ranges=0:18446744073709551615:0:0:0:0
 764 assoc=16
 765 clk_domain=system.cpu_clk_domain
 766 clusivity=mostly_excl
 767 default_p_state=UNDEFINED
 768 demand_mshr_reserve=1
 769 eventq_index=0
 770 hit_latency=12
 771 is_read_only=false
 772 max_miss_count=0
 773 mshrs=16
 774 p_state_clk_gate_bins=20
 775 p_state_clk_gate_max=1000000000000
 776 p_state_clk_gate_min=1000
 777 power_model=Null
 778 prefetch_on_access=true
 779 prefetcher=system.cpu1.l2cache.prefetcher
 780 response_latency=12
 781 sequential_access=false
 782 size=1048576
 783 system=system
 784 tags=system.cpu1.l2cache.tags
 785 tgts_per_mshr=8
 786 write_buffers=8
 787 writeback_clean=false
 788 cpu_side=system.cpu1.toL2Bus.master[0]
 789 mem_side=system.toL2Bus.slave[1]
 790
 791 [system.cpu1.l2cache.prefetcher]
 792 type=StridePrefetcher
 793 cache_snoop=false
 794 clk_domain=system.cpu_clk_domain
 795 default_p_state=UNDEFINED
 796 degree=8
 797 eventq_index=0
 798 latency=1
 799 max_conf=7
 800 min_conf=0
 801 on_data=true
 802 on_inst=true
 803 on_miss=false
 804 on_read=true
 805 on_write=true
 806 p_state_clk_gate_bins=20
 807 p_state_clk_gate_max=1000000000000
 808 p_state_clk_gate_min=1000
 809 power_model=Null
 810 queue_filter=true
 811 queue_size=32
 812 queue_squash=true
 813 start_conf=4
 814 sys=system
 815 table_assoc=4
 816 table_sets=16
 817 tag_prefetch=true
 818 thresh_conf=4
 819 use_master_id=true
 820
 821 [system.cpu1.l2cache.tags]
 822 type=RandomRepl
 823 assoc=16
 824 block_size=64
 825 clk_domain=system.cpu_clk_domain
 826 default_p_state=UNDEFINED
 827 eventq_index=0
 828 hit_latency=12
 829 p_state_clk_gate_bins=20
 830 p_state_clk_gate_max=1000000000000
 831 p_state_clk_gate_min=1000
 832 power_model=Null
 833 sequential_access=false
 834 size=1048576
 835
 836 [system.cpu1.toL2Bus]
 837 type=CoherentXBar
 838 children=snoop_filter
 839 clk_domain=system.cpu_clk_domain
 840 default_p_state=UNDEFINED
 841 eventq_index=0
 842 forward_latency=0
 843 frontend_latency=1
 844 p_state_clk_gate_bins=20
 845 p_state_clk_gate_max=1000000000000
 846 p_state_clk_gate_min=1000
 847 point_of_coherency=false
 848 power_model=Null
 849 response_latency=1
 850 snoop_filter=system.cpu1.toL2Bus.snoop_filter
 851 snoop_response_latency=1
 852 system=system
 853 use_default_range=false
 854 width=32
 855 master=system.cpu1.l2cache.cpu_side
 856 slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 857
 858 [system.cpu1.toL2Bus.snoop_filter]
 859 type=SnoopFilter
 860 eventq_index=0
 861 lookup_latency=0
 862 max_capacity=8388608
 863 system=system
 864
 865 [system.cpu1.tracer]
 866 type=ExeTracer
 867 eventq_index=0
 868
 869 [system.cpu_clk_domain]
 870 type=SrcClockDomain
 871 clock=500
 872 domain_id=-1
 873 eventq_index=0
 874 init_perf_level=0
 875 voltage_domain=system.voltage_domain
 876
 877 [system.dvfs_handler]
 878 type=DVFSHandler
 879 domains=
 880 enable=false
 881 eventq_index=0
 882 sys_clk_domain=system.clk_domain
 883 transition_latency=100000000
 884
 885 [system.intrctrl]
 886 type=IntrControl
 887 eventq_index=0
 888 sys=system
 889
 890 [system.iobus]
 891 type=NoncoherentXBar
 892 clk_domain=system.clk_domain
 893 default_p_state=UNDEFINED
 894 eventq_index=0
 895 forward_latency=1
 896 frontend_latency=2
 897 p_state_clk_gate_bins=20
 898 p_state_clk_gate_max=1000000000000
 899 p_state_clk_gate_min=1000
 900 power_model=Null
 901 response_latency=2
 902 use_default_range=false
 903 width=16
 904 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 905 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 906
 907 [system.iocache]
 908 type=Cache
 909 children=tags
 910 addr_ranges=2147483648:2415919103:0:0:0:0
 911 assoc=8
 912 clk_domain=system.clk_domain
 913 clusivity=mostly_incl
 914 default_p_state=UNDEFINED
 915 demand_mshr_reserve=1
 916 eventq_index=0
 917 hit_latency=50
 918 is_read_only=false
 919 max_miss_count=0
 920 mshrs=20
 921 p_state_clk_gate_bins=20
 922 p_state_clk_gate_max=1000000000000
 923 p_state_clk_gate_min=1000
 924 power_model=Null
 925 prefetch_on_access=false
 926 prefetcher=Null
 927 response_latency=50
 928 sequential_access=false
 929 size=1024
 930 system=system
 931 tags=system.iocache.tags
 932 tgts_per_mshr=12
 933 write_buffers=8
 934 writeback_clean=false
 935 cpu_side=system.iobus.master[25]
 936 mem_side=system.membus.slave[3]
 937
 938 [system.iocache.tags]
 939 type=LRU
 940 assoc=8
 941 block_size=64
 942 clk_domain=system.clk_domain
 943 default_p_state=UNDEFINED
 944 eventq_index=0
 945 hit_latency=50
 946 p_state_clk_gate_bins=20
 947 p_state_clk_gate_max=1000000000000
 948 p_state_clk_gate_min=1000
 949 power_model=Null
 950 sequential_access=false
 951 size=1024
 952
 953 [system.l2c]
 954 type=Cache
 955 children=tags
 956 addr_ranges=0:18446744073709551615:0:0:0:0
 957 assoc=8
 958 clk_domain=system.cpu_clk_domain
 959 clusivity=mostly_incl
 960 default_p_state=UNDEFINED
 961 demand_mshr_reserve=1
 962 eventq_index=0
 963 hit_latency=20
 964 is_read_only=false
 965 max_miss_count=0
 966 mshrs=20
 967 p_state_clk_gate_bins=20
 968 p_state_clk_gate_max=1000000000000
 969 p_state_clk_gate_min=1000
 970 power_model=Null
 971 prefetch_on_access=false
 972 prefetcher=Null
 973 response_latency=20
 974 sequential_access=false
 975 size=4194304
 976 system=system
 977 tags=system.l2c.tags
 978 tgts_per_mshr=12
 979 write_buffers=8
 980 writeback_clean=false
 981 cpu_side=system.toL2Bus.master[0]
 982 mem_side=system.membus.slave[2]
 983
 984 [system.l2c.tags]
 985 type=LRU
 986 assoc=8
 987 block_size=64
 988 clk_domain=system.cpu_clk_domain
 989 default_p_state=UNDEFINED
 990 eventq_index=0
 991 hit_latency=20
 992 p_state_clk_gate_bins=20
 993 p_state_clk_gate_max=1000000000000
 994 p_state_clk_gate_min=1000
 995 power_model=Null
 996 sequential_access=false
 997 size=4194304
 998
 999 [system.membus]
1000 type=CoherentXBar
1001 children=badaddr_responder snoop_filter
1002 clk_domain=system.clk_domain
1003 default_p_state=UNDEFINED
1004 eventq_index=0
1005 forward_latency=4
1006 frontend_latency=3
1007 p_state_clk_gate_bins=20
1008 p_state_clk_gate_max=1000000000000
1009 p_state_clk_gate_min=1000
1010 point_of_coherency=true
1011 power_model=Null
1012 response_latency=2
1013 snoop_filter=system.membus.snoop_filter
1014 snoop_response_latency=4
1015 system=system
1016 use_default_range=false
1017 width=16
1018 default=system.membus.badaddr_responder.pio
1019 master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
1020 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1021
1022 [system.membus.badaddr_responder]
1023 type=IsaFake
1024 clk_domain=system.clk_domain
1025 default_p_state=UNDEFINED
1026 eventq_index=0
1027 fake_mem=false
1028 p_state_clk_gate_bins=20
1029 p_state_clk_gate_max=1000000000000
1030 p_state_clk_gate_min=1000
1031 pio_addr=0
1032 pio_latency=100000
1033 pio_size=8
1034 power_model=Null
1035 ret_bad_addr=true
1036 ret_data16=65535
1037 ret_data32=4294967295
1038 ret_data64=18446744073709551615
1039 ret_data8=255
1040 system=system
1041 update_data=false
1042 warn_access=warn
1043 pio=system.membus.default
1044
1045 [system.membus.snoop_filter]
1046 type=SnoopFilter
1047 eventq_index=0
1048 lookup_latency=1
1049 max_capacity=8388608
1050 system=system
1051
1052 [system.physmem]
1053 type=DRAMCtrl
1054 IDD0=0.055000
1055 IDD02=0.000000
1056 IDD2N=0.032000
1057 IDD2N2=0.000000
1058 IDD2P0=0.000000
1059 IDD2P02=0.000000
1060 IDD2P1=0.032000
1061 IDD2P12=0.000000
1062 IDD3N=0.038000
1063 IDD3N2=0.000000
1064 IDD3P0=0.000000
1065 IDD3P02=0.000000
1066 IDD3P1=0.038000
1067 IDD3P12=0.000000
1068 IDD4R=0.157000
1069 IDD4R2=0.000000
1070 IDD4W=0.125000
1071 IDD4W2=0.000000
1072 IDD5=0.235000
1073 IDD52=0.000000
1074 IDD6=0.020000
1075 IDD62=0.000000
1076 VDD=1.500000
1077 VDD2=0.000000
1078 activation_limit=4
1079 addr_mapping=RoRaBaCoCh
1080 bank_groups_per_rank=0
1081 banks_per_rank=8
1082 burst_length=8
1083 channels=1
1084 clk_domain=system.clk_domain
1085 conf_table_reported=true
1086 default_p_state=UNDEFINED
1087 device_bus_width=8
1088 device_rowbuffer_size=1024
1089 device_size=536870912
1090 devices_per_rank=8
1091 dll=true
1092 eventq_index=0
1093 in_addr_map=true
1094 kvm_map=true
1095 max_accesses_per_row=16
1096 mem_sched_policy=frfcfs
1097 min_writes_per_switch=16
1098 null=false
1099 p_state_clk_gate_bins=20
1100 p_state_clk_gate_max=1000000000000
1101 p_state_clk_gate_min=1000
1102 page_policy=open_adaptive
1103 power_model=Null
1104 range=2147483648:2415919103:0:0:0:0
1105 ranks_per_channel=2
1106 read_buffer_size=32
1107 static_backend_latency=10000
1108 static_frontend_latency=10000
1109 tBURST=5000
1110 tCCD_L=0
1111 tCK=1250
1112 tCL=13750
1113 tCS=2500
1114 tRAS=35000
1115 tRCD=13750
1116 tREFI=7800000
1117 tRFC=260000
1118 tRP=13750
1119 tRRD=6000
1120 tRRD_L=0
1121 tRTP=7500
1122 tRTW=2500
1123 tWR=15000
1124 tWTR=7500
1125 tXAW=30000
1126 tXP=6000
1127 tXPDLL=0
1128 tXS=270000
1129 tXSDLL=0
1130 write_buffer_size=64
1131 write_high_thresh_perc=85
1132 write_low_thresh_perc=50
1133 port=system.membus.master[5]
1134
1135 [system.realview]
1136 type=RealView
1137 children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
1138 eventq_index=0
1139 intrctrl=system.intrctrl
1140 system=system
1141
1142 [system.realview.aaci_fake]
1143 type=AmbaFake
1144 amba_id=0
1145 clk_domain=system.clk_domain
1146 default_p_state=UNDEFINED
1147 eventq_index=0
1148 ignore_access=false
1149 p_state_clk_gate_bins=20
1150 p_state_clk_gate_max=1000000000000
1151 p_state_clk_gate_min=1000
1152 pio_addr=470024192
1153 pio_latency=100000
1154 power_model=Null
1155 system=system
1156 pio=system.iobus.master[18]
1157
1158 [system.realview.cf_ctrl]
1159 type=IdeController
1160 BAR0=471465984
1161 BAR0LegacyIO=true
1162 BAR0Size=256
1163 BAR1=471466240
1164 BAR1LegacyIO=true
1165 BAR1Size=4096
1166 BAR2=1
1167 BAR2LegacyIO=false
1168 BAR2Size=8
1169 BAR3=1
1170 BAR3LegacyIO=false
1171 BAR3Size=4
1172 BAR4=1
1173 BAR4LegacyIO=false
1174 BAR4Size=16
1175 BAR5=1
1176 BAR5LegacyIO=false
1177 BAR5Size=0
1178 BIST=0
1179 CacheLineSize=0
1180 CapabilityPtr=0
1181 CardbusCIS=0
1182 ClassCode=1
1183 Command=1
1184 DeviceID=28945
1185 ExpansionROM=0
1186 HeaderType=0
1187 InterruptLine=31
1188 InterruptPin=1
1189 LatencyTimer=0
1190 LegacyIOBase=0
1191 MSICAPBaseOffset=0
1192 MSICAPCapId=0
1193 MSICAPMaskBits=0
1194 MSICAPMsgAddr=0
1195 MSICAPMsgCtrl=0
1196 MSICAPMsgData=0
1197 MSICAPMsgUpperAddr=0
1198 MSICAPNextCapability=0
1199 MSICAPPendingBits=0
1200 MSIXCAPBaseOffset=0
1201 MSIXCAPCapId=0
1202 MSIXCAPNextCapability=0
1203 MSIXMsgCtrl=0
1204 MSIXPbaOffset=0
1205 MSIXTableOffset=0
1206 MaximumLatency=0
1207 MinimumGrant=0
1208 PMCAPBaseOffset=0
1209 PMCAPCapId=0
1210 PMCAPCapabilities=0
1211 PMCAPCtrlStatus=0
1212 PMCAPNextCapability=0
1213 PXCAPBaseOffset=0
1214 PXCAPCapId=0
1215 PXCAPCapabilities=0
1216 PXCAPDevCap2=0
1217 PXCAPDevCapabilities=0
1218 PXCAPDevCtrl=0
1219 PXCAPDevCtrl2=0
1220 PXCAPDevStatus=0
1221 PXCAPLinkCap=0
1222 PXCAPLinkCtrl=0
1223 PXCAPLinkStatus=0
1224 PXCAPNextCapability=0
1225 ProgIF=133
1226 Revision=0
1227 Status=640
1228 SubClassCode=1
1229 SubsystemID=0
1230 SubsystemVendorID=0
1231 VendorID=32902
1232 clk_domain=system.clk_domain
1233 config_latency=20000
1234 ctrl_offset=2
1235 default_p_state=UNDEFINED
1236 disks=
1237 eventq_index=0
1238 host=system.realview.pci_host
1239 io_shift=2
1240 p_state_clk_gate_bins=20
1241 p_state_clk_gate_max=1000000000000
1242 p_state_clk_gate_min=1000
1243 pci_bus=2
1244 pci_dev=0
1245 pci_func=0
1246 pio_latency=30000
1247 power_model=Null
1248 system=system
1249 dma=system.iobus.slave[2]
1250 pio=system.iobus.master[9]
1251
1252 [system.realview.clcd]
1253 type=Pl111
1254 amba_id=1315089
1255 clk_domain=system.clk_domain
1256 default_p_state=UNDEFINED
1257 enable_capture=true
1258 eventq_index=0
1259 gic=system.realview.gic
1260 int_num=46
1261 p_state_clk_gate_bins=20
1262 p_state_clk_gate_max=1000000000000
1263 p_state_clk_gate_min=1000
1264 pio_addr=471793664
1265 pio_latency=10000
1266 pixel_clock=41667
1267 power_model=Null
1268 system=system
1269 vnc=system.vncserver
1270 dma=system.iobus.slave[1]
1271 pio=system.iobus.master[5]
1272
1273 [system.realview.dcc]
1274 type=SubSystem
1275 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
1276 eventq_index=0
1277 thermal_domain=Null
1278
1279 [system.realview.dcc.osc_cpu]
1280 type=RealViewOsc
1281 dcc=0
1282 device=0
1283 eventq_index=0
1284 freq=16667
1285 parent=system.realview.realview_io
1286 position=0
1287 site=1
1288 voltage_domain=system.voltage_domain
1289
1290 [system.realview.dcc.osc_ddr]
1291 type=RealViewOsc
1292 dcc=0
1293 device=8
1294 eventq_index=0
1295 freq=25000
1296 parent=system.realview.realview_io
1297 position=0
1298 site=1
1299 voltage_domain=system.voltage_domain
1300
1301 [system.realview.dcc.osc_hsbm]
1302 type=RealViewOsc
1303 dcc=0
1304 device=4
1305 eventq_index=0
1306 freq=25000
1307 parent=system.realview.realview_io
1308 position=0
1309 site=1
1310 voltage_domain=system.voltage_domain
1311
1312 [system.realview.dcc.osc_pxl]
1313 type=RealViewOsc
1314 dcc=0
1315 device=5
1316 eventq_index=0
1317 freq=42105
1318 parent=system.realview.realview_io
1319 position=0
1320 site=1
1321 voltage_domain=system.voltage_domain
1322
1323 [system.realview.dcc.osc_smb]
1324 type=RealViewOsc
1325 dcc=0
1326 device=6
1327 eventq_index=0
1328 freq=20000
1329 parent=system.realview.realview_io
1330 position=0
1331 site=1
1332 voltage_domain=system.voltage_domain
1333
1334 [system.realview.dcc.osc_sys]
1335 type=RealViewOsc
1336 dcc=0
1337 device=7
1338 eventq_index=0
1339 freq=16667
1340 parent=system.realview.realview_io
1341 position=0
1342 site=1
1343 voltage_domain=system.voltage_domain
1344
1345 [system.realview.energy_ctrl]
1346 type=EnergyCtrl
1347 clk_domain=system.clk_domain
1348 default_p_state=UNDEFINED
1349 dvfs_handler=system.dvfs_handler
1350 eventq_index=0
1351 p_state_clk_gate_bins=20
1352 p_state_clk_gate_max=1000000000000
1353 p_state_clk_gate_min=1000
1354 pio_addr=470286336
1355 pio_latency=100000
1356 power_model=Null
1357 system=system
1358 pio=system.iobus.master[22]
1359
1360 [system.realview.ethernet]
1361 type=IGbE
1362 BAR0=0
1363 BAR0LegacyIO=false
1364 BAR0Size=131072
1365 BAR1=0
1366 BAR1LegacyIO=false
1367 BAR1Size=0
1368 BAR2=0
1369 BAR2LegacyIO=false
1370 BAR2Size=0
1371 BAR3=0
1372 BAR3LegacyIO=false
1373 BAR3Size=0
1374 BAR4=0
1375 BAR4LegacyIO=false
1376 BAR4Size=0
1377 BAR5=0
1378 BAR5LegacyIO=false
1379 BAR5Size=0
1380 BIST=0
1381 CacheLineSize=0
1382 CapabilityPtr=0
1383 CardbusCIS=0
1384 ClassCode=2
1385 Command=0
1386 DeviceID=4213
1387 ExpansionROM=0
1388 HeaderType=0
1389 InterruptLine=1
1390 InterruptPin=1
1391 LatencyTimer=0
1392 LegacyIOBase=0
1393 MSICAPBaseOffset=0
1394 MSICAPCapId=0
1395 MSICAPMaskBits=0
1396 MSICAPMsgAddr=0
1397 MSICAPMsgCtrl=0
1398 MSICAPMsgData=0
1399 MSICAPMsgUpperAddr=0
1400 MSICAPNextCapability=0
1401 MSICAPPendingBits=0
1402 MSIXCAPBaseOffset=0
1403 MSIXCAPCapId=0
1404 MSIXCAPNextCapability=0
1405 MSIXMsgCtrl=0
1406 MSIXPbaOffset=0
1407 MSIXTableOffset=0
1408 MaximumLatency=0
1409 MinimumGrant=255
1410 PMCAPBaseOffset=0
1411 PMCAPCapId=0
1412 PMCAPCapabilities=0
1413 PMCAPCtrlStatus=0
1414 PMCAPNextCapability=0
1415 PXCAPBaseOffset=0
1416 PXCAPCapId=0
1417 PXCAPCapabilities=0
1418 PXCAPDevCap2=0
1419 PXCAPDevCapabilities=0
1420 PXCAPDevCtrl=0
1421 PXCAPDevCtrl2=0
1422 PXCAPDevStatus=0
1423 PXCAPLinkCap=0
1424 PXCAPLinkCtrl=0
1425 PXCAPLinkStatus=0
1426 PXCAPNextCapability=0
1427 ProgIF=0
1428 Revision=0
1429 Status=0
1430 SubClassCode=0
1431 SubsystemID=4104
1432 SubsystemVendorID=32902
1433 VendorID=32902
1434 clk_domain=system.clk_domain
1435 config_latency=20000
1436 default_p_state=UNDEFINED
1437 eventq_index=0
1438 fetch_comp_delay=10000
1439 fetch_delay=10000
1440 hardware_address=00:90:00:00:00:01
1441 host=system.realview.pci_host
1442 p_state_clk_gate_bins=20
1443 p_state_clk_gate_max=1000000000000
1444 p_state_clk_gate_min=1000
1445 pci_bus=0
1446 pci_dev=0
1447 pci_func=0
1448 phy_epid=896
1449 phy_pid=680
1450 pio_latency=30000
1451 power_model=Null
1452 rx_desc_cache_size=64
1453 rx_fifo_size=393216
1454 rx_write_delay=0
1455 system=system
1456 tx_desc_cache_size=64
1457 tx_fifo_size=393216
1458 tx_read_delay=0
1459 wb_comp_delay=10000
1460 wb_delay=10000
1461 dma=system.iobus.slave[4]
1462 pio=system.iobus.master[24]
1463
1464 [system.realview.generic_timer]
1465 type=GenericTimer
1466 eventq_index=0
1467 gic=system.realview.gic
1468 int_phys=29
1469 int_virt=27
1470 system=system
1471
1472 [system.realview.gic]
1473 type=Pl390
1474 clk_domain=system.clk_domain
1475 cpu_addr=738205696
1476 cpu_pio_delay=10000
1477 default_p_state=UNDEFINED
1478 dist_addr=738201600
1479 dist_pio_delay=10000
1480 eventq_index=0
1481 gem5_extensions=false
1482 int_latency=10000
1483 it_lines=128
1484 p_state_clk_gate_bins=20
1485 p_state_clk_gate_max=1000000000000
1486 p_state_clk_gate_min=1000
1487 platform=system.realview
1488 power_model=Null
1489 system=system
1490 pio=system.membus.master[2]
1491
1492 [system.realview.hdlcd]
1493 type=HDLcd
1494 amba_id=1314816
1495 clk_domain=system.clk_domain
1496 default_p_state=UNDEFINED
1497 enable_capture=true
1498 eventq_index=0
1499 gic=system.realview.gic
1500 int_num=117
1501 p_state_clk_gate_bins=20
1502 p_state_clk_gate_max=1000000000000
1503 p_state_clk_gate_min=1000
1504 pio_addr=721420288
1505 pio_latency=10000
1506 pixel_buffer_size=2048
1507 pixel_chunk=32
1508 power_model=Null
1509 pxl_clk=system.realview.dcc.osc_pxl
1510 system=system
1511 vnc=system.vncserver
1512 workaround_dma_line_count=true
1513 workaround_swap_rb=true
1514 dma=system.membus.slave[0]
1515 pio=system.iobus.master[6]
1516
1517 [system.realview.ide]
1518 type=IdeController
1519 BAR0=1
1520 BAR0LegacyIO=false
1521 BAR0Size=8
1522 BAR1=1
1523 BAR1LegacyIO=false
1524 BAR1Size=4
1525 BAR2=1
1526 BAR2LegacyIO=false
1527 BAR2Size=8
1528 BAR3=1
1529 BAR3LegacyIO=false
1530 BAR3Size=4
1531 BAR4=1
1532 BAR4LegacyIO=false
1533 BAR4Size=16
1534 BAR5=1
1535 BAR5LegacyIO=false
1536 BAR5Size=0
1537 BIST=0
1538 CacheLineSize=0
1539 CapabilityPtr=0
1540 CardbusCIS=0
1541 ClassCode=1
1542 Command=0
1543 DeviceID=28945
1544 ExpansionROM=0
1545 HeaderType=0
1546 InterruptLine=2
1547 InterruptPin=2
1548 LatencyTimer=0
1549 LegacyIOBase=0
1550 MSICAPBaseOffset=0
1551 MSICAPCapId=0
1552 MSICAPMaskBits=0
1553 MSICAPMsgAddr=0
1554 MSICAPMsgCtrl=0
1555 MSICAPMsgData=0
1556 MSICAPMsgUpperAddr=0
1557 MSICAPNextCapability=0
1558 MSICAPPendingBits=0
1559 MSIXCAPBaseOffset=0
1560 MSIXCAPCapId=0
1561 MSIXCAPNextCapability=0
1562 MSIXMsgCtrl=0
1563 MSIXPbaOffset=0
1564 MSIXTableOffset=0
1565 MaximumLatency=0
1566 MinimumGrant=0
1567 PMCAPBaseOffset=0
1568 PMCAPCapId=0
1569 PMCAPCapabilities=0
1570 PMCAPCtrlStatus=0
1571 PMCAPNextCapability=0
1572 PXCAPBaseOffset=0
1573 PXCAPCapId=0
1574 PXCAPCapabilities=0
1575 PXCAPDevCap2=0
1576 PXCAPDevCapabilities=0
1577 PXCAPDevCtrl=0
1578 PXCAPDevCtrl2=0
1579 PXCAPDevStatus=0
1580 PXCAPLinkCap=0
1581 PXCAPLinkCtrl=0
1582 PXCAPLinkStatus=0
1583 PXCAPNextCapability=0
1584 ProgIF=133
1585 Revision=0
1586 Status=640
1587 SubClassCode=1
1588 SubsystemID=0
1589 SubsystemVendorID=0
1590 VendorID=32902
1591 clk_domain=system.clk_domain
1592 config_latency=20000
1593 ctrl_offset=0
1594 default_p_state=UNDEFINED
1595 disks=system.cf0
1596 eventq_index=0
1597 host=system.realview.pci_host
1598 io_shift=0
1599 p_state_clk_gate_bins=20
1600 p_state_clk_gate_max=1000000000000
1601 p_state_clk_gate_min=1000
1602 pci_bus=0
1603 pci_dev=1
1604 pci_func=0
1605 pio_latency=30000
1606 power_model=Null
1607 system=system
1608 dma=system.iobus.slave[3]
1609 pio=system.iobus.master[23]
1610
1611 [system.realview.kmi0]
1612 type=Pl050
1613 amba_id=1314896
1614 clk_domain=system.clk_domain
1615 default_p_state=UNDEFINED
1616 eventq_index=0
1617 gic=system.realview.gic
1618 int_delay=1000000
1619 int_num=44
1620 is_mouse=false
1621 p_state_clk_gate_bins=20
1622 p_state_clk_gate_max=1000000000000
1623 p_state_clk_gate_min=1000
1624 pio_addr=470155264
1625 pio_latency=100000
1626 power_model=Null
1627 system=system
1628 vnc=system.vncserver
1629 pio=system.iobus.master[7]
1630
1631 [system.realview.kmi1]
1632 type=Pl050
1633 amba_id=1314896
1634 clk_domain=system.clk_domain
1635 default_p_state=UNDEFINED
1636 eventq_index=0
1637 gic=system.realview.gic
1638 int_delay=1000000
1639 int_num=45
1640 is_mouse=true
1641 p_state_clk_gate_bins=20
1642 p_state_clk_gate_max=1000000000000
1643 p_state_clk_gate_min=1000
1644 pio_addr=470220800
1645 pio_latency=100000
1646 power_model=Null
1647 system=system
1648 vnc=system.vncserver
1649 pio=system.iobus.master[8]
1650
1651 [system.realview.l2x0_fake]
1652 type=IsaFake
1653 clk_domain=system.clk_domain
1654 default_p_state=UNDEFINED
1655 eventq_index=0
1656 fake_mem=false
1657 p_state_clk_gate_bins=20
1658 p_state_clk_gate_max=1000000000000
1659 p_state_clk_gate_min=1000
1660 pio_addr=739246080
1661 pio_latency=100000
1662 pio_size=4095
1663 power_model=Null
1664 ret_bad_addr=false
1665 ret_data16=65535
1666 ret_data32=4294967295
1667 ret_data64=18446744073709551615
1668 ret_data8=255
1669 system=system
1670 update_data=false
1671 warn_access=
1672 pio=system.iobus.master[12]
1673
1674 [system.realview.lan_fake]
1675 type=IsaFake
1676 clk_domain=system.clk_domain
1677 default_p_state=UNDEFINED
1678 eventq_index=0
1679 fake_mem=false
1680 p_state_clk_gate_bins=20
1681 p_state_clk_gate_max=1000000000000
1682 p_state_clk_gate_min=1000
1683 pio_addr=436207616
1684 pio_latency=100000
1685 pio_size=65535
1686 power_model=Null
1687 ret_bad_addr=false
1688 ret_data16=65535
1689 ret_data32=4294967295
1690 ret_data64=18446744073709551615
1691 ret_data8=255
1692 system=system
1693 update_data=false
1694 warn_access=
1695 pio=system.iobus.master[19]
1696
1697 [system.realview.local_cpu_timer]
1698 type=CpuLocalTimer
1699 clk_domain=system.clk_domain
1700 default_p_state=UNDEFINED
1701 eventq_index=0
1702 gic=system.realview.gic
1703 int_num_timer=29
1704 int_num_watchdog=30
1705 p_state_clk_gate_bins=20
1706 p_state_clk_gate_max=1000000000000
1707 p_state_clk_gate_min=1000
1708 pio_addr=738721792
1709 pio_latency=100000
1710 power_model=Null
1711 system=system
1712 pio=system.membus.master[4]
1713
1714 [system.realview.mcc]
1715 type=SubSystem
1716 children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
1717 eventq_index=0
1718 thermal_domain=Null
1719
1720 [system.realview.mcc.osc_clcd]
1721 type=RealViewOsc
1722 dcc=0
1723 device=1
1724 eventq_index=0
1725 freq=42105
1726 parent=system.realview.realview_io
1727 position=0
1728 site=0
1729 voltage_domain=system.voltage_domain
1730
1731 [system.realview.mcc.osc_mcc]
1732 type=RealViewOsc
1733 dcc=0
1734 device=0
1735 eventq_index=0
1736 freq=20000
1737 parent=system.realview.realview_io
1738 position=0
1739 site=0
1740 voltage_domain=system.voltage_domain
1741
1742 [system.realview.mcc.osc_peripheral]
1743 type=RealViewOsc
1744 dcc=0
1745 device=2
1746 eventq_index=0
1747 freq=41667
1748 parent=system.realview.realview_io
1749 position=0
1750 site=0
1751 voltage_domain=system.voltage_domain
1752
1753 [system.realview.mcc.osc_system_bus]
1754 type=RealViewOsc
1755 dcc=0
1756 device=4
1757 eventq_index=0
1758 freq=41667
1759 parent=system.realview.realview_io
1760 position=0
1761 site=0
1762 voltage_domain=system.voltage_domain
1763
1764 [system.realview.mcc.temp_crtl]
1765 type=RealViewTemperatureSensor
1766 dcc=0
1767 device=0
1768 eventq_index=0
1769 parent=system.realview.realview_io
1770 position=0
1771 site=0
1772 system=system
1773
1774 [system.realview.mmc_fake]
1775 type=AmbaFake
1776 amba_id=0
1777 clk_domain=system.clk_domain
1778 default_p_state=UNDEFINED
1779 eventq_index=0
1780 ignore_access=false
1781 p_state_clk_gate_bins=20
1782 p_state_clk_gate_max=1000000000000
1783 p_state_clk_gate_min=1000
1784 pio_addr=470089728
1785 pio_latency=100000
1786 power_model=Null
1787 system=system
1788 pio=system.iobus.master[21]
1789
1790 [system.realview.nvmem]
1791 type=SimpleMemory
1792 bandwidth=73.000000
1793 clk_domain=system.clk_domain
1794 conf_table_reported=false
1795 default_p_state=UNDEFINED
1796 eventq_index=0
1797 in_addr_map=true
1798 kvm_map=true
1799 latency=30000
1800 latency_var=0
1801 null=false
1802 p_state_clk_gate_bins=20
1803 p_state_clk_gate_max=1000000000000
1804 p_state_clk_gate_min=1000
1805 power_model=Null
1806 range=0:67108863:0:0:0:0
1807 port=system.membus.master[1]
1808
1809 [system.realview.pci_host]
1810 type=GenericPciHost
1811 clk_domain=system.clk_domain
1812 conf_base=805306368
1813 conf_device_bits=12
1814 conf_size=268435456
1815 default_p_state=UNDEFINED
1816 eventq_index=0
1817 p_state_clk_gate_bins=20
1818 p_state_clk_gate_max=1000000000000
1819 p_state_clk_gate_min=1000
1820 pci_dma_base=0
1821 pci_mem_base=0
1822 pci_pio_base=788529152
1823 platform=system.realview
1824 power_model=Null
1825 system=system
1826 pio=system.iobus.master[2]
1827
1828 [system.realview.realview_io]
1829 type=RealViewCtrl
1830 clk_domain=system.clk_domain
1831 default_p_state=UNDEFINED
1832 eventq_index=0
1833 idreg=35979264
1834 p_state_clk_gate_bins=20
1835 p_state_clk_gate_max=1000000000000
1836 p_state_clk_gate_min=1000
1837 pio_addr=469827584
1838 pio_latency=100000
1839 power_model=Null
1840 proc_id0=335544320
1841 proc_id1=335544320
1842 system=system
1843 pio=system.iobus.master[1]
1844
1845 [system.realview.rtc]
1846 type=PL031
1847 amba_id=3412017
1848 clk_domain=system.clk_domain
1849 default_p_state=UNDEFINED
1850 eventq_index=0
1851 gic=system.realview.gic
1852 int_delay=100000
1853 int_num=36
1854 p_state_clk_gate_bins=20
1855 p_state_clk_gate_max=1000000000000
1856 p_state_clk_gate_min=1000
1857 pio_addr=471269376
1858 pio_latency=100000
1859 power_model=Null
1860 system=system
1861 time=Thu Jan  1 00:00:00 2009
1862 pio=system.iobus.master[10]
1863
1864 [system.realview.sp810_fake]
1865 type=AmbaFake
1866 amba_id=0
1867 clk_domain=system.clk_domain
1868 default_p_state=UNDEFINED
1869 eventq_index=0
1870 ignore_access=true
1871 p_state_clk_gate_bins=20
1872 p_state_clk_gate_max=1000000000000
1873 p_state_clk_gate_min=1000
1874 pio_addr=469893120
1875 pio_latency=100000
1876 power_model=Null
1877 system=system
1878 pio=system.iobus.master[16]
1879
1880 [system.realview.timer0]
1881 type=Sp804
1882 amba_id=1316868
1883 clk_domain=system.clk_domain
1884 clock0=1000000
1885 clock1=1000000
1886 default_p_state=UNDEFINED
1887 eventq_index=0
1888 gic=system.realview.gic
1889 int_num0=34
1890 int_num1=34
1891 p_state_clk_gate_bins=20
1892 p_state_clk_gate_max=1000000000000
1893 p_state_clk_gate_min=1000
1894 pio_addr=470876160
1895 pio_latency=100000
1896 power_model=Null
1897 system=system
1898 pio=system.iobus.master[3]
1899
1900 [system.realview.timer1]
1901 type=Sp804
1902 amba_id=1316868
1903 clk_domain=system.clk_domain
1904 clock0=1000000
1905 clock1=1000000
1906 default_p_state=UNDEFINED
1907 eventq_index=0
1908 gic=system.realview.gic
1909 int_num0=35
1910 int_num1=35
1911 p_state_clk_gate_bins=20
1912 p_state_clk_gate_max=1000000000000
1913 p_state_clk_gate_min=1000
1914 pio_addr=470941696
1915 pio_latency=100000
1916 power_model=Null
1917 system=system
1918 pio=system.iobus.master[4]
1919
1920 [system.realview.uart]
1921 type=Pl011
1922 clk_domain=system.clk_domain
1923 default_p_state=UNDEFINED
1924 end_on_eot=false
1925 eventq_index=0
1926 gic=system.realview.gic
1927 int_delay=100000
1928 int_num=37
1929 p_state_clk_gate_bins=20
1930 p_state_clk_gate_max=1000000000000
1931 p_state_clk_gate_min=1000
1932 pio_addr=470351872
1933 pio_latency=100000
1934 platform=system.realview
1935 power_model=Null
1936 system=system
1937 terminal=system.terminal
1938 pio=system.iobus.master[0]
1939
1940 [system.realview.uart1_fake]
1941 type=AmbaFake
1942 amba_id=0
1943 clk_domain=system.clk_domain
1944 default_p_state=UNDEFINED
1945 eventq_index=0
1946 ignore_access=false
1947 p_state_clk_gate_bins=20
1948 p_state_clk_gate_max=1000000000000
1949 p_state_clk_gate_min=1000
1950 pio_addr=470417408
1951 pio_latency=100000
1952 power_model=Null
1953 system=system
1954 pio=system.iobus.master[13]
1955
1956 [system.realview.uart2_fake]
1957 type=AmbaFake
1958 amba_id=0
1959 clk_domain=system.clk_domain
1960 default_p_state=UNDEFINED
1961 eventq_index=0
1962 ignore_access=false
1963 p_state_clk_gate_bins=20
1964 p_state_clk_gate_max=1000000000000
1965 p_state_clk_gate_min=1000
1966 pio_addr=470482944
1967 pio_latency=100000
1968 power_model=Null
1969 system=system
1970 pio=system.iobus.master[14]
1971
1972 [system.realview.uart3_fake]
1973 type=AmbaFake
1974 amba_id=0
1975 clk_domain=system.clk_domain
1976 default_p_state=UNDEFINED
1977 eventq_index=0
1978 ignore_access=false
1979 p_state_clk_gate_bins=20
1980 p_state_clk_gate_max=1000000000000
1981 p_state_clk_gate_min=1000
1982 pio_addr=470548480
1983 pio_latency=100000
1984 power_model=Null
1985 system=system
1986 pio=system.iobus.master[15]
1987
1988 [system.realview.usb_fake]
1989 type=IsaFake
1990 clk_domain=system.clk_domain
1991 default_p_state=UNDEFINED
1992 eventq_index=0
1993 fake_mem=false
1994 p_state_clk_gate_bins=20
1995 p_state_clk_gate_max=1000000000000
1996 p_state_clk_gate_min=1000
1997 pio_addr=452984832
1998 pio_latency=100000
1999 pio_size=131071
2000 power_model=Null
2001 ret_bad_addr=false
2002 ret_data16=65535
2003 ret_data32=4294967295
2004 ret_data64=18446744073709551615
2005 ret_data8=255
2006 system=system
2007 update_data=false
2008 warn_access=
2009 pio=system.iobus.master[20]
2010
2011 [system.realview.vgic]
2012 type=VGic
2013 clk_domain=system.clk_domain
2014 default_p_state=UNDEFINED
2015 eventq_index=0
2016 gic=system.realview.gic
2017 hv_addr=738213888
2018 p_state_clk_gate_bins=20
2019 p_state_clk_gate_max=1000000000000
2020 p_state_clk_gate_min=1000
2021 pio_delay=10000
2022 platform=system.realview
2023 power_model=Null
2024 ppint=25
2025 system=system
2026 vcpu_addr=738222080
2027 pio=system.membus.master[3]
2028
2029 [system.realview.vram]
2030 type=SimpleMemory
2031 bandwidth=73.000000
2032 clk_domain=system.clk_domain
2033 conf_table_reported=false
2034 default_p_state=UNDEFINED
2035 eventq_index=0
2036 in_addr_map=true
2037 kvm_map=true
2038 latency=30000
2039 latency_var=0
2040 null=false
2041 p_state_clk_gate_bins=20
2042 p_state_clk_gate_max=1000000000000
2043 p_state_clk_gate_min=1000
2044 power_model=Null
2045 range=402653184:436207615:0:0:0:0
2046 port=system.iobus.master[11]
2047
2048 [system.realview.watchdog_fake]
2049 type=AmbaFake
2050 amba_id=0
2051 clk_domain=system.clk_domain
2052 default_p_state=UNDEFINED
2053 eventq_index=0
2054 ignore_access=false
2055 p_state_clk_gate_bins=20
2056 p_state_clk_gate_max=1000000000000
2057 p_state_clk_gate_min=1000
2058 pio_addr=470745088
2059 pio_latency=100000
2060 power_model=Null
2061 system=system
2062 pio=system.iobus.master[17]
2063
2064 [system.terminal]
2065 type=Terminal
2066 eventq_index=0
2067 intr_control=system.intrctrl
2068 number=0
2069 output=true
2070 port=3456
2071
2072 [system.toL2Bus]
2073 type=CoherentXBar
2074 children=snoop_filter
2075 clk_domain=system.cpu_clk_domain
2076 default_p_state=UNDEFINED
2077 eventq_index=0
2078 forward_latency=0
2079 frontend_latency=1
2080 p_state_clk_gate_bins=20
2081 p_state_clk_gate_max=1000000000000
2082 p_state_clk_gate_min=1000
2083 point_of_coherency=false
2084 power_model=Null
2085 response_latency=1
2086 snoop_filter=system.toL2Bus.snoop_filter
2087 snoop_response_latency=1
2088 system=system
2089 use_default_range=false
2090 width=32
2091 master=system.l2c.cpu_side
2092 slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
2093
2094 [system.toL2Bus.snoop_filter]
2095 type=SnoopFilter
2096 eventq_index=0
2097 lookup_latency=0
2098 max_capacity=8388608
2099 system=system
2100
2101 [system.vncserver]
2102 type=VncServer
2103 eventq_index=0
2104 frame_capture=false
2105 number=0
2106 port=5900
2107
2108 [system.voltage_domain]
2109 type=VoltageDomain
2110 eventq_index=0
2111 voltage=1.000000
2112