2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 47.602568 # Number of seconds simulated
4 sim_ticks 47602567962500 # Number of ticks simulated
5 final_tick 47602567962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 603747 # Simulator instruction rate (inst/s)
8 host_op_rate 710316 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 32933076215 # Simulator tick rate (ticks/s)
10 host_mem_usage 740648 # Number of bytes of host memory used
11 host_seconds 1445.43 # Real time elapsed on the host
12 sim_insts 872675802 # Number of instructions simulated
13 sim_ops 1026715135 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 97216 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 105280 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 3176436 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 39189384 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.l2cache.prefetcher 13261312 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.dtb.walker 67968 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.itb.walker 64704 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.inst 2473528 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.data 13920528 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu1.l2cache.prefetcher 8902656 # Number of bytes read from this memory
26 system.physmem.bytes_read::realview.ide 417088 # Number of bytes read from this memory
27 system.physmem.bytes_read::total 81676100 # Number of bytes read from this memory
28 system.physmem.bytes_inst_read::cpu0.inst 3176436 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::cpu1.inst 2473528 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::total 5649964 # Number of instructions bytes read from this memory
31 system.physmem.bytes_written::writebacks 69006208 # Number of bytes written to this memory
32 system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33 system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34 system.physmem.bytes_written::total 69026792 # Number of bytes written to this memory
35 system.physmem.num_reads::cpu0.dtb.walker 1519 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.itb.walker 1645 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.inst 90039 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.data 612347 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.l2cache.prefetcher 207208 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu1.dtb.walker 1062 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.itb.walker 1011 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.inst 38737 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.data 217521 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.l2cache.prefetcher 139104 # Number of read requests responded to by this memory
45 system.physmem.num_reads::realview.ide 6517 # Number of read requests responded to by this memory
46 system.physmem.num_reads::total 1316710 # Number of read requests responded to by this memory
47 system.physmem.num_writes::writebacks 1078222 # Number of write requests responded to by this memory
48 system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49 system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50 system.physmem.num_writes::total 1080796 # Number of write requests responded to by this memory
51 system.physmem.bw_read::cpu0.dtb.walker 2042 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu0.itb.walker 2212 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.inst 66728 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.data 823262 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.l2cache.prefetcher 278584 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu1.dtb.walker 1428 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.itb.walker 1359 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.inst 51962 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.data 292432 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.l2cache.prefetcher 187020 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::realview.ide 8762 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::total 1715792 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_inst_read::cpu0.inst 66728 # Instruction read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu1.inst 51962 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::total 118690 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_write::writebacks 1449632 # Write bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::total 1450064 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_total::writebacks 1449632 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu0.dtb.walker 2042 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.itb.walker 2212 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.inst 66728 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.data 823694 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.l2cache.prefetcher 278584 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu1.dtb.walker 1428 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.inst 51962 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.data 292432 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu1.l2cache.prefetcher 187020 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::realview.ide 8762 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::total 3165856 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.readReqs 1316710 # Number of read requests accepted
84 system.physmem.writeReqs 1080796 # Number of write requests accepted
85 system.physmem.readBursts 1316710 # Number of DRAM read bursts, including those serviced by the write queue
86 system.physmem.writeBursts 1080796 # Number of DRAM write bursts, including those merged in the write queue
87 system.physmem.bytesReadDRAM 84239104 # Total number of bytes read from DRAM
88 system.physmem.bytesReadWrQ 30336 # Total number of bytes read from write queue
89 system.physmem.bytesWritten 69025088 # Total number of bytes written to DRAM
90 system.physmem.bytesReadSys 81676100 # Total read bytes from the system interface side
91 system.physmem.bytesWrittenSys 69026792 # Total written bytes from the system interface side
92 system.physmem.servicedByWrQ 474 # Number of DRAM read bursts serviced by the write queue
93 system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one
94 system.physmem.neitherReadNorWriteReqs 461546 # Number of requests that are neither read nor write
95 system.physmem.perBankRdBursts::0 74138 # Per bank write bursts
96 system.physmem.perBankRdBursts::1 82827 # Per bank write bursts
97 system.physmem.perBankRdBursts::2 74957 # Per bank write bursts
98 system.physmem.perBankRdBursts::3 82122 # Per bank write bursts
99 system.physmem.perBankRdBursts::4 83077 # Per bank write bursts
100 system.physmem.perBankRdBursts::5 87558 # Per bank write bursts
101 system.physmem.perBankRdBursts::6 81167 # Per bank write bursts
102 system.physmem.perBankRdBursts::7 84127 # Per bank write bursts
103 system.physmem.perBankRdBursts::8 76730 # Per bank write bursts
104 system.physmem.perBankRdBursts::9 122410 # Per bank write bursts
105 system.physmem.perBankRdBursts::10 70954 # Per bank write bursts
106 system.physmem.perBankRdBursts::11 80684 # Per bank write bursts
107 system.physmem.perBankRdBursts::12 75912 # Per bank write bursts
108 system.physmem.perBankRdBursts::13 81292 # Per bank write bursts
109 system.physmem.perBankRdBursts::14 78761 # Per bank write bursts
110 system.physmem.perBankRdBursts::15 79520 # Per bank write bursts
111 system.physmem.perBankWrBursts::0 61777 # Per bank write bursts
112 system.physmem.perBankWrBursts::1 69166 # Per bank write bursts
113 system.physmem.perBankWrBursts::2 64147 # Per bank write bursts
114 system.physmem.perBankWrBursts::3 68304 # Per bank write bursts
115 system.physmem.perBankWrBursts::4 69323 # Per bank write bursts
116 system.physmem.perBankWrBursts::5 73404 # Per bank write bursts
117 system.physmem.perBankWrBursts::6 67894 # Per bank write bursts
118 system.physmem.perBankWrBursts::7 70420 # Per bank write bursts
119 system.physmem.perBankWrBursts::8 65275 # Per bank write bursts
120 system.physmem.perBankWrBursts::9 69986 # Per bank write bursts
121 system.physmem.perBankWrBursts::10 62072 # Per bank write bursts
122 system.physmem.perBankWrBursts::11 68038 # Per bank write bursts
123 system.physmem.perBankWrBursts::12 64002 # Per bank write bursts
124 system.physmem.perBankWrBursts::13 68951 # Per bank write bursts
125 system.physmem.perBankWrBursts::14 67347 # Per bank write bursts
126 system.physmem.perBankWrBursts::15 68411 # Per bank write bursts
127 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128 system.physmem.numWrRetry 25 # Number of times write queue was full causing retry
129 system.physmem.totGap 47602564597000 # Total gap between requests
130 system.physmem.readPktSize::0 0 # Read request sizes (log2)
131 system.physmem.readPktSize::1 0 # Read request sizes (log2)
132 system.physmem.readPktSize::2 43195 # Read request sizes (log2)
133 system.physmem.readPktSize::3 25 # Read request sizes (log2)
134 system.physmem.readPktSize::4 5 # Read request sizes (log2)
135 system.physmem.readPktSize::5 0 # Read request sizes (log2)
136 system.physmem.readPktSize::6 1273485 # Read request sizes (log2)
137 system.physmem.writePktSize::0 0 # Write request sizes (log2)
138 system.physmem.writePktSize::1 0 # Write request sizes (log2)
139 system.physmem.writePktSize::2 2 # Write request sizes (log2)
140 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141 system.physmem.writePktSize::4 0 # Write request sizes (log2)
142 system.physmem.writePktSize::5 0 # Write request sizes (log2)
143 system.physmem.writePktSize::6 1078222 # Write request sizes (log2)
144 system.physmem.rdQLenPdf::0 1098528 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::1 69154 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::2 30759 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::3 26336 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::4 22457 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::5 19787 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::6 17170 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::7 15034 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::8 11894 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::9 1995 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::10 874 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::11 575 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::13 323 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::14 240 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::15 218 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::17 144 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
176 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::15 18244 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::16 20496 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::17 46518 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::18 53470 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::19 57648 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::20 60710 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::21 64016 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::22 65226 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::23 67393 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::24 67733 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::25 70106 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::26 73801 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::27 68996 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::28 68981 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::29 71721 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::30 66784 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::31 63773 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::32 62218 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::33 1690 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::34 1098 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::35 827 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::36 666 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::37 614 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::38 508 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::39 438 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::40 398 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::41 362 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::42 382 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::43 307 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::45 298 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::46 278 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::52 138 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::53 165 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::58 78 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see
240 system.physmem.bytesPerActivate::samples 845861 # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::mean 181.192513 # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::gmean 111.718720 # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::stdev 240.356894 # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::0-127 524023 61.95% 61.95% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::128-255 157589 18.63% 80.58% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::256-383 52244 6.18% 86.76% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::384-511 27763 3.28% 90.04% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::512-639 18582 2.20% 92.24% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::640-767 11693 1.38% 93.62% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::768-895 8942 1.06% 94.68% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::896-1023 9176 1.08% 95.76% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::1024-1151 35849 4.24% 100.00% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::total 845861 # Bytes accessed per row activation
254 system.physmem.rdPerTurnAround::samples 60416 # Reads before turning the bus around for writes
255 system.physmem.rdPerTurnAround::mean 21.786182 # Reads before turning the bus around for writes
256 system.physmem.rdPerTurnAround::stdev 329.918437 # Reads before turning the bus around for writes
257 system.physmem.rdPerTurnAround::0-4095 60413 100.00% 100.00% # Reads before turning the bus around for writes
258 system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259 system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes
261 system.physmem.rdPerTurnAround::total 60416 # Reads before turning the bus around for writes
262 system.physmem.wrPerTurnAround::samples 60416 # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::mean 17.851513 # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::gmean 17.268088 # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::stdev 7.277078 # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::16-19 56734 93.91% 93.91% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::20-23 1553 2.57% 96.48% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::24-27 255 0.42% 96.90% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::28-31 285 0.47% 97.37% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::32-35 70 0.12% 97.49% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::36-39 285 0.47% 97.96% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::40-43 159 0.26% 98.22% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::44-47 94 0.16% 98.38% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::48-51 78 0.13% 98.51% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::52-55 106 0.18% 98.68% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::56-59 41 0.07% 98.75% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::60-63 61 0.10% 98.85% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::64-67 428 0.71% 99.56% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::68-71 38 0.06% 99.62% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::72-75 49 0.08% 99.70% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::76-79 117 0.19% 99.90% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::80-83 11 0.02% 99.91% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::156-159 5 0.01% 100.00% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::total 60416 # Writes before turning the bus around for reads
299 system.physmem.totQLat 28673044871 # Total ticks spent queuing
300 system.physmem.totMemAccLat 53352469871 # Total ticks spent from burst creation until serviced by the DRAM
301 system.physmem.totBusLat 6581180000 # Total ticks spent in databus transfers
302 system.physmem.avgQLat 21784.12 # Average queueing delay per DRAM burst
303 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
304 system.physmem.avgMemAccLat 40534.12 # Average memory access latency per DRAM burst
305 system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s
306 system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s
307 system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s
308 system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s
309 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
310 system.physmem.busUtil 0.03 # Data bus utilization in percentage
311 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
312 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
313 system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
314 system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing
315 system.physmem.readRowHits 1054044 # Number of row buffer hits during reads
316 system.physmem.writeRowHits 494841 # Number of row buffer hits during writes
317 system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads
318 system.physmem.writeRowHitRate 45.88 # Row buffer hit rate for writes
319 system.physmem.avgGap 19855034.61 # Average gap between requests
320 system.physmem.pageHitRate 64.68 # Row buffer hit rate, read and write combined
321 system.physmem_0.actEnergy 3265088400 # Energy for activate commands per rank (pJ)
322 system.physmem_0.preEnergy 1781546250 # Energy for precharge commands per rank (pJ)
323 system.physmem_0.readEnergy 5069789400 # Energy for read commands per rank (pJ)
324 system.physmem_0.writeEnergy 3527867520 # Energy for write commands per rank (pJ)
325 system.physmem_0.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ)
326 system.physmem_0.actBackEnergy 1219382745750 # Energy for active background per rank (pJ)
327 system.physmem_0.preBackEnergy 27491903982750 # Energy for precharge background per rank (pJ)
328 system.physmem_0.totalEnergy 31834099035270 # Total energy per rank (pJ)
329 system.physmem_0.averagePower 668.747581 # Core power per rank (mW)
330 system.physmem_0.memoryStateTime::IDLE 45734675361714 # Time in different power states
331 system.physmem_0.memoryStateTime::REF 1589554200000 # Time in different power states
332 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
333 system.physmem_0.memoryStateTime::ACT 278338023286 # Time in different power states
334 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
335 system.physmem_1.actEnergy 3129537600 # Energy for activate commands per rank (pJ)
336 system.physmem_1.preEnergy 1707585000 # Energy for precharge commands per rank (pJ)
337 system.physmem_1.readEnergy 5196804600 # Energy for read commands per rank (pJ)
338 system.physmem_1.writeEnergy 3460818960 # Energy for write commands per rank (pJ)
339 system.physmem_1.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ)
340 system.physmem_1.actBackEnergy 1215349697925 # Energy for active background per rank (pJ)
341 system.physmem_1.preBackEnergy 27495441752250 # Energy for precharge background per rank (pJ)
342 system.physmem_1.totalEnergy 31833454211535 # Total energy per rank (pJ)
343 system.physmem_1.averagePower 668.734035 # Core power per rank (mW)
344 system.physmem_1.memoryStateTime::IDLE 45740562014248 # Time in different power states
345 system.physmem_1.memoryStateTime::REF 1589554200000 # Time in different power states
346 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
347 system.physmem_1.memoryStateTime::ACT 272450963752 # Time in different power states
348 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
349 system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
350 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
351 system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
352 system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
353 system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
354 system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
355 system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
356 system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
357 system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
358 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
359 system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
360 system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
361 system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
362 system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
363 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
364 system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
365 system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
366 system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
367 system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
368 system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
369 system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
370 system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
371 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
372 system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
373 system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
374 system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
375 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
376 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
377 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
378 system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
379 system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
380 system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
381 system.cpu_clk_domain.clock 500 # Clock period in ticks
382 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
383 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
384 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
385 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
386 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
387 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
388 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
389 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
390 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
391 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
392 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
393 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
394 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
395 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
396 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
397 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
398 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
399 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
400 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
401 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
402 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
403 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
404 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
405 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
406 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
407 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
408 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
409 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
410 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
411 system.cpu0.dtb.walker.walks 111926 # Table walker walks requested
412 system.cpu0.dtb.walker.walksLong 111926 # Table walker walks initiated with long descriptors
413 system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10169 # Level at which table walker walks with long descriptors terminate
414 system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86471 # Level at which table walker walks with long descriptors terminate
415 system.cpu0.dtb.walker.walksSquashedBefore 18 # Table walks squashed before starting
416 system.cpu0.dtb.walker.walkWaitTime::samples 111908 # Table walker wait (enqueue to first request) latency
417 system.cpu0.dtb.walker.walkWaitTime::mean 0.232334 # Table walker wait (enqueue to first request) latency
418 system.cpu0.dtb.walker.walkWaitTime::stdev 77.721788 # Table walker wait (enqueue to first request) latency
419 system.cpu0.dtb.walker.walkWaitTime::0-2047 111907 100.00% 100.00% # Table walker wait (enqueue to first request) latency
420 system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
421 system.cpu0.dtb.walker.walkWaitTime::total 111908 # Table walker wait (enqueue to first request) latency
422 system.cpu0.dtb.walker.walkCompletionTime::samples 96658 # Table walker service (enqueue to completion) latency
423 system.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374 # Table walker service (enqueue to completion) latency
424 system.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589 # Table walker service (enqueue to completion) latency
425 system.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790 # Table walker service (enqueue to completion) latency
426 system.cpu0.dtb.walker.walkCompletionTime::0-65535 95612 98.92% 98.92% # Table walker service (enqueue to completion) latency
427 system.cpu0.dtb.walker.walkCompletionTime::65536-131071 152 0.16% 99.08% # Table walker service (enqueue to completion) latency
428 system.cpu0.dtb.walker.walkCompletionTime::131072-196607 763 0.79% 99.86% # Table walker service (enqueue to completion) latency
429 system.cpu0.dtb.walker.walkCompletionTime::196608-262143 18 0.02% 99.88% # Table walker service (enqueue to completion) latency
430 system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.92% # Table walker service (enqueue to completion) latency
431 system.cpu0.dtb.walker.walkCompletionTime::327680-393215 23 0.02% 99.95% # Table walker service (enqueue to completion) latency
432 system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency
433 system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
434 system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
435 system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
436 system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
437 system.cpu0.dtb.walker.walkCompletionTime::total 96658 # Table walker service (enqueue to completion) latency
438 system.cpu0.dtb.walker.walksPending::samples 444719432 # Table walker pending requests distribution
439 system.cpu0.dtb.walker.walksPending::mean -3.785405 # Table walker pending requests distribution
440 system.cpu0.dtb.walker.walksPending::0 2128162704 478.54% 478.54% # Table walker pending requests distribution
441 system.cpu0.dtb.walker.walksPending::1 -1683443272 -378.54% 100.00% # Table walker pending requests distribution
442 system.cpu0.dtb.walker.walksPending::total 444719432 # Table walker pending requests distribution
443 system.cpu0.dtb.walker.walkPageSizes::4K 86471 89.48% 89.48% # Table walker page sizes translated
444 system.cpu0.dtb.walker.walkPageSizes::2M 10169 10.52% 100.00% # Table walker page sizes translated
445 system.cpu0.dtb.walker.walkPageSizes::total 96640 # Table walker page sizes translated
446 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111926 # Table walker requests started/completed, data/inst
447 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
448 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111926 # Table walker requests started/completed, data/inst
449 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96640 # Table walker requests started/completed, data/inst
450 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
451 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96640 # Table walker requests started/completed, data/inst
452 system.cpu0.dtb.walker.walkRequestOrigin::total 208566 # Table walker requests started/completed, data/inst
453 system.cpu0.dtb.inst_hits 0 # ITB inst hits
454 system.cpu0.dtb.inst_misses 0 # ITB inst misses
455 system.cpu0.dtb.read_hits 87929647 # DTB read hits
456 system.cpu0.dtb.read_misses 85158 # DTB read misses
457 system.cpu0.dtb.write_hits 79744109 # DTB write hits
458 system.cpu0.dtb.write_misses 26768 # DTB write misses
459 system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
460 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
461 system.cpu0.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID
462 system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
463 system.cpu0.dtb.flush_entries 37859 # Number of entries that have been flushed from TLB
464 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
465 system.cpu0.dtb.prefetch_faults 3884 # Number of TLB faults due to prefetch
466 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
467 system.cpu0.dtb.perms_faults 10087 # Number of TLB faults due to permissions restrictions
468 system.cpu0.dtb.read_accesses 88014805 # DTB read accesses
469 system.cpu0.dtb.write_accesses 79770877 # DTB write accesses
470 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
471 system.cpu0.dtb.hits 167673756 # DTB hits
472 system.cpu0.dtb.misses 111926 # DTB misses
473 system.cpu0.dtb.accesses 167785682 # DTB accesses
474 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
475 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
476 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
477 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
478 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
479 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
480 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
481 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
482 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
483 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
484 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
485 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
486 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
487 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
488 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
489 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
490 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
491 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
492 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
493 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
494 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
495 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
496 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
497 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
498 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
499 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
500 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
501 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
502 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
503 system.cpu0.itb.walker.walks 61252 # Table walker walks requested
504 system.cpu0.itb.walker.walksLong 61252 # Table walker walks initiated with long descriptors
505 system.cpu0.itb.walker.walksLongTerminationLevel::Level2 842 # Level at which table walker walks with long descriptors terminate
506 system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54849 # Level at which table walker walks with long descriptors terminate
507 system.cpu0.itb.walker.walkWaitTime::samples 61252 # Table walker wait (enqueue to first request) latency
508 system.cpu0.itb.walker.walkWaitTime::0 61252 100.00% 100.00% # Table walker wait (enqueue to first request) latency
509 system.cpu0.itb.walker.walkWaitTime::total 61252 # Table walker wait (enqueue to first request) latency
510 system.cpu0.itb.walker.walkCompletionTime::samples 55691 # Table walker service (enqueue to completion) latency
511 system.cpu0.itb.walker.walkCompletionTime::mean 26308.021045 # Table walker service (enqueue to completion) latency
512 system.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275 # Table walker service (enqueue to completion) latency
513 system.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100 # Table walker service (enqueue to completion) latency
514 system.cpu0.itb.walker.walkCompletionTime::0-65535 54619 98.08% 98.08% # Table walker service (enqueue to completion) latency
515 system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.08% 98.15% # Table walker service (enqueue to completion) latency
516 system.cpu0.itb.walker.walkCompletionTime::131072-196607 884 1.59% 99.74% # Table walker service (enqueue to completion) latency
517 system.cpu0.itb.walker.walkCompletionTime::196608-262143 24 0.04% 99.78% # Table walker service (enqueue to completion) latency
518 system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.09% 99.87% # Table walker service (enqueue to completion) latency
519 system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.90% # Table walker service (enqueue to completion) latency
520 system.cpu0.itb.walker.walkCompletionTime::393216-458751 35 0.06% 99.96% # Table walker service (enqueue to completion) latency
521 system.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
522 system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
523 system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
524 system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
525 system.cpu0.itb.walker.walkCompletionTime::total 55691 # Table walker service (enqueue to completion) latency
526 system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution
527 system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution
528 system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution
529 system.cpu0.itb.walker.walkPageSizes::4K 54849 98.49% 98.49% # Table walker page sizes translated
530 system.cpu0.itb.walker.walkPageSizes::2M 842 1.51% 100.00% # Table walker page sizes translated
531 system.cpu0.itb.walker.walkPageSizes::total 55691 # Table walker page sizes translated
532 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
533 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61252 # Table walker requests started/completed, data/inst
534 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61252 # Table walker requests started/completed, data/inst
535 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
536 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55691 # Table walker requests started/completed, data/inst
537 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55691 # Table walker requests started/completed, data/inst
538 system.cpu0.itb.walker.walkRequestOrigin::total 116943 # Table walker requests started/completed, data/inst
539 system.cpu0.itb.inst_hits 467202921 # ITB inst hits
540 system.cpu0.itb.inst_misses 61252 # ITB inst misses
541 system.cpu0.itb.read_hits 0 # DTB read hits
542 system.cpu0.itb.read_misses 0 # DTB read misses
543 system.cpu0.itb.write_hits 0 # DTB write hits
544 system.cpu0.itb.write_misses 0 # DTB write misses
545 system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
546 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
547 system.cpu0.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID
548 system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
549 system.cpu0.itb.flush_entries 27100 # Number of entries that have been flushed from TLB
550 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
551 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
552 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
553 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
554 system.cpu0.itb.read_accesses 0 # DTB read accesses
555 system.cpu0.itb.write_accesses 0 # DTB write accesses
556 system.cpu0.itb.inst_accesses 467264173 # ITB inst accesses
557 system.cpu0.itb.hits 467202921 # DTB hits
558 system.cpu0.itb.misses 61252 # DTB misses
559 system.cpu0.itb.accesses 467264173 # DTB accesses
560 system.cpu0.numCycles 95205135902 # number of cpu cycles simulated
561 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
562 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
563 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
564 system.cpu0.kern.inst.quiesce 5123 # number of quiesce instructions executed
565 system.cpu0.committedInsts 466948479 # Number of instructions committed
566 system.cpu0.committedOps 548389991 # Number of ops (including micro ops) committed
567 system.cpu0.num_int_alu_accesses 504092161 # Number of integer alu accesses
568 system.cpu0.num_fp_alu_accesses 464416 # Number of float alu accesses
569 system.cpu0.num_func_calls 27983491 # number of times a function call or return occured
570 system.cpu0.num_conditional_control_insts 70438282 # number of instructions that are conditional controls
571 system.cpu0.num_int_insts 504092161 # number of integer instructions
572 system.cpu0.num_fp_insts 464416 # number of float instructions
573 system.cpu0.num_int_register_reads 728885661 # number of times the integer registers were read
574 system.cpu0.num_int_register_writes 399652952 # number of times the integer registers were written
575 system.cpu0.num_fp_register_reads 772857 # number of times the floating registers were read
576 system.cpu0.num_fp_register_writes 344936 # number of times the floating registers were written
577 system.cpu0.num_cc_register_reads 120908457 # number of times the CC registers were read
578 system.cpu0.num_cc_register_writes 120465396 # number of times the CC registers were written
579 system.cpu0.num_mem_refs 167663327 # number of memory refs
580 system.cpu0.num_load_insts 87924608 # Number of load instructions
581 system.cpu0.num_store_insts 79738719 # Number of store instructions
582 system.cpu0.num_idle_cycles 93943889977.646729 # Number of idle cycles
583 system.cpu0.num_busy_cycles 1261245924.353277 # Number of busy cycles
584 system.cpu0.not_idle_fraction 0.013248 # Percentage of non-idle cycles
585 system.cpu0.idle_fraction 0.986752 # Percentage of idle cycles
586 system.cpu0.Branches 104008564 # Number of branches fetched
587 system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
588 system.cpu0.op_class::IntAlu 379698158 69.20% 69.20% # Class of executed instruction
589 system.cpu0.op_class::IntMult 1212773 0.22% 69.42% # Class of executed instruction
590 system.cpu0.op_class::IntDiv 66852 0.01% 69.43% # Class of executed instruction
591 system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
592 system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
593 system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
594 system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
595 system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
596 system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
597 system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
598 system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
599 system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
600 system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
601 system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
602 system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
603 system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
604 system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
605 system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
606 system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
607 system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
608 system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction
609 system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
610 system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction
611 system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction
612 system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
613 system.cpu0.op_class::SimdFloatMisc 46447 0.01% 69.44% # Class of executed instruction
614 system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction
615 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction
616 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction
617 system.cpu0.op_class::MemRead 87924608 16.02% 85.47% # Class of executed instruction
618 system.cpu0.op_class::MemWrite 79738719 14.53% 100.00% # Class of executed instruction
619 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
620 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
621 system.cpu0.op_class::total 548687557 # Class of executed instruction
622 system.cpu0.dcache.tags.replacements 5767473 # number of replacements
623 system.cpu0.dcache.tags.tagsinuse 506.102777 # Cycle average of tags in use
624 system.cpu0.dcache.tags.total_refs 161665939 # Total number of references to valid blocks.
625 system.cpu0.dcache.tags.sampled_refs 5767985 # Sample count of references to valid blocks.
626 system.cpu0.dcache.tags.avg_refs 28.028148 # Average number of references to valid blocks.
627 system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit.
628 system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.102777 # Average occupied blocks per requestor
629 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988482 # Average percentage of cache occupancy
630 system.cpu0.dcache.tags.occ_percent::total 0.988482 # Average percentage of cache occupancy
631 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
632 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
633 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id
634 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
635 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
636 system.cpu0.dcache.tags.tag_accesses 341141490 # Number of tag accesses
637 system.cpu0.dcache.tags.data_accesses 341141490 # Number of data accesses
638 system.cpu0.dcache.ReadReq_hits::cpu0.data 81909684 # number of ReadReq hits
639 system.cpu0.dcache.ReadReq_hits::total 81909684 # number of ReadReq hits
640 system.cpu0.dcache.WriteReq_hits::cpu0.data 75364450 # number of WriteReq hits
641 system.cpu0.dcache.WriteReq_hits::total 75364450 # number of WriteReq hits
642 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195602 # number of SoftPFReq hits
643 system.cpu0.dcache.SoftPFReq_hits::total 195602 # number of SoftPFReq hits
644 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 139312 # number of WriteLineReq hits
645 system.cpu0.dcache.WriteLineReq_hits::total 139312 # number of WriteLineReq hits
646 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1827663 # number of LoadLockedReq hits
647 system.cpu0.dcache.LoadLockedReq_hits::total 1827663 # number of LoadLockedReq hits
648 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798607 # number of StoreCondReq hits
649 system.cpu0.dcache.StoreCondReq_hits::total 1798607 # number of StoreCondReq hits
650 system.cpu0.dcache.demand_hits::cpu0.data 157274134 # number of demand (read+write) hits
651 system.cpu0.dcache.demand_hits::total 157274134 # number of demand (read+write) hits
652 system.cpu0.dcache.overall_hits::cpu0.data 157469736 # number of overall hits
653 system.cpu0.dcache.overall_hits::total 157469736 # number of overall hits
654 system.cpu0.dcache.ReadReq_misses::cpu0.data 3156555 # number of ReadReq misses
655 system.cpu0.dcache.ReadReq_misses::total 3156555 # number of ReadReq misses
656 system.cpu0.dcache.WriteReq_misses::cpu0.data 1440320 # number of WriteReq misses
657 system.cpu0.dcache.WriteReq_misses::total 1440320 # number of WriteReq misses
658 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651795 # number of SoftPFReq misses
659 system.cpu0.dcache.SoftPFReq_misses::total 651795 # number of SoftPFReq misses
660 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 776738 # number of WriteLineReq misses
661 system.cpu0.dcache.WriteLineReq_misses::total 776738 # number of WriteLineReq misses
662 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172749 # number of LoadLockedReq misses
663 system.cpu0.dcache.LoadLockedReq_misses::total 172749 # number of LoadLockedReq misses
664 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200464 # number of StoreCondReq misses
665 system.cpu0.dcache.StoreCondReq_misses::total 200464 # number of StoreCondReq misses
666 system.cpu0.dcache.demand_misses::cpu0.data 4596875 # number of demand (read+write) misses
667 system.cpu0.dcache.demand_misses::total 4596875 # number of demand (read+write) misses
668 system.cpu0.dcache.overall_misses::cpu0.data 5248670 # number of overall misses
669 system.cpu0.dcache.overall_misses::total 5248670 # number of overall misses
670 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52100226500 # number of ReadReq miss cycles
671 system.cpu0.dcache.ReadReq_miss_latency::total 52100226500 # number of ReadReq miss cycles
672 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36687284500 # number of WriteReq miss cycles
673 system.cpu0.dcache.WriteReq_miss_latency::total 36687284500 # number of WriteReq miss cycles
674 system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65915448000 # number of WriteLineReq miss cycles
675 system.cpu0.dcache.WriteLineReq_miss_latency::total 65915448000 # number of WriteLineReq miss cycles
676 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2830376000 # number of LoadLockedReq miss cycles
677 system.cpu0.dcache.LoadLockedReq_miss_latency::total 2830376000 # number of LoadLockedReq miss cycles
678 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5792176500 # number of StoreCondReq miss cycles
679 system.cpu0.dcache.StoreCondReq_miss_latency::total 5792176500 # number of StoreCondReq miss cycles
680 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4797000 # number of StoreCondFailReq miss cycles
681 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4797000 # number of StoreCondFailReq miss cycles
682 system.cpu0.dcache.demand_miss_latency::cpu0.data 88787511000 # number of demand (read+write) miss cycles
683 system.cpu0.dcache.demand_miss_latency::total 88787511000 # number of demand (read+write) miss cycles
684 system.cpu0.dcache.overall_miss_latency::cpu0.data 88787511000 # number of overall miss cycles
685 system.cpu0.dcache.overall_miss_latency::total 88787511000 # number of overall miss cycles
686 system.cpu0.dcache.ReadReq_accesses::cpu0.data 85066239 # number of ReadReq accesses(hits+misses)
687 system.cpu0.dcache.ReadReq_accesses::total 85066239 # number of ReadReq accesses(hits+misses)
688 system.cpu0.dcache.WriteReq_accesses::cpu0.data 76804770 # number of WriteReq accesses(hits+misses)
689 system.cpu0.dcache.WriteReq_accesses::total 76804770 # number of WriteReq accesses(hits+misses)
690 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847397 # number of SoftPFReq accesses(hits+misses)
691 system.cpu0.dcache.SoftPFReq_accesses::total 847397 # number of SoftPFReq accesses(hits+misses)
692 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 916050 # number of WriteLineReq accesses(hits+misses)
693 system.cpu0.dcache.WriteLineReq_accesses::total 916050 # number of WriteLineReq accesses(hits+misses)
694 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2000412 # number of LoadLockedReq accesses(hits+misses)
695 system.cpu0.dcache.LoadLockedReq_accesses::total 2000412 # number of LoadLockedReq accesses(hits+misses)
696 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1999071 # number of StoreCondReq accesses(hits+misses)
697 system.cpu0.dcache.StoreCondReq_accesses::total 1999071 # number of StoreCondReq accesses(hits+misses)
698 system.cpu0.dcache.demand_accesses::cpu0.data 161871009 # number of demand (read+write) accesses
699 system.cpu0.dcache.demand_accesses::total 161871009 # number of demand (read+write) accesses
700 system.cpu0.dcache.overall_accesses::cpu0.data 162718406 # number of overall (read+write) accesses
701 system.cpu0.dcache.overall_accesses::total 162718406 # number of overall (read+write) accesses
702 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037107 # miss rate for ReadReq accesses
703 system.cpu0.dcache.ReadReq_miss_rate::total 0.037107 # miss rate for ReadReq accesses
704 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018753 # miss rate for WriteReq accesses
705 system.cpu0.dcache.WriteReq_miss_rate::total 0.018753 # miss rate for WriteReq accesses
706 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769173 # miss rate for SoftPFReq accesses
707 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769173 # miss rate for SoftPFReq accesses
708 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.847921 # miss rate for WriteLineReq accesses
709 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.847921 # miss rate for WriteLineReq accesses
710 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086357 # miss rate for LoadLockedReq accesses
711 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086357 # miss rate for LoadLockedReq accesses
712 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100279 # miss rate for StoreCondReq accesses
713 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100279 # miss rate for StoreCondReq accesses
714 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028398 # miss rate for demand accesses
715 system.cpu0.dcache.demand_miss_rate::total 0.028398 # miss rate for demand accesses
716 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032256 # miss rate for overall accesses
717 system.cpu0.dcache.overall_miss_rate::total 0.032256 # miss rate for overall accesses
718 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16505.407477 # average ReadReq miss latency
719 system.cpu0.dcache.ReadReq_avg_miss_latency::total 16505.407477 # average ReadReq miss latency
720 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25471.620543 # average WriteReq miss latency
721 system.cpu0.dcache.WriteReq_avg_miss_latency::total 25471.620543 # average WriteReq miss latency
722 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 84861.881355 # average WriteLineReq miss latency
723 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 84861.881355 # average WriteLineReq miss latency
724 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16384.326393 # average LoadLockedReq miss latency
725 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16384.326393 # average LoadLockedReq miss latency
726 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771 # average StoreCondReq miss latency
727 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771 # average StoreCondReq miss latency
728 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
729 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
730 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19314.754262 # average overall miss latency
731 system.cpu0.dcache.demand_avg_miss_latency::total 19314.754262 # average overall miss latency
732 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16916.192293 # average overall miss latency
733 system.cpu0.dcache.overall_avg_miss_latency::total 16916.192293 # average overall miss latency
734 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
735 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
736 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
737 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
738 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
739 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
740 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
741 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
742 system.cpu0.dcache.writebacks::writebacks 5767473 # number of writebacks
743 system.cpu0.dcache.writebacks::total 5767473 # number of writebacks
744 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27282 # number of ReadReq MSHR hits
745 system.cpu0.dcache.ReadReq_mshr_hits::total 27282 # number of ReadReq MSHR hits
746 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21266 # number of WriteReq MSHR hits
747 system.cpu0.dcache.WriteReq_mshr_hits::total 21266 # number of WriteReq MSHR hits
748 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44626 # number of LoadLockedReq MSHR hits
749 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44626 # number of LoadLockedReq MSHR hits
750 system.cpu0.dcache.demand_mshr_hits::cpu0.data 48548 # number of demand (read+write) MSHR hits
751 system.cpu0.dcache.demand_mshr_hits::total 48548 # number of demand (read+write) MSHR hits
752 system.cpu0.dcache.overall_mshr_hits::cpu0.data 48548 # number of overall MSHR hits
753 system.cpu0.dcache.overall_mshr_hits::total 48548 # number of overall MSHR hits
754 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3129273 # number of ReadReq MSHR misses
755 system.cpu0.dcache.ReadReq_mshr_misses::total 3129273 # number of ReadReq MSHR misses
756 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419054 # number of WriteReq MSHR misses
757 system.cpu0.dcache.WriteReq_mshr_misses::total 1419054 # number of WriteReq MSHR misses
758 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 650511 # number of SoftPFReq MSHR misses
759 system.cpu0.dcache.SoftPFReq_mshr_misses::total 650511 # number of SoftPFReq MSHR misses
760 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 776738 # number of WriteLineReq MSHR misses
761 system.cpu0.dcache.WriteLineReq_mshr_misses::total 776738 # number of WriteLineReq MSHR misses
762 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128123 # number of LoadLockedReq MSHR misses
763 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128123 # number of LoadLockedReq MSHR misses
764 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200464 # number of StoreCondReq MSHR misses
765 system.cpu0.dcache.StoreCondReq_mshr_misses::total 200464 # number of StoreCondReq MSHR misses
766 system.cpu0.dcache.demand_mshr_misses::cpu0.data 4548327 # number of demand (read+write) MSHR misses
767 system.cpu0.dcache.demand_mshr_misses::total 4548327 # number of demand (read+write) MSHR misses
768 system.cpu0.dcache.overall_mshr_misses::cpu0.data 5198838 # number of overall MSHR misses
769 system.cpu0.dcache.overall_mshr_misses::total 5198838 # number of overall MSHR misses
770 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable
771 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15619 # number of ReadReq MSHR uncacheable
772 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable
773 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16479 # number of WriteReq MSHR uncacheable
774 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses
775 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32098 # number of overall MSHR uncacheable misses
776 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47104061500 # number of ReadReq MSHR miss cycles
777 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47104061500 # number of ReadReq MSHR miss cycles
778 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34681725000 # number of WriteReq MSHR miss cycles
779 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34681725000 # number of WriteReq MSHR miss cycles
780 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15920895000 # number of SoftPFReq MSHR miss cycles
781 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15920895000 # number of SoftPFReq MSHR miss cycles
782 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 65138711000 # number of WriteLineReq MSHR miss cycles
783 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65138711000 # number of WriteLineReq MSHR miss cycles
784 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795303000 # number of LoadLockedReq MSHR miss cycles
785 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795303000 # number of LoadLockedReq MSHR miss cycles
786 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5591766500 # number of StoreCondReq MSHR miss cycles
787 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5591766500 # number of StoreCondReq MSHR miss cycles
788 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4743000 # number of StoreCondFailReq MSHR miss cycles
789 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4743000 # number of StoreCondFailReq MSHR miss cycles
790 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 81785786500 # number of demand (read+write) MSHR miss cycles
791 system.cpu0.dcache.demand_mshr_miss_latency::total 81785786500 # number of demand (read+write) MSHR miss cycles
792 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97706681500 # number of overall MSHR miss cycles
793 system.cpu0.dcache.overall_mshr_miss_latency::total 97706681500 # number of overall MSHR miss cycles
794 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2690935500 # number of ReadReq MSHR uncacheable cycles
795 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2690935500 # number of ReadReq MSHR uncacheable cycles
796 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2795849000 # number of WriteReq MSHR uncacheable cycles
797 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2795849000 # number of WriteReq MSHR uncacheable cycles
798 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5486784500 # number of overall MSHR uncacheable cycles
799 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5486784500 # number of overall MSHR uncacheable cycles
800 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036786 # mshr miss rate for ReadReq accesses
801 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036786 # mshr miss rate for ReadReq accesses
802 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018476 # mshr miss rate for WriteReq accesses
803 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018476 # mshr miss rate for WriteReq accesses
804 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767658 # mshr miss rate for SoftPFReq accesses
805 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767658 # mshr miss rate for SoftPFReq accesses
806 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.847921 # mshr miss rate for WriteLineReq accesses
807 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.847921 # mshr miss rate for WriteLineReq accesses
808 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064048 # mshr miss rate for LoadLockedReq accesses
809 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064048 # mshr miss rate for LoadLockedReq accesses
810 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100279 # mshr miss rate for StoreCondReq accesses
811 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100279 # mshr miss rate for StoreCondReq accesses
812 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028098 # mshr miss rate for demand accesses
813 system.cpu0.dcache.demand_mshr_miss_rate::total 0.028098 # mshr miss rate for demand accesses
814 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031950 # mshr miss rate for overall accesses
815 system.cpu0.dcache.overall_mshr_miss_rate::total 0.031950 # mshr miss rate for overall accesses
816 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15052.717197 # average ReadReq mshr miss latency
817 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15052.717197 # average ReadReq mshr miss latency
818 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24440.031880 # average WriteReq mshr miss latency
819 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24440.031880 # average WriteReq mshr miss latency
820 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24474.443937 # average SoftPFReq mshr miss latency
821 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24474.443937 # average SoftPFReq mshr miss latency
822 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643 # average WriteLineReq mshr miss latency
823 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643 # average WriteLineReq mshr miss latency
824 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705 # average LoadLockedReq mshr miss latency
825 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705 # average LoadLockedReq mshr miss latency
826 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146 # average StoreCondReq mshr miss latency
827 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146 # average StoreCondReq mshr miss latency
828 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
829 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
830 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795 # average overall mshr miss latency
831 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795 # average overall mshr miss latency
832 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166 # average overall mshr miss latency
833 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166 # average overall mshr miss latency
834 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835 # average ReadReq mshr uncacheable latency
835 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835 # average ReadReq mshr uncacheable latency
836 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537 # average WriteReq mshr uncacheable latency
837 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169661.326537 # average WriteReq mshr uncacheable latency
838 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170938.516418 # average overall mshr uncacheable latency
839 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170938.516418 # average overall mshr uncacheable latency
840 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
841 system.cpu0.icache.tags.replacements 5175196 # number of replacements
842 system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use
843 system.cpu0.icache.tags.total_refs 462027213 # Total number of references to valid blocks.
844 system.cpu0.icache.tags.sampled_refs 5175708 # Sample count of references to valid blocks.
845 system.cpu0.icache.tags.avg_refs 89.268408 # Average number of references to valid blocks.
846 system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit.
847 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor
848 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy
849 system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy
850 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
851 system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
852 system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
853 system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id
854 system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
855 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
856 system.cpu0.icache.tags.tag_accesses 939581550 # Number of tag accesses
857 system.cpu0.icache.tags.data_accesses 939581550 # Number of data accesses
858 system.cpu0.icache.ReadReq_hits::cpu0.inst 462027213 # number of ReadReq hits
859 system.cpu0.icache.ReadReq_hits::total 462027213 # number of ReadReq hits
860 system.cpu0.icache.demand_hits::cpu0.inst 462027213 # number of demand (read+write) hits
861 system.cpu0.icache.demand_hits::total 462027213 # number of demand (read+write) hits
862 system.cpu0.icache.overall_hits::cpu0.inst 462027213 # number of overall hits
863 system.cpu0.icache.overall_hits::total 462027213 # number of overall hits
864 system.cpu0.icache.ReadReq_misses::cpu0.inst 5175708 # number of ReadReq misses
865 system.cpu0.icache.ReadReq_misses::total 5175708 # number of ReadReq misses
866 system.cpu0.icache.demand_misses::cpu0.inst 5175708 # number of demand (read+write) misses
867 system.cpu0.icache.demand_misses::total 5175708 # number of demand (read+write) misses
868 system.cpu0.icache.overall_misses::cpu0.inst 5175708 # number of overall misses
869 system.cpu0.icache.overall_misses::total 5175708 # number of overall misses
870 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57336545500 # number of ReadReq miss cycles
871 system.cpu0.icache.ReadReq_miss_latency::total 57336545500 # number of ReadReq miss cycles
872 system.cpu0.icache.demand_miss_latency::cpu0.inst 57336545500 # number of demand (read+write) miss cycles
873 system.cpu0.icache.demand_miss_latency::total 57336545500 # number of demand (read+write) miss cycles
874 system.cpu0.icache.overall_miss_latency::cpu0.inst 57336545500 # number of overall miss cycles
875 system.cpu0.icache.overall_miss_latency::total 57336545500 # number of overall miss cycles
876 system.cpu0.icache.ReadReq_accesses::cpu0.inst 467202921 # number of ReadReq accesses(hits+misses)
877 system.cpu0.icache.ReadReq_accesses::total 467202921 # number of ReadReq accesses(hits+misses)
878 system.cpu0.icache.demand_accesses::cpu0.inst 467202921 # number of demand (read+write) accesses
879 system.cpu0.icache.demand_accesses::total 467202921 # number of demand (read+write) accesses
880 system.cpu0.icache.overall_accesses::cpu0.inst 467202921 # number of overall (read+write) accesses
881 system.cpu0.icache.overall_accesses::total 467202921 # number of overall (read+write) accesses
882 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011078 # miss rate for ReadReq accesses
883 system.cpu0.icache.ReadReq_miss_rate::total 0.011078 # miss rate for ReadReq accesses
884 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011078 # miss rate for demand accesses
885 system.cpu0.icache.demand_miss_rate::total 0.011078 # miss rate for demand accesses
886 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011078 # miss rate for overall accesses
887 system.cpu0.icache.overall_miss_rate::total 0.011078 # miss rate for overall accesses
888 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11078.010100 # average ReadReq miss latency
889 system.cpu0.icache.ReadReq_avg_miss_latency::total 11078.010100 # average ReadReq miss latency
890 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency
891 system.cpu0.icache.demand_avg_miss_latency::total 11078.010100 # average overall miss latency
892 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency
893 system.cpu0.icache.overall_avg_miss_latency::total 11078.010100 # average overall miss latency
894 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
895 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
896 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
897 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
898 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
899 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
900 system.cpu0.icache.fast_writes 0 # number of fast writes performed
901 system.cpu0.icache.cache_copies 0 # number of cache copies performed
902 system.cpu0.icache.writebacks::writebacks 5175196 # number of writebacks
903 system.cpu0.icache.writebacks::total 5175196 # number of writebacks
904 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5175708 # number of ReadReq MSHR misses
905 system.cpu0.icache.ReadReq_mshr_misses::total 5175708 # number of ReadReq MSHR misses
906 system.cpu0.icache.demand_mshr_misses::cpu0.inst 5175708 # number of demand (read+write) MSHR misses
907 system.cpu0.icache.demand_mshr_misses::total 5175708 # number of demand (read+write) MSHR misses
908 system.cpu0.icache.overall_mshr_misses::cpu0.inst 5175708 # number of overall MSHR misses
909 system.cpu0.icache.overall_mshr_misses::total 5175708 # number of overall MSHR misses
910 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
911 system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
912 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
913 system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
914 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 54748691500 # number of ReadReq MSHR miss cycles
915 system.cpu0.icache.ReadReq_mshr_miss_latency::total 54748691500 # number of ReadReq MSHR miss cycles
916 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 54748691500 # number of demand (read+write) MSHR miss cycles
917 system.cpu0.icache.demand_mshr_miss_latency::total 54748691500 # number of demand (read+write) MSHR miss cycles
918 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 54748691500 # number of overall MSHR miss cycles
919 system.cpu0.icache.overall_mshr_miss_latency::total 54748691500 # number of overall MSHR miss cycles
920 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles
921 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles
922 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles
923 system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles
924 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for ReadReq accesses
925 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011078 # mshr miss rate for ReadReq accesses
926 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for demand accesses
927 system.cpu0.icache.demand_mshr_miss_rate::total 0.011078 # mshr miss rate for demand accesses
928 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for overall accesses
929 system.cpu0.icache.overall_mshr_miss_rate::total 0.011078 # mshr miss rate for overall accesses
930 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average ReadReq mshr miss latency
931 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100 # average ReadReq mshr miss latency
932 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency
933 system.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency
934 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency
935 system.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency
936 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency
937 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency
938 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency
939 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency
940 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
941 system.cpu0.l2cache.prefetcher.num_hwpf_issued 7857654 # number of hwpf issued
942 system.cpu0.l2cache.prefetcher.pfIdentified 7857701 # number of prefetch candidates identified
943 system.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue
944 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
945 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
946 system.cpu0.l2cache.prefetcher.pfSpanPage 1019611 # number of prefetches not generated due to page crossing
947 system.cpu0.l2cache.tags.replacements 2391891 # number of replacements
948 system.cpu0.l2cache.tags.tagsinuse 16167.019190 # Cycle average of tags in use
949 system.cpu0.l2cache.tags.total_refs 15476667 # Total number of references to valid blocks.
950 system.cpu0.l2cache.tags.sampled_refs 2407580 # Sample count of references to valid blocks.
951 system.cpu0.l2cache.tags.avg_refs 6.428309 # Average number of references to valid blocks.
952 system.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit.
953 system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.445219 # Average occupied blocks per requestor
954 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.058428 # Average occupied blocks per requestor
955 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.612606 # Average occupied blocks per requestor
956 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 747.902937 # Average occupied blocks per requestor
957 system.cpu0.l2cache.tags.occ_percent::writebacks 0.932522 # Average percentage of cache occupancy
958 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003727 # Average percentage of cache occupancy
959 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004859 # Average percentage of cache occupancy
960 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.045648 # Average percentage of cache occupancy
961 system.cpu0.l2cache.tags.occ_percent::total 0.986757 # Average percentage of cache occupancy
962 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1309 # Occupied blocks per task id
963 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id
964 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14303 # Occupied blocks per task id
965 system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id
966 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 161 # Occupied blocks per task id
967 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id
968 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 356 # Occupied blocks per task id
969 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 28 # Occupied blocks per task id
970 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id
971 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
972 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
973 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id
974 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4392 # Occupied blocks per task id
975 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6793 # Occupied blocks per task id
976 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2165 # Occupied blocks per task id
977 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079895 # Percentage of cache occupancy per task id
978 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id
979 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.872986 # Percentage of cache occupancy per task id
980 system.cpu0.l2cache.tags.tag_accesses 371635811 # Number of tag accesses
981 system.cpu0.l2cache.tags.data_accesses 371635811 # Number of data accesses
982 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 264720 # number of ReadReq hits
983 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157843 # number of ReadReq hits
984 system.cpu0.l2cache.ReadReq_hits::total 422563 # number of ReadReq hits
985 system.cpu0.l2cache.WritebackDirty_hits::writebacks 3807067 # number of WritebackDirty hits
986 system.cpu0.l2cache.WritebackDirty_hits::total 3807067 # number of WritebackDirty hits
987 system.cpu0.l2cache.WritebackClean_hits::writebacks 7134877 # number of WritebackClean hits
988 system.cpu0.l2cache.WritebackClean_hits::total 7134877 # number of WritebackClean hits
989 system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 457 # number of UpgradeReq hits
990 system.cpu0.l2cache.UpgradeReq_hits::total 457 # number of UpgradeReq hits
991 system.cpu0.l2cache.ReadExReq_hits::cpu0.data 928109 # number of ReadExReq hits
992 system.cpu0.l2cache.ReadExReq_hits::total 928109 # number of ReadExReq hits
993 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4693228 # number of ReadCleanReq hits
994 system.cpu0.l2cache.ReadCleanReq_hits::total 4693228 # number of ReadCleanReq hits
995 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2960524 # number of ReadSharedReq hits
996 system.cpu0.l2cache.ReadSharedReq_hits::total 2960524 # number of ReadSharedReq hits
997 system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 208597 # number of InvalidateReq hits
998 system.cpu0.l2cache.InvalidateReq_hits::total 208597 # number of InvalidateReq hits
999 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 264720 # number of demand (read+write) hits
1000 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157843 # number of demand (read+write) hits
1001 system.cpu0.l2cache.demand_hits::cpu0.inst 4693228 # number of demand (read+write) hits
1002 system.cpu0.l2cache.demand_hits::cpu0.data 3888633 # number of demand (read+write) hits
1003 system.cpu0.l2cache.demand_hits::total 9004424 # number of demand (read+write) hits
1004 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 264720 # number of overall hits
1005 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157843 # number of overall hits
1006 system.cpu0.l2cache.overall_hits::cpu0.inst 4693228 # number of overall hits
1007 system.cpu0.l2cache.overall_hits::cpu0.data 3888633 # number of overall hits
1008 system.cpu0.l2cache.overall_hits::total 9004424 # number of overall hits
1009 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10067 # number of ReadReq misses
1010 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8203 # number of ReadReq misses
1011 system.cpu0.l2cache.ReadReq_misses::total 18270 # number of ReadReq misses
1012 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246628 # number of UpgradeReq misses
1013 system.cpu0.l2cache.UpgradeReq_misses::total 246628 # number of UpgradeReq misses
1014 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200453 # number of SCUpgradeReq misses
1015 system.cpu0.l2cache.SCUpgradeReq_misses::total 200453 # number of SCUpgradeReq misses
1016 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses
1017 system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses
1018 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262909 # number of ReadExReq misses
1019 system.cpu0.l2cache.ReadExReq_misses::total 262909 # number of ReadExReq misses
1020 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 482480 # number of ReadCleanReq misses
1021 system.cpu0.l2cache.ReadCleanReq_misses::total 482480 # number of ReadCleanReq misses
1022 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 947383 # number of ReadSharedReq misses
1023 system.cpu0.l2cache.ReadSharedReq_misses::total 947383 # number of ReadSharedReq misses
1024 system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 566022 # number of InvalidateReq misses
1025 system.cpu0.l2cache.InvalidateReq_misses::total 566022 # number of InvalidateReq misses
1026 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10067 # number of demand (read+write) misses
1027 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8203 # number of demand (read+write) misses
1028 system.cpu0.l2cache.demand_misses::cpu0.inst 482480 # number of demand (read+write) misses
1029 system.cpu0.l2cache.demand_misses::cpu0.data 1210292 # number of demand (read+write) misses
1030 system.cpu0.l2cache.demand_misses::total 1711042 # number of demand (read+write) misses
1031 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10067 # number of overall misses
1032 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8203 # number of overall misses
1033 system.cpu0.l2cache.overall_misses::cpu0.inst 482480 # number of overall misses
1034 system.cpu0.l2cache.overall_misses::cpu0.data 1210292 # number of overall misses
1035 system.cpu0.l2cache.overall_misses::total 1711042 # number of overall misses
1036 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 425309500 # number of ReadReq miss cycles
1037 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 392962000 # number of ReadReq miss cycles
1038 system.cpu0.l2cache.ReadReq_miss_latency::total 818271500 # number of ReadReq miss cycles
1039 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3546049000 # number of UpgradeReq miss cycles
1040 system.cpu0.l2cache.UpgradeReq_miss_latency::total 3546049000 # number of UpgradeReq miss cycles
1041 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2066053000 # number of SCUpgradeReq miss cycles
1042 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2066053000 # number of SCUpgradeReq miss cycles
1043 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4661500 # number of SCUpgradeFailReq miss cycles
1044 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4661500 # number of SCUpgradeFailReq miss cycles
1045 system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16748515499 # number of ReadExReq miss cycles
1046 system.cpu0.l2cache.ReadExReq_miss_latency::total 16748515499 # number of ReadExReq miss cycles
1047 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18800277000 # number of ReadCleanReq miss cycles
1048 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 18800277000 # number of ReadCleanReq miss cycles
1049 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39672427000 # number of ReadSharedReq miss cycles
1050 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39672427000 # number of ReadSharedReq miss cycles
1051 system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62566205500 # number of InvalidateReq miss cycles
1052 system.cpu0.l2cache.InvalidateReq_miss_latency::total 62566205500 # number of InvalidateReq miss cycles
1053 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 425309500 # number of demand (read+write) miss cycles
1054 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 392962000 # number of demand (read+write) miss cycles
1055 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 18800277000 # number of demand (read+write) miss cycles
1056 system.cpu0.l2cache.demand_miss_latency::cpu0.data 56420942499 # number of demand (read+write) miss cycles
1057 system.cpu0.l2cache.demand_miss_latency::total 76039490999 # number of demand (read+write) miss cycles
1058 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 425309500 # number of overall miss cycles
1059 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 392962000 # number of overall miss cycles
1060 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 18800277000 # number of overall miss cycles
1061 system.cpu0.l2cache.overall_miss_latency::cpu0.data 56420942499 # number of overall miss cycles
1062 system.cpu0.l2cache.overall_miss_latency::total 76039490999 # number of overall miss cycles
1063 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 274787 # number of ReadReq accesses(hits+misses)
1064 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166046 # number of ReadReq accesses(hits+misses)
1065 system.cpu0.l2cache.ReadReq_accesses::total 440833 # number of ReadReq accesses(hits+misses)
1066 system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3807067 # number of WritebackDirty accesses(hits+misses)
1067 system.cpu0.l2cache.WritebackDirty_accesses::total 3807067 # number of WritebackDirty accesses(hits+misses)
1068 system.cpu0.l2cache.WritebackClean_accesses::writebacks 7134877 # number of WritebackClean accesses(hits+misses)
1069 system.cpu0.l2cache.WritebackClean_accesses::total 7134877 # number of WritebackClean accesses(hits+misses)
1070 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 247085 # number of UpgradeReq accesses(hits+misses)
1071 system.cpu0.l2cache.UpgradeReq_accesses::total 247085 # number of UpgradeReq accesses(hits+misses)
1072 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200453 # number of SCUpgradeReq accesses(hits+misses)
1073 system.cpu0.l2cache.SCUpgradeReq_accesses::total 200453 # number of SCUpgradeReq accesses(hits+misses)
1074 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses)
1075 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses)
1076 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1191018 # number of ReadExReq accesses(hits+misses)
1077 system.cpu0.l2cache.ReadExReq_accesses::total 1191018 # number of ReadExReq accesses(hits+misses)
1078 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5175708 # number of ReadCleanReq accesses(hits+misses)
1079 system.cpu0.l2cache.ReadCleanReq_accesses::total 5175708 # number of ReadCleanReq accesses(hits+misses)
1080 system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3907907 # number of ReadSharedReq accesses(hits+misses)
1081 system.cpu0.l2cache.ReadSharedReq_accesses::total 3907907 # number of ReadSharedReq accesses(hits+misses)
1082 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 774619 # number of InvalidateReq accesses(hits+misses)
1083 system.cpu0.l2cache.InvalidateReq_accesses::total 774619 # number of InvalidateReq accesses(hits+misses)
1084 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 274787 # number of demand (read+write) accesses
1085 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166046 # number of demand (read+write) accesses
1086 system.cpu0.l2cache.demand_accesses::cpu0.inst 5175708 # number of demand (read+write) accesses
1087 system.cpu0.l2cache.demand_accesses::cpu0.data 5098925 # number of demand (read+write) accesses
1088 system.cpu0.l2cache.demand_accesses::total 10715466 # number of demand (read+write) accesses
1089 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 274787 # number of overall (read+write) accesses
1090 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166046 # number of overall (read+write) accesses
1091 system.cpu0.l2cache.overall_accesses::cpu0.inst 5175708 # number of overall (read+write) accesses
1092 system.cpu0.l2cache.overall_accesses::cpu0.data 5098925 # number of overall (read+write) accesses
1093 system.cpu0.l2cache.overall_accesses::total 10715466 # number of overall (read+write) accesses
1094 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for ReadReq accesses
1095 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049402 # miss rate for ReadReq accesses
1096 system.cpu0.l2cache.ReadReq_miss_rate::total 0.041444 # miss rate for ReadReq accesses
1097 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998150 # miss rate for UpgradeReq accesses
1098 system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998150 # miss rate for UpgradeReq accesses
1099 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1100 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1101 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1102 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1103 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.220743 # miss rate for ReadExReq accesses
1104 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.220743 # miss rate for ReadExReq accesses
1105 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093220 # miss rate for ReadCleanReq accesses
1106 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093220 # miss rate for ReadCleanReq accesses
1107 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242427 # miss rate for ReadSharedReq accesses
1108 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242427 # miss rate for ReadSharedReq accesses
1109 system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730710 # miss rate for InvalidateReq accesses
1110 system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730710 # miss rate for InvalidateReq accesses
1111 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for demand accesses
1112 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049402 # miss rate for demand accesses
1113 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093220 # miss rate for demand accesses
1114 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237362 # miss rate for demand accesses
1115 system.cpu0.l2cache.demand_miss_rate::total 0.159680 # miss rate for demand accesses
1116 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for overall accesses
1117 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049402 # miss rate for overall accesses
1118 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093220 # miss rate for overall accesses
1119 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237362 # miss rate for overall accesses
1120 system.cpu0.l2cache.overall_miss_rate::total 0.159680 # miss rate for overall accesses
1121 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average ReadReq miss latency
1122 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47904.669024 # average ReadReq miss latency
1123 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44787.712096 # average ReadReq miss latency
1124 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14378.128193 # average UpgradeReq miss latency
1125 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14378.128193 # average UpgradeReq miss latency
1126 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10306.919827 # average SCUpgradeReq miss latency
1127 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10306.919827 # average SCUpgradeReq miss latency
1128 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423772.727273 # average SCUpgradeFailReq miss latency
1129 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423772.727273 # average SCUpgradeFailReq miss latency
1130 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63704.610717 # average ReadExReq miss latency
1131 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63704.610717 # average ReadExReq miss latency
1132 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38965.919831 # average ReadCleanReq miss latency
1133 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38965.919831 # average ReadCleanReq miss latency
1134 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41875.806300 # average ReadSharedReq miss latency
1135 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41875.806300 # average ReadSharedReq miss latency
1136 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 110536.702637 # average InvalidateReq miss latency
1137 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 110536.702637 # average InvalidateReq miss latency
1138 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average overall miss latency
1139 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47904.669024 # average overall miss latency
1140 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38965.919831 # average overall miss latency
1141 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46617.628224 # average overall miss latency
1142 system.cpu0.l2cache.demand_avg_miss_latency::total 44440.458504 # average overall miss latency
1143 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average overall miss latency
1144 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47904.669024 # average overall miss latency
1145 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38965.919831 # average overall miss latency
1146 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46617.628224 # average overall miss latency
1147 system.cpu0.l2cache.overall_avg_miss_latency::total 44440.458504 # average overall miss latency
1148 system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1149 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1150 system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1151 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1152 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1153 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1154 system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1155 system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1156 system.cpu0.l2cache.writebacks::writebacks 1521426 # number of writebacks
1157 system.cpu0.l2cache.writebacks::total 1521426 # number of writebacks
1158 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5411 # number of ReadExReq MSHR hits
1159 system.cpu0.l2cache.ReadExReq_mshr_hits::total 5411 # number of ReadExReq MSHR hits
1160 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 533 # number of ReadSharedReq MSHR hits
1161 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 533 # number of ReadSharedReq MSHR hits
1162 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5944 # number of demand (read+write) MSHR hits
1163 system.cpu0.l2cache.demand_mshr_hits::total 5944 # number of demand (read+write) MSHR hits
1164 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5944 # number of overall MSHR hits
1165 system.cpu0.l2cache.overall_mshr_hits::total 5944 # number of overall MSHR hits
1166 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10067 # number of ReadReq MSHR misses
1167 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8203 # number of ReadReq MSHR misses
1168 system.cpu0.l2cache.ReadReq_mshr_misses::total 18270 # number of ReadReq MSHR misses
1169 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 721686 # number of HardPFReq MSHR misses
1170 system.cpu0.l2cache.HardPFReq_mshr_misses::total 721686 # number of HardPFReq MSHR misses
1171 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 246628 # number of UpgradeReq MSHR misses
1172 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 246628 # number of UpgradeReq MSHR misses
1173 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200453 # number of SCUpgradeReq MSHR misses
1174 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200453 # number of SCUpgradeReq MSHR misses
1175 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses
1176 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses
1177 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257498 # number of ReadExReq MSHR misses
1178 system.cpu0.l2cache.ReadExReq_mshr_misses::total 257498 # number of ReadExReq MSHR misses
1179 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 482480 # number of ReadCleanReq MSHR misses
1180 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 482480 # number of ReadCleanReq MSHR misses
1181 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 946850 # number of ReadSharedReq MSHR misses
1182 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 946850 # number of ReadSharedReq MSHR misses
1183 system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 566022 # number of InvalidateReq MSHR misses
1184 system.cpu0.l2cache.InvalidateReq_mshr_misses::total 566022 # number of InvalidateReq MSHR misses
1185 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10067 # number of demand (read+write) MSHR misses
1186 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8203 # number of demand (read+write) MSHR misses
1187 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 482480 # number of demand (read+write) MSHR misses
1188 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1204348 # number of demand (read+write) MSHR misses
1189 system.cpu0.l2cache.demand_mshr_misses::total 1705098 # number of demand (read+write) MSHR misses
1190 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10067 # number of overall MSHR misses
1191 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8203 # number of overall MSHR misses
1192 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 482480 # number of overall MSHR misses
1193 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1204348 # number of overall MSHR misses
1194 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 721686 # number of overall MSHR misses
1195 system.cpu0.l2cache.overall_mshr_misses::total 2426784 # number of overall MSHR misses
1196 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
1197 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable
1198 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 58744 # number of ReadReq MSHR uncacheable
1199 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable
1200 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16479 # number of WriteReq MSHR uncacheable
1201 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
1202 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses
1203 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 75223 # number of overall MSHR uncacheable misses
1204 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of ReadReq MSHR miss cycles
1205 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 343744000 # number of ReadReq MSHR miss cycles
1206 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 708651500 # number of ReadReq MSHR miss cycles
1207 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38668799279 # number of HardPFReq MSHR miss cycles
1208 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38668799279 # number of HardPFReq MSHR miss cycles
1209 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7913903000 # number of UpgradeReq MSHR miss cycles
1210 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7913903000 # number of UpgradeReq MSHR miss cycles
1211 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4087252500 # number of SCUpgradeReq MSHR miss cycles
1212 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4087252500 # number of SCUpgradeReq MSHR miss cycles
1213 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4337500 # number of SCUpgradeFailReq MSHR miss cycles
1214 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4337500 # number of SCUpgradeFailReq MSHR miss cycles
1215 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14600636999 # number of ReadExReq MSHR miss cycles
1216 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14600636999 # number of ReadExReq MSHR miss cycles
1217 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15905397000 # number of ReadCleanReq MSHR miss cycles
1218 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15905397000 # number of ReadCleanReq MSHR miss cycles
1219 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33944380000 # number of ReadSharedReq MSHR miss cycles
1220 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33944380000 # number of ReadSharedReq MSHR miss cycles
1221 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 59170079500 # number of InvalidateReq MSHR miss cycles
1222 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 59170079500 # number of InvalidateReq MSHR miss cycles
1223 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of demand (read+write) MSHR miss cycles
1224 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 343744000 # number of demand (read+write) MSHR miss cycles
1225 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15905397000 # number of demand (read+write) MSHR miss cycles
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1227 system.cpu0.l2cache.demand_mshr_miss_latency::total 65159065499 # number of demand (read+write) MSHR miss cycles
1228 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of overall MSHR miss cycles
1229 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 343744000 # number of overall MSHR miss cycles
1230 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15905397000 # number of overall MSHR miss cycles
1231 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 48545016999 # number of overall MSHR miss cycles
1232 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38668799279 # number of overall MSHR miss cycles
1233 system.cpu0.l2cache.overall_mshr_miss_latency::total 103827864778 # number of overall MSHR miss cycles
1234 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles
1235 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2565627500 # number of ReadReq MSHR uncacheable cycles
1236 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8196399000 # number of ReadReq MSHR uncacheable cycles
1237 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2671857000 # number of WriteReq MSHR uncacheable cycles
1238 system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2671857000 # number of WriteReq MSHR uncacheable cycles
1239 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles
1240 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5237484500 # number of overall MSHR uncacheable cycles
1241 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10868256000 # number of overall MSHR uncacheable cycles
1242 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for ReadReq accesses
1243 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for ReadReq accesses
1244 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041444 # mshr miss rate for ReadReq accesses
1245 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1246 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1247 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998150 # mshr miss rate for UpgradeReq accesses
1248 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998150 # mshr miss rate for UpgradeReq accesses
1249 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1250 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1251 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1252 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1253 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216200 # mshr miss rate for ReadExReq accesses
1254 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216200 # mshr miss rate for ReadExReq accesses
1255 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for ReadCleanReq accesses
1256 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093220 # mshr miss rate for ReadCleanReq accesses
1257 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242291 # mshr miss rate for ReadSharedReq accesses
1258 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242291 # mshr miss rate for ReadSharedReq accesses
1259 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730710 # mshr miss rate for InvalidateReq accesses
1260 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730710 # mshr miss rate for InvalidateReq accesses
1261 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for demand accesses
1262 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for demand accesses
1263 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for demand accesses
1264 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236196 # mshr miss rate for demand accesses
1265 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159125 # mshr miss rate for demand accesses
1266 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for overall accesses
1267 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for overall accesses
1268 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for overall accesses
1269 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236196 # mshr miss rate for overall accesses
1270 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1271 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226475 # mshr miss rate for overall accesses
1272 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average ReadReq mshr miss latency
1273 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average ReadReq mshr miss latency
1274 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096 # average ReadReq mshr miss latency
1275 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average HardPFReq mshr miss latency
1276 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364 # average HardPFReq mshr miss latency
1277 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617 # average UpgradeReq mshr miss latency
1278 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617 # average UpgradeReq mshr miss latency
1279 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971 # average SCUpgradeReq mshr miss latency
1280 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971 # average SCUpgradeReq mshr miss latency
1281 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818 # average SCUpgradeFailReq mshr miss latency
1282 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818 # average SCUpgradeFailReq mshr miss latency
1283 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312 # average ReadExReq mshr miss latency
1284 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312 # average ReadExReq mshr miss latency
1285 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average ReadCleanReq mshr miss latency
1286 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831 # average ReadCleanReq mshr miss latency
1287 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694 # average ReadSharedReq mshr miss latency
1288 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694 # average ReadSharedReq mshr miss latency
1289 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237 # average InvalidateReq mshr miss latency
1290 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237 # average InvalidateReq mshr miss latency
1291 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency
1292 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency
1293 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency
1294 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency
1295 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224 # average overall mshr miss latency
1296 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency
1297 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency
1298 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency
1299 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency
1300 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average overall mshr miss latency
1301 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329 # average overall mshr miss latency
1302 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency
1303 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083 # average ReadReq mshr uncacheable latency
1304 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077 # average ReadReq mshr uncacheable latency
1305 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561 # average WriteReq mshr uncacheable latency
1306 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561 # average WriteReq mshr uncacheable latency
1307 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency
1308 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363 # average overall mshr uncacheable latency
1309 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339 # average overall mshr uncacheable latency
1310 system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1311 system.cpu0.toL2Bus.snoop_filter.tot_requests 22685684 # Total number of requests made to the snoop filter.
1312 system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11636633 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1313 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 725 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1314 system.cpu0.toL2Bus.snoop_filter.tot_snoops 1868386 # Total number of snoops made to the snoop filter.
1315 system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1868205 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1316 system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 181 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1317 system.cpu0.toL2Bus.trans_dist::ReadReq 566458 # Transaction distribution
1318 system.cpu0.toL2Bus.trans_dist::ReadResp 9760546 # Transaction distribution
1319 system.cpu0.toL2Bus.trans_dist::WriteReq 16479 # Transaction distribution
1320 system.cpu0.toL2Bus.trans_dist::WriteResp 16479 # Transaction distribution
1321 system.cpu0.toL2Bus.trans_dist::WritebackDirty 5331858 # Transaction distribution
1322 system.cpu0.toL2Bus.trans_dist::WritebackClean 7134877 # Transaction distribution
1323 system.cpu0.toL2Bus.trans_dist::CleanEvict 2347214 # Transaction distribution
1324 system.cpu0.toL2Bus.trans_dist::HardPFReq 886122 # Transaction distribution
1325 system.cpu0.toL2Bus.trans_dist::UpgradeReq 438453 # Transaction distribution
1326 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361903 # Transaction distribution
1327 system.cpu0.toL2Bus.trans_dist::UpgradeResp 524601 # Transaction distribution
1328 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution
1329 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution
1330 system.cpu0.toL2Bus.trans_dist::ReadExReq 1264261 # Transaction distribution
1331 system.cpu0.toL2Bus.trans_dist::ReadExResp 1203854 # Transaction distribution
1332 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5175708 # Transaction distribution
1333 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4797612 # Transaction distribution
1334 system.cpu0.toL2Bus.trans_dist::InvalidateReq 779730 # Transaction distribution
1335 system.cpu0.toL2Bus.trans_dist::InvalidateResp 774618 # Transaction distribution
1336 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15612584 # Packet count per connected master and slave (bytes)
1337 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18673898 # Packet count per connected master and slave (bytes)
1338 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 348811 # Packet count per connected master and slave (bytes)
1339 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 599734 # Packet count per connected master and slave (bytes)
1340 system.cpu0.toL2Bus.pkt_count::total 35235027 # Packet count per connected master and slave (bytes)
1341 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662612564 # Cumulative packet size per connected master and slave (bytes)
1342 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 703409885 # Cumulative packet size per connected master and slave (bytes)
1343 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328368 # Cumulative packet size per connected master and slave (bytes)
1344 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2198296 # Cumulative packet size per connected master and slave (bytes)
1345 system.cpu0.toL2Bus.pkt_size::total 1369549113 # Cumulative packet size per connected master and slave (bytes)
1346 system.cpu0.toL2Bus.snoops 6346450 # Total snoops (count)
1347 system.cpu0.toL2Bus.snoop_fanout::samples 18158816 # Request fanout histogram
1348 system.cpu0.toL2Bus.snoop_fanout::mean 0.116500 # Request fanout histogram
1349 system.cpu0.toL2Bus.snoop_fanout::stdev 0.320855 # Request fanout histogram
1350 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1351 system.cpu0.toL2Bus.snoop_fanout::0 16043491 88.35% 88.35% # Request fanout histogram
1352 system.cpu0.toL2Bus.snoop_fanout::1 2115144 11.65% 100.00% # Request fanout histogram
1353 system.cpu0.toL2Bus.snoop_fanout::2 181 0.00% 100.00% # Request fanout histogram
1354 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1355 system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1356 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1357 system.cpu0.toL2Bus.snoop_fanout::total 18158816 # Request fanout histogram
1358 system.cpu0.toL2Bus.reqLayer0.occupancy 22462112497 # Layer occupancy (ticks)
1359 system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1360 system.cpu0.toL2Bus.snoopLayer0.occupancy 223807892 # Layer occupancy (ticks)
1361 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1362 system.cpu0.toL2Bus.respLayer0.occupancy 7806687000 # Layer occupancy (ticks)
1363 system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1364 system.cpu0.toL2Bus.respLayer1.occupancy 8283648998 # Layer occupancy (ticks)
1365 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1366 system.cpu0.toL2Bus.respLayer2.occupancy 182765499 # Layer occupancy (ticks)
1367 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1368 system.cpu0.toL2Bus.respLayer3.occupancy 324947000 # Layer occupancy (ticks)
1369 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1370 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1371 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1372 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1373 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1374 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1375 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1376 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1377 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1378 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1379 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1380 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1381 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1382 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1383 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1384 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1385 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1386 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1387 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1388 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1389 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1390 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1391 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1392 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1393 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1394 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1395 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1396 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1397 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1398 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1399 system.cpu1.dtb.walker.walks 92112 # Table walker walks requested
1400 system.cpu1.dtb.walker.walksLong 92112 # Table walker walks initiated with long descriptors
1401 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7185 # Level at which table walker walks with long descriptors terminate
1402 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70441 # Level at which table walker walks with long descriptors terminate
1403 system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
1404 system.cpu1.dtb.walker.walkWaitTime::samples 92107 # Table walker wait (enqueue to first request) latency
1405 system.cpu1.dtb.walker.walkWaitTime::mean 0.086856 # Table walker wait (enqueue to first request) latency
1406 system.cpu1.dtb.walker.walkWaitTime::stdev 26.359895 # Table walker wait (enqueue to first request) latency
1407 system.cpu1.dtb.walker.walkWaitTime::0-511 92106 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1408 system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1409 system.cpu1.dtb.walker.walkWaitTime::total 92107 # Table walker wait (enqueue to first request) latency
1410 system.cpu1.dtb.walker.walkCompletionTime::samples 77631 # Table walker service (enqueue to completion) latency
1411 system.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397 # Table walker service (enqueue to completion) latency
1412 system.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713 # Table walker service (enqueue to completion) latency
1413 system.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740 # Table walker service (enqueue to completion) latency
1414 system.cpu1.dtb.walker.walkCompletionTime::0-65535 76846 98.99% 98.99% # Table walker service (enqueue to completion) latency
1415 system.cpu1.dtb.walker.walkCompletionTime::65536-131071 174 0.22% 99.21% # Table walker service (enqueue to completion) latency
1416 system.cpu1.dtb.walker.walkCompletionTime::131072-196607 527 0.68% 99.89% # Table walker service (enqueue to completion) latency
1417 system.cpu1.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.91% # Table walker service (enqueue to completion) latency
1418 system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.95% # Table walker service (enqueue to completion) latency
1419 system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
1420 system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.02% 99.99% # Table walker service (enqueue to completion) latency
1421 system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
1422 system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
1423 system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1424 system.cpu1.dtb.walker.walkCompletionTime::total 77631 # Table walker service (enqueue to completion) latency
1425 system.cpu1.dtb.walker.walksPending::samples -5456316576 # Table walker pending requests distribution
1426 system.cpu1.dtb.walker.walksPending::mean 0.616394 # Table walker pending requests distribution
1427 system.cpu1.dtb.walker.walksPending::stdev 0.486264 # Table walker pending requests distribution
1428 system.cpu1.dtb.walker.walksPending::0 -2093077220 38.36% 38.36% # Table walker pending requests distribution
1429 system.cpu1.dtb.walker.walksPending::1 -3363239356 61.64% 100.00% # Table walker pending requests distribution
1430 system.cpu1.dtb.walker.walksPending::total -5456316576 # Table walker pending requests distribution
1431 system.cpu1.dtb.walker.walkPageSizes::4K 70442 90.74% 90.74% # Table walker page sizes translated
1432 system.cpu1.dtb.walker.walkPageSizes::2M 7185 9.26% 100.00% # Table walker page sizes translated
1433 system.cpu1.dtb.walker.walkPageSizes::total 77627 # Table walker page sizes translated
1434 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92112 # Table walker requests started/completed, data/inst
1435 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1436 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92112 # Table walker requests started/completed, data/inst
1437 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77627 # Table walker requests started/completed, data/inst
1438 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1439 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77627 # Table walker requests started/completed, data/inst
1440 system.cpu1.dtb.walker.walkRequestOrigin::total 169739 # Table walker requests started/completed, data/inst
1441 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1442 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1443 system.cpu1.dtb.read_hits 76812549 # DTB read hits
1444 system.cpu1.dtb.read_misses 67403 # DTB read misses
1445 system.cpu1.dtb.write_hits 69811450 # DTB write hits
1446 system.cpu1.dtb.write_misses 24709 # DTB write misses
1447 system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1448 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1449 system.cpu1.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID
1450 system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
1451 system.cpu1.dtb.flush_entries 34729 # Number of entries that have been flushed from TLB
1452 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1453 system.cpu1.dtb.prefetch_faults 4304 # Number of TLB faults due to prefetch
1454 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1455 system.cpu1.dtb.perms_faults 9295 # Number of TLB faults due to permissions restrictions
1456 system.cpu1.dtb.read_accesses 76879952 # DTB read accesses
1457 system.cpu1.dtb.write_accesses 69836159 # DTB write accesses
1458 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1459 system.cpu1.dtb.hits 146623999 # DTB hits
1460 system.cpu1.dtb.misses 92112 # DTB misses
1461 system.cpu1.dtb.accesses 146716111 # DTB accesses
1462 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1463 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1464 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1465 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1466 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1467 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1468 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1469 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1470 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1471 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1472 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1473 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1474 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1475 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1476 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1477 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1478 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1479 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1480 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1481 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1482 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1483 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1484 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1485 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1486 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1487 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1488 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1489 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1490 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1491 system.cpu1.itb.walker.walks 54749 # Table walker walks requested
1492 system.cpu1.itb.walker.walksLong 54749 # Table walker walks initiated with long descriptors
1493 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 360 # Level at which table walker walks with long descriptors terminate
1494 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate
1495 system.cpu1.itb.walker.walkWaitTime::samples 54749 # Table walker wait (enqueue to first request) latency
1496 system.cpu1.itb.walker.walkWaitTime::0 54749 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1497 system.cpu1.itb.walker.walkWaitTime::total 54749 # Table walker wait (enqueue to first request) latency
1498 system.cpu1.itb.walker.walkCompletionTime::samples 49571 # Table walker service (enqueue to completion) latency
1499 system.cpu1.itb.walker.walkCompletionTime::mean 25509.592302 # Table walker service (enqueue to completion) latency
1500 system.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503 # Table walker service (enqueue to completion) latency
1501 system.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401 # Table walker service (enqueue to completion) latency
1502 system.cpu1.itb.walker.walkCompletionTime::0-65535 48865 98.58% 98.58% # Table walker service (enqueue to completion) latency
1503 system.cpu1.itb.walker.walkCompletionTime::65536-131071 34 0.07% 98.64% # Table walker service (enqueue to completion) latency
1504 system.cpu1.itb.walker.walkCompletionTime::131072-196607 581 1.17% 99.82% # Table walker service (enqueue to completion) latency
1505 system.cpu1.itb.walker.walkCompletionTime::196608-262143 14 0.03% 99.84% # Table walker service (enqueue to completion) latency
1506 system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.06% 99.90% # Table walker service (enqueue to completion) latency
1507 system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.94% # Table walker service (enqueue to completion) latency
1508 system.cpu1.itb.walker.walkCompletionTime::393216-458751 25 0.05% 99.99% # Table walker service (enqueue to completion) latency
1509 system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
1510 system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
1511 system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1512 system.cpu1.itb.walker.walkCompletionTime::total 49571 # Table walker service (enqueue to completion) latency
1513 system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution
1514 system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution
1515 system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution
1516 system.cpu1.itb.walker.walkPageSizes::4K 49211 99.27% 99.27% # Table walker page sizes translated
1517 system.cpu1.itb.walker.walkPageSizes::2M 360 0.73% 100.00% # Table walker page sizes translated
1518 system.cpu1.itb.walker.walkPageSizes::total 49571 # Table walker page sizes translated
1519 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1520 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54749 # Table walker requests started/completed, data/inst
1521 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54749 # Table walker requests started/completed, data/inst
1522 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1523 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49571 # Table walker requests started/completed, data/inst
1524 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49571 # Table walker requests started/completed, data/inst
1525 system.cpu1.itb.walker.walkRequestOrigin::total 104320 # Table walker requests started/completed, data/inst
1526 system.cpu1.itb.inst_hits 406021553 # ITB inst hits
1527 system.cpu1.itb.inst_misses 54749 # ITB inst misses
1528 system.cpu1.itb.read_hits 0 # DTB read hits
1529 system.cpu1.itb.read_misses 0 # DTB read misses
1530 system.cpu1.itb.write_hits 0 # DTB write hits
1531 system.cpu1.itb.write_misses 0 # DTB write misses
1532 system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1533 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1534 system.cpu1.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID
1535 system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
1536 system.cpu1.itb.flush_entries 24319 # Number of entries that have been flushed from TLB
1537 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1538 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1539 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1540 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1541 system.cpu1.itb.read_accesses 0 # DTB read accesses
1542 system.cpu1.itb.write_accesses 0 # DTB write accesses
1543 system.cpu1.itb.inst_accesses 406076302 # ITB inst accesses
1544 system.cpu1.itb.hits 406021553 # DTB hits
1545 system.cpu1.itb.misses 54749 # DTB misses
1546 system.cpu1.itb.accesses 406076302 # DTB accesses
1547 system.cpu1.numCycles 95205135925 # number of cpu cycles simulated
1548 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1549 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1550 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1551 system.cpu1.kern.inst.quiesce 14029 # number of quiesce instructions executed
1552 system.cpu1.committedInsts 405727323 # Number of instructions committed
1553 system.cpu1.committedOps 478325144 # Number of ops (including micro ops) committed
1554 system.cpu1.num_int_alu_accesses 439907771 # Number of integer alu accesses
1555 system.cpu1.num_fp_alu_accesses 446670 # Number of float alu accesses
1556 system.cpu1.num_func_calls 24605699 # number of times a function call or return occured
1557 system.cpu1.num_conditional_control_insts 61596178 # number of instructions that are conditional controls
1558 system.cpu1.num_int_insts 439907771 # number of integer instructions
1559 system.cpu1.num_fp_insts 446670 # number of float instructions
1560 system.cpu1.num_int_register_reads 637924838 # number of times the integer registers were read
1561 system.cpu1.num_int_register_writes 348926241 # number of times the integer registers were written
1562 system.cpu1.num_fp_register_reads 708486 # number of times the floating registers were read
1563 system.cpu1.num_fp_register_writes 403472 # number of times the floating registers were written
1564 system.cpu1.num_cc_register_reads 104772444 # number of times the CC registers were read
1565 system.cpu1.num_cc_register_writes 104573998 # number of times the CC registers were written
1566 system.cpu1.num_mem_refs 146614371 # number of memory refs
1567 system.cpu1.num_load_insts 76808885 # Number of load instructions
1568 system.cpu1.num_store_insts 69805486 # Number of store instructions
1569 system.cpu1.num_idle_cycles 94195407146.248016 # Number of idle cycles
1570 system.cpu1.num_busy_cycles 1009728778.751979 # Number of busy cycles
1571 system.cpu1.not_idle_fraction 0.010606 # Percentage of non-idle cycles
1572 system.cpu1.idle_fraction 0.989394 # Percentage of idle cycles
1573 system.cpu1.Branches 90553045 # Number of branches fetched
1574 system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
1575 system.cpu1.op_class::IntAlu 330876771 69.13% 69.13% # Class of executed instruction
1576 system.cpu1.op_class::IntMult 1002715 0.21% 69.34% # Class of executed instruction
1577 system.cpu1.op_class::IntDiv 57816 0.01% 69.35% # Class of executed instruction
1578 system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction
1579 system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction
1580 system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction
1581 system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction
1582 system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction
1583 system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction
1584 system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction
1585 system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction
1586 system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction
1587 system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction
1588 system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction
1589 system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction
1590 system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction
1591 system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction
1592 system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction
1593 system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction
1594 system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction
1595 system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction
1596 system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction
1597 system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction
1598 system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction
1599 system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction
1600 system.cpu1.op_class::SimdFloatMisc 67767 0.01% 69.37% # Class of executed instruction
1601 system.cpu1.op_class::SimdFloatMult 0 0.00% 69.37% # Class of executed instruction
1602 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.37% # Class of executed instruction
1603 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.37% # Class of executed instruction
1604 system.cpu1.op_class::MemRead 76808885 16.05% 85.42% # Class of executed instruction
1605 system.cpu1.op_class::MemWrite 69805486 14.58% 100.00% # Class of executed instruction
1606 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1607 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1608 system.cpu1.op_class::total 478619483 # Class of executed instruction
1609 system.cpu1.dcache.tags.replacements 4731492 # number of replacements
1610 system.cpu1.dcache.tags.tagsinuse 440.215275 # Cycle average of tags in use
1611 system.cpu1.dcache.tags.total_refs 141682703 # Total number of references to valid blocks.
1612 system.cpu1.dcache.tags.sampled_refs 4732003 # Sample count of references to valid blocks.
1613 system.cpu1.dcache.tags.avg_refs 29.941381 # Average number of references to valid blocks.
1614 system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit.
1615 system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.215275 # Average occupied blocks per requestor
1616 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.859795 # Average percentage of cache occupancy
1617 system.cpu1.dcache.tags.occ_percent::total 0.859795 # Average percentage of cache occupancy
1618 system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1619 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
1620 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id
1621 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
1622 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1623 system.cpu1.dcache.tags.tag_accesses 297963795 # Number of tag accesses
1624 system.cpu1.dcache.tags.data_accesses 297963795 # Number of data accesses
1625 system.cpu1.dcache.ReadReq_hits::cpu1.data 71617652 # number of ReadReq hits
1626 system.cpu1.dcache.ReadReq_hits::total 71617652 # number of ReadReq hits
1627 system.cpu1.dcache.WriteReq_hits::cpu1.data 66171444 # number of WriteReq hits
1628 system.cpu1.dcache.WriteReq_hits::total 66171444 # number of WriteReq hits
1629 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174206 # number of SoftPFReq hits
1630 system.cpu1.dcache.SoftPFReq_hits::total 174206 # number of SoftPFReq hits
1631 system.cpu1.dcache.WriteLineReq_hits::cpu1.data 185116 # number of WriteLineReq hits
1632 system.cpu1.dcache.WriteLineReq_hits::total 185116 # number of WriteLineReq hits
1633 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1590024 # number of LoadLockedReq hits
1634 system.cpu1.dcache.LoadLockedReq_hits::total 1590024 # number of LoadLockedReq hits
1635 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1548743 # number of StoreCondReq hits
1636 system.cpu1.dcache.StoreCondReq_hits::total 1548743 # number of StoreCondReq hits
1637 system.cpu1.dcache.demand_hits::cpu1.data 137789096 # number of demand (read+write) hits
1638 system.cpu1.dcache.demand_hits::total 137789096 # number of demand (read+write) hits
1639 system.cpu1.dcache.overall_hits::cpu1.data 137963302 # number of overall hits
1640 system.cpu1.dcache.overall_hits::total 137963302 # number of overall hits
1641 system.cpu1.dcache.ReadReq_misses::cpu1.data 2694357 # number of ReadReq misses
1642 system.cpu1.dcache.ReadReq_misses::total 2694357 # number of ReadReq misses
1643 system.cpu1.dcache.WriteReq_misses::cpu1.data 1213090 # number of WriteReq misses
1644 system.cpu1.dcache.WriteReq_misses::total 1213090 # number of WriteReq misses
1645 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 558664 # number of SoftPFReq misses
1646 system.cpu1.dcache.SoftPFReq_misses::total 558664 # number of SoftPFReq misses
1647 system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466794 # number of WriteLineReq misses
1648 system.cpu1.dcache.WriteLineReq_misses::total 466794 # number of WriteLineReq misses
1649 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 154053 # number of LoadLockedReq misses
1650 system.cpu1.dcache.LoadLockedReq_misses::total 154053 # number of LoadLockedReq misses
1651 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194127 # number of StoreCondReq misses
1652 system.cpu1.dcache.StoreCondReq_misses::total 194127 # number of StoreCondReq misses
1653 system.cpu1.dcache.demand_misses::cpu1.data 3907447 # number of demand (read+write) misses
1654 system.cpu1.dcache.demand_misses::total 3907447 # number of demand (read+write) misses
1655 system.cpu1.dcache.overall_misses::cpu1.data 4466111 # number of overall misses
1656 system.cpu1.dcache.overall_misses::total 4466111 # number of overall misses
1657 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40157954500 # number of ReadReq miss cycles
1658 system.cpu1.dcache.ReadReq_miss_latency::total 40157954500 # number of ReadReq miss cycles
1659 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28157091500 # number of WriteReq miss cycles
1660 system.cpu1.dcache.WriteReq_miss_latency::total 28157091500 # number of WriteReq miss cycles
1661 system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20750751000 # number of WriteLineReq miss cycles
1662 system.cpu1.dcache.WriteLineReq_miss_latency::total 20750751000 # number of WriteLineReq miss cycles
1663 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2380134500 # number of LoadLockedReq miss cycles
1664 system.cpu1.dcache.LoadLockedReq_miss_latency::total 2380134500 # number of LoadLockedReq miss cycles
1665 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5345117000 # number of StoreCondReq miss cycles
1666 system.cpu1.dcache.StoreCondReq_miss_latency::total 5345117000 # number of StoreCondReq miss cycles
1667 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6929500 # number of StoreCondFailReq miss cycles
1668 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6929500 # number of StoreCondFailReq miss cycles
1669 system.cpu1.dcache.demand_miss_latency::cpu1.data 68315046000 # number of demand (read+write) miss cycles
1670 system.cpu1.dcache.demand_miss_latency::total 68315046000 # number of demand (read+write) miss cycles
1671 system.cpu1.dcache.overall_miss_latency::cpu1.data 68315046000 # number of overall miss cycles
1672 system.cpu1.dcache.overall_miss_latency::total 68315046000 # number of overall miss cycles
1673 system.cpu1.dcache.ReadReq_accesses::cpu1.data 74312009 # number of ReadReq accesses(hits+misses)
1674 system.cpu1.dcache.ReadReq_accesses::total 74312009 # number of ReadReq accesses(hits+misses)
1675 system.cpu1.dcache.WriteReq_accesses::cpu1.data 67384534 # number of WriteReq accesses(hits+misses)
1676 system.cpu1.dcache.WriteReq_accesses::total 67384534 # number of WriteReq accesses(hits+misses)
1677 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 732870 # number of SoftPFReq accesses(hits+misses)
1678 system.cpu1.dcache.SoftPFReq_accesses::total 732870 # number of SoftPFReq accesses(hits+misses)
1679 system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 651910 # number of WriteLineReq accesses(hits+misses)
1680 system.cpu1.dcache.WriteLineReq_accesses::total 651910 # number of WriteLineReq accesses(hits+misses)
1681 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1744077 # number of LoadLockedReq accesses(hits+misses)
1682 system.cpu1.dcache.LoadLockedReq_accesses::total 1744077 # number of LoadLockedReq accesses(hits+misses)
1683 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1742870 # number of StoreCondReq accesses(hits+misses)
1684 system.cpu1.dcache.StoreCondReq_accesses::total 1742870 # number of StoreCondReq accesses(hits+misses)
1685 system.cpu1.dcache.demand_accesses::cpu1.data 141696543 # number of demand (read+write) accesses
1686 system.cpu1.dcache.demand_accesses::total 141696543 # number of demand (read+write) accesses
1687 system.cpu1.dcache.overall_accesses::cpu1.data 142429413 # number of overall (read+write) accesses
1688 system.cpu1.dcache.overall_accesses::total 142429413 # number of overall (read+write) accesses
1689 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036257 # miss rate for ReadReq accesses
1690 system.cpu1.dcache.ReadReq_miss_rate::total 0.036257 # miss rate for ReadReq accesses
1691 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018002 # miss rate for WriteReq accesses
1692 system.cpu1.dcache.WriteReq_miss_rate::total 0.018002 # miss rate for WriteReq accesses
1693 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762296 # miss rate for SoftPFReq accesses
1694 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762296 # miss rate for SoftPFReq accesses
1695 system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716041 # miss rate for WriteLineReq accesses
1696 system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716041 # miss rate for WriteLineReq accesses
1697 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088329 # miss rate for LoadLockedReq accesses
1698 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088329 # miss rate for LoadLockedReq accesses
1699 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111384 # miss rate for StoreCondReq accesses
1700 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111384 # miss rate for StoreCondReq accesses
1701 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027576 # miss rate for demand accesses
1702 system.cpu1.dcache.demand_miss_rate::total 0.027576 # miss rate for demand accesses
1703 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031357 # miss rate for overall accesses
1704 system.cpu1.dcache.overall_miss_rate::total 0.031357 # miss rate for overall accesses
1705 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817 # average ReadReq miss latency
1706 system.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817 # average ReadReq miss latency
1707 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057 # average WriteReq miss latency
1708 system.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057 # average WriteReq miss latency
1709 system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473 # average WriteLineReq miss latency
1710 system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473 # average WriteLineReq miss latency
1711 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588 # average LoadLockedReq miss latency
1712 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588 # average LoadLockedReq miss latency
1713 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568 # average StoreCondReq miss latency
1714 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568 # average StoreCondReq miss latency
1715 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1716 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1717 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17483.294335 # average overall miss latency
1718 system.cpu1.dcache.demand_avg_miss_latency::total 17483.294335 # average overall miss latency
1719 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.316191 # average overall miss latency
1720 system.cpu1.dcache.overall_avg_miss_latency::total 15296.316191 # average overall miss latency
1721 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1722 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1723 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1724 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1725 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1726 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1727 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1728 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1729 system.cpu1.dcache.writebacks::writebacks 4731492 # number of writebacks
1730 system.cpu1.dcache.writebacks::total 4731492 # number of writebacks
1731 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13909 # number of ReadReq MSHR hits
1732 system.cpu1.dcache.ReadReq_mshr_hits::total 13909 # number of ReadReq MSHR hits
1733 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 323 # number of WriteReq MSHR hits
1734 system.cpu1.dcache.WriteReq_mshr_hits::total 323 # number of WriteReq MSHR hits
1735 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44168 # number of LoadLockedReq MSHR hits
1736 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44168 # number of LoadLockedReq MSHR hits
1737 system.cpu1.dcache.demand_mshr_hits::cpu1.data 14232 # number of demand (read+write) MSHR hits
1738 system.cpu1.dcache.demand_mshr_hits::total 14232 # number of demand (read+write) MSHR hits
1739 system.cpu1.dcache.overall_mshr_hits::cpu1.data 14232 # number of overall MSHR hits
1740 system.cpu1.dcache.overall_mshr_hits::total 14232 # number of overall MSHR hits
1741 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2680448 # number of ReadReq MSHR misses
1742 system.cpu1.dcache.ReadReq_mshr_misses::total 2680448 # number of ReadReq MSHR misses
1743 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1212767 # number of WriteReq MSHR misses
1744 system.cpu1.dcache.WriteReq_mshr_misses::total 1212767 # number of WriteReq MSHR misses
1745 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 558664 # number of SoftPFReq MSHR misses
1746 system.cpu1.dcache.SoftPFReq_mshr_misses::total 558664 # number of SoftPFReq MSHR misses
1747 system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466794 # number of WriteLineReq MSHR misses
1748 system.cpu1.dcache.WriteLineReq_mshr_misses::total 466794 # number of WriteLineReq MSHR misses
1749 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109885 # number of LoadLockedReq MSHR misses
1750 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109885 # number of LoadLockedReq MSHR misses
1751 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194127 # number of StoreCondReq MSHR misses
1752 system.cpu1.dcache.StoreCondReq_mshr_misses::total 194127 # number of StoreCondReq MSHR misses
1753 system.cpu1.dcache.demand_mshr_misses::cpu1.data 3893215 # number of demand (read+write) MSHR misses
1754 system.cpu1.dcache.demand_mshr_misses::total 3893215 # number of demand (read+write) MSHR misses
1755 system.cpu1.dcache.overall_mshr_misses::cpu1.data 4451879 # number of overall MSHR misses
1756 system.cpu1.dcache.overall_mshr_misses::total 4451879 # number of overall MSHR misses
1757 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable
1758 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23611 # number of ReadReq MSHR uncacheable
1759 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable
1760 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable
1761 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses
1762 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46231 # number of overall MSHR uncacheable misses
1763 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36382655000 # number of ReadReq MSHR miss cycles
1764 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36382655000 # number of ReadReq MSHR miss cycles
1765 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26928760500 # number of WriteReq MSHR miss cycles
1766 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26928760500 # number of WriteReq MSHR miss cycles
1767 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12609688500 # number of SoftPFReq MSHR miss cycles
1768 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12609688500 # number of SoftPFReq MSHR miss cycles
1769 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20283957000 # number of WriteLineReq MSHR miss cycles
1770 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20283957000 # number of WriteLineReq MSHR miss cycles
1771 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1540230500 # number of LoadLockedReq MSHR miss cycles
1772 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1540230500 # number of LoadLockedReq MSHR miss cycles
1773 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5151064000 # number of StoreCondReq MSHR miss cycles
1774 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5151064000 # number of StoreCondReq MSHR miss cycles
1775 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6855500 # number of StoreCondFailReq MSHR miss cycles
1776 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6855500 # number of StoreCondFailReq MSHR miss cycles
1777 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63311415500 # number of demand (read+write) MSHR miss cycles
1778 system.cpu1.dcache.demand_mshr_miss_latency::total 63311415500 # number of demand (read+write) MSHR miss cycles
1779 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75921104000 # number of overall MSHR miss cycles
1780 system.cpu1.dcache.overall_mshr_miss_latency::total 75921104000 # number of overall MSHR miss cycles
1781 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4287453000 # number of ReadReq MSHR uncacheable cycles
1782 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4287453000 # number of ReadReq MSHR uncacheable cycles
1783 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4160988000 # number of WriteReq MSHR uncacheable cycles
1784 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4160988000 # number of WriteReq MSHR uncacheable cycles
1785 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8448441000 # number of overall MSHR uncacheable cycles
1786 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8448441000 # number of overall MSHR uncacheable cycles
1787 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036070 # mshr miss rate for ReadReq accesses
1788 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036070 # mshr miss rate for ReadReq accesses
1789 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017998 # mshr miss rate for WriteReq accesses
1790 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017998 # mshr miss rate for WriteReq accesses
1791 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762296 # mshr miss rate for SoftPFReq accesses
1792 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762296 # mshr miss rate for SoftPFReq accesses
1793 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716041 # mshr miss rate for WriteLineReq accesses
1794 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716041 # mshr miss rate for WriteLineReq accesses
1795 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063005 # mshr miss rate for LoadLockedReq accesses
1796 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063005 # mshr miss rate for LoadLockedReq accesses
1797 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111384 # mshr miss rate for StoreCondReq accesses
1798 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111384 # mshr miss rate for StoreCondReq accesses
1799 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027476 # mshr miss rate for demand accesses
1800 system.cpu1.dcache.demand_mshr_miss_rate::total 0.027476 # mshr miss rate for demand accesses
1801 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031257 # mshr miss rate for overall accesses
1802 system.cpu1.dcache.overall_mshr_miss_rate::total 0.031257 # mshr miss rate for overall accesses
1803 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560 # average ReadReq mshr miss latency
1804 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560 # average ReadReq mshr miss latency
1805 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465 # average WriteReq mshr miss latency
1806 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465 # average WriteReq mshr miss latency
1807 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206 # average SoftPFReq mshr miss latency
1808 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206 # average SoftPFReq mshr miss latency
1809 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473 # average WriteLineReq mshr miss latency
1810 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473 # average WriteLineReq mshr miss latency
1811 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329 # average LoadLockedReq mshr miss latency
1812 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329 # average LoadLockedReq mshr miss latency
1813 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762 # average StoreCondReq mshr miss latency
1814 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762 # average StoreCondReq mshr miss latency
1815 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1816 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1817 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971 # average overall mshr miss latency
1818 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971 # average overall mshr miss latency
1819 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17053.721361 # average overall mshr miss latency
1820 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17053.721361 # average overall mshr miss latency
1821 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181587.099233 # average ReadReq mshr uncacheable latency
1822 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181587.099233 # average ReadReq mshr uncacheable latency
1823 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183951.724138 # average WriteReq mshr uncacheable latency
1824 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183951.724138 # average WriteReq mshr uncacheable latency
1825 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182744.067833 # average overall mshr uncacheable latency
1826 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182744.067833 # average overall mshr uncacheable latency
1827 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1828 system.cpu1.icache.tags.replacements 4831573 # number of replacements
1829 system.cpu1.icache.tags.tagsinuse 495.969883 # Cycle average of tags in use
1830 system.cpu1.icache.tags.total_refs 401189463 # Total number of references to valid blocks.
1831 system.cpu1.icache.tags.sampled_refs 4832085 # Sample count of references to valid blocks.
1832 system.cpu1.icache.tags.avg_refs 83.026160 # Average number of references to valid blocks.
1833 system.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit.
1834 system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.969883 # Average occupied blocks per requestor
1835 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968691 # Average percentage of cache occupancy
1836 system.cpu1.icache.tags.occ_percent::total 0.968691 # Average percentage of cache occupancy
1837 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1838 system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
1839 system.cpu1.icache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id
1840 system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
1841 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1842 system.cpu1.icache.tags.tag_accesses 816875196 # Number of tag accesses
1843 system.cpu1.icache.tags.data_accesses 816875196 # Number of data accesses
1844 system.cpu1.icache.ReadReq_hits::cpu1.inst 401189463 # number of ReadReq hits
1845 system.cpu1.icache.ReadReq_hits::total 401189463 # number of ReadReq hits
1846 system.cpu1.icache.demand_hits::cpu1.inst 401189463 # number of demand (read+write) hits
1847 system.cpu1.icache.demand_hits::total 401189463 # number of demand (read+write) hits
1848 system.cpu1.icache.overall_hits::cpu1.inst 401189463 # number of overall hits
1849 system.cpu1.icache.overall_hits::total 401189463 # number of overall hits
1850 system.cpu1.icache.ReadReq_misses::cpu1.inst 4832090 # number of ReadReq misses
1851 system.cpu1.icache.ReadReq_misses::total 4832090 # number of ReadReq misses
1852 system.cpu1.icache.demand_misses::cpu1.inst 4832090 # number of demand (read+write) misses
1853 system.cpu1.icache.demand_misses::total 4832090 # number of demand (read+write) misses
1854 system.cpu1.icache.overall_misses::cpu1.inst 4832090 # number of overall misses
1855 system.cpu1.icache.overall_misses::total 4832090 # number of overall misses
1856 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52408341000 # number of ReadReq miss cycles
1857 system.cpu1.icache.ReadReq_miss_latency::total 52408341000 # number of ReadReq miss cycles
1858 system.cpu1.icache.demand_miss_latency::cpu1.inst 52408341000 # number of demand (read+write) miss cycles
1859 system.cpu1.icache.demand_miss_latency::total 52408341000 # number of demand (read+write) miss cycles
1860 system.cpu1.icache.overall_miss_latency::cpu1.inst 52408341000 # number of overall miss cycles
1861 system.cpu1.icache.overall_miss_latency::total 52408341000 # number of overall miss cycles
1862 system.cpu1.icache.ReadReq_accesses::cpu1.inst 406021553 # number of ReadReq accesses(hits+misses)
1863 system.cpu1.icache.ReadReq_accesses::total 406021553 # number of ReadReq accesses(hits+misses)
1864 system.cpu1.icache.demand_accesses::cpu1.inst 406021553 # number of demand (read+write) accesses
1865 system.cpu1.icache.demand_accesses::total 406021553 # number of demand (read+write) accesses
1866 system.cpu1.icache.overall_accesses::cpu1.inst 406021553 # number of overall (read+write) accesses
1867 system.cpu1.icache.overall_accesses::total 406021553 # number of overall (read+write) accesses
1868 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011901 # miss rate for ReadReq accesses
1869 system.cpu1.icache.ReadReq_miss_rate::total 0.011901 # miss rate for ReadReq accesses
1870 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011901 # miss rate for demand accesses
1871 system.cpu1.icache.demand_miss_rate::total 0.011901 # miss rate for demand accesses
1872 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011901 # miss rate for overall accesses
1873 system.cpu1.icache.overall_miss_rate::total 0.011901 # miss rate for overall accesses
1874 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047 # average ReadReq miss latency
1875 system.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047 # average ReadReq miss latency
1876 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency
1877 system.cpu1.icache.demand_avg_miss_latency::total 10845.895047 # average overall miss latency
1878 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency
1879 system.cpu1.icache.overall_avg_miss_latency::total 10845.895047 # average overall miss latency
1880 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1881 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1882 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1883 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1884 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1885 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1886 system.cpu1.icache.fast_writes 0 # number of fast writes performed
1887 system.cpu1.icache.cache_copies 0 # number of cache copies performed
1888 system.cpu1.icache.writebacks::writebacks 4831573 # number of writebacks
1889 system.cpu1.icache.writebacks::total 4831573 # number of writebacks
1890 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4832090 # number of ReadReq MSHR misses
1891 system.cpu1.icache.ReadReq_mshr_misses::total 4832090 # number of ReadReq MSHR misses
1892 system.cpu1.icache.demand_mshr_misses::cpu1.inst 4832090 # number of demand (read+write) MSHR misses
1893 system.cpu1.icache.demand_mshr_misses::total 4832090 # number of demand (read+write) MSHR misses
1894 system.cpu1.icache.overall_mshr_misses::cpu1.inst 4832090 # number of overall MSHR misses
1895 system.cpu1.icache.overall_mshr_misses::total 4832090 # number of overall MSHR misses
1896 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
1897 system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
1898 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
1899 system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
1900 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49992296000 # number of ReadReq MSHR miss cycles
1901 system.cpu1.icache.ReadReq_mshr_miss_latency::total 49992296000 # number of ReadReq MSHR miss cycles
1902 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49992296000 # number of demand (read+write) MSHR miss cycles
1903 system.cpu1.icache.demand_mshr_miss_latency::total 49992296000 # number of demand (read+write) MSHR miss cycles
1904 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49992296000 # number of overall MSHR miss cycles
1905 system.cpu1.icache.overall_mshr_miss_latency::total 49992296000 # number of overall MSHR miss cycles
1906 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles
1907 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles
1908 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles
1909 system.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles
1910 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for ReadReq accesses
1911 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011901 # mshr miss rate for ReadReq accesses
1912 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for demand accesses
1913 system.cpu1.icache.demand_mshr_miss_rate::total 0.011901 # mshr miss rate for demand accesses
1914 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for overall accesses
1915 system.cpu1.icache.overall_mshr_miss_rate::total 0.011901 # mshr miss rate for overall accesses
1916 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average ReadReq mshr miss latency
1917 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10345.895047 # average ReadReq mshr miss latency
1918 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency
1919 system.cpu1.icache.demand_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency
1920 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency
1921 system.cpu1.icache.overall_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency
1922 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency
1923 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency
1924 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency
1925 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency
1926 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1927 system.cpu1.l2cache.prefetcher.num_hwpf_issued 6380299 # number of hwpf issued
1928 system.cpu1.l2cache.prefetcher.pfIdentified 6380331 # number of prefetch candidates identified
1929 system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue
1930 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1931 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1932 system.cpu1.l2cache.prefetcher.pfSpanPage 802101 # number of prefetches not generated due to page crossing
1933 system.cpu1.l2cache.tags.replacements 1778912 # number of replacements
1934 system.cpu1.l2cache.tags.tagsinuse 13269.685648 # Cycle average of tags in use
1935 system.cpu1.l2cache.tags.total_refs 14051315 # Total number of references to valid blocks.
1936 system.cpu1.l2cache.tags.sampled_refs 1794926 # Sample count of references to valid blocks.
1937 system.cpu1.l2cache.tags.avg_refs 7.828353 # Average number of references to valid blocks.
1938 system.cpu1.l2cache.tags.warmup_cycle 10084696105000 # Cycle when the warmup percentage was hit.
1939 system.cpu1.l2cache.tags.occ_blocks::writebacks 12213.003078 # Average occupied blocks per requestor
1940 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.894206 # Average occupied blocks per requestor
1941 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 34.650770 # Average occupied blocks per requestor
1942 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 988.137594 # Average occupied blocks per requestor
1943 system.cpu1.l2cache.tags.occ_percent::writebacks 0.745423 # Average percentage of cache occupancy
1944 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002069 # Average percentage of cache occupancy
1945 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002115 # Average percentage of cache occupancy
1946 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060311 # Average percentage of cache occupancy
1947 system.cpu1.l2cache.tags.occ_percent::total 0.809917 # Average percentage of cache occupancy
1948 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1110 # Occupied blocks per task id
1949 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id
1950 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14818 # Occupied blocks per task id
1951 system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
1952 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id
1953 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 669 # Occupied blocks per task id
1954 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id
1955 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
1956 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 72 # Occupied blocks per task id
1957 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
1958 system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
1959 system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 972 # Occupied blocks per task id
1960 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4464 # Occupied blocks per task id
1961 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8114 # Occupied blocks per task id
1962 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1200 # Occupied blocks per task id
1963 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067749 # Percentage of cache occupancy per task id
1964 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id
1965 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.904419 # Percentage of cache occupancy per task id
1966 system.cpu1.l2cache.tags.tag_accesses 324313053 # Number of tag accesses
1967 system.cpu1.l2cache.tags.data_accesses 324313053 # Number of data accesses
1968 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 211999 # number of ReadReq hits
1969 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140481 # number of ReadReq hits
1970 system.cpu1.l2cache.ReadReq_hits::total 352480 # number of ReadReq hits
1971 system.cpu1.l2cache.WritebackDirty_hits::writebacks 2988895 # number of WritebackDirty hits
1972 system.cpu1.l2cache.WritebackDirty_hits::total 2988895 # number of WritebackDirty hits
1973 system.cpu1.l2cache.WritebackClean_hits::writebacks 6573071 # number of WritebackClean hits
1974 system.cpu1.l2cache.WritebackClean_hits::total 6573071 # number of WritebackClean hits
1975 system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 239 # number of UpgradeReq hits
1976 system.cpu1.l2cache.UpgradeReq_hits::total 239 # number of UpgradeReq hits
1977 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 778234 # number of ReadExReq hits
1978 system.cpu1.l2cache.ReadExReq_hits::total 778234 # number of ReadExReq hits
1979 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4410501 # number of ReadCleanReq hits
1980 system.cpu1.l2cache.ReadCleanReq_hits::total 4410501 # number of ReadCleanReq hits
1981 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2517428 # number of ReadSharedReq hits
1982 system.cpu1.l2cache.ReadSharedReq_hits::total 2517428 # number of ReadSharedReq hits
1983 system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200602 # number of InvalidateReq hits
1984 system.cpu1.l2cache.InvalidateReq_hits::total 200602 # number of InvalidateReq hits
1985 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 211999 # number of demand (read+write) hits
1986 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140481 # number of demand (read+write) hits
1987 system.cpu1.l2cache.demand_hits::cpu1.inst 4410501 # number of demand (read+write) hits
1988 system.cpu1.l2cache.demand_hits::cpu1.data 3295662 # number of demand (read+write) hits
1989 system.cpu1.l2cache.demand_hits::total 8058643 # number of demand (read+write) hits
1990 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 211999 # number of overall hits
1991 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140481 # number of overall hits
1992 system.cpu1.l2cache.overall_hits::cpu1.inst 4410501 # number of overall hits
1993 system.cpu1.l2cache.overall_hits::cpu1.data 3295662 # number of overall hits
1994 system.cpu1.l2cache.overall_hits::total 8058643 # number of overall hits
1995 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9285 # number of ReadReq misses
1996 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7506 # number of ReadReq misses
1997 system.cpu1.l2cache.ReadReq_misses::total 16791 # number of ReadReq misses
1998 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 201343 # number of UpgradeReq misses
1999 system.cpu1.l2cache.UpgradeReq_misses::total 201343 # number of UpgradeReq misses
2000 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194101 # number of SCUpgradeReq misses
2001 system.cpu1.l2cache.SCUpgradeReq_misses::total 194101 # number of SCUpgradeReq misses
2002 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 26 # number of SCUpgradeFailReq misses
2003 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 26 # number of SCUpgradeFailReq misses
2004 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235513 # number of ReadExReq misses
2005 system.cpu1.l2cache.ReadExReq_misses::total 235513 # number of ReadExReq misses
2006 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 421589 # number of ReadCleanReq misses
2007 system.cpu1.l2cache.ReadCleanReq_misses::total 421589 # number of ReadCleanReq misses
2008 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 831569 # number of ReadSharedReq misses
2009 system.cpu1.l2cache.ReadSharedReq_misses::total 831569 # number of ReadSharedReq misses
2010 system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263822 # number of InvalidateReq misses
2011 system.cpu1.l2cache.InvalidateReq_misses::total 263822 # number of InvalidateReq misses
2012 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9285 # number of demand (read+write) misses
2013 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7506 # number of demand (read+write) misses
2014 system.cpu1.l2cache.demand_misses::cpu1.inst 421589 # number of demand (read+write) misses
2015 system.cpu1.l2cache.demand_misses::cpu1.data 1067082 # number of demand (read+write) misses
2016 system.cpu1.l2cache.demand_misses::total 1505462 # number of demand (read+write) misses
2017 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9285 # number of overall misses
2018 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7506 # number of overall misses
2019 system.cpu1.l2cache.overall_misses::cpu1.inst 421589 # number of overall misses
2020 system.cpu1.l2cache.overall_misses::cpu1.data 1067082 # number of overall misses
2021 system.cpu1.l2cache.overall_misses::total 1505462 # number of overall misses
2022 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 349092500 # number of ReadReq miss cycles
2023 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 301051000 # number of ReadReq miss cycles
2024 system.cpu1.l2cache.ReadReq_miss_latency::total 650143500 # number of ReadReq miss cycles
2025 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3162483500 # number of UpgradeReq miss cycles
2026 system.cpu1.l2cache.UpgradeReq_miss_latency::total 3162483500 # number of UpgradeReq miss cycles
2027 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1860693500 # number of SCUpgradeReq miss cycles
2028 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1860693500 # number of SCUpgradeReq miss cycles
2029 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6744500 # number of SCUpgradeFailReq miss cycles
2030 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6744500 # number of SCUpgradeFailReq miss cycles
2031 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12440298999 # number of ReadExReq miss cycles
2032 system.cpu1.l2cache.ReadExReq_miss_latency::total 12440298999 # number of ReadExReq miss cycles
2033 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16234081000 # number of ReadCleanReq miss cycles
2034 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16234081000 # number of ReadCleanReq miss cycles
2035 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29105216000 # number of ReadSharedReq miss cycles
2036 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29105216000 # number of ReadSharedReq miss cycles
2037 system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18219271500 # number of InvalidateReq miss cycles
2038 system.cpu1.l2cache.InvalidateReq_miss_latency::total 18219271500 # number of InvalidateReq miss cycles
2039 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 349092500 # number of demand (read+write) miss cycles
2040 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 301051000 # number of demand (read+write) miss cycles
2041 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16234081000 # number of demand (read+write) miss cycles
2042 system.cpu1.l2cache.demand_miss_latency::cpu1.data 41545514999 # number of demand (read+write) miss cycles
2043 system.cpu1.l2cache.demand_miss_latency::total 58429739499 # number of demand (read+write) miss cycles
2044 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 349092500 # number of overall miss cycles
2045 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 301051000 # number of overall miss cycles
2046 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16234081000 # number of overall miss cycles
2047 system.cpu1.l2cache.overall_miss_latency::cpu1.data 41545514999 # number of overall miss cycles
2048 system.cpu1.l2cache.overall_miss_latency::total 58429739499 # number of overall miss cycles
2049 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 221284 # number of ReadReq accesses(hits+misses)
2050 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 147987 # number of ReadReq accesses(hits+misses)
2051 system.cpu1.l2cache.ReadReq_accesses::total 369271 # number of ReadReq accesses(hits+misses)
2052 system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2988895 # number of WritebackDirty accesses(hits+misses)
2053 system.cpu1.l2cache.WritebackDirty_accesses::total 2988895 # number of WritebackDirty accesses(hits+misses)
2054 system.cpu1.l2cache.WritebackClean_accesses::writebacks 6573071 # number of WritebackClean accesses(hits+misses)
2055 system.cpu1.l2cache.WritebackClean_accesses::total 6573071 # number of WritebackClean accesses(hits+misses)
2056 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 201582 # number of UpgradeReq accesses(hits+misses)
2057 system.cpu1.l2cache.UpgradeReq_accesses::total 201582 # number of UpgradeReq accesses(hits+misses)
2058 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194101 # number of SCUpgradeReq accesses(hits+misses)
2059 system.cpu1.l2cache.SCUpgradeReq_accesses::total 194101 # number of SCUpgradeReq accesses(hits+misses)
2060 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 26 # number of SCUpgradeFailReq accesses(hits+misses)
2061 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 26 # number of SCUpgradeFailReq accesses(hits+misses)
2062 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1013747 # number of ReadExReq accesses(hits+misses)
2063 system.cpu1.l2cache.ReadExReq_accesses::total 1013747 # number of ReadExReq accesses(hits+misses)
2064 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4832090 # number of ReadCleanReq accesses(hits+misses)
2065 system.cpu1.l2cache.ReadCleanReq_accesses::total 4832090 # number of ReadCleanReq accesses(hits+misses)
2066 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3348997 # number of ReadSharedReq accesses(hits+misses)
2067 system.cpu1.l2cache.ReadSharedReq_accesses::total 3348997 # number of ReadSharedReq accesses(hits+misses)
2068 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 464424 # number of InvalidateReq accesses(hits+misses)
2069 system.cpu1.l2cache.InvalidateReq_accesses::total 464424 # number of InvalidateReq accesses(hits+misses)
2070 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 221284 # number of demand (read+write) accesses
2071 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 147987 # number of demand (read+write) accesses
2072 system.cpu1.l2cache.demand_accesses::cpu1.inst 4832090 # number of demand (read+write) accesses
2073 system.cpu1.l2cache.demand_accesses::cpu1.data 4362744 # number of demand (read+write) accesses
2074 system.cpu1.l2cache.demand_accesses::total 9564105 # number of demand (read+write) accesses
2075 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 221284 # number of overall (read+write) accesses
2076 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 147987 # number of overall (read+write) accesses
2077 system.cpu1.l2cache.overall_accesses::cpu1.inst 4832090 # number of overall (read+write) accesses
2078 system.cpu1.l2cache.overall_accesses::cpu1.data 4362744 # number of overall (read+write) accesses
2079 system.cpu1.l2cache.overall_accesses::total 9564105 # number of overall (read+write) accesses
2080 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for ReadReq accesses
2081 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050721 # miss rate for ReadReq accesses
2082 system.cpu1.l2cache.ReadReq_miss_rate::total 0.045471 # miss rate for ReadReq accesses
2083 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998814 # miss rate for UpgradeReq accesses
2084 system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998814 # miss rate for UpgradeReq accesses
2085 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2086 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2087 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2088 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2089 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.232319 # miss rate for ReadExReq accesses
2090 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.232319 # miss rate for ReadExReq accesses
2091 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087248 # miss rate for ReadCleanReq accesses
2092 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087248 # miss rate for ReadCleanReq accesses
2093 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248304 # miss rate for ReadSharedReq accesses
2094 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248304 # miss rate for ReadSharedReq accesses
2095 system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.568063 # miss rate for InvalidateReq accesses
2096 system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.568063 # miss rate for InvalidateReq accesses
2097 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for demand accesses
2098 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050721 # miss rate for demand accesses
2099 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087248 # miss rate for demand accesses
2100 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244590 # miss rate for demand accesses
2101 system.cpu1.l2cache.demand_miss_rate::total 0.157408 # miss rate for demand accesses
2102 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for overall accesses
2103 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050721 # miss rate for overall accesses
2104 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087248 # miss rate for overall accesses
2105 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244590 # miss rate for overall accesses
2106 system.cpu1.l2cache.overall_miss_rate::total 0.157408 # miss rate for overall accesses
2107 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average ReadReq miss latency
2108 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40108.046896 # average ReadReq miss latency
2109 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38719.760586 # average ReadReq miss latency
2110 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15706.945362 # average UpgradeReq miss latency
2111 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15706.945362 # average UpgradeReq miss latency
2112 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9586.212848 # average SCUpgradeReq miss latency
2113 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9586.212848 # average SCUpgradeReq miss latency
2114 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259403.846154 # average SCUpgradeFailReq miss latency
2115 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259403.846154 # average SCUpgradeFailReq miss latency
2116 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52822.132957 # average ReadExReq miss latency
2117 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52822.132957 # average ReadExReq miss latency
2118 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38506.889411 # average ReadCleanReq miss latency
2119 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38506.889411 # average ReadCleanReq miss latency
2120 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.361966 # average ReadSharedReq miss latency
2121 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.361966 # average ReadSharedReq miss latency
2122 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69058.954522 # average InvalidateReq miss latency
2123 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69058.954522 # average InvalidateReq miss latency
2124 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average overall miss latency
2125 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40108.046896 # average overall miss latency
2126 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38506.889411 # average overall miss latency
2127 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38933.760479 # average overall miss latency
2128 system.cpu1.l2cache.demand_avg_miss_latency::total 38811.832845 # average overall miss latency
2129 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average overall miss latency
2130 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40108.046896 # average overall miss latency
2131 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38506.889411 # average overall miss latency
2132 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38933.760479 # average overall miss latency
2133 system.cpu1.l2cache.overall_avg_miss_latency::total 38811.832845 # average overall miss latency
2134 system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2135 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2136 system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2137 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2138 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2139 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2140 system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2141 system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2142 system.cpu1.l2cache.writebacks::writebacks 983057 # number of writebacks
2143 system.cpu1.l2cache.writebacks::total 983057 # number of writebacks
2144 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3912 # number of ReadExReq MSHR hits
2145 system.cpu1.l2cache.ReadExReq_mshr_hits::total 3912 # number of ReadExReq MSHR hits
2146 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 475 # number of ReadSharedReq MSHR hits
2147 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 475 # number of ReadSharedReq MSHR hits
2148 system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits
2149 system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits
2150 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4387 # number of demand (read+write) MSHR hits
2151 system.cpu1.l2cache.demand_mshr_hits::total 4387 # number of demand (read+write) MSHR hits
2152 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4387 # number of overall MSHR hits
2153 system.cpu1.l2cache.overall_mshr_hits::total 4387 # number of overall MSHR hits
2154 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9285 # number of ReadReq MSHR misses
2155 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7506 # number of ReadReq MSHR misses
2156 system.cpu1.l2cache.ReadReq_mshr_misses::total 16791 # number of ReadReq MSHR misses
2157 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 603476 # number of HardPFReq MSHR misses
2158 system.cpu1.l2cache.HardPFReq_mshr_misses::total 603476 # number of HardPFReq MSHR misses
2159 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 201343 # number of UpgradeReq MSHR misses
2160 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 201343 # number of UpgradeReq MSHR misses
2161 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194101 # number of SCUpgradeReq MSHR misses
2162 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194101 # number of SCUpgradeReq MSHR misses
2163 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 26 # number of SCUpgradeFailReq MSHR misses
2164 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 26 # number of SCUpgradeFailReq MSHR misses
2165 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 231601 # number of ReadExReq MSHR misses
2166 system.cpu1.l2cache.ReadExReq_mshr_misses::total 231601 # number of ReadExReq MSHR misses
2167 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 421589 # number of ReadCleanReq MSHR misses
2168 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 421589 # number of ReadCleanReq MSHR misses
2169 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 831094 # number of ReadSharedReq MSHR misses
2170 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 831094 # number of ReadSharedReq MSHR misses
2171 system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263821 # number of InvalidateReq MSHR misses
2172 system.cpu1.l2cache.InvalidateReq_mshr_misses::total 263821 # number of InvalidateReq MSHR misses
2173 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9285 # number of demand (read+write) MSHR misses
2174 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7506 # number of demand (read+write) MSHR misses
2175 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 421589 # number of demand (read+write) MSHR misses
2176 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1062695 # number of demand (read+write) MSHR misses
2177 system.cpu1.l2cache.demand_mshr_misses::total 1501075 # number of demand (read+write) MSHR misses
2178 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9285 # number of overall MSHR misses
2179 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7506 # number of overall MSHR misses
2180 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 421589 # number of overall MSHR misses
2181 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1062695 # number of overall MSHR misses
2182 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 603476 # number of overall MSHR misses
2183 system.cpu1.l2cache.overall_mshr_misses::total 2104551 # number of overall MSHR misses
2184 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2185 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable
2186 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23721 # number of ReadReq MSHR uncacheable
2187 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable
2188 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable
2189 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2190 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses
2191 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46341 # number of overall MSHR uncacheable misses
2192 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of ReadReq MSHR miss cycles
2193 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 256015000 # number of ReadReq MSHR miss cycles
2194 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 549397500 # number of ReadReq MSHR miss cycles
2195 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27540952434 # number of HardPFReq MSHR miss cycles
2196 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27540952434 # number of HardPFReq MSHR miss cycles
2197 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6429356000 # number of UpgradeReq MSHR miss cycles
2198 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6429356000 # number of UpgradeReq MSHR miss cycles
2199 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3693933999 # number of SCUpgradeReq MSHR miss cycles
2200 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3693933999 # number of SCUpgradeReq MSHR miss cycles
2201 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6300500 # number of SCUpgradeFailReq MSHR miss cycles
2202 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6300500 # number of SCUpgradeFailReq MSHR miss cycles
2203 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10580800999 # number of ReadExReq MSHR miss cycles
2204 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10580800999 # number of ReadExReq MSHR miss cycles
2205 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13704547000 # number of ReadCleanReq MSHR miss cycles
2206 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13704547000 # number of ReadCleanReq MSHR miss cycles
2207 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24076200000 # number of ReadSharedReq MSHR miss cycles
2208 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24076200000 # number of ReadSharedReq MSHR miss cycles
2209 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16636263000 # number of InvalidateReq MSHR miss cycles
2210 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16636263000 # number of InvalidateReq MSHR miss cycles
2211 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of demand (read+write) MSHR miss cycles
2212 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 256015000 # number of demand (read+write) MSHR miss cycles
2213 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13704547000 # number of demand (read+write) MSHR miss cycles
2214 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34657000999 # number of demand (read+write) MSHR miss cycles
2215 system.cpu1.l2cache.demand_mshr_miss_latency::total 48910945499 # number of demand (read+write) MSHR miss cycles
2216 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of overall MSHR miss cycles
2217 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 256015000 # number of overall MSHR miss cycles
2218 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13704547000 # number of overall MSHR miss cycles
2219 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34657000999 # number of overall MSHR miss cycles
2220 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27540952434 # number of overall MSHR miss cycles
2221 system.cpu1.l2cache.overall_mshr_miss_latency::total 76451897933 # number of overall MSHR miss cycles
2222 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13974500 # number of ReadReq MSHR uncacheable cycles
2223 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4098070000 # number of ReadReq MSHR uncacheable cycles
2224 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4112044500 # number of ReadReq MSHR uncacheable cycles
2225 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3990752000 # number of WriteReq MSHR uncacheable cycles
2226 system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3990752000 # number of WriteReq MSHR uncacheable cycles
2227 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13974500 # number of overall MSHR uncacheable cycles
2228 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8088822000 # number of overall MSHR uncacheable cycles
2229 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8102796500 # number of overall MSHR uncacheable cycles
2230 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for ReadReq accesses
2231 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for ReadReq accesses
2232 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.045471 # mshr miss rate for ReadReq accesses
2233 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2234 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2235 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998814 # mshr miss rate for UpgradeReq accesses
2236 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998814 # mshr miss rate for UpgradeReq accesses
2237 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2238 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2239 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2240 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2241 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.228460 # mshr miss rate for ReadExReq accesses
2242 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.228460 # mshr miss rate for ReadExReq accesses
2243 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses
2244 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses
2245 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248162 # mshr miss rate for ReadSharedReq accesses
2246 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248162 # mshr miss rate for ReadSharedReq accesses
2247 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.568061 # mshr miss rate for InvalidateReq accesses
2248 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.568061 # mshr miss rate for InvalidateReq accesses
2249 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for demand accesses
2250 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for demand accesses
2251 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses
2252 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for demand accesses
2253 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156949 # mshr miss rate for demand accesses
2254 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for overall accesses
2255 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for overall accesses
2256 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses
2257 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for overall accesses
2258 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2259 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220047 # mshr miss rate for overall accesses
2260 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average ReadReq mshr miss latency
2261 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average ReadReq mshr miss latency
2262 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586 # average ReadReq mshr miss latency
2263 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average HardPFReq mshr miss latency
2264 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902 # average HardPFReq mshr miss latency
2265 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241 # average UpgradeReq mshr miss latency
2266 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241 # average UpgradeReq mshr miss latency
2267 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016 # average SCUpgradeReq mshr miss latency
2268 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016 # average SCUpgradeReq mshr miss latency
2269 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077 # average SCUpgradeFailReq mshr miss latency
2270 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077 # average SCUpgradeFailReq mshr miss latency
2271 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993 # average ReadExReq mshr miss latency
2272 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993 # average ReadExReq mshr miss latency
2273 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average ReadCleanReq mshr miss latency
2274 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411 # average ReadCleanReq mshr miss latency
2275 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266 # average ReadSharedReq mshr miss latency
2276 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266 # average ReadSharedReq mshr miss latency
2277 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575 # average InvalidateReq mshr miss latency
2278 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575 # average InvalidateReq mshr miss latency
2279 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency
2280 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency
2281 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency
2282 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency
2283 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172 # average overall mshr miss latency
2284 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency
2285 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency
2286 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency
2287 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency
2288 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average overall mshr miss latency
2289 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014 # average overall mshr miss latency
2290 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency
2291 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429 # average ReadReq mshr uncacheable latency
2292 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734 # average ReadReq mshr uncacheable latency
2293 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860 # average WriteReq mshr uncacheable latency
2294 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860 # average WriteReq mshr uncacheable latency
2295 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency
2296 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296 # average overall mshr uncacheable latency
2297 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726 # average overall mshr uncacheable latency
2298 system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2299 system.cpu1.toL2Bus.snoop_filter.tot_requests 19832170 # Total number of requests made to the snoop filter.
2300 system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10173061 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2301 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1095 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2302 system.cpu1.toL2Bus.snoop_filter.tot_snoops 1632026 # Total number of snoops made to the snoop filter.
2303 system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1631848 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2304 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 178 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2305 system.cpu1.toL2Bus.trans_dist::ReadReq 456067 # Transaction distribution
2306 system.cpu1.toL2Bus.trans_dist::ReadResp 8724452 # Transaction distribution
2307 system.cpu1.toL2Bus.trans_dist::WriteReq 22620 # Transaction distribution
2308 system.cpu1.toL2Bus.trans_dist::WriteResp 22620 # Transaction distribution
2309 system.cpu1.toL2Bus.trans_dist::WritebackDirty 3978006 # Transaction distribution
2310 system.cpu1.toL2Bus.trans_dist::WritebackClean 6573071 # Transaction distribution
2311 system.cpu1.toL2Bus.trans_dist::CleanEvict 2099842 # Transaction distribution
2312 system.cpu1.toL2Bus.trans_dist::HardPFReq 741149 # Transaction distribution
2313 system.cpu1.toL2Bus.trans_dist::UpgradeReq 395876 # Transaction distribution
2314 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358205 # Transaction distribution
2315 system.cpu1.toL2Bus.trans_dist::UpgradeResp 460652 # Transaction distribution
2316 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution
2317 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution
2318 system.cpu1.toL2Bus.trans_dist::ReadExReq 1084167 # Transaction distribution
2319 system.cpu1.toL2Bus.trans_dist::ReadExResp 1021480 # Transaction distribution
2320 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4832090 # Transaction distribution
2321 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4231593 # Transaction distribution
2322 system.cpu1.toL2Bus.trans_dist::InvalidateReq 474723 # Transaction distribution
2323 system.cpu1.toL2Bus.trans_dist::InvalidateResp 464424 # Transaction distribution
2324 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14495311 # Packet count per connected master and slave (bytes)
2325 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15429373 # Packet count per connected master and slave (bytes)
2326 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 311743 # Packet count per connected master and slave (bytes)
2327 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 489874 # Packet count per connected master and slave (bytes)
2328 system.cpu1.toL2Bus.pkt_count::total 30726301 # Packet count per connected master and slave (bytes)
2329 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 618432504 # Cumulative packet size per connected master and slave (bytes)
2330 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588237954 # Cumulative packet size per connected master and slave (bytes)
2331 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1183896 # Cumulative packet size per connected master and slave (bytes)
2332 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1770272 # Cumulative packet size per connected master and slave (bytes)
2333 system.cpu1.toL2Bus.pkt_size::total 1209624626 # Cumulative packet size per connected master and slave (bytes)
2334 system.cpu1.toL2Bus.snoops 5375046 # Total snoops (count)
2335 system.cpu1.toL2Bus.snoop_fanout::samples 15685523 # Request fanout histogram
2336 system.cpu1.toL2Bus.snoop_fanout::mean 0.117781 # Request fanout histogram
2337 system.cpu1.toL2Bus.snoop_fanout::stdev 0.322383 # Request fanout histogram
2338 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2339 system.cpu1.toL2Bus.snoop_fanout::0 13838252 88.22% 88.22% # Request fanout histogram
2340 system.cpu1.toL2Bus.snoop_fanout::1 1847093 11.78% 100.00% # Request fanout histogram
2341 system.cpu1.toL2Bus.snoop_fanout::2 178 0.00% 100.00% # Request fanout histogram
2342 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2343 system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2344 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2345 system.cpu1.toL2Bus.snoop_fanout::total 15685523 # Request fanout histogram
2346 system.cpu1.toL2Bus.reqLayer0.occupancy 19622729498 # Layer occupancy (ticks)
2347 system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2348 system.cpu1.toL2Bus.snoopLayer0.occupancy 175341179 # Layer occupancy (ticks)
2349 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2350 system.cpu1.toL2Bus.respLayer0.occupancy 7248245000 # Layer occupancy (ticks)
2351 system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2352 system.cpu1.toL2Bus.respLayer1.occupancy 7009474930 # Layer occupancy (ticks)
2353 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2354 system.cpu1.toL2Bus.respLayer2.occupancy 163756499 # Layer occupancy (ticks)
2355 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2356 system.cpu1.toL2Bus.respLayer3.occupancy 268590000 # Layer occupancy (ticks)
2357 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2358 system.iobus.trans_dist::ReadReq 40469 # Transaction distribution
2359 system.iobus.trans_dist::ReadResp 40469 # Transaction distribution
2360 system.iobus.trans_dist::WriteReq 137017 # Transaction distribution
2361 system.iobus.trans_dist::WriteResp 137017 # Transaction distribution
2362 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47986 # Packet count per connected master and slave (bytes)
2363 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2364 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2365 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2366 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2367 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2368 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2369 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2370 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2371 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2372 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
2373 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2374 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2375 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2376 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2377 system.iobus.pkt_count_system.bridge.master::total 123128 # Packet count per connected master and slave (bytes)
2378 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231764 # Packet count per connected master and slave (bytes)
2379 system.iobus.pkt_count_system.realview.ide.dma::total 231764 # Packet count per connected master and slave (bytes)
2380 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2381 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2382 system.iobus.pkt_count::total 354972 # Packet count per connected master and slave (bytes)
2383 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48006 # Cumulative packet size per connected master and slave (bytes)
2384 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2385 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2386 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2387 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2388 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2389 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2390 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2391 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2392 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2393 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
2394 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2395 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2396 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2397 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2398 system.iobus.pkt_size_system.bridge.master::total 156143 # Cumulative packet size per connected master and slave (bytes)
2399 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355408 # Cumulative packet size per connected master and slave (bytes)
2400 system.iobus.pkt_size_system.realview.ide.dma::total 7355408 # Cumulative packet size per connected master and slave (bytes)
2401 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2402 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2403 system.iobus.pkt_size::total 7513637 # Cumulative packet size per connected master and slave (bytes)
2404 system.iobus.reqLayer0.occupancy 37181500 # Layer occupancy (ticks)
2405 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2406 system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks)
2407 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2408 system.iobus.reqLayer2.occupancy 8500 # Layer occupancy (ticks)
2409 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2410 system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
2411 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2412 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2413 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2414 system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
2415 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2416 system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2417 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2418 system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2419 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2420 system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
2421 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2422 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2423 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2424 system.iobus.reqLayer23.occupancy 26640000 # Layer occupancy (ticks)
2425 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2426 system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks)
2427 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2428 system.iobus.reqLayer25.occupancy 37419000 # Layer occupancy (ticks)
2429 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2430 system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks)
2431 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2432 system.iobus.reqLayer27.occupancy 566572505 # Layer occupancy (ticks)
2433 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2434 system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks)
2435 system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2436 system.iobus.respLayer0.occupancy 93098000 # Layer occupancy (ticks)
2437 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2438 system.iobus.respLayer3.occupancy 148204000 # Layer occupancy (ticks)
2439 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2440 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2441 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2442 system.iocache.tags.replacements 115869 # number of replacements
2443 system.iocache.tags.tagsinuse 11.294988 # Cycle average of tags in use
2444 system.iocache.tags.total_refs 4 # Total number of references to valid blocks.
2445 system.iocache.tags.sampled_refs 115885 # Sample count of references to valid blocks.
2446 system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks.
2447 system.iocache.tags.warmup_cycle 9206093766000 # Cycle when the warmup percentage was hit.
2448 system.iocache.tags.occ_blocks::realview.ethernet 3.821408 # Average occupied blocks per requestor
2449 system.iocache.tags.occ_blocks::realview.ide 7.473580 # Average occupied blocks per requestor
2450 system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy
2451 system.iocache.tags.occ_percent::realview.ide 0.467099 # Average percentage of cache occupancy
2452 system.iocache.tags.occ_percent::total 0.705937 # Average percentage of cache occupancy
2453 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2454 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2455 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2456 system.iocache.tags.tag_accesses 1043293 # Number of tag accesses
2457 system.iocache.tags.data_accesses 1043293 # Number of data accesses
2458 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2459 system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses
2460 system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses
2461 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2462 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2463 system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
2464 system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2465 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2466 system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses
2467 system.iocache.demand_misses::total 8938 # number of demand (read+write) misses
2468 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2469 system.iocache.overall_misses::realview.ide 8898 # number of overall misses
2470 system.iocache.overall_misses::total 8938 # number of overall misses
2471 system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles
2472 system.iocache.ReadReq_miss_latency::realview.ide 1681517592 # number of ReadReq miss cycles
2473 system.iocache.ReadReq_miss_latency::total 1686717092 # number of ReadReq miss cycles
2474 system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2475 system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2476 system.iocache.WriteLineReq_miss_latency::realview.ide 14021691413 # number of WriteLineReq miss cycles
2477 system.iocache.WriteLineReq_miss_latency::total 14021691413 # number of WriteLineReq miss cycles
2478 system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles
2479 system.iocache.demand_miss_latency::realview.ide 1681517592 # number of demand (read+write) miss cycles
2480 system.iocache.demand_miss_latency::total 1687086092 # number of demand (read+write) miss cycles
2481 system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles
2482 system.iocache.overall_miss_latency::realview.ide 1681517592 # number of overall miss cycles
2483 system.iocache.overall_miss_latency::total 1687086092 # number of overall miss cycles
2484 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2485 system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses)
2486 system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses)
2487 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2488 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2489 system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
2490 system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2491 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2492 system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses
2493 system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses
2494 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2495 system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses
2496 system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses
2497 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2498 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2499 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2500 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2501 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2502 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2503 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2504 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2505 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2506 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2507 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2508 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2509 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2510 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency
2511 system.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647 # average ReadReq miss latency
2512 system.iocache.ReadReq_avg_miss_latency::total 188776.395299 # average ReadReq miss latency
2513 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2514 system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2515 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253 # average WriteLineReq miss latency
2516 system.iocache.WriteLineReq_avg_miss_latency::total 131063.443253 # average WriteLineReq miss latency
2517 system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
2518 system.iocache.demand_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency
2519 system.iocache.demand_avg_miss_latency::total 188754.317744 # average overall miss latency
2520 system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
2521 system.iocache.overall_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency
2522 system.iocache.overall_avg_miss_latency::total 188754.317744 # average overall miss latency
2523 system.iocache.blocked_cycles::no_mshrs 36073 # number of cycles access was blocked
2524 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2525 system.iocache.blocked::no_mshrs 3617 # number of cycles access was blocked
2526 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2527 system.iocache.avg_blocked_cycles::no_mshrs 9.973182 # average number of cycles each access was blocked
2528 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2529 system.iocache.fast_writes 0 # number of fast writes performed
2530 system.iocache.cache_copies 0 # number of cache copies performed
2531 system.iocache.writebacks::writebacks 106957 # number of writebacks
2532 system.iocache.writebacks::total 106957 # number of writebacks
2533 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2534 system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses
2535 system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses
2536 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2537 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2538 system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
2539 system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2540 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2541 system.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses
2542 system.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses
2543 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2544 system.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses
2545 system.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses
2546 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles
2547 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236617592 # number of ReadReq MSHR miss cycles
2548 system.iocache.ReadReq_mshr_miss_latency::total 1239967092 # number of ReadReq MSHR miss cycles
2549 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2550 system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2551 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8672491413 # number of WriteLineReq MSHR miss cycles
2552 system.iocache.WriteLineReq_mshr_miss_latency::total 8672491413 # number of WriteLineReq MSHR miss cycles
2553 system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles
2554 system.iocache.demand_mshr_miss_latency::realview.ide 1236617592 # number of demand (read+write) MSHR miss cycles
2555 system.iocache.demand_mshr_miss_latency::total 1240186092 # number of demand (read+write) MSHR miss cycles
2556 system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles
2557 system.iocache.overall_mshr_miss_latency::realview.ide 1236617592 # number of overall MSHR miss cycles
2558 system.iocache.overall_mshr_miss_latency::total 1240186092 # number of overall MSHR miss cycles
2559 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2560 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2561 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2562 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2563 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2564 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2565 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2566 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2567 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2568 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2569 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2570 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2571 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2572 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency
2573 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647 # average ReadReq mshr miss latency
2574 system.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299 # average ReadReq mshr miss latency
2575 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2576 system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2577 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253 # average WriteLineReq mshr miss latency
2578 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253 # average WriteLineReq mshr miss latency
2579 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
2580 system.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency
2581 system.iocache.demand_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency
2582 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
2583 system.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency
2584 system.iocache.overall_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency
2585 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2586 system.l2c.tags.replacements 1210264 # number of replacements
2587 system.l2c.tags.tagsinuse 62755.466878 # Cycle average of tags in use
2588 system.l2c.tags.total_refs 5212344 # Total number of references to valid blocks.
2589 system.l2c.tags.sampled_refs 1269955 # Sample count of references to valid blocks.
2590 system.l2c.tags.avg_refs 4.104353 # Average number of references to valid blocks.
2591 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2592 system.l2c.tags.occ_blocks::writebacks 23285.968480 # Average occupied blocks per requestor
2593 system.l2c.tags.occ_blocks::cpu0.dtb.walker 218.650031 # Average occupied blocks per requestor
2594 system.l2c.tags.occ_blocks::cpu0.itb.walker 386.944281 # Average occupied blocks per requestor
2595 system.l2c.tags.occ_blocks::cpu0.inst 4588.836094 # Average occupied blocks per requestor
2596 system.l2c.tags.occ_blocks::cpu0.data 10476.813165 # Average occupied blocks per requestor
2597 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 13833.010748 # Average occupied blocks per requestor
2598 system.l2c.tags.occ_blocks::cpu1.dtb.walker 53.974082 # Average occupied blocks per requestor
2599 system.l2c.tags.occ_blocks::cpu1.itb.walker 79.219380 # Average occupied blocks per requestor
2600 system.l2c.tags.occ_blocks::cpu1.inst 3039.104298 # Average occupied blocks per requestor
2601 system.l2c.tags.occ_blocks::cpu1.data 3132.206690 # Average occupied blocks per requestor
2602 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3660.739630 # Average occupied blocks per requestor
2603 system.l2c.tags.occ_percent::writebacks 0.355316 # Average percentage of cache occupancy
2604 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003336 # Average percentage of cache occupancy
2605 system.l2c.tags.occ_percent::cpu0.itb.walker 0.005904 # Average percentage of cache occupancy
2606 system.l2c.tags.occ_percent::cpu0.inst 0.070020 # Average percentage of cache occupancy
2607 system.l2c.tags.occ_percent::cpu0.data 0.159863 # Average percentage of cache occupancy
2608 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.211075 # Average percentage of cache occupancy
2609 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000824 # Average percentage of cache occupancy
2610 system.l2c.tags.occ_percent::cpu1.itb.walker 0.001209 # Average percentage of cache occupancy
2611 system.l2c.tags.occ_percent::cpu1.inst 0.046373 # Average percentage of cache occupancy
2612 system.l2c.tags.occ_percent::cpu1.data 0.047794 # Average percentage of cache occupancy
2613 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055858 # Average percentage of cache occupancy
2614 system.l2c.tags.occ_percent::total 0.957572 # Average percentage of cache occupancy
2615 system.l2c.tags.occ_task_id_blocks::1022 10565 # Occupied blocks per task id
2616 system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id
2617 system.l2c.tags.occ_task_id_blocks::1024 48895 # Occupied blocks per task id
2618 system.l2c.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id
2619 system.l2c.tags.age_task_id_blocks_1022::2 159 # Occupied blocks per task id
2620 system.l2c.tags.age_task_id_blocks_1022::3 1447 # Occupied blocks per task id
2621 system.l2c.tags.age_task_id_blocks_1022::4 8916 # Occupied blocks per task id
2622 system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
2623 system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
2624 system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
2625 system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
2626 system.l2c.tags.age_task_id_blocks_1024::2 1774 # Occupied blocks per task id
2627 system.l2c.tags.age_task_id_blocks_1024::3 10274 # Occupied blocks per task id
2628 system.l2c.tags.age_task_id_blocks_1024::4 36522 # Occupied blocks per task id
2629 system.l2c.tags.occ_task_id_percent::1022 0.161209 # Percentage of cache occupancy per task id
2630 system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id
2631 system.l2c.tags.occ_task_id_percent::1024 0.746078 # Percentage of cache occupancy per task id
2632 system.l2c.tags.tag_accesses 66950820 # Number of tag accesses
2633 system.l2c.tags.data_accesses 66950820 # Number of data accesses
2634 system.l2c.WritebackDirty_hits::writebacks 2504481 # number of WritebackDirty hits
2635 system.l2c.WritebackDirty_hits::total 2504481 # number of WritebackDirty hits
2636 system.l2c.UpgradeReq_hits::cpu0.data 166895 # number of UpgradeReq hits
2637 system.l2c.UpgradeReq_hits::cpu1.data 113960 # number of UpgradeReq hits
2638 system.l2c.UpgradeReq_hits::total 280855 # number of UpgradeReq hits
2639 system.l2c.SCUpgradeReq_hits::cpu0.data 38875 # number of SCUpgradeReq hits
2640 system.l2c.SCUpgradeReq_hits::cpu1.data 34247 # number of SCUpgradeReq hits
2641 system.l2c.SCUpgradeReq_hits::total 73122 # number of SCUpgradeReq hits
2642 system.l2c.ReadExReq_hits::cpu0.data 158326 # number of ReadExReq hits
2643 system.l2c.ReadExReq_hits::cpu1.data 166214 # number of ReadExReq hits
2644 system.l2c.ReadExReq_hits::total 324540 # number of ReadExReq hits
2645 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5191 # number of ReadSharedReq hits
2646 system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4009 # number of ReadSharedReq hits
2647 system.l2c.ReadSharedReq_hits::cpu0.inst 435451 # number of ReadSharedReq hits
2648 system.l2c.ReadSharedReq_hits::cpu0.data 562405 # number of ReadSharedReq hits
2649 system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296765 # number of ReadSharedReq hits
2650 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5208 # number of ReadSharedReq hits
2651 system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4285 # number of ReadSharedReq hits
2652 system.l2c.ReadSharedReq_hits::cpu1.inst 382834 # number of ReadSharedReq hits
2653 system.l2c.ReadSharedReq_hits::cpu1.data 480125 # number of ReadSharedReq hits
2654 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 262665 # number of ReadSharedReq hits
2655 system.l2c.ReadSharedReq_hits::total 2438938 # number of ReadSharedReq hits
2656 system.l2c.demand_hits::cpu0.dtb.walker 5191 # number of demand (read+write) hits
2657 system.l2c.demand_hits::cpu0.itb.walker 4009 # number of demand (read+write) hits
2658 system.l2c.demand_hits::cpu0.inst 435451 # number of demand (read+write) hits
2659 system.l2c.demand_hits::cpu0.data 720731 # number of demand (read+write) hits
2660 system.l2c.demand_hits::cpu0.l2cache.prefetcher 296765 # number of demand (read+write) hits
2661 system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits
2662 system.l2c.demand_hits::cpu1.itb.walker 4285 # number of demand (read+write) hits
2663 system.l2c.demand_hits::cpu1.inst 382834 # number of demand (read+write) hits
2664 system.l2c.demand_hits::cpu1.data 646339 # number of demand (read+write) hits
2665 system.l2c.demand_hits::cpu1.l2cache.prefetcher 262665 # number of demand (read+write) hits
2666 system.l2c.demand_hits::total 2763478 # number of demand (read+write) hits
2667 system.l2c.overall_hits::cpu0.dtb.walker 5191 # number of overall hits
2668 system.l2c.overall_hits::cpu0.itb.walker 4009 # number of overall hits
2669 system.l2c.overall_hits::cpu0.inst 435451 # number of overall hits
2670 system.l2c.overall_hits::cpu0.data 720731 # number of overall hits
2671 system.l2c.overall_hits::cpu0.l2cache.prefetcher 296765 # number of overall hits
2672 system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits
2673 system.l2c.overall_hits::cpu1.itb.walker 4285 # number of overall hits
2674 system.l2c.overall_hits::cpu1.inst 382834 # number of overall hits
2675 system.l2c.overall_hits::cpu1.data 646339 # number of overall hits
2676 system.l2c.overall_hits::cpu1.l2cache.prefetcher 262665 # number of overall hits
2677 system.l2c.overall_hits::total 2763478 # number of overall hits
2678 system.l2c.UpgradeReq_misses::cpu0.data 67422 # number of UpgradeReq misses
2679 system.l2c.UpgradeReq_misses::cpu1.data 57259 # number of UpgradeReq misses
2680 system.l2c.UpgradeReq_misses::total 124681 # number of UpgradeReq misses
2681 system.l2c.SCUpgradeReq_misses::cpu0.data 14532 # number of SCUpgradeReq misses
2682 system.l2c.SCUpgradeReq_misses::cpu1.data 11014 # number of SCUpgradeReq misses
2683 system.l2c.SCUpgradeReq_misses::total 25546 # number of SCUpgradeReq misses
2684 system.l2c.ReadExReq_misses::cpu0.data 480698 # number of ReadExReq misses
2685 system.l2c.ReadExReq_misses::cpu1.data 148334 # number of ReadExReq misses
2686 system.l2c.ReadExReq_misses::total 629032 # number of ReadExReq misses
2687 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1519 # number of ReadSharedReq misses
2688 system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1645 # number of ReadSharedReq misses
2689 system.l2c.ReadSharedReq_misses::cpu0.inst 47029 # number of ReadSharedReq misses
2690 system.l2c.ReadSharedReq_misses::cpu0.data 136142 # number of ReadSharedReq misses
2691 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 207239 # number of ReadSharedReq misses
2692 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1062 # number of ReadSharedReq misses
2693 system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1011 # number of ReadSharedReq misses
2694 system.l2c.ReadSharedReq_misses::cpu1.inst 38755 # number of ReadSharedReq misses
2695 system.l2c.ReadSharedReq_misses::cpu1.data 73388 # number of ReadSharedReq misses
2696 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 139305 # number of ReadSharedReq misses
2697 system.l2c.ReadSharedReq_misses::total 647095 # number of ReadSharedReq misses
2698 system.l2c.demand_misses::cpu0.dtb.walker 1519 # number of demand (read+write) misses
2699 system.l2c.demand_misses::cpu0.itb.walker 1645 # number of demand (read+write) misses
2700 system.l2c.demand_misses::cpu0.inst 47029 # number of demand (read+write) misses
2701 system.l2c.demand_misses::cpu0.data 616840 # number of demand (read+write) misses
2702 system.l2c.demand_misses::cpu0.l2cache.prefetcher 207239 # number of demand (read+write) misses
2703 system.l2c.demand_misses::cpu1.dtb.walker 1062 # number of demand (read+write) misses
2704 system.l2c.demand_misses::cpu1.itb.walker 1011 # number of demand (read+write) misses
2705 system.l2c.demand_misses::cpu1.inst 38755 # number of demand (read+write) misses
2706 system.l2c.demand_misses::cpu1.data 221722 # number of demand (read+write) misses
2707 system.l2c.demand_misses::cpu1.l2cache.prefetcher 139305 # number of demand (read+write) misses
2708 system.l2c.demand_misses::total 1276127 # number of demand (read+write) misses
2709 system.l2c.overall_misses::cpu0.dtb.walker 1519 # number of overall misses
2710 system.l2c.overall_misses::cpu0.itb.walker 1645 # number of overall misses
2711 system.l2c.overall_misses::cpu0.inst 47029 # number of overall misses
2712 system.l2c.overall_misses::cpu0.data 616840 # number of overall misses
2713 system.l2c.overall_misses::cpu0.l2cache.prefetcher 207239 # number of overall misses
2714 system.l2c.overall_misses::cpu1.dtb.walker 1062 # number of overall misses
2715 system.l2c.overall_misses::cpu1.itb.walker 1011 # number of overall misses
2716 system.l2c.overall_misses::cpu1.inst 38755 # number of overall misses
2717 system.l2c.overall_misses::cpu1.data 221722 # number of overall misses
2718 system.l2c.overall_misses::cpu1.l2cache.prefetcher 139305 # number of overall misses
2719 system.l2c.overall_misses::total 1276127 # number of overall misses
2720 system.l2c.UpgradeReq_miss_latency::cpu0.data 993921500 # number of UpgradeReq miss cycles
2721 system.l2c.UpgradeReq_miss_latency::cpu1.data 971150500 # number of UpgradeReq miss cycles
2722 system.l2c.UpgradeReq_miss_latency::total 1965072000 # number of UpgradeReq miss cycles
2723 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 192356500 # number of SCUpgradeReq miss cycles
2724 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 170135500 # number of SCUpgradeReq miss cycles
2725 system.l2c.SCUpgradeReq_miss_latency::total 362492000 # number of SCUpgradeReq miss cycles
2726 system.l2c.ReadExReq_miss_latency::cpu0.data 63553941500 # number of ReadExReq miss cycles
2727 system.l2c.ReadExReq_miss_latency::cpu1.data 19410172500 # number of ReadExReq miss cycles
2728 system.l2c.ReadExReq_miss_latency::total 82964114000 # number of ReadExReq miss cycles
2729 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 210107500 # number of ReadSharedReq miss cycles
2730 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 226821000 # number of ReadSharedReq miss cycles
2731 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6321092000 # number of ReadSharedReq miss cycles
2732 system.l2c.ReadSharedReq_miss_latency::cpu0.data 18616948500 # number of ReadSharedReq miss cycles
2733 system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of ReadSharedReq miss cycles
2734 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 146053000 # number of ReadSharedReq miss cycles
2735 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 143461000 # number of ReadSharedReq miss cycles
2736 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5220292500 # number of ReadSharedReq miss cycles
2737 system.l2c.ReadSharedReq_miss_latency::cpu1.data 10187553500 # number of ReadSharedReq miss cycles
2738 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of ReadSharedReq miss cycles
2739 system.l2c.ReadSharedReq_miss_latency::total 97218987006 # number of ReadSharedReq miss cycles
2740 system.l2c.demand_miss_latency::cpu0.dtb.walker 210107500 # number of demand (read+write) miss cycles
2741 system.l2c.demand_miss_latency::cpu0.itb.walker 226821000 # number of demand (read+write) miss cycles
2742 system.l2c.demand_miss_latency::cpu0.inst 6321092000 # number of demand (read+write) miss cycles
2743 system.l2c.demand_miss_latency::cpu0.data 82170890000 # number of demand (read+write) miss cycles
2744 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of demand (read+write) miss cycles
2745 system.l2c.demand_miss_latency::cpu1.dtb.walker 146053000 # number of demand (read+write) miss cycles
2746 system.l2c.demand_miss_latency::cpu1.itb.walker 143461000 # number of demand (read+write) miss cycles
2747 system.l2c.demand_miss_latency::cpu1.inst 5220292500 # number of demand (read+write) miss cycles
2748 system.l2c.demand_miss_latency::cpu1.data 29597726000 # number of demand (read+write) miss cycles
2749 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of demand (read+write) miss cycles
2750 system.l2c.demand_miss_latency::total 180183101006 # number of demand (read+write) miss cycles
2751 system.l2c.overall_miss_latency::cpu0.dtb.walker 210107500 # number of overall miss cycles
2752 system.l2c.overall_miss_latency::cpu0.itb.walker 226821000 # number of overall miss cycles
2753 system.l2c.overall_miss_latency::cpu0.inst 6321092000 # number of overall miss cycles
2754 system.l2c.overall_miss_latency::cpu0.data 82170890000 # number of overall miss cycles
2755 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of overall miss cycles
2756 system.l2c.overall_miss_latency::cpu1.dtb.walker 146053000 # number of overall miss cycles
2757 system.l2c.overall_miss_latency::cpu1.itb.walker 143461000 # number of overall miss cycles
2758 system.l2c.overall_miss_latency::cpu1.inst 5220292500 # number of overall miss cycles
2759 system.l2c.overall_miss_latency::cpu1.data 29597726000 # number of overall miss cycles
2760 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of overall miss cycles
2761 system.l2c.overall_miss_latency::total 180183101006 # number of overall miss cycles
2762 system.l2c.WritebackDirty_accesses::writebacks 2504481 # number of WritebackDirty accesses(hits+misses)
2763 system.l2c.WritebackDirty_accesses::total 2504481 # number of WritebackDirty accesses(hits+misses)
2764 system.l2c.UpgradeReq_accesses::cpu0.data 234317 # number of UpgradeReq accesses(hits+misses)
2765 system.l2c.UpgradeReq_accesses::cpu1.data 171219 # number of UpgradeReq accesses(hits+misses)
2766 system.l2c.UpgradeReq_accesses::total 405536 # number of UpgradeReq accesses(hits+misses)
2767 system.l2c.SCUpgradeReq_accesses::cpu0.data 53407 # number of SCUpgradeReq accesses(hits+misses)
2768 system.l2c.SCUpgradeReq_accesses::cpu1.data 45261 # number of SCUpgradeReq accesses(hits+misses)
2769 system.l2c.SCUpgradeReq_accesses::total 98668 # number of SCUpgradeReq accesses(hits+misses)
2770 system.l2c.ReadExReq_accesses::cpu0.data 639024 # number of ReadExReq accesses(hits+misses)
2771 system.l2c.ReadExReq_accesses::cpu1.data 314548 # number of ReadExReq accesses(hits+misses)
2772 system.l2c.ReadExReq_accesses::total 953572 # number of ReadExReq accesses(hits+misses)
2773 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6710 # number of ReadSharedReq accesses(hits+misses)
2774 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5654 # number of ReadSharedReq accesses(hits+misses)
2775 system.l2c.ReadSharedReq_accesses::cpu0.inst 482480 # number of ReadSharedReq accesses(hits+misses)
2776 system.l2c.ReadSharedReq_accesses::cpu0.data 698547 # number of ReadSharedReq accesses(hits+misses)
2777 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 504004 # number of ReadSharedReq accesses(hits+misses)
2778 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6270 # number of ReadSharedReq accesses(hits+misses)
2779 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5296 # number of ReadSharedReq accesses(hits+misses)
2780 system.l2c.ReadSharedReq_accesses::cpu1.inst 421589 # number of ReadSharedReq accesses(hits+misses)
2781 system.l2c.ReadSharedReq_accesses::cpu1.data 553513 # number of ReadSharedReq accesses(hits+misses)
2782 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 401970 # number of ReadSharedReq accesses(hits+misses)
2783 system.l2c.ReadSharedReq_accesses::total 3086033 # number of ReadSharedReq accesses(hits+misses)
2784 system.l2c.demand_accesses::cpu0.dtb.walker 6710 # number of demand (read+write) accesses
2785 system.l2c.demand_accesses::cpu0.itb.walker 5654 # number of demand (read+write) accesses
2786 system.l2c.demand_accesses::cpu0.inst 482480 # number of demand (read+write) accesses
2787 system.l2c.demand_accesses::cpu0.data 1337571 # number of demand (read+write) accesses
2788 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 504004 # number of demand (read+write) accesses
2789 system.l2c.demand_accesses::cpu1.dtb.walker 6270 # number of demand (read+write) accesses
2790 system.l2c.demand_accesses::cpu1.itb.walker 5296 # number of demand (read+write) accesses
2791 system.l2c.demand_accesses::cpu1.inst 421589 # number of demand (read+write) accesses
2792 system.l2c.demand_accesses::cpu1.data 868061 # number of demand (read+write) accesses
2793 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 401970 # number of demand (read+write) accesses
2794 system.l2c.demand_accesses::total 4039605 # number of demand (read+write) accesses
2795 system.l2c.overall_accesses::cpu0.dtb.walker 6710 # number of overall (read+write) accesses
2796 system.l2c.overall_accesses::cpu0.itb.walker 5654 # number of overall (read+write) accesses
2797 system.l2c.overall_accesses::cpu0.inst 482480 # number of overall (read+write) accesses
2798 system.l2c.overall_accesses::cpu0.data 1337571 # number of overall (read+write) accesses
2799 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 504004 # number of overall (read+write) accesses
2800 system.l2c.overall_accesses::cpu1.dtb.walker 6270 # number of overall (read+write) accesses
2801 system.l2c.overall_accesses::cpu1.itb.walker 5296 # number of overall (read+write) accesses
2802 system.l2c.overall_accesses::cpu1.inst 421589 # number of overall (read+write) accesses
2803 system.l2c.overall_accesses::cpu1.data 868061 # number of overall (read+write) accesses
2804 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 401970 # number of overall (read+write) accesses
2805 system.l2c.overall_accesses::total 4039605 # number of overall (read+write) accesses
2806 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.287738 # miss rate for UpgradeReq accesses
2807 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.334420 # miss rate for UpgradeReq accesses
2808 system.l2c.UpgradeReq_miss_rate::total 0.307447 # miss rate for UpgradeReq accesses
2809 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.272099 # miss rate for SCUpgradeReq accesses
2810 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.243344 # miss rate for SCUpgradeReq accesses
2811 system.l2c.SCUpgradeReq_miss_rate::total 0.258909 # miss rate for SCUpgradeReq accesses
2812 system.l2c.ReadExReq_miss_rate::cpu0.data 0.752238 # miss rate for ReadExReq accesses
2813 system.l2c.ReadExReq_miss_rate::cpu1.data 0.471578 # miss rate for ReadExReq accesses
2814 system.l2c.ReadExReq_miss_rate::total 0.659659 # miss rate for ReadExReq accesses
2815 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for ReadSharedReq accesses
2816 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.290944 # miss rate for ReadSharedReq accesses
2817 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097473 # miss rate for ReadSharedReq accesses
2818 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194893 # miss rate for ReadSharedReq accesses
2819 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for ReadSharedReq accesses
2820 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for ReadSharedReq accesses
2821 system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190899 # miss rate for ReadSharedReq accesses
2822 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.091926 # miss rate for ReadSharedReq accesses
2823 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.132586 # miss rate for ReadSharedReq accesses
2824 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for ReadSharedReq accesses
2825 system.l2c.ReadSharedReq_miss_rate::total 0.209685 # miss rate for ReadSharedReq accesses
2826 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for demand accesses
2827 system.l2c.demand_miss_rate::cpu0.itb.walker 0.290944 # miss rate for demand accesses
2828 system.l2c.demand_miss_rate::cpu0.inst 0.097473 # miss rate for demand accesses
2829 system.l2c.demand_miss_rate::cpu0.data 0.461164 # miss rate for demand accesses
2830 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for demand accesses
2831 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for demand accesses
2832 system.l2c.demand_miss_rate::cpu1.itb.walker 0.190899 # miss rate for demand accesses
2833 system.l2c.demand_miss_rate::cpu1.inst 0.091926 # miss rate for demand accesses
2834 system.l2c.demand_miss_rate::cpu1.data 0.255422 # miss rate for demand accesses
2835 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for demand accesses
2836 system.l2c.demand_miss_rate::total 0.315904 # miss rate for demand accesses
2837 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for overall accesses
2838 system.l2c.overall_miss_rate::cpu0.itb.walker 0.290944 # miss rate for overall accesses
2839 system.l2c.overall_miss_rate::cpu0.inst 0.097473 # miss rate for overall accesses
2840 system.l2c.overall_miss_rate::cpu0.data 0.461164 # miss rate for overall accesses
2841 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for overall accesses
2842 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for overall accesses
2843 system.l2c.overall_miss_rate::cpu1.itb.walker 0.190899 # miss rate for overall accesses
2844 system.l2c.overall_miss_rate::cpu1.inst 0.091926 # miss rate for overall accesses
2845 system.l2c.overall_miss_rate::cpu1.data 0.255422 # miss rate for overall accesses
2846 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for overall accesses
2847 system.l2c.overall_miss_rate::total 0.315904 # miss rate for overall accesses
2848 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14741.797929 # average UpgradeReq miss latency
2849 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16960.661206 # average UpgradeReq miss latency
2850 system.l2c.UpgradeReq_avg_miss_latency::total 15760.797555 # average UpgradeReq miss latency
2851 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13236.753372 # average SCUpgradeReq miss latency
2852 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15447.203559 # average SCUpgradeReq miss latency
2853 system.l2c.SCUpgradeReq_avg_miss_latency::total 14189.775307 # average SCUpgradeReq miss latency
2854 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132211.786818 # average ReadExReq miss latency
2855 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130854.507395 # average ReadExReq miss latency
2856 system.l2c.ReadExReq_avg_miss_latency::total 131891.722520 # average ReadExReq miss latency
2857 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average ReadSharedReq miss latency
2858 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 137885.106383 # average ReadSharedReq miss latency
2859 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134408.386315 # average ReadSharedReq miss latency
2860 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136746.547722 # average ReadSharedReq miss latency
2861 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average ReadSharedReq miss latency
2862 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average ReadSharedReq miss latency
2863 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141900.098912 # average ReadSharedReq miss latency
2864 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134699.845181 # average ReadSharedReq miss latency
2865 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138817.701804 # average ReadSharedReq miss latency
2866 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average ReadSharedReq miss latency
2867 system.l2c.ReadSharedReq_avg_miss_latency::total 150239.125640 # average ReadSharedReq miss latency
2868 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average overall miss latency
2869 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137885.106383 # average overall miss latency
2870 system.l2c.demand_avg_miss_latency::cpu0.inst 134408.386315 # average overall miss latency
2871 system.l2c.demand_avg_miss_latency::cpu0.data 133212.648337 # average overall miss latency
2872 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average overall miss latency
2873 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average overall miss latency
2874 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141900.098912 # average overall miss latency
2875 system.l2c.demand_avg_miss_latency::cpu1.inst 134699.845181 # average overall miss latency
2876 system.l2c.demand_avg_miss_latency::cpu1.data 133490.253561 # average overall miss latency
2877 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average overall miss latency
2878 system.l2c.demand_avg_miss_latency::total 141195.273673 # average overall miss latency
2879 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average overall miss latency
2880 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137885.106383 # average overall miss latency
2881 system.l2c.overall_avg_miss_latency::cpu0.inst 134408.386315 # average overall miss latency
2882 system.l2c.overall_avg_miss_latency::cpu0.data 133212.648337 # average overall miss latency
2883 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average overall miss latency
2884 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average overall miss latency
2885 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141900.098912 # average overall miss latency
2886 system.l2c.overall_avg_miss_latency::cpu1.inst 134699.845181 # average overall miss latency
2887 system.l2c.overall_avg_miss_latency::cpu1.data 133490.253561 # average overall miss latency
2888 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average overall miss latency
2889 system.l2c.overall_avg_miss_latency::total 141195.273673 # average overall miss latency
2890 system.l2c.blocked_cycles::no_mshrs 366 # number of cycles access was blocked
2891 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2892 system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked
2893 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2894 system.l2c.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked
2895 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2896 system.l2c.fast_writes 0 # number of fast writes performed
2897 system.l2c.cache_copies 0 # number of cache copies performed
2898 system.l2c.writebacks::writebacks 971265 # number of writebacks
2899 system.l2c.writebacks::total 971265 # number of writebacks
2900 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 78 # number of ReadSharedReq MSHR hits
2901 system.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits
2902 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 112 # number of ReadSharedReq MSHR hits
2903 system.l2c.ReadSharedReq_mshr_hits::cpu1.data 26 # number of ReadSharedReq MSHR hits
2904 system.l2c.ReadSharedReq_mshr_hits::total 224 # number of ReadSharedReq MSHR hits
2905 system.l2c.demand_mshr_hits::cpu0.inst 78 # number of demand (read+write) MSHR hits
2906 system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits
2907 system.l2c.demand_mshr_hits::cpu1.inst 112 # number of demand (read+write) MSHR hits
2908 system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits
2909 system.l2c.demand_mshr_hits::total 224 # number of demand (read+write) MSHR hits
2910 system.l2c.overall_mshr_hits::cpu0.inst 78 # number of overall MSHR hits
2911 system.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits
2912 system.l2c.overall_mshr_hits::cpu1.inst 112 # number of overall MSHR hits
2913 system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits
2914 system.l2c.overall_mshr_hits::total 224 # number of overall MSHR hits
2915 system.l2c.CleanEvict_mshr_misses::writebacks 38370 # number of CleanEvict MSHR misses
2916 system.l2c.CleanEvict_mshr_misses::total 38370 # number of CleanEvict MSHR misses
2917 system.l2c.UpgradeReq_mshr_misses::cpu0.data 67422 # number of UpgradeReq MSHR misses
2918 system.l2c.UpgradeReq_mshr_misses::cpu1.data 57259 # number of UpgradeReq MSHR misses
2919 system.l2c.UpgradeReq_mshr_misses::total 124681 # number of UpgradeReq MSHR misses
2920 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 14532 # number of SCUpgradeReq MSHR misses
2921 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11014 # number of SCUpgradeReq MSHR misses
2922 system.l2c.SCUpgradeReq_mshr_misses::total 25546 # number of SCUpgradeReq MSHR misses
2923 system.l2c.ReadExReq_mshr_misses::cpu0.data 480698 # number of ReadExReq MSHR misses
2924 system.l2c.ReadExReq_mshr_misses::cpu1.data 148334 # number of ReadExReq MSHR misses
2925 system.l2c.ReadExReq_mshr_misses::total 629032 # number of ReadExReq MSHR misses
2926 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1519 # number of ReadSharedReq MSHR misses
2927 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1645 # number of ReadSharedReq MSHR misses
2928 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 46951 # number of ReadSharedReq MSHR misses
2929 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 136134 # number of ReadSharedReq MSHR misses
2930 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 207239 # number of ReadSharedReq MSHR misses
2931 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1062 # number of ReadSharedReq MSHR misses
2932 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1011 # number of ReadSharedReq MSHR misses
2933 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 38643 # number of ReadSharedReq MSHR misses
2934 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 73362 # number of ReadSharedReq MSHR misses
2935 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 139305 # number of ReadSharedReq MSHR misses
2936 system.l2c.ReadSharedReq_mshr_misses::total 646871 # number of ReadSharedReq MSHR misses
2937 system.l2c.demand_mshr_misses::cpu0.dtb.walker 1519 # number of demand (read+write) MSHR misses
2938 system.l2c.demand_mshr_misses::cpu0.itb.walker 1645 # number of demand (read+write) MSHR misses
2939 system.l2c.demand_mshr_misses::cpu0.inst 46951 # number of demand (read+write) MSHR misses
2940 system.l2c.demand_mshr_misses::cpu0.data 616832 # number of demand (read+write) MSHR misses
2941 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 207239 # number of demand (read+write) MSHR misses
2942 system.l2c.demand_mshr_misses::cpu1.dtb.walker 1062 # number of demand (read+write) MSHR misses
2943 system.l2c.demand_mshr_misses::cpu1.itb.walker 1011 # number of demand (read+write) MSHR misses
2944 system.l2c.demand_mshr_misses::cpu1.inst 38643 # number of demand (read+write) MSHR misses
2945 system.l2c.demand_mshr_misses::cpu1.data 221696 # number of demand (read+write) MSHR misses
2946 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 139305 # number of demand (read+write) MSHR misses
2947 system.l2c.demand_mshr_misses::total 1275903 # number of demand (read+write) MSHR misses
2948 system.l2c.overall_mshr_misses::cpu0.dtb.walker 1519 # number of overall MSHR misses
2949 system.l2c.overall_mshr_misses::cpu0.itb.walker 1645 # number of overall MSHR misses
2950 system.l2c.overall_mshr_misses::cpu0.inst 46951 # number of overall MSHR misses
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2953 system.l2c.overall_mshr_misses::cpu1.dtb.walker 1062 # number of overall MSHR misses
2954 system.l2c.overall_mshr_misses::cpu1.itb.walker 1011 # number of overall MSHR misses
2955 system.l2c.overall_mshr_misses::cpu1.inst 38643 # number of overall MSHR misses
2956 system.l2c.overall_mshr_misses::cpu1.data 221696 # number of overall MSHR misses
2957 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 139305 # number of overall MSHR misses
2958 system.l2c.overall_mshr_misses::total 1275903 # number of overall MSHR misses
2959 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
2960 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable
2961 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2962 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23609 # number of ReadReq MSHR uncacheable
2963 system.l2c.ReadReq_mshr_uncacheable::total 82463 # number of ReadReq MSHR uncacheable
2964 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable
2965 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable
2966 system.l2c.WriteReq_mshr_uncacheable::total 39099 # number of WriteReq MSHR uncacheable
2967 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
2968 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses
2969 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2970 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 46229 # number of overall MSHR uncacheable misses
2971 system.l2c.overall_mshr_uncacheable_misses::total 121562 # number of overall MSHR uncacheable misses
2972 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4976293000 # number of UpgradeReq MSHR miss cycles
2973 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4208598500 # number of UpgradeReq MSHR miss cycles
2974 system.l2c.UpgradeReq_mshr_miss_latency::total 9184891500 # number of UpgradeReq MSHR miss cycles
2975 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1113938500 # number of SCUpgradeReq MSHR miss cycles
2976 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 842688500 # number of SCUpgradeReq MSHR miss cycles
2977 system.l2c.SCUpgradeReq_mshr_miss_latency::total 1956627000 # number of SCUpgradeReq MSHR miss cycles
2978 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 58746961500 # number of ReadExReq MSHR miss cycles
2979 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17926832500 # number of ReadExReq MSHR miss cycles
2980 system.l2c.ReadExReq_mshr_miss_latency::total 76673794000 # number of ReadExReq MSHR miss cycles
2981 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 194917500 # number of ReadSharedReq MSHR miss cycles
2982 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 210371000 # number of ReadSharedReq MSHR miss cycles
2983 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5842188000 # number of ReadSharedReq MSHR miss cycles
2984 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17254770500 # number of ReadSharedReq MSHR miss cycles
2985 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 31323421187 # number of ReadSharedReq MSHR miss cycles
2986 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 135433000 # number of ReadSharedReq MSHR miss cycles
2987 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 133351000 # number of ReadSharedReq MSHR miss cycles
2988 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4820369500 # number of ReadSharedReq MSHR miss cycles
2989 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9450937500 # number of ReadSharedReq MSHR miss cycles
2990 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21357796819 # number of ReadSharedReq MSHR miss cycles
2991 system.l2c.ReadSharedReq_mshr_miss_latency::total 90723556006 # number of ReadSharedReq MSHR miss cycles
2992 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 194917500 # number of demand (read+write) MSHR miss cycles
2993 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 210371000 # number of demand (read+write) MSHR miss cycles
2994 system.l2c.demand_mshr_miss_latency::cpu0.inst 5842188000 # number of demand (read+write) MSHR miss cycles
2995 system.l2c.demand_mshr_miss_latency::cpu0.data 76001732000 # number of demand (read+write) MSHR miss cycles
2996 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 31323421187 # number of demand (read+write) MSHR miss cycles
2997 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 135433000 # number of demand (read+write) MSHR miss cycles
2998 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 133351000 # number of demand (read+write) MSHR miss cycles
2999 system.l2c.demand_mshr_miss_latency::cpu1.inst 4820369500 # number of demand (read+write) MSHR miss cycles
3000 system.l2c.demand_mshr_miss_latency::cpu1.data 27377770000 # number of demand (read+write) MSHR miss cycles
3001 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21357796819 # number of demand (read+write) MSHR miss cycles
3002 system.l2c.demand_mshr_miss_latency::total 167397350006 # number of demand (read+write) MSHR miss cycles
3003 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 194917500 # number of overall MSHR miss cycles
3004 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 210371000 # number of overall MSHR miss cycles
3005 system.l2c.overall_mshr_miss_latency::cpu0.inst 5842188000 # number of overall MSHR miss cycles
3006 system.l2c.overall_mshr_miss_latency::cpu0.data 76001732000 # number of overall MSHR miss cycles
3007 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31323421187 # number of overall MSHR miss cycles
3008 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 135433000 # number of overall MSHR miss cycles
3009 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 133351000 # number of overall MSHR miss cycles
3010 system.l2c.overall_mshr_miss_latency::cpu1.inst 4820369500 # number of overall MSHR miss cycles
3011 system.l2c.overall_mshr_miss_latency::cpu1.data 27377770000 # number of overall MSHR miss cycles
3012 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21357796819 # number of overall MSHR miss cycles
3013 system.l2c.overall_mshr_miss_latency::total 167397350006 # number of overall MSHR miss cycles
3014 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles
3015 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2284412000 # number of ReadReq MSHR uncacheable cycles
3016 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11994000 # number of ReadReq MSHR uncacheable cycles
3017 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3673036000 # number of ReadReq MSHR uncacheable cycles
3018 system.l2c.ReadReq_mshr_uncacheable_latency::total 10823963000 # number of ReadReq MSHR uncacheable cycles
3019 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2391400000 # number of WriteReq MSHR uncacheable cycles
3020 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3605950000 # number of WriteReq MSHR uncacheable cycles
3021 system.l2c.WriteReq_mshr_uncacheable_latency::total 5997350000 # number of WriteReq MSHR uncacheable cycles
3022 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles
3023 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4675812000 # number of overall MSHR uncacheable cycles
3024 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11994000 # number of overall MSHR uncacheable cycles
3025 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7278986000 # number of overall MSHR uncacheable cycles
3026 system.l2c.overall_mshr_uncacheable_latency::total 16821313000 # number of overall MSHR uncacheable cycles
3027 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3028 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3029 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.287738 # mshr miss rate for UpgradeReq accesses
3030 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.334420 # mshr miss rate for UpgradeReq accesses
3031 system.l2c.UpgradeReq_mshr_miss_rate::total 0.307447 # mshr miss rate for UpgradeReq accesses
3032 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.272099 # mshr miss rate for SCUpgradeReq accesses
3033 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.243344 # mshr miss rate for SCUpgradeReq accesses
3034 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.258909 # mshr miss rate for SCUpgradeReq accesses
3035 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.752238 # mshr miss rate for ReadExReq accesses
3036 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.471578 # mshr miss rate for ReadExReq accesses
3037 system.l2c.ReadExReq_mshr_miss_rate::total 0.659659 # mshr miss rate for ReadExReq accesses
3038 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.226379 # mshr miss rate for ReadSharedReq accesses
3039 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.290944 # mshr miss rate for ReadSharedReq accesses
3040 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097312 # mshr miss rate for ReadSharedReq accesses
3041 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.194882 # mshr miss rate for ReadSharedReq accesses
3042 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for ReadSharedReq accesses
3043 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for ReadSharedReq accesses
3044 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for ReadSharedReq accesses
3045 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for ReadSharedReq accesses
3046 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.132539 # mshr miss rate for ReadSharedReq accesses
3047 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for ReadSharedReq accesses
3048 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209612 # mshr miss rate for ReadSharedReq accesses
3049 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.226379 # mshr miss rate for demand accesses
3050 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.290944 # mshr miss rate for demand accesses
3051 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097312 # mshr miss rate for demand accesses
3052 system.l2c.demand_mshr_miss_rate::cpu0.data 0.461158 # mshr miss rate for demand accesses
3053 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for demand accesses
3054 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for demand accesses
3055 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for demand accesses
3056 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for demand accesses
3057 system.l2c.demand_mshr_miss_rate::cpu1.data 0.255392 # mshr miss rate for demand accesses
3058 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for demand accesses
3059 system.l2c.demand_mshr_miss_rate::total 0.315848 # mshr miss rate for demand accesses
3060 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.226379 # mshr miss rate for overall accesses
3061 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.290944 # mshr miss rate for overall accesses
3062 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097312 # mshr miss rate for overall accesses
3063 system.l2c.overall_mshr_miss_rate::cpu0.data 0.461158 # mshr miss rate for overall accesses
3064 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for overall accesses
3065 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for overall accesses
3066 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for overall accesses
3067 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for overall accesses
3068 system.l2c.overall_mshr_miss_rate::cpu1.data 0.255392 # mshr miss rate for overall accesses
3069 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for overall accesses
3070 system.l2c.overall_mshr_miss_rate::total 0.315848 # mshr miss rate for overall accesses
3071 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73808.148676 # average UpgradeReq mshr miss latency
3072 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73501.082799 # average UpgradeReq mshr miss latency
3073 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73667.130517 # average UpgradeReq mshr miss latency
3074 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76654.176989 # average SCUpgradeReq mshr miss latency
3075 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76510.668240 # average SCUpgradeReq mshr miss latency
3076 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76592.304079 # average SCUpgradeReq mshr miss latency
3077 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122211.786818 # average ReadExReq mshr miss latency
3078 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120854.507395 # average ReadExReq mshr miss latency
3079 system.l2c.ReadExReq_avg_mshr_miss_latency::total 121891.722520 # average ReadExReq mshr miss latency
3080 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average ReadSharedReq mshr miss latency
3081 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average ReadSharedReq mshr miss latency
3082 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average ReadSharedReq mshr miss latency
3083 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126748.428019 # average ReadSharedReq mshr miss latency
3084 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average ReadSharedReq mshr miss latency
3085 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average ReadSharedReq mshr miss latency
3086 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average ReadSharedReq mshr miss latency
3087 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average ReadSharedReq mshr miss latency
3088 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128826.061176 # average ReadSharedReq mshr miss latency
3089 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average ReadSharedReq mshr miss latency
3090 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140249.842714 # average ReadSharedReq mshr miss latency
3091 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency
3092 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency
3093 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency
3094 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency
3095 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency
3096 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency
3097 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency
3098 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency
3099 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency
3100 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency
3101 system.l2c.demand_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency
3102 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency
3103 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency
3104 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency
3105 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency
3106 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency
3107 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency
3108 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency
3109 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency
3110 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency
3111 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency
3112 system.l2c.overall_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency
3113 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency
3114 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276 # average ReadReq mshr uncacheable latency
3115 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency
3116 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132 # average ReadReq mshr uncacheable latency
3117 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927 # average ReadReq mshr uncacheable latency
3118 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007 # average WriteReq mshr uncacheable latency
3119 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190 # average WriteReq mshr uncacheable latency
3120 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474 # average WriteReq mshr uncacheable latency
3121 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency
3122 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433 # average overall mshr uncacheable latency
3123 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency
3124 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150 # average overall mshr uncacheable latency
3125 system.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746 # average overall mshr uncacheable latency
3126 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3127 system.membus.trans_dist::ReadReq 82463 # Transaction distribution
3128 system.membus.trans_dist::ReadResp 738269 # Transaction distribution
3129 system.membus.trans_dist::WriteReq 39099 # Transaction distribution
3130 system.membus.trans_dist::WriteResp 39099 # Transaction distribution
3131 system.membus.trans_dist::WritebackDirty 1078222 # Transaction distribution
3132 system.membus.trans_dist::CleanEvict 196131 # Transaction distribution
3133 system.membus.trans_dist::UpgradeReq 410883 # Transaction distribution
3134 system.membus.trans_dist::SCUpgradeReq 321341 # Transaction distribution
3135 system.membus.trans_dist::UpgradeResp 158448 # Transaction distribution
3136 system.membus.trans_dist::ReadExReq 644070 # Transaction distribution
3137 system.membus.trans_dist::ReadExResp 620815 # Transaction distribution
3138 system.membus.trans_dist::ReadSharedReq 655806 # Transaction distribution
3139 system.membus.trans_dist::InvalidateReq 106983 # Transaction distribution
3140 system.membus.trans_dist::InvalidateResp 106983 # Transaction distribution
3141 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123128 # Packet count per connected master and slave (bytes)
3142 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3143 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28306 # Packet count per connected master and slave (bytes)
3144 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4701222 # Packet count per connected master and slave (bytes)
3145 system.membus.pkt_count_system.l2c.mem_side::total 4852748 # Packet count per connected master and slave (bytes)
3146 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342712 # Packet count per connected master and slave (bytes)
3147 system.membus.pkt_count_system.iocache.mem_side::total 342712 # Packet count per connected master and slave (bytes)
3148 system.membus.pkt_count::total 5195460 # Packet count per connected master and slave (bytes)
3149 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156143 # Cumulative packet size per connected master and slave (bytes)
3150 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3151 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56612 # Cumulative packet size per connected master and slave (bytes)
3152 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143440556 # Cumulative packet size per connected master and slave (bytes)
3153 system.membus.pkt_size_system.l2c.mem_side::total 143653515 # Cumulative packet size per connected master and slave (bytes)
3154 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262336 # Cumulative packet size per connected master and slave (bytes)
3155 system.membus.pkt_size_system.iocache.mem_side::total 7262336 # Cumulative packet size per connected master and slave (bytes)
3156 system.membus.pkt_size::total 150915851 # Cumulative packet size per connected master and slave (bytes)
3157 system.membus.snoops 600183 # Total snoops (count)
3158 system.membus.snoop_fanout::samples 3537604 # Request fanout histogram
3159 system.membus.snoop_fanout::mean 1 # Request fanout histogram
3160 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3161 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3162 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3163 system.membus.snoop_fanout::1 3537604 100.00% 100.00% # Request fanout histogram
3164 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3165 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3166 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3167 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3168 system.membus.snoop_fanout::total 3537604 # Request fanout histogram
3169 system.membus.reqLayer0.occupancy 101645000 # Layer occupancy (ticks)
3170 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3171 system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3172 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3173 system.membus.reqLayer2.occupancy 23516499 # Layer occupancy (ticks)
3174 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3175 system.membus.reqLayer5.occupancy 7437675124 # Layer occupancy (ticks)
3176 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3177 system.membus.respLayer2.occupancy 7217345032 # Layer occupancy (ticks)
3178 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3179 system.membus.respLayer3.occupancy 228825593 # Layer occupancy (ticks)
3180 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3181 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3182 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3183 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3184 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3185 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3186 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3187 system.realview.ethernet.txBytes 966 # Bytes Transmitted
3188 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3189 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3190 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3191 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3192 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3193 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3194 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3195 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3196 system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s)
3197 system.realview.ethernet.totPackets 3 # Total Packets
3198 system.realview.ethernet.totBytes 966 # Total Bytes
3199 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
3200 system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s)
3201 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
3202 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3203 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
3204 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3205 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3206 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
3207 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3208 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3209 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
3210 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3211 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3212 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
3213 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3214 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3215 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
3216 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3217 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3218 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
3219 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3220 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3221 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3222 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3223 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3224 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3225 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3226 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3227 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3228 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3229 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3230 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3231 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3232 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3233 system.toL2Bus.snoop_filter.tot_requests 10517449 # Total number of requests made to the snoop filter.
3234 system.toL2Bus.snoop_filter.hit_single_requests 5725465 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3235 system.toL2Bus.snoop_filter.hit_multi_requests 1766756 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3236 system.toL2Bus.snoop_filter.tot_snoops 114752 # Total number of snoops made to the snoop filter.
3237 system.toL2Bus.snoop_filter.hit_single_snoops 104186 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3238 system.toL2Bus.snoop_filter.hit_multi_snoops 10566 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3239 system.toL2Bus.trans_dist::ReadReq 82465 # Transaction distribution
3240 system.toL2Bus.trans_dist::ReadResp 3940978 # Transaction distribution
3241 system.toL2Bus.trans_dist::WriteReq 39099 # Transaction distribution
3242 system.toL2Bus.trans_dist::WriteResp 39099 # Transaction distribution
3243 system.toL2Bus.trans_dist::WritebackDirty 3582727 # Transaction distribution
3244 system.toL2Bus.trans_dist::CleanEvict 1240251 # Transaction distribution
3245 system.toL2Bus.trans_dist::UpgradeReq 683521 # Transaction distribution
3246 system.toL2Bus.trans_dist::SCUpgradeReq 394463 # Transaction distribution
3247 system.toL2Bus.trans_dist::UpgradeResp 1077983 # Transaction distribution
3248 system.toL2Bus.trans_dist::SCUpgradeFailReq 128 # Transaction distribution
3249 system.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution
3250 system.toL2Bus.trans_dist::ReadExReq 1083401 # Transaction distribution
3251 system.toL2Bus.trans_dist::ReadExResp 1083400 # Transaction distribution
3252 system.toL2Bus.trans_dist::ReadSharedReq 3865739 # Transaction distribution
3253 system.toL2Bus.trans_dist::InvalidateReq 106983 # Transaction distribution
3254 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8168699 # Packet count per connected master and slave (bytes)
3255 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6135080 # Packet count per connected master and slave (bytes)
3256 system.toL2Bus.pkt_count::total 14303779 # Packet count per connected master and slave (bytes)
3257 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 247232417 # Cumulative packet size per connected master and slave (bytes)
3258 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 172105066 # Cumulative packet size per connected master and slave (bytes)
3259 system.toL2Bus.pkt_size::total 419337483 # Cumulative packet size per connected master and slave (bytes)
3260 system.toL2Bus.snoops 2918298 # Total snoops (count)
3261 system.toL2Bus.snoop_fanout::samples 7581961 # Request fanout histogram
3262 system.toL2Bus.snoop_fanout::mean 0.362851 # Request fanout histogram
3263 system.toL2Bus.snoop_fanout::stdev 0.483712 # Request fanout histogram
3264 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3265 system.toL2Bus.snoop_fanout::0 4841404 63.85% 63.85% # Request fanout histogram
3266 system.toL2Bus.snoop_fanout::1 2729991 36.01% 99.86% # Request fanout histogram
3267 system.toL2Bus.snoop_fanout::2 10566 0.14% 100.00% # Request fanout histogram
3268 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3269 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3270 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3271 system.toL2Bus.snoop_fanout::total 7581961 # Request fanout histogram
3272 system.toL2Bus.reqLayer0.occupancy 8230397518 # Layer occupancy (ticks)
3273 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3274 system.toL2Bus.snoopLayer0.occupancy 2646637 # Layer occupancy (ticks)
3275 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3276 system.toL2Bus.respLayer0.occupancy 4512530115 # Layer occupancy (ticks)
3277 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3278 system.toL2Bus.respLayer1.occupancy 3554923231 # Layer occupancy (ticks)
3279 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3281 ---------- End Simulation Statistics ----------
projects / gem5.git / blob