2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 47.403575 # Number of seconds simulated
4 sim_ticks 47403574916500 # Number of ticks simulated
5 final_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 473223 # Simulator instruction rate (inst/s)
8 host_op_rate 556671 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 25492174892 # Simulator tick rate (ticks/s)
10 host_mem_usage 749540 # Number of bytes of host memory used
11 host_seconds 1859.53 # Real time elapsed on the host
12 sim_insts 879974755 # Number of instructions simulated
13 sim_ops 1035148021 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
17 system.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory
26 system.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory
27 system.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory
28 system.physmem.bytes_read::total 56576516 # Number of bytes read from this memory
29 system.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory
31 system.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory
32 system.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory
33 system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34 system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35 system.physmem.bytes_written::total 75204968 # Number of bytes written to this memory
36 system.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory
46 system.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory
47 system.physmem.num_reads::total 924529 # Number of read requests responded to by this memory
48 system.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory
49 system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50 system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51 system.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory
52 system.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s)
58 system.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s)
59 system.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s)
60 system.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s)
61 system.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s)
62 system.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s)
63 system.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s)
65 system.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s)
66 system.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s)
67 system.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s)
68 system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69 system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70 system.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s)
71 system.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s)
76 system.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s)
77 system.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s)
78 system.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s)
79 system.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s)
80 system.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s)
81 system.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s)
82 system.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s)
83 system.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s)
84 system.physmem.readReqs 924529 # Number of read requests accepted
85 system.physmem.writeReqs 1177330 # Number of write requests accepted
86 system.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue
87 system.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue
88 system.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM
89 system.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue
90 system.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM
91 system.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side
92 system.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side
93 system.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue
94 system.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one
95 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96 system.physmem.perBankRdBursts::0 51848 # Per bank write bursts
97 system.physmem.perBankRdBursts::1 60547 # Per bank write bursts
98 system.physmem.perBankRdBursts::2 52943 # Per bank write bursts
99 system.physmem.perBankRdBursts::3 59873 # Per bank write bursts
100 system.physmem.perBankRdBursts::4 53995 # Per bank write bursts
101 system.physmem.perBankRdBursts::5 59394 # Per bank write bursts
102 system.physmem.perBankRdBursts::6 55656 # Per bank write bursts
103 system.physmem.perBankRdBursts::7 56350 # Per bank write bursts
104 system.physmem.perBankRdBursts::8 47470 # Per bank write bursts
105 system.physmem.perBankRdBursts::9 98045 # Per bank write bursts
106 system.physmem.perBankRdBursts::10 51346 # Per bank write bursts
107 system.physmem.perBankRdBursts::11 58216 # Per bank write bursts
108 system.physmem.perBankRdBursts::12 52575 # Per bank write bursts
109 system.physmem.perBankRdBursts::13 60842 # Per bank write bursts
110 system.physmem.perBankRdBursts::14 50185 # Per bank write bursts
111 system.physmem.perBankRdBursts::15 54822 # Per bank write bursts
112 system.physmem.perBankWrBursts::0 69717 # Per bank write bursts
113 system.physmem.perBankWrBursts::1 76530 # Per bank write bursts
114 system.physmem.perBankWrBursts::2 71410 # Per bank write bursts
115 system.physmem.perBankWrBursts::3 77292 # Per bank write bursts
116 system.physmem.perBankWrBursts::4 71372 # Per bank write bursts
117 system.physmem.perBankWrBursts::5 75019 # Per bank write bursts
118 system.physmem.perBankWrBursts::6 75211 # Per bank write bursts
119 system.physmem.perBankWrBursts::7 75617 # Per bank write bursts
120 system.physmem.perBankWrBursts::8 67898 # Per bank write bursts
121 system.physmem.perBankWrBursts::9 76939 # Per bank write bursts
122 system.physmem.perBankWrBursts::10 70016 # Per bank write bursts
123 system.physmem.perBankWrBursts::11 75357 # Per bank write bursts
124 system.physmem.perBankWrBursts::12 71664 # Per bank write bursts
125 system.physmem.perBankWrBursts::13 78615 # Per bank write bursts
126 system.physmem.perBankWrBursts::14 70257 # Per bank write bursts
127 system.physmem.perBankWrBursts::15 72133 # Per bank write bursts
128 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129 system.physmem.numWrRetry 33 # Number of times write queue was full causing retry
130 system.physmem.totGap 47403571626000 # Total gap between requests
131 system.physmem.readPktSize::0 0 # Read request sizes (log2)
132 system.physmem.readPktSize::1 0 # Read request sizes (log2)
133 system.physmem.readPktSize::2 43195 # Read request sizes (log2)
134 system.physmem.readPktSize::3 25 # Read request sizes (log2)
135 system.physmem.readPktSize::4 5 # Read request sizes (log2)
136 system.physmem.readPktSize::5 0 # Read request sizes (log2)
137 system.physmem.readPktSize::6 881304 # Read request sizes (log2)
138 system.physmem.writePktSize::0 0 # Write request sizes (log2)
139 system.physmem.writePktSize::1 0 # Write request sizes (log2)
140 system.physmem.writePktSize::2 2 # Write request sizes (log2)
141 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142 system.physmem.writePktSize::4 0 # Write request sizes (log2)
143 system.physmem.writePktSize::5 0 # Write request sizes (log2)
144 system.physmem.writePktSize::6 1174756 # Write request sizes (log2)
145 system.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
168 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
169 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
176 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
177 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::29 77885 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::30 70974 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::31 65826 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::32 63695 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::34 1650 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::35 1244 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::36 937 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::37 692 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::38 576 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::39 555 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::40 407 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::41 403 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see
240 system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see
241 system.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation
255 system.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes
256 system.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes
257 system.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes
258 system.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes
259 system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
260 system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
261 system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
262 system.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes
263 system.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
299 system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads
300 system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
301 system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
302 system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
303 system.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads
304 system.physmem.totQLat 29056215697 # Total ticks spent queuing
305 system.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM
306 system.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers
307 system.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst
308 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
309 system.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst
310 system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
311 system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s
312 system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
313 system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s
314 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
315 system.physmem.busUtil 0.02 # Data bus utilization in percentage
316 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
317 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
318 system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
319 system.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing
320 system.physmem.readRowHits 688543 # Number of row buffer hits during reads
321 system.physmem.writeRowHits 439987 # Number of row buffer hits during writes
322 system.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads
323 system.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes
324 system.physmem.avgGap 22553164.43 # Average gap between requests
325 system.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined
326 system.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ)
327 system.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ)
328 system.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ)
329 system.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ)
330 system.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ)
331 system.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ)
332 system.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ)
333 system.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ)
334 system.physmem_0.averagePower 668.669411 # Core power per rank (mW)
335 system.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states
336 system.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states
337 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
338 system.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states
339 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
340 system.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ)
341 system.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ)
342 system.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ)
343 system.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ)
344 system.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ)
345 system.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ)
346 system.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ)
347 system.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ)
348 system.physmem_1.averagePower 668.683580 # Core power per rank (mW)
349 system.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states
350 system.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states
351 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
352 system.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states
353 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
354 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
355 system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
356 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
357 system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
358 system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
359 system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
360 system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
361 system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
362 system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
363 system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
364 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
365 system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
366 system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
367 system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
368 system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
369 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
370 system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
371 system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
372 system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
373 system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
374 system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
375 system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
376 system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
377 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
378 system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
379 system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
380 system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
381 system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
382 system.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
383 system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
384 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
385 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
386 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
387 system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
388 system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
389 system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
390 system.cpu_clk_domain.clock 500 # Clock period in ticks
391 system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
392 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
393 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
394 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
395 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
396 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
397 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
398 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
399 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
400 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
401 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
402 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
403 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
404 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
405 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
406 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
407 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
408 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
409 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
410 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
411 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
412 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
413 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
414 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
415 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
416 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
417 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
418 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
419 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
420 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
421 system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
422 system.cpu0.dtb.walker.walks 114038 # Table walker walks requested
423 system.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors
424 system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate
425 system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate
426 system.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting
427 system.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency
428 system.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency
429 system.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency
430 system.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency
431 system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
432 system.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency
433 system.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency
434 system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency
435 system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency
436 system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency
437 system.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency
438 system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency
439 system.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency
440 system.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency
441 system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency
442 system.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency
443 system.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency
444 system.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency
445 system.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency
446 system.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency
447 system.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
448 system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
449 system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
450 system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
451 system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
452 system.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency
453 system.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution
454 system.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution
455 system.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution
456 system.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution
457 system.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution
458 system.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated
459 system.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated
460 system.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated
461 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst
462 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
463 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst
464 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst
465 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
466 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst
467 system.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst
468 system.cpu0.dtb.inst_hits 0 # ITB inst hits
469 system.cpu0.dtb.inst_misses 0 # ITB inst misses
470 system.cpu0.dtb.read_hits 86092375 # DTB read hits
471 system.cpu0.dtb.read_misses 87013 # DTB read misses
472 system.cpu0.dtb.write_hits 77928513 # DTB write hits
473 system.cpu0.dtb.write_misses 27025 # DTB write misses
474 system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
475 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
476 system.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
477 system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
478 system.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB
479 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
480 system.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch
481 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
482 system.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions
483 system.cpu0.dtb.read_accesses 86179388 # DTB read accesses
484 system.cpu0.dtb.write_accesses 77955538 # DTB write accesses
485 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
486 system.cpu0.dtb.hits 164020888 # DTB hits
487 system.cpu0.dtb.misses 114038 # DTB misses
488 system.cpu0.dtb.accesses 164134926 # DTB accesses
489 system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
490 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
491 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
492 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
493 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
494 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
495 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
496 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
497 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
498 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
499 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
500 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
501 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
502 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
503 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
504 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
505 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
506 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
507 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
508 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
509 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
510 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
511 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
512 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
513 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
514 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
515 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
516 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
517 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
518 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
519 system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
520 system.cpu0.itb.walker.walks 57747 # Table walker walks requested
521 system.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors
522 system.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate
523 system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate
524 system.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency
525 system.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency
526 system.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency
527 system.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency
528 system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency
529 system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency
530 system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency
531 system.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency
532 system.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency
533 system.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency
534 system.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency
535 system.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency
536 system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency
537 system.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency
538 system.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency
539 system.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency
540 system.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency
541 system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency
542 system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency
543 system.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency
544 system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
545 system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
546 system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
547 system.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency
548 system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution
549 system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution
550 system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution
551 system.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated
552 system.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated
553 system.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated
554 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
555 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst
556 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst
557 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
558 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst
559 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst
560 system.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst
561 system.cpu0.itb.inst_hits 458544228 # ITB inst hits
562 system.cpu0.itb.inst_misses 57747 # ITB inst misses
563 system.cpu0.itb.read_hits 0 # DTB read hits
564 system.cpu0.itb.read_misses 0 # DTB read misses
565 system.cpu0.itb.write_hits 0 # DTB write hits
566 system.cpu0.itb.write_misses 0 # DTB write misses
567 system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
568 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
569 system.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
570 system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
571 system.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB
572 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
573 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
574 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
575 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
576 system.cpu0.itb.read_accesses 0 # DTB read accesses
577 system.cpu0.itb.write_accesses 0 # DTB write accesses
578 system.cpu0.itb.inst_accesses 458601975 # ITB inst accesses
579 system.cpu0.itb.hits 458544228 # DTB hits
580 system.cpu0.itb.misses 57747 # DTB misses
581 system.cpu0.itb.accesses 458601975 # DTB accesses
582 system.cpu0.numPwrStateTransitions 27516 # Number of power state transitions
583 system.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state
584 system.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state
585 system.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state
586 system.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state
587 system.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state
588 system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state
589 system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
590 system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
591 system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state
592 system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state
593 system.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state
594 system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
595 system.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state
596 system.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state
597 system.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states
598 system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states
599 system.cpu0.numCycles 94807149833 # number of cpu cycles simulated
600 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
601 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
602 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
603 system.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed
604 system.cpu0.committedInsts 458270897 # Number of instructions committed
605 system.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed
606 system.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses
607 system.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses
608 system.cpu0.num_func_calls 27507374 # number of times a function call or return occured
609 system.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls
610 system.cpu0.num_int_insts 494447989 # number of integer instructions
611 system.cpu0.num_fp_insts 420942 # number of float instructions
612 system.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read
613 system.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written
614 system.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read
615 system.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written
616 system.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read
617 system.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written
618 system.cpu0.num_mem_refs 164010919 # number of memory refs
619 system.cpu0.num_load_insts 86087147 # Number of load instructions
620 system.cpu0.num_store_insts 77923772 # Number of store instructions
621 system.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles
622 system.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles
623 system.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles
624 system.cpu0.idle_fraction 0.988082 # Percentage of idle cycles
625 system.cpu0.Branches 102213618 # Number of branches fetched
626 system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
627 system.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction
628 system.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction
629 system.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction
630 system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction
631 system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction
632 system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction
633 system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction
634 system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction
635 system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction
636 system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction
637 system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction
638 system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction
639 system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction
640 system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction
641 system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction
642 system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction
643 system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction
644 system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction
645 system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction
646 system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction
647 system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction
648 system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction
649 system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction
650 system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction
651 system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction
652 system.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction
653 system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction
654 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction
655 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction
656 system.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction
657 system.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction
658 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
659 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
660 system.cpu0.op_class::total 538410126 # Class of executed instruction
661 system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
662 system.cpu0.dcache.tags.replacements 5755741 # number of replacements
663 system.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use
664 system.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks.
665 system.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks.
666 system.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks.
667 system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit.
668 system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor
669 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy
670 system.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy
671 system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
672 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
673 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id
674 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
675 system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
676 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
677 system.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses
678 system.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses
679 system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
680 system.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits
681 system.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits
682 system.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits
683 system.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits
684 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits
685 system.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits
686 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits
687 system.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits
688 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits
689 system.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits
690 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits
691 system.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits
692 system.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits
693 system.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits
694 system.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits
695 system.cpu0.dcache.overall_hits::total 153968410 # number of overall hits
696 system.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses
697 system.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses
698 system.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses
699 system.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses
700 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses
701 system.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses
702 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses
703 system.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses
704 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses
705 system.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses
706 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses
707 system.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses
708 system.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses
709 system.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses
710 system.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses
711 system.cpu0.dcache.overall_misses::total 5993812 # number of overall misses
712 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles
713 system.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles
714 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles
715 system.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles
716 system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles
717 system.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles
718 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles
719 system.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles
720 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles
721 system.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles
722 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles
723 system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles
724 system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles
725 system.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles
726 system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles
727 system.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles
728 system.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses)
729 system.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses)
730 system.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses)
731 system.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses)
732 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses)
733 system.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses)
734 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses)
735 system.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses)
736 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses)
737 system.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses)
738 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses)
739 system.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses)
740 system.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses
741 system.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses
742 system.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses
743 system.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses
744 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses
745 system.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses
746 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses
747 system.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses
748 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses
749 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses
750 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses
751 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses
752 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses
753 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses
754 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses
755 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # miss rate for StoreCondReq accesses
756 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033537 # miss rate for demand accesses
757 system.cpu0.dcache.demand_miss_rate::total 0.033537 # miss rate for demand accesses
758 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037470 # miss rate for overall accesses
759 system.cpu0.dcache.overall_miss_rate::total 0.037470 # miss rate for overall accesses
760 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306 # average ReadReq miss latency
761 system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306 # average ReadReq miss latency
762 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948 # average WriteReq miss latency
763 system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948 # average WriteReq miss latency
764 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922 # average WriteLineReq miss latency
765 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922 # average WriteLineReq miss latency
766 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270 # average LoadLockedReq miss latency
767 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency
768 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency
769 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency
770 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
771 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
772 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency
773 system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency
774 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency
775 system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency
776 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
777 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
778 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
779 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
780 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
781 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
782 system.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks
783 system.cpu0.dcache.writebacks::total 5755741 # number of writebacks
784 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits
785 system.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits
786 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits
787 system.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits
788 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits
789 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits
790 system.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits
791 system.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits
792 system.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits
793 system.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits
794 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses
795 system.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses
796 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses
797 system.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses
798 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses
799 system.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses
800 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses
801 system.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses
802 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses
803 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses
804 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses
805 system.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses
806 system.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses
807 system.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses
808 system.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses
809 system.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses
810 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable
811 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable
812 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable
813 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable
814 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses
815 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses
816 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles
817 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles
818 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles
819 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles
820 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles
821 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles
822 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles
823 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles
824 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles
825 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles
826 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles
827 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles
828 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles
829 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles
830 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles
831 system.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles
832 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles
833 system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles
834 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles
835 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles
836 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles
837 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles
838 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses
839 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses
840 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses
841 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses
842 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses
843 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses
844 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses
845 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses
846 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses
847 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses
848 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses
849 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses
850 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses
851 system.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses
852 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses
853 system.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses
854 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency
855 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency
856 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency
857 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency
858 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency
859 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency
860 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency
861 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency
862 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency
863 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency
864 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency
865 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency
866 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
867 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
868 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency
869 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency
870 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency
871 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency
872 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency
873 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency
874 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency
875 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency
876 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
877 system.cpu0.icache.tags.replacements 4916262 # number of replacements
878 system.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use
879 system.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks.
880 system.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks.
881 system.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks.
882 system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit.
883 system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor
884 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy
885 system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy
886 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
887 system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
888 system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
889 system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
890 system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
891 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
892 system.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses
893 system.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses
894 system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
895 system.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits
896 system.cpu0.icache.ReadReq_hits::total 453627454 # number of ReadReq hits
897 system.cpu0.icache.demand_hits::cpu0.inst 453627454 # number of demand (read+write) hits
898 system.cpu0.icache.demand_hits::total 453627454 # number of demand (read+write) hits
899 system.cpu0.icache.overall_hits::cpu0.inst 453627454 # number of overall hits
900 system.cpu0.icache.overall_hits::total 453627454 # number of overall hits
901 system.cpu0.icache.ReadReq_misses::cpu0.inst 4916774 # number of ReadReq misses
902 system.cpu0.icache.ReadReq_misses::total 4916774 # number of ReadReq misses
903 system.cpu0.icache.demand_misses::cpu0.inst 4916774 # number of demand (read+write) misses
904 system.cpu0.icache.demand_misses::total 4916774 # number of demand (read+write) misses
905 system.cpu0.icache.overall_misses::cpu0.inst 4916774 # number of overall misses
906 system.cpu0.icache.overall_misses::total 4916774 # number of overall misses
907 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52276659500 # number of ReadReq miss cycles
908 system.cpu0.icache.ReadReq_miss_latency::total 52276659500 # number of ReadReq miss cycles
909 system.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles
910 system.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles
911 system.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles
912 system.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles
913 system.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses)
914 system.cpu0.icache.ReadReq_accesses::total 458544228 # number of ReadReq accesses(hits+misses)
915 system.cpu0.icache.demand_accesses::cpu0.inst 458544228 # number of demand (read+write) accesses
916 system.cpu0.icache.demand_accesses::total 458544228 # number of demand (read+write) accesses
917 system.cpu0.icache.overall_accesses::cpu0.inst 458544228 # number of overall (read+write) accesses
918 system.cpu0.icache.overall_accesses::total 458544228 # number of overall (read+write) accesses
919 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010723 # miss rate for ReadReq accesses
920 system.cpu0.icache.ReadReq_miss_rate::total 0.010723 # miss rate for ReadReq accesses
921 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010723 # miss rate for demand accesses
922 system.cpu0.icache.demand_miss_rate::total 0.010723 # miss rate for demand accesses
923 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010723 # miss rate for overall accesses
924 system.cpu0.icache.overall_miss_rate::total 0.010723 # miss rate for overall accesses
925 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807 # average ReadReq miss latency
926 system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807 # average ReadReq miss latency
927 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency
928 system.cpu0.icache.demand_avg_miss_latency::total 10632.308807 # average overall miss latency
929 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency
930 system.cpu0.icache.overall_avg_miss_latency::total 10632.308807 # average overall miss latency
931 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
932 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
933 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
934 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
935 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
936 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
937 system.cpu0.icache.writebacks::writebacks 4916262 # number of writebacks
938 system.cpu0.icache.writebacks::total 4916262 # number of writebacks
939 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4916774 # number of ReadReq MSHR misses
940 system.cpu0.icache.ReadReq_mshr_misses::total 4916774 # number of ReadReq MSHR misses
941 system.cpu0.icache.demand_mshr_misses::cpu0.inst 4916774 # number of demand (read+write) MSHR misses
942 system.cpu0.icache.demand_mshr_misses::total 4916774 # number of demand (read+write) MSHR misses
943 system.cpu0.icache.overall_mshr_misses::cpu0.inst 4916774 # number of overall MSHR misses
944 system.cpu0.icache.overall_mshr_misses::total 4916774 # number of overall MSHR misses
945 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
946 system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
947 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
948 system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
949 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 49818272500 # number of ReadReq MSHR miss cycles
950 system.cpu0.icache.ReadReq_mshr_miss_latency::total 49818272500 # number of ReadReq MSHR miss cycles
951 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 49818272500 # number of demand (read+write) MSHR miss cycles
952 system.cpu0.icache.demand_mshr_miss_latency::total 49818272500 # number of demand (read+write) MSHR miss cycles
953 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 49818272500 # number of overall MSHR miss cycles
954 system.cpu0.icache.overall_mshr_miss_latency::total 49818272500 # number of overall MSHR miss cycles
955 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles
956 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles
957 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles
958 system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles
959 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for ReadReq accesses
960 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010723 # mshr miss rate for ReadReq accesses
961 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for demand accesses
962 system.cpu0.icache.demand_mshr_miss_rate::total 0.010723 # mshr miss rate for demand accesses
963 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for overall accesses
964 system.cpu0.icache.overall_mshr_miss_rate::total 0.010723 # mshr miss rate for overall accesses
965 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average ReadReq mshr miss latency
966 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10132.308807 # average ReadReq mshr miss latency
967 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency
968 system.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency
969 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency
970 system.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency
971 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency
972 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency
973 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency
974 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency
975 system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
976 system.cpu0.l2cache.prefetcher.num_hwpf_issued 7829609 # number of hwpf issued
977 system.cpu0.l2cache.prefetcher.pfIdentified 7829625 # number of prefetch candidates identified
978 system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
979 system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
980 system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
981 system.cpu0.l2cache.prefetcher.pfSpanPage 1043159 # number of prefetches not generated due to page crossing
982 system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
983 system.cpu0.l2cache.tags.replacements 2362641 # number of replacements
984 system.cpu0.l2cache.tags.tagsinuse 16162.227513 # Cycle average of tags in use
985 system.cpu0.l2cache.tags.total_refs 14986861 # Total number of references to valid blocks.
986 system.cpu0.l2cache.tags.sampled_refs 2378231 # Sample count of references to valid blocks.
987 system.cpu0.l2cache.tags.avg_refs 6.301684 # Average number of references to valid blocks.
988 system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit.
989 system.cpu0.l2cache.tags.occ_blocks::writebacks 15129.176557 # Average occupied blocks per requestor
990 system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.599278 # Average occupied blocks per requestor
991 system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 80.860024 # Average occupied blocks per requestor
992 system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 896.591654 # Average occupied blocks per requestor
993 system.cpu0.l2cache.tags.occ_percent::writebacks 0.923412 # Average percentage of cache occupancy
994 system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003394 # Average percentage of cache occupancy
995 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004935 # Average percentage of cache occupancy
996 system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054724 # Average percentage of cache occupancy
997 system.cpu0.l2cache.tags.occ_percent::total 0.986464 # Average percentage of cache occupancy
998 system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1593 # Occupied blocks per task id
999 system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
1000 system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13925 # Occupied blocks per task id
1001 system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 258 # Occupied blocks per task id
1002 system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 732 # Occupied blocks per task id
1003 system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 603 # Occupied blocks per task id
1004 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
1005 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id
1006 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
1007 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
1008 system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
1009 system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2612 # Occupied blocks per task id
1010 system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5888 # Occupied blocks per task id
1011 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5210 # Occupied blocks per task id
1012 system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097229 # Percentage of cache occupancy per task id
1013 system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id
1014 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.849915 # Percentage of cache occupancy per task id
1015 system.cpu0.l2cache.tags.tag_accesses 362405390 # Number of tag accesses
1016 system.cpu0.l2cache.tags.data_accesses 362405390 # Number of data accesses
1017 system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1018 system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 268274 # number of ReadReq hits
1019 system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147126 # number of ReadReq hits
1020 system.cpu0.l2cache.ReadReq_hits::total 415400 # number of ReadReq hits
1021 system.cpu0.l2cache.WritebackDirty_hits::writebacks 3821588 # number of WritebackDirty hits
1022 system.cpu0.l2cache.WritebackDirty_hits::total 3821588 # number of WritebackDirty hits
1023 system.cpu0.l2cache.WritebackClean_hits::writebacks 6849535 # number of WritebackClean hits
1024 system.cpu0.l2cache.WritebackClean_hits::total 6849535 # number of WritebackClean hits
1025 system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 548 # number of UpgradeReq hits
1026 system.cpu0.l2cache.UpgradeReq_hits::total 548 # number of UpgradeReq hits
1027 system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933451 # number of ReadExReq hits
1028 system.cpu0.l2cache.ReadExReq_hits::total 933451 # number of ReadExReq hits
1029 system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4462897 # number of ReadCleanReq hits
1030 system.cpu0.l2cache.ReadCleanReq_hits::total 4462897 # number of ReadCleanReq hits
1031 system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2959469 # number of ReadSharedReq hits
1032 system.cpu0.l2cache.ReadSharedReq_hits::total 2959469 # number of ReadSharedReq hits
1033 system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 207284 # number of InvalidateReq hits
1034 system.cpu0.l2cache.InvalidateReq_hits::total 207284 # number of InvalidateReq hits
1035 system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 268274 # number of demand (read+write) hits
1036 system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147126 # number of demand (read+write) hits
1037 system.cpu0.l2cache.demand_hits::cpu0.inst 4462897 # number of demand (read+write) hits
1038 system.cpu0.l2cache.demand_hits::cpu0.data 3892920 # number of demand (read+write) hits
1039 system.cpu0.l2cache.demand_hits::total 8771217 # number of demand (read+write) hits
1040 system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 268274 # number of overall hits
1041 system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147126 # number of overall hits
1042 system.cpu0.l2cache.overall_hits::cpu0.inst 4462897 # number of overall hits
1043 system.cpu0.l2cache.overall_hits::cpu0.data 3892920 # number of overall hits
1044 system.cpu0.l2cache.overall_hits::total 8771217 # number of overall hits
1045 system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10042 # number of ReadReq misses
1046 system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8210 # number of ReadReq misses
1047 system.cpu0.l2cache.ReadReq_misses::total 18252 # number of ReadReq misses
1048 system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 241773 # number of UpgradeReq misses
1049 system.cpu0.l2cache.UpgradeReq_misses::total 241773 # number of UpgradeReq misses
1050 system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190127 # number of SCUpgradeReq misses
1051 system.cpu0.l2cache.SCUpgradeReq_misses::total 190127 # number of SCUpgradeReq misses
1052 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses
1053 system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
1054 system.cpu0.l2cache.ReadExReq_misses::cpu0.data 253021 # number of ReadExReq misses
1055 system.cpu0.l2cache.ReadExReq_misses::total 253021 # number of ReadExReq misses
1056 system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 453877 # number of ReadCleanReq misses
1057 system.cpu0.l2cache.ReadCleanReq_misses::total 453877 # number of ReadCleanReq misses
1058 system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 922445 # number of ReadSharedReq misses
1059 system.cpu0.l2cache.ReadSharedReq_misses::total 922445 # number of ReadSharedReq misses
1060 system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 574180 # number of InvalidateReq misses
1061 system.cpu0.l2cache.InvalidateReq_misses::total 574180 # number of InvalidateReq misses
1062 system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10042 # number of demand (read+write) misses
1063 system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8210 # number of demand (read+write) misses
1064 system.cpu0.l2cache.demand_misses::cpu0.inst 453877 # number of demand (read+write) misses
1065 system.cpu0.l2cache.demand_misses::cpu0.data 1175466 # number of demand (read+write) misses
1066 system.cpu0.l2cache.demand_misses::total 1647595 # number of demand (read+write) misses
1067 system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10042 # number of overall misses
1068 system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8210 # number of overall misses
1069 system.cpu0.l2cache.overall_misses::cpu0.inst 453877 # number of overall misses
1070 system.cpu0.l2cache.overall_misses::cpu0.data 1175466 # number of overall misses
1071 system.cpu0.l2cache.overall_misses::total 1647595 # number of overall misses
1072 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 376993500 # number of ReadReq miss cycles
1073 system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 339890500 # number of ReadReq miss cycles
1074 system.cpu0.l2cache.ReadReq_miss_latency::total 716884000 # number of ReadReq miss cycles
1075 system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 1915432500 # number of UpgradeReq miss cycles
1076 system.cpu0.l2cache.UpgradeReq_miss_latency::total 1915432500 # number of UpgradeReq miss cycles
1077 system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1581298000 # number of SCUpgradeReq miss cycles
1078 system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1581298000 # number of SCUpgradeReq miss cycles
1079 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2680500 # number of SCUpgradeFailReq miss cycles
1080 system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2680500 # number of SCUpgradeFailReq miss cycles
1081 system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12742251999 # number of ReadExReq miss cycles
1082 system.cpu0.l2cache.ReadExReq_miss_latency::total 12742251999 # number of ReadExReq miss cycles
1083 system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15633345500 # number of ReadCleanReq miss cycles
1084 system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15633345500 # number of ReadCleanReq miss cycles
1085 system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 32366023500 # number of ReadSharedReq miss cycles
1086 system.cpu0.l2cache.ReadSharedReq_miss_latency::total 32366023500 # number of ReadSharedReq miss cycles
1087 system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 286150500 # number of InvalidateReq miss cycles
1088 system.cpu0.l2cache.InvalidateReq_miss_latency::total 286150500 # number of InvalidateReq miss cycles
1089 system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 376993500 # number of demand (read+write) miss cycles
1090 system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 339890500 # number of demand (read+write) miss cycles
1091 system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15633345500 # number of demand (read+write) miss cycles
1092 system.cpu0.l2cache.demand_miss_latency::cpu0.data 45108275499 # number of demand (read+write) miss cycles
1093 system.cpu0.l2cache.demand_miss_latency::total 61458504999 # number of demand (read+write) miss cycles
1094 system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 376993500 # number of overall miss cycles
1095 system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 339890500 # number of overall miss cycles
1096 system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15633345500 # number of overall miss cycles
1097 system.cpu0.l2cache.overall_miss_latency::cpu0.data 45108275499 # number of overall miss cycles
1098 system.cpu0.l2cache.overall_miss_latency::total 61458504999 # number of overall miss cycles
1099 system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278316 # number of ReadReq accesses(hits+misses)
1100 system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155336 # number of ReadReq accesses(hits+misses)
1101 system.cpu0.l2cache.ReadReq_accesses::total 433652 # number of ReadReq accesses(hits+misses)
1102 system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3821588 # number of WritebackDirty accesses(hits+misses)
1103 system.cpu0.l2cache.WritebackDirty_accesses::total 3821588 # number of WritebackDirty accesses(hits+misses)
1104 system.cpu0.l2cache.WritebackClean_accesses::writebacks 6849535 # number of WritebackClean accesses(hits+misses)
1105 system.cpu0.l2cache.WritebackClean_accesses::total 6849535 # number of WritebackClean accesses(hits+misses)
1106 system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242321 # number of UpgradeReq accesses(hits+misses)
1107 system.cpu0.l2cache.UpgradeReq_accesses::total 242321 # number of UpgradeReq accesses(hits+misses)
1108 system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190127 # number of SCUpgradeReq accesses(hits+misses)
1109 system.cpu0.l2cache.SCUpgradeReq_accesses::total 190127 # number of SCUpgradeReq accesses(hits+misses)
1110 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
1111 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
1112 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1186472 # number of ReadExReq accesses(hits+misses)
1113 system.cpu0.l2cache.ReadExReq_accesses::total 1186472 # number of ReadExReq accesses(hits+misses)
1114 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4916774 # number of ReadCleanReq accesses(hits+misses)
1115 system.cpu0.l2cache.ReadCleanReq_accesses::total 4916774 # number of ReadCleanReq accesses(hits+misses)
1116 system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3881914 # number of ReadSharedReq accesses(hits+misses)
1117 system.cpu0.l2cache.ReadSharedReq_accesses::total 3881914 # number of ReadSharedReq accesses(hits+misses)
1118 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 781464 # number of InvalidateReq accesses(hits+misses)
1119 system.cpu0.l2cache.InvalidateReq_accesses::total 781464 # number of InvalidateReq accesses(hits+misses)
1120 system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278316 # number of demand (read+write) accesses
1121 system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155336 # number of demand (read+write) accesses
1122 system.cpu0.l2cache.demand_accesses::cpu0.inst 4916774 # number of demand (read+write) accesses
1123 system.cpu0.l2cache.demand_accesses::cpu0.data 5068386 # number of demand (read+write) accesses
1124 system.cpu0.l2cache.demand_accesses::total 10418812 # number of demand (read+write) accesses
1125 system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278316 # number of overall (read+write) accesses
1126 system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155336 # number of overall (read+write) accesses
1127 system.cpu0.l2cache.overall_accesses::cpu0.inst 4916774 # number of overall (read+write) accesses
1128 system.cpu0.l2cache.overall_accesses::cpu0.data 5068386 # number of overall (read+write) accesses
1129 system.cpu0.l2cache.overall_accesses::total 10418812 # number of overall (read+write) accesses
1130 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036081 # miss rate for ReadReq accesses
1131 system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052853 # miss rate for ReadReq accesses
1132 system.cpu0.l2cache.ReadReq_miss_rate::total 0.042089 # miss rate for ReadReq accesses
1133 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997739 # miss rate for UpgradeReq accesses
1134 system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997739 # miss rate for UpgradeReq accesses
1135 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1136 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1137 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1138 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1139 system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.213255 # miss rate for ReadExReq accesses
1140 system.cpu0.l2cache.ReadExReq_miss_rate::total 0.213255 # miss rate for ReadExReq accesses
1141 system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092312 # miss rate for ReadCleanReq accesses
1142 system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092312 # miss rate for ReadCleanReq accesses
1143 system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.237626 # miss rate for ReadSharedReq accesses
1144 system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.237626 # miss rate for ReadSharedReq accesses
1145 system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734749 # miss rate for InvalidateReq accesses
1146 system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734749 # miss rate for InvalidateReq accesses
1147 system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036081 # miss rate for demand accesses
1148 system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052853 # miss rate for demand accesses
1149 system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092312 # miss rate for demand accesses
1150 system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.231921 # miss rate for demand accesses
1151 system.cpu0.l2cache.demand_miss_rate::total 0.158137 # miss rate for demand accesses
1152 system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036081 # miss rate for overall accesses
1153 system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052853 # miss rate for overall accesses
1154 system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092312 # miss rate for overall accesses
1155 system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.231921 # miss rate for overall accesses
1156 system.cpu0.l2cache.overall_miss_rate::total 0.158137 # miss rate for overall accesses
1157 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average ReadReq miss latency
1158 system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41399.573691 # average ReadReq miss latency
1159 system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39277.010739 # average ReadReq miss latency
1160 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7922.441712 # average UpgradeReq miss latency
1161 system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7922.441712 # average UpgradeReq miss latency
1162 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 8317.061753 # average SCUpgradeReq miss latency
1163 system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 8317.061753 # average SCUpgradeReq miss latency
1164 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 382928.571429 # average SCUpgradeFailReq miss latency
1165 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382928.571429 # average SCUpgradeFailReq miss latency
1166 system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50360.452291 # average ReadExReq miss latency
1167 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50360.452291 # average ReadExReq miss latency
1168 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34444.013466 # average ReadCleanReq miss latency
1169 system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34444.013466 # average ReadCleanReq miss latency
1170 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35087.212246 # average ReadSharedReq miss latency
1171 system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35087.212246 # average ReadSharedReq miss latency
1172 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 498.363754 # average InvalidateReq miss latency
1173 system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 498.363754 # average InvalidateReq miss latency
1174 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average overall miss latency
1175 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41399.573691 # average overall miss latency
1176 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34444.013466 # average overall miss latency
1177 system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38374.802418 # average overall miss latency
1178 system.cpu0.l2cache.demand_avg_miss_latency::total 37301.949204 # average overall miss latency
1179 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average overall miss latency
1180 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41399.573691 # average overall miss latency
1181 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34444.013466 # average overall miss latency
1182 system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38374.802418 # average overall miss latency
1183 system.cpu0.l2cache.overall_avg_miss_latency::total 37301.949204 # average overall miss latency
1184 system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1185 system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1186 system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1187 system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1188 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1189 system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1190 system.cpu0.l2cache.unused_prefetches 39736 # number of HardPF blocks evicted w/o reference
1191 system.cpu0.l2cache.writebacks::writebacks 1527732 # number of writebacks
1192 system.cpu0.l2cache.writebacks::total 1527732 # number of writebacks
1193 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5839 # number of ReadExReq MSHR hits
1194 system.cpu0.l2cache.ReadExReq_mshr_hits::total 5839 # number of ReadExReq MSHR hits
1195 system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 307 # number of ReadSharedReq MSHR hits
1196 system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 307 # number of ReadSharedReq MSHR hits
1197 system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6146 # number of demand (read+write) MSHR hits
1198 system.cpu0.l2cache.demand_mshr_hits::total 6146 # number of demand (read+write) MSHR hits
1199 system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6146 # number of overall MSHR hits
1200 system.cpu0.l2cache.overall_mshr_hits::total 6146 # number of overall MSHR hits
1201 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10042 # number of ReadReq MSHR misses
1202 system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8210 # number of ReadReq MSHR misses
1203 system.cpu0.l2cache.ReadReq_mshr_misses::total 18252 # number of ReadReq MSHR misses
1204 system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 748015 # number of HardPFReq MSHR misses
1205 system.cpu0.l2cache.HardPFReq_mshr_misses::total 748015 # number of HardPFReq MSHR misses
1206 system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 241773 # number of UpgradeReq MSHR misses
1207 system.cpu0.l2cache.UpgradeReq_mshr_misses::total 241773 # number of UpgradeReq MSHR misses
1208 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190127 # number of SCUpgradeReq MSHR misses
1209 system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190127 # number of SCUpgradeReq MSHR misses
1210 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses
1211 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
1212 system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247182 # number of ReadExReq MSHR misses
1213 system.cpu0.l2cache.ReadExReq_mshr_misses::total 247182 # number of ReadExReq MSHR misses
1214 system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 453877 # number of ReadCleanReq MSHR misses
1215 system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 453877 # number of ReadCleanReq MSHR misses
1216 system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 922138 # number of ReadSharedReq MSHR misses
1217 system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 922138 # number of ReadSharedReq MSHR misses
1218 system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 574180 # number of InvalidateReq MSHR misses
1219 system.cpu0.l2cache.InvalidateReq_mshr_misses::total 574180 # number of InvalidateReq MSHR misses
1220 system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10042 # number of demand (read+write) MSHR misses
1221 system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8210 # number of demand (read+write) MSHR misses
1222 system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 453877 # number of demand (read+write) MSHR misses
1223 system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1169320 # number of demand (read+write) MSHR misses
1224 system.cpu0.l2cache.demand_mshr_misses::total 1641449 # number of demand (read+write) MSHR misses
1225 system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10042 # number of overall MSHR misses
1226 system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8210 # number of overall MSHR misses
1227 system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 453877 # number of overall MSHR misses
1228 system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1169320 # number of overall MSHR misses
1229 system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 748015 # number of overall MSHR misses
1230 system.cpu0.l2cache.overall_mshr_misses::total 2389464 # number of overall MSHR misses
1231 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
1232 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable
1233 system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70700 # number of ReadReq MSHR uncacheable
1234 system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable
1235 system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable
1236 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
1237 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses
1238 system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 97240 # number of overall MSHR uncacheable misses
1239 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of ReadReq MSHR miss cycles
1240 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290630500 # number of ReadReq MSHR miss cycles
1241 system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 607372000 # number of ReadReq MSHR miss cycles
1242 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33693542276 # number of HardPFReq MSHR miss cycles
1243 system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33693542276 # number of HardPFReq MSHR miss cycles
1244 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5018820000 # number of UpgradeReq MSHR miss cycles
1245 system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5018820000 # number of UpgradeReq MSHR miss cycles
1246 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3123659500 # number of SCUpgradeReq MSHR miss cycles
1247 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3123659500 # number of SCUpgradeReq MSHR miss cycles
1248 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2368500 # number of SCUpgradeFailReq MSHR miss cycles
1249 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2368500 # number of SCUpgradeFailReq MSHR miss cycles
1250 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10716539999 # number of ReadExReq MSHR miss cycles
1251 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10716539999 # number of ReadExReq MSHR miss cycles
1252 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 12910083500 # number of ReadCleanReq MSHR miss cycles
1253 system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 12910083500 # number of ReadCleanReq MSHR miss cycles
1254 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 26808700000 # number of ReadSharedReq MSHR miss cycles
1255 system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 26808700000 # number of ReadSharedReq MSHR miss cycles
1256 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18844533500 # number of InvalidateReq MSHR miss cycles
1257 system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18844533500 # number of InvalidateReq MSHR miss cycles
1258 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of demand (read+write) MSHR miss cycles
1259 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290630500 # number of demand (read+write) MSHR miss cycles
1260 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12910083500 # number of demand (read+write) MSHR miss cycles
1261 system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37525239999 # number of demand (read+write) MSHR miss cycles
1262 system.cpu0.l2cache.demand_mshr_miss_latency::total 51042695499 # number of demand (read+write) MSHR miss cycles
1263 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of overall MSHR miss cycles
1264 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290630500 # number of overall MSHR miss cycles
1265 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12910083500 # number of overall MSHR miss cycles
1266 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37525239999 # number of overall MSHR miss cycles
1267 system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33693542276 # number of overall MSHR miss cycles
1268 system.cpu0.l2cache.overall_mshr_miss_latency::total 84736237775 # number of overall MSHR miss cycles
1269 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles
1270 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850748500 # number of ReadReq MSHR uncacheable cycles
1271 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles
1272 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles
1273 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles
1274 system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # number of overall MSHR uncacheable cycles
1275 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for ReadReq accesses
1276 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for ReadReq accesses
1277 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042089 # mshr miss rate for ReadReq accesses
1278 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1279 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1280 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997739 # mshr miss rate for UpgradeReq accesses
1281 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997739 # mshr miss rate for UpgradeReq accesses
1282 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1283 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1284 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1285 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1286 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses
1287 system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses
1288 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses
1289 system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses
1290 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses
1291 system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses
1292 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses
1293 system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses
1294 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses
1295 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses
1296 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses
1297 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses
1298 system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses
1299 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses
1300 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses
1301 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses
1302 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses
1303 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1304 system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses
1305 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency
1306 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency
1307 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency
1308 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency
1309 system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency
1310 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency
1311 system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency
1312 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency
1313 system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency
1314 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency
1315 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency
1316 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency
1317 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency
1318 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency
1319 system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency
1320 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency
1321 system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency
1322 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency
1323 system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency
1324 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency
1325 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency
1326 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency
1327 system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency
1328 system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency
1329 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency
1330 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency
1331 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency
1332 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency
1333 system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency
1334 system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency
1335 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency
1336 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency
1337 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency
1338 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency
1339 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency
1340 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency
1341 system.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter.
1342 system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1343 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1344 system.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter.
1345 system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1346 system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1347 system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1348 system.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution
1349 system.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution
1350 system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1351 system.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution
1352 system.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution
1353 system.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution
1354 system.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution
1355 system.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution
1356 system.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution
1357 system.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution
1358 system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution
1359 system.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution
1360 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
1361 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution
1362 system.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution
1363 system.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution
1364 system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution
1365 system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution
1366 system.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution
1367 system.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution
1368 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes)
1369 system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes)
1370 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes)
1371 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes)
1372 system.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes)
1373 system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes)
1374 system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes)
1375 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes)
1376 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes)
1377 system.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes)
1378 system.cpu0.toL2Bus.snoops 6259200 # Total snoops (count)
1379 system.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes)
1380 system.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram
1381 system.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram
1382 system.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram
1383 system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1384 system.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram
1385 system.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram
1386 system.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram
1387 system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1388 system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1389 system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1390 system.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram
1391 system.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks)
1392 system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1393 system.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks)
1394 system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1395 system.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks)
1396 system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1397 system.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks)
1398 system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1399 system.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks)
1400 system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1401 system.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks)
1402 system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1403 system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1404 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1405 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1406 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1407 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1408 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1409 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1410 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1411 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1412 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1413 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1414 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1415 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1416 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1417 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1418 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1419 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1420 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1421 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1422 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1423 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1424 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1425 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1426 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1427 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1428 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1429 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1430 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1431 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1432 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1433 system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1434 system.cpu1.dtb.walker.walks 102344 # Table walker walks requested
1435 system.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors
1436 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate
1437 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate
1438 system.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting
1439 system.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency
1440 system.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency
1441 system.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency
1442 system.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1443 system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1444 system.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency
1445 system.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency
1446 system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency
1447 system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency
1448 system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency
1449 system.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency
1450 system.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency
1451 system.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency
1452 system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency
1453 system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency
1454 system.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
1455 system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1456 system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1457 system.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency
1458 system.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution
1459 system.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution
1460 system.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution
1461 system.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution
1462 system.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution
1463 system.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution
1464 system.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated
1465 system.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated
1466 system.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated
1467 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst
1468 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1469 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst
1470 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst
1471 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1472 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst
1473 system.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst
1474 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1475 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1476 system.cpu1.dtb.read_hits 79660508 # DTB read hits
1477 system.cpu1.dtb.read_misses 74735 # DTB read misses
1478 system.cpu1.dtb.write_hits 72705787 # DTB write hits
1479 system.cpu1.dtb.write_misses 27609 # DTB write misses
1480 system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1481 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1482 system.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
1483 system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1484 system.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB
1485 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1486 system.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch
1487 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1488 system.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions
1489 system.cpu1.dtb.read_accesses 79735243 # DTB read accesses
1490 system.cpu1.dtb.write_accesses 72733396 # DTB write accesses
1491 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1492 system.cpu1.dtb.hits 152366295 # DTB hits
1493 system.cpu1.dtb.misses 102344 # DTB misses
1494 system.cpu1.dtb.accesses 152468639 # DTB accesses
1495 system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1496 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1497 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1498 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1499 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1500 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1501 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1502 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1503 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1504 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1505 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1506 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1507 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1508 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1509 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1510 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1511 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1512 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1513 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1514 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1515 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1516 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1517 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1518 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1519 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1520 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1521 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1522 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1523 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1524 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1525 system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1526 system.cpu1.itb.walker.walks 58593 # Table walker walks requested
1527 system.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors
1528 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate
1529 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate
1530 system.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency
1531 system.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1532 system.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency
1533 system.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency
1534 system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency
1535 system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency
1536 system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency
1537 system.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency
1538 system.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency
1539 system.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency
1540 system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency
1541 system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency
1542 system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency
1543 system.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency
1544 system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency
1545 system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency
1546 system.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency
1547 system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
1548 system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
1549 system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1550 system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1551 system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1552 system.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency
1553 system.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution
1554 system.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution
1555 system.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution
1556 system.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated
1557 system.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated
1558 system.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated
1559 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1560 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst
1561 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst
1562 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1563 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst
1564 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst
1565 system.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst
1566 system.cpu1.itb.inst_hits 421982441 # ITB inst hits
1567 system.cpu1.itb.inst_misses 58593 # ITB inst misses
1568 system.cpu1.itb.read_hits 0 # DTB read hits
1569 system.cpu1.itb.read_misses 0 # DTB read misses
1570 system.cpu1.itb.write_hits 0 # DTB write hits
1571 system.cpu1.itb.write_misses 0 # DTB write misses
1572 system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1573 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1574 system.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
1575 system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1576 system.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB
1577 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1578 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1579 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1580 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1581 system.cpu1.itb.read_accesses 0 # DTB read accesses
1582 system.cpu1.itb.write_accesses 0 # DTB write accesses
1583 system.cpu1.itb.inst_accesses 422041034 # ITB inst accesses
1584 system.cpu1.itb.hits 421982441 # DTB hits
1585 system.cpu1.itb.misses 58593 # DTB misses
1586 system.cpu1.itb.accesses 422041034 # DTB accesses
1587 system.cpu1.numPwrStateTransitions 9904 # Number of power state transitions
1588 system.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state
1589 system.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state
1590 system.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state
1591 system.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state
1592 system.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state
1593 system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state
1594 system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state
1595 system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state
1596 system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state
1597 system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state
1598 system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state
1599 system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state
1600 system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state
1601 system.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state
1602 system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1603 system.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state
1604 system.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state
1605 system.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states
1606 system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states
1607 system.cpu1.numCycles 94807149833 # number of cpu cycles simulated
1608 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1609 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1610 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1611 system.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed
1612 system.cpu1.committedInsts 421703858 # Number of instructions committed
1613 system.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed
1614 system.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses
1615 system.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses
1616 system.cpu1.num_func_calls 25188507 # number of times a function call or return occured
1617 system.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls
1618 system.cpu1.num_int_insts 456781482 # number of integer instructions
1619 system.cpu1.num_fp_insts 475663 # number of float instructions
1620 system.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read
1621 system.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written
1622 system.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read
1623 system.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written
1624 system.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read
1625 system.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written
1626 system.cpu1.num_mem_refs 152358964 # number of memory refs
1627 system.cpu1.num_load_insts 79658830 # Number of load instructions
1628 system.cpu1.num_store_insts 72700134 # Number of store instructions
1629 system.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles
1630 system.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles
1631 system.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles
1632 system.cpu1.idle_fraction 0.989420 # Percentage of idle cycles
1633 system.cpu1.Branches 94064671 # Number of branches fetched
1634 system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
1635 system.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction
1636 system.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction
1637 system.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction
1638 system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction
1639 system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction
1640 system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction
1641 system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction
1642 system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction
1643 system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction
1644 system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction
1645 system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction
1646 system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction
1647 system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction
1648 system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction
1649 system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction
1650 system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction
1651 system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction
1652 system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction
1653 system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction
1654 system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction
1655 system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction
1656 system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction
1657 system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction
1658 system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction
1659 system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction
1660 system.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction
1661 system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction
1662 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction
1663 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction
1664 system.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction
1665 system.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction
1666 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1667 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1668 system.cpu1.op_class::total 497333042 # Class of executed instruction
1669 system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1670 system.cpu1.dcache.tags.replacements 5003393 # number of replacements
1671 system.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use
1672 system.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks.
1673 system.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks.
1674 system.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks.
1675 system.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit.
1676 system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor
1677 system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy
1678 system.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy
1679 system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1680 system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
1681 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id
1682 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
1683 system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1684 system.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses
1685 system.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses
1686 system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1687 system.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits
1688 system.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits
1689 system.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits
1690 system.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits
1691 system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits
1692 system.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits
1693 system.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits
1694 system.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits
1695 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits
1696 system.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits
1697 system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits
1698 system.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits
1699 system.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits
1700 system.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits
1701 system.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits
1702 system.cpu1.dcache.overall_hits::total 143489600 # number of overall hits
1703 system.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses
1704 system.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses
1705 system.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses
1706 system.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses
1707 system.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses
1708 system.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses
1709 system.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses
1710 system.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses
1711 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses
1712 system.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses
1713 system.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses
1714 system.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses
1715 system.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses
1716 system.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses
1717 system.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses
1718 system.cpu1.dcache.overall_misses::total 5199606 # number of overall misses
1719 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles
1720 system.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles
1721 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles
1722 system.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles
1723 system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles
1724 system.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles
1725 system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles
1726 system.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles
1727 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles
1728 system.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles
1729 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles
1730 system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles
1731 system.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles
1732 system.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles
1733 system.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles
1734 system.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles
1735 system.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses)
1736 system.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses)
1737 system.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses)
1738 system.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses)
1739 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses)
1740 system.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses)
1741 system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses)
1742 system.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses)
1743 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses)
1744 system.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses)
1745 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses)
1746 system.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses)
1747 system.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses
1748 system.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses
1749 system.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses
1750 system.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses
1751 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses
1752 system.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses
1753 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses
1754 system.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses
1755 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses
1756 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses
1757 system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses
1758 system.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses
1759 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses
1760 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses
1761 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses
1762 system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses
1763 system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses
1764 system.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses
1765 system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses
1766 system.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses
1767 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency
1768 system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency
1769 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency
1770 system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency
1771 system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency
1772 system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency
1773 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency
1774 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency
1775 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency
1776 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency
1777 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1778 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1779 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency
1780 system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency
1781 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency
1782 system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency
1783 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1784 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1785 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1786 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1787 system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1788 system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1789 system.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks
1790 system.cpu1.dcache.writebacks::total 5003393 # number of writebacks
1791 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits
1792 system.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits
1793 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits
1794 system.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits
1795 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits
1796 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits
1797 system.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits
1798 system.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits
1799 system.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits
1800 system.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits
1801 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses
1802 system.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses
1803 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses
1804 system.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses
1805 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses
1806 system.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses
1807 system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses
1808 system.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses
1809 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses
1810 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses
1811 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses
1812 system.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses
1813 system.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses
1814 system.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses
1815 system.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses
1816 system.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses
1817 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable
1818 system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable
1819 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable
1820 system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable
1821 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses
1822 system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses
1823 system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles
1824 system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles
1825 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles
1826 system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles
1827 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles
1828 system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles
1829 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles
1830 system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles
1831 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles
1832 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles
1833 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles
1834 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles
1835 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles
1836 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles
1837 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles
1838 system.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles
1839 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles
1840 system.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles
1841 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles
1842 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles
1843 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles
1844 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles
1845 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses
1846 system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses
1847 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses
1848 system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses
1849 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses
1850 system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses
1851 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses
1852 system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses
1853 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses
1854 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses
1855 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses
1856 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses
1857 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses
1858 system.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses
1859 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses
1860 system.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses
1861 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency
1862 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency
1863 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency
1864 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency
1865 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency
1866 system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency
1867 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency
1868 system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency
1869 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency
1870 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency
1871 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency
1872 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency
1873 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1874 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1875 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency
1876 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency
1877 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency
1878 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency
1879 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency
1880 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency
1881 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency
1882 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency
1883 system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1884 system.cpu1.icache.tags.replacements 5018955 # number of replacements
1885 system.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use
1886 system.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks.
1887 system.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks.
1888 system.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks.
1889 system.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit.
1890 system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor
1891 system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy
1892 system.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy
1893 system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1894 system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
1895 system.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
1896 system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
1897 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1898 system.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses
1899 system.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses
1900 system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1901 system.cpu1.icache.ReadReq_hits::cpu1.inst 416962969 # number of ReadReq hits
1902 system.cpu1.icache.ReadReq_hits::total 416962969 # number of ReadReq hits
1903 system.cpu1.icache.demand_hits::cpu1.inst 416962969 # number of demand (read+write) hits
1904 system.cpu1.icache.demand_hits::total 416962969 # number of demand (read+write) hits
1905 system.cpu1.icache.overall_hits::cpu1.inst 416962969 # number of overall hits
1906 system.cpu1.icache.overall_hits::total 416962969 # number of overall hits
1907 system.cpu1.icache.ReadReq_misses::cpu1.inst 5019472 # number of ReadReq misses
1908 system.cpu1.icache.ReadReq_misses::total 5019472 # number of ReadReq misses
1909 system.cpu1.icache.demand_misses::cpu1.inst 5019472 # number of demand (read+write) misses
1910 system.cpu1.icache.demand_misses::total 5019472 # number of demand (read+write) misses
1911 system.cpu1.icache.overall_misses::cpu1.inst 5019472 # number of overall misses
1912 system.cpu1.icache.overall_misses::total 5019472 # number of overall misses
1913 system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53186343000 # number of ReadReq miss cycles
1914 system.cpu1.icache.ReadReq_miss_latency::total 53186343000 # number of ReadReq miss cycles
1915 system.cpu1.icache.demand_miss_latency::cpu1.inst 53186343000 # number of demand (read+write) miss cycles
1916 system.cpu1.icache.demand_miss_latency::total 53186343000 # number of demand (read+write) miss cycles
1917 system.cpu1.icache.overall_miss_latency::cpu1.inst 53186343000 # number of overall miss cycles
1918 system.cpu1.icache.overall_miss_latency::total 53186343000 # number of overall miss cycles
1919 system.cpu1.icache.ReadReq_accesses::cpu1.inst 421982441 # number of ReadReq accesses(hits+misses)
1920 system.cpu1.icache.ReadReq_accesses::total 421982441 # number of ReadReq accesses(hits+misses)
1921 system.cpu1.icache.demand_accesses::cpu1.inst 421982441 # number of demand (read+write) accesses
1922 system.cpu1.icache.demand_accesses::total 421982441 # number of demand (read+write) accesses
1923 system.cpu1.icache.overall_accesses::cpu1.inst 421982441 # number of overall (read+write) accesses
1924 system.cpu1.icache.overall_accesses::total 421982441 # number of overall (read+write) accesses
1925 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011895 # miss rate for ReadReq accesses
1926 system.cpu1.icache.ReadReq_miss_rate::total 0.011895 # miss rate for ReadReq accesses
1927 system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011895 # miss rate for demand accesses
1928 system.cpu1.icache.demand_miss_rate::total 0.011895 # miss rate for demand accesses
1929 system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011895 # miss rate for overall accesses
1930 system.cpu1.icache.overall_miss_rate::total 0.011895 # miss rate for overall accesses
1931 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524 # average ReadReq miss latency
1932 system.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524 # average ReadReq miss latency
1933 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency
1934 system.cpu1.icache.demand_avg_miss_latency::total 10596.003524 # average overall miss latency
1935 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency
1936 system.cpu1.icache.overall_avg_miss_latency::total 10596.003524 # average overall miss latency
1937 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1938 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1939 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1940 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1941 system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1942 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1943 system.cpu1.icache.writebacks::writebacks 5018955 # number of writebacks
1944 system.cpu1.icache.writebacks::total 5018955 # number of writebacks
1945 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5019472 # number of ReadReq MSHR misses
1946 system.cpu1.icache.ReadReq_mshr_misses::total 5019472 # number of ReadReq MSHR misses
1947 system.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses
1948 system.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses
1949 system.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses
1950 system.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses
1951 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
1952 system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
1953 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
1954 system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
1955 system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles
1956 system.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles
1957 system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles
1958 system.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles
1959 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles
1960 system.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles
1961 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles
1962 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles
1963 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles
1964 system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles
1965 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses
1966 system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses
1967 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses
1968 system.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses
1969 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses
1970 system.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses
1971 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency
1972 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency
1973 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency
1974 system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency
1975 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency
1976 system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency
1977 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency
1978 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency
1979 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency
1980 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency
1981 system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1982 system.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued
1983 system.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified
1984 system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
1985 system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1986 system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1987 system.cpu1.l2cache.prefetcher.pfSpanPage 855832 # number of prefetches not generated due to page crossing
1988 system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1989 system.cpu1.l2cache.tags.replacements 1952199 # number of replacements
1990 system.cpu1.l2cache.tags.tagsinuse 13310.052713 # Cycle average of tags in use
1991 system.cpu1.l2cache.tags.total_refs 14647404 # Total number of references to valid blocks.
1992 system.cpu1.l2cache.tags.sampled_refs 1968271 # Sample count of references to valid blocks.
1993 system.cpu1.l2cache.tags.avg_refs 7.441762 # Average number of references to valid blocks.
1994 system.cpu1.l2cache.tags.warmup_cycle 9691338413500 # Cycle when the warmup percentage was hit.
1995 system.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537 # Average occupied blocks per requestor
1996 system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.710351 # Average occupied blocks per requestor
1997 system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 42.105943 # Average occupied blocks per requestor
1998 system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 846.327882 # Average occupied blocks per requestor
1999 system.cpu1.l2cache.tags.occ_percent::writebacks 0.755304 # Average percentage of cache occupancy
2000 system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002851 # Average percentage of cache occupancy
2001 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002570 # Average percentage of cache occupancy
2002 system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051656 # Average percentage of cache occupancy
2003 system.cpu1.l2cache.tags.occ_percent::total 0.812381 # Average percentage of cache occupancy
2004 system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1315 # Occupied blocks per task id
2005 system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id
2006 system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id
2007 system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 28 # Occupied blocks per task id
2008 system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 206 # Occupied blocks per task id
2009 system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 560 # Occupied blocks per task id
2010 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id
2011 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id
2012 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
2013 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
2014 system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
2015 system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 976 # Occupied blocks per task id
2016 system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4506 # Occupied blocks per task id
2017 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5198 # Occupied blocks per task id
2018 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3947 # Occupied blocks per task id
2019 system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080261 # Percentage of cache occupancy per task id
2020 system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id
2021 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id
2022 system.cpu1.l2cache.tags.tag_accesses 339868675 # Number of tag accesses
2023 system.cpu1.l2cache.tags.data_accesses 339868675 # Number of data accesses
2024 system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2025 system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 236019 # number of ReadReq hits
2026 system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150274 # number of ReadReq hits
2027 system.cpu1.l2cache.ReadReq_hits::total 386293 # number of ReadReq hits
2028 system.cpu1.l2cache.WritebackDirty_hits::writebacks 3171050 # number of WritebackDirty hits
2029 system.cpu1.l2cache.WritebackDirty_hits::total 3171050 # number of WritebackDirty hits
2030 system.cpu1.l2cache.WritebackClean_hits::writebacks 6850339 # number of WritebackClean hits
2031 system.cpu1.l2cache.WritebackClean_hits::total 6850339 # number of WritebackClean hits
2032 system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 404 # number of UpgradeReq hits
2033 system.cpu1.l2cache.UpgradeReq_hits::total 404 # number of UpgradeReq hits
2034 system.cpu1.l2cache.ReadExReq_hits::cpu1.data 839001 # number of ReadExReq hits
2035 system.cpu1.l2cache.ReadExReq_hits::total 839001 # number of ReadExReq hits
2036 system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4555671 # number of ReadCleanReq hits
2037 system.cpu1.l2cache.ReadCleanReq_hits::total 4555671 # number of ReadCleanReq hits
2038 system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2665864 # number of ReadSharedReq hits
2039 system.cpu1.l2cache.ReadSharedReq_hits::total 2665864 # number of ReadSharedReq hits
2040 system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 201941 # number of InvalidateReq hits
2041 system.cpu1.l2cache.InvalidateReq_hits::total 201941 # number of InvalidateReq hits
2042 system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 236019 # number of demand (read+write) hits
2043 system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150274 # number of demand (read+write) hits
2044 system.cpu1.l2cache.demand_hits::cpu1.inst 4555671 # number of demand (read+write) hits
2045 system.cpu1.l2cache.demand_hits::cpu1.data 3504865 # number of demand (read+write) hits
2046 system.cpu1.l2cache.demand_hits::total 8446829 # number of demand (read+write) hits
2047 system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 236019 # number of overall hits
2048 system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150274 # number of overall hits
2049 system.cpu1.l2cache.overall_hits::cpu1.inst 4555671 # number of overall hits
2050 system.cpu1.l2cache.overall_hits::cpu1.data 3504865 # number of overall hits
2051 system.cpu1.l2cache.overall_hits::total 8446829 # number of overall hits
2052 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10494 # number of ReadReq misses
2053 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9148 # number of ReadReq misses
2054 system.cpu1.l2cache.ReadReq_misses::total 19642 # number of ReadReq misses
2055 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207236 # number of UpgradeReq misses
2056 system.cpu1.l2cache.UpgradeReq_misses::total 207236 # number of UpgradeReq misses
2057 system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 191347 # number of SCUpgradeReq misses
2058 system.cpu1.l2cache.SCUpgradeReq_misses::total 191347 # number of SCUpgradeReq misses
2059 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
2060 system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
2061 system.cpu1.l2cache.ReadExReq_misses::cpu1.data 252464 # number of ReadExReq misses
2062 system.cpu1.l2cache.ReadExReq_misses::total 252464 # number of ReadExReq misses
2063 system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463801 # number of ReadCleanReq misses
2064 system.cpu1.l2cache.ReadCleanReq_misses::total 463801 # number of ReadCleanReq misses
2065 system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 876385 # number of ReadSharedReq misses
2066 system.cpu1.l2cache.ReadSharedReq_misses::total 876385 # number of ReadSharedReq misses
2067 system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256334 # number of InvalidateReq misses
2068 system.cpu1.l2cache.InvalidateReq_misses::total 256334 # number of InvalidateReq misses
2069 system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10494 # number of demand (read+write) misses
2070 system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9148 # number of demand (read+write) misses
2071 system.cpu1.l2cache.demand_misses::cpu1.inst 463801 # number of demand (read+write) misses
2072 system.cpu1.l2cache.demand_misses::cpu1.data 1128849 # number of demand (read+write) misses
2073 system.cpu1.l2cache.demand_misses::total 1612292 # number of demand (read+write) misses
2074 system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10494 # number of overall misses
2075 system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9148 # number of overall misses
2076 system.cpu1.l2cache.overall_misses::cpu1.inst 463801 # number of overall misses
2077 system.cpu1.l2cache.overall_misses::cpu1.data 1128849 # number of overall misses
2078 system.cpu1.l2cache.overall_misses::total 1612292 # number of overall misses
2079 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 383427500 # number of ReadReq miss cycles
2080 system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 341472000 # number of ReadReq miss cycles
2081 system.cpu1.l2cache.ReadReq_miss_latency::total 724899500 # number of ReadReq miss cycles
2082 system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1893664000 # number of UpgradeReq miss cycles
2083 system.cpu1.l2cache.UpgradeReq_miss_latency::total 1893664000 # number of UpgradeReq miss cycles
2084 system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1540982500 # number of SCUpgradeReq miss cycles
2085 system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1540982500 # number of SCUpgradeReq miss cycles
2086 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2848499 # number of SCUpgradeFailReq miss cycles
2087 system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2848499 # number of SCUpgradeFailReq miss cycles
2088 system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10062122499 # number of ReadExReq miss cycles
2089 system.cpu1.l2cache.ReadExReq_miss_latency::total 10062122499 # number of ReadExReq miss cycles
2090 system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15777836000 # number of ReadCleanReq miss cycles
2091 system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15777836000 # number of ReadCleanReq miss cycles
2092 system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28794953500 # number of ReadSharedReq miss cycles
2093 system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28794953500 # number of ReadSharedReq miss cycles
2094 system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 441282000 # number of InvalidateReq miss cycles
2095 system.cpu1.l2cache.InvalidateReq_miss_latency::total 441282000 # number of InvalidateReq miss cycles
2096 system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 383427500 # number of demand (read+write) miss cycles
2097 system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 341472000 # number of demand (read+write) miss cycles
2098 system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15777836000 # number of demand (read+write) miss cycles
2099 system.cpu1.l2cache.demand_miss_latency::cpu1.data 38857075999 # number of demand (read+write) miss cycles
2100 system.cpu1.l2cache.demand_miss_latency::total 55359811499 # number of demand (read+write) miss cycles
2101 system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 383427500 # number of overall miss cycles
2102 system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 341472000 # number of overall miss cycles
2103 system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15777836000 # number of overall miss cycles
2104 system.cpu1.l2cache.overall_miss_latency::cpu1.data 38857075999 # number of overall miss cycles
2105 system.cpu1.l2cache.overall_miss_latency::total 55359811499 # number of overall miss cycles
2106 system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 246513 # number of ReadReq accesses(hits+misses)
2107 system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159422 # number of ReadReq accesses(hits+misses)
2108 system.cpu1.l2cache.ReadReq_accesses::total 405935 # number of ReadReq accesses(hits+misses)
2109 system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3171050 # number of WritebackDirty accesses(hits+misses)
2110 system.cpu1.l2cache.WritebackDirty_accesses::total 3171050 # number of WritebackDirty accesses(hits+misses)
2111 system.cpu1.l2cache.WritebackClean_accesses::writebacks 6850339 # number of WritebackClean accesses(hits+misses)
2112 system.cpu1.l2cache.WritebackClean_accesses::total 6850339 # number of WritebackClean accesses(hits+misses)
2113 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207640 # number of UpgradeReq accesses(hits+misses)
2114 system.cpu1.l2cache.UpgradeReq_accesses::total 207640 # number of UpgradeReq accesses(hits+misses)
2115 system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 191347 # number of SCUpgradeReq accesses(hits+misses)
2116 system.cpu1.l2cache.SCUpgradeReq_accesses::total 191347 # number of SCUpgradeReq accesses(hits+misses)
2117 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
2118 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
2119 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1091465 # number of ReadExReq accesses(hits+misses)
2120 system.cpu1.l2cache.ReadExReq_accesses::total 1091465 # number of ReadExReq accesses(hits+misses)
2121 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5019472 # number of ReadCleanReq accesses(hits+misses)
2122 system.cpu1.l2cache.ReadCleanReq_accesses::total 5019472 # number of ReadCleanReq accesses(hits+misses)
2123 system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3542249 # number of ReadSharedReq accesses(hits+misses)
2124 system.cpu1.l2cache.ReadSharedReq_accesses::total 3542249 # number of ReadSharedReq accesses(hits+misses)
2125 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 458275 # number of InvalidateReq accesses(hits+misses)
2126 system.cpu1.l2cache.InvalidateReq_accesses::total 458275 # number of InvalidateReq accesses(hits+misses)
2127 system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 246513 # number of demand (read+write) accesses
2128 system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159422 # number of demand (read+write) accesses
2129 system.cpu1.l2cache.demand_accesses::cpu1.inst 5019472 # number of demand (read+write) accesses
2130 system.cpu1.l2cache.demand_accesses::cpu1.data 4633714 # number of demand (read+write) accesses
2131 system.cpu1.l2cache.demand_accesses::total 10059121 # number of demand (read+write) accesses
2132 system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 246513 # number of overall (read+write) accesses
2133 system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159422 # number of overall (read+write) accesses
2134 system.cpu1.l2cache.overall_accesses::cpu1.inst 5019472 # number of overall (read+write) accesses
2135 system.cpu1.l2cache.overall_accesses::cpu1.data 4633714 # number of overall (read+write) accesses
2136 system.cpu1.l2cache.overall_accesses::total 10059121 # number of overall (read+write) accesses
2137 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for ReadReq accesses
2138 system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057382 # miss rate for ReadReq accesses
2139 system.cpu1.l2cache.ReadReq_miss_rate::total 0.048387 # miss rate for ReadReq accesses
2140 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998054 # miss rate for UpgradeReq accesses
2141 system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998054 # miss rate for UpgradeReq accesses
2142 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2143 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2144 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2145 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2146 system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231307 # miss rate for ReadExReq accesses
2147 system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231307 # miss rate for ReadExReq accesses
2148 system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092400 # miss rate for ReadCleanReq accesses
2149 system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092400 # miss rate for ReadCleanReq accesses
2150 system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.247409 # miss rate for ReadSharedReq accesses
2151 system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.247409 # miss rate for ReadSharedReq accesses
2152 system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.559345 # miss rate for InvalidateReq accesses
2153 system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.559345 # miss rate for InvalidateReq accesses
2154 system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for demand accesses
2155 system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057382 # miss rate for demand accesses
2156 system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092400 # miss rate for demand accesses
2157 system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243616 # miss rate for demand accesses
2158 system.cpu1.l2cache.demand_miss_rate::total 0.160282 # miss rate for demand accesses
2159 system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for overall accesses
2160 system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057382 # miss rate for overall accesses
2161 system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092400 # miss rate for overall accesses
2162 system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243616 # miss rate for overall accesses
2163 system.cpu1.l2cache.overall_miss_rate::total 0.160282 # miss rate for overall accesses
2164 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average ReadReq miss latency
2165 system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37327.503279 # average ReadReq miss latency
2166 system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36905.584971 # average ReadReq miss latency
2167 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9137.717385 # average UpgradeReq miss latency
2168 system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9137.717385 # average UpgradeReq miss latency
2169 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 8053.340267 # average SCUpgradeReq miss latency
2170 system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 8053.340267 # average SCUpgradeReq miss latency
2171 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 406928.428571 # average SCUpgradeFailReq miss latency
2172 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 406928.428571 # average SCUpgradeFailReq miss latency
2173 system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39855.672488 # average ReadExReq miss latency
2174 system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39855.672488 # average ReadExReq miss latency
2175 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34018.546747 # average ReadCleanReq miss latency
2176 system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34018.546747 # average ReadCleanReq miss latency
2177 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32856.511122 # average ReadSharedReq miss latency
2178 system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32856.511122 # average ReadSharedReq miss latency
2179 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1721.511778 # average InvalidateReq miss latency
2180 system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1721.511778 # average InvalidateReq miss latency
2181 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average overall miss latency
2182 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37327.503279 # average overall miss latency
2183 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34018.546747 # average overall miss latency
2184 system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34421.854472 # average overall miss latency
2185 system.cpu1.l2cache.demand_avg_miss_latency::total 34336.095136 # average overall miss latency
2186 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average overall miss latency
2187 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37327.503279 # average overall miss latency
2188 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34018.546747 # average overall miss latency
2189 system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34421.854472 # average overall miss latency
2190 system.cpu1.l2cache.overall_avg_miss_latency::total 34336.095136 # average overall miss latency
2191 system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2192 system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2193 system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2194 system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2195 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2196 system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2197 system.cpu1.l2cache.unused_prefetches 40910 # number of HardPF blocks evicted w/o reference
2198 system.cpu1.l2cache.writebacks::writebacks 1077285 # number of writebacks
2199 system.cpu1.l2cache.writebacks::total 1077285 # number of writebacks
2200 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4355 # number of ReadExReq MSHR hits
2201 system.cpu1.l2cache.ReadExReq_mshr_hits::total 4355 # number of ReadExReq MSHR hits
2202 system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 371 # number of ReadSharedReq MSHR hits
2203 system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 371 # number of ReadSharedReq MSHR hits
2204 system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4726 # number of demand (read+write) MSHR hits
2205 system.cpu1.l2cache.demand_mshr_hits::total 4726 # number of demand (read+write) MSHR hits
2206 system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4726 # number of overall MSHR hits
2207 system.cpu1.l2cache.overall_mshr_hits::total 4726 # number of overall MSHR hits
2208 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10494 # number of ReadReq MSHR misses
2209 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9148 # number of ReadReq MSHR misses
2210 system.cpu1.l2cache.ReadReq_mshr_misses::total 19642 # number of ReadReq MSHR misses
2211 system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 670250 # number of HardPFReq MSHR misses
2212 system.cpu1.l2cache.HardPFReq_mshr_misses::total 670250 # number of HardPFReq MSHR misses
2213 system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207236 # number of UpgradeReq MSHR misses
2214 system.cpu1.l2cache.UpgradeReq_mshr_misses::total 207236 # number of UpgradeReq MSHR misses
2215 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 191347 # number of SCUpgradeReq MSHR misses
2216 system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 191347 # number of SCUpgradeReq MSHR misses
2217 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
2218 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
2219 system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248109 # number of ReadExReq MSHR misses
2220 system.cpu1.l2cache.ReadExReq_mshr_misses::total 248109 # number of ReadExReq MSHR misses
2221 system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463801 # number of ReadCleanReq MSHR misses
2222 system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463801 # number of ReadCleanReq MSHR misses
2223 system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 876014 # number of ReadSharedReq MSHR misses
2224 system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 876014 # number of ReadSharedReq MSHR misses
2225 system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256334 # number of InvalidateReq MSHR misses
2226 system.cpu1.l2cache.InvalidateReq_mshr_misses::total 256334 # number of InvalidateReq MSHR misses
2227 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10494 # number of demand (read+write) MSHR misses
2228 system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9148 # number of demand (read+write) MSHR misses
2229 system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463801 # number of demand (read+write) MSHR misses
2230 system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1124123 # number of demand (read+write) MSHR misses
2231 system.cpu1.l2cache.demand_mshr_misses::total 1607566 # number of demand (read+write) MSHR misses
2232 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10494 # number of overall MSHR misses
2233 system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9148 # number of overall MSHR misses
2234 system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463801 # number of overall MSHR misses
2235 system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1124123 # number of overall MSHR misses
2236 system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 670250 # number of overall MSHR misses
2237 system.cpu1.l2cache.overall_mshr_misses::total 2277816 # number of overall MSHR misses
2238 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2239 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable
2240 system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11131 # number of ReadReq MSHR uncacheable
2241 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable
2242 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable
2243 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2244 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses
2245 system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23055 # number of overall MSHR uncacheable misses
2246 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of ReadReq MSHR miss cycles
2247 system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 286584000 # number of ReadReq MSHR miss cycles
2248 system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 607047500 # number of ReadReq MSHR miss cycles
2249 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of HardPFReq MSHR miss cycles
2250 system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26432385766 # number of HardPFReq MSHR miss cycles
2251 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4355093500 # number of UpgradeReq MSHR miss cycles
2252 system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4355093500 # number of UpgradeReq MSHR miss cycles
2253 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3151504000 # number of SCUpgradeReq MSHR miss cycles
2254 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3151504000 # number of SCUpgradeReq MSHR miss cycles
2255 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2506499 # number of SCUpgradeFailReq MSHR miss cycles
2256 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2506499 # number of SCUpgradeFailReq MSHR miss cycles
2257 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8136910999 # number of ReadExReq MSHR miss cycles
2258 system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8136910999 # number of ReadExReq MSHR miss cycles
2259 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12995030000 # number of ReadCleanReq MSHR miss cycles
2260 system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12995030000 # number of ReadCleanReq MSHR miss cycles
2261 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23494652500 # number of ReadSharedReq MSHR miss cycles
2262 system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23494652500 # number of ReadSharedReq MSHR miss cycles
2263 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6984949000 # number of InvalidateReq MSHR miss cycles
2264 system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6984949000 # number of InvalidateReq MSHR miss cycles
2265 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of demand (read+write) MSHR miss cycles
2266 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286584000 # number of demand (read+write) MSHR miss cycles
2267 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12995030000 # number of demand (read+write) MSHR miss cycles
2268 system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31631563499 # number of demand (read+write) MSHR miss cycles
2269 system.cpu1.l2cache.demand_mshr_miss_latency::total 45233640999 # number of demand (read+write) MSHR miss cycles
2270 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of overall MSHR miss cycles
2271 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286584000 # number of overall MSHR miss cycles
2272 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12995030000 # number of overall MSHR miss cycles
2273 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31631563499 # number of overall MSHR miss cycles
2274 system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of overall MSHR miss cycles
2275 system.cpu1.l2cache.overall_mshr_miss_latency::total 71666026765 # number of overall MSHR miss cycles
2276 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401000 # number of ReadReq MSHR uncacheable cycles
2277 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1799706000 # number of ReadReq MSHR uncacheable cycles
2278 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1809107000 # number of ReadReq MSHR uncacheable cycles
2279 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401000 # number of overall MSHR uncacheable cycles
2280 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1799706000 # number of overall MSHR uncacheable cycles
2281 system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1809107000 # number of overall MSHR uncacheable cycles
2282 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for ReadReq accesses
2283 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for ReadReq accesses
2284 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048387 # mshr miss rate for ReadReq accesses
2285 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2286 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2287 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998054 # mshr miss rate for UpgradeReq accesses
2288 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998054 # mshr miss rate for UpgradeReq accesses
2289 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2290 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2291 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2292 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2293 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.227317 # mshr miss rate for ReadExReq accesses
2294 system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.227317 # mshr miss rate for ReadExReq accesses
2295 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for ReadCleanReq accesses
2296 system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092400 # mshr miss rate for ReadCleanReq accesses
2297 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247304 # mshr miss rate for ReadSharedReq accesses
2298 system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247304 # mshr miss rate for ReadSharedReq accesses
2299 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.559345 # mshr miss rate for InvalidateReq accesses
2300 system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.559345 # mshr miss rate for InvalidateReq accesses
2301 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for demand accesses
2302 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for demand accesses
2303 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for demand accesses
2304 system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for demand accesses
2305 system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159812 # mshr miss rate for demand accesses
2306 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for overall accesses
2307 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for overall accesses
2308 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for overall accesses
2309 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for overall accesses
2310 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2311 system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226443 # mshr miss rate for overall accesses
2312 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average ReadReq mshr miss latency
2313 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average ReadReq mshr miss latency
2314 system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971 # average ReadReq mshr miss latency
2315 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average HardPFReq mshr miss latency
2316 system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887 # average HardPFReq mshr miss latency
2317 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744 # average UpgradeReq mshr miss latency
2318 system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744 # average UpgradeReq mshr miss latency
2319 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826 # average SCUpgradeReq mshr miss latency
2320 system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826 # average SCUpgradeReq mshr miss latency
2321 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714 # average SCUpgradeFailReq mshr miss latency
2322 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714 # average SCUpgradeFailReq mshr miss latency
2323 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752 # average ReadExReq mshr miss latency
2324 system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752 # average ReadExReq mshr miss latency
2325 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average ReadCleanReq mshr miss latency
2326 system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747 # average ReadCleanReq mshr miss latency
2327 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937 # average ReadSharedReq mshr miss latency
2328 system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937 # average ReadSharedReq mshr miss latency
2329 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency
2330 system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency
2331 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency
2332 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency
2333 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency
2334 system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency
2335 system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency
2336 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency
2337 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency
2338 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency
2339 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency
2340 system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency
2341 system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency
2342 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency
2343 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency
2344 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency
2345 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency
2346 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency
2347 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency
2348 system.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter.
2349 system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2350 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2351 system.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter.
2352 system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2353 system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2354 system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2355 system.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution
2356 system.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution
2357 system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2358 system.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution
2359 system.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution
2360 system.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution
2361 system.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution
2362 system.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution
2363 system.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution
2364 system.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution
2365 system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution
2366 system.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution
2367 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution
2368 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution
2369 system.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution
2370 system.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution
2371 system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution
2372 system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution
2373 system.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution
2374 system.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution
2375 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes)
2376 system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes)
2377 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes)
2378 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes)
2379 system.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes)
2380 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes)
2381 system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes)
2382 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes)
2383 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes)
2384 system.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes)
2385 system.cpu1.toL2Bus.snoops 5663025 # Total snoops (count)
2386 system.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes)
2387 system.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram
2388 system.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram
2389 system.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram
2390 system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2391 system.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram
2392 system.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram
2393 system.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram
2394 system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2395 system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2396 system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2397 system.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram
2398 system.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks)
2399 system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2400 system.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks)
2401 system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2402 system.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks)
2403 system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2404 system.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks)
2405 system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2406 system.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks)
2407 system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2408 system.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks)
2409 system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2410 system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2411 system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
2412 system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
2413 system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
2414 system.iobus.trans_dist::WriteResp 136621 # Transaction distribution
2415 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes)
2416 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2417 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2418 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2419 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2420 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2421 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2422 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2423 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2424 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2425 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2426 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2427 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2428 system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes)
2429 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes)
2430 system.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes)
2431 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2432 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2433 system.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes)
2434 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes)
2435 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2436 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2437 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2438 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2439 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2440 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2441 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2442 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2443 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2444 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2445 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2446 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2447 system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes)
2448 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes)
2449 system.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes)
2450 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2451 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2452 system.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes)
2453 system.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks)
2454 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2455 system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks)
2456 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2457 system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
2458 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2459 system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
2460 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2461 system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
2462 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2463 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2464 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2465 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2466 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2467 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2468 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2469 system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2470 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2471 system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2472 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2473 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2474 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2475 system.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks)
2476 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2477 system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks)
2478 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2479 system.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks)
2480 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2481 system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks)
2482 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2483 system.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks)
2484 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2485 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2486 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2487 system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2488 system.iocache.tags.replacements 115616 # number of replacements
2489 system.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use
2490 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2491 system.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks.
2492 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2493 system.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit.
2494 system.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor
2495 system.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor
2496 system.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy
2497 system.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy
2498 system.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy
2499 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2500 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2501 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2502 system.iocache.tags.tag_accesses 1040928 # Number of tag accesses
2503 system.iocache.tags.data_accesses 1040928 # Number of data accesses
2504 system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2505 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2506 system.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses
2507 system.iocache.ReadReq_misses::total 8928 # number of ReadReq misses
2508 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2509 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2510 system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2511 system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2512 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2513 system.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses
2514 system.iocache.demand_misses::total 115659 # number of demand (read+write) misses
2515 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2516 system.iocache.overall_misses::realview.ide 115619 # number of overall misses
2517 system.iocache.overall_misses::total 115659 # number of overall misses
2518 system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
2519 system.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles
2520 system.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles
2521 system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2522 system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2523 system.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles
2524 system.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles
2525 system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
2526 system.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles
2527 system.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles
2528 system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
2529 system.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles
2530 system.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles
2531 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2532 system.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses)
2533 system.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses)
2534 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2535 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2536 system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2537 system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2538 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2539 system.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses
2540 system.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses
2541 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2542 system.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses
2543 system.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses
2544 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2545 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2546 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2547 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2548 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2549 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2550 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2551 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2552 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2553 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2554 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2555 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2556 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2557 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
2558 system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency
2559 system.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency
2560 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2561 system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2562 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency
2563 system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency
2564 system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
2565 system.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency
2566 system.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency
2567 system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
2568 system.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency
2569 system.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency
2570 system.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked
2571 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2572 system.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked
2573 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2574 system.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked
2575 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2576 system.iocache.writebacks::writebacks 106695 # number of writebacks
2577 system.iocache.writebacks::total 106695 # number of writebacks
2578 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2579 system.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses
2580 system.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses
2581 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2582 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2583 system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2584 system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2585 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2586 system.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses
2587 system.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses
2588 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2589 system.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses
2590 system.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses
2591 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
2592 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles
2593 system.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles
2594 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2595 system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2596 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles
2597 system.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles
2598 system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
2599 system.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles
2600 system.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles
2601 system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
2602 system.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles
2603 system.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles
2604 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2605 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2606 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2607 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2608 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2609 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2610 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2611 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2612 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2613 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2614 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2615 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2616 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2617 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
2618 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency
2619 system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency
2620 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2621 system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2622 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency
2623 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency
2624 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
2625 system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency
2626 system.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency
2627 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
2628 system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency
2629 system.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency
2630 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2631 system.l2c.tags.replacements 1334376 # number of replacements
2632 system.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use
2633 system.l2c.tags.total_refs 5390543 # Total number of references to valid blocks.
2634 system.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks.
2635 system.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks.
2636 system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit.
2637 system.l2c.tags.occ_blocks::writebacks 22223.163606 # Average occupied blocks per requestor
2638 system.l2c.tags.occ_blocks::cpu0.dtb.walker 261.500257 # Average occupied blocks per requestor
2639 system.l2c.tags.occ_blocks::cpu0.itb.walker 456.360455 # Average occupied blocks per requestor
2640 system.l2c.tags.occ_blocks::cpu0.inst 3501.846073 # Average occupied blocks per requestor
2641 system.l2c.tags.occ_blocks::cpu0.data 10429.068271 # Average occupied blocks per requestor
2642 system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383 # Average occupied blocks per requestor
2643 system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.820782 # Average occupied blocks per requestor
2644 system.l2c.tags.occ_blocks::cpu1.itb.walker 49.581814 # Average occupied blocks per requestor
2645 system.l2c.tags.occ_blocks::cpu1.inst 3191.520948 # Average occupied blocks per requestor
2646 system.l2c.tags.occ_blocks::cpu1.data 3798.713740 # Average occupied blocks per requestor
2647 system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor
2648 system.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy
2649 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy
2650 system.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy
2651 system.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy
2652 system.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy
2653 system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy
2654 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy
2655 system.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy
2656 system.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy
2657 system.l2c.tags.occ_percent::cpu1.data 0.057964 # Average percentage of cache occupancy
2658 system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.039963 # Average percentage of cache occupancy
2659 system.l2c.tags.occ_percent::total 0.965797 # Average percentage of cache occupancy
2660 system.l2c.tags.occ_task_id_blocks::1022 10362 # Occupied blocks per task id
2661 system.l2c.tags.occ_task_id_blocks::1023 274 # Occupied blocks per task id
2662 system.l2c.tags.occ_task_id_blocks::1024 48360 # Occupied blocks per task id
2663 system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
2664 system.l2c.tags.age_task_id_blocks_1022::2 240 # Occupied blocks per task id
2665 system.l2c.tags.age_task_id_blocks_1022::3 245 # Occupied blocks per task id
2666 system.l2c.tags.age_task_id_blocks_1022::4 9869 # Occupied blocks per task id
2667 system.l2c.tags.age_task_id_blocks_1023::4 274 # Occupied blocks per task id
2668 system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
2669 system.l2c.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
2670 system.l2c.tags.age_task_id_blocks_1024::2 1630 # Occupied blocks per task id
2671 system.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id
2672 system.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id
2673 system.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id
2674 system.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id
2675 system.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id
2676 system.l2c.tags.tag_accesses 69824789 # Number of tag accesses
2677 system.l2c.tags.data_accesses 69824789 # Number of data accesses
2678 system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2679 system.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits
2680 system.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits
2681 system.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits
2682 system.l2c.UpgradeReq_hits::cpu1.data 131498 # number of UpgradeReq hits
2683 system.l2c.UpgradeReq_hits::total 288738 # number of UpgradeReq hits
2684 system.l2c.SCUpgradeReq_hits::cpu0.data 36551 # number of SCUpgradeReq hits
2685 system.l2c.SCUpgradeReq_hits::cpu1.data 35663 # number of SCUpgradeReq hits
2686 system.l2c.SCUpgradeReq_hits::total 72214 # number of SCUpgradeReq hits
2687 system.l2c.ReadExReq_hits::cpu0.data 46670 # number of ReadExReq hits
2688 system.l2c.ReadExReq_hits::cpu1.data 57995 # number of ReadExReq hits
2689 system.l2c.ReadExReq_hits::total 104665 # number of ReadExReq hits
2690 system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4832 # number of ReadSharedReq hits
2691 system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3674 # number of ReadSharedReq hits
2692 system.l2c.ReadSharedReq_hits::cpu0.inst 408343 # number of ReadSharedReq hits
2693 system.l2c.ReadSharedReq_hits::cpu0.data 539971 # number of ReadSharedReq hits
2694 system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 281420 # number of ReadSharedReq hits
2695 system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5997 # number of ReadSharedReq hits
2696 system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5496 # number of ReadSharedReq hits
2697 system.l2c.ReadSharedReq_hits::cpu1.inst 419901 # number of ReadSharedReq hits
2698 system.l2c.ReadSharedReq_hits::cpu1.data 530515 # number of ReadSharedReq hits
2699 system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 275271 # number of ReadSharedReq hits
2700 system.l2c.ReadSharedReq_hits::total 2475420 # number of ReadSharedReq hits
2701 system.l2c.InvalidateReq_hits::cpu0.data 117433 # number of InvalidateReq hits
2702 system.l2c.InvalidateReq_hits::cpu1.data 122622 # number of InvalidateReq hits
2703 system.l2c.InvalidateReq_hits::total 240055 # number of InvalidateReq hits
2704 system.l2c.demand_hits::cpu0.dtb.walker 4832 # number of demand (read+write) hits
2705 system.l2c.demand_hits::cpu0.itb.walker 3674 # number of demand (read+write) hits
2706 system.l2c.demand_hits::cpu0.inst 408343 # number of demand (read+write) hits
2707 system.l2c.demand_hits::cpu0.data 586641 # number of demand (read+write) hits
2708 system.l2c.demand_hits::cpu0.l2cache.prefetcher 281420 # number of demand (read+write) hits
2709 system.l2c.demand_hits::cpu1.dtb.walker 5997 # number of demand (read+write) hits
2710 system.l2c.demand_hits::cpu1.itb.walker 5496 # number of demand (read+write) hits
2711 system.l2c.demand_hits::cpu1.inst 419901 # number of demand (read+write) hits
2712 system.l2c.demand_hits::cpu1.data 588510 # number of demand (read+write) hits
2713 system.l2c.demand_hits::cpu1.l2cache.prefetcher 275271 # number of demand (read+write) hits
2714 system.l2c.demand_hits::total 2580085 # number of demand (read+write) hits
2715 system.l2c.overall_hits::cpu0.dtb.walker 4832 # number of overall hits
2716 system.l2c.overall_hits::cpu0.itb.walker 3674 # number of overall hits
2717 system.l2c.overall_hits::cpu0.inst 408343 # number of overall hits
2718 system.l2c.overall_hits::cpu0.data 586641 # number of overall hits
2719 system.l2c.overall_hits::cpu0.l2cache.prefetcher 281420 # number of overall hits
2720 system.l2c.overall_hits::cpu1.dtb.walker 5997 # number of overall hits
2721 system.l2c.overall_hits::cpu1.itb.walker 5496 # number of overall hits
2722 system.l2c.overall_hits::cpu1.inst 419901 # number of overall hits
2723 system.l2c.overall_hits::cpu1.data 588510 # number of overall hits
2724 system.l2c.overall_hits::cpu1.l2cache.prefetcher 275271 # number of overall hits
2725 system.l2c.overall_hits::total 2580085 # number of overall hits
2726 system.l2c.UpgradeReq_misses::cpu0.data 61532 # number of UpgradeReq misses
2727 system.l2c.UpgradeReq_misses::cpu1.data 60685 # number of UpgradeReq misses
2728 system.l2c.UpgradeReq_misses::total 122217 # number of UpgradeReq misses
2729 system.l2c.SCUpgradeReq_misses::cpu0.data 12602 # number of SCUpgradeReq misses
2730 system.l2c.SCUpgradeReq_misses::cpu1.data 13049 # number of SCUpgradeReq misses
2731 system.l2c.SCUpgradeReq_misses::total 25651 # number of SCUpgradeReq misses
2732 system.l2c.ReadExReq_misses::cpu0.data 81623 # number of ReadExReq misses
2733 system.l2c.ReadExReq_misses::cpu1.data 50736 # number of ReadExReq misses
2734 system.l2c.ReadExReq_misses::total 132359 # number of ReadExReq misses
2735 system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq misses
2736 system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1980 # number of ReadSharedReq misses
2737 system.l2c.ReadSharedReq_misses::cpu0.inst 45534 # number of ReadSharedReq misses
2738 system.l2c.ReadSharedReq_misses::cpu0.data 135010 # number of ReadSharedReq misses
2739 system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq misses
2740 system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq misses
2741 system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1646 # number of ReadSharedReq misses
2742 system.l2c.ReadSharedReq_misses::cpu1.inst 43900 # number of ReadSharedReq misses
2743 system.l2c.ReadSharedReq_misses::cpu1.data 98157 # number of ReadSharedReq misses
2744 system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq misses
2745 system.l2c.ReadSharedReq_misses::total 747537 # number of ReadSharedReq misses
2746 system.l2c.InvalidateReq_misses::cpu0.data 445868 # number of InvalidateReq misses
2747 system.l2c.InvalidateReq_misses::cpu1.data 117477 # number of InvalidateReq misses
2748 system.l2c.InvalidateReq_misses::total 563345 # number of InvalidateReq misses
2749 system.l2c.demand_misses::cpu0.dtb.walker 1903 # number of demand (read+write) misses
2750 system.l2c.demand_misses::cpu0.itb.walker 1980 # number of demand (read+write) misses
2751 system.l2c.demand_misses::cpu0.inst 45534 # number of demand (read+write) misses
2752 system.l2c.demand_misses::cpu0.data 216633 # number of demand (read+write) misses
2753 system.l2c.demand_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) misses
2754 system.l2c.demand_misses::cpu1.dtb.walker 1748 # number of demand (read+write) misses
2755 system.l2c.demand_misses::cpu1.itb.walker 1646 # number of demand (read+write) misses
2756 system.l2c.demand_misses::cpu1.inst 43900 # number of demand (read+write) misses
2757 system.l2c.demand_misses::cpu1.data 148893 # number of demand (read+write) misses
2758 system.l2c.demand_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) misses
2759 system.l2c.demand_misses::total 879896 # number of demand (read+write) misses
2760 system.l2c.overall_misses::cpu0.dtb.walker 1903 # number of overall misses
2761 system.l2c.overall_misses::cpu0.itb.walker 1980 # number of overall misses
2762 system.l2c.overall_misses::cpu0.inst 45534 # number of overall misses
2763 system.l2c.overall_misses::cpu0.data 216633 # number of overall misses
2764 system.l2c.overall_misses::cpu0.l2cache.prefetcher 240877 # number of overall misses
2765 system.l2c.overall_misses::cpu1.dtb.walker 1748 # number of overall misses
2766 system.l2c.overall_misses::cpu1.itb.walker 1646 # number of overall misses
2767 system.l2c.overall_misses::cpu1.inst 43900 # number of overall misses
2768 system.l2c.overall_misses::cpu1.data 148893 # number of overall misses
2769 system.l2c.overall_misses::cpu1.l2cache.prefetcher 176782 # number of overall misses
2770 system.l2c.overall_misses::total 879896 # number of overall misses
2771 system.l2c.UpgradeReq_miss_latency::cpu0.data 390440000 # number of UpgradeReq miss cycles
2772 system.l2c.UpgradeReq_miss_latency::cpu1.data 373608000 # number of UpgradeReq miss cycles
2773 system.l2c.UpgradeReq_miss_latency::total 764048000 # number of UpgradeReq miss cycles
2774 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 65654000 # number of SCUpgradeReq miss cycles
2775 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 76676500 # number of SCUpgradeReq miss cycles
2776 system.l2c.SCUpgradeReq_miss_latency::total 142330500 # number of SCUpgradeReq miss cycles
2777 system.l2c.ReadExReq_miss_latency::cpu0.data 7135565500 # number of ReadExReq miss cycles
2778 system.l2c.ReadExReq_miss_latency::cpu1.data 4240679000 # number of ReadExReq miss cycles
2779 system.l2c.ReadExReq_miss_latency::total 11376244500 # number of ReadExReq miss cycles
2780 system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 166331500 # number of ReadSharedReq miss cycles
2781 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 176995000 # number of ReadSharedReq miss cycles
2782 system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3903055500 # number of ReadSharedReq miss cycles
2783 system.l2c.ReadSharedReq_miss_latency::cpu0.data 11953058500 # number of ReadSharedReq miss cycles
2784 system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of ReadSharedReq miss cycles
2785 system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157717000 # number of ReadSharedReq miss cycles
2786 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 151093000 # number of ReadSharedReq miss cycles
2787 system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3757434500 # number of ReadSharedReq miss cycles
2788 system.l2c.ReadSharedReq_miss_latency::cpu1.data 9007178500 # number of ReadSharedReq miss cycles
2789 system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of ReadSharedReq miss cycles
2790 system.l2c.ReadSharedReq_miss_latency::total 79243121431 # number of ReadSharedReq miss cycles
2791 system.l2c.InvalidateReq_miss_latency::cpu0.data 55722000 # number of InvalidateReq miss cycles
2792 system.l2c.InvalidateReq_miss_latency::cpu1.data 43983500 # number of InvalidateReq miss cycles
2793 system.l2c.InvalidateReq_miss_latency::total 99705500 # number of InvalidateReq miss cycles
2794 system.l2c.demand_miss_latency::cpu0.dtb.walker 166331500 # number of demand (read+write) miss cycles
2795 system.l2c.demand_miss_latency::cpu0.itb.walker 176995000 # number of demand (read+write) miss cycles
2796 system.l2c.demand_miss_latency::cpu0.inst 3903055500 # number of demand (read+write) miss cycles
2797 system.l2c.demand_miss_latency::cpu0.data 19088624000 # number of demand (read+write) miss cycles
2798 system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of demand (read+write) miss cycles
2799 system.l2c.demand_miss_latency::cpu1.dtb.walker 157717000 # number of demand (read+write) miss cycles
2800 system.l2c.demand_miss_latency::cpu1.itb.walker 151093000 # number of demand (read+write) miss cycles
2801 system.l2c.demand_miss_latency::cpu1.inst 3757434500 # number of demand (read+write) miss cycles
2802 system.l2c.demand_miss_latency::cpu1.data 13247857500 # number of demand (read+write) miss cycles
2803 system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of demand (read+write) miss cycles
2804 system.l2c.demand_miss_latency::total 90619365931 # number of demand (read+write) miss cycles
2805 system.l2c.overall_miss_latency::cpu0.dtb.walker 166331500 # number of overall miss cycles
2806 system.l2c.overall_miss_latency::cpu0.itb.walker 176995000 # number of overall miss cycles
2807 system.l2c.overall_miss_latency::cpu0.inst 3903055500 # number of overall miss cycles
2808 system.l2c.overall_miss_latency::cpu0.data 19088624000 # number of overall miss cycles
2809 system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of overall miss cycles
2810 system.l2c.overall_miss_latency::cpu1.dtb.walker 157717000 # number of overall miss cycles
2811 system.l2c.overall_miss_latency::cpu1.itb.walker 151093000 # number of overall miss cycles
2812 system.l2c.overall_miss_latency::cpu1.inst 3757434500 # number of overall miss cycles
2813 system.l2c.overall_miss_latency::cpu1.data 13247857500 # number of overall miss cycles
2814 system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of overall miss cycles
2815 system.l2c.overall_miss_latency::total 90619365931 # number of overall miss cycles
2816 system.l2c.WritebackDirty_accesses::writebacks 2605015 # number of WritebackDirty accesses(hits+misses)
2817 system.l2c.WritebackDirty_accesses::total 2605015 # number of WritebackDirty accesses(hits+misses)
2818 system.l2c.UpgradeReq_accesses::cpu0.data 218772 # number of UpgradeReq accesses(hits+misses)
2819 system.l2c.UpgradeReq_accesses::cpu1.data 192183 # number of UpgradeReq accesses(hits+misses)
2820 system.l2c.UpgradeReq_accesses::total 410955 # number of UpgradeReq accesses(hits+misses)
2821 system.l2c.SCUpgradeReq_accesses::cpu0.data 49153 # number of SCUpgradeReq accesses(hits+misses)
2822 system.l2c.SCUpgradeReq_accesses::cpu1.data 48712 # number of SCUpgradeReq accesses(hits+misses)
2823 system.l2c.SCUpgradeReq_accesses::total 97865 # number of SCUpgradeReq accesses(hits+misses)
2824 system.l2c.ReadExReq_accesses::cpu0.data 128293 # number of ReadExReq accesses(hits+misses)
2825 system.l2c.ReadExReq_accesses::cpu1.data 108731 # number of ReadExReq accesses(hits+misses)
2826 system.l2c.ReadExReq_accesses::total 237024 # number of ReadExReq accesses(hits+misses)
2827 system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6735 # number of ReadSharedReq accesses(hits+misses)
2828 system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5654 # number of ReadSharedReq accesses(hits+misses)
2829 system.l2c.ReadSharedReq_accesses::cpu0.inst 453877 # number of ReadSharedReq accesses(hits+misses)
2830 system.l2c.ReadSharedReq_accesses::cpu0.data 674981 # number of ReadSharedReq accesses(hits+misses)
2831 system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 522297 # number of ReadSharedReq accesses(hits+misses)
2832 system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7745 # number of ReadSharedReq accesses(hits+misses)
2833 system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7142 # number of ReadSharedReq accesses(hits+misses)
2834 system.l2c.ReadSharedReq_accesses::cpu1.inst 463801 # number of ReadSharedReq accesses(hits+misses)
2835 system.l2c.ReadSharedReq_accesses::cpu1.data 628672 # number of ReadSharedReq accesses(hits+misses)
2836 system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 452053 # number of ReadSharedReq accesses(hits+misses)
2837 system.l2c.ReadSharedReq_accesses::total 3222957 # number of ReadSharedReq accesses(hits+misses)
2838 system.l2c.InvalidateReq_accesses::cpu0.data 563301 # number of InvalidateReq accesses(hits+misses)
2839 system.l2c.InvalidateReq_accesses::cpu1.data 240099 # number of InvalidateReq accesses(hits+misses)
2840 system.l2c.InvalidateReq_accesses::total 803400 # number of InvalidateReq accesses(hits+misses)
2841 system.l2c.demand_accesses::cpu0.dtb.walker 6735 # number of demand (read+write) accesses
2842 system.l2c.demand_accesses::cpu0.itb.walker 5654 # number of demand (read+write) accesses
2843 system.l2c.demand_accesses::cpu0.inst 453877 # number of demand (read+write) accesses
2844 system.l2c.demand_accesses::cpu0.data 803274 # number of demand (read+write) accesses
2845 system.l2c.demand_accesses::cpu0.l2cache.prefetcher 522297 # number of demand (read+write) accesses
2846 system.l2c.demand_accesses::cpu1.dtb.walker 7745 # number of demand (read+write) accesses
2847 system.l2c.demand_accesses::cpu1.itb.walker 7142 # number of demand (read+write) accesses
2848 system.l2c.demand_accesses::cpu1.inst 463801 # number of demand (read+write) accesses
2849 system.l2c.demand_accesses::cpu1.data 737403 # number of demand (read+write) accesses
2850 system.l2c.demand_accesses::cpu1.l2cache.prefetcher 452053 # number of demand (read+write) accesses
2851 system.l2c.demand_accesses::total 3459981 # number of demand (read+write) accesses
2852 system.l2c.overall_accesses::cpu0.dtb.walker 6735 # number of overall (read+write) accesses
2853 system.l2c.overall_accesses::cpu0.itb.walker 5654 # number of overall (read+write) accesses
2854 system.l2c.overall_accesses::cpu0.inst 453877 # number of overall (read+write) accesses
2855 system.l2c.overall_accesses::cpu0.data 803274 # number of overall (read+write) accesses
2856 system.l2c.overall_accesses::cpu0.l2cache.prefetcher 522297 # number of overall (read+write) accesses
2857 system.l2c.overall_accesses::cpu1.dtb.walker 7745 # number of overall (read+write) accesses
2858 system.l2c.overall_accesses::cpu1.itb.walker 7142 # number of overall (read+write) accesses
2859 system.l2c.overall_accesses::cpu1.inst 463801 # number of overall (read+write) accesses
2860 system.l2c.overall_accesses::cpu1.data 737403 # number of overall (read+write) accesses
2861 system.l2c.overall_accesses::cpu1.l2cache.prefetcher 452053 # number of overall (read+write) accesses
2862 system.l2c.overall_accesses::total 3459981 # number of overall (read+write) accesses
2863 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.281261 # miss rate for UpgradeReq accesses
2864 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.315767 # miss rate for UpgradeReq accesses
2865 system.l2c.UpgradeReq_miss_rate::total 0.297398 # miss rate for UpgradeReq accesses
2866 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.256383 # miss rate for SCUpgradeReq accesses
2867 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.267881 # miss rate for SCUpgradeReq accesses
2868 system.l2c.SCUpgradeReq_miss_rate::total 0.262106 # miss rate for SCUpgradeReq accesses
2869 system.l2c.ReadExReq_miss_rate::cpu0.data 0.636223 # miss rate for ReadExReq accesses
2870 system.l2c.ReadExReq_miss_rate::cpu1.data 0.466619 # miss rate for ReadExReq accesses
2871 system.l2c.ReadExReq_miss_rate::total 0.558420 # miss rate for ReadExReq accesses
2872 system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for ReadSharedReq accesses
2873 system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.350195 # miss rate for ReadSharedReq accesses
2874 system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100322 # miss rate for ReadSharedReq accesses
2875 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200020 # miss rate for ReadSharedReq accesses
2876 system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for ReadSharedReq accesses
2877 system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for ReadSharedReq accesses
2878 system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230468 # miss rate for ReadSharedReq accesses
2879 system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.094653 # miss rate for ReadSharedReq accesses
2880 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.156134 # miss rate for ReadSharedReq accesses
2881 system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for ReadSharedReq accesses
2882 system.l2c.ReadSharedReq_miss_rate::total 0.231941 # miss rate for ReadSharedReq accesses
2883 system.l2c.InvalidateReq_miss_rate::cpu0.data 0.791527 # miss rate for InvalidateReq accesses
2884 system.l2c.InvalidateReq_miss_rate::cpu1.data 0.489286 # miss rate for InvalidateReq accesses
2885 system.l2c.InvalidateReq_miss_rate::total 0.701201 # miss rate for InvalidateReq accesses
2886 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for demand accesses
2887 system.l2c.demand_miss_rate::cpu0.itb.walker 0.350195 # miss rate for demand accesses
2888 system.l2c.demand_miss_rate::cpu0.inst 0.100322 # miss rate for demand accesses
2889 system.l2c.demand_miss_rate::cpu0.data 0.269688 # miss rate for demand accesses
2890 system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for demand accesses
2891 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for demand accesses
2892 system.l2c.demand_miss_rate::cpu1.itb.walker 0.230468 # miss rate for demand accesses
2893 system.l2c.demand_miss_rate::cpu1.inst 0.094653 # miss rate for demand accesses
2894 system.l2c.demand_miss_rate::cpu1.data 0.201915 # miss rate for demand accesses
2895 system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for demand accesses
2896 system.l2c.demand_miss_rate::total 0.254307 # miss rate for demand accesses
2897 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for overall accesses
2898 system.l2c.overall_miss_rate::cpu0.itb.walker 0.350195 # miss rate for overall accesses
2899 system.l2c.overall_miss_rate::cpu0.inst 0.100322 # miss rate for overall accesses
2900 system.l2c.overall_miss_rate::cpu0.data 0.269688 # miss rate for overall accesses
2901 system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for overall accesses
2902 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for overall accesses
2903 system.l2c.overall_miss_rate::cpu1.itb.walker 0.230468 # miss rate for overall accesses
2904 system.l2c.overall_miss_rate::cpu1.inst 0.094653 # miss rate for overall accesses
2905 system.l2c.overall_miss_rate::cpu1.data 0.201915 # miss rate for overall accesses
2906 system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for overall accesses
2907 system.l2c.overall_miss_rate::total 0.254307 # miss rate for overall accesses
2908 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6345.316258 # average UpgradeReq miss latency
2909 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6156.513142 # average UpgradeReq miss latency
2910 system.l2c.UpgradeReq_avg_miss_latency::total 6251.568931 # average UpgradeReq miss latency
2911 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5209.807967 # average SCUpgradeReq miss latency
2912 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5876.044141 # average SCUpgradeReq miss latency
2913 system.l2c.SCUpgradeReq_avg_miss_latency::total 5548.731044 # average SCUpgradeReq miss latency
2914 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87421.014910 # average ReadExReq miss latency
2915 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83583.234784 # average ReadExReq miss latency
2916 system.l2c.ReadExReq_avg_miss_latency::total 85949.912737 # average ReadExReq miss latency
2917 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average ReadSharedReq miss latency
2918 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89391.414141 # average ReadSharedReq miss latency
2919 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85717.387008 # average ReadSharedReq miss latency
2920 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88534.615954 # average ReadSharedReq miss latency
2921 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average ReadSharedReq miss latency
2922 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average ReadSharedReq miss latency
2923 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 91794.046173 # average ReadSharedReq miss latency
2924 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85590.763098 # average ReadSharedReq miss latency
2925 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91762.976660 # average ReadSharedReq miss latency
2926 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average ReadSharedReq miss latency
2927 system.l2c.ReadSharedReq_avg_miss_latency::total 106005.617690 # average ReadSharedReq miss latency
2928 system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 124.974208 # average InvalidateReq miss latency
2929 system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 374.400947 # average InvalidateReq miss latency
2930 system.l2c.InvalidateReq_avg_miss_latency::total 176.988346 # average InvalidateReq miss latency
2931 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average overall miss latency
2932 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89391.414141 # average overall miss latency
2933 system.l2c.demand_avg_miss_latency::cpu0.inst 85717.387008 # average overall miss latency
2934 system.l2c.demand_avg_miss_latency::cpu0.data 88115.033259 # average overall miss latency
2935 system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average overall miss latency
2936 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average overall miss latency
2937 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91794.046173 # average overall miss latency
2938 system.l2c.demand_avg_miss_latency::cpu1.inst 85590.763098 # average overall miss latency
2939 system.l2c.demand_avg_miss_latency::cpu1.data 88975.690597 # average overall miss latency
2940 system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average overall miss latency
2941 system.l2c.demand_avg_miss_latency::total 102988.723589 # average overall miss latency
2942 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average overall miss latency
2943 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89391.414141 # average overall miss latency
2944 system.l2c.overall_avg_miss_latency::cpu0.inst 85717.387008 # average overall miss latency
2945 system.l2c.overall_avg_miss_latency::cpu0.data 88115.033259 # average overall miss latency
2946 system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average overall miss latency
2947 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average overall miss latency
2948 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91794.046173 # average overall miss latency
2949 system.l2c.overall_avg_miss_latency::cpu1.inst 85590.763098 # average overall miss latency
2950 system.l2c.overall_avg_miss_latency::cpu1.data 88975.690597 # average overall miss latency
2951 system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average overall miss latency
2952 system.l2c.overall_avg_miss_latency::total 102988.723589 # average overall miss latency
2953 system.l2c.blocked_cycles::no_mshrs 494 # number of cycles access was blocked
2954 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2955 system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2956 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2957 system.l2c.avg_blocked_cycles::no_mshrs 54.888889 # average number of cycles each access was blocked
2958 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2959 system.l2c.writebacks::writebacks 1068061 # number of writebacks
2960 system.l2c.writebacks::total 1068061 # number of writebacks
2961 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 54 # number of ReadSharedReq MSHR hits
2962 system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits
2963 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 49 # number of ReadSharedReq MSHR hits
2964 system.l2c.ReadSharedReq_mshr_hits::cpu1.data 43 # number of ReadSharedReq MSHR hits
2965 system.l2c.ReadSharedReq_mshr_hits::total 165 # number of ReadSharedReq MSHR hits
2966 system.l2c.demand_mshr_hits::cpu0.inst 54 # number of demand (read+write) MSHR hits
2967 system.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits
2968 system.l2c.demand_mshr_hits::cpu1.inst 49 # number of demand (read+write) MSHR hits
2969 system.l2c.demand_mshr_hits::cpu1.data 43 # number of demand (read+write) MSHR hits
2970 system.l2c.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
2971 system.l2c.overall_mshr_hits::cpu0.inst 54 # number of overall MSHR hits
2972 system.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits
2973 system.l2c.overall_mshr_hits::cpu1.inst 49 # number of overall MSHR hits
2974 system.l2c.overall_mshr_hits::cpu1.data 43 # number of overall MSHR hits
2975 system.l2c.overall_mshr_hits::total 165 # number of overall MSHR hits
2976 system.l2c.CleanEvict_mshr_misses::writebacks 48108 # number of CleanEvict MSHR misses
2977 system.l2c.CleanEvict_mshr_misses::total 48108 # number of CleanEvict MSHR misses
2978 system.l2c.UpgradeReq_mshr_misses::cpu0.data 61532 # number of UpgradeReq MSHR misses
2979 system.l2c.UpgradeReq_mshr_misses::cpu1.data 60685 # number of UpgradeReq MSHR misses
2980 system.l2c.UpgradeReq_mshr_misses::total 122217 # number of UpgradeReq MSHR misses
2981 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12602 # number of SCUpgradeReq MSHR misses
2982 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 13049 # number of SCUpgradeReq MSHR misses
2983 system.l2c.SCUpgradeReq_mshr_misses::total 25651 # number of SCUpgradeReq MSHR misses
2984 system.l2c.ReadExReq_mshr_misses::cpu0.data 81623 # number of ReadExReq MSHR misses
2985 system.l2c.ReadExReq_mshr_misses::cpu1.data 50736 # number of ReadExReq MSHR misses
2986 system.l2c.ReadExReq_mshr_misses::total 132359 # number of ReadExReq MSHR misses
2987 system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq MSHR misses
2988 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1980 # number of ReadSharedReq MSHR misses
2989 system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45480 # number of ReadSharedReq MSHR misses
2990 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 134991 # number of ReadSharedReq MSHR misses
2991 system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq MSHR misses
2992 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq MSHR misses
2993 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1646 # number of ReadSharedReq MSHR misses
2994 system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 43851 # number of ReadSharedReq MSHR misses
2995 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 98114 # number of ReadSharedReq MSHR misses
2996 system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq MSHR misses
2997 system.l2c.ReadSharedReq_mshr_misses::total 747372 # number of ReadSharedReq MSHR misses
2998 system.l2c.InvalidateReq_mshr_misses::cpu0.data 445868 # number of InvalidateReq MSHR misses
2999 system.l2c.InvalidateReq_mshr_misses::cpu1.data 117477 # number of InvalidateReq MSHR misses
3000 system.l2c.InvalidateReq_mshr_misses::total 563345 # number of InvalidateReq MSHR misses
3001 system.l2c.demand_mshr_misses::cpu0.dtb.walker 1903 # number of demand (read+write) MSHR misses
3002 system.l2c.demand_mshr_misses::cpu0.itb.walker 1980 # number of demand (read+write) MSHR misses
3003 system.l2c.demand_mshr_misses::cpu0.inst 45480 # number of demand (read+write) MSHR misses
3004 system.l2c.demand_mshr_misses::cpu0.data 216614 # number of demand (read+write) MSHR misses
3005 system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) MSHR misses
3006 system.l2c.demand_mshr_misses::cpu1.dtb.walker 1748 # number of demand (read+write) MSHR misses
3007 system.l2c.demand_mshr_misses::cpu1.itb.walker 1646 # number of demand (read+write) MSHR misses
3008 system.l2c.demand_mshr_misses::cpu1.inst 43851 # number of demand (read+write) MSHR misses
3009 system.l2c.demand_mshr_misses::cpu1.data 148850 # number of demand (read+write) MSHR misses
3010 system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) MSHR misses
3011 system.l2c.demand_mshr_misses::total 879731 # number of demand (read+write) MSHR misses
3012 system.l2c.overall_mshr_misses::cpu0.dtb.walker 1903 # number of overall MSHR misses
3013 system.l2c.overall_mshr_misses::cpu0.itb.walker 1980 # number of overall MSHR misses
3014 system.l2c.overall_mshr_misses::cpu0.inst 45480 # number of overall MSHR misses
3015 system.l2c.overall_mshr_misses::cpu0.data 216614 # number of overall MSHR misses
3016 system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of overall MSHR misses
3017 system.l2c.overall_mshr_misses::cpu1.dtb.walker 1748 # number of overall MSHR misses
3018 system.l2c.overall_mshr_misses::cpu1.itb.walker 1646 # number of overall MSHR misses
3019 system.l2c.overall_mshr_misses::cpu1.inst 43851 # number of overall MSHR misses
3020 system.l2c.overall_mshr_misses::cpu1.data 148850 # number of overall MSHR misses
3021 system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of overall MSHR misses
3022 system.l2c.overall_mshr_misses::total 879731 # number of overall MSHR misses
3023 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
3024 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable
3025 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
3026 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11019 # number of ReadReq MSHR uncacheable
3027 system.l2c.ReadReq_mshr_uncacheable::total 81829 # number of ReadReq MSHR uncacheable
3028 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable
3029 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable
3030 system.l2c.WriteReq_mshr_uncacheable::total 38464 # number of WriteReq MSHR uncacheable
3031 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
3032 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses
3033 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
3034 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 22943 # number of overall MSHR uncacheable misses
3035 system.l2c.overall_mshr_uncacheable_misses::total 120293 # number of overall MSHR uncacheable misses
3036 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1338948000 # number of UpgradeReq MSHR miss cycles
3037 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1324584000 # number of UpgradeReq MSHR miss cycles
3038 system.l2c.UpgradeReq_mshr_miss_latency::total 2663532000 # number of UpgradeReq MSHR miss cycles
3039 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 312012000 # number of SCUpgradeReq MSHR miss cycles
3040 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 323877000 # number of SCUpgradeReq MSHR miss cycles
3041 system.l2c.SCUpgradeReq_mshr_miss_latency::total 635889000 # number of SCUpgradeReq MSHR miss cycles
3042 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6319298576 # number of ReadExReq MSHR miss cycles
3043 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3733266108 # number of ReadExReq MSHR miss cycles
3044 system.l2c.ReadExReq_mshr_miss_latency::total 10052564684 # number of ReadExReq MSHR miss cycles
3045 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of ReadSharedReq MSHR miss cycles
3046 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 157194002 # number of ReadSharedReq MSHR miss cycles
3047 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3443824526 # number of ReadSharedReq MSHR miss cycles
3048 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10601706692 # number of ReadSharedReq MSHR miss cycles
3049 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of ReadSharedReq MSHR miss cycles
3050 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of ReadSharedReq MSHR miss cycles
3051 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 134631004 # number of ReadSharedReq MSHR miss cycles
3052 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3315499572 # number of ReadSharedReq MSHR miss cycles
3053 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8022481292 # number of ReadSharedReq MSHR miss cycles
3054 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of ReadSharedReq MSHR miss cycles
3055 system.l2c.ReadSharedReq_mshr_miss_latency::total 71756096476 # number of ReadSharedReq MSHR miss cycles
3056 system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8904054000 # number of InvalidateReq MSHR miss cycles
3057 system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2392104000 # number of InvalidateReq MSHR miss cycles
3058 system.l2c.InvalidateReq_mshr_miss_latency::total 11296158000 # number of InvalidateReq MSHR miss cycles
3059 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of demand (read+write) MSHR miss cycles
3060 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 157194002 # number of demand (read+write) MSHR miss cycles
3061 system.l2c.demand_mshr_miss_latency::cpu0.inst 3443824526 # number of demand (read+write) MSHR miss cycles
3062 system.l2c.demand_mshr_miss_latency::cpu0.data 16921005268 # number of demand (read+write) MSHR miss cycles
3063 system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of demand (read+write) MSHR miss cycles
3064 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of demand (read+write) MSHR miss cycles
3065 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 134631004 # number of demand (read+write) MSHR miss cycles
3066 system.l2c.demand_mshr_miss_latency::cpu1.inst 3315499572 # number of demand (read+write) MSHR miss cycles
3067 system.l2c.demand_mshr_miss_latency::cpu1.data 11755747400 # number of demand (read+write) MSHR miss cycles
3068 system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of demand (read+write) MSHR miss cycles
3069 system.l2c.demand_mshr_miss_latency::total 81808661160 # number of demand (read+write) MSHR miss cycles
3070 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of overall MSHR miss cycles
3071 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 157194002 # number of overall MSHR miss cycles
3072 system.l2c.overall_mshr_miss_latency::cpu0.inst 3443824526 # number of overall MSHR miss cycles
3073 system.l2c.overall_mshr_miss_latency::cpu0.data 16921005268 # number of overall MSHR miss cycles
3074 system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of overall MSHR miss cycles
3075 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of overall MSHR miss cycles
3076 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 134631004 # number of overall MSHR miss cycles
3077 system.l2c.overall_mshr_miss_latency::cpu1.inst 3315499572 # number of overall MSHR miss cycles
3078 system.l2c.overall_mshr_miss_latency::cpu1.data 11755747400 # number of overall MSHR miss cycles
3079 system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of overall MSHR miss cycles
3080 system.l2c.overall_mshr_miss_latency::total 81808661160 # number of overall MSHR miss cycles
3081 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles
3082 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4354335503 # number of ReadReq MSHR uncacheable cycles
3083 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7420500 # number of ReadReq MSHR uncacheable cycles
3084 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1601314002 # number of ReadReq MSHR uncacheable cycles
3085 system.l2c.ReadReq_mshr_uncacheable_latency::total 8682852005 # number of ReadReq MSHR uncacheable cycles
3086 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles
3087 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4354335503 # number of overall MSHR uncacheable cycles
3088 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7420500 # number of overall MSHR uncacheable cycles
3089 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1601314002 # number of overall MSHR uncacheable cycles
3090 system.l2c.overall_mshr_uncacheable_latency::total 8682852005 # number of overall MSHR uncacheable cycles
3091 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3092 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3093 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.281261 # mshr miss rate for UpgradeReq accesses
3094 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315767 # mshr miss rate for UpgradeReq accesses
3095 system.l2c.UpgradeReq_mshr_miss_rate::total 0.297398 # mshr miss rate for UpgradeReq accesses
3096 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.256383 # mshr miss rate for SCUpgradeReq accesses
3097 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.267881 # mshr miss rate for SCUpgradeReq accesses
3098 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.262106 # mshr miss rate for SCUpgradeReq accesses
3099 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.636223 # mshr miss rate for ReadExReq accesses
3100 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466619 # mshr miss rate for ReadExReq accesses
3101 system.l2c.ReadExReq_mshr_miss_rate::total 0.558420 # mshr miss rate for ReadExReq accesses
3102 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for ReadSharedReq accesses
3103 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for ReadSharedReq accesses
3104 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for ReadSharedReq accesses
3105 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199992 # mshr miss rate for ReadSharedReq accesses
3106 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for ReadSharedReq accesses
3107 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for ReadSharedReq accesses
3108 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for ReadSharedReq accesses
3109 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for ReadSharedReq accesses
3110 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.156065 # mshr miss rate for ReadSharedReq accesses
3111 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for ReadSharedReq accesses
3112 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231890 # mshr miss rate for ReadSharedReq accesses
3113 system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.791527 # mshr miss rate for InvalidateReq accesses
3114 system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489286 # mshr miss rate for InvalidateReq accesses
3115 system.l2c.InvalidateReq_mshr_miss_rate::total 0.701201 # mshr miss rate for InvalidateReq accesses
3116 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for demand accesses
3117 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for demand accesses
3118 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for demand accesses
3119 system.l2c.demand_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for demand accesses
3120 system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for demand accesses
3121 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for demand accesses
3122 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for demand accesses
3123 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for demand accesses
3124 system.l2c.demand_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for demand accesses
3125 system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for demand accesses
3126 system.l2c.demand_mshr_miss_rate::total 0.254259 # mshr miss rate for demand accesses
3127 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for overall accesses
3128 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for overall accesses
3129 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for overall accesses
3130 system.l2c.overall_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for overall accesses
3131 system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for overall accesses
3132 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for overall accesses
3133 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for overall accesses
3134 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for overall accesses
3135 system.l2c.overall_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for overall accesses
3136 system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for overall accesses
3137 system.l2c.overall_mshr_miss_rate::total 0.254259 # mshr miss rate for overall accesses
3138 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21760.189820 # average UpgradeReq mshr miss latency
3139 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21827.206064 # average UpgradeReq mshr miss latency
3140 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21793.465721 # average UpgradeReq mshr miss latency
3141 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154 # average SCUpgradeReq mshr miss latency
3142 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840 # average SCUpgradeReq mshr miss latency
3143 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679 # average SCUpgradeReq mshr miss latency
3144 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538 # average ReadExReq mshr miss latency
3145 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289 # average ReadExReq mshr miss latency
3146 system.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159 # average ReadExReq mshr miss latency
3147 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average ReadSharedReq mshr miss latency
3148 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average ReadSharedReq mshr miss latency
3149 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average ReadSharedReq mshr miss latency
3150 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441 # average ReadSharedReq mshr miss latency
3151 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average ReadSharedReq mshr miss latency
3152 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average ReadSharedReq mshr miss latency
3153 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average ReadSharedReq mshr miss latency
3154 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average ReadSharedReq mshr miss latency
3155 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359 # average ReadSharedReq mshr miss latency
3156 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average ReadSharedReq mshr miss latency
3157 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611 # average ReadSharedReq mshr miss latency
3158 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087 # average InvalidateReq mshr miss latency
3159 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730 # average InvalidateReq mshr miss latency
3160 system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203 # average InvalidateReq mshr miss latency
3161 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency
3162 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency
3163 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency
3164 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency
3165 system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency
3166 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency
3167 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency
3168 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency
3169 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency
3170 system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency
3171 system.l2c.demand_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency
3172 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency
3173 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency
3174 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency
3175 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency
3176 system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency
3177 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency
3178 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency
3179 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency
3180 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency
3181 system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency
3182 system.l2c.overall_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency
3183 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency
3184 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency
3185 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency
3186 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency
3187 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency
3188 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency
3189 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency
3190 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency
3191 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency
3192 system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency
3193 system.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter.
3194 system.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3195 system.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3196 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3197 system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3198 system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3199 system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3200 system.membus.trans_dist::ReadReq 81829 # Transaction distribution
3201 system.membus.trans_dist::ReadResp 838129 # Transaction distribution
3202 system.membus.trans_dist::WriteReq 38464 # Transaction distribution
3203 system.membus.trans_dist::WriteResp 38464 # Transaction distribution
3204 system.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution
3205 system.membus.trans_dist::CleanEvict 216961 # Transaction distribution
3206 system.membus.trans_dist::UpgradeReq 398327 # Transaction distribution
3207 system.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution
3208 system.membus.trans_dist::UpgradeResp 22 # Transaction distribution
3209 system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
3210 system.membus.trans_dist::ReadExReq 145872 # Transaction distribution
3211 system.membus.trans_dist::ReadExResp 127949 # Transaction distribution
3212 system.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution
3213 system.membus.trans_dist::InvalidateReq 666856 # Transaction distribution
3214 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes)
3215 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3216 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes)
3217 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes)
3218 system.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes)
3219 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes)
3220 system.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes)
3221 system.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes)
3222 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes)
3223 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3224 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes)
3225 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes)
3226 system.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes)
3227 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes)
3228 system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes)
3229 system.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes)
3230 system.membus.snoops 572885 # Total snoops (count)
3231 system.membus.snoopTraffic 188480 # Total snoop traffic (bytes)
3232 system.membus.snoop_fanout::samples 2396814 # Request fanout histogram
3233 system.membus.snoop_fanout::mean 0.013654 # Request fanout histogram
3234 system.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram
3235 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3236 system.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram
3237 system.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram
3238 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3239 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3240 system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3241 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3242 system.membus.snoop_fanout::total 2396814 # Request fanout histogram
3243 system.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks)
3244 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3245 system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3246 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3247 system.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks)
3248 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3249 system.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks)
3250 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3251 system.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks)
3252 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3253 system.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks)
3254 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3255 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3256 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3257 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3258 system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3259 system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3260 system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3261 system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3262 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3263 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3264 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3265 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3266 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3267 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3268 system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3269 system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3270 system.realview.ethernet.txBytes 966 # Bytes Transmitted
3271 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3272 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3273 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3274 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3275 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3276 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3277 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3278 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3279 system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
3280 system.realview.ethernet.totPackets 3 # Total Packets
3281 system.realview.ethernet.totBytes 966 # Total Bytes
3282 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
3283 system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
3284 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
3285 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3286 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
3287 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3288 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3289 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
3290 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3291 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3292 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
3293 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3294 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3295 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
3296 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3297 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3298 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
3299 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3300 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3301 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
3302 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3303 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3304 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3305 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3306 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3307 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3308 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3309 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3310 system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3311 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3312 system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3313 system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3314 system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3315 system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3316 system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3317 system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3318 system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3319 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3320 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3321 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3322 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3323 system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3324 system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3325 system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3326 system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3327 system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3328 system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3329 system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3330 system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3331 system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3332 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3333 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3334 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3335 system.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter.
3336 system.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3337 system.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3338 system.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter.
3339 system.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3340 system.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3341 system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3342 system.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution
3343 system.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution
3344 system.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution
3345 system.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution
3346 system.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution
3347 system.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution
3348 system.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution
3349 system.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution
3350 system.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution
3351 system.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution
3352 system.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution
3353 system.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution
3354 system.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution
3355 system.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution
3356 system.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution
3357 system.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution
3358 system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes)
3359 system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes)
3360 system.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes)
3361 system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes)
3362 system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes)
3363 system.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes)
3364 system.toL2Bus.snoops 2716758 # Total snoops (count)
3365 system.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes)
3366 system.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram
3367 system.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram
3368 system.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram
3369 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3370 system.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram
3371 system.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram
3372 system.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram
3373 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3374 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3375 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3376 system.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram
3377 system.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks)
3378 system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3379 system.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks)
3380 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3381 system.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks)
3382 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3383 system.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks)
3384 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3386 ---------- End Simulation Statistics ----------
projects / gem5.git / blob