2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 51.278396 # Number of seconds simulated
4 sim_ticks 51278396244000 # Number of ticks simulated
5 final_tick 51278396244000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 287420 # Simulator instruction rate (inst/s)
8 host_op_rate 337741 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 17381457033 # Simulator tick rate (ticks/s)
10 host_mem_usage 688188 # Number of bytes of host memory used
11 host_seconds 2950.18 # Real time elapsed on the host
12 sim_insts 847940135 # Number of instructions simulated
13 sim_ops 996397451 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 80128 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 85632 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 2427380 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 43615880 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.dtb.walker 26944 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.itb.walker 22528 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.inst 448704 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.data 6225152 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu2.dtb.walker 27008 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu2.itb.walker 28160 # Number of bytes read from this memory
26 system.physmem.bytes_read::cpu2.inst 1496000 # Number of bytes read from this memory
27 system.physmem.bytes_read::cpu2.data 7976640 # Number of bytes read from this memory
28 system.physmem.bytes_read::cpu3.dtb.walker 59008 # Number of bytes read from this memory
29 system.physmem.bytes_read::cpu3.itb.walker 56384 # Number of bytes read from this memory
30 system.physmem.bytes_read::cpu3.inst 1720000 # Number of bytes read from this memory
31 system.physmem.bytes_read::cpu3.data 14392384 # Number of bytes read from this memory
32 system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory
33 system.physmem.bytes_read::total 79110012 # Number of bytes read from this memory
34 system.physmem.bytes_inst_read::cpu0.inst 2427380 # Number of instructions bytes read from this memory
35 system.physmem.bytes_inst_read::cpu1.inst 448704 # Number of instructions bytes read from this memory
36 system.physmem.bytes_inst_read::cpu2.inst 1496000 # Number of instructions bytes read from this memory
37 system.physmem.bytes_inst_read::cpu3.inst 1720000 # Number of instructions bytes read from this memory
38 system.physmem.bytes_inst_read::total 6092084 # Number of instructions bytes read from this memory
39 system.physmem.bytes_written::writebacks 67404672 # Number of bytes written to this memory
40 system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
41 system.physmem.bytes_written::total 67425252 # Number of bytes written to this memory
42 system.physmem.num_reads::cpu0.dtb.walker 1252 # Number of read requests responded to by this memory
43 system.physmem.num_reads::cpu0.itb.walker 1338 # Number of read requests responded to by this memory
44 system.physmem.num_reads::cpu0.inst 78335 # Number of read requests responded to by this memory
45 system.physmem.num_reads::cpu0.data 681511 # Number of read requests responded to by this memory
46 system.physmem.num_reads::cpu1.dtb.walker 421 # Number of read requests responded to by this memory
47 system.physmem.num_reads::cpu1.itb.walker 352 # Number of read requests responded to by this memory
48 system.physmem.num_reads::cpu1.inst 7011 # Number of read requests responded to by this memory
49 system.physmem.num_reads::cpu1.data 97268 # Number of read requests responded to by this memory
50 system.physmem.num_reads::cpu2.dtb.walker 422 # Number of read requests responded to by this memory
51 system.physmem.num_reads::cpu2.itb.walker 440 # Number of read requests responded to by this memory
52 system.physmem.num_reads::cpu2.inst 23375 # Number of read requests responded to by this memory
53 system.physmem.num_reads::cpu2.data 124635 # Number of read requests responded to by this memory
54 system.physmem.num_reads::cpu3.dtb.walker 922 # Number of read requests responded to by this memory
55 system.physmem.num_reads::cpu3.itb.walker 881 # Number of read requests responded to by this memory
56 system.physmem.num_reads::cpu3.inst 26875 # Number of read requests responded to by this memory
57 system.physmem.num_reads::cpu3.data 224881 # Number of read requests responded to by this memory
58 system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory
59 system.physmem.num_reads::total 1276514 # Number of read requests responded to by this memory
60 system.physmem.num_writes::writebacks 1053198 # Number of write requests responded to by this memory
61 system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
62 system.physmem.num_writes::total 1055771 # Number of write requests responded to by this memory
63 system.physmem.bw_read::cpu0.dtb.walker 1563 # Total read bandwidth from this memory (bytes/s)
64 system.physmem.bw_read::cpu0.itb.walker 1670 # Total read bandwidth from this memory (bytes/s)
65 system.physmem.bw_read::cpu0.inst 47337 # Total read bandwidth from this memory (bytes/s)
66 system.physmem.bw_read::cpu0.data 850570 # Total read bandwidth from this memory (bytes/s)
67 system.physmem.bw_read::cpu1.dtb.walker 525 # Total read bandwidth from this memory (bytes/s)
68 system.physmem.bw_read::cpu1.itb.walker 439 # Total read bandwidth from this memory (bytes/s)
69 system.physmem.bw_read::cpu1.inst 8750 # Total read bandwidth from this memory (bytes/s)
70 system.physmem.bw_read::cpu1.data 121399 # Total read bandwidth from this memory (bytes/s)
71 system.physmem.bw_read::cpu2.dtb.walker 527 # Total read bandwidth from this memory (bytes/s)
72 system.physmem.bw_read::cpu2.itb.walker 549 # Total read bandwidth from this memory (bytes/s)
73 system.physmem.bw_read::cpu2.inst 29174 # Total read bandwidth from this memory (bytes/s)
74 system.physmem.bw_read::cpu2.data 155556 # Total read bandwidth from this memory (bytes/s)
75 system.physmem.bw_read::cpu3.dtb.walker 1151 # Total read bandwidth from this memory (bytes/s)
76 system.physmem.bw_read::cpu3.itb.walker 1100 # Total read bandwidth from this memory (bytes/s)
77 system.physmem.bw_read::cpu3.inst 33542 # Total read bandwidth from this memory (bytes/s)
78 system.physmem.bw_read::cpu3.data 280671 # Total read bandwidth from this memory (bytes/s)
79 system.physmem.bw_read::realview.ide 8231 # Total read bandwidth from this memory (bytes/s)
80 system.physmem.bw_read::total 1542755 # Total read bandwidth from this memory (bytes/s)
81 system.physmem.bw_inst_read::cpu0.inst 47337 # Instruction read bandwidth from this memory (bytes/s)
82 system.physmem.bw_inst_read::cpu1.inst 8750 # Instruction read bandwidth from this memory (bytes/s)
83 system.physmem.bw_inst_read::cpu2.inst 29174 # Instruction read bandwidth from this memory (bytes/s)
84 system.physmem.bw_inst_read::cpu3.inst 33542 # Instruction read bandwidth from this memory (bytes/s)
85 system.physmem.bw_inst_read::total 118804 # Instruction read bandwidth from this memory (bytes/s)
86 system.physmem.bw_write::writebacks 1314485 # Write bandwidth from this memory (bytes/s)
87 system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
88 system.physmem.bw_write::total 1314886 # Write bandwidth from this memory (bytes/s)
89 system.physmem.bw_total::writebacks 1314485 # Total bandwidth to/from this memory (bytes/s)
90 system.physmem.bw_total::cpu0.dtb.walker 1563 # Total bandwidth to/from this memory (bytes/s)
91 system.physmem.bw_total::cpu0.itb.walker 1670 # Total bandwidth to/from this memory (bytes/s)
92 system.physmem.bw_total::cpu0.inst 47337 # Total bandwidth to/from this memory (bytes/s)
93 system.physmem.bw_total::cpu0.data 850972 # Total bandwidth to/from this memory (bytes/s)
94 system.physmem.bw_total::cpu1.dtb.walker 525 # Total bandwidth to/from this memory (bytes/s)
95 system.physmem.bw_total::cpu1.itb.walker 439 # Total bandwidth to/from this memory (bytes/s)
96 system.physmem.bw_total::cpu1.inst 8750 # Total bandwidth to/from this memory (bytes/s)
97 system.physmem.bw_total::cpu1.data 121399 # Total bandwidth to/from this memory (bytes/s)
98 system.physmem.bw_total::cpu2.dtb.walker 527 # Total bandwidth to/from this memory (bytes/s)
99 system.physmem.bw_total::cpu2.itb.walker 549 # Total bandwidth to/from this memory (bytes/s)
100 system.physmem.bw_total::cpu2.inst 29174 # Total bandwidth to/from this memory (bytes/s)
101 system.physmem.bw_total::cpu2.data 155556 # Total bandwidth to/from this memory (bytes/s)
102 system.physmem.bw_total::cpu3.dtb.walker 1151 # Total bandwidth to/from this memory (bytes/s)
103 system.physmem.bw_total::cpu3.itb.walker 1100 # Total bandwidth to/from this memory (bytes/s)
104 system.physmem.bw_total::cpu3.inst 33542 # Total bandwidth to/from this memory (bytes/s)
105 system.physmem.bw_total::cpu3.data 280671 # Total bandwidth to/from this memory (bytes/s)
106 system.physmem.bw_total::realview.ide 8231 # Total bandwidth to/from this memory (bytes/s)
107 system.physmem.bw_total::total 2857641 # Total bandwidth to/from this memory (bytes/s)
108 system.physmem.readReqs 511823 # Number of read requests accepted
109 system.physmem.writeReqs 447580 # Number of write requests accepted
110 system.physmem.readBursts 511823 # Number of DRAM read bursts, including those serviced by the write queue
111 system.physmem.writeBursts 447580 # Number of DRAM write bursts, including those merged in the write queue
112 system.physmem.bytesReadDRAM 32737280 # Total number of bytes read from DRAM
113 system.physmem.bytesReadWrQ 19392 # Total number of bytes read from write queue
114 system.physmem.bytesWritten 28644032 # Total number of bytes written to DRAM
115 system.physmem.bytesReadSys 32756672 # Total read bytes from the system interface side
116 system.physmem.bytesWrittenSys 28645120 # Total written bytes from the system interface side
117 system.physmem.servicedByWrQ 303 # Number of DRAM read bursts serviced by the write queue
118 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
119 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
120 system.physmem.perBankRdBursts::0 29703 # Per bank write bursts
121 system.physmem.perBankRdBursts::1 34345 # Per bank write bursts
122 system.physmem.perBankRdBursts::2 31026 # Per bank write bursts
123 system.physmem.perBankRdBursts::3 30271 # Per bank write bursts
124 system.physmem.perBankRdBursts::4 32199 # Per bank write bursts
125 system.physmem.perBankRdBursts::5 37423 # Per bank write bursts
126 system.physmem.perBankRdBursts::6 31570 # Per bank write bursts
127 system.physmem.perBankRdBursts::7 30956 # Per bank write bursts
128 system.physmem.perBankRdBursts::8 30714 # Per bank write bursts
129 system.physmem.perBankRdBursts::9 34361 # Per bank write bursts
130 system.physmem.perBankRdBursts::10 33202 # Per bank write bursts
131 system.physmem.perBankRdBursts::11 32791 # Per bank write bursts
132 system.physmem.perBankRdBursts::12 32230 # Per bank write bursts
133 system.physmem.perBankRdBursts::13 32440 # Per bank write bursts
134 system.physmem.perBankRdBursts::14 29459 # Per bank write bursts
135 system.physmem.perBankRdBursts::15 28830 # Per bank write bursts
136 system.physmem.perBankWrBursts::0 25970 # Per bank write bursts
137 system.physmem.perBankWrBursts::1 28442 # Per bank write bursts
138 system.physmem.perBankWrBursts::2 26808 # Per bank write bursts
139 system.physmem.perBankWrBursts::3 27272 # Per bank write bursts
140 system.physmem.perBankWrBursts::4 29035 # Per bank write bursts
141 system.physmem.perBankWrBursts::5 31977 # Per bank write bursts
142 system.physmem.perBankWrBursts::6 28169 # Per bank write bursts
143 system.physmem.perBankWrBursts::7 28603 # Per bank write bursts
144 system.physmem.perBankWrBursts::8 27151 # Per bank write bursts
145 system.physmem.perBankWrBursts::9 29537 # Per bank write bursts
146 system.physmem.perBankWrBursts::10 28051 # Per bank write bursts
147 system.physmem.perBankWrBursts::11 28561 # Per bank write bursts
148 system.physmem.perBankWrBursts::12 27796 # Per bank write bursts
149 system.physmem.perBankWrBursts::13 28123 # Per bank write bursts
150 system.physmem.perBankWrBursts::14 26050 # Per bank write bursts
151 system.physmem.perBankWrBursts::15 26018 # Per bank write bursts
152 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
153 system.physmem.numWrRetry 29 # Number of times write queue was full causing retry
154 system.physmem.totGap 51277395805500 # Total gap between requests
155 system.physmem.readPktSize::0 0 # Read request sizes (log2)
156 system.physmem.readPktSize::1 0 # Read request sizes (log2)
157 system.physmem.readPktSize::2 0 # Read request sizes (log2)
158 system.physmem.readPktSize::3 0 # Read request sizes (log2)
159 system.physmem.readPktSize::4 0 # Read request sizes (log2)
160 system.physmem.readPktSize::5 0 # Read request sizes (log2)
161 system.physmem.readPktSize::6 511823 # Read request sizes (log2)
162 system.physmem.writePktSize::0 0 # Write request sizes (log2)
163 system.physmem.writePktSize::1 0 # Write request sizes (log2)
164 system.physmem.writePktSize::2 0 # Write request sizes (log2)
165 system.physmem.writePktSize::3 0 # Write request sizes (log2)
166 system.physmem.writePktSize::4 0 # Write request sizes (log2)
167 system.physmem.writePktSize::5 0 # Write request sizes (log2)
168 system.physmem.writePktSize::6 447580 # Write request sizes (log2)
169 system.physmem.rdQLenPdf::0 363555 # What read queue length does an incoming req see
170 system.physmem.rdQLenPdf::1 93711 # What read queue length does an incoming req see
171 system.physmem.rdQLenPdf::2 31585 # What read queue length does an incoming req see
172 system.physmem.rdQLenPdf::3 19104 # What read queue length does an incoming req see
173 system.physmem.rdQLenPdf::4 420 # What read queue length does an incoming req see
174 system.physmem.rdQLenPdf::5 374 # What read queue length does an incoming req see
175 system.physmem.rdQLenPdf::6 356 # What read queue length does an incoming req see
176 system.physmem.rdQLenPdf::7 769 # What read queue length does an incoming req see
177 system.physmem.rdQLenPdf::8 457 # What read queue length does an incoming req see
178 system.physmem.rdQLenPdf::9 237 # What read queue length does an incoming req see
179 system.physmem.rdQLenPdf::10 242 # What read queue length does an incoming req see
180 system.physmem.rdQLenPdf::11 118 # What read queue length does an incoming req see
181 system.physmem.rdQLenPdf::12 102 # What read queue length does an incoming req see
182 system.physmem.rdQLenPdf::13 87 # What read queue length does an incoming req see
183 system.physmem.rdQLenPdf::14 83 # What read queue length does an incoming req see
184 system.physmem.rdQLenPdf::15 79 # What read queue length does an incoming req see
185 system.physmem.rdQLenPdf::16 70 # What read queue length does an incoming req see
186 system.physmem.rdQLenPdf::17 66 # What read queue length does an incoming req see
187 system.physmem.rdQLenPdf::18 57 # What read queue length does an incoming req see
188 system.physmem.rdQLenPdf::19 40 # What read queue length does an incoming req see
189 system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
190 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
191 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
192 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
193 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
194 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
195 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
196 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
197 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
198 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
199 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
200 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
201 system.physmem.wrQLenPdf::0 594 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::1 582 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::2 577 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::3 574 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::4 572 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::6 566 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::7 565 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::8 564 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::9 564 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::11 557 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::12 550 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::14 559 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::15 7257 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::16 8731 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::17 19434 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::18 21637 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::19 24704 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::20 25741 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::21 25599 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::22 25799 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::23 26255 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::24 26532 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::25 27053 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::26 28426 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::27 27490 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::28 27929 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::29 30961 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::30 26710 # What write queue length does an incoming req see
232 system.physmem.wrQLenPdf::31 26732 # What write queue length does an incoming req see
233 system.physmem.wrQLenPdf::32 25592 # What write queue length does an incoming req see
234 system.physmem.wrQLenPdf::33 1484 # What write queue length does an incoming req see
235 system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see
236 system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see
237 system.physmem.wrQLenPdf::36 273 # What write queue length does an incoming req see
238 system.physmem.wrQLenPdf::37 337 # What write queue length does an incoming req see
239 system.physmem.wrQLenPdf::38 284 # What write queue length does an incoming req see
240 system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see
241 system.physmem.wrQLenPdf::40 184 # What write queue length does an incoming req see
242 system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see
243 system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see
244 system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see
245 system.physmem.wrQLenPdf::44 158 # What write queue length does an incoming req see
246 system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see
247 system.physmem.wrQLenPdf::46 131 # What write queue length does an incoming req see
248 system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see
249 system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see
250 system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
251 system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see
252 system.physmem.wrQLenPdf::51 109 # What write queue length does an incoming req see
253 system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see
254 system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see
255 system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see
256 system.physmem.wrQLenPdf::55 127 # What write queue length does an incoming req see
257 system.physmem.wrQLenPdf::56 146 # What write queue length does an incoming req see
258 system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see
259 system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see
260 system.physmem.wrQLenPdf::59 104 # What write queue length does an incoming req see
261 system.physmem.wrQLenPdf::60 70 # What write queue length does an incoming req see
262 system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see
263 system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see
264 system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see
265 system.physmem.bytesPerActivate::samples 257915 # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::mean 237.988981 # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::gmean 144.092695 # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::stdev 278.727383 # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::0-127 118797 46.06% 46.06% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::128-255 64316 24.94% 71.00% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::256-383 23486 9.11% 80.10% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::384-511 11936 4.63% 84.73% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::512-639 8805 3.41% 88.15% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::640-767 5543 2.15% 90.29% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::768-895 4520 1.75% 92.05% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::896-1023 3591 1.39% 93.44% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::1024-1151 16921 6.56% 100.00% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::total 257915 # Bytes accessed per row activation
279 system.physmem.rdPerTurnAround::samples 24705 # Reads before turning the bus around for writes
280 system.physmem.rdPerTurnAround::mean 20.705080 # Reads before turning the bus around for writes
281 system.physmem.rdPerTurnAround::stdev 14.399508 # Reads before turning the bus around for writes
282 system.physmem.rdPerTurnAround::0-63 24532 99.30% 99.30% # Reads before turning the bus around for writes
283 system.physmem.rdPerTurnAround::64-127 158 0.64% 99.94% # Reads before turning the bus around for writes
284 system.physmem.rdPerTurnAround::128-191 5 0.02% 99.96% # Reads before turning the bus around for writes
285 system.physmem.rdPerTurnAround::192-255 5 0.02% 99.98% # Reads before turning the bus around for writes
286 system.physmem.rdPerTurnAround::256-319 1 0.00% 99.98% # Reads before turning the bus around for writes
287 system.physmem.rdPerTurnAround::512-575 1 0.00% 99.99% # Reads before turning the bus around for writes
288 system.physmem.rdPerTurnAround::640-703 2 0.01% 100.00% # Reads before turning the bus around for writes
289 system.physmem.rdPerTurnAround::1088-1151 1 0.00% 100.00% # Reads before turning the bus around for writes
290 system.physmem.rdPerTurnAround::total 24705 # Reads before turning the bus around for writes
291 system.physmem.wrPerTurnAround::samples 24705 # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::mean 18.116292 # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::gmean 17.314740 # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::stdev 8.551029 # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::0-3 22 0.09% 0.09% # Writes before turning the bus around for reads
296 system.physmem.wrPerTurnAround::4-7 13 0.05% 0.14% # Writes before turning the bus around for reads
297 system.physmem.wrPerTurnAround::8-11 13 0.05% 0.19% # Writes before turning the bus around for reads
298 system.physmem.wrPerTurnAround::12-15 49 0.20% 0.39% # Writes before turning the bus around for reads
299 system.physmem.wrPerTurnAround::16-19 23047 93.29% 93.68% # Writes before turning the bus around for reads
300 system.physmem.wrPerTurnAround::20-23 446 1.81% 95.49% # Writes before turning the bus around for reads
301 system.physmem.wrPerTurnAround::24-27 165 0.67% 96.15% # Writes before turning the bus around for reads
302 system.physmem.wrPerTurnAround::28-31 178 0.72% 96.88% # Writes before turning the bus around for reads
303 system.physmem.wrPerTurnAround::32-35 51 0.21% 97.08% # Writes before turning the bus around for reads
304 system.physmem.wrPerTurnAround::36-39 35 0.14% 97.22% # Writes before turning the bus around for reads
305 system.physmem.wrPerTurnAround::40-43 69 0.28% 97.50% # Writes before turning the bus around for reads
306 system.physmem.wrPerTurnAround::44-47 9 0.04% 97.54% # Writes before turning the bus around for reads
307 system.physmem.wrPerTurnAround::48-51 185 0.75% 98.29% # Writes before turning the bus around for reads
308 system.physmem.wrPerTurnAround::52-55 38 0.15% 98.44% # Writes before turning the bus around for reads
309 system.physmem.wrPerTurnAround::56-59 14 0.06% 98.50% # Writes before turning the bus around for reads
310 system.physmem.wrPerTurnAround::60-63 28 0.11% 98.61% # Writes before turning the bus around for reads
311 system.physmem.wrPerTurnAround::64-67 125 0.51% 99.12% # Writes before turning the bus around for reads
312 system.physmem.wrPerTurnAround::68-71 16 0.06% 99.18% # Writes before turning the bus around for reads
313 system.physmem.wrPerTurnAround::72-75 10 0.04% 99.22% # Writes before turning the bus around for reads
314 system.physmem.wrPerTurnAround::76-79 68 0.28% 99.50% # Writes before turning the bus around for reads
315 system.physmem.wrPerTurnAround::80-83 94 0.38% 99.88% # Writes before turning the bus around for reads
316 system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads
317 system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads
318 system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads
319 system.physmem.wrPerTurnAround::100-103 2 0.01% 99.90% # Writes before turning the bus around for reads
320 system.physmem.wrPerTurnAround::112-115 5 0.02% 99.92% # Writes before turning the bus around for reads
321 system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads
322 system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
323 system.physmem.wrPerTurnAround::128-131 5 0.02% 99.95% # Writes before turning the bus around for reads
324 system.physmem.wrPerTurnAround::140-143 2 0.01% 99.96% # Writes before turning the bus around for reads
325 system.physmem.wrPerTurnAround::144-147 10 0.04% 100.00% # Writes before turning the bus around for reads
326 system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
327 system.physmem.wrPerTurnAround::total 24705 # Writes before turning the bus around for reads
328 system.physmem.totQLat 10604540202 # Total ticks spent queuing
329 system.physmem.totMemAccLat 20195540202 # Total ticks spent from burst creation until serviced by the DRAM
330 system.physmem.totBusLat 2557600000 # Total ticks spent in databus transfers
331 system.physmem.avgQLat 20731.43 # Average queueing delay per DRAM burst
332 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
333 system.physmem.avgMemAccLat 39481.43 # Average memory access latency per DRAM burst
334 system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s
335 system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MiByte/s
336 system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s
337 system.physmem.avgWrBWSys 0.56 # Average system write bandwidth in MiByte/s
338 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
339 system.physmem.busUtil 0.01 # Data bus utilization in percentage
340 system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
341 system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
342 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
343 system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing
344 system.physmem.readRowHits 390042 # Number of row buffer hits during reads
345 system.physmem.writeRowHits 311121 # Number of row buffer hits during writes
346 system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads
347 system.physmem.writeRowHitRate 69.51 # Row buffer hit rate for writes
348 system.physmem.avgGap 53447191.44 # Average gap between requests
349 system.physmem.pageHitRate 73.11 # Row buffer hit rate, read and write combined
350 system.physmem_0.actEnergy 987139440 # Energy for activate commands per rank (pJ)
351 system.physmem_0.preEnergy 536905875 # Energy for precharge commands per rank (pJ)
352 system.physmem_0.readEnergy 2008390800 # Energy for read commands per rank (pJ)
353 system.physmem_0.writeEnergy 1466203680 # Energy for write commands per rank (pJ)
354 system.physmem_0.refreshEnergy 3310428600960 # Energy for refresh commands per rank (pJ)
355 system.physmem_0.actBackEnergy 1177085104875 # Energy for active background per rank (pJ)
356 system.physmem_0.preBackEnergy 30106909725750 # Energy for precharge background per rank (pJ)
357 system.physmem_0.totalEnergy 34599422071380 # Total energy per rank (pJ)
358 system.physmem_0.averagePower 666.667509 # Core power per rank (mW)
359 system.physmem_0.memoryStateTime::IDLE 48872262134916 # Time in different power states
360 system.physmem_0.memoryStateTime::REF 1692448160000 # Time in different power states
361 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
362 system.physmem_0.memoryStateTime::ACT 119734785584 # Time in different power states
363 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
364 system.physmem_1.actEnergy 962629920 # Energy for activate commands per rank (pJ)
365 system.physmem_1.preEnergy 523549125 # Energy for precharge commands per rank (pJ)
366 system.physmem_1.readEnergy 1981395000 # Energy for read commands per rank (pJ)
367 system.physmem_1.writeEnergy 1433900880 # Energy for write commands per rank (pJ)
368 system.physmem_1.refreshEnergy 3310428600960 # Energy for refresh commands per rank (pJ)
369 system.physmem_1.actBackEnergy 1177786265580 # Energy for active background per rank (pJ)
370 system.physmem_1.preBackEnergy 29667035331750 # Energy for precharge background per rank (pJ)
371 system.physmem_1.totalEnergy 34160151673215 # Total energy per rank (pJ)
372 system.physmem_1.averagePower 667.621174 # Core power per rank (mW)
373 system.physmem_1.memoryStateTime::IDLE 48871271616428 # Time in different power states
374 system.physmem_1.memoryStateTime::REF 1692448160000 # Time in different power states
375 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
376 system.physmem_1.memoryStateTime::ACT 120718837572 # Time in different power states
377 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
378 system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
379 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
380 system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
381 system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
382 system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
383 system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
384 system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
385 system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
386 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
387 system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
388 system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
389 system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
390 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
391 system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
392 system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
393 system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
394 system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
395 system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
396 system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
397 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
398 system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
399 system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
400 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
401 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
402 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
403 system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
404 system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
405 system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
406 system.cpu_clk_domain.clock 500 # Clock period in ticks
407 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
408 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
409 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
410 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
411 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
412 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
413 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
414 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
415 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
416 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
417 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
418 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
419 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
420 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
421 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
422 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
423 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
424 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
425 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
426 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
427 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
428 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
429 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
430 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
431 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
432 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
433 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
434 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
435 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
436 system.cpu0.dtb.walker.walks 90127 # Table walker walks requested
437 system.cpu0.dtb.walker.walksLong 90127 # Table walker walks initiated with long descriptors
438 system.cpu0.dtb.walker.walkWaitTime::samples 90127 # Table walker wait (enqueue to first request) latency
439 system.cpu0.dtb.walker.walkWaitTime::0 90127 100.00% 100.00% # Table walker wait (enqueue to first request) latency
440 system.cpu0.dtb.walker.walkWaitTime::total 90127 # Table walker wait (enqueue to first request) latency
441 system.cpu0.dtb.walker.walksPending::samples 389002834492 # Table walker pending requests distribution
442 system.cpu0.dtb.walker.walksPending::mean 1.524244 # Table walker pending requests distribution
443 system.cpu0.dtb.walker.walksPending::0 -203932266508 -52.42% -52.42% # Table walker pending requests distribution
444 system.cpu0.dtb.walker.walksPending::1 592935101000 152.42% 100.00% # Table walker pending requests distribution
445 system.cpu0.dtb.walker.walksPending::total 389002834492 # Table walker pending requests distribution
446 system.cpu0.dtb.walker.walkPageSizes::4K 65772 85.00% 85.00% # Table walker page sizes translated
447 system.cpu0.dtb.walker.walkPageSizes::2M 11604 15.00% 100.00% # Table walker page sizes translated
448 system.cpu0.dtb.walker.walkPageSizes::total 77376 # Table walker page sizes translated
449 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90127 # Table walker requests started/completed, data/inst
450 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
451 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90127 # Table walker requests started/completed, data/inst
452 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77376 # Table walker requests started/completed, data/inst
453 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
454 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77376 # Table walker requests started/completed, data/inst
455 system.cpu0.dtb.walker.walkRequestOrigin::total 167503 # Table walker requests started/completed, data/inst
456 system.cpu0.dtb.inst_hits 0 # ITB inst hits
457 system.cpu0.dtb.inst_misses 0 # ITB inst misses
458 system.cpu0.dtb.read_hits 64859725 # DTB read hits
459 system.cpu0.dtb.read_misses 68631 # DTB read misses
460 system.cpu0.dtb.write_hits 59094124 # DTB write hits
461 system.cpu0.dtb.write_misses 21496 # DTB write misses
462 system.cpu0.dtb.flush_tlb 1195 # Number of times complete TLB was flushed
463 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
464 system.cpu0.dtb.flush_tlb_mva_asid 16177 # Number of times TLB was flushed by MVA & ASID
465 system.cpu0.dtb.flush_tlb_asid 384 # Number of times TLB was flushed by ASID
466 system.cpu0.dtb.flush_entries 40401 # Number of entries that have been flushed from TLB
467 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
468 system.cpu0.dtb.prefetch_faults 2751 # Number of TLB faults due to prefetch
469 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
470 system.cpu0.dtb.perms_faults 7419 # Number of TLB faults due to permissions restrictions
471 system.cpu0.dtb.read_accesses 64928356 # DTB read accesses
472 system.cpu0.dtb.write_accesses 59115620 # DTB write accesses
473 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
474 system.cpu0.dtb.hits 123953849 # DTB hits
475 system.cpu0.dtb.misses 90127 # DTB misses
476 system.cpu0.dtb.accesses 124043976 # DTB accesses
477 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
478 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
479 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
480 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
481 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
482 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
483 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
484 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
485 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
486 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
487 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
488 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
489 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
490 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
491 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
492 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
493 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
494 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
495 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
496 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
497 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
498 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
499 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
500 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
501 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
502 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
503 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
504 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
505 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
506 system.cpu0.itb.walker.walks 53226 # Table walker walks requested
507 system.cpu0.itb.walker.walksLong 53226 # Table walker walks initiated with long descriptors
508 system.cpu0.itb.walker.walkWaitTime::samples 53226 # Table walker wait (enqueue to first request) latency
509 system.cpu0.itb.walker.walkWaitTime::0 53226 100.00% 100.00% # Table walker wait (enqueue to first request) latency
510 system.cpu0.itb.walker.walkWaitTime::total 53226 # Table walker wait (enqueue to first request) latency
511 system.cpu0.itb.walker.walksPending::samples 389002834492 # Table walker pending requests distribution
512 system.cpu0.itb.walker.walksPending::mean 1.524351 # Table walker pending requests distribution
513 system.cpu0.itb.walker.walksPending::0 -203974019508 -52.44% -52.44% # Table walker pending requests distribution
514 system.cpu0.itb.walker.walksPending::1 592976854000 152.44% 100.00% # Table walker pending requests distribution
515 system.cpu0.itb.walker.walksPending::total 389002834492 # Table walker pending requests distribution
516 system.cpu0.itb.walker.walkPageSizes::4K 46188 94.90% 94.90% # Table walker page sizes translated
517 system.cpu0.itb.walker.walkPageSizes::2M 2484 5.10% 100.00% # Table walker page sizes translated
518 system.cpu0.itb.walker.walkPageSizes::total 48672 # Table walker page sizes translated
519 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
520 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53226 # Table walker requests started/completed, data/inst
521 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53226 # Table walker requests started/completed, data/inst
522 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
523 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48672 # Table walker requests started/completed, data/inst
524 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48672 # Table walker requests started/completed, data/inst
525 system.cpu0.itb.walker.walkRequestOrigin::total 101898 # Table walker requests started/completed, data/inst
526 system.cpu0.itb.inst_hits 346140401 # ITB inst hits
527 system.cpu0.itb.inst_misses 53226 # ITB inst misses
528 system.cpu0.itb.read_hits 0 # DTB read hits
529 system.cpu0.itb.read_misses 0 # DTB read misses
530 system.cpu0.itb.write_hits 0 # DTB write hits
531 system.cpu0.itb.write_misses 0 # DTB write misses
532 system.cpu0.itb.flush_tlb 1195 # Number of times complete TLB was flushed
533 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
534 system.cpu0.itb.flush_tlb_mva_asid 16177 # Number of times TLB was flushed by MVA & ASID
535 system.cpu0.itb.flush_tlb_asid 384 # Number of times TLB was flushed by ASID
536 system.cpu0.itb.flush_entries 28414 # Number of entries that have been flushed from TLB
537 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
538 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
539 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
540 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
541 system.cpu0.itb.read_accesses 0 # DTB read accesses
542 system.cpu0.itb.write_accesses 0 # DTB write accesses
543 system.cpu0.itb.inst_accesses 346193627 # ITB inst accesses
544 system.cpu0.itb.hits 346140401 # DTB hits
545 system.cpu0.itb.misses 53226 # DTB misses
546 system.cpu0.itb.accesses 346193627 # DTB accesses
547 system.cpu0.numCycles 417471005 # number of cpu cycles simulated
548 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
549 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
550 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
551 system.cpu0.kern.inst.quiesce 16511 # number of quiesce instructions executed
552 system.cpu0.committedInsts 345998217 # Number of instructions committed
553 system.cpu0.committedOps 406905705 # Number of ops (including micro ops) committed
554 system.cpu0.num_int_alu_accesses 373867604 # Number of integer alu accesses
555 system.cpu0.num_fp_alu_accesses 363074 # Number of float alu accesses
556 system.cpu0.num_func_calls 20947482 # number of times a function call or return occured
557 system.cpu0.num_conditional_control_insts 52475381 # number of instructions that are conditional controls
558 system.cpu0.num_int_insts 373867604 # number of integer instructions
559 system.cpu0.num_fp_insts 363074 # number of float instructions
560 system.cpu0.num_int_register_reads 545388282 # number of times the integer registers were read
561 system.cpu0.num_int_register_writes 296679828 # number of times the integer registers were written
562 system.cpu0.num_fp_register_reads 584270 # number of times the floating registers were read
563 system.cpu0.num_fp_register_writes 311304 # number of times the floating registers were written
564 system.cpu0.num_cc_register_reads 89963697 # number of times the CC registers were read
565 system.cpu0.num_cc_register_writes 89731719 # number of times the CC registers were written
566 system.cpu0.num_mem_refs 124026394 # number of memory refs
567 system.cpu0.num_load_insts 64916857 # Number of load instructions
568 system.cpu0.num_store_insts 59109537 # Number of store instructions
569 system.cpu0.num_idle_cycles 408121506.428325 # Number of idle cycles
570 system.cpu0.num_busy_cycles 9349498.571675 # Number of busy cycles
571 system.cpu0.not_idle_fraction 0.022396 # Percentage of non-idle cycles
572 system.cpu0.idle_fraction 0.977604 # Percentage of idle cycles
573 system.cpu0.Branches 77230042 # Number of branches fetched
574 system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
575 system.cpu0.op_class::IntAlu 282115014 69.29% 69.29% # Class of executed instruction
576 system.cpu0.op_class::IntMult 908017 0.22% 69.51% # Class of executed instruction
577 system.cpu0.op_class::IntDiv 41532 0.01% 69.53% # Class of executed instruction
578 system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction
579 system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction
580 system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction
581 system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction
582 system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction
583 system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction
584 system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction
585 system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction
586 system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction
587 system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction
588 system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction
589 system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction
590 system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction
591 system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction
592 system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction
593 system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction
594 system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction
595 system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction
596 system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction
597 system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction
598 system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction
599 system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction
600 system.cpu0.op_class::SimdFloatMisc 48729 0.01% 69.54% # Class of executed instruction
601 system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction
602 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction
603 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction
604 system.cpu0.op_class::MemRead 64916857 15.94% 85.48% # Class of executed instruction
605 system.cpu0.op_class::MemWrite 59109537 14.52% 100.00% # Class of executed instruction
606 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
607 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
608 system.cpu0.op_class::total 407139686 # Class of executed instruction
609 system.cpu0.dcache.tags.replacements 9649816 # number of replacements
610 system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use
611 system.cpu0.dcache.tags.total_refs 292739937 # Total number of references to valid blocks.
612 system.cpu0.dcache.tags.sampled_refs 9650328 # Sample count of references to valid blocks.
613 system.cpu0.dcache.tags.avg_refs 30.334714 # Average number of references to valid blocks.
614 system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
615 system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.097568 # Average occupied blocks per requestor
616 system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.975954 # Average occupied blocks per requestor
617 system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.503732 # Average occupied blocks per requestor
618 system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.422464 # Average occupied blocks per requestor
619 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972847 # Average percentage of cache occupancy
620 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009719 # Average percentage of cache occupancy
621 system.cpu0.dcache.tags.occ_percent::cpu2.data 0.008796 # Average percentage of cache occupancy
622 system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008638 # Average percentage of cache occupancy
623 system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
624 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
625 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
626 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
627 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
628 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
629 system.cpu0.dcache.tags.tag_accesses 1240452518 # Number of tag accesses
630 system.cpu0.dcache.tags.data_accesses 1240452518 # Number of data accesses
631 system.cpu0.dcache.ReadReq_hits::cpu0.data 60697634 # number of ReadReq hits
632 system.cpu0.dcache.ReadReq_hits::cpu1.data 18777257 # number of ReadReq hits
633 system.cpu0.dcache.ReadReq_hits::cpu2.data 26142693 # number of ReadReq hits
634 system.cpu0.dcache.ReadReq_hits::cpu3.data 44948482 # number of ReadReq hits
635 system.cpu0.dcache.ReadReq_hits::total 150566066 # number of ReadReq hits
636 system.cpu0.dcache.WriteReq_hits::cpu0.data 55906928 # number of WriteReq hits
637 system.cpu0.dcache.WriteReq_hits::cpu1.data 17271712 # number of WriteReq hits
638 system.cpu0.dcache.WriteReq_hits::cpu2.data 23345865 # number of WriteReq hits
639 system.cpu0.dcache.WriteReq_hits::cpu3.data 37782358 # number of WriteReq hits
640 system.cpu0.dcache.WriteReq_hits::total 134306863 # number of WriteReq hits
641 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159073 # number of SoftPFReq hits
642 system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47007 # number of SoftPFReq hits
643 system.cpu0.dcache.SoftPFReq_hits::cpu2.data 77709 # number of SoftPFReq hits
644 system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113008 # number of SoftPFReq hits
645 system.cpu0.dcache.SoftPFReq_hits::total 396797 # number of SoftPFReq hits
646 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 126017 # number of WriteLineReq hits
647 system.cpu0.dcache.WriteLineReq_hits::cpu1.data 45823 # number of WriteLineReq hits
648 system.cpu0.dcache.WriteLineReq_hits::cpu2.data 59716 # number of WriteLineReq hits
649 system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97286 # number of WriteLineReq hits
650 system.cpu0.dcache.WriteLineReq_hits::total 328842 # number of WriteLineReq hits
651 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1444166 # number of LoadLockedReq hits
652 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 434424 # number of LoadLockedReq hits
653 system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 579867 # number of LoadLockedReq hits
654 system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933968 # number of LoadLockedReq hits
655 system.cpu0.dcache.LoadLockedReq_hits::total 3392425 # number of LoadLockedReq hits
656 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1534667 # number of StoreCondReq hits
657 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 472976 # number of StoreCondReq hits
658 system.cpu0.dcache.StoreCondReq_hits::cpu2.data 630117 # number of StoreCondReq hits
659 system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1067463 # number of StoreCondReq hits
660 system.cpu0.dcache.StoreCondReq_hits::total 3705223 # number of StoreCondReq hits
661 system.cpu0.dcache.demand_hits::cpu0.data 116604562 # number of demand (read+write) hits
662 system.cpu0.dcache.demand_hits::cpu1.data 36048969 # number of demand (read+write) hits
663 system.cpu0.dcache.demand_hits::cpu2.data 49488558 # number of demand (read+write) hits
664 system.cpu0.dcache.demand_hits::cpu3.data 82730840 # number of demand (read+write) hits
665 system.cpu0.dcache.demand_hits::total 284872929 # number of demand (read+write) hits
666 system.cpu0.dcache.overall_hits::cpu0.data 116763635 # number of overall hits
667 system.cpu0.dcache.overall_hits::cpu1.data 36095976 # number of overall hits
668 system.cpu0.dcache.overall_hits::cpu2.data 49566267 # number of overall hits
669 system.cpu0.dcache.overall_hits::cpu3.data 82843848 # number of overall hits
670 system.cpu0.dcache.overall_hits::total 285269726 # number of overall hits
671 system.cpu0.dcache.ReadReq_misses::cpu0.data 2054873 # number of ReadReq misses
672 system.cpu0.dcache.ReadReq_misses::cpu1.data 645438 # number of ReadReq misses
673 system.cpu0.dcache.ReadReq_misses::cpu2.data 971207 # number of ReadReq misses
674 system.cpu0.dcache.ReadReq_misses::cpu3.data 3440752 # number of ReadReq misses
675 system.cpu0.dcache.ReadReq_misses::total 7112270 # number of ReadReq misses
676 system.cpu0.dcache.WriteReq_misses::cpu0.data 839053 # number of WriteReq misses
677 system.cpu0.dcache.WriteReq_misses::cpu1.data 258864 # number of WriteReq misses
678 system.cpu0.dcache.WriteReq_misses::cpu2.data 597119 # number of WriteReq misses
679 system.cpu0.dcache.WriteReq_misses::cpu3.data 3449762 # number of WriteReq misses
680 system.cpu0.dcache.WriteReq_misses::total 5144798 # number of WriteReq misses
681 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 459594 # number of SoftPFReq misses
682 system.cpu0.dcache.SoftPFReq_misses::cpu1.data 152322 # number of SoftPFReq misses
683 system.cpu0.dcache.SoftPFReq_misses::cpu2.data 206104 # number of SoftPFReq misses
684 system.cpu0.dcache.SoftPFReq_misses::cpu3.data 350750 # number of SoftPFReq misses
685 system.cpu0.dcache.SoftPFReq_misses::total 1168770 # number of SoftPFReq misses
686 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 686647 # number of WriteLineReq misses
687 system.cpu0.dcache.WriteLineReq_misses::cpu1.data 108408 # number of WriteLineReq misses
688 system.cpu0.dcache.WriteLineReq_misses::cpu2.data 151049 # number of WriteLineReq misses
689 system.cpu0.dcache.WriteLineReq_misses::cpu3.data 279871 # number of WriteLineReq misses
690 system.cpu0.dcache.WriteLineReq_misses::total 1225975 # number of WriteLineReq misses
691 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91254 # number of LoadLockedReq misses
692 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38759 # number of LoadLockedReq misses
693 system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 50526 # number of LoadLockedReq misses
694 system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 171973 # number of LoadLockedReq misses
695 system.cpu0.dcache.LoadLockedReq_misses::total 352512 # number of LoadLockedReq misses
696 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
697 system.cpu0.dcache.StoreCondReq_misses::cpu3.data 1 # number of StoreCondReq misses
698 system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
699 system.cpu0.dcache.demand_misses::cpu0.data 2893926 # number of demand (read+write) misses
700 system.cpu0.dcache.demand_misses::cpu1.data 904302 # number of demand (read+write) misses
701 system.cpu0.dcache.demand_misses::cpu2.data 1568326 # number of demand (read+write) misses
702 system.cpu0.dcache.demand_misses::cpu3.data 6890514 # number of demand (read+write) misses
703 system.cpu0.dcache.demand_misses::total 12257068 # number of demand (read+write) misses
704 system.cpu0.dcache.overall_misses::cpu0.data 3353520 # number of overall misses
705 system.cpu0.dcache.overall_misses::cpu1.data 1056624 # number of overall misses
706 system.cpu0.dcache.overall_misses::cpu2.data 1774430 # number of overall misses
707 system.cpu0.dcache.overall_misses::cpu3.data 7241264 # number of overall misses
708 system.cpu0.dcache.overall_misses::total 13425838 # number of overall misses
709 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10693475500 # number of ReadReq miss cycles
710 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 16789198500 # number of ReadReq miss cycles
711 system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 60054572500 # number of ReadReq miss cycles
712 system.cpu0.dcache.ReadReq_miss_latency::total 87537246500 # number of ReadReq miss cycles
713 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9893449500 # number of WriteReq miss cycles
714 system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22002273500 # number of WriteReq miss cycles
715 system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 116544874640 # number of WriteReq miss cycles
716 system.cpu0.dcache.WriteReq_miss_latency::total 148440597640 # number of WriteReq miss cycles
717 system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3721833000 # number of WriteLineReq miss cycles
718 system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 5259250500 # number of WriteLineReq miss cycles
719 system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 11075466859 # number of WriteLineReq miss cycles
720 system.cpu0.dcache.WriteLineReq_miss_latency::total 20056550359 # number of WriteLineReq miss cycles
721 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 550414500 # number of LoadLockedReq miss cycles
722 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 751937500 # number of LoadLockedReq miss cycles
723 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2294222000 # number of LoadLockedReq miss cycles
724 system.cpu0.dcache.LoadLockedReq_miss_latency::total 3596574000 # number of LoadLockedReq miss cycles
725 system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 82000 # number of StoreCondReq miss cycles
726 system.cpu0.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
727 system.cpu0.dcache.demand_miss_latency::cpu1.data 20586925000 # number of demand (read+write) miss cycles
728 system.cpu0.dcache.demand_miss_latency::cpu2.data 38791472000 # number of demand (read+write) miss cycles
729 system.cpu0.dcache.demand_miss_latency::cpu3.data 176599447140 # number of demand (read+write) miss cycles
730 system.cpu0.dcache.demand_miss_latency::total 235977844140 # number of demand (read+write) miss cycles
731 system.cpu0.dcache.overall_miss_latency::cpu1.data 20586925000 # number of overall miss cycles
732 system.cpu0.dcache.overall_miss_latency::cpu2.data 38791472000 # number of overall miss cycles
733 system.cpu0.dcache.overall_miss_latency::cpu3.data 176599447140 # number of overall miss cycles
734 system.cpu0.dcache.overall_miss_latency::total 235977844140 # number of overall miss cycles
735 system.cpu0.dcache.ReadReq_accesses::cpu0.data 62752507 # number of ReadReq accesses(hits+misses)
736 system.cpu0.dcache.ReadReq_accesses::cpu1.data 19422695 # number of ReadReq accesses(hits+misses)
737 system.cpu0.dcache.ReadReq_accesses::cpu2.data 27113900 # number of ReadReq accesses(hits+misses)
738 system.cpu0.dcache.ReadReq_accesses::cpu3.data 48389234 # number of ReadReq accesses(hits+misses)
739 system.cpu0.dcache.ReadReq_accesses::total 157678336 # number of ReadReq accesses(hits+misses)
740 system.cpu0.dcache.WriteReq_accesses::cpu0.data 56745981 # number of WriteReq accesses(hits+misses)
741 system.cpu0.dcache.WriteReq_accesses::cpu1.data 17530576 # number of WriteReq accesses(hits+misses)
742 system.cpu0.dcache.WriteReq_accesses::cpu2.data 23942984 # number of WriteReq accesses(hits+misses)
743 system.cpu0.dcache.WriteReq_accesses::cpu3.data 41232120 # number of WriteReq accesses(hits+misses)
744 system.cpu0.dcache.WriteReq_accesses::total 139451661 # number of WriteReq accesses(hits+misses)
745 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 618667 # number of SoftPFReq accesses(hits+misses)
746 system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 199329 # number of SoftPFReq accesses(hits+misses)
747 system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 283813 # number of SoftPFReq accesses(hits+misses)
748 system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 463758 # number of SoftPFReq accesses(hits+misses)
749 system.cpu0.dcache.SoftPFReq_accesses::total 1565567 # number of SoftPFReq accesses(hits+misses)
750 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 812664 # number of WriteLineReq accesses(hits+misses)
751 system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 154231 # number of WriteLineReq accesses(hits+misses)
752 system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 210765 # number of WriteLineReq accesses(hits+misses)
753 system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 377157 # number of WriteLineReq accesses(hits+misses)
754 system.cpu0.dcache.WriteLineReq_accesses::total 1554817 # number of WriteLineReq accesses(hits+misses)
755 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1535420 # number of LoadLockedReq accesses(hits+misses)
756 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 473183 # number of LoadLockedReq accesses(hits+misses)
757 system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 630393 # number of LoadLockedReq accesses(hits+misses)
758 system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1105941 # number of LoadLockedReq accesses(hits+misses)
759 system.cpu0.dcache.LoadLockedReq_accesses::total 3744937 # number of LoadLockedReq accesses(hits+misses)
760 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1534668 # number of StoreCondReq accesses(hits+misses)
761 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 472976 # number of StoreCondReq accesses(hits+misses)
762 system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 630117 # number of StoreCondReq accesses(hits+misses)
763 system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1067464 # number of StoreCondReq accesses(hits+misses)
764 system.cpu0.dcache.StoreCondReq_accesses::total 3705225 # number of StoreCondReq accesses(hits+misses)
765 system.cpu0.dcache.demand_accesses::cpu0.data 119498488 # number of demand (read+write) accesses
766 system.cpu0.dcache.demand_accesses::cpu1.data 36953271 # number of demand (read+write) accesses
767 system.cpu0.dcache.demand_accesses::cpu2.data 51056884 # number of demand (read+write) accesses
768 system.cpu0.dcache.demand_accesses::cpu3.data 89621354 # number of demand (read+write) accesses
769 system.cpu0.dcache.demand_accesses::total 297129997 # number of demand (read+write) accesses
770 system.cpu0.dcache.overall_accesses::cpu0.data 120117155 # number of overall (read+write) accesses
771 system.cpu0.dcache.overall_accesses::cpu1.data 37152600 # number of overall (read+write) accesses
772 system.cpu0.dcache.overall_accesses::cpu2.data 51340697 # number of overall (read+write) accesses
773 system.cpu0.dcache.overall_accesses::cpu3.data 90085112 # number of overall (read+write) accesses
774 system.cpu0.dcache.overall_accesses::total 298695564 # number of overall (read+write) accesses
775 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032746 # miss rate for ReadReq accesses
776 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033231 # miss rate for ReadReq accesses
777 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035820 # miss rate for ReadReq accesses
778 system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071106 # miss rate for ReadReq accesses
779 system.cpu0.dcache.ReadReq_miss_rate::total 0.045106 # miss rate for ReadReq accesses
780 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014786 # miss rate for WriteReq accesses
781 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014766 # miss rate for WriteReq accesses
782 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.024939 # miss rate for WriteReq accesses
783 system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.083667 # miss rate for WriteReq accesses
784 system.cpu0.dcache.WriteReq_miss_rate::total 0.036893 # miss rate for WriteReq accesses
785 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.742878 # miss rate for SoftPFReq accesses
786 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.764174 # miss rate for SoftPFReq accesses
787 system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.726196 # miss rate for SoftPFReq accesses
788 system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.756321 # miss rate for SoftPFReq accesses
789 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.746547 # miss rate for SoftPFReq accesses
790 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.844933 # miss rate for WriteLineReq accesses
791 system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.702894 # miss rate for WriteLineReq accesses
792 system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.716670 # miss rate for WriteLineReq accesses
793 system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.742054 # miss rate for WriteLineReq accesses
794 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788501 # miss rate for WriteLineReq accesses
795 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059433 # miss rate for LoadLockedReq accesses
796 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081911 # miss rate for LoadLockedReq accesses
797 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.080150 # miss rate for LoadLockedReq accesses
798 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.155499 # miss rate for LoadLockedReq accesses
799 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094130 # miss rate for LoadLockedReq accesses
800 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
801 system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000001 # miss rate for StoreCondReq accesses
802 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
803 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024217 # miss rate for demand accesses
804 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024472 # miss rate for demand accesses
805 system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030717 # miss rate for demand accesses
806 system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076885 # miss rate for demand accesses
807 system.cpu0.dcache.demand_miss_rate::total 0.041252 # miss rate for demand accesses
808 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027919 # miss rate for overall accesses
809 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028440 # miss rate for overall accesses
810 system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034562 # miss rate for overall accesses
811 system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080382 # miss rate for overall accesses
812 system.cpu0.dcache.overall_miss_rate::total 0.044948 # miss rate for overall accesses
813 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16567.781104 # average ReadReq miss latency
814 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17286.941404 # average ReadReq miss latency
815 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17453.909058 # average ReadReq miss latency
816 system.cpu0.dcache.ReadReq_avg_miss_latency::total 12307.919483 # average ReadReq miss latency
817 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38218.715233 # average WriteReq miss latency
818 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36847.384692 # average WriteReq miss latency
819 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33783.453653 # average WriteReq miss latency
820 system.cpu0.dcache.WriteReq_avg_miss_latency::total 28852.560905 # average WriteReq miss latency
821 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34331.719061 # average WriteLineReq miss latency
822 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34818.174897 # average WriteLineReq miss latency
823 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39573.470845 # average WriteLineReq miss latency
824 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16359.673206 # average WriteLineReq miss latency
825 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14200.946877 # average LoadLockedReq miss latency
826 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14882.189368 # average LoadLockedReq miss latency
827 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13340.594163 # average LoadLockedReq miss latency
828 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10202.699483 # average LoadLockedReq miss latency
829 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 82000 # average StoreCondReq miss latency
830 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 41000 # average StoreCondReq miss latency
831 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22765.541821 # average overall miss latency
832 system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24734.316717 # average overall miss latency
833 system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25629.357569 # average overall miss latency
834 system.cpu0.dcache.demand_avg_miss_latency::total 19252.389245 # average overall miss latency
835 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19483.681045 # average overall miss latency
836 system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21861.370694 # average overall miss latency
837 system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24387.931049 # average overall miss latency
838 system.cpu0.dcache.overall_avg_miss_latency::total 17576.395912 # average overall miss latency
839 system.cpu0.dcache.blocked_cycles::no_mshrs 14582944 # number of cycles access was blocked
840 system.cpu0.dcache.blocked_cycles::no_targets 41803 # number of cycles access was blocked
841 system.cpu0.dcache.blocked::no_mshrs 883633 # number of cycles access was blocked
842 system.cpu0.dcache.blocked::no_targets 391 # number of cycles access was blocked
843 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.503395 # average number of cycles each access was blocked
844 system.cpu0.dcache.avg_blocked_cycles::no_targets 106.913043 # average number of cycles each access was blocked
845 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
846 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
847 system.cpu0.dcache.writebacks::writebacks 7469710 # number of writebacks
848 system.cpu0.dcache.writebacks::total 7469710 # number of writebacks
849 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3285 # number of ReadReq MSHR hits
850 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 124429 # number of ReadReq MSHR hits
851 system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1909922 # number of ReadReq MSHR hits
852 system.cpu0.dcache.ReadReq_mshr_hits::total 2037636 # number of ReadReq MSHR hits
853 system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4905 # number of WriteReq MSHR hits
854 system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 264011 # number of WriteReq MSHR hits
855 system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2867438 # number of WriteReq MSHR hits
856 system.cpu0.dcache.WriteReq_mshr_hits::total 3136354 # number of WriteReq MSHR hits
857 system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 23 # number of WriteLineReq MSHR hits
858 system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2121 # number of WriteLineReq MSHR hits
859 system.cpu0.dcache.WriteLineReq_mshr_hits::total 2144 # number of WriteLineReq MSHR hits
860 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8176 # number of LoadLockedReq MSHR hits
861 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10487 # number of LoadLockedReq MSHR hits
862 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 105681 # number of LoadLockedReq MSHR hits
863 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 124344 # number of LoadLockedReq MSHR hits
864 system.cpu0.dcache.demand_mshr_hits::cpu1.data 8190 # number of demand (read+write) MSHR hits
865 system.cpu0.dcache.demand_mshr_hits::cpu2.data 388440 # number of demand (read+write) MSHR hits
866 system.cpu0.dcache.demand_mshr_hits::cpu3.data 4777360 # number of demand (read+write) MSHR hits
867 system.cpu0.dcache.demand_mshr_hits::total 5173990 # number of demand (read+write) MSHR hits
868 system.cpu0.dcache.overall_mshr_hits::cpu1.data 8190 # number of overall MSHR hits
869 system.cpu0.dcache.overall_mshr_hits::cpu2.data 388440 # number of overall MSHR hits
870 system.cpu0.dcache.overall_mshr_hits::cpu3.data 4777360 # number of overall MSHR hits
871 system.cpu0.dcache.overall_mshr_hits::total 5173990 # number of overall MSHR hits
872 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 642153 # number of ReadReq MSHR misses
873 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 846778 # number of ReadReq MSHR misses
874 system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1530830 # number of ReadReq MSHR misses
875 system.cpu0.dcache.ReadReq_mshr_misses::total 3019761 # number of ReadReq MSHR misses
876 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 253959 # number of WriteReq MSHR misses
877 system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 333108 # number of WriteReq MSHR misses
878 system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 582324 # number of WriteReq MSHR misses
879 system.cpu0.dcache.WriteReq_mshr_misses::total 1169391 # number of WriteReq MSHR misses
880 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 151941 # number of SoftPFReq MSHR misses
881 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 203469 # number of SoftPFReq MSHR misses
882 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 343395 # number of SoftPFReq MSHR misses
883 system.cpu0.dcache.SoftPFReq_mshr_misses::total 698805 # number of SoftPFReq MSHR misses
884 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 108408 # number of WriteLineReq MSHR misses
885 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 151026 # number of WriteLineReq MSHR misses
886 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 277750 # number of WriteLineReq MSHR misses
887 system.cpu0.dcache.WriteLineReq_mshr_misses::total 537184 # number of WriteLineReq MSHR misses
888 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30583 # number of LoadLockedReq MSHR misses
889 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 40039 # number of LoadLockedReq MSHR misses
890 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 66292 # number of LoadLockedReq MSHR misses
891 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136914 # number of LoadLockedReq MSHR misses
892 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 1 # number of StoreCondReq MSHR misses
893 system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
894 system.cpu0.dcache.demand_mshr_misses::cpu1.data 896112 # number of demand (read+write) MSHR misses
895 system.cpu0.dcache.demand_mshr_misses::cpu2.data 1179886 # number of demand (read+write) MSHR misses
896 system.cpu0.dcache.demand_mshr_misses::cpu3.data 2113154 # number of demand (read+write) MSHR misses
897 system.cpu0.dcache.demand_mshr_misses::total 4189152 # number of demand (read+write) MSHR misses
898 system.cpu0.dcache.overall_mshr_misses::cpu1.data 1048053 # number of overall MSHR misses
899 system.cpu0.dcache.overall_mshr_misses::cpu2.data 1383355 # number of overall MSHR misses
900 system.cpu0.dcache.overall_mshr_misses::cpu3.data 2456549 # number of overall MSHR misses
901 system.cpu0.dcache.overall_mshr_misses::total 4887957 # number of overall MSHR misses
902 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6903 # number of ReadReq MSHR uncacheable
903 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6938 # number of ReadReq MSHR uncacheable
904 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7170 # number of ReadReq MSHR uncacheable
905 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21011 # number of ReadReq MSHR uncacheable
906 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 6403 # number of WriteReq MSHR uncacheable
907 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6456 # number of WriteReq MSHR uncacheable
908 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6887 # number of WriteReq MSHR uncacheable
909 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19746 # number of WriteReq MSHR uncacheable
910 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 13306 # number of overall MSHR uncacheable misses
911 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 13394 # number of overall MSHR uncacheable misses
912 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 14057 # number of overall MSHR uncacheable misses
913 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40757 # number of overall MSHR uncacheable misses
914 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9834011500 # number of ReadReq MSHR miss cycles
915 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13414476000 # number of ReadReq MSHR miss cycles
916 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26248104500 # number of ReadReq MSHR miss cycles
917 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49496592000 # number of ReadReq MSHR miss cycles
918 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9425671500 # number of WriteReq MSHR miss cycles
919 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 11707052500 # number of WriteReq MSHR miss cycles
920 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21288427290 # number of WriteReq MSHR miss cycles
921 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42421151290 # number of WriteReq MSHR miss cycles
922 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3120110500 # number of SoftPFReq MSHR miss cycles
923 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4040690000 # number of SoftPFReq MSHR miss cycles
924 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6773951000 # number of SoftPFReq MSHR miss cycles
925 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13934751500 # number of SoftPFReq MSHR miss cycles
926 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3613425000 # number of WriteLineReq MSHR miss cycles
927 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 5107026000 # number of WriteLineReq MSHR miss cycles
928 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10670616859 # number of WriteLineReq MSHR miss cycles
929 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 19391067859 # number of WriteLineReq MSHR miss cycles
930 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 396226000 # number of LoadLockedReq MSHR miss cycles
931 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 532705500 # number of LoadLockedReq MSHR miss cycles
932 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 945307500 # number of LoadLockedReq MSHR miss cycles
933 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1874239000 # number of LoadLockedReq MSHR miss cycles
934 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 81000 # number of StoreCondReq MSHR miss cycles
935 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
936 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19259683000 # number of demand (read+write) MSHR miss cycles
937 system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25121528500 # number of demand (read+write) MSHR miss cycles
938 system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 47536531790 # number of demand (read+write) MSHR miss cycles
939 system.cpu0.dcache.demand_mshr_miss_latency::total 91917743290 # number of demand (read+write) MSHR miss cycles
940 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22379793500 # number of overall MSHR miss cycles
941 system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29162218500 # number of overall MSHR miss cycles
942 system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 54310482790 # number of overall MSHR miss cycles
943 system.cpu0.dcache.overall_mshr_miss_latency::total 105852494790 # number of overall MSHR miss cycles
944 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1362861000 # number of ReadReq MSHR uncacheable cycles
945 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1366136000 # number of ReadReq MSHR uncacheable cycles
946 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1368520000 # number of ReadReq MSHR uncacheable cycles
947 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4097517000 # number of ReadReq MSHR uncacheable cycles
948 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1303404500 # number of WriteReq MSHR uncacheable cycles
949 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1305231500 # number of WriteReq MSHR uncacheable cycles
950 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1342048955 # number of WriteReq MSHR uncacheable cycles
951 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3950684955 # number of WriteReq MSHR uncacheable cycles
952 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2666265500 # number of overall MSHR uncacheable cycles
953 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2671367500 # number of overall MSHR uncacheable cycles
954 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2710568955 # number of overall MSHR uncacheable cycles
955 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8048201955 # number of overall MSHR uncacheable cycles
956 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033062 # mshr miss rate for ReadReq accesses
957 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031230 # mshr miss rate for ReadReq accesses
958 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031636 # mshr miss rate for ReadReq accesses
959 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019151 # mshr miss rate for ReadReq accesses
960 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014487 # mshr miss rate for WriteReq accesses
961 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013913 # mshr miss rate for WriteReq accesses
962 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014123 # mshr miss rate for WriteReq accesses
963 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008386 # mshr miss rate for WriteReq accesses
964 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762262 # mshr miss rate for SoftPFReq accesses
965 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.716912 # mshr miss rate for SoftPFReq accesses
966 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.740462 # mshr miss rate for SoftPFReq accesses
967 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.446359 # mshr miss rate for SoftPFReq accesses
968 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.702894 # mshr miss rate for WriteLineReq accesses
969 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716561 # mshr miss rate for WriteLineReq accesses
970 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.736431 # mshr miss rate for WriteLineReq accesses
971 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.345497 # mshr miss rate for WriteLineReq accesses
972 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064632 # mshr miss rate for LoadLockedReq accesses
973 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.063514 # mshr miss rate for LoadLockedReq accesses
974 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.059942 # mshr miss rate for LoadLockedReq accesses
975 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036560 # mshr miss rate for LoadLockedReq accesses
976 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000001 # mshr miss rate for StoreCondReq accesses
977 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
978 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024250 # mshr miss rate for demand accesses
979 system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023109 # mshr miss rate for demand accesses
980 system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023579 # mshr miss rate for demand accesses
981 system.cpu0.dcache.demand_mshr_miss_rate::total 0.014099 # mshr miss rate for demand accesses
982 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028209 # mshr miss rate for overall accesses
983 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026945 # mshr miss rate for overall accesses
984 system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027269 # mshr miss rate for overall accesses
985 system.cpu0.dcache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses
986 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15314.125294 # average ReadReq mshr miss latency
987 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15841.786159 # average ReadReq mshr miss latency
988 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17146.322257 # average ReadReq mshr miss latency
989 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16390.897160 # average ReadReq mshr miss latency
990 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37114.933907 # average WriteReq mshr miss latency
991 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35144.915463 # average WriteReq mshr miss latency
992 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36557.702052 # average WriteReq mshr miss latency
993 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36276.276532 # average WriteReq mshr miss latency
994 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20535.013591 # average SoftPFReq mshr miss latency
995 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19858.995719 # average SoftPFReq mshr miss latency
996 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19726.411276 # average SoftPFReq mshr miss latency
997 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19940.829702 # average SoftPFReq mshr miss latency
998 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33331.719061 # average WriteLineReq mshr miss latency
999 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33815.541695 # average WriteLineReq mshr miss latency
1000 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38418.062499 # average WriteLineReq mshr miss latency
1001 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36097.627366 # average WriteLineReq mshr miss latency
1002 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12955.759736 # average LoadLockedReq mshr miss latency
1003 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13304.665451 # average LoadLockedReq mshr miss latency
1004 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.752308 # average LoadLockedReq mshr miss latency
1005 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13689.169844 # average LoadLockedReq mshr miss latency
1006 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 81000 # average StoreCondReq mshr miss latency
1007 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
1008 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21492.495358 # average overall mshr miss latency
1009 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21291.487906 # average overall mshr miss latency
1010 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22495.535957 # average overall mshr miss latency
1011 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21941.849637 # average overall mshr miss latency
1012 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21353.684880 # average overall mshr miss latency
1013 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21080.791626 # average overall mshr miss latency
1014 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22108.446764 # average overall mshr miss latency
1015 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21655.774548 # average overall mshr miss latency
1016 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197430.247718 # average ReadReq mshr uncacheable latency
1017 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196906.313059 # average ReadReq mshr uncacheable latency
1018 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 190867.503487 # average ReadReq mshr uncacheable latency
1019 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195017.705012 # average ReadReq mshr uncacheable latency
1020 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203561.533656 # average WriteReq mshr uncacheable latency
1021 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202173.404585 # average WriteReq mshr uncacheable latency
1022 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 194866.989255 # average WriteReq mshr uncacheable latency
1023 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200075.202826 # average WriteReq mshr uncacheable latency
1024 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200380.692920 # average overall mshr uncacheable latency
1025 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199445.087353 # average overall mshr uncacheable latency
1026 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 192826.986910 # average overall mshr uncacheable latency
1027 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197467.967588 # average overall mshr uncacheable latency
1028 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1029 system.cpu0.icache.tags.replacements 15707105 # number of replacements
1030 system.cpu0.icache.tags.tagsinuse 511.971411 # Cycle average of tags in use
1031 system.cpu0.icache.tags.total_refs 557754178 # Total number of references to valid blocks.
1032 system.cpu0.icache.tags.sampled_refs 15707617 # Sample count of references to valid blocks.
1033 system.cpu0.icache.tags.avg_refs 35.508517 # Average number of references to valid blocks.
1034 system.cpu0.icache.tags.warmup_cycle 11785355500 # Cycle when the warmup percentage was hit.
1035 system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.312770 # Average occupied blocks per requestor
1036 system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.251841 # Average occupied blocks per requestor
1037 system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.846438 # Average occupied blocks per requestor
1038 system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.560362 # Average occupied blocks per requestor
1039 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934205 # Average percentage of cache occupancy
1040 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006351 # Average percentage of cache occupancy
1041 system.cpu0.icache.tags.occ_percent::cpu2.inst 0.046575 # Average percentage of cache occupancy
1042 system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012813 # Average percentage of cache occupancy
1043 system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy
1044 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1045 system.cpu0.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
1046 system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
1047 system.cpu0.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
1048 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1049 system.cpu0.icache.tags.tag_accesses 589528421 # Number of tag accesses
1050 system.cpu0.icache.tags.data_accesses 589528421 # Number of data accesses
1051 system.cpu0.icache.ReadReq_hits::cpu0.inst 340625874 # number of ReadReq hits
1052 system.cpu0.icache.ReadReq_hits::cpu1.inst 105592046 # number of ReadReq hits
1053 system.cpu0.icache.ReadReq_hits::cpu2.inst 63997933 # number of ReadReq hits
1054 system.cpu0.icache.ReadReq_hits::cpu3.inst 47538325 # number of ReadReq hits
1055 system.cpu0.icache.ReadReq_hits::total 557754178 # number of ReadReq hits
1056 system.cpu0.icache.demand_hits::cpu0.inst 340625874 # number of demand (read+write) hits
1057 system.cpu0.icache.demand_hits::cpu1.inst 105592046 # number of demand (read+write) hits
1058 system.cpu0.icache.demand_hits::cpu2.inst 63997933 # number of demand (read+write) hits
1059 system.cpu0.icache.demand_hits::cpu3.inst 47538325 # number of demand (read+write) hits
1060 system.cpu0.icache.demand_hits::total 557754178 # number of demand (read+write) hits
1061 system.cpu0.icache.overall_hits::cpu0.inst 340625874 # number of overall hits
1062 system.cpu0.icache.overall_hits::cpu1.inst 105592046 # number of overall hits
1063 system.cpu0.icache.overall_hits::cpu2.inst 63997933 # number of overall hits
1064 system.cpu0.icache.overall_hits::cpu3.inst 47538325 # number of overall hits
1065 system.cpu0.icache.overall_hits::total 557754178 # number of overall hits
1066 system.cpu0.icache.ReadReq_misses::cpu0.inst 5563199 # number of ReadReq misses
1067 system.cpu0.icache.ReadReq_misses::cpu1.inst 1667816 # number of ReadReq misses
1068 system.cpu0.icache.ReadReq_misses::cpu2.inst 3866259 # number of ReadReq misses
1069 system.cpu0.icache.ReadReq_misses::cpu3.inst 4969275 # number of ReadReq misses
1070 system.cpu0.icache.ReadReq_misses::total 16066549 # number of ReadReq misses
1071 system.cpu0.icache.demand_misses::cpu0.inst 5563199 # number of demand (read+write) misses
1072 system.cpu0.icache.demand_misses::cpu1.inst 1667816 # number of demand (read+write) misses
1073 system.cpu0.icache.demand_misses::cpu2.inst 3866259 # number of demand (read+write) misses
1074 system.cpu0.icache.demand_misses::cpu3.inst 4969275 # number of demand (read+write) misses
1075 system.cpu0.icache.demand_misses::total 16066549 # number of demand (read+write) misses
1076 system.cpu0.icache.overall_misses::cpu0.inst 5563199 # number of overall misses
1077 system.cpu0.icache.overall_misses::cpu1.inst 1667816 # number of overall misses
1078 system.cpu0.icache.overall_misses::cpu2.inst 3866259 # number of overall misses
1079 system.cpu0.icache.overall_misses::cpu3.inst 4969275 # number of overall misses
1080 system.cpu0.icache.overall_misses::total 16066549 # number of overall misses
1081 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22564855500 # number of ReadReq miss cycles
1082 system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53176348000 # number of ReadReq miss cycles
1083 system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 67096069815 # number of ReadReq miss cycles
1084 system.cpu0.icache.ReadReq_miss_latency::total 142837273315 # number of ReadReq miss cycles
1085 system.cpu0.icache.demand_miss_latency::cpu1.inst 22564855500 # number of demand (read+write) miss cycles
1086 system.cpu0.icache.demand_miss_latency::cpu2.inst 53176348000 # number of demand (read+write) miss cycles
1087 system.cpu0.icache.demand_miss_latency::cpu3.inst 67096069815 # number of demand (read+write) miss cycles
1088 system.cpu0.icache.demand_miss_latency::total 142837273315 # number of demand (read+write) miss cycles
1089 system.cpu0.icache.overall_miss_latency::cpu1.inst 22564855500 # number of overall miss cycles
1090 system.cpu0.icache.overall_miss_latency::cpu2.inst 53176348000 # number of overall miss cycles
1091 system.cpu0.icache.overall_miss_latency::cpu3.inst 67096069815 # number of overall miss cycles
1092 system.cpu0.icache.overall_miss_latency::total 142837273315 # number of overall miss cycles
1093 system.cpu0.icache.ReadReq_accesses::cpu0.inst 346189073 # number of ReadReq accesses(hits+misses)
1094 system.cpu0.icache.ReadReq_accesses::cpu1.inst 107259862 # number of ReadReq accesses(hits+misses)
1095 system.cpu0.icache.ReadReq_accesses::cpu2.inst 67864192 # number of ReadReq accesses(hits+misses)
1096 system.cpu0.icache.ReadReq_accesses::cpu3.inst 52507600 # number of ReadReq accesses(hits+misses)
1097 system.cpu0.icache.ReadReq_accesses::total 573820727 # number of ReadReq accesses(hits+misses)
1098 system.cpu0.icache.demand_accesses::cpu0.inst 346189073 # number of demand (read+write) accesses
1099 system.cpu0.icache.demand_accesses::cpu1.inst 107259862 # number of demand (read+write) accesses
1100 system.cpu0.icache.demand_accesses::cpu2.inst 67864192 # number of demand (read+write) accesses
1101 system.cpu0.icache.demand_accesses::cpu3.inst 52507600 # number of demand (read+write) accesses
1102 system.cpu0.icache.demand_accesses::total 573820727 # number of demand (read+write) accesses
1103 system.cpu0.icache.overall_accesses::cpu0.inst 346189073 # number of overall (read+write) accesses
1104 system.cpu0.icache.overall_accesses::cpu1.inst 107259862 # number of overall (read+write) accesses
1105 system.cpu0.icache.overall_accesses::cpu2.inst 67864192 # number of overall (read+write) accesses
1106 system.cpu0.icache.overall_accesses::cpu3.inst 52507600 # number of overall (read+write) accesses
1107 system.cpu0.icache.overall_accesses::total 573820727 # number of overall (read+write) accesses
1108 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016070 # miss rate for ReadReq accesses
1109 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015549 # miss rate for ReadReq accesses
1110 system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056971 # miss rate for ReadReq accesses
1111 system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.094639 # miss rate for ReadReq accesses
1112 system.cpu0.icache.ReadReq_miss_rate::total 0.027999 # miss rate for ReadReq accesses
1113 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016070 # miss rate for demand accesses
1114 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015549 # miss rate for demand accesses
1115 system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056971 # miss rate for demand accesses
1116 system.cpu0.icache.demand_miss_rate::cpu3.inst 0.094639 # miss rate for demand accesses
1117 system.cpu0.icache.demand_miss_rate::total 0.027999 # miss rate for demand accesses
1118 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016070 # miss rate for overall accesses
1119 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015549 # miss rate for overall accesses
1120 system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056971 # miss rate for overall accesses
1121 system.cpu0.icache.overall_miss_rate::cpu3.inst 0.094639 # miss rate for overall accesses
1122 system.cpu0.icache.overall_miss_rate::total 0.027999 # miss rate for overall accesses
1123 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.583299 # average ReadReq miss latency
1124 system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13753.953887 # average ReadReq miss latency
1125 system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13502.184889 # average ReadReq miss latency
1126 system.cpu0.icache.ReadReq_avg_miss_latency::total 8890.351831 # average ReadReq miss latency
1127 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13529.583299 # average overall miss latency
1128 system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13753.953887 # average overall miss latency
1129 system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13502.184889 # average overall miss latency
1130 system.cpu0.icache.demand_avg_miss_latency::total 8890.351831 # average overall miss latency
1131 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13529.583299 # average overall miss latency
1132 system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13753.953887 # average overall miss latency
1133 system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13502.184889 # average overall miss latency
1134 system.cpu0.icache.overall_avg_miss_latency::total 8890.351831 # average overall miss latency
1135 system.cpu0.icache.blocked_cycles::no_mshrs 59004 # number of cycles access was blocked
1136 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1137 system.cpu0.icache.blocked::no_mshrs 3622 # number of cycles access was blocked
1138 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1139 system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.290447 # average number of cycles each access was blocked
1140 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1141 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1142 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1143 system.cpu0.icache.writebacks::writebacks 15707105 # number of writebacks
1144 system.cpu0.icache.writebacks::total 15707105 # number of writebacks
1145 system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358855 # number of ReadReq MSHR hits
1146 system.cpu0.icache.ReadReq_mshr_hits::total 358855 # number of ReadReq MSHR hits
1147 system.cpu0.icache.demand_mshr_hits::cpu3.inst 358855 # number of demand (read+write) MSHR hits
1148 system.cpu0.icache.demand_mshr_hits::total 358855 # number of demand (read+write) MSHR hits
1149 system.cpu0.icache.overall_mshr_hits::cpu3.inst 358855 # number of overall MSHR hits
1150 system.cpu0.icache.overall_mshr_hits::total 358855 # number of overall MSHR hits
1151 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1667816 # number of ReadReq MSHR misses
1152 system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3866259 # number of ReadReq MSHR misses
1153 system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4610420 # number of ReadReq MSHR misses
1154 system.cpu0.icache.ReadReq_mshr_misses::total 10144495 # number of ReadReq MSHR misses
1155 system.cpu0.icache.demand_mshr_misses::cpu1.inst 1667816 # number of demand (read+write) MSHR misses
1156 system.cpu0.icache.demand_mshr_misses::cpu2.inst 3866259 # number of demand (read+write) MSHR misses
1157 system.cpu0.icache.demand_mshr_misses::cpu3.inst 4610420 # number of demand (read+write) MSHR misses
1158 system.cpu0.icache.demand_mshr_misses::total 10144495 # number of demand (read+write) MSHR misses
1159 system.cpu0.icache.overall_mshr_misses::cpu1.inst 1667816 # number of overall MSHR misses
1160 system.cpu0.icache.overall_mshr_misses::cpu2.inst 3866259 # number of overall MSHR misses
1161 system.cpu0.icache.overall_mshr_misses::cpu3.inst 4610420 # number of overall MSHR misses
1162 system.cpu0.icache.overall_mshr_misses::total 10144495 # number of overall MSHR misses
1163 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 20897039500 # number of ReadReq MSHR miss cycles
1164 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49310089000 # number of ReadReq MSHR miss cycles
1165 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 59222114846 # number of ReadReq MSHR miss cycles
1166 system.cpu0.icache.ReadReq_mshr_miss_latency::total 129429243346 # number of ReadReq MSHR miss cycles
1167 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 20897039500 # number of demand (read+write) MSHR miss cycles
1168 system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49310089000 # number of demand (read+write) MSHR miss cycles
1169 system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59222114846 # number of demand (read+write) MSHR miss cycles
1170 system.cpu0.icache.demand_mshr_miss_latency::total 129429243346 # number of demand (read+write) MSHR miss cycles
1171 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 20897039500 # number of overall MSHR miss cycles
1172 system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49310089000 # number of overall MSHR miss cycles
1173 system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59222114846 # number of overall MSHR miss cycles
1174 system.cpu0.icache.overall_mshr_miss_latency::total 129429243346 # number of overall MSHR miss cycles
1175 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for ReadReq accesses
1176 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.056971 # mshr miss rate for ReadReq accesses
1177 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.087805 # mshr miss rate for ReadReq accesses
1178 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017679 # mshr miss rate for ReadReq accesses
1179 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for demand accesses
1180 system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.056971 # mshr miss rate for demand accesses
1181 system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.087805 # mshr miss rate for demand accesses
1182 system.cpu0.icache.demand_mshr_miss_rate::total 0.017679 # mshr miss rate for demand accesses
1183 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for overall accesses
1184 system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.056971 # mshr miss rate for overall accesses
1185 system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.087805 # mshr miss rate for overall accesses
1186 system.cpu0.icache.overall_mshr_miss_rate::total 0.017679 # mshr miss rate for overall accesses
1187 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12529.583299 # average ReadReq mshr miss latency
1188 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12753.953887 # average ReadReq mshr miss latency
1189 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.275451 # average ReadReq mshr miss latency
1190 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12758.569386 # average ReadReq mshr miss latency
1191 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.583299 # average overall mshr miss latency
1192 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12753.953887 # average overall mshr miss latency
1193 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.275451 # average overall mshr miss latency
1194 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12758.569386 # average overall mshr miss latency
1195 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.583299 # average overall mshr miss latency
1196 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12753.953887 # average overall mshr miss latency
1197 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.275451 # average overall mshr miss latency
1198 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12758.569386 # average overall mshr miss latency
1199 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1200 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1201 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1202 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1203 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1204 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1205 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1206 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1207 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1208 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1209 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1210 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1211 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1212 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1213 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1214 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1215 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1216 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1217 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1218 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1219 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1220 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1221 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1222 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1223 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1224 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1225 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1226 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1227 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1228 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1229 system.cpu1.dtb.walker.walks 31889 # Table walker walks requested
1230 system.cpu1.dtb.walker.walksLong 31889 # Table walker walks initiated with long descriptors
1231 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4559 # Level at which table walker walks with long descriptors terminate
1232 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23393 # Level at which table walker walks with long descriptors terminate
1233 system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting
1234 system.cpu1.dtb.walker.walkWaitTime::samples 31883 # Table walker wait (enqueue to first request) latency
1235 system.cpu1.dtb.walker.walkWaitTime::mean 0.878211 # Table walker wait (enqueue to first request) latency
1236 system.cpu1.dtb.walker.walkWaitTime::stdev 156.811692 # Table walker wait (enqueue to first request) latency
1237 system.cpu1.dtb.walker.walkWaitTime::0-2047 31882 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1238 system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1239 system.cpu1.dtb.walker.walkWaitTime::total 31883 # Table walker wait (enqueue to first request) latency
1240 system.cpu1.dtb.walker.walkCompletionTime::samples 27958 # Table walker service (enqueue to completion) latency
1241 system.cpu1.dtb.walker.walkCompletionTime::mean 25168.842550 # Table walker service (enqueue to completion) latency
1242 system.cpu1.dtb.walker.walkCompletionTime::gmean 21742.406424 # Table walker service (enqueue to completion) latency
1243 system.cpu1.dtb.walker.walkCompletionTime::stdev 16076.029843 # Table walker service (enqueue to completion) latency
1244 system.cpu1.dtb.walker.walkCompletionTime::0-32767 18219 65.17% 65.17% # Table walker service (enqueue to completion) latency
1245 system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9556 34.18% 99.35% # Table walker service (enqueue to completion) latency
1246 system.cpu1.dtb.walker.walkCompletionTime::98304-131071 2 0.01% 99.35% # Table walker service (enqueue to completion) latency
1247 system.cpu1.dtb.walker.walkCompletionTime::131072-163839 143 0.51% 99.86% # Table walker service (enqueue to completion) latency
1248 system.cpu1.dtb.walker.walkCompletionTime::163840-196607 15 0.05% 99.92% # Table walker service (enqueue to completion) latency
1249 system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.93% # Table walker service (enqueue to completion) latency
1250 system.cpu1.dtb.walker.walkCompletionTime::262144-294911 12 0.04% 99.97% # Table walker service (enqueue to completion) latency
1251 system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
1252 system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
1253 system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
1254 system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1255 system.cpu1.dtb.walker.walkCompletionTime::total 27958 # Table walker service (enqueue to completion) latency
1256 system.cpu1.dtb.walker.walksPending::samples -1140126012 # Table walker pending requests distribution
1257 system.cpu1.dtb.walker.walksPending::mean 1.890541 # Table walker pending requests distribution
1258 system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
1259 system.cpu1.dtb.walker.walksPending::0 1015329500 -89.05% -89.05% # Table walker pending requests distribution
1260 system.cpu1.dtb.walker.walksPending::1 -2155455512 189.05% 100.00% # Table walker pending requests distribution
1261 system.cpu1.dtb.walker.walksPending::total -1140126012 # Table walker pending requests distribution
1262 system.cpu1.dtb.walker.walkPageSizes::4K 23393 83.69% 83.69% # Table walker page sizes translated
1263 system.cpu1.dtb.walker.walkPageSizes::2M 4559 16.31% 100.00% # Table walker page sizes translated
1264 system.cpu1.dtb.walker.walkPageSizes::total 27952 # Table walker page sizes translated
1265 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31889 # Table walker requests started/completed, data/inst
1266 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1267 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31889 # Table walker requests started/completed, data/inst
1268 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27952 # Table walker requests started/completed, data/inst
1269 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1270 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27952 # Table walker requests started/completed, data/inst
1271 system.cpu1.dtb.walker.walkRequestOrigin::total 59841 # Table walker requests started/completed, data/inst
1272 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1273 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1274 system.cpu1.dtb.read_hits 20102110 # DTB read hits
1275 system.cpu1.dtb.read_misses 24529 # DTB read misses
1276 system.cpu1.dtb.write_hits 18166884 # DTB write hits
1277 system.cpu1.dtb.write_misses 7360 # DTB write misses
1278 system.cpu1.dtb.flush_tlb 1186 # Number of times complete TLB was flushed
1279 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1280 system.cpu1.dtb.flush_tlb_mva_asid 5389 # Number of times TLB was flushed by MVA & ASID
1281 system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID
1282 system.cpu1.dtb.flush_entries 18327 # Number of entries that have been flushed from TLB
1283 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1284 system.cpu1.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch
1285 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1286 system.cpu1.dtb.perms_faults 2685 # Number of TLB faults due to permissions restrictions
1287 system.cpu1.dtb.read_accesses 20126639 # DTB read accesses
1288 system.cpu1.dtb.write_accesses 18174244 # DTB write accesses
1289 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1290 system.cpu1.dtb.hits 38268994 # DTB hits
1291 system.cpu1.dtb.misses 31889 # DTB misses
1292 system.cpu1.dtb.accesses 38300883 # DTB accesses
1293 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1294 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1295 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1296 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1297 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1298 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1299 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1300 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1301 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1302 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1303 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1304 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1305 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1306 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1307 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1308 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1309 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1310 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1311 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1312 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1313 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1314 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1315 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1316 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1317 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1318 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1319 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1320 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1321 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1322 system.cpu1.itb.walker.walks 20281 # Table walker walks requested
1323 system.cpu1.itb.walker.walksLong 20281 # Table walker walks initiated with long descriptors
1324 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 944 # Level at which table walker walks with long descriptors terminate
1325 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17917 # Level at which table walker walks with long descriptors terminate
1326 system.cpu1.itb.walker.walkWaitTime::samples 20281 # Table walker wait (enqueue to first request) latency
1327 system.cpu1.itb.walker.walkWaitTime::0 20281 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1328 system.cpu1.itb.walker.walkWaitTime::total 20281 # Table walker wait (enqueue to first request) latency
1329 system.cpu1.itb.walker.walkCompletionTime::samples 18861 # Table walker service (enqueue to completion) latency
1330 system.cpu1.itb.walker.walkCompletionTime::mean 28459.466624 # Table walker service (enqueue to completion) latency
1331 system.cpu1.itb.walker.walkCompletionTime::gmean 25212.666818 # Table walker service (enqueue to completion) latency
1332 system.cpu1.itb.walker.walkCompletionTime::stdev 18596.263354 # Table walker service (enqueue to completion) latency
1333 system.cpu1.itb.walker.walkCompletionTime::0-65535 18677 99.02% 99.02% # Table walker service (enqueue to completion) latency
1334 system.cpu1.itb.walker.walkCompletionTime::131072-196607 158 0.84% 99.86% # Table walker service (enqueue to completion) latency
1335 system.cpu1.itb.walker.walkCompletionTime::196608-262143 7 0.04% 99.90% # Table walker service (enqueue to completion) latency
1336 system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.05% 99.95% # Table walker service (enqueue to completion) latency
1337 system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.03% 99.98% # Table walker service (enqueue to completion) latency
1338 system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
1339 system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
1340 system.cpu1.itb.walker.walkCompletionTime::total 18861 # Table walker service (enqueue to completion) latency
1341 system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
1342 system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
1343 system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
1344 system.cpu1.itb.walker.walkPageSizes::4K 17917 94.99% 94.99% # Table walker page sizes translated
1345 system.cpu1.itb.walker.walkPageSizes::2M 944 5.01% 100.00% # Table walker page sizes translated
1346 system.cpu1.itb.walker.walkPageSizes::total 18861 # Table walker page sizes translated
1347 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1348 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20281 # Table walker requests started/completed, data/inst
1349 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20281 # Table walker requests started/completed, data/inst
1350 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1351 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18861 # Table walker requests started/completed, data/inst
1352 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18861 # Table walker requests started/completed, data/inst
1353 system.cpu1.itb.walker.walkRequestOrigin::total 39142 # Table walker requests started/completed, data/inst
1354 system.cpu1.itb.inst_hits 107259862 # ITB inst hits
1355 system.cpu1.itb.inst_misses 20281 # ITB inst misses
1356 system.cpu1.itb.read_hits 0 # DTB read hits
1357 system.cpu1.itb.read_misses 0 # DTB read misses
1358 system.cpu1.itb.write_hits 0 # DTB write hits
1359 system.cpu1.itb.write_misses 0 # DTB write misses
1360 system.cpu1.itb.flush_tlb 1186 # Number of times complete TLB was flushed
1361 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1362 system.cpu1.itb.flush_tlb_mva_asid 5389 # Number of times TLB was flushed by MVA & ASID
1363 system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID
1364 system.cpu1.itb.flush_entries 13712 # Number of entries that have been flushed from TLB
1365 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1366 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1367 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1368 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1369 system.cpu1.itb.read_accesses 0 # DTB read accesses
1370 system.cpu1.itb.write_accesses 0 # DTB write accesses
1371 system.cpu1.itb.inst_accesses 107280143 # ITB inst accesses
1372 system.cpu1.itb.hits 107259862 # DTB hits
1373 system.cpu1.itb.misses 20281 # DTB misses
1374 system.cpu1.itb.accesses 107280143 # DTB accesses
1375 system.cpu1.numCycles 1186091604 # number of cpu cycles simulated
1376 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1377 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1378 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1379 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1380 system.cpu1.committedInsts 107180280 # Number of instructions committed
1381 system.cpu1.committedOps 125798339 # Number of ops (including micro ops) committed
1382 system.cpu1.num_int_alu_accesses 115609456 # Number of integer alu accesses
1383 system.cpu1.num_fp_alu_accesses 108829 # Number of float alu accesses
1384 system.cpu1.num_func_calls 6343191 # number of times a function call or return occured
1385 system.cpu1.num_conditional_control_insts 16252887 # number of instructions that are conditional controls
1386 system.cpu1.num_int_insts 115609456 # number of integer instructions
1387 system.cpu1.num_fp_insts 108829 # number of float instructions
1388 system.cpu1.num_int_register_reads 167399256 # number of times the integer registers were read
1389 system.cpu1.num_int_register_writes 91770929 # number of times the integer registers were written
1390 system.cpu1.num_fp_register_reads 176307 # number of times the floating registers were read
1391 system.cpu1.num_fp_register_writes 89468 # number of times the floating registers were written
1392 system.cpu1.num_cc_register_reads 27813306 # number of times the CC registers were read
1393 system.cpu1.num_cc_register_writes 27752983 # number of times the CC registers were written
1394 system.cpu1.num_mem_refs 38266694 # number of memory refs
1395 system.cpu1.num_load_insts 20101554 # Number of load instructions
1396 system.cpu1.num_store_insts 18165140 # Number of store instructions
1397 system.cpu1.num_idle_cycles 1160685667.067715 # Number of idle cycles
1398 system.cpu1.num_busy_cycles 25405936.932285 # Number of busy cycles
1399 system.cpu1.not_idle_fraction 0.021420 # Percentage of non-idle cycles
1400 system.cpu1.idle_fraction 0.978580 # Percentage of idle cycles
1401 system.cpu1.Branches 23816903 # Number of branches fetched
1402 system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
1403 system.cpu1.op_class::IntAlu 87315881 69.37% 69.37% # Class of executed instruction
1404 system.cpu1.op_class::IntMult 273375 0.22% 69.58% # Class of executed instruction
1405 system.cpu1.op_class::IntDiv 10716 0.01% 69.59% # Class of executed instruction
1406 system.cpu1.op_class::FloatAdd 0 0.00% 69.59% # Class of executed instruction
1407 system.cpu1.op_class::FloatCmp 0 0.00% 69.59% # Class of executed instruction
1408 system.cpu1.op_class::FloatCvt 0 0.00% 69.59% # Class of executed instruction
1409 system.cpu1.op_class::FloatMult 0 0.00% 69.59% # Class of executed instruction
1410 system.cpu1.op_class::FloatDiv 0 0.00% 69.59% # Class of executed instruction
1411 system.cpu1.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction
1412 system.cpu1.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction
1413 system.cpu1.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction
1414 system.cpu1.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction
1415 system.cpu1.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction
1416 system.cpu1.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction
1417 system.cpu1.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction
1418 system.cpu1.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction
1419 system.cpu1.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction
1420 system.cpu1.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction
1421 system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction
1422 system.cpu1.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction
1423 system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.59% # Class of executed instruction
1424 system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction
1425 system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.59% # Class of executed instruction
1426 system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.59% # Class of executed instruction
1427 system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction
1428 system.cpu1.op_class::SimdFloatMisc 11213 0.01% 69.60% # Class of executed instruction
1429 system.cpu1.op_class::SimdFloatMult 0 0.00% 69.60% # Class of executed instruction
1430 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.60% # Class of executed instruction
1431 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.60% # Class of executed instruction
1432 system.cpu1.op_class::MemRead 20101554 15.97% 85.57% # Class of executed instruction
1433 system.cpu1.op_class::MemWrite 18165140 14.43% 100.00% # Class of executed instruction
1434 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1435 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1436 system.cpu1.op_class::total 125877921 # Class of executed instruction
1437 system.cpu2.branchPred.lookups 39521108 # Number of BP lookups
1438 system.cpu2.branchPred.condPredicted 27394498 # Number of conditional branches predicted
1439 system.cpu2.branchPred.condIncorrect 1977688 # Number of conditional branches incorrect
1440 system.cpu2.branchPred.BTBLookups 28624019 # Number of BTB lookups
1441 system.cpu2.branchPred.BTBHits 20176228 # Number of BTB hits
1442 system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1443 system.cpu2.branchPred.BTBHitPct 70.487055 # BTB Hit Percentage
1444 system.cpu2.branchPred.usedRAS 4882878 # Number of times the RAS was used to get a target.
1445 system.cpu2.branchPred.RASInCorrect 320724 # Number of incorrect RAS predictions.
1446 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1447 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1448 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1449 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1450 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1451 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1452 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1453 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1454 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1455 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1456 system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1457 system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1458 system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1459 system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1460 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1461 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1462 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1463 system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1464 system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1465 system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1466 system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1467 system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1468 system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1469 system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1470 system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1471 system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1472 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1473 system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1474 system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1475 system.cpu2.dtb.walker.walks 93699 # Table walker walks requested
1476 system.cpu2.dtb.walker.walksLong 93699 # Table walker walks initiated with long descriptors
1477 system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6670 # Level at which table walker walks with long descriptors terminate
1478 system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29108 # Level at which table walker walks with long descriptors terminate
1479 system.cpu2.dtb.walker.walkWaitTime::samples 93699 # Table walker wait (enqueue to first request) latency
1480 system.cpu2.dtb.walker.walkWaitTime::0 93699 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1481 system.cpu2.dtb.walker.walkWaitTime::total 93699 # Table walker wait (enqueue to first request) latency
1482 system.cpu2.dtb.walker.walkCompletionTime::samples 35778 # Table walker service (enqueue to completion) latency
1483 system.cpu2.dtb.walker.walkCompletionTime::mean 25406.269216 # Table walker service (enqueue to completion) latency
1484 system.cpu2.dtb.walker.walkCompletionTime::gmean 22092.991962 # Table walker service (enqueue to completion) latency
1485 system.cpu2.dtb.walker.walkCompletionTime::stdev 16331.424603 # Table walker service (enqueue to completion) latency
1486 system.cpu2.dtb.walker.walkCompletionTime::0-65535 35575 99.43% 99.43% # Table walker service (enqueue to completion) latency
1487 system.cpu2.dtb.walker.walkCompletionTime::131072-196607 169 0.47% 99.90% # Table walker service (enqueue to completion) latency
1488 system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.93% # Table walker service (enqueue to completion) latency
1489 system.cpu2.dtb.walker.walkCompletionTime::262144-327679 13 0.04% 99.96% # Table walker service (enqueue to completion) latency
1490 system.cpu2.dtb.walker.walkCompletionTime::327680-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
1491 system.cpu2.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 99.99% # Table walker service (enqueue to completion) latency
1492 system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1493 system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
1494 system.cpu2.dtb.walker.walkCompletionTime::total 35778 # Table walker service (enqueue to completion) latency
1495 system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution
1496 system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution
1497 system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution
1498 system.cpu2.dtb.walker.walkPageSizes::4K 29108 81.36% 81.36% # Table walker page sizes translated
1499 system.cpu2.dtb.walker.walkPageSizes::2M 6670 18.64% 100.00% # Table walker page sizes translated
1500 system.cpu2.dtb.walker.walkPageSizes::total 35778 # Table walker page sizes translated
1501 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93699 # Table walker requests started/completed, data/inst
1502 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1503 system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93699 # Table walker requests started/completed, data/inst
1504 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 35778 # Table walker requests started/completed, data/inst
1505 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1506 system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 35778 # Table walker requests started/completed, data/inst
1507 system.cpu2.dtb.walker.walkRequestOrigin::total 129477 # Table walker requests started/completed, data/inst
1508 system.cpu2.dtb.inst_hits 0 # ITB inst hits
1509 system.cpu2.dtb.inst_misses 0 # ITB inst misses
1510 system.cpu2.dtb.read_hits 28306173 # DTB read hits
1511 system.cpu2.dtb.read_misses 78188 # DTB read misses
1512 system.cpu2.dtb.write_hits 24883433 # DTB write hits
1513 system.cpu2.dtb.write_misses 15511 # DTB write misses
1514 system.cpu2.dtb.flush_tlb 1186 # Number of times complete TLB was flushed
1515 system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1516 system.cpu2.dtb.flush_tlb_mva_asid 6582 # Number of times TLB was flushed by MVA & ASID
1517 system.cpu2.dtb.flush_tlb_asid 193 # Number of times TLB was flushed by ASID
1518 system.cpu2.dtb.flush_entries 22329 # Number of entries that have been flushed from TLB
1519 system.cpu2.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions
1520 system.cpu2.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch
1521 system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1522 system.cpu2.dtb.perms_faults 3725 # Number of TLB faults due to permissions restrictions
1523 system.cpu2.dtb.read_accesses 28384361 # DTB read accesses
1524 system.cpu2.dtb.write_accesses 24898944 # DTB write accesses
1525 system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
1526 system.cpu2.dtb.hits 53189606 # DTB hits
1527 system.cpu2.dtb.misses 93699 # DTB misses
1528 system.cpu2.dtb.accesses 53283305 # DTB accesses
1529 system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1530 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1531 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1532 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1533 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1534 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1535 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1536 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1537 system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1538 system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1539 system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1540 system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1541 system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1542 system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1543 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1544 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1545 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1546 system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1547 system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1548 system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1549 system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1550 system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1551 system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1552 system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1553 system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1554 system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1555 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1556 system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1557 system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1558 system.cpu2.itb.walker.walks 27049 # Table walker walks requested
1559 system.cpu2.itb.walker.walksLong 27049 # Table walker walks initiated with long descriptors
1560 system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1824 # Level at which table walker walks with long descriptors terminate
1561 system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22699 # Level at which table walker walks with long descriptors terminate
1562 system.cpu2.itb.walker.walkWaitTime::samples 27049 # Table walker wait (enqueue to first request) latency
1563 system.cpu2.itb.walker.walkWaitTime::0 27049 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1564 system.cpu2.itb.walker.walkWaitTime::total 27049 # Table walker wait (enqueue to first request) latency
1565 system.cpu2.itb.walker.walkCompletionTime::samples 24523 # Table walker service (enqueue to completion) latency
1566 system.cpu2.itb.walker.walkCompletionTime::mean 29055.621254 # Table walker service (enqueue to completion) latency
1567 system.cpu2.itb.walker.walkCompletionTime::gmean 25956.010792 # Table walker service (enqueue to completion) latency
1568 system.cpu2.itb.walker.walkCompletionTime::stdev 17576.904821 # Table walker service (enqueue to completion) latency
1569 system.cpu2.itb.walker.walkCompletionTime::0-32767 12420 50.65% 50.65% # Table walker service (enqueue to completion) latency
1570 system.cpu2.itb.walker.walkCompletionTime::32768-65535 11833 48.25% 98.90% # Table walker service (enqueue to completion) latency
1571 system.cpu2.itb.walker.walkCompletionTime::131072-163839 203 0.83% 99.73% # Table walker service (enqueue to completion) latency
1572 system.cpu2.itb.walker.walkCompletionTime::163840-196607 48 0.20% 99.92% # Table walker service (enqueue to completion) latency
1573 system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.93% # Table walker service (enqueue to completion) latency
1574 system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency
1575 system.cpu2.itb.walker.walkCompletionTime::262144-294911 7 0.03% 99.97% # Table walker service (enqueue to completion) latency
1576 system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
1577 system.cpu2.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
1578 system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1579 system.cpu2.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1580 system.cpu2.itb.walker.walkCompletionTime::total 24523 # Table walker service (enqueue to completion) latency
1581 system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution
1582 system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution
1583 system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution
1584 system.cpu2.itb.walker.walkPageSizes::4K 22699 92.56% 92.56% # Table walker page sizes translated
1585 system.cpu2.itb.walker.walkPageSizes::2M 1824 7.44% 100.00% # Table walker page sizes translated
1586 system.cpu2.itb.walker.walkPageSizes::total 24523 # Table walker page sizes translated
1587 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1588 system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27049 # Table walker requests started/completed, data/inst
1589 system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27049 # Table walker requests started/completed, data/inst
1590 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1591 system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24523 # Table walker requests started/completed, data/inst
1592 system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24523 # Table walker requests started/completed, data/inst
1593 system.cpu2.itb.walker.walkRequestOrigin::total 51572 # Table walker requests started/completed, data/inst
1594 system.cpu2.itb.inst_hits 67920418 # ITB inst hits
1595 system.cpu2.itb.inst_misses 27049 # ITB inst misses
1596 system.cpu2.itb.read_hits 0 # DTB read hits
1597 system.cpu2.itb.read_misses 0 # DTB read misses
1598 system.cpu2.itb.write_hits 0 # DTB write hits
1599 system.cpu2.itb.write_misses 0 # DTB write misses
1600 system.cpu2.itb.flush_tlb 1186 # Number of times complete TLB was flushed
1601 system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1602 system.cpu2.itb.flush_tlb_mva_asid 6582 # Number of times TLB was flushed by MVA & ASID
1603 system.cpu2.itb.flush_tlb_asid 193 # Number of times TLB was flushed by ASID
1604 system.cpu2.itb.flush_entries 16678 # Number of entries that have been flushed from TLB
1605 system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1606 system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1607 system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1608 system.cpu2.itb.perms_faults 53297 # Number of TLB faults due to permissions restrictions
1609 system.cpu2.itb.read_accesses 0 # DTB read accesses
1610 system.cpu2.itb.write_accesses 0 # DTB write accesses
1611 system.cpu2.itb.inst_accesses 67947467 # ITB inst accesses
1612 system.cpu2.itb.hits 67920418 # DTB hits
1613 system.cpu2.itb.misses 27049 # DTB misses
1614 system.cpu2.itb.accesses 67947467 # DTB accesses
1615 system.cpu2.numCycles 6665733461 # number of cpu cycles simulated
1616 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1617 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1618 system.cpu2.committedInsts 145260015 # Number of instructions committed
1619 system.cpu2.committedOps 170560320 # Number of ops (including micro ops) committed
1620 system.cpu2.discardedOps 13528820 # Number of ops (including micro ops) which were discarded before commit
1621 system.cpu2.numFetchSuspends 1578 # Number of times Execute suspended instruction fetching
1622 system.cpu2.quiesceCycles 95889999557 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1623 system.cpu2.cpi 45.888288 # CPI: cycles per instruction
1624 system.cpu2.ipc 0.021792 # IPC: instructions per cycle
1625 system.cpu2.kern.inst.arm 0 # number of arm instructions executed
1626 system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
1627 system.cpu2.tickCycles 269818486 # Number of cycles that the object actually ticked
1628 system.cpu2.idleCycles 6395914975 # Total number of cycles that the object has spent stopped
1629 system.cpu3.branchPred.lookups 73106744 # Number of BP lookups
1630 system.cpu3.branchPred.condPredicted 49439775 # Number of conditional branches predicted
1631 system.cpu3.branchPred.condIncorrect 3283160 # Number of conditional branches incorrect
1632 system.cpu3.branchPred.BTBLookups 49494170 # Number of BTB lookups
1633 system.cpu3.branchPred.BTBHits 35647247 # Number of BTB hits
1634 system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1635 system.cpu3.branchPred.BTBHitPct 72.023123 # BTB Hit Percentage
1636 system.cpu3.branchPred.usedRAS 9537276 # Number of times the RAS was used to get a target.
1637 system.cpu3.branchPred.RASInCorrect 105421 # Number of incorrect RAS predictions.
1638 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1639 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1640 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1641 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1642 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1643 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1644 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1645 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1646 system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1647 system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1648 system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1649 system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1650 system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1651 system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1652 system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1653 system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1654 system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1655 system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1656 system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1657 system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1658 system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1659 system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1660 system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1661 system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1662 system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1663 system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1664 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1665 system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1666 system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1667 system.cpu3.dtb.walker.walks 494727 # Table walker walks requested
1668 system.cpu3.dtb.walker.walksLong 494727 # Table walker walks initiated with long descriptors
1669 system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8139 # Level at which table walker walks with long descriptors terminate
1670 system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49597 # Level at which table walker walks with long descriptors terminate
1671 system.cpu3.dtb.walker.walksSquashedBefore 307402 # Table walks squashed before starting
1672 system.cpu3.dtb.walker.walkWaitTime::samples 187325 # Table walker wait (enqueue to first request) latency
1673 system.cpu3.dtb.walker.walkWaitTime::mean 2316.431336 # Table walker wait (enqueue to first request) latency
1674 system.cpu3.dtb.walker.walkWaitTime::stdev 13967.085425 # Table walker wait (enqueue to first request) latency
1675 system.cpu3.dtb.walker.walkWaitTime::0-65535 186132 99.36% 99.36% # Table walker wait (enqueue to first request) latency
1676 system.cpu3.dtb.walker.walkWaitTime::65536-131071 667 0.36% 99.72% # Table walker wait (enqueue to first request) latency
1677 system.cpu3.dtb.walker.walkWaitTime::131072-196607 353 0.19% 99.91% # Table walker wait (enqueue to first request) latency
1678 system.cpu3.dtb.walker.walkWaitTime::196608-262143 78 0.04% 99.95% # Table walker wait (enqueue to first request) latency
1679 system.cpu3.dtb.walker.walkWaitTime::262144-327679 59 0.03% 99.98% # Table walker wait (enqueue to first request) latency
1680 system.cpu3.dtb.walker.walkWaitTime::327680-393215 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1681 system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1682 system.cpu3.dtb.walker.walkWaitTime::458752-524287 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1683 system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1684 system.cpu3.dtb.walker.walkWaitTime::total 187325 # Table walker wait (enqueue to first request) latency
1685 system.cpu3.dtb.walker.walkCompletionTime::samples 229787 # Table walker service (enqueue to completion) latency
1686 system.cpu3.dtb.walker.walkCompletionTime::mean 22726.216017 # Table walker service (enqueue to completion) latency
1687 system.cpu3.dtb.walker.walkCompletionTime::gmean 18353.180951 # Table walker service (enqueue to completion) latency
1688 system.cpu3.dtb.walker.walkCompletionTime::stdev 18914.444967 # Table walker service (enqueue to completion) latency
1689 system.cpu3.dtb.walker.walkCompletionTime::0-65535 225128 97.97% 97.97% # Table walker service (enqueue to completion) latency
1690 system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3594 1.56% 99.54% # Table walker service (enqueue to completion) latency
1691 system.cpu3.dtb.walker.walkCompletionTime::131072-196607 720 0.31% 99.85% # Table walker service (enqueue to completion) latency
1692 system.cpu3.dtb.walker.walkCompletionTime::196608-262143 65 0.03% 99.88% # Table walker service (enqueue to completion) latency
1693 system.cpu3.dtb.walker.walkCompletionTime::262144-327679 153 0.07% 99.94% # Table walker service (enqueue to completion) latency
1694 system.cpu3.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.98% # Table walker service (enqueue to completion) latency
1695 system.cpu3.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency
1696 system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
1697 system.cpu3.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
1698 system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1699 system.cpu3.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1700 system.cpu3.dtb.walker.walkCompletionTime::total 229787 # Table walker service (enqueue to completion) latency
1701 system.cpu3.dtb.walker.walksPending::samples -29283845516 # Table walker pending requests distribution
1702 system.cpu3.dtb.walker.walksPending::mean 0.245317 # Table walker pending requests distribution
1703 system.cpu3.dtb.walker.walksPending::0-3 -29839367516 101.90% 101.90% # Table walker pending requests distribution
1704 system.cpu3.dtb.walker.walksPending::4-7 306582000 -1.05% 100.85% # Table walker pending requests distribution
1705 system.cpu3.dtb.walker.walksPending::8-11 107118000 -0.37% 100.48% # Table walker pending requests distribution
1706 system.cpu3.dtb.walker.walksPending::12-15 65892000 -0.23% 100.26% # Table walker pending requests distribution
1707 system.cpu3.dtb.walker.walksPending::16-19 24591000 -0.08% 100.18% # Table walker pending requests distribution
1708 system.cpu3.dtb.walker.walksPending::20-23 14226000 -0.05% 100.13% # Table walker pending requests distribution
1709 system.cpu3.dtb.walker.walksPending::24-27 14020500 -0.05% 100.08% # Table walker pending requests distribution
1710 system.cpu3.dtb.walker.walksPending::28-31 18907500 -0.06% 100.01% # Table walker pending requests distribution
1711 system.cpu3.dtb.walker.walksPending::32-35 4030000 -0.01% 100.00% # Table walker pending requests distribution
1712 system.cpu3.dtb.walker.walksPending::36-39 146000 -0.00% 100.00% # Table walker pending requests distribution
1713 system.cpu3.dtb.walker.walksPending::40-43 9000 -0.00% 100.00% # Table walker pending requests distribution
1714 system.cpu3.dtb.walker.walksPending::total -29283845516 # Table walker pending requests distribution
1715 system.cpu3.dtb.walker.walkPageSizes::4K 49597 85.90% 85.90% # Table walker page sizes translated
1716 system.cpu3.dtb.walker.walkPageSizes::2M 8139 14.10% 100.00% # Table walker page sizes translated
1717 system.cpu3.dtb.walker.walkPageSizes::total 57736 # Table walker page sizes translated
1718 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 494727 # Table walker requests started/completed, data/inst
1719 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1720 system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 494727 # Table walker requests started/completed, data/inst
1721 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 57736 # Table walker requests started/completed, data/inst
1722 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1723 system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 57736 # Table walker requests started/completed, data/inst
1724 system.cpu3.dtb.walker.walkRequestOrigin::total 552463 # Table walker requests started/completed, data/inst
1725 system.cpu3.dtb.inst_hits 0 # ITB inst hits
1726 system.cpu3.dtb.inst_misses 0 # ITB inst misses
1727 system.cpu3.dtb.read_hits 58246352 # DTB read hits
1728 system.cpu3.dtb.read_misses 339748 # DTB read misses
1729 system.cpu3.dtb.write_hits 45232753 # DTB write hits
1730 system.cpu3.dtb.write_misses 154979 # DTB write misses
1731 system.cpu3.dtb.flush_tlb 1185 # Number of times complete TLB was flushed
1732 system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1733 system.cpu3.dtb.flush_tlb_mva_asid 11213 # Number of times TLB was flushed by MVA & ASID
1734 system.cpu3.dtb.flush_tlb_asid 305 # Number of times TLB was flushed by ASID
1735 system.cpu3.dtb.flush_entries 29617 # Number of entries that have been flushed from TLB
1736 system.cpu3.dtb.align_faults 79 # Number of TLB faults due to alignment restrictions
1737 system.cpu3.dtb.prefetch_faults 4718 # Number of TLB faults due to prefetch
1738 system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1739 system.cpu3.dtb.perms_faults 32277 # Number of TLB faults due to permissions restrictions
1740 system.cpu3.dtb.read_accesses 58586100 # DTB read accesses
1741 system.cpu3.dtb.write_accesses 45387732 # DTB write accesses
1742 system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
1743 system.cpu3.dtb.hits 103479105 # DTB hits
1744 system.cpu3.dtb.misses 494727 # DTB misses
1745 system.cpu3.dtb.accesses 103973832 # DTB accesses
1746 system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1747 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1748 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1749 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1750 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1751 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1752 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1753 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1754 system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1755 system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1756 system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1757 system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1758 system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1759 system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1760 system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1761 system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1762 system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1763 system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1764 system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1765 system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1766 system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1767 system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1768 system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1769 system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1770 system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1771 system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1772 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1773 system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1774 system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1775 system.cpu3.itb.walker.walks 60127 # Table walker walks requested
1776 system.cpu3.itb.walker.walksLong 60127 # Table walker walks initiated with long descriptors
1777 system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1977 # Level at which table walker walks with long descriptors terminate
1778 system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41370 # Level at which table walker walks with long descriptors terminate
1779 system.cpu3.itb.walker.walksSquashedBefore 8202 # Table walks squashed before starting
1780 system.cpu3.itb.walker.walkWaitTime::samples 51925 # Table walker wait (enqueue to first request) latency
1781 system.cpu3.itb.walker.walkWaitTime::mean 1583.187289 # Table walker wait (enqueue to first request) latency
1782 system.cpu3.itb.walker.walkWaitTime::stdev 9631.832849 # Table walker wait (enqueue to first request) latency
1783 system.cpu3.itb.walker.walkWaitTime::0-32767 51469 99.12% 99.12% # Table walker wait (enqueue to first request) latency
1784 system.cpu3.itb.walker.walkWaitTime::32768-65535 278 0.54% 99.66% # Table walker wait (enqueue to first request) latency
1785 system.cpu3.itb.walker.walkWaitTime::65536-98303 39 0.08% 99.73% # Table walker wait (enqueue to first request) latency
1786 system.cpu3.itb.walker.walkWaitTime::98304-131071 41 0.08% 99.81% # Table walker wait (enqueue to first request) latency
1787 system.cpu3.itb.walker.walkWaitTime::131072-163839 70 0.13% 99.95% # Table walker wait (enqueue to first request) latency
1788 system.cpu3.itb.walker.walkWaitTime::163840-196607 14 0.03% 99.97% # Table walker wait (enqueue to first request) latency
1789 system.cpu3.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1790 system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1791 system.cpu3.itb.walker.walkWaitTime::262144-294911 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1792 system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1793 system.cpu3.itb.walker.walkWaitTime::total 51925 # Table walker wait (enqueue to first request) latency
1794 system.cpu3.itb.walker.walkCompletionTime::samples 51549 # Table walker service (enqueue to completion) latency
1795 system.cpu3.itb.walker.walkCompletionTime::mean 29040.146269 # Table walker service (enqueue to completion) latency
1796 system.cpu3.itb.walker.walkCompletionTime::gmean 24568.436348 # Table walker service (enqueue to completion) latency
1797 system.cpu3.itb.walker.walkCompletionTime::stdev 21519.136506 # Table walker service (enqueue to completion) latency
1798 system.cpu3.itb.walker.walkCompletionTime::0-65535 50502 97.97% 97.97% # Table walker service (enqueue to completion) latency
1799 system.cpu3.itb.walker.walkCompletionTime::65536-131071 358 0.69% 98.66% # Table walker service (enqueue to completion) latency
1800 system.cpu3.itb.walker.walkCompletionTime::131072-196607 600 1.16% 99.83% # Table walker service (enqueue to completion) latency
1801 system.cpu3.itb.walker.walkCompletionTime::196608-262143 30 0.06% 99.89% # Table walker service (enqueue to completion) latency
1802 system.cpu3.itb.walker.walkCompletionTime::262144-327679 32 0.06% 99.95% # Table walker service (enqueue to completion) latency
1803 system.cpu3.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.98% # Table walker service (enqueue to completion) latency
1804 system.cpu3.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1805 system.cpu3.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
1806 system.cpu3.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
1807 system.cpu3.itb.walker.walkCompletionTime::total 51549 # Table walker service (enqueue to completion) latency
1808 system.cpu3.itb.walker.walksPending::samples -29286303016 # Table walker pending requests distribution
1809 system.cpu3.itb.walker.walksPending::mean 0.896957 # Table walker pending requests distribution
1810 system.cpu3.itb.walker.walksPending::stdev 0.299007 # Table walker pending requests distribution
1811 system.cpu3.itb.walker.walksPending::0 -2976637360 10.16% 10.16% # Table walker pending requests distribution
1812 system.cpu3.itb.walker.walksPending::1 -26347752656 89.97% 100.13% # Table walker pending requests distribution
1813 system.cpu3.itb.walker.walksPending::2 35165500 -0.12% 100.01% # Table walker pending requests distribution
1814 system.cpu3.itb.walker.walksPending::3 2840000 -0.01% 100.00% # Table walker pending requests distribution
1815 system.cpu3.itb.walker.walksPending::4 71000 -0.00% 100.00% # Table walker pending requests distribution
1816 system.cpu3.itb.walker.walksPending::5 10500 -0.00% 100.00% # Table walker pending requests distribution
1817 system.cpu3.itb.walker.walksPending::total -29286303016 # Table walker pending requests distribution
1818 system.cpu3.itb.walker.walkPageSizes::4K 41370 95.44% 95.44% # Table walker page sizes translated
1819 system.cpu3.itb.walker.walkPageSizes::2M 1977 4.56% 100.00% # Table walker page sizes translated
1820 system.cpu3.itb.walker.walkPageSizes::total 43347 # Table walker page sizes translated
1821 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1822 system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60127 # Table walker requests started/completed, data/inst
1823 system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60127 # Table walker requests started/completed, data/inst
1824 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1825 system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43347 # Table walker requests started/completed, data/inst
1826 system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43347 # Table walker requests started/completed, data/inst
1827 system.cpu3.itb.walker.walkRequestOrigin::total 103474 # Table walker requests started/completed, data/inst
1828 system.cpu3.itb.inst_hits 52640414 # ITB inst hits
1829 system.cpu3.itb.inst_misses 60127 # ITB inst misses
1830 system.cpu3.itb.read_hits 0 # DTB read hits
1831 system.cpu3.itb.read_misses 0 # DTB read misses
1832 system.cpu3.itb.write_hits 0 # DTB write hits
1833 system.cpu3.itb.write_misses 0 # DTB write misses
1834 system.cpu3.itb.flush_tlb 1185 # Number of times complete TLB was flushed
1835 system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1836 system.cpu3.itb.flush_tlb_mva_asid 11213 # Number of times TLB was flushed by MVA & ASID
1837 system.cpu3.itb.flush_tlb_asid 305 # Number of times TLB was flushed by ASID
1838 system.cpu3.itb.flush_entries 23184 # Number of entries that have been flushed from TLB
1839 system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1840 system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1841 system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1842 system.cpu3.itb.perms_faults 115097 # Number of TLB faults due to permissions restrictions
1843 system.cpu3.itb.read_accesses 0 # DTB read accesses
1844 system.cpu3.itb.write_accesses 0 # DTB write accesses
1845 system.cpu3.itb.inst_accesses 52700541 # ITB inst accesses
1846 system.cpu3.itb.hits 52640414 # DTB hits
1847 system.cpu3.itb.misses 60127 # DTB misses
1848 system.cpu3.itb.accesses 52700541 # DTB accesses
1849 system.cpu3.numCycles 367415947 # number of cpu cycles simulated
1850 system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
1851 system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
1852 system.cpu3.fetch.icacheStallCycles 138047852 # Number of cycles fetch is stalled on an Icache miss
1853 system.cpu3.fetch.Insts 324925438 # Number of instructions fetch has processed
1854 system.cpu3.fetch.Branches 73106744 # Number of branches that fetch encountered
1855 system.cpu3.fetch.predictedBranches 45184523 # Number of branches that fetch has predicted taken
1856 system.cpu3.fetch.Cycles 206488551 # Number of cycles fetch has run and was not squashing or blocked
1857 system.cpu3.fetch.SquashCycles 7421915 # Number of cycles fetch has spent squashing
1858 system.cpu3.fetch.TlbCycles 1494390 # Number of cycles fetch has spent waiting for tlb
1859 system.cpu3.fetch.MiscStallCycles 8711 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1860 system.cpu3.fetch.PendingDrainCycles 1919 # Number of cycles fetch has spent waiting on pipes to drain
1861 system.cpu3.fetch.PendingTrapStallCycles 2933513 # Number of stall cycles due to pending traps
1862 system.cpu3.fetch.PendingQuiesceStallCycles 92576 # Number of stall cycles due to pending quiesce instructions
1863 system.cpu3.fetch.IcacheWaitRetryStallCycles 5529 # Number of stall cycles due to full MSHR
1864 system.cpu3.fetch.CacheLines 52507671 # Number of cache lines fetched
1865 system.cpu3.fetch.IcacheSquashes 2023167 # Number of outstanding Icache misses that were squashed
1866 system.cpu3.fetch.ItlbSquashes 24008 # Number of outstanding ITLB misses that were squashed
1867 system.cpu3.fetch.rateDist::samples 352783845 # Number of instructions fetched each cycle (Total)
1868 system.cpu3.fetch.rateDist::mean 1.078296 # Number of instructions fetched each cycle (Total)
1869 system.cpu3.fetch.rateDist::stdev 2.326372 # Number of instructions fetched each cycle (Total)
1870 system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1871 system.cpu3.fetch.rateDist::0 272678491 77.29% 77.29% # Number of instructions fetched each cycle (Total)
1872 system.cpu3.fetch.rateDist::1 9999177 2.83% 80.13% # Number of instructions fetched each cycle (Total)
1873 system.cpu3.fetch.rateDist::2 10154215 2.88% 83.01% # Number of instructions fetched each cycle (Total)
1874 system.cpu3.fetch.rateDist::3 7447502 2.11% 85.12% # Number of instructions fetched each cycle (Total)
1875 system.cpu3.fetch.rateDist::4 15397984 4.36% 89.48% # Number of instructions fetched each cycle (Total)
1876 system.cpu3.fetch.rateDist::5 5025734 1.42% 90.91% # Number of instructions fetched each cycle (Total)
1877 system.cpu3.fetch.rateDist::6 5401897 1.53% 92.44% # Number of instructions fetched each cycle (Total)
1878 system.cpu3.fetch.rateDist::7 4807386 1.36% 93.80% # Number of instructions fetched each cycle (Total)
1879 system.cpu3.fetch.rateDist::8 21871459 6.20% 100.00% # Number of instructions fetched each cycle (Total)
1880 system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1881 system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1882 system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1883 system.cpu3.fetch.rateDist::total 352783845 # Number of instructions fetched each cycle (Total)
1884 system.cpu3.fetch.branchRate 0.198975 # Number of branch fetches per cycle
1885 system.cpu3.fetch.rate 0.884353 # Number of inst fetches per cycle
1886 system.cpu3.decode.IdleCycles 112906719 # Number of cycles decode is idle
1887 system.cpu3.decode.BlockedCycles 170627658 # Number of cycles decode is blocked
1888 system.cpu3.decode.RunCycles 59194480 # Number of cycles decode is running
1889 system.cpu3.decode.UnblockCycles 7143620 # Number of cycles decode is unblocking
1890 system.cpu3.decode.SquashCycles 2909626 # Number of cycles decode is squashing
1891 system.cpu3.decode.BranchResolved 10993587 # Number of times decode resolved a branch
1892 system.cpu3.decode.BranchMispred 812434 # Number of times decode detected a branch misprediction
1893 system.cpu3.decode.DecodedInsts 355125435 # Number of instructions handled by decode
1894 system.cpu3.decode.SquashedInsts 2492983 # Number of squashed instructions handled by decode
1895 system.cpu3.rename.SquashCycles 2909626 # Number of cycles rename is squashing
1896 system.cpu3.rename.IdleCycles 117007450 # Number of cycles rename is idle
1897 system.cpu3.rename.BlockCycles 13956942 # Number of cycles rename is blocking
1898 system.cpu3.rename.serializeStallCycles 135354583 # count of cycles rename stalled for serializing inst
1899 system.cpu3.rename.RunCycles 62147599 # Number of cycles rename is running
1900 system.cpu3.rename.UnblockCycles 21405678 # Number of cycles rename is unblocking
1901 system.cpu3.rename.RenamedInsts 346848000 # Number of instructions processed by rename
1902 system.cpu3.rename.ROBFullEvents 65680 # Number of times rename has blocked due to ROB full
1903 system.cpu3.rename.IQFullEvents 1218522 # Number of times rename has blocked due to IQ full
1904 system.cpu3.rename.LQFullEvents 931993 # Number of times rename has blocked due to LQ full
1905 system.cpu3.rename.SQFullEvents 11105485 # Number of times rename has blocked due to SQ full
1906 system.cpu3.rename.FullRegisterEvents 2097 # Number of times there has been no free registers
1907 system.cpu3.rename.RenamedOperands 331495484 # Number of destination operands rename has renamed
1908 system.cpu3.rename.RenameLookups 531299079 # Number of register rename lookups that rename has made
1909 system.cpu3.rename.int_rename_lookups 409883872 # Number of integer rename lookups
1910 system.cpu3.rename.fp_rename_lookups 498256 # Number of floating rename lookups
1911 system.cpu3.rename.CommittedMaps 278579121 # Number of HB maps that are committed
1912 system.cpu3.rename.UndoneMaps 52916358 # Number of HB maps that are undone due to squashing
1913 system.cpu3.rename.serializingInsts 7952838 # count of serializing insts renamed
1914 system.cpu3.rename.tempSerializingInsts 6842362 # count of temporary serializing insts renamed
1915 system.cpu3.rename.skidInsts 39655118 # count of insts added to the skid buffer
1916 system.cpu3.memDep0.insertedLoads 56090576 # Number of loads inserted to the mem dependence unit.
1917 system.cpu3.memDep0.insertedStores 47550992 # Number of stores inserted to the mem dependence unit.
1918 system.cpu3.memDep0.conflictingLoads 7265418 # Number of conflicting loads.
1919 system.cpu3.memDep0.conflictingStores 7939600 # Number of conflicting stores.
1920 system.cpu3.iq.iqInstsAdded 329496362 # Number of instructions added to the IQ (excludes non-spec)
1921 system.cpu3.iq.iqNonSpecInstsAdded 7936863 # Number of non-speculative instructions added to the IQ
1922 system.cpu3.iq.iqInstsIssued 329269236 # Number of instructions issued
1923 system.cpu3.iq.iqSquashedInstsIssued 468664 # Number of squashed instructions issued
1924 system.cpu3.iq.iqSquashedInstsExamined 44300133 # Number of squashed instructions iterated over during squash; mainly for profiling
1925 system.cpu3.iq.iqSquashedOperandsExamined 28411196 # Number of squashed operands that are examined and possibly removed from graph
1926 system.cpu3.iq.iqSquashedNonSpecRemoved 197124 # Number of squashed non-spec instructions that were removed
1927 system.cpu3.iq.issued_per_cycle::samples 352783845 # Number of insts issued each cycle
1928 system.cpu3.iq.issued_per_cycle::mean 0.933346 # Number of insts issued each cycle
1929 system.cpu3.iq.issued_per_cycle::stdev 1.659424 # Number of insts issued each cycle
1930 system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1931 system.cpu3.iq.issued_per_cycle::0 224815035 63.73% 63.73% # Number of insts issued each cycle
1932 system.cpu3.iq.issued_per_cycle::1 52801661 14.97% 78.69% # Number of insts issued each cycle
1933 system.cpu3.iq.issued_per_cycle::2 24147394 6.84% 85.54% # Number of insts issued each cycle
1934 system.cpu3.iq.issued_per_cycle::3 17186087 4.87% 90.41% # Number of insts issued each cycle
1935 system.cpu3.iq.issued_per_cycle::4 12829115 3.64% 94.05% # Number of insts issued each cycle
1936 system.cpu3.iq.issued_per_cycle::5 9014914 2.56% 96.60% # Number of insts issued each cycle
1937 system.cpu3.iq.issued_per_cycle::6 6070700 1.72% 98.32% # Number of insts issued each cycle
1938 system.cpu3.iq.issued_per_cycle::7 3552216 1.01% 99.33% # Number of insts issued each cycle
1939 system.cpu3.iq.issued_per_cycle::8 2366723 0.67% 100.00% # Number of insts issued each cycle
1940 system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1941 system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1942 system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1943 system.cpu3.iq.issued_per_cycle::total 352783845 # Number of insts issued each cycle
1944 system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1945 system.cpu3.iq.fu_full::IntAlu 1655726 25.42% 25.42% # attempts to use FU when none available
1946 system.cpu3.iq.fu_full::IntMult 16802 0.26% 25.68% # attempts to use FU when none available
1947 system.cpu3.iq.fu_full::IntDiv 1467 0.02% 25.70% # attempts to use FU when none available
1948 system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.70% # attempts to use FU when none available
1949 system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.70% # attempts to use FU when none available
1950 system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.70% # attempts to use FU when none available
1951 system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.70% # attempts to use FU when none available
1952 system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.70% # attempts to use FU when none available
1953 system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.70% # attempts to use FU when none available
1954 system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.70% # attempts to use FU when none available
1955 system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.70% # attempts to use FU when none available
1956 system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.70% # attempts to use FU when none available
1957 system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.70% # attempts to use FU when none available
1958 system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.70% # attempts to use FU when none available
1959 system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.70% # attempts to use FU when none available
1960 system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.70% # attempts to use FU when none available
1961 system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.70% # attempts to use FU when none available
1962 system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.70% # attempts to use FU when none available
1963 system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.70% # attempts to use FU when none available
1964 system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.70% # attempts to use FU when none available
1965 system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.70% # attempts to use FU when none available
1966 system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.70% # attempts to use FU when none available
1967 system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.70% # attempts to use FU when none available
1968 system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.70% # attempts to use FU when none available
1969 system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.70% # attempts to use FU when none available
1970 system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.70% # attempts to use FU when none available
1971 system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.70% # attempts to use FU when none available
1972 system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.70% # attempts to use FU when none available
1973 system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.70% # attempts to use FU when none available
1974 system.cpu3.iq.fu_full::MemRead 2658135 40.82% 66.52% # attempts to use FU when none available
1975 system.cpu3.iq.fu_full::MemWrite 2180482 33.48% 100.00% # attempts to use FU when none available
1976 system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1977 system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1978 system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued
1979 system.cpu3.iq.FU_type_0::IntAlu 223168493 67.78% 67.78% # Type of FU issued
1980 system.cpu3.iq.FU_type_0::IntMult 780707 0.24% 68.01% # Type of FU issued
1981 system.cpu3.iq.FU_type_0::IntDiv 40175 0.01% 68.03% # Type of FU issued
1982 system.cpu3.iq.FU_type_0::FloatAdd 174 0.00% 68.03% # Type of FU issued
1983 system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.03% # Type of FU issued
1984 system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.03% # Type of FU issued
1985 system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.03% # Type of FU issued
1986 system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.03% # Type of FU issued
1987 system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.03% # Type of FU issued
1988 system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.03% # Type of FU issued
1989 system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.03% # Type of FU issued
1990 system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.03% # Type of FU issued
1991 system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.03% # Type of FU issued
1992 system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.03% # Type of FU issued
1993 system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.03% # Type of FU issued
1994 system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.03% # Type of FU issued
1995 system.cpu3.iq.FU_type_0::SimdMultAcc 1 0.00% 68.03% # Type of FU issued
1996 system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.03% # Type of FU issued
1997 system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued
1998 system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.03% # Type of FU issued
1999 system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued
2000 system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued
2001 system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued
2002 system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued
2003 system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued
2004 system.cpu3.iq.FU_type_0::SimdFloatMisc 42531 0.01% 68.04% # Type of FU issued
2005 system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued
2006 system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued
2007 system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued
2008 system.cpu3.iq.FU_type_0::MemRead 59412355 18.04% 86.08% # Type of FU issued
2009 system.cpu3.iq.FU_type_0::MemWrite 45824773 13.92% 100.00% # Type of FU issued
2010 system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2011 system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2012 system.cpu3.iq.FU_type_0::total 329269236 # Type of FU issued
2013 system.cpu3.iq.rate 0.896176 # Inst issue rate
2014 system.cpu3.iq.fu_busy_cnt 6512612 # FU busy when requested
2015 system.cpu3.iq.fu_busy_rate 0.019779 # FU busy rate (busy events/executed inst)
2016 system.cpu3.iq.int_inst_queue_reads 1017639354 # Number of integer instruction queue reads
2017 system.cpu3.iq.int_inst_queue_writes 381768294 # Number of integer instruction queue writes
2018 system.cpu3.iq.int_inst_queue_wakeup_accesses 317351059 # Number of integer instruction queue wakeup accesses
2019 system.cpu3.iq.fp_inst_queue_reads 664239 # Number of floating instruction queue reads
2020 system.cpu3.iq.fp_inst_queue_writes 330816 # Number of floating instruction queue writes
2021 system.cpu3.iq.fp_inst_queue_wakeup_accesses 296027 # Number of floating instruction queue wakeup accesses
2022 system.cpu3.iq.int_alu_accesses 335426759 # Number of integer alu accesses
2023 system.cpu3.iq.fp_alu_accesses 355062 # Number of floating point alu accesses
2024 system.cpu3.iew.lsq.thread0.forwLoads 2617033 # Number of loads that had data forwarded from stores
2025 system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2026 system.cpu3.iew.lsq.thread0.squashedLoads 8910571 # Number of loads squashed
2027 system.cpu3.iew.lsq.thread0.ignoredResponses 11930 # Number of memory responses ignored because the instruction is squashed
2028 system.cpu3.iew.lsq.thread0.memOrderViolation 371819 # Number of memory ordering violations
2029 system.cpu3.iew.lsq.thread0.squashedStores 4873914 # Number of stores squashed
2030 system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2031 system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2032 system.cpu3.iew.lsq.thread0.rescheduledLoads 2093383 # Number of loads that were rescheduled
2033 system.cpu3.iew.lsq.thread0.cacheBlocked 4209996 # Number of times an access to memory failed due to the cache being blocked
2034 system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2035 system.cpu3.iew.iewSquashCycles 2909626 # Number of cycles IEW is squashing
2036 system.cpu3.iew.iewBlockCycles 8686652 # Number of cycles IEW is blocking
2037 system.cpu3.iew.iewUnblockCycles 4058716 # Number of cycles IEW is unblocking
2038 system.cpu3.iew.iewDispatchedInsts 337508586 # Number of instructions dispatched to IQ
2039 system.cpu3.iew.iewDispSquashedInsts 999497 # Number of squashed instructions skipped by dispatch
2040 system.cpu3.iew.iewDispLoadInsts 56090576 # Number of dispatched load instructions
2041 system.cpu3.iew.iewDispStoreInsts 47550992 # Number of dispatched store instructions
2042 system.cpu3.iew.iewDispNonSpecInsts 6693033 # Number of dispatched non-speculative instructions
2043 system.cpu3.iew.iewIQFullEvents 115188 # Number of times the IQ has become full, causing a stall
2044 system.cpu3.iew.iewLSQFullEvents 3897473 # Number of times the LSQ has become full, causing a stall
2045 system.cpu3.iew.memOrderViolationEvents 371819 # Number of memory order violations
2046 system.cpu3.iew.predictedTakenIncorrect 1479948 # Number of branches that were predicted taken incorrectly
2047 system.cpu3.iew.predictedNotTakenIncorrect 1304525 # Number of branches that were predicted not taken incorrectly
2048 system.cpu3.iew.branchMispredicts 2784473 # Number of branch mispredicts detected at execute
2049 system.cpu3.iew.iewExecutedInsts 325518299 # Number of executed instructions
2050 system.cpu3.iew.iewExecLoadInsts 58237072 # Number of load instructions executed
2051 system.cpu3.iew.iewExecSquashedInsts 3261982 # Number of squashed instructions skipped in execute
2052 system.cpu3.iew.exec_swp 0 # number of swp insts executed
2053 system.cpu3.iew.exec_nop 75361 # number of nop insts executed
2054 system.cpu3.iew.exec_refs 103468304 # number of memory reference insts executed
2055 system.cpu3.iew.exec_branches 60421077 # Number of branches executed
2056 system.cpu3.iew.exec_stores 45231232 # Number of stores executed
2057 system.cpu3.iew.exec_rate 0.885967 # Inst execution rate
2058 system.cpu3.iew.wb_sent 318319204 # cumulative count of insts sent to commit
2059 system.cpu3.iew.wb_count 317647086 # cumulative count of insts written-back
2060 system.cpu3.iew.wb_producers 156971025 # num instructions producing a value
2061 system.cpu3.iew.wb_consumers 272519290 # num instructions consuming a value
2062 system.cpu3.iew.wb_rate 0.864544 # insts written-back per cycle
2063 system.cpu3.iew.wb_fanout 0.576000 # average fanout of values written-back
2064 system.cpu3.commit.commitSquashedInsts 44325764 # The number of squashed insts skipped by commit
2065 system.cpu3.commit.commitNonSpecStalls 7739739 # The number of times commit has been forced to stall to communicate backwards
2066 system.cpu3.commit.branchMispredicts 2481675 # The number of times a branch was mispredicted
2067 system.cpu3.commit.committed_per_cycle::samples 345244332 # Number of insts commited each cycle
2068 system.cpu3.commit.committed_per_cycle::mean 0.849060 # Number of insts commited each cycle
2069 system.cpu3.commit.committed_per_cycle::stdev 1.846955 # Number of insts commited each cycle
2070 system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2071 system.cpu3.commit.committed_per_cycle::0 238738698 69.15% 69.15% # Number of insts commited each cycle
2072 system.cpu3.commit.committed_per_cycle::1 51567808 14.94% 84.09% # Number of insts commited each cycle
2073 system.cpu3.commit.committed_per_cycle::2 18622481 5.39% 89.48% # Number of insts commited each cycle
2074 system.cpu3.commit.committed_per_cycle::3 8388535 2.43% 91.91% # Number of insts commited each cycle
2075 system.cpu3.commit.committed_per_cycle::4 6065452 1.76% 93.67% # Number of insts commited each cycle
2076 system.cpu3.commit.committed_per_cycle::5 3663652 1.06% 94.73% # Number of insts commited each cycle
2077 system.cpu3.commit.committed_per_cycle::6 3429214 0.99% 95.72% # Number of insts commited each cycle
2078 system.cpu3.commit.committed_per_cycle::7 2148576 0.62% 96.34% # Number of insts commited each cycle
2079 system.cpu3.commit.committed_per_cycle::8 12619916 3.66% 100.00% # Number of insts commited each cycle
2080 system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2081 system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2082 system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2083 system.cpu3.commit.committed_per_cycle::total 345244332 # Number of insts commited each cycle
2084 system.cpu3.commit.committedInsts 249501623 # Number of instructions committed
2085 system.cpu3.commit.committedOps 293133087 # Number of ops (including micro ops) committed
2086 system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
2087 system.cpu3.commit.refs 89857082 # Number of memory references committed
2088 system.cpu3.commit.loads 47180004 # Number of loads committed
2089 system.cpu3.commit.membars 1961101 # Number of memory barriers committed
2090 system.cpu3.commit.branches 55730410 # Number of branches committed
2091 system.cpu3.commit.fp_insts 284466 # Number of committed floating point instructions.
2092 system.cpu3.commit.int_insts 269318634 # Number of committed integer instructions.
2093 system.cpu3.commit.function_calls 7382541 # Number of function calls committed.
2094 system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2095 system.cpu3.commit.op_class_0::IntAlu 202599565 69.12% 69.12% # Class of committed instruction
2096 system.cpu3.commit.op_class_0::IntMult 609386 0.21% 69.32% # Class of committed instruction
2097 system.cpu3.commit.op_class_0::IntDiv 30413 0.01% 69.33% # Class of committed instruction
2098 system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
2099 system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
2100 system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
2101 system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
2102 system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
2103 system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
2104 system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
2105 system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
2106 system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
2107 system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
2108 system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
2109 system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
2110 system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
2111 system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
2112 system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
2113 system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
2114 system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
2115 system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
2116 system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
2117 system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
2118 system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
2119 system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
2120 system.cpu3.commit.op_class_0::SimdFloatMisc 36641 0.01% 69.35% # Class of committed instruction
2121 system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction
2122 system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction
2123 system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction
2124 system.cpu3.commit.op_class_0::MemRead 47180004 16.10% 85.44% # Class of committed instruction
2125 system.cpu3.commit.op_class_0::MemWrite 42677078 14.56% 100.00% # Class of committed instruction
2126 system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2127 system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2128 system.cpu3.commit.op_class_0::total 293133087 # Class of committed instruction
2129 system.cpu3.commit.bw_lim_events 12619916 # number cycles where commit BW limit reached
2130 system.cpu3.rob.rob_reads 668027626 # The number of ROB reads
2131 system.cpu3.rob.rob_writes 682469296 # The number of ROB writes
2132 system.cpu3.timesIdled 2366991 # Number of times that the entire CPU went into an idle state and unscheduled itself
2133 system.cpu3.idleCycles 14632102 # Total number of cycles that the CPU has spent unscheduled due to idling
2134 system.cpu3.quiesceCycles 98631076285 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2135 system.cpu3.committedInsts 249501623 # Number of Instructions Simulated
2136 system.cpu3.committedOps 293133087 # Number of Ops (including micro ops) Simulated
2137 system.cpu3.cpi 1.472599 # CPI: Cycles Per Instruction
2138 system.cpu3.cpi_total 1.472599 # CPI: Total CPI of All Threads
2139 system.cpu3.ipc 0.679071 # IPC: Instructions Per Cycle
2140 system.cpu3.ipc_total 0.679071 # IPC: Total IPC of All Threads
2141 system.cpu3.int_regfile_reads 383683244 # number of integer regfile reads
2142 system.cpu3.int_regfile_writes 227091338 # number of integer regfile writes
2143 system.cpu3.fp_regfile_reads 575742 # number of floating regfile reads
2144 system.cpu3.fp_regfile_writes 354224 # number of floating regfile writes
2145 system.cpu3.cc_regfile_reads 69408942 # number of cc regfile reads
2146 system.cpu3.cc_regfile_writes 70047711 # number of cc regfile writes
2147 system.cpu3.misc_regfile_reads 653726404 # number of misc regfile reads
2148 system.cpu3.misc_regfile_writes 7798013 # number of misc regfile writes
2149 system.iobus.trans_dist::ReadReq 40238 # Transaction distribution
2150 system.iobus.trans_dist::ReadResp 40238 # Transaction distribution
2151 system.iobus.trans_dist::WriteReq 136511 # Transaction distribution
2152 system.iobus.trans_dist::WriteResp 136511 # Transaction distribution
2153 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes)
2154 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2155 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2156 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2157 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2158 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2159 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2160 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2161 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2162 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2163 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2164 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29444 # Packet count per connected master and slave (bytes)
2165 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2166 system.iobus.pkt_count_system.bridge.master::total 122464 # Packet count per connected master and slave (bytes)
2167 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
2168 system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
2169 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2170 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2171 system.iobus.pkt_count::total 353498 # Packet count per connected master and slave (bytes)
2172 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes)
2173 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2174 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2175 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2176 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2177 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2178 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2179 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2180 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2181 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2182 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2183 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17500 # Cumulative packet size per connected master and slave (bytes)
2184 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2185 system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes)
2186 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
2187 system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
2188 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2189 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2190 system.iobus.pkt_size::total 7491974 # Cumulative packet size per connected master and slave (bytes)
2191 system.iobus.reqLayer0.occupancy 34324500 # Layer occupancy (ticks)
2192 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2193 system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks)
2194 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2195 system.iobus.reqLayer2.occupancy 218500 # Layer occupancy (ticks)
2196 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2197 system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2198 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2199 system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
2200 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2201 system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
2202 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2203 system.iobus.reqLayer16.occupancy 5500 # Layer occupancy (ticks)
2204 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2205 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2206 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2207 system.iobus.reqLayer23.occupancy 13530000 # Layer occupancy (ticks)
2208 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2209 system.iobus.reqLayer24.occupancy 21519000 # Layer occupancy (ticks)
2210 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2211 system.iobus.reqLayer25.occupancy 268744919 # Layer occupancy (ticks)
2212 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2213 system.iobus.respLayer0.occupancy 59904000 # Layer occupancy (ticks)
2214 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2215 system.iobus.respLayer3.occupancy 77390000 # Layer occupancy (ticks)
2216 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2217 system.iocache.tags.replacements 115459 # number of replacements
2218 system.iocache.tags.tagsinuse 10.420604 # Cycle average of tags in use
2219 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2220 system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
2221 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2222 system.iocache.tags.warmup_cycle 13089166746509 # Cycle when the warmup percentage was hit.
2223 system.iocache.tags.occ_blocks::realview.ethernet 3.547315 # Average occupied blocks per requestor
2224 system.iocache.tags.occ_blocks::realview.ide 6.873289 # Average occupied blocks per requestor
2225 system.iocache.tags.occ_percent::realview.ethernet 0.221707 # Average percentage of cache occupancy
2226 system.iocache.tags.occ_percent::realview.ide 0.429581 # Average percentage of cache occupancy
2227 system.iocache.tags.occ_percent::total 0.651288 # Average percentage of cache occupancy
2228 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2229 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2230 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2231 system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
2232 system.iocache.tags.data_accesses 1039650 # Number of data accesses
2233 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2234 system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
2235 system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
2236 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2237 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2238 system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
2239 system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2240 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2241 system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
2242 system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
2243 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2244 system.iocache.overall_misses::realview.ide 8813 # number of overall misses
2245 system.iocache.overall_misses::total 8853 # number of overall misses
2246 system.iocache.ReadReq_miss_latency::realview.ide 1097461741 # number of ReadReq miss cycles
2247 system.iocache.ReadReq_miss_latency::total 1097461741 # number of ReadReq miss cycles
2248 system.iocache.WriteLineReq_miss_latency::realview.ide 6290187178 # number of WriteLineReq miss cycles
2249 system.iocache.WriteLineReq_miss_latency::total 6290187178 # number of WriteLineReq miss cycles
2250 system.iocache.demand_miss_latency::realview.ide 1097461741 # number of demand (read+write) miss cycles
2251 system.iocache.demand_miss_latency::total 1097461741 # number of demand (read+write) miss cycles
2252 system.iocache.overall_miss_latency::realview.ide 1097461741 # number of overall miss cycles
2253 system.iocache.overall_miss_latency::total 1097461741 # number of overall miss cycles
2254 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2255 system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
2256 system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
2257 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2258 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2259 system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
2260 system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2261 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2262 system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
2263 system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
2264 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2265 system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
2266 system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
2267 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2268 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2269 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2270 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2271 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2272 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2273 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2274 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2275 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2276 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2277 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2278 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2279 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2280 system.iocache.ReadReq_avg_miss_latency::realview.ide 124527.600250 # average ReadReq miss latency
2281 system.iocache.ReadReq_avg_miss_latency::total 124006.976384 # average ReadReq miss latency
2282 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58971.979093 # average WriteLineReq miss latency
2283 system.iocache.WriteLineReq_avg_miss_latency::total 58971.979093 # average WriteLineReq miss latency
2284 system.iocache.demand_avg_miss_latency::realview.ide 124527.600250 # average overall miss latency
2285 system.iocache.demand_avg_miss_latency::total 123964.954366 # average overall miss latency
2286 system.iocache.overall_avg_miss_latency::realview.ide 124527.600250 # average overall miss latency
2287 system.iocache.overall_avg_miss_latency::total 123964.954366 # average overall miss latency
2288 system.iocache.blocked_cycles::no_mshrs 22895 # number of cycles access was blocked
2289 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2290 system.iocache.blocked::no_mshrs 2302 # number of cycles access was blocked
2291 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2292 system.iocache.avg_blocked_cycles::no_mshrs 9.945699 # average number of cycles each access was blocked
2293 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2294 system.iocache.fast_writes 0 # number of fast writes performed
2295 system.iocache.cache_copies 0 # number of cache copies performed
2296 system.iocache.writebacks::writebacks 106631 # number of writebacks
2297 system.iocache.writebacks::total 106631 # number of writebacks
2298 system.iocache.ReadReq_mshr_misses::realview.ide 5727 # number of ReadReq MSHR misses
2299 system.iocache.ReadReq_mshr_misses::total 5727 # number of ReadReq MSHR misses
2300 system.iocache.WriteLineReq_mshr_misses::realview.ide 50000 # number of WriteLineReq MSHR misses
2301 system.iocache.WriteLineReq_mshr_misses::total 50000 # number of WriteLineReq MSHR misses
2302 system.iocache.demand_mshr_misses::realview.ide 5727 # number of demand (read+write) MSHR misses
2303 system.iocache.demand_mshr_misses::total 5727 # number of demand (read+write) MSHR misses
2304 system.iocache.overall_mshr_misses::realview.ide 5727 # number of overall MSHR misses
2305 system.iocache.overall_mshr_misses::total 5727 # number of overall MSHR misses
2306 system.iocache.ReadReq_mshr_miss_latency::realview.ide 811111741 # number of ReadReq MSHR miss cycles
2307 system.iocache.ReadReq_mshr_miss_latency::total 811111741 # number of ReadReq MSHR miss cycles
2308 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3787932075 # number of WriteLineReq MSHR miss cycles
2309 system.iocache.WriteLineReq_mshr_miss_latency::total 3787932075 # number of WriteLineReq MSHR miss cycles
2310 system.iocache.demand_mshr_miss_latency::realview.ide 811111741 # number of demand (read+write) MSHR miss cycles
2311 system.iocache.demand_mshr_miss_latency::total 811111741 # number of demand (read+write) MSHR miss cycles
2312 system.iocache.overall_mshr_miss_latency::realview.ide 811111741 # number of overall MSHR miss cycles
2313 system.iocache.overall_mshr_miss_latency::total 811111741 # number of overall MSHR miss cycles
2314 system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for ReadReq accesses
2315 system.iocache.ReadReq_mshr_miss_rate::total 0.647119 # mshr miss rate for ReadReq accesses
2316 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.468762 # mshr miss rate for WriteLineReq accesses
2317 system.iocache.WriteLineReq_mshr_miss_rate::total 0.468762 # mshr miss rate for WriteLineReq accesses
2318 system.iocache.demand_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for demand accesses
2319 system.iocache.demand_mshr_miss_rate::total 0.646899 # mshr miss rate for demand accesses
2320 system.iocache.overall_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for overall accesses
2321 system.iocache.overall_mshr_miss_rate::total 0.646899 # mshr miss rate for overall accesses
2322 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141629.429195 # average ReadReq mshr miss latency
2323 system.iocache.ReadReq_avg_mshr_miss_latency::total 141629.429195 # average ReadReq mshr miss latency
2324 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75758.641500 # average WriteLineReq mshr miss latency
2325 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75758.641500 # average WriteLineReq mshr miss latency
2326 system.iocache.demand_avg_mshr_miss_latency::realview.ide 141629.429195 # average overall mshr miss latency
2327 system.iocache.demand_avg_mshr_miss_latency::total 141629.429195 # average overall mshr miss latency
2328 system.iocache.overall_avg_mshr_miss_latency::realview.ide 141629.429195 # average overall mshr miss latency
2329 system.iocache.overall_avg_mshr_miss_latency::total 141629.429195 # average overall mshr miss latency
2330 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2331 system.l2c.tags.replacements 1134655 # number of replacements
2332 system.l2c.tags.tagsinuse 65348.585655 # Cycle average of tags in use
2333 system.l2c.tags.total_refs 47218951 # Total number of references to valid blocks.
2334 system.l2c.tags.sampled_refs 1196839 # Sample count of references to valid blocks.
2335 system.l2c.tags.avg_refs 39.453052 # Average number of references to valid blocks.
2336 system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
2337 system.l2c.tags.occ_blocks::writebacks 36858.424918 # Average occupied blocks per requestor
2338 system.l2c.tags.occ_blocks::cpu0.dtb.walker 139.336234 # Average occupied blocks per requestor
2339 system.l2c.tags.occ_blocks::cpu0.itb.walker 207.961932 # Average occupied blocks per requestor
2340 system.l2c.tags.occ_blocks::cpu0.inst 3464.040368 # Average occupied blocks per requestor
2341 system.l2c.tags.occ_blocks::cpu0.data 8073.434256 # Average occupied blocks per requestor
2342 system.l2c.tags.occ_blocks::cpu1.dtb.walker 31.851614 # Average occupied blocks per requestor
2343 system.l2c.tags.occ_blocks::cpu1.itb.walker 46.563538 # Average occupied blocks per requestor
2344 system.l2c.tags.occ_blocks::cpu1.inst 388.442961 # Average occupied blocks per requestor
2345 system.l2c.tags.occ_blocks::cpu1.data 2039.653767 # Average occupied blocks per requestor
2346 system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.632115 # Average occupied blocks per requestor
2347 system.l2c.tags.occ_blocks::cpu2.itb.walker 59.555007 # Average occupied blocks per requestor
2348 system.l2c.tags.occ_blocks::cpu2.inst 1814.509325 # Average occupied blocks per requestor
2349 system.l2c.tags.occ_blocks::cpu2.data 3538.387838 # Average occupied blocks per requestor
2350 system.l2c.tags.occ_blocks::cpu3.dtb.walker 81.542571 # Average occupied blocks per requestor
2351 system.l2c.tags.occ_blocks::cpu3.itb.walker 121.893588 # Average occupied blocks per requestor
2352 system.l2c.tags.occ_blocks::cpu3.inst 2682.398731 # Average occupied blocks per requestor
2353 system.l2c.tags.occ_blocks::cpu3.data 5761.956894 # Average occupied blocks per requestor
2354 system.l2c.tags.occ_percent::writebacks 0.562415 # Average percentage of cache occupancy
2355 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002126 # Average percentage of cache occupancy
2356 system.l2c.tags.occ_percent::cpu0.itb.walker 0.003173 # Average percentage of cache occupancy
2357 system.l2c.tags.occ_percent::cpu0.inst 0.052857 # Average percentage of cache occupancy
2358 system.l2c.tags.occ_percent::cpu0.data 0.123191 # Average percentage of cache occupancy
2359 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000486 # Average percentage of cache occupancy
2360 system.l2c.tags.occ_percent::cpu1.itb.walker 0.000711 # Average percentage of cache occupancy
2361 system.l2c.tags.occ_percent::cpu1.inst 0.005927 # Average percentage of cache occupancy
2362 system.l2c.tags.occ_percent::cpu1.data 0.031123 # Average percentage of cache occupancy
2363 system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000589 # Average percentage of cache occupancy
2364 system.l2c.tags.occ_percent::cpu2.itb.walker 0.000909 # Average percentage of cache occupancy
2365 system.l2c.tags.occ_percent::cpu2.inst 0.027687 # Average percentage of cache occupancy
2366 system.l2c.tags.occ_percent::cpu2.data 0.053992 # Average percentage of cache occupancy
2367 system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001244 # Average percentage of cache occupancy
2368 system.l2c.tags.occ_percent::cpu3.itb.walker 0.001860 # Average percentage of cache occupancy
2369 system.l2c.tags.occ_percent::cpu3.inst 0.040930 # Average percentage of cache occupancy
2370 system.l2c.tags.occ_percent::cpu3.data 0.087920 # Average percentage of cache occupancy
2371 system.l2c.tags.occ_percent::total 0.997140 # Average percentage of cache occupancy
2372 system.l2c.tags.occ_task_id_blocks::1023 269 # Occupied blocks per task id
2373 system.l2c.tags.occ_task_id_blocks::1024 61915 # Occupied blocks per task id
2374 system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
2375 system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id
2376 system.l2c.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
2377 system.l2c.tags.age_task_id_blocks_1024::1 568 # Occupied blocks per task id
2378 system.l2c.tags.age_task_id_blocks_1024::2 2797 # Occupied blocks per task id
2379 system.l2c.tags.age_task_id_blocks_1024::3 5091 # Occupied blocks per task id
2380 system.l2c.tags.age_task_id_blocks_1024::4 53356 # Occupied blocks per task id
2381 system.l2c.tags.occ_task_id_percent::1023 0.004105 # Percentage of cache occupancy per task id
2382 system.l2c.tags.occ_task_id_percent::1024 0.944748 # Percentage of cache occupancy per task id
2383 system.l2c.tags.tag_accesses 417874191 # Number of tag accesses
2384 system.l2c.tags.data_accesses 417874191 # Number of data accesses
2385 system.l2c.ReadReq_hits::cpu0.dtb.walker 157547 # number of ReadReq hits
2386 system.l2c.ReadReq_hits::cpu0.itb.walker 107991 # number of ReadReq hits
2387 system.l2c.ReadReq_hits::cpu1.dtb.walker 56540 # number of ReadReq hits
2388 system.l2c.ReadReq_hits::cpu1.itb.walker 42358 # number of ReadReq hits
2389 system.l2c.ReadReq_hits::cpu2.dtb.walker 150716 # number of ReadReq hits
2390 system.l2c.ReadReq_hits::cpu2.itb.walker 57617 # number of ReadReq hits
2391 system.l2c.ReadReq_hits::cpu3.dtb.walker 285535 # number of ReadReq hits
2392 system.l2c.ReadReq_hits::cpu3.itb.walker 108659 # number of ReadReq hits
2393 system.l2c.ReadReq_hits::total 966963 # number of ReadReq hits
2394 system.l2c.WritebackDirty_hits::writebacks 7469710 # number of WritebackDirty hits
2395 system.l2c.WritebackDirty_hits::total 7469710 # number of WritebackDirty hits
2396 system.l2c.WritebackClean_hits::writebacks 15704683 # number of WritebackClean hits
2397 system.l2c.WritebackClean_hits::total 15704683 # number of WritebackClean hits
2398 system.l2c.UpgradeReq_hits::cpu0.data 3849 # number of UpgradeReq hits
2399 system.l2c.UpgradeReq_hits::cpu1.data 1299 # number of UpgradeReq hits
2400 system.l2c.UpgradeReq_hits::cpu2.data 1546 # number of UpgradeReq hits
2401 system.l2c.UpgradeReq_hits::cpu3.data 2673 # number of UpgradeReq hits
2402 system.l2c.UpgradeReq_hits::total 9367 # number of UpgradeReq hits
2403 system.l2c.ReadExReq_hits::cpu0.data 642784 # number of ReadExReq hits
2404 system.l2c.ReadExReq_hits::cpu1.data 197897 # number of ReadExReq hits
2405 system.l2c.ReadExReq_hits::cpu2.data 265419 # number of ReadExReq hits
2406 system.l2c.ReadExReq_hits::cpu3.data 474003 # number of ReadExReq hits
2407 system.l2c.ReadExReq_hits::total 1580103 # number of ReadExReq hits
2408 system.l2c.ReadCleanReq_hits::cpu0.inst 5527952 # number of ReadCleanReq hits
2409 system.l2c.ReadCleanReq_hits::cpu1.inst 1660805 # number of ReadCleanReq hits
2410 system.l2c.ReadCleanReq_hits::cpu2.inst 3842883 # number of ReadCleanReq hits
2411 system.l2c.ReadCleanReq_hits::cpu3.inst 4583462 # number of ReadCleanReq hits
2412 system.l2c.ReadCleanReq_hits::total 15615102 # number of ReadCleanReq hits
2413 system.l2c.ReadSharedReq_hits::cpu0.data 2499377 # number of ReadSharedReq hits
2414 system.l2c.ReadSharedReq_hits::cpu1.data 796548 # number of ReadSharedReq hits
2415 system.l2c.ReadSharedReq_hits::cpu2.data 1051090 # number of ReadSharedReq hits
2416 system.l2c.ReadSharedReq_hits::cpu3.data 1860386 # number of ReadSharedReq hits
2417 system.l2c.ReadSharedReq_hits::total 6207401 # number of ReadSharedReq hits
2418 system.l2c.InvalidateReq_hits::cpu0.data 289262 # number of InvalidateReq hits
2419 system.l2c.InvalidateReq_hits::cpu1.data 89246 # number of InvalidateReq hits
2420 system.l2c.InvalidateReq_hits::cpu2.data 125740 # number of InvalidateReq hits
2421 system.l2c.InvalidateReq_hits::cpu3.data 228993 # number of InvalidateReq hits
2422 system.l2c.InvalidateReq_hits::total 733241 # number of InvalidateReq hits
2423 system.l2c.demand_hits::cpu0.dtb.walker 157547 # number of demand (read+write) hits
2424 system.l2c.demand_hits::cpu0.itb.walker 107991 # number of demand (read+write) hits
2425 system.l2c.demand_hits::cpu0.inst 5527952 # number of demand (read+write) hits
2426 system.l2c.demand_hits::cpu0.data 3142161 # number of demand (read+write) hits
2427 system.l2c.demand_hits::cpu1.dtb.walker 56540 # number of demand (read+write) hits
2428 system.l2c.demand_hits::cpu1.itb.walker 42358 # number of demand (read+write) hits
2429 system.l2c.demand_hits::cpu1.inst 1660805 # number of demand (read+write) hits
2430 system.l2c.demand_hits::cpu1.data 994445 # number of demand (read+write) hits
2431 system.l2c.demand_hits::cpu2.dtb.walker 150716 # number of demand (read+write) hits
2432 system.l2c.demand_hits::cpu2.itb.walker 57617 # number of demand (read+write) hits
2433 system.l2c.demand_hits::cpu2.inst 3842883 # number of demand (read+write) hits
2434 system.l2c.demand_hits::cpu2.data 1316509 # number of demand (read+write) hits
2435 system.l2c.demand_hits::cpu3.dtb.walker 285535 # number of demand (read+write) hits
2436 system.l2c.demand_hits::cpu3.itb.walker 108659 # number of demand (read+write) hits
2437 system.l2c.demand_hits::cpu3.inst 4583462 # number of demand (read+write) hits
2438 system.l2c.demand_hits::cpu3.data 2334389 # number of demand (read+write) hits
2439 system.l2c.demand_hits::total 24369569 # number of demand (read+write) hits
2440 system.l2c.overall_hits::cpu0.dtb.walker 157547 # number of overall hits
2441 system.l2c.overall_hits::cpu0.itb.walker 107991 # number of overall hits
2442 system.l2c.overall_hits::cpu0.inst 5527952 # number of overall hits
2443 system.l2c.overall_hits::cpu0.data 3142161 # number of overall hits
2444 system.l2c.overall_hits::cpu1.dtb.walker 56540 # number of overall hits
2445 system.l2c.overall_hits::cpu1.itb.walker 42358 # number of overall hits
2446 system.l2c.overall_hits::cpu1.inst 1660805 # number of overall hits
2447 system.l2c.overall_hits::cpu1.data 994445 # number of overall hits
2448 system.l2c.overall_hits::cpu2.dtb.walker 150716 # number of overall hits
2449 system.l2c.overall_hits::cpu2.itb.walker 57617 # number of overall hits
2450 system.l2c.overall_hits::cpu2.inst 3842883 # number of overall hits
2451 system.l2c.overall_hits::cpu2.data 1316509 # number of overall hits
2452 system.l2c.overall_hits::cpu3.dtb.walker 285535 # number of overall hits
2453 system.l2c.overall_hits::cpu3.itb.walker 108659 # number of overall hits
2454 system.l2c.overall_hits::cpu3.inst 4583462 # number of overall hits
2455 system.l2c.overall_hits::cpu3.data 2334389 # number of overall hits
2456 system.l2c.overall_hits::total 24369569 # number of overall hits
2457 system.l2c.ReadReq_misses::cpu0.dtb.walker 1252 # number of ReadReq misses
2458 system.l2c.ReadReq_misses::cpu0.itb.walker 1338 # number of ReadReq misses
2459 system.l2c.ReadReq_misses::cpu1.dtb.walker 421 # number of ReadReq misses
2460 system.l2c.ReadReq_misses::cpu1.itb.walker 352 # number of ReadReq misses
2461 system.l2c.ReadReq_misses::cpu2.dtb.walker 422 # number of ReadReq misses
2462 system.l2c.ReadReq_misses::cpu2.itb.walker 440 # number of ReadReq misses
2463 system.l2c.ReadReq_misses::cpu3.dtb.walker 924 # number of ReadReq misses
2464 system.l2c.ReadReq_misses::cpu3.itb.walker 892 # number of ReadReq misses
2465 system.l2c.ReadReq_misses::total 6041 # number of ReadReq misses
2466 system.l2c.UpgradeReq_misses::cpu0.data 13973 # number of UpgradeReq misses
2467 system.l2c.UpgradeReq_misses::cpu1.data 4552 # number of UpgradeReq misses
2468 system.l2c.UpgradeReq_misses::cpu2.data 5817 # number of UpgradeReq misses
2469 system.l2c.UpgradeReq_misses::cpu3.data 9421 # number of UpgradeReq misses
2470 system.l2c.UpgradeReq_misses::total 33763 # number of UpgradeReq misses
2471 system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
2472 system.l2c.SCUpgradeReq_misses::cpu3.data 1 # number of SCUpgradeReq misses
2473 system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
2474 system.l2c.ReadExReq_misses::cpu0.data 178447 # number of ReadExReq misses
2475 system.l2c.ReadExReq_misses::cpu1.data 50211 # number of ReadExReq misses
2476 system.l2c.ReadExReq_misses::cpu2.data 60375 # number of ReadExReq misses
2477 system.l2c.ReadExReq_misses::cpu3.data 98714 # number of ReadExReq misses
2478 system.l2c.ReadExReq_misses::total 387747 # number of ReadExReq misses
2479 system.l2c.ReadCleanReq_misses::cpu0.inst 35247 # number of ReadCleanReq misses
2480 system.l2c.ReadCleanReq_misses::cpu1.inst 7011 # number of ReadCleanReq misses
2481 system.l2c.ReadCleanReq_misses::cpu2.inst 23376 # number of ReadCleanReq misses
2482 system.l2c.ReadCleanReq_misses::cpu3.inst 26876 # number of ReadCleanReq misses
2483 system.l2c.ReadCleanReq_misses::total 92510 # number of ReadCleanReq misses
2484 system.l2c.ReadSharedReq_misses::cpu0.data 106344 # number of ReadSharedReq misses
2485 system.l2c.ReadSharedReq_misses::cpu1.data 28129 # number of ReadSharedReq misses
2486 system.l2c.ReadSharedReq_misses::cpu2.data 39147 # number of ReadSharedReq misses
2487 system.l2c.ReadSharedReq_misses::cpu3.data 77644 # number of ReadSharedReq misses
2488 system.l2c.ReadSharedReq_misses::total 251264 # number of ReadSharedReq misses
2489 system.l2c.InvalidateReq_misses::cpu0.data 397385 # number of InvalidateReq misses
2490 system.l2c.InvalidateReq_misses::cpu1.data 19162 # number of InvalidateReq misses
2491 system.l2c.InvalidateReq_misses::cpu2.data 25286 # number of InvalidateReq misses
2492 system.l2c.InvalidateReq_misses::cpu3.data 48757 # number of InvalidateReq misses
2493 system.l2c.InvalidateReq_misses::total 490590 # number of InvalidateReq misses
2494 system.l2c.demand_misses::cpu0.dtb.walker 1252 # number of demand (read+write) misses
2495 system.l2c.demand_misses::cpu0.itb.walker 1338 # number of demand (read+write) misses
2496 system.l2c.demand_misses::cpu0.inst 35247 # number of demand (read+write) misses
2497 system.l2c.demand_misses::cpu0.data 284791 # number of demand (read+write) misses
2498 system.l2c.demand_misses::cpu1.dtb.walker 421 # number of demand (read+write) misses
2499 system.l2c.demand_misses::cpu1.itb.walker 352 # number of demand (read+write) misses
2500 system.l2c.demand_misses::cpu1.inst 7011 # number of demand (read+write) misses
2501 system.l2c.demand_misses::cpu1.data 78340 # number of demand (read+write) misses
2502 system.l2c.demand_misses::cpu2.dtb.walker 422 # number of demand (read+write) misses
2503 system.l2c.demand_misses::cpu2.itb.walker 440 # number of demand (read+write) misses
2504 system.l2c.demand_misses::cpu2.inst 23376 # number of demand (read+write) misses
2505 system.l2c.demand_misses::cpu2.data 99522 # number of demand (read+write) misses
2506 system.l2c.demand_misses::cpu3.dtb.walker 924 # number of demand (read+write) misses
2507 system.l2c.demand_misses::cpu3.itb.walker 892 # number of demand (read+write) misses
2508 system.l2c.demand_misses::cpu3.inst 26876 # number of demand (read+write) misses
2509 system.l2c.demand_misses::cpu3.data 176358 # number of demand (read+write) misses
2510 system.l2c.demand_misses::total 737562 # number of demand (read+write) misses
2511 system.l2c.overall_misses::cpu0.dtb.walker 1252 # number of overall misses
2512 system.l2c.overall_misses::cpu0.itb.walker 1338 # number of overall misses
2513 system.l2c.overall_misses::cpu0.inst 35247 # number of overall misses
2514 system.l2c.overall_misses::cpu0.data 284791 # number of overall misses
2515 system.l2c.overall_misses::cpu1.dtb.walker 421 # number of overall misses
2516 system.l2c.overall_misses::cpu1.itb.walker 352 # number of overall misses
2517 system.l2c.overall_misses::cpu1.inst 7011 # number of overall misses
2518 system.l2c.overall_misses::cpu1.data 78340 # number of overall misses
2519 system.l2c.overall_misses::cpu2.dtb.walker 422 # number of overall misses
2520 system.l2c.overall_misses::cpu2.itb.walker 440 # number of overall misses
2521 system.l2c.overall_misses::cpu2.inst 23376 # number of overall misses
2522 system.l2c.overall_misses::cpu2.data 99522 # number of overall misses
2523 system.l2c.overall_misses::cpu3.dtb.walker 924 # number of overall misses
2524 system.l2c.overall_misses::cpu3.itb.walker 892 # number of overall misses
2525 system.l2c.overall_misses::cpu3.inst 26876 # number of overall misses
2526 system.l2c.overall_misses::cpu3.data 176358 # number of overall misses
2527 system.l2c.overall_misses::total 737562 # number of overall misses
2528 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 56414500 # number of ReadReq miss cycles
2529 system.l2c.ReadReq_miss_latency::cpu1.itb.walker 48383000 # number of ReadReq miss cycles
2530 system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 57823500 # number of ReadReq miss cycles
2531 system.l2c.ReadReq_miss_latency::cpu2.itb.walker 59723000 # number of ReadReq miss cycles
2532 system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 126486500 # number of ReadReq miss cycles
2533 system.l2c.ReadReq_miss_latency::cpu3.itb.walker 121800000 # number of ReadReq miss cycles
2534 system.l2c.ReadReq_miss_latency::total 470630500 # number of ReadReq miss cycles
2535 system.l2c.UpgradeReq_miss_latency::cpu1.data 180440500 # number of UpgradeReq miss cycles
2536 system.l2c.UpgradeReq_miss_latency::cpu2.data 237646000 # number of UpgradeReq miss cycles
2537 system.l2c.UpgradeReq_miss_latency::cpu3.data 390941500 # number of UpgradeReq miss cycles
2538 system.l2c.UpgradeReq_miss_latency::total 809028000 # number of UpgradeReq miss cycles
2539 system.l2c.ReadExReq_miss_latency::cpu1.data 6592113000 # number of ReadExReq miss cycles
2540 system.l2c.ReadExReq_miss_latency::cpu2.data 7946110000 # number of ReadExReq miss cycles
2541 system.l2c.ReadExReq_miss_latency::cpu3.data 14567039000 # number of ReadExReq miss cycles
2542 system.l2c.ReadExReq_miss_latency::total 29105262000 # number of ReadExReq miss cycles
2543 system.l2c.ReadCleanReq_miss_latency::cpu1.inst 923100500 # number of ReadCleanReq miss cycles
2544 system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3124017500 # number of ReadCleanReq miss cycles
2545 system.l2c.ReadCleanReq_miss_latency::cpu3.inst 3653424999 # number of ReadCleanReq miss cycles
2546 system.l2c.ReadCleanReq_miss_latency::total 7700542999 # number of ReadCleanReq miss cycles
2547 system.l2c.ReadSharedReq_miss_latency::cpu1.data 3739908000 # number of ReadSharedReq miss cycles
2548 system.l2c.ReadSharedReq_miss_latency::cpu2.data 5269271500 # number of ReadSharedReq miss cycles
2549 system.l2c.ReadSharedReq_miss_latency::cpu3.data 10960372000 # number of ReadSharedReq miss cycles
2550 system.l2c.ReadSharedReq_miss_latency::total 19969551500 # number of ReadSharedReq miss cycles
2551 system.l2c.InvalidateReq_miss_latency::cpu1.data 2513729500 # number of InvalidateReq miss cycles
2552 system.l2c.InvalidateReq_miss_latency::cpu2.data 3528376000 # number of InvalidateReq miss cycles
2553 system.l2c.InvalidateReq_miss_latency::cpu3.data 7538845500 # number of InvalidateReq miss cycles
2554 system.l2c.InvalidateReq_miss_latency::total 13580951000 # number of InvalidateReq miss cycles
2555 system.l2c.demand_miss_latency::cpu1.dtb.walker 56414500 # number of demand (read+write) miss cycles
2556 system.l2c.demand_miss_latency::cpu1.itb.walker 48383000 # number of demand (read+write) miss cycles
2557 system.l2c.demand_miss_latency::cpu1.inst 923100500 # number of demand (read+write) miss cycles
2558 system.l2c.demand_miss_latency::cpu1.data 10332021000 # number of demand (read+write) miss cycles
2559 system.l2c.demand_miss_latency::cpu2.dtb.walker 57823500 # number of demand (read+write) miss cycles
2560 system.l2c.demand_miss_latency::cpu2.itb.walker 59723000 # number of demand (read+write) miss cycles
2561 system.l2c.demand_miss_latency::cpu2.inst 3124017500 # number of demand (read+write) miss cycles
2562 system.l2c.demand_miss_latency::cpu2.data 13215381500 # number of demand (read+write) miss cycles
2563 system.l2c.demand_miss_latency::cpu3.dtb.walker 126486500 # number of demand (read+write) miss cycles
2564 system.l2c.demand_miss_latency::cpu3.itb.walker 121800000 # number of demand (read+write) miss cycles
2565 system.l2c.demand_miss_latency::cpu3.inst 3653424999 # number of demand (read+write) miss cycles
2566 system.l2c.demand_miss_latency::cpu3.data 25527411000 # number of demand (read+write) miss cycles
2567 system.l2c.demand_miss_latency::total 57245986999 # number of demand (read+write) miss cycles
2568 system.l2c.overall_miss_latency::cpu1.dtb.walker 56414500 # number of overall miss cycles
2569 system.l2c.overall_miss_latency::cpu1.itb.walker 48383000 # number of overall miss cycles
2570 system.l2c.overall_miss_latency::cpu1.inst 923100500 # number of overall miss cycles
2571 system.l2c.overall_miss_latency::cpu1.data 10332021000 # number of overall miss cycles
2572 system.l2c.overall_miss_latency::cpu2.dtb.walker 57823500 # number of overall miss cycles
2573 system.l2c.overall_miss_latency::cpu2.itb.walker 59723000 # number of overall miss cycles
2574 system.l2c.overall_miss_latency::cpu2.inst 3124017500 # number of overall miss cycles
2575 system.l2c.overall_miss_latency::cpu2.data 13215381500 # number of overall miss cycles
2576 system.l2c.overall_miss_latency::cpu3.dtb.walker 126486500 # number of overall miss cycles
2577 system.l2c.overall_miss_latency::cpu3.itb.walker 121800000 # number of overall miss cycles
2578 system.l2c.overall_miss_latency::cpu3.inst 3653424999 # number of overall miss cycles
2579 system.l2c.overall_miss_latency::cpu3.data 25527411000 # number of overall miss cycles
2580 system.l2c.overall_miss_latency::total 57245986999 # number of overall miss cycles
2581 system.l2c.ReadReq_accesses::cpu0.dtb.walker 158799 # number of ReadReq accesses(hits+misses)
2582 system.l2c.ReadReq_accesses::cpu0.itb.walker 109329 # number of ReadReq accesses(hits+misses)
2583 system.l2c.ReadReq_accesses::cpu1.dtb.walker 56961 # number of ReadReq accesses(hits+misses)
2584 system.l2c.ReadReq_accesses::cpu1.itb.walker 42710 # number of ReadReq accesses(hits+misses)
2585 system.l2c.ReadReq_accesses::cpu2.dtb.walker 151138 # number of ReadReq accesses(hits+misses)
2586 system.l2c.ReadReq_accesses::cpu2.itb.walker 58057 # number of ReadReq accesses(hits+misses)
2587 system.l2c.ReadReq_accesses::cpu3.dtb.walker 286459 # number of ReadReq accesses(hits+misses)
2588 system.l2c.ReadReq_accesses::cpu3.itb.walker 109551 # number of ReadReq accesses(hits+misses)
2589 system.l2c.ReadReq_accesses::total 973004 # number of ReadReq accesses(hits+misses)
2590 system.l2c.WritebackDirty_accesses::writebacks 7469710 # number of WritebackDirty accesses(hits+misses)
2591 system.l2c.WritebackDirty_accesses::total 7469710 # number of WritebackDirty accesses(hits+misses)
2592 system.l2c.WritebackClean_accesses::writebacks 15704683 # number of WritebackClean accesses(hits+misses)
2593 system.l2c.WritebackClean_accesses::total 15704683 # number of WritebackClean accesses(hits+misses)
2594 system.l2c.UpgradeReq_accesses::cpu0.data 17822 # number of UpgradeReq accesses(hits+misses)
2595 system.l2c.UpgradeReq_accesses::cpu1.data 5851 # number of UpgradeReq accesses(hits+misses)
2596 system.l2c.UpgradeReq_accesses::cpu2.data 7363 # number of UpgradeReq accesses(hits+misses)
2597 system.l2c.UpgradeReq_accesses::cpu3.data 12094 # number of UpgradeReq accesses(hits+misses)
2598 system.l2c.UpgradeReq_accesses::total 43130 # number of UpgradeReq accesses(hits+misses)
2599 system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
2600 system.l2c.SCUpgradeReq_accesses::cpu3.data 1 # number of SCUpgradeReq accesses(hits+misses)
2601 system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
2602 system.l2c.ReadExReq_accesses::cpu0.data 821231 # number of ReadExReq accesses(hits+misses)
2603 system.l2c.ReadExReq_accesses::cpu1.data 248108 # number of ReadExReq accesses(hits+misses)
2604 system.l2c.ReadExReq_accesses::cpu2.data 325794 # number of ReadExReq accesses(hits+misses)
2605 system.l2c.ReadExReq_accesses::cpu3.data 572717 # number of ReadExReq accesses(hits+misses)
2606 system.l2c.ReadExReq_accesses::total 1967850 # number of ReadExReq accesses(hits+misses)
2607 system.l2c.ReadCleanReq_accesses::cpu0.inst 5563199 # number of ReadCleanReq accesses(hits+misses)
2608 system.l2c.ReadCleanReq_accesses::cpu1.inst 1667816 # number of ReadCleanReq accesses(hits+misses)
2609 system.l2c.ReadCleanReq_accesses::cpu2.inst 3866259 # number of ReadCleanReq accesses(hits+misses)
2610 system.l2c.ReadCleanReq_accesses::cpu3.inst 4610338 # number of ReadCleanReq accesses(hits+misses)
2611 system.l2c.ReadCleanReq_accesses::total 15707612 # number of ReadCleanReq accesses(hits+misses)
2612 system.l2c.ReadSharedReq_accesses::cpu0.data 2605721 # number of ReadSharedReq accesses(hits+misses)
2613 system.l2c.ReadSharedReq_accesses::cpu1.data 824677 # number of ReadSharedReq accesses(hits+misses)
2614 system.l2c.ReadSharedReq_accesses::cpu2.data 1090237 # number of ReadSharedReq accesses(hits+misses)
2615 system.l2c.ReadSharedReq_accesses::cpu3.data 1938030 # number of ReadSharedReq accesses(hits+misses)
2616 system.l2c.ReadSharedReq_accesses::total 6458665 # number of ReadSharedReq accesses(hits+misses)
2617 system.l2c.InvalidateReq_accesses::cpu0.data 686647 # number of InvalidateReq accesses(hits+misses)
2618 system.l2c.InvalidateReq_accesses::cpu1.data 108408 # number of InvalidateReq accesses(hits+misses)
2619 system.l2c.InvalidateReq_accesses::cpu2.data 151026 # number of InvalidateReq accesses(hits+misses)
2620 system.l2c.InvalidateReq_accesses::cpu3.data 277750 # number of InvalidateReq accesses(hits+misses)
2621 system.l2c.InvalidateReq_accesses::total 1223831 # number of InvalidateReq accesses(hits+misses)
2622 system.l2c.demand_accesses::cpu0.dtb.walker 158799 # number of demand (read+write) accesses
2623 system.l2c.demand_accesses::cpu0.itb.walker 109329 # number of demand (read+write) accesses
2624 system.l2c.demand_accesses::cpu0.inst 5563199 # number of demand (read+write) accesses
2625 system.l2c.demand_accesses::cpu0.data 3426952 # number of demand (read+write) accesses
2626 system.l2c.demand_accesses::cpu1.dtb.walker 56961 # number of demand (read+write) accesses
2627 system.l2c.demand_accesses::cpu1.itb.walker 42710 # number of demand (read+write) accesses
2628 system.l2c.demand_accesses::cpu1.inst 1667816 # number of demand (read+write) accesses
2629 system.l2c.demand_accesses::cpu1.data 1072785 # number of demand (read+write) accesses
2630 system.l2c.demand_accesses::cpu2.dtb.walker 151138 # number of demand (read+write) accesses
2631 system.l2c.demand_accesses::cpu2.itb.walker 58057 # number of demand (read+write) accesses
2632 system.l2c.demand_accesses::cpu2.inst 3866259 # number of demand (read+write) accesses
2633 system.l2c.demand_accesses::cpu2.data 1416031 # number of demand (read+write) accesses
2634 system.l2c.demand_accesses::cpu3.dtb.walker 286459 # number of demand (read+write) accesses
2635 system.l2c.demand_accesses::cpu3.itb.walker 109551 # number of demand (read+write) accesses
2636 system.l2c.demand_accesses::cpu3.inst 4610338 # number of demand (read+write) accesses
2637 system.l2c.demand_accesses::cpu3.data 2510747 # number of demand (read+write) accesses
2638 system.l2c.demand_accesses::total 25107131 # number of demand (read+write) accesses
2639 system.l2c.overall_accesses::cpu0.dtb.walker 158799 # number of overall (read+write) accesses
2640 system.l2c.overall_accesses::cpu0.itb.walker 109329 # number of overall (read+write) accesses
2641 system.l2c.overall_accesses::cpu0.inst 5563199 # number of overall (read+write) accesses
2642 system.l2c.overall_accesses::cpu0.data 3426952 # number of overall (read+write) accesses
2643 system.l2c.overall_accesses::cpu1.dtb.walker 56961 # number of overall (read+write) accesses
2644 system.l2c.overall_accesses::cpu1.itb.walker 42710 # number of overall (read+write) accesses
2645 system.l2c.overall_accesses::cpu1.inst 1667816 # number of overall (read+write) accesses
2646 system.l2c.overall_accesses::cpu1.data 1072785 # number of overall (read+write) accesses
2647 system.l2c.overall_accesses::cpu2.dtb.walker 151138 # number of overall (read+write) accesses
2648 system.l2c.overall_accesses::cpu2.itb.walker 58057 # number of overall (read+write) accesses
2649 system.l2c.overall_accesses::cpu2.inst 3866259 # number of overall (read+write) accesses
2650 system.l2c.overall_accesses::cpu2.data 1416031 # number of overall (read+write) accesses
2651 system.l2c.overall_accesses::cpu3.dtb.walker 286459 # number of overall (read+write) accesses
2652 system.l2c.overall_accesses::cpu3.itb.walker 109551 # number of overall (read+write) accesses
2653 system.l2c.overall_accesses::cpu3.inst 4610338 # number of overall (read+write) accesses
2654 system.l2c.overall_accesses::cpu3.data 2510747 # number of overall (read+write) accesses
2655 system.l2c.overall_accesses::total 25107131 # number of overall (read+write) accesses
2656 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.007884 # miss rate for ReadReq accesses
2657 system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012238 # miss rate for ReadReq accesses
2658 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.007391 # miss rate for ReadReq accesses
2659 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.008242 # miss rate for ReadReq accesses
2660 system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002792 # miss rate for ReadReq accesses
2661 system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.007579 # miss rate for ReadReq accesses
2662 system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003226 # miss rate for ReadReq accesses
2663 system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.008142 # miss rate for ReadReq accesses
2664 system.l2c.ReadReq_miss_rate::total 0.006209 # miss rate for ReadReq accesses
2665 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784031 # miss rate for UpgradeReq accesses
2666 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.777987 # miss rate for UpgradeReq accesses
2667 system.l2c.UpgradeReq_miss_rate::cpu2.data 0.790031 # miss rate for UpgradeReq accesses
2668 system.l2c.UpgradeReq_miss_rate::cpu3.data 0.778981 # miss rate for UpgradeReq accesses
2669 system.l2c.UpgradeReq_miss_rate::total 0.782819 # miss rate for UpgradeReq accesses
2670 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
2671 system.l2c.SCUpgradeReq_miss_rate::cpu3.data 1 # miss rate for SCUpgradeReq accesses
2672 system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2673 system.l2c.ReadExReq_miss_rate::cpu0.data 0.217292 # miss rate for ReadExReq accesses
2674 system.l2c.ReadExReq_miss_rate::cpu1.data 0.202376 # miss rate for ReadExReq accesses
2675 system.l2c.ReadExReq_miss_rate::cpu2.data 0.185316 # miss rate for ReadExReq accesses
2676 system.l2c.ReadExReq_miss_rate::cpu3.data 0.172361 # miss rate for ReadExReq accesses
2677 system.l2c.ReadExReq_miss_rate::total 0.197041 # miss rate for ReadExReq accesses
2678 system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006336 # miss rate for ReadCleanReq accesses
2679 system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004204 # miss rate for ReadCleanReq accesses
2680 system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006046 # miss rate for ReadCleanReq accesses
2681 system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.005830 # miss rate for ReadCleanReq accesses
2682 system.l2c.ReadCleanReq_miss_rate::total 0.005890 # miss rate for ReadCleanReq accesses
2683 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.040812 # miss rate for ReadSharedReq accesses
2684 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.034109 # miss rate for ReadSharedReq accesses
2685 system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.035907 # miss rate for ReadSharedReq accesses
2686 system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.040063 # miss rate for ReadSharedReq accesses
2687 system.l2c.ReadSharedReq_miss_rate::total 0.038903 # miss rate for ReadSharedReq accesses
2688 system.l2c.InvalidateReq_miss_rate::cpu0.data 0.578733 # miss rate for InvalidateReq accesses
2689 system.l2c.InvalidateReq_miss_rate::cpu1.data 0.176758 # miss rate for InvalidateReq accesses
2690 system.l2c.InvalidateReq_miss_rate::cpu2.data 0.167428 # miss rate for InvalidateReq accesses
2691 system.l2c.InvalidateReq_miss_rate::cpu3.data 0.175543 # miss rate for InvalidateReq accesses
2692 system.l2c.InvalidateReq_miss_rate::total 0.400864 # miss rate for InvalidateReq accesses
2693 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007884 # miss rate for demand accesses
2694 system.l2c.demand_miss_rate::cpu0.itb.walker 0.012238 # miss rate for demand accesses
2695 system.l2c.demand_miss_rate::cpu0.inst 0.006336 # miss rate for demand accesses
2696 system.l2c.demand_miss_rate::cpu0.data 0.083103 # miss rate for demand accesses
2697 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.007391 # miss rate for demand accesses
2698 system.l2c.demand_miss_rate::cpu1.itb.walker 0.008242 # miss rate for demand accesses
2699 system.l2c.demand_miss_rate::cpu1.inst 0.004204 # miss rate for demand accesses
2700 system.l2c.demand_miss_rate::cpu1.data 0.073025 # miss rate for demand accesses
2701 system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002792 # miss rate for demand accesses
2702 system.l2c.demand_miss_rate::cpu2.itb.walker 0.007579 # miss rate for demand accesses
2703 system.l2c.demand_miss_rate::cpu2.inst 0.006046 # miss rate for demand accesses
2704 system.l2c.demand_miss_rate::cpu2.data 0.070282 # miss rate for demand accesses
2705 system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003226 # miss rate for demand accesses
2706 system.l2c.demand_miss_rate::cpu3.itb.walker 0.008142 # miss rate for demand accesses
2707 system.l2c.demand_miss_rate::cpu3.inst 0.005830 # miss rate for demand accesses
2708 system.l2c.demand_miss_rate::cpu3.data 0.070241 # miss rate for demand accesses
2709 system.l2c.demand_miss_rate::total 0.029377 # miss rate for demand accesses
2710 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007884 # miss rate for overall accesses
2711 system.l2c.overall_miss_rate::cpu0.itb.walker 0.012238 # miss rate for overall accesses
2712 system.l2c.overall_miss_rate::cpu0.inst 0.006336 # miss rate for overall accesses
2713 system.l2c.overall_miss_rate::cpu0.data 0.083103 # miss rate for overall accesses
2714 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.007391 # miss rate for overall accesses
2715 system.l2c.overall_miss_rate::cpu1.itb.walker 0.008242 # miss rate for overall accesses
2716 system.l2c.overall_miss_rate::cpu1.inst 0.004204 # miss rate for overall accesses
2717 system.l2c.overall_miss_rate::cpu1.data 0.073025 # miss rate for overall accesses
2718 system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002792 # miss rate for overall accesses
2719 system.l2c.overall_miss_rate::cpu2.itb.walker 0.007579 # miss rate for overall accesses
2720 system.l2c.overall_miss_rate::cpu2.inst 0.006046 # miss rate for overall accesses
2721 system.l2c.overall_miss_rate::cpu2.data 0.070282 # miss rate for overall accesses
2722 system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003226 # miss rate for overall accesses
2723 system.l2c.overall_miss_rate::cpu3.itb.walker 0.008142 # miss rate for overall accesses
2724 system.l2c.overall_miss_rate::cpu3.inst 0.005830 # miss rate for overall accesses
2725 system.l2c.overall_miss_rate::cpu3.data 0.070241 # miss rate for overall accesses
2726 system.l2c.overall_miss_rate::total 0.029377 # miss rate for overall accesses
2727 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134001.187648 # average ReadReq miss latency
2728 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137451.704545 # average ReadReq miss latency
2729 system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 137022.511848 # average ReadReq miss latency
2730 system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 135734.090909 # average ReadReq miss latency
2731 system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 136890.151515 # average ReadReq miss latency
2732 system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 136547.085202 # average ReadReq miss latency
2733 system.l2c.ReadReq_avg_miss_latency::total 77906.058600 # average ReadReq miss latency
2734 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39639.828647 # average UpgradeReq miss latency
2735 system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 40853.704659 # average UpgradeReq miss latency
2736 system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 41496.815625 # average UpgradeReq miss latency
2737 system.l2c.UpgradeReq_avg_miss_latency::total 23961.970204 # average UpgradeReq miss latency
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2740 system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147568.115971 # average ReadExReq miss latency
2741 system.l2c.ReadExReq_avg_miss_latency::total 75062.507253 # average ReadExReq miss latency
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2743 system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133642.090178 # average ReadCleanReq miss latency
2744 system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 135936.337215 # average ReadCleanReq miss latency
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2748 system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141161.866983 # average ReadSharedReq miss latency
2749 system.l2c.ReadSharedReq_avg_miss_latency::total 79476.373456 # average ReadSharedReq miss latency
2750 system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 131183.044567 # average InvalidateReq miss latency
2751 system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 139538.717077 # average InvalidateReq miss latency
2752 system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 154620.782657 # average InvalidateReq miss latency
2753 system.l2c.InvalidateReq_avg_miss_latency::total 27682.894066 # average InvalidateReq miss latency
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2755 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137451.704545 # average overall miss latency
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2759 system.l2c.demand_avg_miss_latency::cpu2.itb.walker 135734.090909 # average overall miss latency
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2763 system.l2c.demand_avg_miss_latency::cpu3.itb.walker 136547.085202 # average overall miss latency
2764 system.l2c.demand_avg_miss_latency::cpu3.inst 135936.337215 # average overall miss latency
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2767 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134001.187648 # average overall miss latency
2768 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137451.704545 # average overall miss latency
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2772 system.l2c.overall_avg_miss_latency::cpu2.itb.walker 135734.090909 # average overall miss latency
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2776 system.l2c.overall_avg_miss_latency::cpu3.itb.walker 136547.085202 # average overall miss latency
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2781 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2785 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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2874 system.l2c.overall_mshr_uncacheable_misses::cpu2.data 13394 # number of overall MSHR uncacheable misses
2875 system.l2c.overall_mshr_uncacheable_misses::cpu3.data 14057 # number of overall MSHR uncacheable misses
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2882 system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 111660000 # number of ReadReq MSHR miss cycles
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2901 system.l2c.ReadSharedReq_mshr_miss_latency::total 18519710001 # number of ReadSharedReq MSHR miss cycles
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2903 system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 3275516000 # number of InvalidateReq MSHR miss cycles
2904 system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 7051275500 # number of InvalidateReq MSHR miss cycles
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2906 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 52204500 # number of demand (read+write) MSHR miss cycles
2907 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 44863000 # number of demand (read+write) MSHR miss cycles
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2919 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 52204500 # number of overall MSHR miss cycles
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2921 system.l2c.overall_mshr_miss_latency::cpu1.inst 852990500 # number of overall MSHR miss cycles
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2932 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1276511500 # number of ReadReq MSHR uncacheable cycles
2933 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1279406000 # number of ReadReq MSHR uncacheable cycles
2934 system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1278862500 # number of ReadReq MSHR uncacheable cycles
2935 system.l2c.ReadReq_mshr_uncacheable_latency::total 3834780000 # number of ReadReq MSHR uncacheable cycles
2936 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1229770000 # number of WriteReq MSHR uncacheable cycles
2937 system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1230900500 # number of WriteReq MSHR uncacheable cycles
2938 system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1262767998 # number of WriteReq MSHR uncacheable cycles
2939 system.l2c.WriteReq_mshr_uncacheable_latency::total 3723438498 # number of WriteReq MSHR uncacheable cycles
2940 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2506281500 # number of overall MSHR uncacheable cycles
2941 system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2510306500 # number of overall MSHR uncacheable cycles
2942 system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2541630498 # number of overall MSHR uncacheable cycles
2943 system.l2c.overall_mshr_uncacheable_latency::total 7558218498 # number of overall MSHR uncacheable cycles
2944 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007391 # mshr miss rate for ReadReq accesses
2945 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.008242 # mshr miss rate for ReadReq accesses
2946 system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002792 # mshr miss rate for ReadReq accesses
2947 system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.007579 # mshr miss rate for ReadReq accesses
2948 system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003219 # mshr miss rate for ReadReq accesses
2949 system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008042 # mshr miss rate for ReadReq accesses
2950 system.l2c.ReadReq_mshr_miss_rate::total 0.003533 # mshr miss rate for ReadReq accesses
2951 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.777987 # mshr miss rate for UpgradeReq accesses
2952 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.790031 # mshr miss rate for UpgradeReq accesses
2953 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.778981 # mshr miss rate for UpgradeReq accesses
2954 system.l2c.UpgradeReq_mshr_miss_rate::total 0.458845 # mshr miss rate for UpgradeReq accesses
2955 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for SCUpgradeReq accesses
2956 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
2957 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.202376 # mshr miss rate for ReadExReq accesses
2958 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.185316 # mshr miss rate for ReadExReq accesses
2959 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.172361 # mshr miss rate for ReadExReq accesses
2960 system.l2c.ReadExReq_mshr_miss_rate::total 0.106360 # mshr miss rate for ReadExReq accesses
2961 system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.004204 # mshr miss rate for ReadCleanReq accesses
2962 system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006046 # mshr miss rate for ReadCleanReq accesses
2963 system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005829 # mshr miss rate for ReadCleanReq accesses
2964 system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003645 # mshr miss rate for ReadCleanReq accesses
2965 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034109 # mshr miss rate for ReadSharedReq accesses
2966 system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.035902 # mshr miss rate for ReadSharedReq accesses
2967 system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.040062 # mshr miss rate for ReadSharedReq accesses
2968 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.022437 # mshr miss rate for ReadSharedReq accesses
2969 system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.176758 # mshr miss rate for InvalidateReq accesses
2970 system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.167428 # mshr miss rate for InvalidateReq accesses
2971 system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.175543 # mshr miss rate for InvalidateReq accesses
2972 system.l2c.InvalidateReq_mshr_miss_rate::total 0.076158 # mshr miss rate for InvalidateReq accesses
2973 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007391 # mshr miss rate for demand accesses
2974 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.008242 # mshr miss rate for demand accesses
2975 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004204 # mshr miss rate for demand accesses
2976 system.l2c.demand_mshr_miss_rate::cpu1.data 0.073025 # mshr miss rate for demand accesses
2977 system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002792 # mshr miss rate for demand accesses
2978 system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007579 # mshr miss rate for demand accesses
2979 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006046 # mshr miss rate for demand accesses
2980 system.l2c.demand_mshr_miss_rate::cpu2.data 0.070279 # mshr miss rate for demand accesses
2981 system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003219 # mshr miss rate for demand accesses
2982 system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008042 # mshr miss rate for demand accesses
2983 system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005829 # mshr miss rate for demand accesses
2984 system.l2c.demand_mshr_miss_rate::cpu3.data 0.070240 # mshr miss rate for demand accesses
2985 system.l2c.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses
2986 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007391 # mshr miss rate for overall accesses
2987 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.008242 # mshr miss rate for overall accesses
2988 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004204 # mshr miss rate for overall accesses
2989 system.l2c.overall_mshr_miss_rate::cpu1.data 0.073025 # mshr miss rate for overall accesses
2990 system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002792 # mshr miss rate for overall accesses
2991 system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007579 # mshr miss rate for overall accesses
2992 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006046 # mshr miss rate for overall accesses
2993 system.l2c.overall_mshr_miss_rate::cpu2.data 0.070279 # mshr miss rate for overall accesses
2994 system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003219 # mshr miss rate for overall accesses
2995 system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008042 # mshr miss rate for overall accesses
2996 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005829 # mshr miss rate for overall accesses
2997 system.l2c.overall_mshr_miss_rate::cpu3.data 0.070240 # mshr miss rate for overall accesses
2998 system.l2c.overall_mshr_miss_rate::total 0.016526 # mshr miss rate for overall accesses
2999 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648 # average ReadReq mshr miss latency
3000 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545 # average ReadReq mshr miss latency
3001 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848 # average ReadReq mshr miss latency
3002 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909 # average ReadReq mshr miss latency
3003 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607 # average ReadReq mshr miss latency
3004 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252 # average ReadReq mshr miss latency
3005 system.l2c.ReadReq_avg_mshr_miss_latency::total 126448.662304 # average ReadReq mshr miss latency
3006 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67943.760984 # average UpgradeReq mshr miss latency
3007 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68004.641568 # average UpgradeReq mshr miss latency
3008 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68003.715105 # average UpgradeReq mshr miss latency
3009 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67990.197069 # average UpgradeReq mshr miss latency
3010 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 69500 # average SCUpgradeReq mshr miss latency
3011 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
3012 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121288.223696 # average ReadExReq mshr miss latency
3013 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 121612.571462 # average ReadExReq mshr miss latency
3014 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137568.095751 # average ReadExReq mshr miss latency
3015 system.l2c.ReadExReq_avg_mshr_miss_latency::total 129060.004806 # average ReadExReq mshr miss latency
3016 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121664.598488 # average ReadCleanReq mshr miss latency
3017 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123642.090178 # average ReadCleanReq mshr miss latency
3018 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125940.353712 # average ReadCleanReq mshr miss latency
3019 system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124478.624673 # average ReadCleanReq mshr miss latency
3020 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122955.597426 # average ReadSharedReq mshr miss latency
3021 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124607.135558 # average ReadSharedReq mshr miss latency
3022 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131162.508707 # average ReadSharedReq mshr miss latency
3023 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127798.817228 # average ReadSharedReq mshr miss latency
3024 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121183.044567 # average InvalidateReq mshr miss latency
3025 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129538.717077 # average InvalidateReq mshr miss latency
3026 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 144620.782657 # average InvalidateReq mshr miss latency
3027 system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135710.541280 # average InvalidateReq mshr miss latency
3028 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648 # average overall mshr miss latency
3029 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545 # average overall mshr miss latency
3030 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121664.598488 # average overall mshr miss latency
3031 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121886.916007 # average overall mshr miss latency
3032 system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848 # average overall mshr miss latency
3033 system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909 # average overall mshr miss latency
3034 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123642.090178 # average overall mshr miss latency
3035 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122790.392616 # average overall mshr miss latency
3036 system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607 # average overall mshr miss latency
3037 system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252 # average overall mshr miss latency
3038 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125940.353712 # average overall mshr miss latency
3039 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134747.989890 # average overall mshr miss latency
3040 system.l2c.demand_avg_mshr_miss_latency::total 127965.608487 # average overall mshr miss latency
3041 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648 # average overall mshr miss latency
3042 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545 # average overall mshr miss latency
3043 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121664.598488 # average overall mshr miss latency
3044 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121886.916007 # average overall mshr miss latency
3045 system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848 # average overall mshr miss latency
3046 system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909 # average overall mshr miss latency
3047 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123642.090178 # average overall mshr miss latency
3048 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122790.392616 # average overall mshr miss latency
3049 system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607 # average overall mshr miss latency
3050 system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252 # average overall mshr miss latency
3051 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125940.353712 # average overall mshr miss latency
3052 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134747.989890 # average overall mshr miss latency
3053 system.l2c.overall_avg_mshr_miss_latency::total 127965.608487 # average overall mshr miss latency
3054 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184921.266116 # average ReadReq mshr uncacheable latency
3055 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184405.592390 # average ReadReq mshr uncacheable latency
3056 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178362.970711 # average ReadReq mshr uncacheable latency
3057 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182512.969397 # average ReadReq mshr uncacheable latency
3058 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192061.533656 # average WriteReq mshr uncacheable latency
3059 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190659.928748 # average WriteReq mshr uncacheable latency
3060 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183355.306810 # average WriteReq mshr uncacheable latency
3061 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188566.722273 # average WriteReq mshr uncacheable latency
3062 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188357.244852 # average overall mshr uncacheable latency
3063 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187420.225474 # average overall mshr uncacheable latency
3064 system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 180808.885111 # average overall mshr uncacheable latency
3065 system.l2c.overall_avg_mshr_uncacheable_latency::total 185445.898815 # average overall mshr uncacheable latency
3066 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3067 system.membus.trans_dist::ReadReq 76702 # Transaction distribution
3068 system.membus.trans_dist::ReadResp 435346 # Transaction distribution
3069 system.membus.trans_dist::WriteReq 33616 # Transaction distribution
3070 system.membus.trans_dist::WriteResp 33616 # Transaction distribution
3071 system.membus.trans_dist::WritebackDirty 1053198 # Transaction distribution
3072 system.membus.trans_dist::CleanEvict 195936 # Transaction distribution
3073 system.membus.trans_dist::UpgradeReq 34438 # Transaction distribution
3074 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
3075 system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution
3076 system.membus.trans_dist::ReadExReq 877665 # Transaction distribution
3077 system.membus.trans_dist::ReadExResp 877665 # Transaction distribution
3078 system.membus.trans_dist::ReadSharedReq 358644 # Transaction distribution
3079 system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
3080 system.membus.trans_dist::InvalidateResp 56664 # Transaction distribution
3081 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122464 # Packet count per connected master and slave (bytes)
3082 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
3083 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6736 # Packet count per connected master and slave (bytes)
3084 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3728417 # Packet count per connected master and slave (bytes)
3085 system.membus.pkt_count_system.l2c.mem_side::total 3857678 # Packet count per connected master and slave (bytes)
3086 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295106 # Packet count per connected master and slave (bytes)
3087 system.membus.pkt_count_system.iocache.mem_side::total 295106 # Packet count per connected master and slave (bytes)
3088 system.membus.pkt_count::total 4152784 # Packet count per connected master and slave (bytes)
3089 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes)
3090 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
3091 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13472 # Cumulative packet size per connected master and slave (bytes)
3092 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139314336 # Cumulative packet size per connected master and slave (bytes)
3093 system.membus.pkt_size_system.l2c.mem_side::total 139483644 # Cumulative packet size per connected master and slave (bytes)
3094 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302016 # Cumulative packet size per connected master and slave (bytes)
3095 system.membus.pkt_size_system.iocache.mem_side::total 7302016 # Cumulative packet size per connected master and slave (bytes)
3096 system.membus.pkt_size::total 146785660 # Cumulative packet size per connected master and slave (bytes)
3097 system.membus.snoops 1643 # Total snoops (count)
3098 system.membus.snoop_fanout::samples 2736894 # Request fanout histogram
3099 system.membus.snoop_fanout::mean 1 # Request fanout histogram
3100 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3101 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3102 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3103 system.membus.snoop_fanout::1 2736894 100.00% 100.00% # Request fanout histogram
3104 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3105 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3106 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3107 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3108 system.membus.snoop_fanout::total 2736894 # Request fanout histogram
3109 system.membus.reqLayer0.occupancy 69642000 # Layer occupancy (ticks)
3110 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3111 system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
3112 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3113 system.membus.reqLayer2.occupancy 1869502 # Layer occupancy (ticks)
3114 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3115 system.membus.reqLayer5.occupancy 3024540179 # Layer occupancy (ticks)
3116 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3117 system.membus.respLayer2.occupancy 2745498213 # Layer occupancy (ticks)
3118 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3119 system.membus.respLayer3.occupancy 28895247 # Layer occupancy (ticks)
3120 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3121 system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3122 system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3123 system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3124 system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3125 system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3126 system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3127 system.realview.ethernet.txBytes 966 # Bytes Transmitted
3128 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3129 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3130 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3131 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3132 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3133 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3134 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3135 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3136 system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
3137 system.realview.ethernet.totPackets 3 # Total Packets
3138 system.realview.ethernet.totBytes 966 # Total Bytes
3139 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
3140 system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
3141 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
3142 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3143 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
3144 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3145 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
3146 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
3147 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
3148 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
3149 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
3150 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
3151 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
3152 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
3153 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
3154 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
3155 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
3156 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
3157 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
3158 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
3159 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
3160 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
3161 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3162 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3163 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3164 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3165 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3166 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3167 system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
3168 system.realview.ethernet.droppedPackets 0 # number of packets dropped
3169 system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3170 system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3171 system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3172 system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3173 system.toL2Bus.snoop_filter.tot_requests 51377281 # Total number of requests made to the snoop filter.
3174 system.toL2Bus.snoop_filter.hit_single_requests 26019251 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3175 system.toL2Bus.snoop_filter.hit_multi_requests 2963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3176 system.toL2Bus.snoop_filter.tot_snoops 1998 # Total number of snoops made to the snoop filter.
3177 system.toL2Bus.snoop_filter.hit_single_snoops 1998 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3178 system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3179 system.toL2Bus.trans_dist::ReadReq 1480293 # Transaction distribution
3180 system.toL2Bus.trans_dist::ReadResp 23646990 # Transaction distribution
3181 system.toL2Bus.trans_dist::WriteReq 33616 # Transaction distribution
3182 system.toL2Bus.trans_dist::WriteResp 33616 # Transaction distribution
3183 system.toL2Bus.trans_dist::WritebackDirty 7917317 # Transaction distribution
3184 system.toL2Bus.trans_dist::WritebackClean 15707105 # Transaction distribution
3185 system.toL2Bus.trans_dist::CleanEvict 2286569 # Transaction distribution
3186 system.toL2Bus.trans_dist::UpgradeReq 43130 # Transaction distribution
3187 system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
3188 system.toL2Bus.trans_dist::UpgradeResp 43132 # Transaction distribution
3189 system.toL2Bus.trans_dist::ReadExReq 1967850 # Transaction distribution
3190 system.toL2Bus.trans_dist::ReadExResp 1967850 # Transaction distribution
3191 system.toL2Bus.trans_dist::ReadCleanReq 15707694 # Transaction distribution
3192 system.toL2Bus.trans_dist::ReadSharedReq 6464392 # Transaction distribution
3193 system.toL2Bus.trans_dist::InvalidateReq 1273831 # Transaction distribution
3194 system.toL2Bus.trans_dist::InvalidateResp 1223831 # Transaction distribution
3195 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47208661 # Packet count per connected master and slave (bytes)
3196 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29171496 # Packet count per connected master and slave (bytes)
3197 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 814900 # Packet count per connected master and slave (bytes)
3198 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1708889 # Packet count per connected master and slave (bytes)
3199 system.toL2Bus.pkt_count::total 78903946 # Packet count per connected master and slave (bytes)
3200 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2010714388 # Cumulative packet size per connected master and slave (bytes)
3201 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1017569896 # Cumulative packet size per connected master and slave (bytes)
3202 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2939088 # Cumulative packet size per connected master and slave (bytes)
3203 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6022496 # Cumulative packet size per connected master and slave (bytes)
3204 system.toL2Bus.pkt_size::total 3037245868 # Cumulative packet size per connected master and slave (bytes)
3205 system.toL2Bus.snoops 1649773 # Total snoops (count)
3206 system.toL2Bus.snoop_fanout::samples 37956541 # Request fanout histogram
3207 system.toL2Bus.snoop_fanout::mean 0.016464 # Request fanout histogram
3208 system.toL2Bus.snoop_fanout::stdev 0.127251 # Request fanout histogram
3209 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3210 system.toL2Bus.snoop_fanout::0 37331626 98.35% 98.35% # Request fanout histogram
3211 system.toL2Bus.snoop_fanout::1 624915 1.65% 100.00% # Request fanout histogram
3212 system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3213 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3214 system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3215 system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
3216 system.toL2Bus.snoop_fanout::total 37956541 # Request fanout histogram
3217 system.toL2Bus.reqLayer0.occupancy 30638283989 # Layer occupancy (ticks)
3218 system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
3219 system.toL2Bus.snoopLayer0.occupancy 663187 # Layer occupancy (ticks)
3220 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3221 system.toL2Bus.respLayer0.occupancy 15222114677 # Layer occupancy (ticks)
3222 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3223 system.toL2Bus.respLayer1.occupancy 7813255878 # Layer occupancy (ticks)
3224 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3225 system.toL2Bus.respLayer2.occupancy 290580214 # Layer occupancy (ticks)
3226 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
3227 system.toL2Bus.respLayer3.occupancy 698608876 # Layer occupancy (ticks)
3228 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
3229 system.cpu3.kern.inst.arm 0 # number of arm instructions executed
3230 system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
3232 ---------- End Simulation Statistics ----------
projects / gem5.git / blob