2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 51.832615 # Number of seconds simulated
4 sim_ticks 51832614542500 # Number of ticks simulated
5 final_tick 51832614542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 636228 # Simulator instruction rate (inst/s)
8 host_op_rate 747615 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 37416431352 # Simulator tick rate (ticks/s)
10 host_mem_usage 669888 # Number of bytes of host memory used
11 host_seconds 1385.29 # Real time elapsed on the host
12 sim_insts 881360160 # Number of instructions simulated
13 sim_ops 1035663034 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu0.dtb.walker 134080 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 130496 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 2944516 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 40297840 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.dtb.walker 118912 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.itb.walker 116992 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu1.inst 2475952 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu1.data 40549336 # Number of bytes read from this memory
24 system.physmem.bytes_read::realview.ide 378752 # Number of bytes read from this memory
25 system.physmem.bytes_read::total 87146876 # Number of bytes read from this memory
26 system.physmem.bytes_inst_read::cpu0.inst 2944516 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::cpu1.inst 2475952 # Number of instructions bytes read from this memory
28 system.physmem.bytes_inst_read::total 5420468 # Number of instructions bytes read from this memory
29 system.physmem.bytes_written::writebacks 75611328 # Number of bytes written to this memory
30 system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory
31 system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory
32 system.physmem.bytes_written::total 75631908 # Number of bytes written to this memory
33 system.physmem.num_reads::cpu0.dtb.walker 2095 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu0.itb.walker 2039 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu0.inst 70534 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.data 629657 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu1.dtb.walker 1858 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu1.itb.walker 1828 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu1.inst 54568 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu1.data 633593 # Number of read requests responded to by this memory
41 system.physmem.num_reads::realview.ide 5918 # Number of read requests responded to by this memory
42 system.physmem.num_reads::total 1402090 # Number of read requests responded to by this memory
43 system.physmem.num_writes::writebacks 1181427 # Number of write requests responded to by this memory
44 system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory
45 system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory
46 system.physmem.num_writes::total 1184000 # Number of write requests responded to by this memory
47 system.physmem.bw_read::cpu0.dtb.walker 2587 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::cpu0.itb.walker 2518 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_read::cpu0.inst 56808 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu0.data 777461 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::cpu1.dtb.walker 2294 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu1.itb.walker 2257 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu1.inst 47768 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu1.data 782313 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::realview.ide 7307 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::total 1681314 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_inst_read::cpu0.inst 56808 # Instruction read bandwidth from this memory (bytes/s)
58 system.physmem.bw_inst_read::cpu1.inst 47768 # Instruction read bandwidth from this memory (bytes/s)
59 system.physmem.bw_inst_read::total 104576 # Instruction read bandwidth from this memory (bytes/s)
60 system.physmem.bw_write::writebacks 1458760 # Write bandwidth from this memory (bytes/s)
61 system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s)
62 system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s)
63 system.physmem.bw_write::total 1459157 # Write bandwidth from this memory (bytes/s)
64 system.physmem.bw_total::writebacks 1458760 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.bw_total::cpu0.dtb.walker 2587 # Total bandwidth to/from this memory (bytes/s)
66 system.physmem.bw_total::cpu0.itb.walker 2518 # Total bandwidth to/from this memory (bytes/s)
67 system.physmem.bw_total::cpu0.inst 56808 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::cpu0.data 777461 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.bw_total::cpu1.dtb.walker 2294 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu1.itb.walker 2257 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu1.inst 47768 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu1.data 782710 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::realview.ide 7307 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::total 3140470 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.readReqs 1402090 # Number of read requests accepted
76 system.physmem.writeReqs 1184000 # Number of write requests accepted
77 system.physmem.readBursts 1402090 # Number of DRAM read bursts, including those serviced by the write queue
78 system.physmem.writeBursts 1184000 # Number of DRAM write bursts, including those merged in the write queue
79 system.physmem.bytesReadDRAM 89692096 # Total number of bytes read from DRAM
80 system.physmem.bytesReadWrQ 41664 # Total number of bytes read from write queue
81 system.physmem.bytesWritten 75632192 # Total number of bytes written to DRAM
82 system.physmem.bytesReadSys 87146876 # Total read bytes from the system interface side
83 system.physmem.bytesWrittenSys 75631908 # Total written bytes from the system interface side
84 system.physmem.servicedByWrQ 651 # Number of DRAM read bursts serviced by the write queue
85 system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
86 system.physmem.neitherReadNorWriteReqs 142152 # Number of requests that are neither read nor write
87 system.physmem.perBankRdBursts::0 86151 # Per bank write bursts
88 system.physmem.perBankRdBursts::1 87375 # Per bank write bursts
89 system.physmem.perBankRdBursts::2 80357 # Per bank write bursts
90 system.physmem.perBankRdBursts::3 81721 # Per bank write bursts
91 system.physmem.perBankRdBursts::4 87059 # Per bank write bursts
92 system.physmem.perBankRdBursts::5 94652 # Per bank write bursts
93 system.physmem.perBankRdBursts::6 87531 # Per bank write bursts
94 system.physmem.perBankRdBursts::7 83073 # Per bank write bursts
95 system.physmem.perBankRdBursts::8 80243 # Per bank write bursts
96 system.physmem.perBankRdBursts::9 128909 # Per bank write bursts
97 system.physmem.perBankRdBursts::10 86457 # Per bank write bursts
98 system.physmem.perBankRdBursts::11 85414 # Per bank write bursts
99 system.physmem.perBankRdBursts::12 83586 # Per bank write bursts
100 system.physmem.perBankRdBursts::13 88109 # Per bank write bursts
101 system.physmem.perBankRdBursts::14 80365 # Per bank write bursts
102 system.physmem.perBankRdBursts::15 80437 # Per bank write bursts
103 system.physmem.perBankWrBursts::0 72704 # Per bank write bursts
104 system.physmem.perBankWrBursts::1 74469 # Per bank write bursts
105 system.physmem.perBankWrBursts::2 70529 # Per bank write bursts
106 system.physmem.perBankWrBursts::3 72860 # Per bank write bursts
107 system.physmem.perBankWrBursts::4 75808 # Per bank write bursts
108 system.physmem.perBankWrBursts::5 80444 # Per bank write bursts
109 system.physmem.perBankWrBursts::6 76110 # Per bank write bursts
110 system.physmem.perBankWrBursts::7 73633 # Per bank write bursts
111 system.physmem.perBankWrBursts::8 70562 # Per bank write bursts
112 system.physmem.perBankWrBursts::9 76081 # Per bank write bursts
113 system.physmem.perBankWrBursts::10 73660 # Per bank write bursts
114 system.physmem.perBankWrBursts::11 73767 # Per bank write bursts
115 system.physmem.perBankWrBursts::12 72713 # Per bank write bursts
116 system.physmem.perBankWrBursts::13 77059 # Per bank write bursts
117 system.physmem.perBankWrBursts::14 70231 # Per bank write bursts
118 system.physmem.perBankWrBursts::15 71123 # Per bank write bursts
119 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120 system.physmem.numWrRetry 31 # Number of times write queue was full causing retry
121 system.physmem.totGap 51832611910500 # Total gap between requests
122 system.physmem.readPktSize::0 0 # Read request sizes (log2)
123 system.physmem.readPktSize::1 0 # Read request sizes (log2)
124 system.physmem.readPktSize::2 43101 # Read request sizes (log2)
125 system.physmem.readPktSize::3 13 # Read request sizes (log2)
126 system.physmem.readPktSize::4 2 # Read request sizes (log2)
127 system.physmem.readPktSize::5 0 # Read request sizes (log2)
128 system.physmem.readPktSize::6 1358974 # Read request sizes (log2)
129 system.physmem.writePktSize::0 0 # Write request sizes (log2)
130 system.physmem.writePktSize::1 0 # Write request sizes (log2)
131 system.physmem.writePktSize::2 1 # Write request sizes (log2)
132 system.physmem.writePktSize::3 2572 # Write request sizes (log2)
133 system.physmem.writePktSize::4 0 # Write request sizes (log2)
134 system.physmem.writePktSize::5 0 # Write request sizes (log2)
135 system.physmem.writePktSize::6 1181427 # Write request sizes (log2)
136 system.physmem.rdQLenPdf::0 1369118 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::1 26985 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::2 376 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::3 299 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::4 442 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::5 427 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::6 463 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::8 766 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::9 841 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::10 338 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::12 146 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::13 107 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::14 107 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
168 system.physmem.wrQLenPdf::0 1627 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::1 1594 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::2 1574 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::3 1554 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::4 1528 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::5 1510 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::6 1499 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::7 1486 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::8 1478 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::9 1460 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::10 1444 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::11 1433 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::12 1423 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::13 1412 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::14 1406 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::15 16205 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::16 18522 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::17 67973 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::18 68856 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::19 68869 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::20 68651 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::21 68381 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::22 71263 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::23 71520 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::24 74085 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::25 72568 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::26 72467 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::27 69770 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::28 69647 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::29 70062 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::30 67493 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::31 67216 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::32 66673 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::33 661 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::34 653 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::35 686 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::37 477 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::38 438 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::39 419 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::40 401 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::41 423 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::43 318 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::44 279 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::45 231 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::46 346 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::47 337 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::48 303 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::50 176 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::51 225 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::59 102 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::61 105 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see
232 system.physmem.bytesPerActivate::samples 564759 # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::mean 292.733658 # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::gmean 169.256086 # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::stdev 326.085017 # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::0-127 228658 40.49% 40.49% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::128-255 138332 24.49% 64.98% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::256-383 49531 8.77% 73.75% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::384-511 28277 5.01% 78.76% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::512-639 20268 3.59% 82.35% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::640-767 14095 2.50% 84.84% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::768-895 11027 1.95% 86.80% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::896-1023 10949 1.94% 88.73% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::1024-1151 63622 11.27% 100.00% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::total 564759 # Bytes accessed per row activation
246 system.physmem.rdPerTurnAround::samples 67625 # Reads before turning the bus around for writes
247 system.physmem.rdPerTurnAround::mean 20.723608 # Reads before turning the bus around for writes
248 system.physmem.rdPerTurnAround::stdev 277.022721 # Reads before turning the bus around for writes
249 system.physmem.rdPerTurnAround::0-4095 67622 100.00% 100.00% # Reads before turning the bus around for writes
250 system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
251 system.physmem.rdPerTurnAround::12288-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
252 system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes
253 system.physmem.rdPerTurnAround::total 67625 # Reads before turning the bus around for writes
254 system.physmem.wrPerTurnAround::samples 67625 # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::mean 17.475091 # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::gmean 16.957142 # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::stdev 6.452813 # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::0-3 76 0.11% 0.11% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::4-7 68 0.10% 0.21% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::8-11 65 0.10% 0.31% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::12-15 131 0.19% 0.50% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::16-19 63823 94.38% 94.88% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::20-23 440 0.65% 95.53% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::24-27 742 1.10% 96.63% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::28-31 499 0.74% 97.37% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::32-35 390 0.58% 97.94% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::36-39 489 0.72% 98.67% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::40-43 119 0.18% 98.84% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::44-47 25 0.04% 98.88% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::48-51 63 0.09% 98.97% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::52-55 45 0.07% 99.04% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::56-59 39 0.06% 99.10% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::60-63 22 0.03% 99.13% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::64-67 448 0.66% 99.79% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::68-71 23 0.03% 99.83% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::72-75 39 0.06% 99.88% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::76-79 24 0.04% 99.92% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::80-83 5 0.01% 99.93% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::116-119 1 0.00% 99.95% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::128-131 23 0.03% 99.98% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
292 system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads
293 system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
294 system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads
295 system.physmem.wrPerTurnAround::total 67625 # Writes before turning the bus around for reads
296 system.physmem.totQLat 16718468525 # Total ticks spent queuing
297 system.physmem.totMemAccLat 42995449775 # Total ticks spent from burst creation until serviced by the DRAM
298 system.physmem.totBusLat 7007195000 # Total ticks spent in databus transfers
299 system.physmem.avgQLat 11929.50 # Average queueing delay per DRAM burst
300 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
301 system.physmem.avgMemAccLat 30679.50 # Average memory access latency per DRAM burst
302 system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
303 system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s
304 system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s
305 system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s
306 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
307 system.physmem.busUtil 0.02 # Data bus utilization in percentage
308 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
309 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
310 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
311 system.physmem.avgWrQLen 12.63 # Average write queue length when enqueuing
312 system.physmem.readRowHits 1132210 # Number of row buffer hits during reads
313 system.physmem.writeRowHits 886222 # Number of row buffer hits during writes
314 system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads
315 system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes
316 system.physmem.avgGap 20042849.21 # Average gap between requests
317 system.physmem.pageHitRate 78.14 # Row buffer hit rate, read and write combined
318 system.physmem_0.actEnergy 2158387560 # Energy for activate commands per rank (pJ)
319 system.physmem_0.preEnergy 1177691625 # Energy for precharge commands per rank (pJ)
320 system.physmem_0.readEnergy 5365768200 # Energy for read commands per rank (pJ)
321 system.physmem_0.writeEnergy 3865689360 # Energy for write commands per rank (pJ)
322 system.physmem_0.refreshEnergy 3385453914960 # Energy for refresh commands per rank (pJ)
323 system.physmem_0.actBackEnergy 1313258572845 # Energy for active background per rank (pJ)
324 system.physmem_0.preBackEnergy 29947583060250 # Energy for precharge background per rank (pJ)
325 system.physmem_0.totalEnergy 34658863084800 # Total energy per rank (pJ)
326 system.physmem_0.averagePower 668.669107 # Core power per rank (mW)
327 system.physmem_0.memoryStateTime::IDLE 49819671489024 # Time in different power states
328 system.physmem_0.memoryStateTime::REF 1730804660000 # Time in different power states
329 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
330 system.physmem_0.memoryStateTime::ACT 282130972226 # Time in different power states
331 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
332 system.physmem_1.actEnergy 2111190480 # Energy for activate commands per rank (pJ)
333 system.physmem_1.preEnergy 1151939250 # Energy for precharge commands per rank (pJ)
334 system.physmem_1.readEnergy 5565417000 # Energy for read commands per rank (pJ)
335 system.physmem_1.writeEnergy 3792070080 # Energy for write commands per rank (pJ)
336 system.physmem_1.refreshEnergy 3385453914960 # Energy for refresh commands per rank (pJ)
337 system.physmem_1.actBackEnergy 1310153724135 # Energy for active background per rank (pJ)
338 system.physmem_1.preBackEnergy 29950306611750 # Energy for precharge background per rank (pJ)
339 system.physmem_1.totalEnergy 34658534867655 # Total energy per rank (pJ)
340 system.physmem_1.averagePower 668.662774 # Core power per rank (mW)
341 system.physmem_1.memoryStateTime::IDLE 49824215805224 # Time in different power states
342 system.physmem_1.memoryStateTime::REF 1730804660000 # Time in different power states
343 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
344 system.physmem_1.memoryStateTime::ACT 277593670776 # Time in different power states
345 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
346 system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
347 system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
348 system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
349 system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
350 system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
351 system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
352 system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
353 system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
354 system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
355 system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
356 system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
357 system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
358 system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
359 system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
360 system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
361 system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
362 system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
363 system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
364 system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
365 system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
366 system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
367 system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
368 system.cpu_clk_domain.clock 500 # Clock period in ticks
369 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
370 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
371 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
372 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
373 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
374 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
375 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
376 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
377 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
378 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
379 system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
380 system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
381 system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
382 system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
383 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
384 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
385 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
386 system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
387 system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
388 system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
389 system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
390 system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
391 system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
392 system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
393 system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
394 system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
395 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
396 system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
397 system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
398 system.cpu0.dtb.walker.walks 130428 # Table walker walks requested
399 system.cpu0.dtb.walker.walksLong 130428 # Table walker walks initiated with long descriptors
400 system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20426 # Level at which table walker walks with long descriptors terminate
401 system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94161 # Level at which table walker walks with long descriptors terminate
402 system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
403 system.cpu0.dtb.walker.walkWaitTime::samples 130414 # Table walker wait (enqueue to first request) latency
404 system.cpu0.dtb.walker.walkWaitTime::0 130414 100.00% 100.00% # Table walker wait (enqueue to first request) latency
405 system.cpu0.dtb.walker.walkWaitTime::total 130414 # Table walker wait (enqueue to first request) latency
406 system.cpu0.dtb.walker.walkCompletionTime::samples 114601 # Table walker service (enqueue to completion) latency
407 system.cpu0.dtb.walker.walkCompletionTime::mean 25025.623686 # Table walker service (enqueue to completion) latency
408 system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.133741 # Table walker service (enqueue to completion) latency
409 system.cpu0.dtb.walker.walkCompletionTime::stdev 14193.681922 # Table walker service (enqueue to completion) latency
410 system.cpu0.dtb.walker.walkCompletionTime::0-65535 113576 99.11% 99.11% # Table walker service (enqueue to completion) latency
411 system.cpu0.dtb.walker.walkCompletionTime::65536-131071 877 0.77% 99.87% # Table walker service (enqueue to completion) latency
412 system.cpu0.dtb.walker.walkCompletionTime::131072-196607 64 0.06% 99.93% # Table walker service (enqueue to completion) latency
413 system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.04% 99.96% # Table walker service (enqueue to completion) latency
414 system.cpu0.dtb.walker.walkCompletionTime::262144-327679 23 0.02% 99.98% # Table walker service (enqueue to completion) latency
415 system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
416 system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
417 system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
418 system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
419 system.cpu0.dtb.walker.walkCompletionTime::total 114601 # Table walker service (enqueue to completion) latency
420 system.cpu0.dtb.walker.walksPending::samples -626546628 # Table walker pending requests distribution
421 system.cpu0.dtb.walker.walksPending::mean 0.597966 # Table walker pending requests distribution
422 system.cpu0.dtb.walker.walksPending::stdev 0.490309 # Table walker pending requests distribution
423 system.cpu0.dtb.walker.walksPending::0 -251893296 40.20% 40.20% # Table walker pending requests distribution
424 system.cpu0.dtb.walker.walksPending::1 -374653332 59.80% 100.00% # Table walker pending requests distribution
425 system.cpu0.dtb.walker.walksPending::total -626546628 # Table walker pending requests distribution
426 system.cpu0.dtb.walker.walkPageSizes::4K 94162 82.17% 82.17% # Table walker page sizes translated
427 system.cpu0.dtb.walker.walkPageSizes::2M 20426 17.83% 100.00% # Table walker page sizes translated
428 system.cpu0.dtb.walker.walkPageSizes::total 114588 # Table walker page sizes translated
429 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130428 # Table walker requests started/completed, data/inst
430 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
431 system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130428 # Table walker requests started/completed, data/inst
432 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114588 # Table walker requests started/completed, data/inst
433 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
434 system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114588 # Table walker requests started/completed, data/inst
435 system.cpu0.dtb.walker.walkRequestOrigin::total 245016 # Table walker requests started/completed, data/inst
436 system.cpu0.dtb.inst_hits 0 # ITB inst hits
437 system.cpu0.dtb.inst_misses 0 # ITB inst misses
438 system.cpu0.dtb.read_hits 82615908 # DTB read hits
439 system.cpu0.dtb.read_misses 99897 # DTB read misses
440 system.cpu0.dtb.write_hits 75294881 # DTB write hits
441 system.cpu0.dtb.write_misses 30531 # DTB write misses
442 system.cpu0.dtb.flush_tlb 51838 # Number of times complete TLB was flushed
443 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
444 system.cpu0.dtb.flush_tlb_mva_asid 21162 # Number of times TLB was flushed by MVA & ASID
445 system.cpu0.dtb.flush_tlb_asid 519 # Number of times TLB was flushed by ASID
446 system.cpu0.dtb.flush_entries 72657 # Number of entries that have been flushed from TLB
447 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
448 system.cpu0.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch
449 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
450 system.cpu0.dtb.perms_faults 9875 # Number of TLB faults due to permissions restrictions
451 system.cpu0.dtb.read_accesses 82715805 # DTB read accesses
452 system.cpu0.dtb.write_accesses 75325412 # DTB write accesses
453 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
454 system.cpu0.dtb.hits 157910789 # DTB hits
455 system.cpu0.dtb.misses 130428 # DTB misses
456 system.cpu0.dtb.accesses 158041217 # DTB accesses
457 system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
458 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
459 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
460 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
461 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
462 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
463 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
464 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
465 system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
466 system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
467 system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
468 system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
469 system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
470 system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
471 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
472 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
473 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
474 system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
475 system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
476 system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
477 system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
478 system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
479 system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
480 system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
481 system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
482 system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
483 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
484 system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
485 system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
486 system.cpu0.itb.walker.walks 77694 # Table walker walks requested
487 system.cpu0.itb.walker.walksLong 77694 # Table walker walks initiated with long descriptors
488 system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4299 # Level at which table walker walks with long descriptors terminate
489 system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67844 # Level at which table walker walks with long descriptors terminate
490 system.cpu0.itb.walker.walkWaitTime::samples 77694 # Table walker wait (enqueue to first request) latency
491 system.cpu0.itb.walker.walkWaitTime::0 77694 100.00% 100.00% # Table walker wait (enqueue to first request) latency
492 system.cpu0.itb.walker.walkWaitTime::total 77694 # Table walker wait (enqueue to first request) latency
493 system.cpu0.itb.walker.walkCompletionTime::samples 72143 # Table walker service (enqueue to completion) latency
494 system.cpu0.itb.walker.walkCompletionTime::mean 28108.645329 # Table walker service (enqueue to completion) latency
495 system.cpu0.itb.walker.walkCompletionTime::gmean 25072.463875 # Table walker service (enqueue to completion) latency
496 system.cpu0.itb.walker.walkCompletionTime::stdev 16528.773937 # Table walker service (enqueue to completion) latency
497 system.cpu0.itb.walker.walkCompletionTime::0-65535 70985 98.39% 98.39% # Table walker service (enqueue to completion) latency
498 system.cpu0.itb.walker.walkCompletionTime::65536-131071 998 1.38% 99.78% # Table walker service (enqueue to completion) latency
499 system.cpu0.itb.walker.walkCompletionTime::131072-196607 60 0.08% 99.86% # Table walker service (enqueue to completion) latency
500 system.cpu0.itb.walker.walkCompletionTime::196608-262143 53 0.07% 99.93% # Table walker service (enqueue to completion) latency
501 system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.97% # Table walker service (enqueue to completion) latency
502 system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
503 system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
504 system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
505 system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
506 system.cpu0.itb.walker.walkCompletionTime::total 72143 # Table walker service (enqueue to completion) latency
507 system.cpu0.itb.walker.walksPending::samples -294780296 # Table walker pending requests distribution
508 system.cpu0.itb.walker.walksPending::0 -294780296 100.00% 100.00% # Table walker pending requests distribution
509 system.cpu0.itb.walker.walksPending::total -294780296 # Table walker pending requests distribution
510 system.cpu0.itb.walker.walkPageSizes::4K 67844 94.04% 94.04% # Table walker page sizes translated
511 system.cpu0.itb.walker.walkPageSizes::2M 4299 5.96% 100.00% # Table walker page sizes translated
512 system.cpu0.itb.walker.walkPageSizes::total 72143 # Table walker page sizes translated
513 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
514 system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77694 # Table walker requests started/completed, data/inst
515 system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77694 # Table walker requests started/completed, data/inst
516 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
517 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72143 # Table walker requests started/completed, data/inst
518 system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72143 # Table walker requests started/completed, data/inst
519 system.cpu0.itb.walker.walkRequestOrigin::total 149837 # Table walker requests started/completed, data/inst
520 system.cpu0.itb.inst_hits 440762049 # ITB inst hits
521 system.cpu0.itb.inst_misses 77694 # ITB inst misses
522 system.cpu0.itb.read_hits 0 # DTB read hits
523 system.cpu0.itb.read_misses 0 # DTB read misses
524 system.cpu0.itb.write_hits 0 # DTB write hits
525 system.cpu0.itb.write_misses 0 # DTB write misses
526 system.cpu0.itb.flush_tlb 51838 # Number of times complete TLB was flushed
527 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
528 system.cpu0.itb.flush_tlb_mva_asid 21162 # Number of times TLB was flushed by MVA & ASID
529 system.cpu0.itb.flush_tlb_asid 519 # Number of times TLB was flushed by ASID
530 system.cpu0.itb.flush_entries 53801 # Number of entries that have been flushed from TLB
531 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
532 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
533 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
534 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
535 system.cpu0.itb.read_accesses 0 # DTB read accesses
536 system.cpu0.itb.write_accesses 0 # DTB write accesses
537 system.cpu0.itb.inst_accesses 440839743 # ITB inst accesses
538 system.cpu0.itb.hits 440762049 # DTB hits
539 system.cpu0.itb.misses 77694 # DTB misses
540 system.cpu0.itb.accesses 440839743 # DTB accesses
541 system.cpu0.numCycles 51832801454 # number of cpu cycles simulated
542 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
543 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
544 system.cpu0.committedInsts 440492275 # Number of instructions committed
545 system.cpu0.committedOps 517776891 # Number of ops (including micro ops) committed
546 system.cpu0.num_int_alu_accesses 475595742 # Number of integer alu accesses
547 system.cpu0.num_fp_alu_accesses 442272 # Number of float alu accesses
548 system.cpu0.num_func_calls 26261796 # number of times a function call or return occured
549 system.cpu0.num_conditional_control_insts 67159010 # number of instructions that are conditional controls
550 system.cpu0.num_int_insts 475595742 # number of integer instructions
551 system.cpu0.num_fp_insts 442272 # number of float instructions
552 system.cpu0.num_int_register_reads 692983656 # number of times the integer registers were read
553 system.cpu0.num_int_register_writes 377245689 # number of times the integer registers were written
554 system.cpu0.num_fp_register_reads 706646 # number of times the floating registers were read
555 system.cpu0.num_fp_register_writes 389336 # number of times the floating registers were written
556 system.cpu0.num_cc_register_reads 115273932 # number of times the CC registers were read
557 system.cpu0.num_cc_register_writes 114990138 # number of times the CC registers were written
558 system.cpu0.num_mem_refs 157900832 # number of memory refs
559 system.cpu0.num_load_insts 82612008 # Number of load instructions
560 system.cpu0.num_store_insts 75288824 # Number of store instructions
561 system.cpu0.num_idle_cycles 50243492062.967224 # Number of idle cycles
562 system.cpu0.num_busy_cycles 1589309391.032773 # Number of busy cycles
563 system.cpu0.not_idle_fraction 0.030662 # Percentage of non-idle cycles
564 system.cpu0.idle_fraction 0.969338 # Percentage of idle cycles
565 system.cpu0.Branches 98397494 # Number of branches fetched
566 system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
567 system.cpu0.op_class::IntAlu 358993131 69.29% 69.29% # Class of executed instruction
568 system.cpu0.op_class::IntMult 1071583 0.21% 69.50% # Class of executed instruction
569 system.cpu0.op_class::IntDiv 48336 0.01% 69.51% # Class of executed instruction
570 system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
571 system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
572 system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
573 system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
574 system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
575 system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
576 system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
577 system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
578 system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
579 system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
580 system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
581 system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
582 system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
583 system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
584 system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
585 system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
586 system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
587 system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
588 system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
589 system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
590 system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction
591 system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
592 system.cpu0.op_class::SimdFloatMisc 58966 0.01% 69.52% # Class of executed instruction
593 system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
594 system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
595 system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
596 system.cpu0.op_class::MemRead 82612008 15.95% 85.47% # Class of executed instruction
597 system.cpu0.op_class::MemWrite 75288824 14.53% 100.00% # Class of executed instruction
598 system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
599 system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
600 system.cpu0.op_class::total 518072849 # Class of executed instruction
601 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
602 system.cpu0.kern.inst.quiesce 16267 # number of quiesce instructions executed
603 system.cpu0.dcache.tags.replacements 10037940 # number of replacements
604 system.cpu0.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use
605 system.cpu0.dcache.tags.total_refs 305864730 # Total number of references to valid blocks.
606 system.cpu0.dcache.tags.sampled_refs 10038452 # Sample count of references to valid blocks.
607 system.cpu0.dcache.tags.avg_refs 30.469312 # Average number of references to valid blocks.
608 system.cpu0.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit.
609 system.cpu0.dcache.tags.occ_blocks::cpu0.data 221.416582 # Average occupied blocks per requestor
610 system.cpu0.dcache.tags.occ_blocks::cpu1.data 290.549452 # Average occupied blocks per requestor
611 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.432454 # Average percentage of cache occupancy
612 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.567479 # Average percentage of cache occupancy
613 system.cpu0.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy
614 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
615 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
616 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
617 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
618 system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
619 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
620 system.cpu0.dcache.tags.tag_accesses 1274123450 # Number of tag accesses
621 system.cpu0.dcache.tags.data_accesses 1274123450 # Number of data accesses
622 system.cpu0.dcache.ReadReq_hits::cpu0.data 77217599 # number of ReadReq hits
623 system.cpu0.dcache.ReadReq_hits::cpu1.data 77513026 # number of ReadReq hits
624 system.cpu0.dcache.ReadReq_hits::total 154730625 # number of ReadReq hits
625 system.cpu0.dcache.WriteReq_hits::cpu0.data 71443407 # number of WriteReq hits
626 system.cpu0.dcache.WriteReq_hits::cpu1.data 71419351 # number of WriteReq hits
627 system.cpu0.dcache.WriteReq_hits::total 142862758 # number of WriteReq hits
628 system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195522 # number of SoftPFReq hits
629 system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192929 # number of SoftPFReq hits
630 system.cpu0.dcache.SoftPFReq_hits::total 388451 # number of SoftPFReq hits
631 system.cpu0.dcache.WriteLineReq_hits::cpu0.data 168757 # number of WriteLineReq hits
632 system.cpu0.dcache.WriteLineReq_hits::cpu1.data 166793 # number of WriteLineReq hits
633 system.cpu0.dcache.WriteLineReq_hits::total 335550 # number of WriteLineReq hits
634 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1811257 # number of LoadLockedReq hits
635 system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1789885 # number of LoadLockedReq hits
636 system.cpu0.dcache.LoadLockedReq_hits::total 3601142 # number of LoadLockedReq hits
637 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1962197 # number of StoreCondReq hits
638 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1939338 # number of StoreCondReq hits
639 system.cpu0.dcache.StoreCondReq_hits::total 3901535 # number of StoreCondReq hits
640 system.cpu0.dcache.demand_hits::cpu0.data 148661006 # number of demand (read+write) hits
641 system.cpu0.dcache.demand_hits::cpu1.data 148932377 # number of demand (read+write) hits
642 system.cpu0.dcache.demand_hits::total 297593383 # number of demand (read+write) hits
643 system.cpu0.dcache.overall_hits::cpu0.data 148856528 # number of overall hits
644 system.cpu0.dcache.overall_hits::cpu1.data 149125306 # number of overall hits
645 system.cpu0.dcache.overall_hits::total 297981834 # number of overall hits
646 system.cpu0.dcache.ReadReq_misses::cpu0.data 2588533 # number of ReadReq misses
647 system.cpu0.dcache.ReadReq_misses::cpu1.data 2647536 # number of ReadReq misses
648 system.cpu0.dcache.ReadReq_misses::total 5236069 # number of ReadReq misses
649 system.cpu0.dcache.WriteReq_misses::cpu0.data 1081685 # number of WriteReq misses
650 system.cpu0.dcache.WriteReq_misses::cpu1.data 1087089 # number of WriteReq misses
651 system.cpu0.dcache.WriteReq_misses::total 2168774 # number of WriteReq misses
652 system.cpu0.dcache.SoftPFReq_misses::cpu0.data 633947 # number of SoftPFReq misses
653 system.cpu0.dcache.SoftPFReq_misses::cpu1.data 631509 # number of SoftPFReq misses
654 system.cpu0.dcache.SoftPFReq_misses::total 1265456 # number of SoftPFReq misses
655 system.cpu0.dcache.WriteLineReq_misses::cpu0.data 612829 # number of WriteLineReq misses
656 system.cpu0.dcache.WriteLineReq_misses::cpu1.data 615985 # number of WriteLineReq misses
657 system.cpu0.dcache.WriteLineReq_misses::total 1228814 # number of WriteLineReq misses
658 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 151773 # number of LoadLockedReq misses
659 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 150295 # number of LoadLockedReq misses
660 system.cpu0.dcache.LoadLockedReq_misses::total 302068 # number of LoadLockedReq misses
661 system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
662 system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
663 system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
664 system.cpu0.dcache.demand_misses::cpu0.data 3670218 # number of demand (read+write) misses
665 system.cpu0.dcache.demand_misses::cpu1.data 3734625 # number of demand (read+write) misses
666 system.cpu0.dcache.demand_misses::total 7404843 # number of demand (read+write) misses
667 system.cpu0.dcache.overall_misses::cpu0.data 4304165 # number of overall misses
668 system.cpu0.dcache.overall_misses::cpu1.data 4366134 # number of overall misses
669 system.cpu0.dcache.overall_misses::total 8670299 # number of overall misses
670 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41004192000 # number of ReadReq miss cycles
671 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 41620421500 # number of ReadReq miss cycles
672 system.cpu0.dcache.ReadReq_miss_latency::total 82624613500 # number of ReadReq miss cycles
673 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 31575309500 # number of WriteReq miss cycles
674 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 31406770000 # number of WriteReq miss cycles
675 system.cpu0.dcache.WriteReq_miss_latency::total 62982079500 # number of WriteReq miss cycles
676 system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25211350000 # number of WriteLineReq miss cycles
677 system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 25725023500 # number of WriteLineReq miss cycles
678 system.cpu0.dcache.WriteLineReq_miss_latency::total 50936373500 # number of WriteLineReq miss cycles
679 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2229514000 # number of LoadLockedReq miss cycles
680 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2184997000 # number of LoadLockedReq miss cycles
681 system.cpu0.dcache.LoadLockedReq_miss_latency::total 4414511000 # number of LoadLockedReq miss cycles
682 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 82000 # number of StoreCondReq miss cycles
683 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 33000 # number of StoreCondReq miss cycles
684 system.cpu0.dcache.StoreCondReq_miss_latency::total 115000 # number of StoreCondReq miss cycles
685 system.cpu0.dcache.demand_miss_latency::cpu0.data 72579501500 # number of demand (read+write) miss cycles
686 system.cpu0.dcache.demand_miss_latency::cpu1.data 73027191500 # number of demand (read+write) miss cycles
687 system.cpu0.dcache.demand_miss_latency::total 145606693000 # number of demand (read+write) miss cycles
688 system.cpu0.dcache.overall_miss_latency::cpu0.data 72579501500 # number of overall miss cycles
689 system.cpu0.dcache.overall_miss_latency::cpu1.data 73027191500 # number of overall miss cycles
690 system.cpu0.dcache.overall_miss_latency::total 145606693000 # number of overall miss cycles
691 system.cpu0.dcache.ReadReq_accesses::cpu0.data 79806132 # number of ReadReq accesses(hits+misses)
692 system.cpu0.dcache.ReadReq_accesses::cpu1.data 80160562 # number of ReadReq accesses(hits+misses)
693 system.cpu0.dcache.ReadReq_accesses::total 159966694 # number of ReadReq accesses(hits+misses)
694 system.cpu0.dcache.WriteReq_accesses::cpu0.data 72525092 # number of WriteReq accesses(hits+misses)
695 system.cpu0.dcache.WriteReq_accesses::cpu1.data 72506440 # number of WriteReq accesses(hits+misses)
696 system.cpu0.dcache.WriteReq_accesses::total 145031532 # number of WriteReq accesses(hits+misses)
697 system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 829469 # number of SoftPFReq accesses(hits+misses)
698 system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 824438 # number of SoftPFReq accesses(hits+misses)
699 system.cpu0.dcache.SoftPFReq_accesses::total 1653907 # number of SoftPFReq accesses(hits+misses)
700 system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 781586 # number of WriteLineReq accesses(hits+misses)
701 system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 782778 # number of WriteLineReq accesses(hits+misses)
702 system.cpu0.dcache.WriteLineReq_accesses::total 1564364 # number of WriteLineReq accesses(hits+misses)
703 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1963030 # number of LoadLockedReq accesses(hits+misses)
704 system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1940180 # number of LoadLockedReq accesses(hits+misses)
705 system.cpu0.dcache.LoadLockedReq_accesses::total 3903210 # number of LoadLockedReq accesses(hits+misses)
706 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1962198 # number of StoreCondReq accesses(hits+misses)
707 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1939339 # number of StoreCondReq accesses(hits+misses)
708 system.cpu0.dcache.StoreCondReq_accesses::total 3901537 # number of StoreCondReq accesses(hits+misses)
709 system.cpu0.dcache.demand_accesses::cpu0.data 152331224 # number of demand (read+write) accesses
710 system.cpu0.dcache.demand_accesses::cpu1.data 152667002 # number of demand (read+write) accesses
711 system.cpu0.dcache.demand_accesses::total 304998226 # number of demand (read+write) accesses
712 system.cpu0.dcache.overall_accesses::cpu0.data 153160693 # number of overall (read+write) accesses
713 system.cpu0.dcache.overall_accesses::cpu1.data 153491440 # number of overall (read+write) accesses
714 system.cpu0.dcache.overall_accesses::total 306652133 # number of overall (read+write) accesses
715 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032435 # miss rate for ReadReq accesses
716 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033028 # miss rate for ReadReq accesses
717 system.cpu0.dcache.ReadReq_miss_rate::total 0.032732 # miss rate for ReadReq accesses
718 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014915 # miss rate for WriteReq accesses
719 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014993 # miss rate for WriteReq accesses
720 system.cpu0.dcache.WriteReq_miss_rate::total 0.014954 # miss rate for WriteReq accesses
721 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764281 # miss rate for SoftPFReq accesses
722 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.765987 # miss rate for SoftPFReq accesses
723 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765131 # miss rate for SoftPFReq accesses
724 system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.784084 # miss rate for WriteLineReq accesses
725 system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.786922 # miss rate for WriteLineReq accesses
726 system.cpu0.dcache.WriteLineReq_miss_rate::total 0.785504 # miss rate for WriteLineReq accesses
727 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077316 # miss rate for LoadLockedReq accesses
728 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077464 # miss rate for LoadLockedReq accesses
729 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077390 # miss rate for LoadLockedReq accesses
730 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
731 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
732 system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
733 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024094 # miss rate for demand accesses
734 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024463 # miss rate for demand accesses
735 system.cpu0.dcache.demand_miss_rate::total 0.024278 # miss rate for demand accesses
736 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028102 # miss rate for overall accesses
737 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028445 # miss rate for overall accesses
738 system.cpu0.dcache.overall_miss_rate::total 0.028274 # miss rate for overall accesses
739 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15840.706686 # average ReadReq miss latency
740 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15720.436474 # average ReadReq miss latency
741 system.cpu0.dcache.ReadReq_avg_miss_latency::total 15779.893943 # average ReadReq miss latency
742 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29190.854546 # average WriteReq miss latency
743 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28890.707201 # average WriteReq miss latency
744 system.cpu0.dcache.WriteReq_avg_miss_latency::total 29040.406930 # average WriteReq miss latency
745 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 41139.290079 # average WriteLineReq miss latency
746 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41762.418728 # average WriteLineReq miss latency
747 system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 41451.654604 # average WriteLineReq miss latency
748 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14689.793310 # average LoadLockedReq miss latency
749 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14538.055158 # average LoadLockedReq miss latency
750 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14614.295457 # average LoadLockedReq miss latency
751 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency
752 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 33000 # average StoreCondReq miss latency
753 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 57500 # average StoreCondReq miss latency
754 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19775.256265 # average overall miss latency
755 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19554.089500 # average overall miss latency
756 system.cpu0.dcache.demand_avg_miss_latency::total 19663.711033 # average overall miss latency
757 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16862.620624 # average overall miss latency
758 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16725.824608 # average overall miss latency
759 system.cpu0.dcache.overall_avg_miss_latency::total 16793.733757 # average overall miss latency
760 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
761 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
762 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
763 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
764 system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
765 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
766 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
767 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
768 system.cpu0.dcache.writebacks::writebacks 7725236 # number of writebacks
769 system.cpu0.dcache.writebacks::total 7725236 # number of writebacks
770 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 11311 # number of ReadReq MSHR hits
771 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 11844 # number of ReadReq MSHR hits
772 system.cpu0.dcache.ReadReq_mshr_hits::total 23155 # number of ReadReq MSHR hits
773 system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 9967 # number of WriteReq MSHR hits
774 system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 11283 # number of WriteReq MSHR hits
775 system.cpu0.dcache.WriteReq_mshr_hits::total 21250 # number of WriteReq MSHR hits
776 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36142 # number of LoadLockedReq MSHR hits
777 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35738 # number of LoadLockedReq MSHR hits
778 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 71880 # number of LoadLockedReq MSHR hits
779 system.cpu0.dcache.demand_mshr_hits::cpu0.data 21278 # number of demand (read+write) MSHR hits
780 system.cpu0.dcache.demand_mshr_hits::cpu1.data 23127 # number of demand (read+write) MSHR hits
781 system.cpu0.dcache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits
782 system.cpu0.dcache.overall_mshr_hits::cpu0.data 21278 # number of overall MSHR hits
783 system.cpu0.dcache.overall_mshr_hits::cpu1.data 23127 # number of overall MSHR hits
784 system.cpu0.dcache.overall_mshr_hits::total 44405 # number of overall MSHR hits
785 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2577222 # number of ReadReq MSHR misses
786 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2635692 # number of ReadReq MSHR misses
787 system.cpu0.dcache.ReadReq_mshr_misses::total 5212914 # number of ReadReq MSHR misses
788 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1071718 # number of WriteReq MSHR misses
789 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1075806 # number of WriteReq MSHR misses
790 system.cpu0.dcache.WriteReq_mshr_misses::total 2147524 # number of WriteReq MSHR misses
791 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 633158 # number of SoftPFReq MSHR misses
792 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 630543 # number of SoftPFReq MSHR misses
793 system.cpu0.dcache.SoftPFReq_mshr_misses::total 1263701 # number of SoftPFReq MSHR misses
794 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 612829 # number of WriteLineReq MSHR misses
795 system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 615985 # number of WriteLineReq MSHR misses
796 system.cpu0.dcache.WriteLineReq_mshr_misses::total 1228814 # number of WriteLineReq MSHR misses
797 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115631 # number of LoadLockedReq MSHR misses
798 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 114557 # number of LoadLockedReq MSHR misses
799 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 230188 # number of LoadLockedReq MSHR misses
800 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses
801 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses
802 system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
803 system.cpu0.dcache.demand_mshr_misses::cpu0.data 3648940 # number of demand (read+write) MSHR misses
804 system.cpu0.dcache.demand_mshr_misses::cpu1.data 3711498 # number of demand (read+write) MSHR misses
805 system.cpu0.dcache.demand_mshr_misses::total 7360438 # number of demand (read+write) MSHR misses
806 system.cpu0.dcache.overall_mshr_misses::cpu0.data 4282098 # number of overall MSHR misses
807 system.cpu0.dcache.overall_mshr_misses::cpu1.data 4342041 # number of overall MSHR misses
808 system.cpu0.dcache.overall_mshr_misses::total 8624139 # number of overall MSHR misses
809 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17286 # number of ReadReq MSHR uncacheable
810 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16418 # number of ReadReq MSHR uncacheable
811 system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33704 # number of ReadReq MSHR uncacheable
812 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16057 # number of WriteReq MSHR uncacheable
813 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 17652 # number of WriteReq MSHR uncacheable
814 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33709 # number of WriteReq MSHR uncacheable
815 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33343 # number of overall MSHR uncacheable misses
816 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 34070 # number of overall MSHR uncacheable misses
817 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67413 # number of overall MSHR uncacheable misses
818 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38167566000 # number of ReadReq MSHR miss cycles
819 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 38688442500 # number of ReadReq MSHR miss cycles
820 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 76856008500 # number of ReadReq MSHR miss cycles
821 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30213193500 # number of WriteReq MSHR miss cycles
822 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 29970900500 # number of WriteReq MSHR miss cycles
823 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 60184094000 # number of WriteReq MSHR miss cycles
824 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10061362000 # number of SoftPFReq MSHR miss cycles
825 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10320868500 # number of SoftPFReq MSHR miss cycles
826 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20382230500 # number of SoftPFReq MSHR miss cycles
827 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24598521000 # number of WriteLineReq MSHR miss cycles
828 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 25109038500 # number of WriteLineReq MSHR miss cycles
829 system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 49707559500 # number of WriteLineReq MSHR miss cycles
830 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1553845500 # number of LoadLockedReq MSHR miss cycles
831 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1517429500 # number of LoadLockedReq MSHR miss cycles
832 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3071275000 # number of LoadLockedReq MSHR miss cycles
833 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 81000 # number of StoreCondReq MSHR miss cycles
834 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32000 # number of StoreCondReq MSHR miss cycles
835 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 113000 # number of StoreCondReq MSHR miss cycles
836 system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68380759500 # number of demand (read+write) MSHR miss cycles
837 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 68659343000 # number of demand (read+write) MSHR miss cycles
838 system.cpu0.dcache.demand_mshr_miss_latency::total 137040102500 # number of demand (read+write) MSHR miss cycles
839 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 78442121500 # number of overall MSHR miss cycles
840 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 78980211500 # number of overall MSHR miss cycles
841 system.cpu0.dcache.overall_mshr_miss_latency::total 157422333000 # number of overall MSHR miss cycles
842 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2977259000 # number of ReadReq MSHR uncacheable cycles
843 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2853920500 # number of ReadReq MSHR uncacheable cycles
844 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5831179500 # number of ReadReq MSHR uncacheable cycles
845 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2866948000 # number of WriteReq MSHR uncacheable cycles
846 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2828284500 # number of WriteReq MSHR uncacheable cycles
847 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5695232500 # number of WriteReq MSHR uncacheable cycles
848 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5844207000 # number of overall MSHR uncacheable cycles
849 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5682205000 # number of overall MSHR uncacheable cycles
850 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11526412000 # number of overall MSHR uncacheable cycles
851 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032294 # mshr miss rate for ReadReq accesses
852 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032880 # mshr miss rate for ReadReq accesses
853 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032587 # mshr miss rate for ReadReq accesses
854 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014777 # mshr miss rate for WriteReq accesses
855 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014837 # mshr miss rate for WriteReq accesses
856 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014807 # mshr miss rate for WriteReq accesses
857 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763329 # mshr miss rate for SoftPFReq accesses
858 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764816 # mshr miss rate for SoftPFReq accesses
859 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.764070 # mshr miss rate for SoftPFReq accesses
860 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784084 # mshr miss rate for WriteLineReq accesses
861 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.786922 # mshr miss rate for WriteLineReq accesses
862 system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785504 # mshr miss rate for WriteLineReq accesses
863 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058904 # mshr miss rate for LoadLockedReq accesses
864 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059045 # mshr miss rate for LoadLockedReq accesses
865 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058974 # mshr miss rate for LoadLockedReq accesses
866 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses
867 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
868 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
869 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023954 # mshr miss rate for demand accesses
870 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024311 # mshr miss rate for demand accesses
871 system.cpu0.dcache.demand_mshr_miss_rate::total 0.024133 # mshr miss rate for demand accesses
872 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027958 # mshr miss rate for overall accesses
873 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028288 # mshr miss rate for overall accesses
874 system.cpu0.dcache.overall_mshr_miss_rate::total 0.028124 # mshr miss rate for overall accesses
875 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14809.576358 # average ReadReq mshr miss latency
876 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14678.665982 # average ReadReq mshr miss latency
877 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14743.387000 # average ReadReq mshr miss latency
878 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28191.365173 # average WriteReq mshr miss latency
879 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27859.019656 # average WriteReq mshr miss latency
880 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28024.876090 # average WriteReq mshr miss latency
881 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15890.760284 # average SoftPFReq mshr miss latency
882 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16368.223103 # average SoftPFReq mshr miss latency
883 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16128.997682 # average SoftPFReq mshr miss latency
884 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 40139.290079 # average WriteLineReq mshr miss latency
885 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40762.418728 # average WriteLineReq mshr miss latency
886 system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 40451.654604 # average WriteLineReq mshr miss latency
887 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13437.966462 # average LoadLockedReq mshr miss latency
888 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13246.065278 # average LoadLockedReq mshr miss latency
889 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13342.463552 # average LoadLockedReq mshr miss latency
890 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency
891 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 32000 # average StoreCondReq mshr miss latency
892 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 56500 # average StoreCondReq mshr miss latency
893 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18739.896929 # average overall mshr miss latency
894 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18499.092011 # average overall mshr miss latency
895 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18618.471143 # average overall mshr miss latency
896 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18318.618934 # average overall mshr miss latency
897 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18189.651249 # average overall mshr miss latency
898 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18253.686890 # average overall mshr miss latency
899 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172235.277103 # average ReadReq mshr uncacheable latency
900 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173828.755025 # average ReadReq mshr uncacheable latency
901 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.497152 # average ReadReq mshr uncacheable latency
902 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178548.172137 # average WriteReq mshr uncacheable latency
903 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160224.592114 # average WriteReq mshr uncacheable latency
904 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168952.876087 # average WriteReq mshr uncacheable latency
905 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175275.380140 # average overall mshr uncacheable latency
906 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166780.305254 # average overall mshr uncacheable latency
907 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170982.036106 # average overall mshr uncacheable latency
908 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
909 system.cpu0.icache.tags.replacements 13866895 # number of replacements
910 system.cpu0.icache.tags.tagsinuse 511.854828 # Cycle average of tags in use
911 system.cpu0.icache.tags.total_refs 868036851 # Total number of references to valid blocks.
912 system.cpu0.icache.tags.sampled_refs 13867407 # Sample count of references to valid blocks.
913 system.cpu0.icache.tags.avg_refs 62.595469 # Average number of references to valid blocks.
914 system.cpu0.icache.tags.warmup_cycle 43293883500 # Cycle when the warmup percentage was hit.
915 system.cpu0.icache.tags.occ_blocks::cpu0.inst 253.434107 # Average occupied blocks per requestor
916 system.cpu0.icache.tags.occ_blocks::cpu1.inst 258.420721 # Average occupied blocks per requestor
917 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.494988 # Average percentage of cache occupancy
918 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.504728 # Average percentage of cache occupancy
919 system.cpu0.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy
920 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
921 system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
922 system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
923 system.cpu0.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id
924 system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
925 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
926 system.cpu0.icache.tags.tag_accesses 895771675 # Number of tag accesses
927 system.cpu0.icache.tags.data_accesses 895771675 # Number of data accesses
928 system.cpu0.icache.ReadReq_hits::cpu0.inst 433832015 # number of ReadReq hits
929 system.cpu0.icache.ReadReq_hits::cpu1.inst 434204836 # number of ReadReq hits
930 system.cpu0.icache.ReadReq_hits::total 868036851 # number of ReadReq hits
931 system.cpu0.icache.demand_hits::cpu0.inst 433832015 # number of demand (read+write) hits
932 system.cpu0.icache.demand_hits::cpu1.inst 434204836 # number of demand (read+write) hits
933 system.cpu0.icache.demand_hits::total 868036851 # number of demand (read+write) hits
934 system.cpu0.icache.overall_hits::cpu0.inst 433832015 # number of overall hits
935 system.cpu0.icache.overall_hits::cpu1.inst 434204836 # number of overall hits
936 system.cpu0.icache.overall_hits::total 868036851 # number of overall hits
937 system.cpu0.icache.ReadReq_misses::cpu0.inst 6930034 # number of ReadReq misses
938 system.cpu0.icache.ReadReq_misses::cpu1.inst 6937378 # number of ReadReq misses
939 system.cpu0.icache.ReadReq_misses::total 13867412 # number of ReadReq misses
940 system.cpu0.icache.demand_misses::cpu0.inst 6930034 # number of demand (read+write) misses
941 system.cpu0.icache.demand_misses::cpu1.inst 6937378 # number of demand (read+write) misses
942 system.cpu0.icache.demand_misses::total 13867412 # number of demand (read+write) misses
943 system.cpu0.icache.overall_misses::cpu0.inst 6930034 # number of overall misses
944 system.cpu0.icache.overall_misses::cpu1.inst 6937378 # number of overall misses
945 system.cpu0.icache.overall_misses::total 13867412 # number of overall misses
946 system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93266994500 # number of ReadReq miss cycles
947 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 92872882000 # number of ReadReq miss cycles
948 system.cpu0.icache.ReadReq_miss_latency::total 186139876500 # number of ReadReq miss cycles
949 system.cpu0.icache.demand_miss_latency::cpu0.inst 93266994500 # number of demand (read+write) miss cycles
950 system.cpu0.icache.demand_miss_latency::cpu1.inst 92872882000 # number of demand (read+write) miss cycles
951 system.cpu0.icache.demand_miss_latency::total 186139876500 # number of demand (read+write) miss cycles
952 system.cpu0.icache.overall_miss_latency::cpu0.inst 93266994500 # number of overall miss cycles
953 system.cpu0.icache.overall_miss_latency::cpu1.inst 92872882000 # number of overall miss cycles
954 system.cpu0.icache.overall_miss_latency::total 186139876500 # number of overall miss cycles
955 system.cpu0.icache.ReadReq_accesses::cpu0.inst 440762049 # number of ReadReq accesses(hits+misses)
956 system.cpu0.icache.ReadReq_accesses::cpu1.inst 441142214 # number of ReadReq accesses(hits+misses)
957 system.cpu0.icache.ReadReq_accesses::total 881904263 # number of ReadReq accesses(hits+misses)
958 system.cpu0.icache.demand_accesses::cpu0.inst 440762049 # number of demand (read+write) accesses
959 system.cpu0.icache.demand_accesses::cpu1.inst 441142214 # number of demand (read+write) accesses
960 system.cpu0.icache.demand_accesses::total 881904263 # number of demand (read+write) accesses
961 system.cpu0.icache.overall_accesses::cpu0.inst 440762049 # number of overall (read+write) accesses
962 system.cpu0.icache.overall_accesses::cpu1.inst 441142214 # number of overall (read+write) accesses
963 system.cpu0.icache.overall_accesses::total 881904263 # number of overall (read+write) accesses
964 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015723 # miss rate for ReadReq accesses
965 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015726 # miss rate for ReadReq accesses
966 system.cpu0.icache.ReadReq_miss_rate::total 0.015724 # miss rate for ReadReq accesses
967 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015723 # miss rate for demand accesses
968 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015726 # miss rate for demand accesses
969 system.cpu0.icache.demand_miss_rate::total 0.015724 # miss rate for demand accesses
970 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015723 # miss rate for overall accesses
971 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015726 # miss rate for overall accesses
972 system.cpu0.icache.overall_miss_rate::total 0.015724 # miss rate for overall accesses
973 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13458.374735 # average ReadReq miss latency
974 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.317514 # average ReadReq miss latency
975 system.cpu0.icache.ReadReq_avg_miss_latency::total 13422.827309 # average ReadReq miss latency
976 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13458.374735 # average overall miss latency
977 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13387.317514 # average overall miss latency
978 system.cpu0.icache.demand_avg_miss_latency::total 13422.827309 # average overall miss latency
979 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13458.374735 # average overall miss latency
980 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13387.317514 # average overall miss latency
981 system.cpu0.icache.overall_avg_miss_latency::total 13422.827309 # average overall miss latency
982 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
983 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
984 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
985 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
986 system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
987 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
988 system.cpu0.icache.fast_writes 0 # number of fast writes performed
989 system.cpu0.icache.cache_copies 0 # number of cache copies performed
990 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6930034 # number of ReadReq MSHR misses
991 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6937378 # number of ReadReq MSHR misses
992 system.cpu0.icache.ReadReq_mshr_misses::total 13867412 # number of ReadReq MSHR misses
993 system.cpu0.icache.demand_mshr_misses::cpu0.inst 6930034 # number of demand (read+write) MSHR misses
994 system.cpu0.icache.demand_mshr_misses::cpu1.inst 6937378 # number of demand (read+write) MSHR misses
995 system.cpu0.icache.demand_mshr_misses::total 13867412 # number of demand (read+write) MSHR misses
996 system.cpu0.icache.overall_mshr_misses::cpu0.inst 6930034 # number of overall MSHR misses
997 system.cpu0.icache.overall_mshr_misses::cpu1.inst 6937378 # number of overall MSHR misses
998 system.cpu0.icache.overall_mshr_misses::total 13867412 # number of overall MSHR misses
999 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 26185 # number of ReadReq MSHR uncacheable
1000 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 16940 # number of ReadReq MSHR uncacheable
1001 system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
1002 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 26185 # number of overall MSHR uncacheable misses
1003 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 16940 # number of overall MSHR uncacheable misses
1004 system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
1005 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 86336960500 # number of ReadReq MSHR miss cycles
1006 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 85935504000 # number of ReadReq MSHR miss cycles
1007 system.cpu0.icache.ReadReq_mshr_miss_latency::total 172272464500 # number of ReadReq MSHR miss cycles
1008 system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 86336960500 # number of demand (read+write) MSHR miss cycles
1009 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 85935504000 # number of demand (read+write) MSHR miss cycles
1010 system.cpu0.icache.demand_mshr_miss_latency::total 172272464500 # number of demand (read+write) MSHR miss cycles
1011 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 86336960500 # number of overall MSHR miss cycles
1012 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 85935504000 # number of overall MSHR miss cycles
1013 system.cpu0.icache.overall_mshr_miss_latency::total 172272464500 # number of overall MSHR miss cycles
1014 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1959231000 # number of ReadReq MSHR uncacheable cycles
1015 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1269892000 # number of ReadReq MSHR uncacheable cycles
1016 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3229123000 # number of ReadReq MSHR uncacheable cycles
1017 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959231000 # number of overall MSHR uncacheable cycles
1018 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1269892000 # number of overall MSHR uncacheable cycles
1019 system.cpu0.icache.overall_mshr_uncacheable_latency::total 3229123000 # number of overall MSHR uncacheable cycles
1020 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015723 # mshr miss rate for ReadReq accesses
1021 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015726 # mshr miss rate for ReadReq accesses
1022 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015724 # mshr miss rate for ReadReq accesses
1023 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015723 # mshr miss rate for demand accesses
1024 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015726 # mshr miss rate for demand accesses
1025 system.cpu0.icache.demand_mshr_miss_rate::total 0.015724 # mshr miss rate for demand accesses
1026 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015723 # mshr miss rate for overall accesses
1027 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015726 # mshr miss rate for overall accesses
1028 system.cpu0.icache.overall_mshr_miss_rate::total 0.015724 # mshr miss rate for overall accesses
1029 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12458.374735 # average ReadReq mshr miss latency
1030 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average ReadReq mshr miss latency
1031 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12422.827309 # average ReadReq mshr miss latency
1032 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12458.374735 # average overall mshr miss latency
1033 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average overall mshr miss latency
1034 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12422.827309 # average overall mshr miss latency
1035 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12458.374735 # average overall mshr miss latency
1036 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average overall mshr miss latency
1037 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12422.827309 # average overall mshr miss latency
1038 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553 # average ReadReq mshr uncacheable latency
1039 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619 # average ReadReq mshr uncacheable latency
1040 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74878.214493 # average ReadReq mshr uncacheable latency
1041 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553 # average overall mshr uncacheable latency
1042 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619 # average overall mshr uncacheable latency
1043 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74878.214493 # average overall mshr uncacheable latency
1044 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1045 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1046 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1047 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1048 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1049 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1050 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1051 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1052 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1053 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1054 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1055 system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1056 system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1057 system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1058 system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1059 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1060 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1061 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1062 system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1063 system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1064 system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1065 system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1066 system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1067 system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1068 system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1069 system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1070 system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1071 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1072 system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1073 system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1074 system.cpu1.dtb.walker.walks 127806 # Table walker walks requested
1075 system.cpu1.dtb.walker.walksLong 127806 # Table walker walks initiated with long descriptors
1076 system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20371 # Level at which table walker walks with long descriptors terminate
1077 system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91874 # Level at which table walker walks with long descriptors terminate
1078 system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
1079 system.cpu1.dtb.walker.walkWaitTime::samples 127789 # Table walker wait (enqueue to first request) latency
1080 system.cpu1.dtb.walker.walkWaitTime::mean 0.297365 # Table walker wait (enqueue to first request) latency
1081 system.cpu1.dtb.walker.walkWaitTime::stdev 80.104866 # Table walker wait (enqueue to first request) latency
1082 system.cpu1.dtb.walker.walkWaitTime::0-2047 127787 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1083 system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1084 system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1085 system.cpu1.dtb.walker.walkWaitTime::total 127789 # Table walker wait (enqueue to first request) latency
1086 system.cpu1.dtb.walker.walkCompletionTime::samples 112262 # Table walker service (enqueue to completion) latency
1087 system.cpu1.dtb.walker.walkCompletionTime::mean 24820.406727 # Table walker service (enqueue to completion) latency
1088 system.cpu1.dtb.walker.walkCompletionTime::gmean 21828.616459 # Table walker service (enqueue to completion) latency
1089 system.cpu1.dtb.walker.walkCompletionTime::stdev 13574.434559 # Table walker service (enqueue to completion) latency
1090 system.cpu1.dtb.walker.walkCompletionTime::0-32767 72880 64.92% 64.92% # Table walker service (enqueue to completion) latency
1091 system.cpu1.dtb.walker.walkCompletionTime::32768-65535 38528 34.32% 99.24% # Table walker service (enqueue to completion) latency
1092 system.cpu1.dtb.walker.walkCompletionTime::65536-98303 428 0.38% 99.62% # Table walker service (enqueue to completion) latency
1093 system.cpu1.dtb.walker.walkCompletionTime::98304-131071 314 0.28% 99.90% # Table walker service (enqueue to completion) latency
1094 system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.00% 99.90% # Table walker service (enqueue to completion) latency
1095 system.cpu1.dtb.walker.walkCompletionTime::163840-196607 36 0.03% 99.94% # Table walker service (enqueue to completion) latency
1096 system.cpu1.dtb.walker.walkCompletionTime::196608-229375 8 0.01% 99.94% # Table walker service (enqueue to completion) latency
1097 system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency
1098 system.cpu1.dtb.walker.walkCompletionTime::262144-294911 22 0.02% 99.98% # Table walker service (enqueue to completion) latency
1099 system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
1100 system.cpu1.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
1101 system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
1102 system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1103 system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1104 system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1105 system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1106 system.cpu1.dtb.walker.walkCompletionTime::total 112262 # Table walker service (enqueue to completion) latency
1107 system.cpu1.dtb.walker.walksPending::samples 8237382924 # Table walker pending requests distribution
1108 system.cpu1.dtb.walker.walksPending::mean 0.971809 # Table walker pending requests distribution
1109 system.cpu1.dtb.walker.walksPending::stdev 0.165518 # Table walker pending requests distribution
1110 system.cpu1.dtb.walker.walksPending::0 232218204 2.82% 2.82% # Table walker pending requests distribution
1111 system.cpu1.dtb.walker.walksPending::1 8005164720 97.18% 100.00% # Table walker pending requests distribution
1112 system.cpu1.dtb.walker.walksPending::total 8237382924 # Table walker pending requests distribution
1113 system.cpu1.dtb.walker.walkPageSizes::4K 91874 81.85% 81.85% # Table walker page sizes translated
1114 system.cpu1.dtb.walker.walkPageSizes::2M 20371 18.15% 100.00% # Table walker page sizes translated
1115 system.cpu1.dtb.walker.walkPageSizes::total 112245 # Table walker page sizes translated
1116 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127806 # Table walker requests started/completed, data/inst
1117 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1118 system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127806 # Table walker requests started/completed, data/inst
1119 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112245 # Table walker requests started/completed, data/inst
1120 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1121 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112245 # Table walker requests started/completed, data/inst
1122 system.cpu1.dtb.walker.walkRequestOrigin::total 240051 # Table walker requests started/completed, data/inst
1123 system.cpu1.dtb.inst_hits 0 # ITB inst hits
1124 system.cpu1.dtb.inst_misses 0 # ITB inst misses
1125 system.cpu1.dtb.read_hits 82941587 # DTB read hits
1126 system.cpu1.dtb.read_misses 97218 # DTB read misses
1127 system.cpu1.dtb.write_hits 75253518 # DTB write hits
1128 system.cpu1.dtb.write_misses 30588 # DTB write misses
1129 system.cpu1.dtb.flush_tlb 51836 # Number of times complete TLB was flushed
1130 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1131 system.cpu1.dtb.flush_tlb_mva_asid 20662 # Number of times TLB was flushed by MVA & ASID
1132 system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
1133 system.cpu1.dtb.flush_entries 71746 # Number of entries that have been flushed from TLB
1134 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1135 system.cpu1.dtb.prefetch_faults 4678 # Number of TLB faults due to prefetch
1136 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1137 system.cpu1.dtb.perms_faults 9800 # Number of TLB faults due to permissions restrictions
1138 system.cpu1.dtb.read_accesses 83038805 # DTB read accesses
1139 system.cpu1.dtb.write_accesses 75284106 # DTB write accesses
1140 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1141 system.cpu1.dtb.hits 158195105 # DTB hits
1142 system.cpu1.dtb.misses 127806 # DTB misses
1143 system.cpu1.dtb.accesses 158322911 # DTB accesses
1144 system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1145 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1146 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1147 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1148 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1149 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1150 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1151 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1152 system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1153 system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1154 system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1155 system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1156 system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1157 system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1158 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1159 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1160 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1161 system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1162 system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1163 system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1164 system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1165 system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1166 system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1167 system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1168 system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1169 system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1170 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1171 system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1172 system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1173 system.cpu1.itb.walker.walks 77092 # Table walker walks requested
1174 system.cpu1.itb.walker.walksLong 77092 # Table walker walks initiated with long descriptors
1175 system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4382 # Level at which table walker walks with long descriptors terminate
1176 system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67241 # Level at which table walker walks with long descriptors terminate
1177 system.cpu1.itb.walker.walkWaitTime::samples 77092 # Table walker wait (enqueue to first request) latency
1178 system.cpu1.itb.walker.walkWaitTime::0 77092 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1179 system.cpu1.itb.walker.walkWaitTime::total 77092 # Table walker wait (enqueue to first request) latency
1180 system.cpu1.itb.walker.walkCompletionTime::samples 71623 # Table walker service (enqueue to completion) latency
1181 system.cpu1.itb.walker.walkCompletionTime::mean 28009.703587 # Table walker service (enqueue to completion) latency
1182 system.cpu1.itb.walker.walkCompletionTime::gmean 25156.150396 # Table walker service (enqueue to completion) latency
1183 system.cpu1.itb.walker.walkCompletionTime::stdev 15232.175605 # Table walker service (enqueue to completion) latency
1184 system.cpu1.itb.walker.walkCompletionTime::0-32767 36121 50.43% 50.43% # Table walker service (enqueue to completion) latency
1185 system.cpu1.itb.walker.walkCompletionTime::32768-65535 34500 48.17% 98.60% # Table walker service (enqueue to completion) latency
1186 system.cpu1.itb.walker.walkCompletionTime::65536-98303 359 0.50% 99.10% # Table walker service (enqueue to completion) latency
1187 system.cpu1.itb.walker.walkCompletionTime::98304-131071 519 0.72% 99.83% # Table walker service (enqueue to completion) latency
1188 system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency
1189 system.cpu1.itb.walker.walkCompletionTime::163840-196607 46 0.06% 99.90% # Table walker service (enqueue to completion) latency
1190 system.cpu1.itb.walker.walkCompletionTime::196608-229375 17 0.02% 99.93% # Table walker service (enqueue to completion) latency
1191 system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.03% 99.96% # Table walker service (enqueue to completion) latency
1192 system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency
1193 system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
1194 system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
1195 system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
1196 system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1197 system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1198 system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1199 system.cpu1.itb.walker.walkCompletionTime::total 71623 # Table walker service (enqueue to completion) latency
1200 system.cpu1.itb.walker.walksPending::samples -887431296 # Table walker pending requests distribution
1201 system.cpu1.itb.walker.walksPending::0 -887431296 100.00% 100.00% # Table walker pending requests distribution
1202 system.cpu1.itb.walker.walksPending::total -887431296 # Table walker pending requests distribution
1203 system.cpu1.itb.walker.walkPageSizes::4K 67241 93.88% 93.88% # Table walker page sizes translated
1204 system.cpu1.itb.walker.walkPageSizes::2M 4382 6.12% 100.00% # Table walker page sizes translated
1205 system.cpu1.itb.walker.walkPageSizes::total 71623 # Table walker page sizes translated
1206 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1207 system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77092 # Table walker requests started/completed, data/inst
1208 system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77092 # Table walker requests started/completed, data/inst
1209 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1210 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71623 # Table walker requests started/completed, data/inst
1211 system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71623 # Table walker requests started/completed, data/inst
1212 system.cpu1.itb.walker.walkRequestOrigin::total 148715 # Table walker requests started/completed, data/inst
1213 system.cpu1.itb.inst_hits 441142214 # ITB inst hits
1214 system.cpu1.itb.inst_misses 77092 # ITB inst misses
1215 system.cpu1.itb.read_hits 0 # DTB read hits
1216 system.cpu1.itb.read_misses 0 # DTB read misses
1217 system.cpu1.itb.write_hits 0 # DTB write hits
1218 system.cpu1.itb.write_misses 0 # DTB write misses
1219 system.cpu1.itb.flush_tlb 51836 # Number of times complete TLB was flushed
1220 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1221 system.cpu1.itb.flush_tlb_mva_asid 20662 # Number of times TLB was flushed by MVA & ASID
1222 system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
1223 system.cpu1.itb.flush_entries 52225 # Number of entries that have been flushed from TLB
1224 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1225 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1226 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1227 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1228 system.cpu1.itb.read_accesses 0 # DTB read accesses
1229 system.cpu1.itb.write_accesses 0 # DTB write accesses
1230 system.cpu1.itb.inst_accesses 441219306 # ITB inst accesses
1231 system.cpu1.itb.hits 441142214 # DTB hits
1232 system.cpu1.itb.misses 77092 # DTB misses
1233 system.cpu1.itb.accesses 441219306 # DTB accesses
1234 system.cpu1.numCycles 51832427631 # number of cpu cycles simulated
1235 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1236 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1237 system.cpu1.committedInsts 440867885 # Number of instructions committed
1238 system.cpu1.committedOps 517886143 # Number of ops (including micro ops) committed
1239 system.cpu1.num_int_alu_accesses 475513559 # Number of integer alu accesses
1240 system.cpu1.num_fp_alu_accesses 454227 # Number of float alu accesses
1241 system.cpu1.num_func_calls 26111235 # number of times a function call or return occured
1242 system.cpu1.num_conditional_control_insts 67284853 # number of instructions that are conditional controls
1243 system.cpu1.num_int_insts 475513559 # number of integer instructions
1244 system.cpu1.num_fp_insts 454227 # number of float instructions
1245 system.cpu1.num_int_register_reads 692532840 # number of times the integer registers were read
1246 system.cpu1.num_int_register_writes 377153809 # number of times the integer registers were written
1247 system.cpu1.num_fp_register_reads 737892 # number of times the floating registers were read
1248 system.cpu1.num_fp_register_writes 372156 # number of times the floating registers were written
1249 system.cpu1.num_cc_register_reads 115804323 # number of times the CC registers were read
1250 system.cpu1.num_cc_register_writes 115491463 # number of times the CC registers were written
1251 system.cpu1.num_mem_refs 158189082 # number of memory refs
1252 system.cpu1.num_load_insts 82939410 # Number of load instructions
1253 system.cpu1.num_store_insts 75249672 # Number of store instructions
1254 system.cpu1.num_idle_cycles 50245805753.829796 # Number of idle cycles
1255 system.cpu1.num_busy_cycles 1586621877.170202 # Number of busy cycles
1256 system.cpu1.not_idle_fraction 0.030611 # Percentage of non-idle cycles
1257 system.cpu1.idle_fraction 0.969389 # Percentage of idle cycles
1258 system.cpu1.Branches 98435537 # Number of branches fetched
1259 system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
1260 system.cpu1.op_class::IntAlu 358757749 69.23% 69.23% # Class of executed instruction
1261 system.cpu1.op_class::IntMult 1128666 0.22% 69.45% # Class of executed instruction
1262 system.cpu1.op_class::IntDiv 49961 0.01% 69.46% # Class of executed instruction
1263 system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction
1264 system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction
1265 system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction
1266 system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction
1267 system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction
1268 system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction
1269 system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction
1270 system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction
1271 system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction
1272 system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction
1273 system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction
1274 system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction
1275 system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction
1276 system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction
1277 system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction
1278 system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction
1279 system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction
1280 system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction
1281 system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction
1282 system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction
1283 system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction
1284 system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction
1285 system.cpu1.op_class::SimdFloatMisc 51912 0.01% 69.47% # Class of executed instruction
1286 system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction
1287 system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction
1288 system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction
1289 system.cpu1.op_class::MemRead 82939410 16.01% 85.48% # Class of executed instruction
1290 system.cpu1.op_class::MemWrite 75249672 14.52% 100.00% # Class of executed instruction
1291 system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1292 system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1293 system.cpu1.op_class::total 518177412 # Class of executed instruction
1294 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1295 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1296 system.iobus.trans_dist::ReadReq 40326 # Transaction distribution
1297 system.iobus.trans_dist::ReadResp 40326 # Transaction distribution
1298 system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1299 system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1300 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1301 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1302 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1303 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1304 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1305 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1306 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1307 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1308 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1309 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1310 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1311 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1312 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1313 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1314 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1315 system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1316 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231010 # Packet count per connected master and slave (bytes)
1317 system.iobus.pkt_count_system.realview.ide.dma::total 231010 # Packet count per connected master and slave (bytes)
1318 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1319 system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1320 system.iobus.pkt_count::total 353794 # Packet count per connected master and slave (bytes)
1321 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1322 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1323 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1324 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1325 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1326 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1327 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1328 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1329 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1330 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1331 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1332 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1333 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1334 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1335 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1336 system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1337 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334472 # Cumulative packet size per connected master and slave (bytes)
1338 system.iobus.pkt_size_system.realview.ide.dma::total 7334472 # Cumulative packet size per connected master and slave (bytes)
1339 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1340 system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1341 system.iobus.pkt_size::total 7492392 # Cumulative packet size per connected master and slave (bytes)
1342 system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
1343 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1344 system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1345 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1346 system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1347 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1348 system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1349 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1350 system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1351 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1352 system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1353 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1354 system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1355 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1356 system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1357 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1358 system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1359 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1360 system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1361 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1362 system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1363 system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1364 system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1365 system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1366 system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1367 system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1368 system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1369 system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1370 system.iobus.reqLayer27.occupancy 568807378 # Layer occupancy (ticks)
1371 system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1372 system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1373 system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1374 system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1375 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1376 system.iobus.respLayer3.occupancy 147770000 # Layer occupancy (ticks)
1377 system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1378 system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1379 system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1380 system.iocache.tags.replacements 115487 # number of replacements
1381 system.iocache.tags.tagsinuse 10.455201 # Cycle average of tags in use
1382 system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1383 system.iocache.tags.sampled_refs 115503 # Sample count of references to valid blocks.
1384 system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1385 system.iocache.tags.warmup_cycle 13165365743000 # Cycle when the warmup percentage was hit.
1386 system.iocache.tags.occ_blocks::realview.ethernet 3.510018 # Average occupied blocks per requestor
1387 system.iocache.tags.occ_blocks::realview.ide 6.945183 # Average occupied blocks per requestor
1388 system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy
1389 system.iocache.tags.occ_percent::realview.ide 0.434074 # Average percentage of cache occupancy
1390 system.iocache.tags.occ_percent::total 0.653450 # Average percentage of cache occupancy
1391 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1392 system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1393 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1394 system.iocache.tags.tag_accesses 1039902 # Number of tag accesses
1395 system.iocache.tags.data_accesses 1039902 # Number of data accesses
1396 system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1397 system.iocache.ReadReq_misses::realview.ide 8841 # number of ReadReq misses
1398 system.iocache.ReadReq_misses::total 8878 # number of ReadReq misses
1399 system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1400 system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1401 system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1402 system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1403 system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1404 system.iocache.demand_misses::realview.ide 8841 # number of demand (read+write) misses
1405 system.iocache.demand_misses::total 8881 # number of demand (read+write) misses
1406 system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1407 system.iocache.overall_misses::realview.ide 8841 # number of overall misses
1408 system.iocache.overall_misses::total 8881 # number of overall misses
1409 system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
1410 system.iocache.ReadReq_miss_latency::realview.ide 1579254237 # number of ReadReq miss cycles
1411 system.iocache.ReadReq_miss_latency::total 1584323237 # number of ReadReq miss cycles
1412 system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
1413 system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
1414 system.iocache.WriteLineReq_miss_latency::realview.ide 12612931141 # number of WriteLineReq miss cycles
1415 system.iocache.WriteLineReq_miss_latency::total 12612931141 # number of WriteLineReq miss cycles
1416 system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles
1417 system.iocache.demand_miss_latency::realview.ide 1579254237 # number of demand (read+write) miss cycles
1418 system.iocache.demand_miss_latency::total 1584674237 # number of demand (read+write) miss cycles
1419 system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles
1420 system.iocache.overall_miss_latency::realview.ide 1579254237 # number of overall miss cycles
1421 system.iocache.overall_miss_latency::total 1584674237 # number of overall miss cycles
1422 system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1423 system.iocache.ReadReq_accesses::realview.ide 8841 # number of ReadReq accesses(hits+misses)
1424 system.iocache.ReadReq_accesses::total 8878 # number of ReadReq accesses(hits+misses)
1425 system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1426 system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1427 system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
1428 system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
1429 system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1430 system.iocache.demand_accesses::realview.ide 8841 # number of demand (read+write) accesses
1431 system.iocache.demand_accesses::total 8881 # number of demand (read+write) accesses
1432 system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1433 system.iocache.overall_accesses::realview.ide 8841 # number of overall (read+write) accesses
1434 system.iocache.overall_accesses::total 8881 # number of overall (read+write) accesses
1435 system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1436 system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1437 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1438 system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1439 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1440 system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1441 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1442 system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1443 system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1444 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1445 system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1446 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1447 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1448 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
1449 system.iocache.ReadReq_avg_miss_latency::realview.ide 178628.462504 # average ReadReq miss latency
1450 system.iocache.ReadReq_avg_miss_latency::total 178454.971503 # average ReadReq miss latency
1451 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
1452 system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
1453 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118249.185677 # average WriteLineReq miss latency
1454 system.iocache.WriteLineReq_avg_miss_latency::total 118249.185677 # average WriteLineReq miss latency
1455 system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
1456 system.iocache.demand_avg_miss_latency::realview.ide 178628.462504 # average overall miss latency
1457 system.iocache.demand_avg_miss_latency::total 178434.212026 # average overall miss latency
1458 system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
1459 system.iocache.overall_avg_miss_latency::realview.ide 178628.462504 # average overall miss latency
1460 system.iocache.overall_avg_miss_latency::total 178434.212026 # average overall miss latency
1461 system.iocache.blocked_cycles::no_mshrs 30353 # number of cycles access was blocked
1462 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1463 system.iocache.blocked::no_mshrs 3277 # number of cycles access was blocked
1464 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1465 system.iocache.avg_blocked_cycles::no_mshrs 9.262435 # average number of cycles each access was blocked
1466 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1467 system.iocache.fast_writes 0 # number of fast writes performed
1468 system.iocache.cache_copies 0 # number of cache copies performed
1469 system.iocache.writebacks::writebacks 106631 # number of writebacks
1470 system.iocache.writebacks::total 106631 # number of writebacks
1471 system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1472 system.iocache.ReadReq_mshr_misses::realview.ide 8841 # number of ReadReq MSHR misses
1473 system.iocache.ReadReq_mshr_misses::total 8878 # number of ReadReq MSHR misses
1474 system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1475 system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1476 system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
1477 system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
1478 system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1479 system.iocache.demand_mshr_misses::realview.ide 8841 # number of demand (read+write) MSHR misses
1480 system.iocache.demand_mshr_misses::total 8881 # number of demand (read+write) MSHR misses
1481 system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1482 system.iocache.overall_mshr_misses::realview.ide 8841 # number of overall MSHR misses
1483 system.iocache.overall_mshr_misses::total 8881 # number of overall MSHR misses
1484 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
1485 system.iocache.ReadReq_mshr_miss_latency::realview.ide 1137204237 # number of ReadReq MSHR miss cycles
1486 system.iocache.ReadReq_mshr_miss_latency::total 1140423237 # number of ReadReq MSHR miss cycles
1487 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
1488 system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
1489 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279731141 # number of WriteLineReq MSHR miss cycles
1490 system.iocache.WriteLineReq_mshr_miss_latency::total 7279731141 # number of WriteLineReq MSHR miss cycles
1491 system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
1492 system.iocache.demand_mshr_miss_latency::realview.ide 1137204237 # number of demand (read+write) MSHR miss cycles
1493 system.iocache.demand_mshr_miss_latency::total 1140624237 # number of demand (read+write) MSHR miss cycles
1494 system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
1495 system.iocache.overall_mshr_miss_latency::realview.ide 1137204237 # number of overall MSHR miss cycles
1496 system.iocache.overall_mshr_miss_latency::total 1140624237 # number of overall MSHR miss cycles
1497 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1498 system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1499 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1500 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1501 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1502 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1503 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1504 system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1505 system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1506 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1507 system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1508 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1509 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1510 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
1511 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 128628.462504 # average ReadReq mshr miss latency
1512 system.iocache.ReadReq_avg_mshr_miss_latency::total 128454.971503 # average ReadReq mshr miss latency
1513 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
1514 system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
1515 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68249.185677 # average WriteLineReq mshr miss latency
1516 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68249.185677 # average WriteLineReq mshr miss latency
1517 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
1518 system.iocache.demand_avg_mshr_miss_latency::realview.ide 128628.462504 # average overall mshr miss latency
1519 system.iocache.demand_avg_mshr_miss_latency::total 128434.212026 # average overall mshr miss latency
1520 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
1521 system.iocache.overall_avg_mshr_miss_latency::realview.ide 128628.462504 # average overall mshr miss latency
1522 system.iocache.overall_avg_mshr_miss_latency::total 128434.212026 # average overall mshr miss latency
1523 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1524 system.l2c.tags.replacements 1260623 # number of replacements
1525 system.l2c.tags.tagsinuse 65280.532461 # Cycle average of tags in use
1526 system.l2c.tags.total_refs 43887253 # Total number of references to valid blocks.
1527 system.l2c.tags.sampled_refs 1323818 # Sample count of references to valid blocks.
1528 system.l2c.tags.avg_refs 33.152029 # Average number of references to valid blocks.
1529 system.l2c.tags.warmup_cycle 38344006500 # Cycle when the warmup percentage was hit.
1530 system.l2c.tags.occ_blocks::writebacks 38235.631490 # Average occupied blocks per requestor
1531 system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.327159 # Average occupied blocks per requestor
1532 system.l2c.tags.occ_blocks::cpu0.itb.walker 255.763508 # Average occupied blocks per requestor
1533 system.l2c.tags.occ_blocks::cpu0.inst 4002.247331 # Average occupied blocks per requestor
1534 system.l2c.tags.occ_blocks::cpu0.data 10061.721412 # Average occupied blocks per requestor
1535 system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.225182 # Average occupied blocks per requestor
1536 system.l2c.tags.occ_blocks::cpu1.itb.walker 222.893104 # Average occupied blocks per requestor
1537 system.l2c.tags.occ_blocks::cpu1.inst 2612.785728 # Average occupied blocks per requestor
1538 system.l2c.tags.occ_blocks::cpu1.data 9555.937547 # Average occupied blocks per requestor
1539 system.l2c.tags.occ_percent::writebacks 0.583429 # Average percentage of cache occupancy
1540 system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002950 # Average percentage of cache occupancy
1541 system.l2c.tags.occ_percent::cpu0.itb.walker 0.003903 # Average percentage of cache occupancy
1542 system.l2c.tags.occ_percent::cpu0.inst 0.061069 # Average percentage of cache occupancy
1543 system.l2c.tags.occ_percent::cpu0.data 0.153530 # Average percentage of cache occupancy
1544 system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002140 # Average percentage of cache occupancy
1545 system.l2c.tags.occ_percent::cpu1.itb.walker 0.003401 # Average percentage of cache occupancy
1546 system.l2c.tags.occ_percent::cpu1.inst 0.039868 # Average percentage of cache occupancy
1547 system.l2c.tags.occ_percent::cpu1.data 0.145812 # Average percentage of cache occupancy
1548 system.l2c.tags.occ_percent::total 0.996102 # Average percentage of cache occupancy
1549 system.l2c.tags.occ_task_id_blocks::1023 327 # Occupied blocks per task id
1550 system.l2c.tags.occ_task_id_blocks::1024 62868 # Occupied blocks per task id
1551 system.l2c.tags.age_task_id_blocks_1023::4 327 # Occupied blocks per task id
1552 system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
1553 system.l2c.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
1554 system.l2c.tags.age_task_id_blocks_1024::2 2451 # Occupied blocks per task id
1555 system.l2c.tags.age_task_id_blocks_1024::3 5488 # Occupied blocks per task id
1556 system.l2c.tags.age_task_id_blocks_1024::4 54479 # Occupied blocks per task id
1557 system.l2c.tags.occ_task_id_percent::1023 0.004990 # Percentage of cache occupancy per task id
1558 system.l2c.tags.occ_task_id_percent::1024 0.959290 # Percentage of cache occupancy per task id
1559 system.l2c.tags.tag_accesses 393981982 # Number of tag accesses
1560 system.l2c.tags.data_accesses 393981982 # Number of data accesses
1561 system.l2c.ReadReq_hits::cpu0.dtb.walker 238329 # number of ReadReq hits
1562 system.l2c.ReadReq_hits::cpu0.itb.walker 162891 # number of ReadReq hits
1563 system.l2c.ReadReq_hits::cpu1.dtb.walker 232955 # number of ReadReq hits
1564 system.l2c.ReadReq_hits::cpu1.itb.walker 163054 # number of ReadReq hits
1565 system.l2c.ReadReq_hits::total 797229 # number of ReadReq hits
1566 system.l2c.Writeback_hits::writebacks 7725236 # number of Writeback hits
1567 system.l2c.Writeback_hits::total 7725236 # number of Writeback hits
1568 system.l2c.UpgradeReq_hits::cpu0.data 4940 # number of UpgradeReq hits
1569 system.l2c.UpgradeReq_hits::cpu1.data 4801 # number of UpgradeReq hits
1570 system.l2c.UpgradeReq_hits::total 9741 # number of UpgradeReq hits
1571 system.l2c.ReadExReq_hits::cpu0.data 806406 # number of ReadExReq hits
1572 system.l2c.ReadExReq_hits::cpu1.data 815086 # number of ReadExReq hits
1573 system.l2c.ReadExReq_hits::total 1621492 # number of ReadExReq hits
1574 system.l2c.ReadCleanReq_hits::cpu0.inst 6885661 # number of ReadCleanReq hits
1575 system.l2c.ReadCleanReq_hits::cpu1.inst 6899737 # number of ReadCleanReq hits
1576 system.l2c.ReadCleanReq_hits::total 13785398 # number of ReadCleanReq hits
1577 system.l2c.ReadSharedReq_hits::cpu0.data 3189949 # number of ReadSharedReq hits
1578 system.l2c.ReadSharedReq_hits::cpu1.data 3243555 # number of ReadSharedReq hits
1579 system.l2c.ReadSharedReq_hits::total 6433504 # number of ReadSharedReq hits
1580 system.l2c.InvalidateReq_hits::cpu0.data 361245 # number of InvalidateReq hits
1581 system.l2c.InvalidateReq_hits::cpu1.data 357794 # number of InvalidateReq hits
1582 system.l2c.InvalidateReq_hits::total 719039 # number of InvalidateReq hits
1583 system.l2c.demand_hits::cpu0.dtb.walker 238329 # number of demand (read+write) hits
1584 system.l2c.demand_hits::cpu0.itb.walker 162891 # number of demand (read+write) hits
1585 system.l2c.demand_hits::cpu0.inst 6885661 # number of demand (read+write) hits
1586 system.l2c.demand_hits::cpu0.data 3996355 # number of demand (read+write) hits
1587 system.l2c.demand_hits::cpu1.dtb.walker 232955 # number of demand (read+write) hits
1588 system.l2c.demand_hits::cpu1.itb.walker 163054 # number of demand (read+write) hits
1589 system.l2c.demand_hits::cpu1.inst 6899737 # number of demand (read+write) hits
1590 system.l2c.demand_hits::cpu1.data 4058641 # number of demand (read+write) hits
1591 system.l2c.demand_hits::total 22637623 # number of demand (read+write) hits
1592 system.l2c.overall_hits::cpu0.dtb.walker 238329 # number of overall hits
1593 system.l2c.overall_hits::cpu0.itb.walker 162891 # number of overall hits
1594 system.l2c.overall_hits::cpu0.inst 6885661 # number of overall hits
1595 system.l2c.overall_hits::cpu0.data 3996355 # number of overall hits
1596 system.l2c.overall_hits::cpu1.dtb.walker 232955 # number of overall hits
1597 system.l2c.overall_hits::cpu1.itb.walker 163054 # number of overall hits
1598 system.l2c.overall_hits::cpu1.inst 6899737 # number of overall hits
1599 system.l2c.overall_hits::cpu1.data 4058641 # number of overall hits
1600 system.l2c.overall_hits::total 22637623 # number of overall hits
1601 system.l2c.ReadReq_misses::cpu0.dtb.walker 2095 # number of ReadReq misses
1602 system.l2c.ReadReq_misses::cpu0.itb.walker 2039 # number of ReadReq misses
1603 system.l2c.ReadReq_misses::cpu1.dtb.walker 1858 # number of ReadReq misses
1604 system.l2c.ReadReq_misses::cpu1.itb.walker 1828 # number of ReadReq misses
1605 system.l2c.ReadReq_misses::total 7820 # number of ReadReq misses
1606 system.l2c.UpgradeReq_misses::cpu0.data 17709 # number of UpgradeReq misses
1607 system.l2c.UpgradeReq_misses::cpu1.data 17217 # number of UpgradeReq misses
1608 system.l2c.UpgradeReq_misses::total 34926 # number of UpgradeReq misses
1609 system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
1610 system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
1611 system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
1612 system.l2c.ReadExReq_misses::cpu0.data 242663 # number of ReadExReq misses
1613 system.l2c.ReadExReq_misses::cpu1.data 238702 # number of ReadExReq misses
1614 system.l2c.ReadExReq_misses::total 481365 # number of ReadExReq misses
1615 system.l2c.ReadCleanReq_misses::cpu0.inst 44373 # number of ReadCleanReq misses
1616 system.l2c.ReadCleanReq_misses::cpu1.inst 37641 # number of ReadCleanReq misses
1617 system.l2c.ReadCleanReq_misses::total 82014 # number of ReadCleanReq misses
1618 system.l2c.ReadSharedReq_misses::cpu0.data 136062 # number of ReadSharedReq misses
1619 system.l2c.ReadSharedReq_misses::cpu1.data 137237 # number of ReadSharedReq misses
1620 system.l2c.ReadSharedReq_misses::total 273299 # number of ReadSharedReq misses
1621 system.l2c.InvalidateReq_misses::cpu0.data 251584 # number of InvalidateReq misses
1622 system.l2c.InvalidateReq_misses::cpu1.data 258191 # number of InvalidateReq misses
1623 system.l2c.InvalidateReq_misses::total 509775 # number of InvalidateReq misses
1624 system.l2c.demand_misses::cpu0.dtb.walker 2095 # number of demand (read+write) misses
1625 system.l2c.demand_misses::cpu0.itb.walker 2039 # number of demand (read+write) misses
1626 system.l2c.demand_misses::cpu0.inst 44373 # number of demand (read+write) misses
1627 system.l2c.demand_misses::cpu0.data 378725 # number of demand (read+write) misses
1628 system.l2c.demand_misses::cpu1.dtb.walker 1858 # number of demand (read+write) misses
1629 system.l2c.demand_misses::cpu1.itb.walker 1828 # number of demand (read+write) misses
1630 system.l2c.demand_misses::cpu1.inst 37641 # number of demand (read+write) misses
1631 system.l2c.demand_misses::cpu1.data 375939 # number of demand (read+write) misses
1632 system.l2c.demand_misses::total 844498 # number of demand (read+write) misses
1633 system.l2c.overall_misses::cpu0.dtb.walker 2095 # number of overall misses
1634 system.l2c.overall_misses::cpu0.itb.walker 2039 # number of overall misses
1635 system.l2c.overall_misses::cpu0.inst 44373 # number of overall misses
1636 system.l2c.overall_misses::cpu0.data 378725 # number of overall misses
1637 system.l2c.overall_misses::cpu1.dtb.walker 1858 # number of overall misses
1638 system.l2c.overall_misses::cpu1.itb.walker 1828 # number of overall misses
1639 system.l2c.overall_misses::cpu1.inst 37641 # number of overall misses
1640 system.l2c.overall_misses::cpu1.data 375939 # number of overall misses
1641 system.l2c.overall_misses::total 844498 # number of overall misses
1642 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 179866500 # number of ReadReq miss cycles
1643 system.l2c.ReadReq_miss_latency::cpu0.itb.walker 180146000 # number of ReadReq miss cycles
1644 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 162156000 # number of ReadReq miss cycles
1645 system.l2c.ReadReq_miss_latency::cpu1.itb.walker 158214500 # number of ReadReq miss cycles
1646 system.l2c.ReadReq_miss_latency::total 680383000 # number of ReadReq miss cycles
1647 system.l2c.UpgradeReq_miss_latency::cpu0.data 276798500 # number of UpgradeReq miss cycles
1648 system.l2c.UpgradeReq_miss_latency::cpu1.data 263076500 # number of UpgradeReq miss cycles
1649 system.l2c.UpgradeReq_miss_latency::total 539875000 # number of UpgradeReq miss cycles
1650 system.l2c.SCUpgradeReq_miss_latency::cpu0.data 79500 # number of SCUpgradeReq miss cycles
1651 system.l2c.SCUpgradeReq_miss_latency::cpu1.data 30500 # number of SCUpgradeReq miss cycles
1652 system.l2c.SCUpgradeReq_miss_latency::total 110000 # number of SCUpgradeReq miss cycles
1653 system.l2c.ReadExReq_miss_latency::cpu0.data 19543422000 # number of ReadExReq miss cycles
1654 system.l2c.ReadExReq_miss_latency::cpu1.data 19220420500 # number of ReadExReq miss cycles
1655 system.l2c.ReadExReq_miss_latency::total 38763842500 # number of ReadExReq miss cycles
1656 system.l2c.ReadCleanReq_miss_latency::cpu0.inst 3621036000 # number of ReadCleanReq miss cycles
1657 system.l2c.ReadCleanReq_miss_latency::cpu1.inst 3060803500 # number of ReadCleanReq miss cycles
1658 system.l2c.ReadCleanReq_miss_latency::total 6681839500 # number of ReadCleanReq miss cycles
1659 system.l2c.ReadSharedReq_miss_latency::cpu0.data 11298249500 # number of ReadSharedReq miss cycles
1660 system.l2c.ReadSharedReq_miss_latency::cpu1.data 11397176000 # number of ReadSharedReq miss cycles
1661 system.l2c.ReadSharedReq_miss_latency::total 22695425500 # number of ReadSharedReq miss cycles
1662 system.l2c.InvalidateReq_miss_latency::cpu0.data 19886204500 # number of InvalidateReq miss cycles
1663 system.l2c.InvalidateReq_miss_latency::cpu1.data 20428221500 # number of InvalidateReq miss cycles
1664 system.l2c.InvalidateReq_miss_latency::total 40314426000 # number of InvalidateReq miss cycles
1665 system.l2c.demand_miss_latency::cpu0.dtb.walker 179866500 # number of demand (read+write) miss cycles
1666 system.l2c.demand_miss_latency::cpu0.itb.walker 180146000 # number of demand (read+write) miss cycles
1667 system.l2c.demand_miss_latency::cpu0.inst 3621036000 # number of demand (read+write) miss cycles
1668 system.l2c.demand_miss_latency::cpu0.data 30841671500 # number of demand (read+write) miss cycles
1669 system.l2c.demand_miss_latency::cpu1.dtb.walker 162156000 # number of demand (read+write) miss cycles
1670 system.l2c.demand_miss_latency::cpu1.itb.walker 158214500 # number of demand (read+write) miss cycles
1671 system.l2c.demand_miss_latency::cpu1.inst 3060803500 # number of demand (read+write) miss cycles
1672 system.l2c.demand_miss_latency::cpu1.data 30617596500 # number of demand (read+write) miss cycles
1673 system.l2c.demand_miss_latency::total 68821490500 # number of demand (read+write) miss cycles
1674 system.l2c.overall_miss_latency::cpu0.dtb.walker 179866500 # number of overall miss cycles
1675 system.l2c.overall_miss_latency::cpu0.itb.walker 180146000 # number of overall miss cycles
1676 system.l2c.overall_miss_latency::cpu0.inst 3621036000 # number of overall miss cycles
1677 system.l2c.overall_miss_latency::cpu0.data 30841671500 # number of overall miss cycles
1678 system.l2c.overall_miss_latency::cpu1.dtb.walker 162156000 # number of overall miss cycles
1679 system.l2c.overall_miss_latency::cpu1.itb.walker 158214500 # number of overall miss cycles
1680 system.l2c.overall_miss_latency::cpu1.inst 3060803500 # number of overall miss cycles
1681 system.l2c.overall_miss_latency::cpu1.data 30617596500 # number of overall miss cycles
1682 system.l2c.overall_miss_latency::total 68821490500 # number of overall miss cycles
1683 system.l2c.ReadReq_accesses::cpu0.dtb.walker 240424 # number of ReadReq accesses(hits+misses)
1684 system.l2c.ReadReq_accesses::cpu0.itb.walker 164930 # number of ReadReq accesses(hits+misses)
1685 system.l2c.ReadReq_accesses::cpu1.dtb.walker 234813 # number of ReadReq accesses(hits+misses)
1686 system.l2c.ReadReq_accesses::cpu1.itb.walker 164882 # number of ReadReq accesses(hits+misses)
1687 system.l2c.ReadReq_accesses::total 805049 # number of ReadReq accesses(hits+misses)
1688 system.l2c.Writeback_accesses::writebacks 7725236 # number of Writeback accesses(hits+misses)
1689 system.l2c.Writeback_accesses::total 7725236 # number of Writeback accesses(hits+misses)
1690 system.l2c.UpgradeReq_accesses::cpu0.data 22649 # number of UpgradeReq accesses(hits+misses)
1691 system.l2c.UpgradeReq_accesses::cpu1.data 22018 # number of UpgradeReq accesses(hits+misses)
1692 system.l2c.UpgradeReq_accesses::total 44667 # number of UpgradeReq accesses(hits+misses)
1693 system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
1694 system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
1695 system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
1696 system.l2c.ReadExReq_accesses::cpu0.data 1049069 # number of ReadExReq accesses(hits+misses)
1697 system.l2c.ReadExReq_accesses::cpu1.data 1053788 # number of ReadExReq accesses(hits+misses)
1698 system.l2c.ReadExReq_accesses::total 2102857 # number of ReadExReq accesses(hits+misses)
1699 system.l2c.ReadCleanReq_accesses::cpu0.inst 6930034 # number of ReadCleanReq accesses(hits+misses)
1700 system.l2c.ReadCleanReq_accesses::cpu1.inst 6937378 # number of ReadCleanReq accesses(hits+misses)
1701 system.l2c.ReadCleanReq_accesses::total 13867412 # number of ReadCleanReq accesses(hits+misses)
1702 system.l2c.ReadSharedReq_accesses::cpu0.data 3326011 # number of ReadSharedReq accesses(hits+misses)
1703 system.l2c.ReadSharedReq_accesses::cpu1.data 3380792 # number of ReadSharedReq accesses(hits+misses)
1704 system.l2c.ReadSharedReq_accesses::total 6706803 # number of ReadSharedReq accesses(hits+misses)
1705 system.l2c.InvalidateReq_accesses::cpu0.data 612829 # number of InvalidateReq accesses(hits+misses)
1706 system.l2c.InvalidateReq_accesses::cpu1.data 615985 # number of InvalidateReq accesses(hits+misses)
1707 system.l2c.InvalidateReq_accesses::total 1228814 # number of InvalidateReq accesses(hits+misses)
1708 system.l2c.demand_accesses::cpu0.dtb.walker 240424 # number of demand (read+write) accesses
1709 system.l2c.demand_accesses::cpu0.itb.walker 164930 # number of demand (read+write) accesses
1710 system.l2c.demand_accesses::cpu0.inst 6930034 # number of demand (read+write) accesses
1711 system.l2c.demand_accesses::cpu0.data 4375080 # number of demand (read+write) accesses
1712 system.l2c.demand_accesses::cpu1.dtb.walker 234813 # number of demand (read+write) accesses
1713 system.l2c.demand_accesses::cpu1.itb.walker 164882 # number of demand (read+write) accesses
1714 system.l2c.demand_accesses::cpu1.inst 6937378 # number of demand (read+write) accesses
1715 system.l2c.demand_accesses::cpu1.data 4434580 # number of demand (read+write) accesses
1716 system.l2c.demand_accesses::total 23482121 # number of demand (read+write) accesses
1717 system.l2c.overall_accesses::cpu0.dtb.walker 240424 # number of overall (read+write) accesses
1718 system.l2c.overall_accesses::cpu0.itb.walker 164930 # number of overall (read+write) accesses
1719 system.l2c.overall_accesses::cpu0.inst 6930034 # number of overall (read+write) accesses
1720 system.l2c.overall_accesses::cpu0.data 4375080 # number of overall (read+write) accesses
1721 system.l2c.overall_accesses::cpu1.dtb.walker 234813 # number of overall (read+write) accesses
1722 system.l2c.overall_accesses::cpu1.itb.walker 164882 # number of overall (read+write) accesses
1723 system.l2c.overall_accesses::cpu1.inst 6937378 # number of overall (read+write) accesses
1724 system.l2c.overall_accesses::cpu1.data 4434580 # number of overall (read+write) accesses
1725 system.l2c.overall_accesses::total 23482121 # number of overall (read+write) accesses
1726 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.008714 # miss rate for ReadReq accesses
1727 system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012363 # miss rate for ReadReq accesses
1728 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.007913 # miss rate for ReadReq accesses
1729 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011087 # miss rate for ReadReq accesses
1730 system.l2c.ReadReq_miss_rate::total 0.009714 # miss rate for ReadReq accesses
1731 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.781889 # miss rate for UpgradeReq accesses
1732 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781951 # miss rate for UpgradeReq accesses
1733 system.l2c.UpgradeReq_miss_rate::total 0.781920 # miss rate for UpgradeReq accesses
1734 system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1735 system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1736 system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1737 system.l2c.ReadExReq_miss_rate::cpu0.data 0.231313 # miss rate for ReadExReq accesses
1738 system.l2c.ReadExReq_miss_rate::cpu1.data 0.226518 # miss rate for ReadExReq accesses
1739 system.l2c.ReadExReq_miss_rate::total 0.228910 # miss rate for ReadExReq accesses
1740 system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006403 # miss rate for ReadCleanReq accesses
1741 system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005426 # miss rate for ReadCleanReq accesses
1742 system.l2c.ReadCleanReq_miss_rate::total 0.005914 # miss rate for ReadCleanReq accesses
1743 system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.040908 # miss rate for ReadSharedReq accesses
1744 system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.040593 # miss rate for ReadSharedReq accesses
1745 system.l2c.ReadSharedReq_miss_rate::total 0.040750 # miss rate for ReadSharedReq accesses
1746 system.l2c.InvalidateReq_miss_rate::cpu0.data 0.410529 # miss rate for InvalidateReq accesses
1747 system.l2c.InvalidateReq_miss_rate::cpu1.data 0.419151 # miss rate for InvalidateReq accesses
1748 system.l2c.InvalidateReq_miss_rate::total 0.414851 # miss rate for InvalidateReq accesses
1749 system.l2c.demand_miss_rate::cpu0.dtb.walker 0.008714 # miss rate for demand accesses
1750 system.l2c.demand_miss_rate::cpu0.itb.walker 0.012363 # miss rate for demand accesses
1751 system.l2c.demand_miss_rate::cpu0.inst 0.006403 # miss rate for demand accesses
1752 system.l2c.demand_miss_rate::cpu0.data 0.086564 # miss rate for demand accesses
1753 system.l2c.demand_miss_rate::cpu1.dtb.walker 0.007913 # miss rate for demand accesses
1754 system.l2c.demand_miss_rate::cpu1.itb.walker 0.011087 # miss rate for demand accesses
1755 system.l2c.demand_miss_rate::cpu1.inst 0.005426 # miss rate for demand accesses
1756 system.l2c.demand_miss_rate::cpu1.data 0.084774 # miss rate for demand accesses
1757 system.l2c.demand_miss_rate::total 0.035963 # miss rate for demand accesses
1758 system.l2c.overall_miss_rate::cpu0.dtb.walker 0.008714 # miss rate for overall accesses
1759 system.l2c.overall_miss_rate::cpu0.itb.walker 0.012363 # miss rate for overall accesses
1760 system.l2c.overall_miss_rate::cpu0.inst 0.006403 # miss rate for overall accesses
1761 system.l2c.overall_miss_rate::cpu0.data 0.086564 # miss rate for overall accesses
1762 system.l2c.overall_miss_rate::cpu1.dtb.walker 0.007913 # miss rate for overall accesses
1763 system.l2c.overall_miss_rate::cpu1.itb.walker 0.011087 # miss rate for overall accesses
1764 system.l2c.overall_miss_rate::cpu1.inst 0.005426 # miss rate for overall accesses
1765 system.l2c.overall_miss_rate::cpu1.data 0.084774 # miss rate for overall accesses
1766 system.l2c.overall_miss_rate::total 0.035963 # miss rate for overall accesses
1767 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85855.131265 # average ReadReq miss latency
1768 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88350.171653 # average ReadReq miss latency
1769 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87274.488698 # average ReadReq miss latency
1770 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86550.601751 # average ReadReq miss latency
1771 system.l2c.ReadReq_avg_miss_latency::total 87005.498721 # average ReadReq miss latency
1772 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15630.385680 # average UpgradeReq miss latency
1773 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15280.042981 # average UpgradeReq miss latency
1774 system.l2c.UpgradeReq_avg_miss_latency::total 15457.681956 # average UpgradeReq miss latency
1775 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency
1776 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 30500 # average SCUpgradeReq miss latency
1777 system.l2c.SCUpgradeReq_avg_miss_latency::total 55000 # average SCUpgradeReq miss latency
1778 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80537.296580 # average ReadExReq miss latency
1779 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80520.567486 # average ReadExReq miss latency
1780 system.l2c.ReadExReq_avg_miss_latency::total 80529.000862 # average ReadExReq miss latency
1781 system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81604.489216 # average ReadCleanReq miss latency
1782 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81315.679711 # average ReadCleanReq miss latency
1783 system.l2c.ReadCleanReq_avg_miss_latency::total 81471.937718 # average ReadCleanReq miss latency
1784 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 83037.508636 # average ReadSharedReq miss latency
1785 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83047.399754 # average ReadSharedReq miss latency
1786 system.l2c.ReadSharedReq_avg_miss_latency::total 83042.475457 # average ReadSharedReq miss latency
1787 system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 79043.995246 # average InvalidateReq miss latency
1788 system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79120.579339 # average InvalidateReq miss latency
1789 system.l2c.InvalidateReq_avg_miss_latency::total 79082.783581 # average InvalidateReq miss latency
1790 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85855.131265 # average overall miss latency
1791 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88350.171653 # average overall miss latency
1792 system.l2c.demand_avg_miss_latency::cpu0.inst 81604.489216 # average overall miss latency
1793 system.l2c.demand_avg_miss_latency::cpu0.data 81435.531058 # average overall miss latency
1794 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87274.488698 # average overall miss latency
1795 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86550.601751 # average overall miss latency
1796 system.l2c.demand_avg_miss_latency::cpu1.inst 81315.679711 # average overall miss latency
1797 system.l2c.demand_avg_miss_latency::cpu1.data 81442.990751 # average overall miss latency
1798 system.l2c.demand_avg_miss_latency::total 81493.965054 # average overall miss latency
1799 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85855.131265 # average overall miss latency
1800 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88350.171653 # average overall miss latency
1801 system.l2c.overall_avg_miss_latency::cpu0.inst 81604.489216 # average overall miss latency
1802 system.l2c.overall_avg_miss_latency::cpu0.data 81435.531058 # average overall miss latency
1803 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87274.488698 # average overall miss latency
1804 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86550.601751 # average overall miss latency
1805 system.l2c.overall_avg_miss_latency::cpu1.inst 81315.679711 # average overall miss latency
1806 system.l2c.overall_avg_miss_latency::cpu1.data 81442.990751 # average overall miss latency
1807 system.l2c.overall_avg_miss_latency::total 81493.965054 # average overall miss latency
1808 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1809 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1810 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1811 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1812 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1813 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1814 system.l2c.fast_writes 0 # number of fast writes performed
1815 system.l2c.cache_copies 0 # number of cache copies performed
1816 system.l2c.writebacks::writebacks 1074796 # number of writebacks
1817 system.l2c.writebacks::total 1074796 # number of writebacks
1818 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2095 # number of ReadReq MSHR misses
1819 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2039 # number of ReadReq MSHR misses
1820 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1858 # number of ReadReq MSHR misses
1821 system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1828 # number of ReadReq MSHR misses
1822 system.l2c.ReadReq_mshr_misses::total 7820 # number of ReadReq MSHR misses
1823 system.l2c.CleanEvict_mshr_misses::writebacks 1119 # number of CleanEvict MSHR misses
1824 system.l2c.CleanEvict_mshr_misses::total 1119 # number of CleanEvict MSHR misses
1825 system.l2c.UpgradeReq_mshr_misses::cpu0.data 17709 # number of UpgradeReq MSHR misses
1826 system.l2c.UpgradeReq_mshr_misses::cpu1.data 17217 # number of UpgradeReq MSHR misses
1827 system.l2c.UpgradeReq_mshr_misses::total 34926 # number of UpgradeReq MSHR misses
1828 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
1829 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
1830 system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1831 system.l2c.ReadExReq_mshr_misses::cpu0.data 242663 # number of ReadExReq MSHR misses
1832 system.l2c.ReadExReq_mshr_misses::cpu1.data 238702 # number of ReadExReq MSHR misses
1833 system.l2c.ReadExReq_mshr_misses::total 481365 # number of ReadExReq MSHR misses
1834 system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 44373 # number of ReadCleanReq MSHR misses
1835 system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 37641 # number of ReadCleanReq MSHR misses
1836 system.l2c.ReadCleanReq_mshr_misses::total 82014 # number of ReadCleanReq MSHR misses
1837 system.l2c.ReadSharedReq_mshr_misses::cpu0.data 136062 # number of ReadSharedReq MSHR misses
1838 system.l2c.ReadSharedReq_mshr_misses::cpu1.data 137237 # number of ReadSharedReq MSHR misses
1839 system.l2c.ReadSharedReq_mshr_misses::total 273299 # number of ReadSharedReq MSHR misses
1840 system.l2c.InvalidateReq_mshr_misses::cpu0.data 251584 # number of InvalidateReq MSHR misses
1841 system.l2c.InvalidateReq_mshr_misses::cpu1.data 258191 # number of InvalidateReq MSHR misses
1842 system.l2c.InvalidateReq_mshr_misses::total 509775 # number of InvalidateReq MSHR misses
1843 system.l2c.demand_mshr_misses::cpu0.dtb.walker 2095 # number of demand (read+write) MSHR misses
1844 system.l2c.demand_mshr_misses::cpu0.itb.walker 2039 # number of demand (read+write) MSHR misses
1845 system.l2c.demand_mshr_misses::cpu0.inst 44373 # number of demand (read+write) MSHR misses
1846 system.l2c.demand_mshr_misses::cpu0.data 378725 # number of demand (read+write) MSHR misses
1847 system.l2c.demand_mshr_misses::cpu1.dtb.walker 1858 # number of demand (read+write) MSHR misses
1848 system.l2c.demand_mshr_misses::cpu1.itb.walker 1828 # number of demand (read+write) MSHR misses
1849 system.l2c.demand_mshr_misses::cpu1.inst 37641 # number of demand (read+write) MSHR misses
1850 system.l2c.demand_mshr_misses::cpu1.data 375939 # number of demand (read+write) MSHR misses
1851 system.l2c.demand_mshr_misses::total 844498 # number of demand (read+write) MSHR misses
1852 system.l2c.overall_mshr_misses::cpu0.dtb.walker 2095 # number of overall MSHR misses
1853 system.l2c.overall_mshr_misses::cpu0.itb.walker 2039 # number of overall MSHR misses
1854 system.l2c.overall_mshr_misses::cpu0.inst 44373 # number of overall MSHR misses
1855 system.l2c.overall_mshr_misses::cpu0.data 378725 # number of overall MSHR misses
1856 system.l2c.overall_mshr_misses::cpu1.dtb.walker 1858 # number of overall MSHR misses
1857 system.l2c.overall_mshr_misses::cpu1.itb.walker 1828 # number of overall MSHR misses
1858 system.l2c.overall_mshr_misses::cpu1.inst 37641 # number of overall MSHR misses
1859 system.l2c.overall_mshr_misses::cpu1.data 375939 # number of overall MSHR misses
1860 system.l2c.overall_mshr_misses::total 844498 # number of overall MSHR misses
1861 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 26185 # number of ReadReq MSHR uncacheable
1862 system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17286 # number of ReadReq MSHR uncacheable
1863 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 16940 # number of ReadReq MSHR uncacheable
1864 system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16418 # number of ReadReq MSHR uncacheable
1865 system.l2c.ReadReq_mshr_uncacheable::total 76829 # number of ReadReq MSHR uncacheable
1866 system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16057 # number of WriteReq MSHR uncacheable
1867 system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17652 # number of WriteReq MSHR uncacheable
1868 system.l2c.WriteReq_mshr_uncacheable::total 33709 # number of WriteReq MSHR uncacheable
1869 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 26185 # number of overall MSHR uncacheable misses
1870 system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33343 # number of overall MSHR uncacheable misses
1871 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 16940 # number of overall MSHR uncacheable misses
1872 system.l2c.overall_mshr_uncacheable_misses::cpu1.data 34070 # number of overall MSHR uncacheable misses
1873 system.l2c.overall_mshr_uncacheable_misses::total 110538 # number of overall MSHR uncacheable misses
1874 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158916500 # number of ReadReq MSHR miss cycles
1875 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 159756000 # number of ReadReq MSHR miss cycles
1876 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 143576000 # number of ReadReq MSHR miss cycles
1877 system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 139934500 # number of ReadReq MSHR miss cycles
1878 system.l2c.ReadReq_mshr_miss_latency::total 602183000 # number of ReadReq MSHR miss cycles
1879 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 365788000 # number of UpgradeReq MSHR miss cycles
1880 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 355619500 # number of UpgradeReq MSHR miss cycles
1881 system.l2c.UpgradeReq_mshr_miss_latency::total 721407500 # number of UpgradeReq MSHR miss cycles
1882 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 69500 # number of SCUpgradeReq MSHR miss cycles
1883 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20500 # number of SCUpgradeReq MSHR miss cycles
1884 system.l2c.SCUpgradeReq_mshr_miss_latency::total 90000 # number of SCUpgradeReq MSHR miss cycles
1885 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 17116792000 # number of ReadExReq MSHR miss cycles
1886 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16833400500 # number of ReadExReq MSHR miss cycles
1887 system.l2c.ReadExReq_mshr_miss_latency::total 33950192500 # number of ReadExReq MSHR miss cycles
1888 system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 3177306000 # number of ReadCleanReq MSHR miss cycles
1889 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 2684393500 # number of ReadCleanReq MSHR miss cycles
1890 system.l2c.ReadCleanReq_mshr_miss_latency::total 5861699500 # number of ReadCleanReq MSHR miss cycles
1891 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 9937629500 # number of ReadSharedReq MSHR miss cycles
1892 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10024806000 # number of ReadSharedReq MSHR miss cycles
1893 system.l2c.ReadSharedReq_mshr_miss_latency::total 19962435500 # number of ReadSharedReq MSHR miss cycles
1894 system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 17370364500 # number of InvalidateReq MSHR miss cycles
1895 system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 17846311500 # number of InvalidateReq MSHR miss cycles
1896 system.l2c.InvalidateReq_mshr_miss_latency::total 35216676000 # number of InvalidateReq MSHR miss cycles
1897 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158916500 # number of demand (read+write) MSHR miss cycles
1898 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 159756000 # number of demand (read+write) MSHR miss cycles
1899 system.l2c.demand_mshr_miss_latency::cpu0.inst 3177306000 # number of demand (read+write) MSHR miss cycles
1900 system.l2c.demand_mshr_miss_latency::cpu0.data 27054421500 # number of demand (read+write) MSHR miss cycles
1901 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 143576000 # number of demand (read+write) MSHR miss cycles
1902 system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 139934500 # number of demand (read+write) MSHR miss cycles
1903 system.l2c.demand_mshr_miss_latency::cpu1.inst 2684393500 # number of demand (read+write) MSHR miss cycles
1904 system.l2c.demand_mshr_miss_latency::cpu1.data 26858206500 # number of demand (read+write) MSHR miss cycles
1905 system.l2c.demand_mshr_miss_latency::total 60376510500 # number of demand (read+write) MSHR miss cycles
1906 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158916500 # number of overall MSHR miss cycles
1907 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 159756000 # number of overall MSHR miss cycles
1908 system.l2c.overall_mshr_miss_latency::cpu0.inst 3177306000 # number of overall MSHR miss cycles
1909 system.l2c.overall_mshr_miss_latency::cpu0.data 27054421500 # number of overall MSHR miss cycles
1910 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 143576000 # number of overall MSHR miss cycles
1911 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 139934500 # number of overall MSHR miss cycles
1912 system.l2c.overall_mshr_miss_latency::cpu1.inst 2684393500 # number of overall MSHR miss cycles
1913 system.l2c.overall_mshr_miss_latency::cpu1.data 26858206500 # number of overall MSHR miss cycles
1914 system.l2c.overall_mshr_miss_latency::total 60376510500 # number of overall MSHR miss cycles
1915 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1631918500 # number of ReadReq MSHR uncacheable cycles
1916 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2761184000 # number of ReadReq MSHR uncacheable cycles
1917 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1058142000 # number of ReadReq MSHR uncacheable cycles
1918 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2648695500 # number of ReadReq MSHR uncacheable cycles
1919 system.l2c.ReadReq_mshr_uncacheable_latency::total 8099940000 # number of ReadReq MSHR uncacheable cycles
1920 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2682292500 # number of WriteReq MSHR uncacheable cycles
1921 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2625286500 # number of WriteReq MSHR uncacheable cycles
1922 system.l2c.WriteReq_mshr_uncacheable_latency::total 5307579000 # number of WriteReq MSHR uncacheable cycles
1923 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1631918500 # number of overall MSHR uncacheable cycles
1924 system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5443476500 # number of overall MSHR uncacheable cycles
1925 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1058142000 # number of overall MSHR uncacheable cycles
1926 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5273982000 # number of overall MSHR uncacheable cycles
1927 system.l2c.overall_mshr_uncacheable_latency::total 13407519000 # number of overall MSHR uncacheable cycles
1928 system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008714 # mshr miss rate for ReadReq accesses
1929 system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012363 # mshr miss rate for ReadReq accesses
1930 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007913 # mshr miss rate for ReadReq accesses
1931 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011087 # mshr miss rate for ReadReq accesses
1932 system.l2c.ReadReq_mshr_miss_rate::total 0.009714 # mshr miss rate for ReadReq accesses
1933 system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1934 system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1935 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.781889 # mshr miss rate for UpgradeReq accesses
1936 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781951 # mshr miss rate for UpgradeReq accesses
1937 system.l2c.UpgradeReq_mshr_miss_rate::total 0.781920 # mshr miss rate for UpgradeReq accesses
1938 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1939 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
1940 system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1941 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.231313 # mshr miss rate for ReadExReq accesses
1942 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.226518 # mshr miss rate for ReadExReq accesses
1943 system.l2c.ReadExReq_mshr_miss_rate::total 0.228910 # mshr miss rate for ReadExReq accesses
1944 system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.006403 # mshr miss rate for ReadCleanReq accesses
1945 system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005426 # mshr miss rate for ReadCleanReq accesses
1946 system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005914 # mshr miss rate for ReadCleanReq accesses
1947 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.040908 # mshr miss rate for ReadSharedReq accesses
1948 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.040593 # mshr miss rate for ReadSharedReq accesses
1949 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040750 # mshr miss rate for ReadSharedReq accesses
1950 system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.410529 # mshr miss rate for InvalidateReq accesses
1951 system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.419151 # mshr miss rate for InvalidateReq accesses
1952 system.l2c.InvalidateReq_mshr_miss_rate::total 0.414851 # mshr miss rate for InvalidateReq accesses
1953 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.008714 # mshr miss rate for demand accesses
1954 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012363 # mshr miss rate for demand accesses
1955 system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006403 # mshr miss rate for demand accesses
1956 system.l2c.demand_mshr_miss_rate::cpu0.data 0.086564 # mshr miss rate for demand accesses
1957 system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007913 # mshr miss rate for demand accesses
1958 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011087 # mshr miss rate for demand accesses
1959 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005426 # mshr miss rate for demand accesses
1960 system.l2c.demand_mshr_miss_rate::cpu1.data 0.084774 # mshr miss rate for demand accesses
1961 system.l2c.demand_mshr_miss_rate::total 0.035963 # mshr miss rate for demand accesses
1962 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.008714 # mshr miss rate for overall accesses
1963 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012363 # mshr miss rate for overall accesses
1964 system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006403 # mshr miss rate for overall accesses
1965 system.l2c.overall_mshr_miss_rate::cpu0.data 0.086564 # mshr miss rate for overall accesses
1966 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007913 # mshr miss rate for overall accesses
1967 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011087 # mshr miss rate for overall accesses
1968 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005426 # mshr miss rate for overall accesses
1969 system.l2c.overall_mshr_miss_rate::cpu1.data 0.084774 # mshr miss rate for overall accesses
1970 system.l2c.overall_mshr_miss_rate::total 0.035963 # mshr miss rate for overall accesses
1971 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average ReadReq mshr miss latency
1972 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average ReadReq mshr miss latency
1973 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average ReadReq mshr miss latency
1974 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average ReadReq mshr miss latency
1975 system.l2c.ReadReq_avg_mshr_miss_latency::total 77005.498721 # average ReadReq mshr miss latency
1976 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20655.485911 # average UpgradeReq mshr miss latency
1977 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20655.137364 # average UpgradeReq mshr miss latency
1978 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20655.314093 # average UpgradeReq mshr miss latency
1979 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69500 # average SCUpgradeReq mshr miss latency
1980 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20500 # average SCUpgradeReq mshr miss latency
1981 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45000 # average SCUpgradeReq mshr miss latency
1982 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70537.296580 # average ReadExReq mshr miss latency
1983 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70520.567486 # average ReadExReq mshr miss latency
1984 system.l2c.ReadExReq_avg_mshr_miss_latency::total 70529.000862 # average ReadExReq mshr miss latency
1985 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average ReadCleanReq mshr miss latency
1986 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average ReadCleanReq mshr miss latency
1987 system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71471.937718 # average ReadCleanReq mshr miss latency
1988 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 73037.508636 # average ReadSharedReq mshr miss latency
1989 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73047.399754 # average ReadSharedReq mshr miss latency
1990 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73042.475457 # average ReadSharedReq mshr miss latency
1991 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69043.995246 # average InvalidateReq mshr miss latency
1992 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69120.579339 # average InvalidateReq mshr miss latency
1993 system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69082.783581 # average InvalidateReq mshr miss latency
1994 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average overall mshr miss latency
1995 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average overall mshr miss latency
1996 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average overall mshr miss latency
1997 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71435.531058 # average overall mshr miss latency
1998 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average overall mshr miss latency
1999 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average overall mshr miss latency
2000 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average overall mshr miss latency
2001 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71442.990751 # average overall mshr miss latency
2002 system.l2c.demand_avg_mshr_miss_latency::total 71493.965054 # average overall mshr miss latency
2003 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average overall mshr miss latency
2004 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average overall mshr miss latency
2005 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average overall mshr miss latency
2006 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71435.531058 # average overall mshr miss latency
2007 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average overall mshr miss latency
2008 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average overall mshr miss latency
2009 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average overall mshr miss latency
2010 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71442.990751 # average overall mshr miss latency
2011 system.l2c.overall_avg_mshr_miss_latency::total 71493.965054 # average overall mshr miss latency
2012 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553 # average ReadReq mshr uncacheable latency
2013 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159735.277103 # average ReadReq mshr uncacheable latency
2014 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619 # average ReadReq mshr uncacheable latency
2015 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161328.755025 # average ReadReq mshr uncacheable latency
2016 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105428.158638 # average ReadReq mshr uncacheable latency
2017 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167048.172137 # average WriteReq mshr uncacheable latency
2018 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148724.592114 # average WriteReq mshr uncacheable latency
2019 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157452.876087 # average WriteReq mshr uncacheable latency
2020 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553 # average overall mshr uncacheable latency
2021 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163256.950484 # average overall mshr uncacheable latency
2022 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619 # average overall mshr uncacheable latency
2023 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154798.415028 # average overall mshr uncacheable latency
2024 system.l2c.overall_avg_mshr_uncacheable_latency::total 121293.301851 # average overall mshr uncacheable latency
2025 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2026 system.membus.trans_dist::ReadReq 76829 # Transaction distribution
2027 system.membus.trans_dist::ReadResp 448840 # Transaction distribution
2028 system.membus.trans_dist::WriteReq 33709 # Transaction distribution
2029 system.membus.trans_dist::WriteResp 33709 # Transaction distribution
2030 system.membus.trans_dist::Writeback 1181427 # Transaction distribution
2031 system.membus.trans_dist::CleanEvict 191531 # Transaction distribution
2032 system.membus.trans_dist::UpgradeReq 35493 # Transaction distribution
2033 system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2034 system.membus.trans_dist::UpgradeResp 35495 # Transaction distribution
2035 system.membus.trans_dist::ReadExReq 990576 # Transaction distribution
2036 system.membus.trans_dist::ReadExResp 990576 # Transaction distribution
2037 system.membus.trans_dist::ReadSharedReq 372011 # Transaction distribution
2038 system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
2039 system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
2040 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2041 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2042 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes)
2043 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4129743 # Packet count per connected master and slave (bytes)
2044 system.membus.pkt_count_system.l2c.mem_side::total 4259441 # Packet count per connected master and slave (bytes)
2045 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340465 # Packet count per connected master and slave (bytes)
2046 system.membus.pkt_count_system.iocache.mem_side::total 340465 # Packet count per connected master and slave (bytes)
2047 system.membus.pkt_count::total 4599906 # Packet count per connected master and slave (bytes)
2048 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2049 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
2050 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes)
2051 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 155575648 # Cumulative packet size per connected master and slave (bytes)
2052 system.membus.pkt_size_system.l2c.mem_side::total 155745486 # Cumulative packet size per connected master and slave (bytes)
2053 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7203136 # Cumulative packet size per connected master and slave (bytes)
2054 system.membus.pkt_size_system.iocache.mem_side::total 7203136 # Cumulative packet size per connected master and slave (bytes)
2055 system.membus.pkt_size::total 162948622 # Cumulative packet size per connected master and slave (bytes)
2056 system.membus.snoops 3620 # Total snoops (count)
2057 system.membus.snoop_fanout::samples 2991422 # Request fanout histogram
2058 system.membus.snoop_fanout::mean 1 # Request fanout histogram
2059 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2060 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2061 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2062 system.membus.snoop_fanout::1 2991422 100.00% 100.00% # Request fanout histogram
2063 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2064 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2065 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2066 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2067 system.membus.snoop_fanout::total 2991422 # Request fanout histogram
2068 system.membus.reqLayer0.occupancy 107341500 # Layer occupancy (ticks)
2069 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2070 system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
2071 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2072 system.membus.reqLayer2.occupancy 5250000 # Layer occupancy (ticks)
2073 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2074 system.membus.reqLayer5.occupancy 7710006309 # Layer occupancy (ticks)
2075 system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2076 system.membus.respLayer2.occupancy 7440287022 # Layer occupancy (ticks)
2077 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2078 system.membus.respLayer3.occupancy 228944719 # Layer occupancy (ticks)
2079 system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2080 system.realview.ethernet.txBytes 966 # Bytes Transmitted
2081 system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
2082 system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
2083 system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
2084 system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
2085 system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2086 system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2087 system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2088 system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2089 system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
2090 system.realview.ethernet.totPackets 3 # Total Packets
2091 system.realview.ethernet.totBytes 966 # Total Bytes
2092 system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2093 system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
2094 system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
2095 system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2096 system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
2097 system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2098 system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
2099 system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
2100 system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2101 system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
2102 system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
2103 system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2104 system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
2105 system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
2106 system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
2107 system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
2108 system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
2109 system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2110 system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
2111 system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
2112 system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
2113 system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
2114 system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
2115 system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2116 system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2117 system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
2118 system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2119 system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
2120 system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
2121 system.realview.ethernet.droppedPackets 0 # number of packets dropped
2122 system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
2123 system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
2124 system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
2125 system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
2126 system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
2127 system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
2128 system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2129 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
2130 system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
2131 system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2132 system.toL2Bus.trans_dist::ReadReq 1264904 # Transaction distribution
2133 system.toL2Bus.trans_dist::ReadResp 21840032 # Transaction distribution
2134 system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution
2135 system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution
2136 system.toL2Bus.trans_dist::Writeback 8906693 # Transaction distribution
2137 system.toL2Bus.trans_dist::CleanEvict 16372534 # Transaction distribution
2138 system.toL2Bus.trans_dist::UpgradeReq 44670 # Transaction distribution
2139 system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2140 system.toL2Bus.trans_dist::UpgradeResp 44672 # Transaction distribution
2141 system.toL2Bus.trans_dist::ReadExReq 2102857 # Transaction distribution
2142 system.toL2Bus.trans_dist::ReadExResp 2102857 # Transaction distribution
2143 system.toL2Bus.trans_dist::ReadCleanReq 13867412 # Transaction distribution
2144 system.toL2Bus.trans_dist::ReadSharedReq 6715681 # Transaction distribution
2145 system.toL2Bus.trans_dist::InvalidateReq 1335478 # Transaction distribution
2146 system.toL2Bus.trans_dist::InvalidateResp 1228814 # Transaction distribution
2147 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41686402 # Packet count per connected master and slave (bytes)
2148 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30339787 # Packet count per connected master and slave (bytes)
2149 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 785213 # Packet count per connected master and slave (bytes)
2150 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1207911 # Packet count per connected master and slave (bytes)
2151 system.toL2Bus.pkt_count::total 74019313 # Packet count per connected master and slave (bytes)
2152 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 887686868 # Cumulative packet size per connected master and slave (bytes)
2153 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1058482234 # Cumulative packet size per connected master and slave (bytes)
2154 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2638496 # Cumulative packet size per connected master and slave (bytes)
2155 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3801896 # Cumulative packet size per connected master and slave (bytes)
2156 system.toL2Bus.pkt_size::total 1952609494 # Cumulative packet size per connected master and slave (bytes)
2157 system.toL2Bus.snoops 1875627 # Total snoops (count)
2158 system.toL2Bus.snoop_fanout::samples 50645688 # Request fanout histogram
2159 system.toL2Bus.snoop_fanout::mean 1.052912 # Request fanout histogram
2160 system.toL2Bus.snoop_fanout::stdev 0.223858 # Request fanout histogram
2161 system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2162 system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2163 system.toL2Bus.snoop_fanout::1 47965928 94.71% 94.71% # Request fanout histogram
2164 system.toL2Bus.snoop_fanout::2 2679760 5.29% 100.00% # Request fanout histogram
2165 system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2166 system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2167 system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2168 system.toL2Bus.snoop_fanout::total 50645688 # Request fanout histogram
2169 system.toL2Bus.reqLayer0.occupancy 32319092000 # Layer occupancy (ticks)
2170 system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2171 system.toL2Bus.snoopLayer0.occupancy 1371000 # Layer occupancy (ticks)
2172 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2173 system.toL2Bus.respLayer0.occupancy 20844243000 # Layer occupancy (ticks)
2174 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2175 system.toL2Bus.respLayer1.occupancy 13901838902 # Layer occupancy (ticks)
2176 system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2177 system.toL2Bus.respLayer2.occupancy 455401000 # Layer occupancy (ticks)
2178 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2179 system.toL2Bus.respLayer3.occupancy 732674000 # Layer occupancy (ticks)
2180 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2182 ---------- End Simulation Statistics ----------
projects / gem5.git / blob