2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.230834 # Number of seconds simulated
4 sim_ticks 5230834315000 # Number of ticks simulated
5 final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 207627 # Simulator instruction rate (inst/s)
8 host_op_rate 410431 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2662189440 # Simulator tick rate (ticks/s)
10 host_mem_usage 751184 # Number of bytes of host memory used
11 host_seconds 1964.86 # Real time elapsed on the host
12 sim_insts 407959263 # Number of instructions simulated
13 sim_ops 806441023 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 181488 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 145215 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 181488 # Number of read requests accepted
52 system.physmem.writeReqs 145215 # Number of write requests accepted
53 system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11156 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 11363 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 11879 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11399 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11231 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 10765 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 10426 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 10967 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 10953 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 10767 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11374 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11178 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 12058 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12613 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11821 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11247 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 9305 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9167 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 9550 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 8690 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9047 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 8729 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 8333 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 8814 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 9019 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 9026 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 9076 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 9210 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9034 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 9456 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9034 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
97 system.physmem.totGap 5230834265500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 181488 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 145215 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads
263 system.physmem.totQLat 2046328821 # Total ticks spent queuing
264 system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM
265 system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers
266 system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst
267 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268 system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst
269 system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
270 system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
271 system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
272 system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
273 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274 system.physmem.busUtil 0.03 # Data bus utilization in percentage
275 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
276 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
277 system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
278 system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing
279 system.physmem.readRowHits 147319 # Number of row buffer hits during reads
280 system.physmem.writeRowHits 107244 # Number of row buffer hits during writes
281 system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
282 system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
283 system.physmem.avgGap 16010977.14 # Average gap between requests
284 system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined
285 system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ)
286 system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ)
287 system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ)
288 system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ)
289 system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
290 system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ)
291 system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ)
292 system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ)
293 system.physmem_0.averagePower 668.813765 # Core power per rank (mW)
294 system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states
295 system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states
296 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297 system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states
298 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299 system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ)
300 system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ)
301 system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ)
302 system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ)
303 system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
304 system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ)
305 system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ)
306 system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ)
307 system.physmem_1.averagePower 668.831291 # Core power per rank (mW)
308 system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states
309 system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states
310 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311 system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states
312 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
313 system.cpu.branchPred.lookups 94759510 # Number of BP lookups
314 system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted
315 system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect
316 system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups
317 system.cpu.branchPred.BTBHits 0 # Number of BTB hits
318 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
319 system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
320 system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target.
321 system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions.
322 system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups.
323 system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits.
324 system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses.
325 system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches.
326 system.cpu_clk_domain.clock 500 # Clock period in ticks
327 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
328 system.cpu.numCycles 480891878 # number of cpu cycles simulated
329 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
330 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
331 system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss
332 system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed
333 system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered
334 system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken
335 system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked
336 system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing
337 system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb
338 system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
339 system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps
340 system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions
341 system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR
342 system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched
343 system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed
344 system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed
345 system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total)
355 system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total)
357 system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
359 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
360 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
361 system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total)
362 system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle
363 system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle
364 system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle
365 system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked
366 system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running
367 system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking
368 system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing
369 system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode
370 system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing
371 system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle
372 system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking
373 system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst
374 system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running
375 system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking
376 system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename
377 system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full
378 system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full
379 system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full
380 system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full
381 system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed
382 system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made
383 system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups
384 system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups
385 system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed
386 system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing
387 system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed
388 system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed
389 system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer
390 system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit.
391 system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit.
392 system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads.
393 system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores.
394 system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec)
395 system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ
396 system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued
397 system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued
398 system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling
399 system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph
400 system.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed
401 system.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle
411 system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle
412 system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle
413 system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle
414 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
415 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
416 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
417 system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle
418 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
419 system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available
420 system.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available
421 system.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available
422 system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available
423 system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available
424 system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available
425 system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available
426 system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available
427 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available
445 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
448 system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available
449 system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available
450 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
451 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
452 system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued
453 system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued
454 system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued
455 system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued
456 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued
457 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued
458 system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued
459 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued
460 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued
461 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued
479 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued
482 system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued
483 system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued
484 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
485 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
486 system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued
487 system.cpu.iq.rate 1.759858 # Inst issue rate
488 system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested
489 system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst)
490 system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads
491 system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes
492 system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses
493 system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
494 system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes
495 system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
496 system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses
497 system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
498 system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores
499 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
500 system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed
501 system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed
502 system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations
503 system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed
504 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
505 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
506 system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled
507 system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked
508 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
509 system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing
510 system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking
511 system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking
512 system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ
513 system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch
514 system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions
515 system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions
516 system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions
517 system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall
518 system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall
519 system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations
520 system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly
521 system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly
522 system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute
523 system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions
524 system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed
525 system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute
526 system.cpu.iew.exec_swp 0 # number of swp insts executed
527 system.cpu.iew.exec_nop 0 # number of nop insts executed
528 system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed
529 system.cpu.iew.exec_branches 84810471 # Number of branches executed
530 system.cpu.iew.exec_stores 9925440 # Number of stores executed
531 system.cpu.iew.exec_rate 1.747546 # Inst execution rate
532 system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit
533 system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back
534 system.cpu.iew.wb_producers 651539387 # num instructions producing a value
535 system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value
536 system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle
537 system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back
538 system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit
539 system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards
540 system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted
541 system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle
552 system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle
553 system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle
554 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
555 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
556 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
557 system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle
558 system.cpu.commit.committedInsts 407959263 # Number of instructions committed
559 system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed
560 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
561 system.cpu.commit.refs 22368017 # Number of memory references committed
562 system.cpu.commit.loads 13951296 # Number of loads committed
563 system.cpu.commit.membars 447981 # Number of memory barriers committed
564 system.cpu.commit.branches 82209281 # Number of branches committed
565 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
566 system.cpu.commit.int_insts 735219945 # Number of committed integer instructions.
567 system.cpu.commit.function_calls 1155854 # Number of function calls committed.
568 system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction
569 system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction
570 system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction
571 system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction
572 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction
573 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction
574 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction
575 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction
576 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction
577 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction
592 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction
593 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction
594 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction
595 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction
596 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction
597 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction
598 system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction
599 system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction
600 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
601 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
602 system.cpu.commit.op_class_0::total 806441023 # Class of committed instruction
603 system.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached
604 system.cpu.rob.rob_reads 1325977641 # The number of ROB reads
605 system.cpu.rob.rob_writes 1738470998 # The number of ROB writes
606 system.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself
607 system.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling
608 system.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
609 system.cpu.committedInsts 407959263 # Number of Instructions Simulated
610 system.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated
611 system.cpu.cpi 1.178774 # CPI: Cycles Per Instruction
612 system.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads
613 system.cpu.ipc 0.848339 # IPC: Instructions Per Cycle
614 system.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads
615 system.cpu.int_regfile_reads 1112363546 # number of integer regfile reads
616 system.cpu.int_regfile_writes 669949193 # number of integer regfile writes
617 system.cpu.fp_regfile_reads 124 # number of floating regfile reads
618 system.cpu.cc_regfile_reads 420347609 # number of cc regfile reads
619 system.cpu.cc_regfile_writes 325273387 # number of cc regfile writes
620 system.cpu.misc_regfile_reads 273375214 # number of misc regfile reads
621 system.cpu.misc_regfile_writes 400822 # number of misc regfile writes
622 system.cpu.dcache.tags.replacements 1703381 # number of replacements
623 system.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use
624 system.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks.
625 system.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks.
626 system.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks.
627 system.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit.
628 system.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor
629 system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
630 system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
631 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
632 system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
633 system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
634 system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
635 system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
636 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
637 system.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses
638 system.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses
639 system.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits
640 system.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits
641 system.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits
642 system.cpu.dcache.WriteReq_hits::total 8077773 # number of WriteReq hits
643 system.cpu.dcache.SoftPFReq_hits::cpu.data 71009 # number of SoftPFReq hits
644 system.cpu.dcache.SoftPFReq_hits::total 71009 # number of SoftPFReq hits
645 system.cpu.dcache.demand_hits::cpu.data 21241306 # number of demand (read+write) hits
646 system.cpu.dcache.demand_hits::total 21241306 # number of demand (read+write) hits
647 system.cpu.dcache.overall_hits::cpu.data 21312315 # number of overall hits
648 system.cpu.dcache.overall_hits::total 21312315 # number of overall hits
649 system.cpu.dcache.ReadReq_misses::cpu.data 1883327 # number of ReadReq misses
650 system.cpu.dcache.ReadReq_misses::total 1883327 # number of ReadReq misses
651 system.cpu.dcache.WriteReq_misses::cpu.data 329239 # number of WriteReq misses
652 system.cpu.dcache.WriteReq_misses::total 329239 # number of WriteReq misses
653 system.cpu.dcache.SoftPFReq_misses::cpu.data 408040 # number of SoftPFReq misses
654 system.cpu.dcache.SoftPFReq_misses::total 408040 # number of SoftPFReq misses
655 system.cpu.dcache.demand_misses::cpu.data 2212566 # number of demand (read+write) misses
656 system.cpu.dcache.demand_misses::total 2212566 # number of demand (read+write) misses
657 system.cpu.dcache.overall_misses::cpu.data 2620606 # number of overall misses
658 system.cpu.dcache.overall_misses::total 2620606 # number of overall misses
659 system.cpu.dcache.ReadReq_miss_latency::cpu.data 31677233500 # number of ReadReq miss cycles
660 system.cpu.dcache.ReadReq_miss_latency::total 31677233500 # number of ReadReq miss cycles
661 system.cpu.dcache.WriteReq_miss_latency::cpu.data 20451778744 # number of WriteReq miss cycles
662 system.cpu.dcache.WriteReq_miss_latency::total 20451778744 # number of WriteReq miss cycles
663 system.cpu.dcache.demand_miss_latency::cpu.data 52129012244 # number of demand (read+write) miss cycles
664 system.cpu.dcache.demand_miss_latency::total 52129012244 # number of demand (read+write) miss cycles
665 system.cpu.dcache.overall_miss_latency::cpu.data 52129012244 # number of overall miss cycles
666 system.cpu.dcache.overall_miss_latency::total 52129012244 # number of overall miss cycles
667 system.cpu.dcache.ReadReq_accesses::cpu.data 15046860 # number of ReadReq accesses(hits+misses)
668 system.cpu.dcache.ReadReq_accesses::total 15046860 # number of ReadReq accesses(hits+misses)
669 system.cpu.dcache.WriteReq_accesses::cpu.data 8407012 # number of WriteReq accesses(hits+misses)
670 system.cpu.dcache.WriteReq_accesses::total 8407012 # number of WriteReq accesses(hits+misses)
671 system.cpu.dcache.SoftPFReq_accesses::cpu.data 479049 # number of SoftPFReq accesses(hits+misses)
672 system.cpu.dcache.SoftPFReq_accesses::total 479049 # number of SoftPFReq accesses(hits+misses)
673 system.cpu.dcache.demand_accesses::cpu.data 23453872 # number of demand (read+write) accesses
674 system.cpu.dcache.demand_accesses::total 23453872 # number of demand (read+write) accesses
675 system.cpu.dcache.overall_accesses::cpu.data 23932921 # number of overall (read+write) accesses
676 system.cpu.dcache.overall_accesses::total 23932921 # number of overall (read+write) accesses
677 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125164 # miss rate for ReadReq accesses
678 system.cpu.dcache.ReadReq_miss_rate::total 0.125164 # miss rate for ReadReq accesses
679 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039162 # miss rate for WriteReq accesses
680 system.cpu.dcache.WriteReq_miss_rate::total 0.039162 # miss rate for WriteReq accesses
681 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.851771 # miss rate for SoftPFReq accesses
682 system.cpu.dcache.SoftPFReq_miss_rate::total 0.851771 # miss rate for SoftPFReq accesses
683 system.cpu.dcache.demand_miss_rate::cpu.data 0.094337 # miss rate for demand accesses
684 system.cpu.dcache.demand_miss_rate::total 0.094337 # miss rate for demand accesses
685 system.cpu.dcache.overall_miss_rate::cpu.data 0.109498 # miss rate for overall accesses
686 system.cpu.dcache.overall_miss_rate::total 0.109498 # miss rate for overall accesses
687 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562 # average ReadReq miss latency
688 system.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562 # average ReadReq miss latency
689 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750 # average WriteReq miss latency
690 system.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750 # average WriteReq miss latency
691 system.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658 # average overall miss latency
692 system.cpu.dcache.demand_avg_miss_latency::total 23560.432658 # average overall miss latency
693 system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency
694 system.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency
695 system.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked
696 system.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked
697 system.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked
698 system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
699 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked
700 system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked
701 system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks
702 system.cpu.dcache.writebacks::total 1592887 # number of writebacks
703 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits
704 system.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits
705 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits
706 system.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits
707 system.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits
708 system.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits
709 system.cpu.dcache.overall_mshr_hits::cpu.data 910407 # number of overall MSHR hits
710 system.cpu.dcache.overall_mshr_hits::total 910407 # number of overall MSHR hits
711 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1015040 # number of ReadReq MSHR misses
712 system.cpu.dcache.ReadReq_mshr_misses::total 1015040 # number of ReadReq MSHR misses
713 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 287119 # number of WriteReq MSHR misses
714 system.cpu.dcache.WriteReq_mshr_misses::total 287119 # number of WriteReq MSHR misses
715 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 404591 # number of SoftPFReq MSHR misses
716 system.cpu.dcache.SoftPFReq_mshr_misses::total 404591 # number of SoftPFReq MSHR misses
717 system.cpu.dcache.demand_mshr_misses::cpu.data 1302159 # number of demand (read+write) MSHR misses
718 system.cpu.dcache.demand_mshr_misses::total 1302159 # number of demand (read+write) MSHR misses
719 system.cpu.dcache.overall_mshr_misses::cpu.data 1706750 # number of overall MSHR misses
720 system.cpu.dcache.overall_mshr_misses::total 1706750 # number of overall MSHR misses
721 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
722 system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
723 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
724 system.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
725 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
726 system.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
727 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15261276000 # number of ReadReq MSHR miss cycles
728 system.cpu.dcache.ReadReq_mshr_miss_latency::total 15261276000 # number of ReadReq MSHR miss cycles
729 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18535708244 # number of WriteReq MSHR miss cycles
730 system.cpu.dcache.WriteReq_mshr_miss_latency::total 18535708244 # number of WriteReq MSHR miss cycles
731 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles
732 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles
733 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles
734 system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles
735 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles
736 system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles
737 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles
738 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles
739 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
740 system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles
741 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses
742 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses
743 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses
744 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses
745 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses
746 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses
747 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses
748 system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses
749 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071314 # mshr miss rate for overall accesses
750 system.cpu.dcache.overall_mshr_miss_rate::total 0.071314 # mshr miss rate for overall accesses
751 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383 # average ReadReq mshr miss latency
752 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency
753 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency
754 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency
755 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency
756 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency
757 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency
758 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency
759 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency
760 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency
761 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency
762 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency
763 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
764 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency
765 system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements
766 system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use
767 system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks.
768 system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks.
769 system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks.
770 system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit.
771 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor
772 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy
773 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy
774 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
775 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
776 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
777 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
778 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
779 system.cpu.dtb_walker_cache.tags.tag_accesses 1086216 # Number of tag accesses
780 system.cpu.dtb_walker_cache.tags.data_accesses 1086216 # Number of data accesses
781 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 319137 # number of ReadReq hits
782 system.cpu.dtb_walker_cache.ReadReq_hits::total 319137 # number of ReadReq hits
783 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 319137 # number of demand (read+write) hits
784 system.cpu.dtb_walker_cache.demand_hits::total 319137 # number of demand (read+write) hits
785 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 319137 # number of overall hits
786 system.cpu.dtb_walker_cache.overall_hits::total 319137 # number of overall hits
787 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 149314 # number of ReadReq misses
788 system.cpu.dtb_walker_cache.ReadReq_misses::total 149314 # number of ReadReq misses
789 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 149314 # number of demand (read+write) misses
790 system.cpu.dtb_walker_cache.demand_misses::total 149314 # number of demand (read+write) misses
791 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 149314 # number of overall misses
792 system.cpu.dtb_walker_cache.overall_misses::total 149314 # number of overall misses
793 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1956836500 # number of ReadReq miss cycles
794 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1956836500 # number of ReadReq miss cycles
795 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1956836500 # number of demand (read+write) miss cycles
796 system.cpu.dtb_walker_cache.demand_miss_latency::total 1956836500 # number of demand (read+write) miss cycles
797 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1956836500 # number of overall miss cycles
798 system.cpu.dtb_walker_cache.overall_miss_latency::total 1956836500 # number of overall miss cycles
799 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 468451 # number of ReadReq accesses(hits+misses)
800 system.cpu.dtb_walker_cache.ReadReq_accesses::total 468451 # number of ReadReq accesses(hits+misses)
801 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 468451 # number of demand (read+write) accesses
802 system.cpu.dtb_walker_cache.demand_accesses::total 468451 # number of demand (read+write) accesses
803 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 468451 # number of overall (read+write) accesses
804 system.cpu.dtb_walker_cache.overall_accesses::total 468451 # number of overall (read+write) accesses
805 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.318740 # miss rate for ReadReq accesses
806 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.318740 # miss rate for ReadReq accesses
807 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.318740 # miss rate for demand accesses
808 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.318740 # miss rate for demand accesses
809 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.318740 # miss rate for overall accesses
810 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.318740 # miss rate for overall accesses
811 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544 # average ReadReq miss latency
812 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544 # average ReadReq miss latency
813 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
814 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544 # average overall miss latency
815 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
816 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency
817 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
818 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
819 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
820 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
821 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
822 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
823 system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks
824 system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks
825 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses
826 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses
827 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses
828 system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses
829 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses
830 system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses
831 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of ReadReq MSHR miss cycles
832 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles
833 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles
834 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1807522500 # number of demand (read+write) MSHR miss cycles
835 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles
836 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1807522500 # number of overall MSHR miss cycles
837 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for ReadReq accesses
838 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.318740 # mshr miss rate for ReadReq accesses
839 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for demand accesses
840 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.318740 # mshr miss rate for demand accesses
841 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses
842 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses
843 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency
844 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency
845 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
846 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
847 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
848 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
849 system.cpu.icache.tags.replacements 1273398 # number of replacements
850 system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use
851 system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks.
852 system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks.
853 system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks.
854 system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit.
855 system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor
856 system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy
857 system.cpu.icache.tags.occ_percent::total 0.997599 # Average percentage of cache occupancy
858 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
859 system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
860 system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
861 system.cpu.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
862 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
863 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
864 system.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses
865 system.cpu.icache.tags.data_accesses 14031709 # Number of data accesses
866 system.cpu.icache.ReadReq_hits::cpu.inst 11313989 # number of ReadReq hits
867 system.cpu.icache.ReadReq_hits::total 11313989 # number of ReadReq hits
868 system.cpu.icache.demand_hits::cpu.inst 11313989 # number of demand (read+write) hits
869 system.cpu.icache.demand_hits::total 11313989 # number of demand (read+write) hits
870 system.cpu.icache.overall_hits::cpu.inst 11313989 # number of overall hits
871 system.cpu.icache.overall_hits::total 11313989 # number of overall hits
872 system.cpu.icache.ReadReq_misses::cpu.inst 1443748 # number of ReadReq misses
873 system.cpu.icache.ReadReq_misses::total 1443748 # number of ReadReq misses
874 system.cpu.icache.demand_misses::cpu.inst 1443748 # number of demand (read+write) misses
875 system.cpu.icache.demand_misses::total 1443748 # number of demand (read+write) misses
876 system.cpu.icache.overall_misses::cpu.inst 1443748 # number of overall misses
877 system.cpu.icache.overall_misses::total 1443748 # number of overall misses
878 system.cpu.icache.ReadReq_miss_latency::cpu.inst 20254966986 # number of ReadReq miss cycles
879 system.cpu.icache.ReadReq_miss_latency::total 20254966986 # number of ReadReq miss cycles
880 system.cpu.icache.demand_miss_latency::cpu.inst 20254966986 # number of demand (read+write) miss cycles
881 system.cpu.icache.demand_miss_latency::total 20254966986 # number of demand (read+write) miss cycles
882 system.cpu.icache.overall_miss_latency::cpu.inst 20254966986 # number of overall miss cycles
883 system.cpu.icache.overall_miss_latency::total 20254966986 # number of overall miss cycles
884 system.cpu.icache.ReadReq_accesses::cpu.inst 12757737 # number of ReadReq accesses(hits+misses)
885 system.cpu.icache.ReadReq_accesses::total 12757737 # number of ReadReq accesses(hits+misses)
886 system.cpu.icache.demand_accesses::cpu.inst 12757737 # number of demand (read+write) accesses
887 system.cpu.icache.demand_accesses::total 12757737 # number of demand (read+write) accesses
888 system.cpu.icache.overall_accesses::cpu.inst 12757737 # number of overall (read+write) accesses
889 system.cpu.icache.overall_accesses::total 12757737 # number of overall (read+write) accesses
890 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.113166 # miss rate for ReadReq accesses
891 system.cpu.icache.ReadReq_miss_rate::total 0.113166 # miss rate for ReadReq accesses
892 system.cpu.icache.demand_miss_rate::cpu.inst 0.113166 # miss rate for demand accesses
893 system.cpu.icache.demand_miss_rate::total 0.113166 # miss rate for demand accesses
894 system.cpu.icache.overall_miss_rate::cpu.inst 0.113166 # miss rate for overall accesses
895 system.cpu.icache.overall_miss_rate::total 0.113166 # miss rate for overall accesses
896 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797 # average ReadReq miss latency
897 system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency
898 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
899 system.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency
900 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
901 system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency
902 system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked
903 system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked
904 system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked
905 system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
906 system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked
907 system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked
908 system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks
909 system.cpu.icache.writebacks::total 1273398 # number of writebacks
910 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits
911 system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits
912 system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits
913 system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits
914 system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits
915 system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits
916 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1273972 # number of ReadReq MSHR misses
917 system.cpu.icache.ReadReq_mshr_misses::total 1273972 # number of ReadReq MSHR misses
918 system.cpu.icache.demand_mshr_misses::cpu.inst 1273972 # number of demand (read+write) MSHR misses
919 system.cpu.icache.demand_mshr_misses::total 1273972 # number of demand (read+write) MSHR misses
920 system.cpu.icache.overall_mshr_misses::cpu.inst 1273972 # number of overall MSHR misses
921 system.cpu.icache.overall_mshr_misses::total 1273972 # number of overall MSHR misses
922 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329222989 # number of ReadReq MSHR miss cycles
923 system.cpu.icache.ReadReq_mshr_miss_latency::total 17329222989 # number of ReadReq MSHR miss cycles
924 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329222989 # number of demand (read+write) MSHR miss cycles
925 system.cpu.icache.demand_mshr_miss_latency::total 17329222989 # number of demand (read+write) MSHR miss cycles
926 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles
927 system.cpu.icache.overall_mshr_miss_latency::total 17329222989 # number of overall MSHR miss cycles
928 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for ReadReq accesses
929 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses
930 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for demand accesses
931 system.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses
932 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses
933 system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses
934 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency
935 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency
936 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
937 system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
938 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
939 system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
940 system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements
941 system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use
942 system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks.
943 system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks.
944 system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks.
945 system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit.
946 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor
947 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy
948 system.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy
949 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
950 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
951 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
952 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
953 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
954 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
955 system.cpu.itb_walker_cache.tags.tag_accesses 146624 # Number of tag accesses
956 system.cpu.itb_walker_cache.tags.data_accesses 146624 # Number of data accesses
957 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 49439 # number of ReadReq hits
958 system.cpu.itb_walker_cache.ReadReq_hits::total 49439 # number of ReadReq hits
959 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
960 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
961 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 49441 # number of demand (read+write) hits
962 system.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits
963 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits
964 system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits
965 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses
966 system.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses
967 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses
968 system.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses
969 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses
970 system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses
971 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles
972 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles
973 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193233000 # number of demand (read+write) miss cycles
974 system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles
975 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles
976 system.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles
977 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses)
978 system.cpu.itb_walker_cache.ReadReq_accesses::total 65353 # number of ReadReq accesses(hits+misses)
979 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
980 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
981 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses
982 system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses
983 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses
984 system.cpu.itb_walker_cache.overall_accesses::total 65355 # number of overall (read+write) accesses
985 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.243508 # miss rate for ReadReq accesses
986 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.243508 # miss rate for ReadReq accesses
987 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.243501 # miss rate for demand accesses
988 system.cpu.itb_walker_cache.demand_miss_rate::total 0.243501 # miss rate for demand accesses
989 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.243501 # miss rate for overall accesses
990 system.cpu.itb_walker_cache.overall_miss_rate::total 0.243501 # miss rate for overall accesses
991 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510 # average ReadReq miss latency
992 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510 # average ReadReq miss latency
993 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
994 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency
995 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
996 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency
997 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
998 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
999 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1000 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1001 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1002 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1003 system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks
1004 system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks
1005 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses
1006 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses
1007 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses
1008 system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses
1009 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses
1010 system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses
1011 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 177319000 # number of ReadReq MSHR miss cycles
1012 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles
1013 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 177319000 # number of demand (read+write) MSHR miss cycles
1014 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 177319000 # number of demand (read+write) MSHR miss cycles
1015 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles
1016 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles
1017 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.243508 # mshr miss rate for ReadReq accesses
1018 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.243508 # mshr miss rate for ReadReq accesses
1019 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for demand accesses
1020 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.243501 # mshr miss rate for demand accesses
1021 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses
1022 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses
1023 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency
1024 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency
1025 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
1026 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
1027 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
1028 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
1029 system.cpu.l2cache.tags.replacements 108236 # number of replacements
1030 system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use
1031 system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks.
1032 system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks.
1033 system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks.
1034 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1035 system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor
1036 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor
1037 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.037525 # Average occupied blocks per requestor
1038 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3440.033923 # Average occupied blocks per requestor
1039 system.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126 # Average occupied blocks per requestor
1040 system.cpu.l2cache.tags.occ_percent::writebacks 0.746636 # Average percentage of cache occupancy
1041 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000889 # Average percentage of cache occupancy
1042 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000046 # Average percentage of cache occupancy
1043 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052491 # Average percentage of cache occupancy
1044 system.cpu.l2cache.tags.occ_percent::cpu.data 0.188035 # Average percentage of cache occupancy
1045 system.cpu.l2cache.tags.occ_percent::total 0.988097 # Average percentage of cache occupancy
1046 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64158 # Occupied blocks per task id
1047 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
1048 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id
1049 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2466 # Occupied blocks per task id
1050 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3980 # Occupied blocks per task id
1051 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57082 # Occupied blocks per task id
1052 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978973 # Percentage of cache occupancy per task id
1053 system.cpu.l2cache.tags.tag_accesses 49981831 # Number of tag accesses
1054 system.cpu.l2cache.tags.data_accesses 49981831 # Number of data accesses
1055 system.cpu.l2cache.WritebackDirty_hits::writebacks 1631474 # number of WritebackDirty hits
1056 system.cpu.l2cache.WritebackDirty_hits::total 1631474 # number of WritebackDirty hits
1057 system.cpu.l2cache.WritebackClean_hits::writebacks 1270391 # number of WritebackClean hits
1058 system.cpu.l2cache.WritebackClean_hits::total 1270391 # number of WritebackClean hits
1059 system.cpu.l2cache.UpgradeReq_hits::cpu.data 340 # number of UpgradeReq hits
1060 system.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits
1061 system.cpu.l2cache.ReadExReq_hits::cpu.data 157196 # number of ReadExReq hits
1062 system.cpu.l2cache.ReadExReq_hits::total 157196 # number of ReadExReq hits
1063 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1257840 # number of ReadCleanReq hits
1064 system.cpu.l2cache.ReadCleanReq_hits::total 1257840 # number of ReadCleanReq hits
1065 system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 140642 # number of ReadSharedReq hits
1066 system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13110 # number of ReadSharedReq hits
1067 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1380239 # number of ReadSharedReq hits
1068 system.cpu.l2cache.ReadSharedReq_hits::total 1533991 # number of ReadSharedReq hits
1069 system.cpu.l2cache.demand_hits::cpu.dtb.walker 140642 # number of demand (read+write) hits
1070 system.cpu.l2cache.demand_hits::cpu.itb.walker 13110 # number of demand (read+write) hits
1071 system.cpu.l2cache.demand_hits::cpu.inst 1257840 # number of demand (read+write) hits
1072 system.cpu.l2cache.demand_hits::cpu.data 1537435 # number of demand (read+write) hits
1073 system.cpu.l2cache.demand_hits::total 2949027 # number of demand (read+write) hits
1074 system.cpu.l2cache.overall_hits::cpu.dtb.walker 140642 # number of overall hits
1075 system.cpu.l2cache.overall_hits::cpu.itb.walker 13110 # number of overall hits
1076 system.cpu.l2cache.overall_hits::cpu.inst 1257840 # number of overall hits
1077 system.cpu.l2cache.overall_hits::cpu.data 1537435 # number of overall hits
1078 system.cpu.l2cache.overall_hits::total 2949027 # number of overall hits
1079 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses
1080 system.cpu.l2cache.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
1081 system.cpu.l2cache.ReadExReq_misses::cpu.data 127805 # number of ReadExReq misses
1082 system.cpu.l2cache.ReadExReq_misses::total 127805 # number of ReadExReq misses
1083 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15982 # number of ReadCleanReq misses
1084 system.cpu.l2cache.ReadCleanReq_misses::total 15982 # number of ReadCleanReq misses
1085 system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 124 # number of ReadSharedReq misses
1086 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 7 # number of ReadSharedReq misses
1087 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 38662 # number of ReadSharedReq misses
1088 system.cpu.l2cache.ReadSharedReq_misses::total 38793 # number of ReadSharedReq misses
1089 system.cpu.l2cache.demand_misses::cpu.dtb.walker 124 # number of demand (read+write) misses
1090 system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1091 system.cpu.l2cache.demand_misses::cpu.inst 15982 # number of demand (read+write) misses
1092 system.cpu.l2cache.demand_misses::cpu.data 166467 # number of demand (read+write) misses
1093 system.cpu.l2cache.demand_misses::total 182580 # number of demand (read+write) misses
1094 system.cpu.l2cache.overall_misses::cpu.dtb.walker 124 # number of overall misses
1095 system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1096 system.cpu.l2cache.overall_misses::cpu.inst 15982 # number of overall misses
1097 system.cpu.l2cache.overall_misses::cpu.data 166467 # number of overall misses
1098 system.cpu.l2cache.overall_misses::total 182580 # number of overall misses
1099 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60579000 # number of UpgradeReq miss cycles
1100 system.cpu.l2cache.UpgradeReq_miss_latency::total 60579000 # number of UpgradeReq miss cycles
1101 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16318726500 # number of ReadExReq miss cycles
1102 system.cpu.l2cache.ReadExReq_miss_latency::total 16318726500 # number of ReadExReq miss cycles
1103 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2135667000 # number of ReadCleanReq miss cycles
1104 system.cpu.l2cache.ReadCleanReq_miss_latency::total 2135667000 # number of ReadCleanReq miss cycles
1105 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 17077500 # number of ReadSharedReq miss cycles
1106 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 945500 # number of ReadSharedReq miss cycles
1107 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5106603500 # number of ReadSharedReq miss cycles
1108 system.cpu.l2cache.ReadSharedReq_miss_latency::total 5124626500 # number of ReadSharedReq miss cycles
1109 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17077500 # number of demand (read+write) miss cycles
1110 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 945500 # number of demand (read+write) miss cycles
1111 system.cpu.l2cache.demand_miss_latency::cpu.inst 2135667000 # number of demand (read+write) miss cycles
1112 system.cpu.l2cache.demand_miss_latency::cpu.data 21425330000 # number of demand (read+write) miss cycles
1113 system.cpu.l2cache.demand_miss_latency::total 23579020000 # number of demand (read+write) miss cycles
1114 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17077500 # number of overall miss cycles
1115 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 945500 # number of overall miss cycles
1116 system.cpu.l2cache.overall_miss_latency::cpu.inst 2135667000 # number of overall miss cycles
1117 system.cpu.l2cache.overall_miss_latency::cpu.data 21425330000 # number of overall miss cycles
1118 system.cpu.l2cache.overall_miss_latency::total 23579020000 # number of overall miss cycles
1119 system.cpu.l2cache.WritebackDirty_accesses::writebacks 1631474 # number of WritebackDirty accesses(hits+misses)
1120 system.cpu.l2cache.WritebackDirty_accesses::total 1631474 # number of WritebackDirty accesses(hits+misses)
1121 system.cpu.l2cache.WritebackClean_accesses::writebacks 1270391 # number of WritebackClean accesses(hits+misses)
1122 system.cpu.l2cache.WritebackClean_accesses::total 1270391 # number of WritebackClean accesses(hits+misses)
1123 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1838 # number of UpgradeReq accesses(hits+misses)
1124 system.cpu.l2cache.UpgradeReq_accesses::total 1838 # number of UpgradeReq accesses(hits+misses)
1125 system.cpu.l2cache.ReadExReq_accesses::cpu.data 285001 # number of ReadExReq accesses(hits+misses)
1126 system.cpu.l2cache.ReadExReq_accesses::total 285001 # number of ReadExReq accesses(hits+misses)
1127 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1273822 # number of ReadCleanReq accesses(hits+misses)
1128 system.cpu.l2cache.ReadCleanReq_accesses::total 1273822 # number of ReadCleanReq accesses(hits+misses)
1129 system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 140766 # number of ReadSharedReq accesses(hits+misses)
1130 system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13117 # number of ReadSharedReq accesses(hits+misses)
1131 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1418901 # number of ReadSharedReq accesses(hits+misses)
1132 system.cpu.l2cache.ReadSharedReq_accesses::total 1572784 # number of ReadSharedReq accesses(hits+misses)
1133 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 140766 # number of demand (read+write) accesses
1134 system.cpu.l2cache.demand_accesses::cpu.itb.walker 13117 # number of demand (read+write) accesses
1135 system.cpu.l2cache.demand_accesses::cpu.inst 1273822 # number of demand (read+write) accesses
1136 system.cpu.l2cache.demand_accesses::cpu.data 1703902 # number of demand (read+write) accesses
1137 system.cpu.l2cache.demand_accesses::total 3131607 # number of demand (read+write) accesses
1138 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 140766 # number of overall (read+write) accesses
1139 system.cpu.l2cache.overall_accesses::cpu.itb.walker 13117 # number of overall (read+write) accesses
1140 system.cpu.l2cache.overall_accesses::cpu.inst 1273822 # number of overall (read+write) accesses
1141 system.cpu.l2cache.overall_accesses::cpu.data 1703902 # number of overall (read+write) accesses
1142 system.cpu.l2cache.overall_accesses::total 3131607 # number of overall (read+write) accesses
1143 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815016 # miss rate for UpgradeReq accesses
1144 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815016 # miss rate for UpgradeReq accesses
1145 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.448437 # miss rate for ReadExReq accesses
1146 system.cpu.l2cache.ReadExReq_miss_rate::total 0.448437 # miss rate for ReadExReq accesses
1147 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.012546 # miss rate for ReadCleanReq accesses
1148 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.012546 # miss rate for ReadCleanReq accesses
1149 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000881 # miss rate for ReadSharedReq accesses
1150 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000534 # miss rate for ReadSharedReq accesses
1151 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.027248 # miss rate for ReadSharedReq accesses
1152 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024665 # miss rate for ReadSharedReq accesses
1153 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000881 # miss rate for demand accesses
1154 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000534 # miss rate for demand accesses
1155 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012546 # miss rate for demand accesses
1156 system.cpu.l2cache.demand_miss_rate::cpu.data 0.097698 # miss rate for demand accesses
1157 system.cpu.l2cache.demand_miss_rate::total 0.058302 # miss rate for demand accesses
1158 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000881 # miss rate for overall accesses
1159 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000534 # miss rate for overall accesses
1160 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012546 # miss rate for overall accesses
1161 system.cpu.l2cache.overall_miss_rate::cpu.data 0.097698 # miss rate for overall accesses
1162 system.cpu.l2cache.overall_miss_rate::total 0.058302 # miss rate for overall accesses
1163 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40439.919893 # average UpgradeReq miss latency
1164 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893 # average UpgradeReq miss latency
1165 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127684.570244 # average ReadExReq miss latency
1166 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244 # average ReadExReq miss latency
1167 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711 # average ReadCleanReq miss latency
1168 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711 # average ReadCleanReq miss latency
1169 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194 # average ReadSharedReq miss latency
1170 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571 # average ReadSharedReq miss latency
1171 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981 # average ReadSharedReq miss latency
1172 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383 # average ReadSharedReq miss latency
1173 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
1174 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
1175 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
1176 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
1177 system.cpu.l2cache.demand_avg_miss_latency::total 129143.498740 # average overall miss latency
1178 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
1179 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
1180 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
1181 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
1182 system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency
1183 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1184 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1185 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1186 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1187 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1188 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1189 system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks
1190 system.cpu.l2cache.writebacks::total 98548 # number of writebacks
1191 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
1192 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1193 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits
1194 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
1195 system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
1196 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1197 system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1198 system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
1199 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1200 system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1201 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
1202 system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
1203 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
1204 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
1205 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127805 # number of ReadExReq MSHR misses
1206 system.cpu.l2cache.ReadExReq_mshr_misses::total 127805 # number of ReadExReq MSHR misses
1207 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15980 # number of ReadCleanReq MSHR misses
1208 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15980 # number of ReadCleanReq MSHR misses
1209 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 123 # number of ReadSharedReq MSHR misses
1210 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 7 # number of ReadSharedReq MSHR misses
1211 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 38662 # number of ReadSharedReq MSHR misses
1212 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 38792 # number of ReadSharedReq MSHR misses
1213 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses
1214 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1215 system.cpu.l2cache.demand_mshr_misses::cpu.inst 15980 # number of demand (read+write) MSHR misses
1216 system.cpu.l2cache.demand_mshr_misses::cpu.data 166467 # number of demand (read+write) MSHR misses
1217 system.cpu.l2cache.demand_mshr_misses::total 182577 # number of demand (read+write) MSHR misses
1218 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses
1219 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1220 system.cpu.l2cache.overall_mshr_misses::cpu.inst 15980 # number of overall MSHR misses
1221 system.cpu.l2cache.overall_mshr_misses::cpu.data 166467 # number of overall MSHR misses
1222 system.cpu.l2cache.overall_mshr_misses::total 182577 # number of overall MSHR misses
1223 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
1224 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
1225 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
1226 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
1227 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
1228 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
1229 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102897000 # number of UpgradeReq MSHR miss cycles
1230 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102897000 # number of UpgradeReq MSHR miss cycles
1231 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15040676500 # number of ReadExReq MSHR miss cycles
1232 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15040676500 # number of ReadExReq MSHR miss cycles
1233 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1975642505 # number of ReadCleanReq MSHR miss cycles
1234 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1975642505 # number of ReadCleanReq MSHR miss cycles
1235 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 15740000 # number of ReadSharedReq MSHR miss cycles
1236 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 875500 # number of ReadSharedReq MSHR miss cycles
1237 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4799287008 # number of ReadSharedReq MSHR miss cycles
1238 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4815902508 # number of ReadSharedReq MSHR miss cycles
1239 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15740000 # number of demand (read+write) MSHR miss cycles
1240 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 875500 # number of demand (read+write) MSHR miss cycles
1241 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1975642505 # number of demand (read+write) MSHR miss cycles
1242 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19839963508 # number of demand (read+write) MSHR miss cycles
1243 system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles
1244 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles
1245 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles
1246 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles
1247 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles
1248 system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles
1249 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles
1250 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles
1251 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
1252 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
1253 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1254 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1255 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses
1256 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses
1257 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses
1258 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses
1259 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses
1260 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses
1261 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses
1262 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses
1263 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses
1264 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses
1265 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses
1266 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses
1267 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses
1268 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses
1269 system.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses
1270 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses
1271 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses
1272 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses
1273 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses
1274 system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses
1275 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency
1276 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency
1277 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency
1278 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency
1279 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency
1280 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency
1281 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency
1282 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency
1283 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency
1284 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency
1285 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
1286 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
1287 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
1288 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
1289 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
1290 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
1291 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
1292 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
1293 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
1294 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
1295 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
1296 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency
1297 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
1298 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
1299 system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
1300 system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1301 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1302 system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
1303 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1304 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1305 system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
1306 system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
1307 system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution
1308 system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
1309 system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution
1310 system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution
1311 system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution
1312 system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
1315 system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
1316 system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
1317 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
1318 system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
1319 system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
1320 system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1321 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
1322 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
1323 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
1324 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
1325 system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
1326 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
1327 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
1328 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
1329 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
1330 system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
1331 system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
1332 system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
1333 system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
1334 system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
1335 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1336 system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
1337 system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
1338 system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
1339 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
1340 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1341 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1342 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1343 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1344 system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
1345 system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
1346 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1347 system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
1348 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1349 system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
1350 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1351 system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
1352 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1353 system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
1354 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1355 system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
1356 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1357 system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
1358 system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
1359 system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
1360 system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
1361 system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
1362 system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
1363 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1364 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1365 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1366 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1367 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
1368 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
1386 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1387 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1388 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1389 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1390 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
1391 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
1410 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1411 system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
1412 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1413 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1414 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1415 system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
1416 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1417 system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
1418 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1419 system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
1420 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1421 system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
1422 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1423 system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
1424 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
1426 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
1428 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
1430 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
1432 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
1434 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1436 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
1438 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1439 system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1440 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1441 system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
1442 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1443 system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
1444 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1445 system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
1446 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1447 system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
1448 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1449 system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
1450 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1451 system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
1452 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1453 system.iocache.tags.replacements 47572 # number of replacements
1454 system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
1455 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1456 system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
1457 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1458 system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
1459 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
1460 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
1461 system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
1462 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1463 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1464 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1465 system.iocache.tags.tag_accesses 428643 # Number of tag accesses
1466 system.iocache.tags.data_accesses 428643 # Number of data accesses
1467 system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
1468 system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
1469 system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1470 system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
1471 system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
1472 system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
1473 system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
1474 system.iocache.overall_misses::total 47627 # number of overall misses
1475 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
1476 system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
1477 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
1478 system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles
1479 system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
1480 system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
1481 system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
1482 system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
1483 system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
1484 system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
1485 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1486 system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
1487 system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
1488 system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
1489 system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
1490 system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
1491 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1492 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1493 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1494 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1495 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1496 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1497 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1498 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1499 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
1500 system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
1501 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
1502 system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency
1503 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
1504 system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
1505 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
1506 system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
1507 system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
1508 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1509 system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
1510 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1511 system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
1512 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1513 system.iocache.writebacks::writebacks 46667 # number of writebacks
1514 system.iocache.writebacks::total 46667 # number of writebacks
1515 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
1516 system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
1517 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1518 system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
1519 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
1520 system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
1521 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
1522 system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
1523 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
1524 system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
1525 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
1526 system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles
1527 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
1528 system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
1529 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
1530 system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
1531 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1532 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1533 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1534 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1535 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1536 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1537 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1538 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1539 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
1540 system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
1541 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
1542 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency
1543 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
1544 system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
1545 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
1546 system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
1547 system.membus.trans_dist::ReadReq 573476 # Transaction distribution
1548 system.membus.trans_dist::ReadResp 628544 # Transaction distribution
1549 system.membus.trans_dist::WriteReq 13974 # Transaction distribution
1550 system.membus.trans_dist::WriteResp 13974 # Transaction distribution
1551 system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution
1552 system.membus.trans_dist::CleanEvict 10528 # Transaction distribution
1553 system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution
1554 system.membus.trans_dist::UpgradeResp 20 # Transaction distribution
1555 system.membus.trans_dist::ReadExReq 127539 # Transaction distribution
1556 system.membus.trans_dist::ReadExResp 127538 # Transaction distribution
1557 system.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution
1558 system.membus.trans_dist::MessageReq 1666 # Transaction distribution
1559 system.membus.trans_dist::MessageResp 1666 # Transaction distribution
1560 system.membus.trans_dist::BadAddressError 611 # Transaction distribution
1561 system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
1562 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes)
1563 system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes)
1564 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes)
1565 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes)
1566 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes)
1567 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes)
1568 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes)
1569 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes)
1570 system.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes)
1571 system.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes)
1572 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes)
1573 system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes)
1574 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes)
1575 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes)
1576 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes)
1577 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes)
1578 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
1579 system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
1580 system.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes)
1581 system.membus.snoops 1549 # Total snoops (count)
1582 system.membus.snoop_fanout::samples 976982 # Request fanout histogram
1583 system.membus.snoop_fanout::mean 1.001705 # Request fanout histogram
1584 system.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram
1585 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1586 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1587 system.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram
1588 system.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram
1589 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1590 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1591 system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1592 system.membus.snoop_fanout::total 976982 # Request fanout histogram
1593 system.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks)
1594 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1595 system.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks)
1596 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1597 system.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks)
1598 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1599 system.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks)
1600 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1601 system.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks)
1602 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1603 system.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks)
1604 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1605 system.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks)
1606 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1607 system.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks)
1608 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1609 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1610 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1611 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1612 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1613 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1614 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1615 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1616 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1617 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1618 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1619 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1620 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1621 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1622 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1624 ---------- End Simulation Statistics ----------
projects / gem5.git / blob