2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.125717 # Number of seconds simulated
4 sim_ticks 5125716951000 # Number of ticks simulated
5 final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 203249 # Simulator instruction rate (inst/s)
8 host_op_rate 401765 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2555120499 # Simulator tick rate (ticks/s)
10 host_mem_usage 728844 # Number of bytes of host memory used
11 host_seconds 2006.06 # Real time elapsed on the host
12 sim_insts 407728401 # Number of instructions simulated
13 sim_ops 805963181 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.readReqs 222005 # Total number of read requests seen
50 system.physmem.writeReqs 148125 # Total number of write requests seen
51 system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady
52 system.physmem.bytesRead 14208320 # Total number of bytes read from memory
53 system.physmem.bytesWritten 9480000 # Total number of bytes written to memory
54 system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize()
55 system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize()
56 system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q
57 system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed
58 system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis
74 system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis
90 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
91 system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry
92 system.physmem.totGap 5125716897500 # Total gap between requests
93 system.physmem.readPktSize::0 0 # Categorize read packet sizes
94 system.physmem.readPktSize::1 0 # Categorize read packet sizes
95 system.physmem.readPktSize::2 0 # Categorize read packet sizes
96 system.physmem.readPktSize::3 0 # Categorize read packet sizes
97 system.physmem.readPktSize::4 0 # Categorize read packet sizes
98 system.physmem.readPktSize::5 0 # Categorize read packet sizes
99 system.physmem.readPktSize::6 222005 # Categorize read packet sizes
100 system.physmem.writePktSize::0 0 # Categorize write packet sizes
101 system.physmem.writePktSize::1 0 # Categorize write packet sizes
102 system.physmem.writePktSize::2 0 # Categorize write packet sizes
103 system.physmem.writePktSize::3 0 # Categorize write packet sizes
104 system.physmem.writePktSize::4 0 # Categorize write packet sizes
105 system.physmem.writePktSize::5 0 # Categorize write packet sizes
106 system.physmem.writePktSize::6 148125 # Categorize write packet sizes
107 system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
139 system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
171 system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation
172 system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation
173 system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation
174 system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation
175 system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation
176 system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation
293 system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation
294 system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation
295 system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation
296 system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation
297 system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation
298 system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation
299 system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation
300 system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation
301 system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation
302 system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation
303 system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation
304 system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation
305 system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation
306 system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation
307 system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation
308 system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation
309 system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation
310 system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation
311 system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation
312 system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation
313 system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation
314 system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation
315 system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation
316 system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation
317 system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation
318 system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation
319 system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation
320 system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation
321 system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation
322 system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation
323 system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation
324 system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation
325 system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation
326 system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation
327 system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation
328 system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation
329 system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation
330 system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation
331 system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation
332 system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation
333 system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation
334 system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation
335 system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation
336 system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation
337 system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation
338 system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation
339 system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation
340 system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation
341 system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation
342 system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation
343 system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation
344 system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation
345 system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation
346 system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation
347 system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation
348 system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation
349 system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation
350 system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation
351 system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation
352 system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation
353 system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation
354 system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation
355 system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation
356 system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation
357 system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation
358 system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation
359 system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation
360 system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation
361 system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation
362 system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation
363 system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation
364 system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation
365 system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation
366 system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation
367 system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation
368 system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation
369 system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation
370 system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation
371 system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation
372 system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays
373 system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests
374 system.physmem.totBusLat 1109565000 # Total cycles spent in databus access
375 system.physmem.totBankLat 3154263750 # Total cycles spent in bank access
376 system.physmem.avgQLat 18030.39 # Average queueing delay per request
377 system.physmem.avgBankLat 14213.97 # Average bank access latency per request
378 system.physmem.avgBusLat 5000.00 # Average bus latency per request
379 system.physmem.avgMemAccLat 37244.35 # Average memory access latency
380 system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s
381 system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s
382 system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s
383 system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s
384 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
385 system.physmem.busUtil 0.04 # Data bus utilization in percentage
386 system.physmem.avgRdQLen 0.00 # Average read queue length over time
387 system.physmem.avgWrQLen 11.40 # Average write queue length over time
388 system.physmem.readRowHits 198637 # Number of row buffer hits during reads
389 system.physmem.writeRowHits 108987 # Number of row buffer hits during writes
390 system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads
391 system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes
392 system.physmem.avgGap 13848423.25 # Average gap between requests
393 system.membus.throughput 5098961 # Throughput (bytes/s)
394 system.membus.trans_dist::ReadReq 662131 # Transaction distribution
395 system.membus.trans_dist::ReadResp 662131 # Transaction distribution
396 system.membus.trans_dist::WriteReq 13694 # Transaction distribution
397 system.membus.trans_dist::WriteResp 13694 # Transaction distribution
398 system.membus.trans_dist::Writeback 148125 # Transaction distribution
399 system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution
400 system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution
401 system.membus.trans_dist::ReadExReq 179249 # Transaction distribution
402 system.membus.trans_dist::ReadExResp 179246 # Transaction distribution
403 system.membus.trans_dist::MessageReq 1640 # Transaction distribution
404 system.membus.trans_dist::MessageResp 1640 # Transaction distribution
405 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes)
406 system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes)
407 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes)
408 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
409 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
410 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes)
411 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes)
412 system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes)
413 system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes)
414 system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
415 system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
416 system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes)
417 system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes)
418 system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes)
419 system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes)
420 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes)
421 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
422 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
423 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes)
424 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes)
425 system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes)
426 system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes)
427 system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
428 system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
429 system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes)
430 system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes)
431 system.membus.data_through_bus 25486679 # Total data (bytes)
432 system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes)
433 system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks)
434 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
435 system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks)
436 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
437 system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks)
438 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
439 system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks)
440 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
441 system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks)
442 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
443 system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks)
444 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
445 system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks)
446 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
447 system.iocache.replacements 47577 # number of replacements
448 system.iocache.tagsinuse 0.079131 # Cycle average of tags in use
449 system.iocache.total_refs 0 # Total number of references to valid blocks.
450 system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
451 system.iocache.avg_refs 0 # Average number of references to valid blocks.
452 system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit.
453 system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor
454 system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy
455 system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy
456 system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
457 system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
458 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
459 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
460 system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
461 system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
462 system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
463 system.iocache.overall_misses::total 47632 # number of overall misses
464 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles
465 system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles
466 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles
467 system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles
468 system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles
469 system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles
470 system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles
471 system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles
472 system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
473 system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
474 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
475 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
476 system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
477 system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
478 system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
479 system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
480 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
481 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
482 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
483 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
484 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
485 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
486 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
487 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
488 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency
489 system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency
490 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency
491 system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency
492 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency
493 system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency
494 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency
495 system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency
496 system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked
497 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
498 system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked
499 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
500 system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked
501 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
502 system.iocache.fast_writes 0 # number of fast writes performed
503 system.iocache.cache_copies 0 # number of cache copies performed
504 system.iocache.writebacks::writebacks 46667 # number of writebacks
505 system.iocache.writebacks::total 46667 # number of writebacks
506 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
507 system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
508 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
509 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
510 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
511 system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
512 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
513 system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
514 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles
515 system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles
516 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles
517 system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles
518 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles
519 system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles
520 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles
521 system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles
522 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
523 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
524 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
525 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
526 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
527 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
528 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
529 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
530 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency
531 system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency
532 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency
533 system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency
534 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency
535 system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency
536 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency
537 system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency
538 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
539 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
540 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
541 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
542 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
543 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
544 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
545 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
546 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
547 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
548 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
549 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
550 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
551 system.iobus.throughput 639145 # Throughput (bytes/s)
552 system.iobus.trans_dist::ReadReq 225496 # Transaction distribution
553 system.iobus.trans_dist::ReadResp 225496 # Transaction distribution
554 system.iobus.trans_dist::WriteReq 57527 # Transaction distribution
555 system.iobus.trans_dist::WriteResp 57527 # Transaction distribution
556 system.iobus.trans_dist::MessageReq 1640 # Transaction distribution
557 system.iobus.trans_dist::MessageResp 1640 # Transaction distribution
558 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
559 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
560 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
561 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
562 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
563 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
564 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
565 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
566 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
567 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
568 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
569 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
570 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
571 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
572 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
573 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
574 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
575 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
576 system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes)
577 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes)
578 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes)
579 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes)
580 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes)
581 system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes)
582 system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
583 system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
584 system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
585 system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
586 system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
587 system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
588 system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
589 system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
590 system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
591 system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
592 system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
593 system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
594 system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
595 system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
596 system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
597 system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
598 system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
599 system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes)
600 system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
601 system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes)
602 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
603 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
604 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
605 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
606 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
607 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
608 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
609 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
610 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
611 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
612 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
613 system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
614 system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
615 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
616 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
617 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
618 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
619 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
620 system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes)
621 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes)
622 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes)
623 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes)
624 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes)
625 system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes)
626 system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
627 system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
628 system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
629 system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
630 system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
631 system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
632 system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
633 system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
634 system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
635 system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
636 system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
637 system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
638 system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
639 system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
640 system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
641 system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
642 system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
643 system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes)
644 system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
645 system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes)
646 system.iobus.data_through_bus 3276074 # Total data (bytes)
647 system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks)
648 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
649 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
650 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
651 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
652 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
653 system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
654 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
655 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
656 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
657 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
658 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
659 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
660 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
661 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
662 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
663 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
664 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
665 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
666 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
667 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
668 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
669 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
670 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
671 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
672 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
673 system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks)
674 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
675 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
676 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
677 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
678 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
679 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
680 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
681 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
682 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
683 system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks)
684 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
685 system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
686 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
687 system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks)
688 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
689 system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks)
690 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
691 system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks)
692 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
693 system.cpu.branchPred.lookups 85601186 # Number of BP lookups
694 system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted
695 system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect
696 system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups
697 system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits
698 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
699 system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage
700 system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target.
701 system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions.
702 system.cpu.numCycles 453375451 # number of cpu cycles simulated
703 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
704 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
705 system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss
706 system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed
707 system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered
708 system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken
709 system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked
710 system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing
711 system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb
712 system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked
713 system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
714 system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps
715 system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
716 system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched
717 system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed
718 system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed
719 system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total)
720 system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total)
721 system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total)
722 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
723 system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total)
724 system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total)
725 system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total)
726 system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total)
727 system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total)
728 system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total)
729 system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total)
730 system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total)
731 system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total)
732 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
733 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
734 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
735 system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total)
736 system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle
737 system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle
738 system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle
739 system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked
740 system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running
741 system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking
742 system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing
743 system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode
744 system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode
745 system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing
746 system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle
747 system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking
748 system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst
749 system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running
750 system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking
751 system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename
752 system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full
753 system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full
754 system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full
755 system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers
756 system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed
757 system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made
758 system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups
759 system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups
760 system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed
761 system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing
762 system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed
763 system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed
764 system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer
765 system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit.
766 system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit.
767 system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads.
768 system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores.
769 system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec)
770 system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ
771 system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued
772 system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued
773 system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling
774 system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph
775 system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed
776 system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle
777 system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle
778 system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle
779 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
780 system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle
781 system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle
782 system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle
783 system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle
784 system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle
785 system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle
786 system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle
787 system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle
788 system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle
789 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
790 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
791 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
792 system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle
793 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
794 system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available
795 system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available
796 system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available
797 system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available
798 system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available
799 system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available
800 system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available
801 system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available
802 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available
803 system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available
804 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available
805 system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available
806 system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available
807 system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available
808 system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available
809 system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available
810 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available
811 system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available
812 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available
813 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available
814 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available
815 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available
816 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available
817 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available
818 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available
819 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available
820 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available
821 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available
822 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available
823 system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available
824 system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available
825 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
826 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
827 system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued
828 system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued
829 system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued
830 system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued
831 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
832 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
833 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
834 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
835 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
836 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
837 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
838 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
839 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
840 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
841 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
842 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
843 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
844 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
845 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
846 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
847 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
848 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
849 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
850 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
851 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
852 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
853 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
854 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
855 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
856 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
857 system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued
858 system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued
859 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
860 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
861 system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued
862 system.cpu.iq.rate 1.810787 # Inst issue rate
863 system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested
864 system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst)
865 system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads
866 system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes
867 system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses
868 system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads
869 system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes
870 system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
871 system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses
872 system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses
873 system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores
874 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
875 system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed
876 system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed
877 system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations
878 system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed
879 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
880 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
881 system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled
882 system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked
883 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
884 system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing
885 system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking
886 system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking
887 system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ
888 system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch
889 system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions
890 system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions
891 system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions
892 system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall
893 system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall
894 system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations
895 system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly
896 system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly
897 system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute
898 system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions
899 system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed
900 system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute
901 system.cpu.iew.exec_swp 0 # number of swp insts executed
902 system.cpu.iew.exec_nop 0 # number of nop insts executed
903 system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed
904 system.cpu.iew.exec_branches 83095032 # Number of branches executed
905 system.cpu.iew.exec_stores 9034738 # Number of stores executed
906 system.cpu.iew.exec_rate 1.807683 # Inst execution rate
907 system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit
908 system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back
909 system.cpu.iew.wb_producers 638600685 # num instructions producing a value
910 system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value
911 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
912 system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle
913 system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back
914 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
915 system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit
916 system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards
917 system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted
918 system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle
919 system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle
920 system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle
921 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
922 system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle
923 system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle
924 system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle
925 system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle
926 system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle
927 system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle
928 system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle
929 system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle
930 system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle
931 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
932 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
933 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
934 system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle
935 system.cpu.commit.committedInsts 407728401 # Number of instructions committed
936 system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed
937 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
938 system.cpu.commit.refs 22399743 # Number of memory references committed
939 system.cpu.commit.loads 13982748 # Number of loads committed
940 system.cpu.commit.membars 474399 # Number of memory barriers committed
941 system.cpu.commit.branches 82153759 # Number of branches committed
942 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
943 system.cpu.commit.int_insts 734952654 # Number of committed integer instructions.
944 system.cpu.commit.function_calls 1154691 # Number of function calls committed.
945 system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached
946 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
947 system.cpu.rob.rob_reads 1079657633 # The number of ROB reads
948 system.cpu.rob.rob_writes 1655096826 # The number of ROB writes
949 system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself
950 system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling
951 system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
952 system.cpu.committedInsts 407728401 # Number of Instructions Simulated
953 system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated
954 system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated
955 system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction
956 system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads
957 system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle
958 system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads
959 system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads
960 system.cpu.int_regfile_writes 975319683 # number of integer regfile writes
961 system.cpu.fp_regfile_reads 50 # number of floating regfile reads
962 system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads
963 system.cpu.misc_regfile_writes 401987 # number of misc regfile writes
964 system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s)
965 system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution
966 system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution
967 system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution
968 system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution
969 system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution
970 system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution
971 system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution
972 system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution
973 system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution
974 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes)
975 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes)
976 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes)
977 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes)
978 system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes)
979 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes)
980 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes)
981 system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes)
982 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes)
983 system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes)
984 system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes)
985 system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes)
986 system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks)
987 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
988 system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks)
989 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
990 system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks)
991 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
992 system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks)
993 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
994 system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks)
995 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
996 system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks)
997 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
998 system.cpu.icache.replacements 953322 # number of replacements
999 system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use
1000 system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks.
1001 system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks.
1002 system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks.
1003 system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit.
1004 system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor
1005 system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy
1006 system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy
1007 system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits
1008 system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits
1009 system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits
1010 system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits
1011 system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits
1012 system.cpu.icache.overall_hits::total 7473092 # number of overall hits
1013 system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses
1014 system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses
1015 system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses
1016 system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses
1017 system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses
1018 system.cpu.icache.overall_misses::total 1006614 # number of overall misses
1019 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles
1020 system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles
1021 system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles
1022 system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles
1023 system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles
1024 system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles
1025 system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses)
1026 system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses)
1027 system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses
1028 system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses
1029 system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses
1030 system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses
1031 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses
1032 system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses
1033 system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses
1034 system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses
1035 system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses
1036 system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses
1037 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency
1038 system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency
1039 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency
1040 system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency
1041 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency
1042 system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency
1043 system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked
1044 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1045 system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked
1046 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1047 system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked
1048 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1049 system.cpu.icache.fast_writes 0 # number of fast writes performed
1050 system.cpu.icache.cache_copies 0 # number of cache copies performed
1051 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits
1052 system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits
1053 system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits
1054 system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits
1055 system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits
1056 system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits
1057 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses
1058 system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses
1059 system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses
1060 system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses
1061 system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses
1062 system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses
1063 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles
1064 system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles
1065 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles
1066 system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles
1067 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles
1068 system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles
1069 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses
1070 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses
1071 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses
1072 system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses
1073 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses
1074 system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses
1075 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency
1076 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency
1077 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency
1078 system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency
1079 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency
1080 system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency
1081 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1082 system.cpu.itb_walker_cache.replacements 7857 # number of replacements
1083 system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use
1084 system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks.
1085 system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks.
1086 system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks.
1087 system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit.
1088 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor
1089 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy
1090 system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy
1091 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits
1092 system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits
1093 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1094 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1095 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits
1096 system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits
1097 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits
1098 system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits
1099 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses
1100 system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses
1101 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses
1102 system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses
1103 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses
1104 system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses
1105 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles
1106 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles
1107 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles
1108 system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles
1109 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles
1110 system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles
1111 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses)
1112 system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses)
1113 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1114 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1115 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses
1116 system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses
1117 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses
1118 system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses
1119 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses
1120 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses
1121 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses
1122 system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses
1123 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses
1124 system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses
1125 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency
1126 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency
1127 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency
1128 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency
1129 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency
1130 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency
1131 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1132 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1133 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1134 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1135 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1136 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1137 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1138 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1139 system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks
1140 system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks
1141 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses
1142 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses
1143 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses
1144 system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses
1145 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses
1146 system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses
1147 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles
1148 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles
1149 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles
1150 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles
1151 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles
1152 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles
1153 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses
1154 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses
1155 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses
1156 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses
1157 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses
1158 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses
1159 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency
1160 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency
1161 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency
1162 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency
1163 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency
1164 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency
1165 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1166 system.cpu.dtb_walker_cache.replacements 67431 # number of replacements
1167 system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use
1168 system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks.
1169 system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks.
1170 system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks.
1171 system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit.
1172 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor
1173 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy
1174 system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy
1175 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits
1176 system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits
1177 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits
1178 system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits
1179 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits
1180 system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits
1181 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses
1182 system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses
1183 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses
1184 system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses
1185 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses
1186 system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses
1187 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles
1188 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles
1189 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles
1190 system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles
1191 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles
1192 system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles
1193 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses)
1194 system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses)
1195 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses
1196 system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses
1197 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses
1198 system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses
1199 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses
1200 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses
1201 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses
1202 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses
1203 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses
1204 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses
1205 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency
1206 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency
1207 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency
1208 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency
1209 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency
1210 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency
1211 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1212 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1213 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1214 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1215 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1216 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1217 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1218 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1219 system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks
1220 system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks
1221 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses
1222 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses
1223 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses
1224 system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses
1225 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses
1226 system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses
1227 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles
1228 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles
1229 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles
1230 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles
1231 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles
1232 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles
1233 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses
1234 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses
1235 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses
1236 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses
1237 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses
1238 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses
1239 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency
1240 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency
1241 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency
1242 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency
1243 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency
1244 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency
1245 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1246 system.cpu.dcache.replacements 1656381 # number of replacements
1247 system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use
1248 system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks.
1249 system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks.
1250 system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks.
1251 system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit.
1252 system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor
1253 system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
1254 system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
1255 system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits
1256 system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits
1257 system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits
1258 system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits
1259 system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits
1260 system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits
1261 system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits
1262 system.cpu.dcache.overall_hits::total 18979052 # number of overall hits
1263 system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # number of ReadReq misses
1264 system.cpu.dcache.ReadReq_misses::total 2237799 # number of ReadReq misses
1265 system.cpu.dcache.WriteReq_misses::cpu.data 315625 # number of WriteReq misses
1266 system.cpu.dcache.WriteReq_misses::total 315625 # number of WriteReq misses
1267 system.cpu.dcache.demand_misses::cpu.data 2553424 # number of demand (read+write) misses
1268 system.cpu.dcache.demand_misses::total 2553424 # number of demand (read+write) misses
1269 system.cpu.dcache.overall_misses::cpu.data 2553424 # number of overall misses
1270 system.cpu.dcache.overall_misses::total 2553424 # number of overall misses
1271 system.cpu.dcache.ReadReq_miss_latency::cpu.data 33108471000 # number of ReadReq miss cycles
1272 system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles
1273 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles
1274 system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles
1275 system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles
1276 system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles
1277 system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles
1278 system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles
1279 system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses)
1280 system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses)
1281 system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses)
1282 system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses)
1283 system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses
1284 system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses
1285 system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses
1286 system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses
1287 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses
1288 system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses
1289 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses
1290 system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses
1291 system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses
1292 system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses
1293 system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses
1294 system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses
1295 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency
1296 system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency
1297 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency
1298 system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency
1299 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency
1300 system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency
1301 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency
1302 system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency
1303 system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked
1304 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1305 system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked
1306 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1307 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked
1308 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1309 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1310 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1311 system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks
1312 system.cpu.dcache.writebacks::total 1558312 # number of writebacks
1313 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits
1314 system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits
1315 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits
1316 system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits
1317 system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits
1318 system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits
1319 system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits
1320 system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits
1321 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses
1322 system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses
1323 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses
1324 system.cpu.dcache.WriteReq_mshr_misses::total 289725 # number of WriteReq MSHR misses
1325 system.cpu.dcache.demand_mshr_misses::cpu.data 1659193 # number of demand (read+write) MSHR misses
1326 system.cpu.dcache.demand_mshr_misses::total 1659193 # number of demand (read+write) MSHR misses
1327 system.cpu.dcache.overall_mshr_misses::cpu.data 1659193 # number of overall MSHR misses
1328 system.cpu.dcache.overall_mshr_misses::total 1659193 # number of overall MSHR misses
1329 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17883109030 # number of ReadReq MSHR miss cycles
1330 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17883109030 # number of ReadReq MSHR miss cycles
1331 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11189452001 # number of WriteReq MSHR miss cycles
1332 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11189452001 # number of WriteReq MSHR miss cycles
1333 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29072561031 # number of demand (read+write) MSHR miss cycles
1334 system.cpu.dcache.demand_mshr_miss_latency::total 29072561031 # number of demand (read+write) MSHR miss cycles
1335 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29072561031 # number of overall MSHR miss cycles
1336 system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles
1337 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles
1338 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles
1339 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles
1340 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles
1341 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles
1342 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles
1343 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses
1344 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses
1345 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # mshr miss rate for WriteReq accesses
1346 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034460 # mshr miss rate for WriteReq accesses
1347 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for demand accesses
1348 system.cpu.dcache.demand_mshr_miss_rate::total 0.077055 # mshr miss rate for demand accesses
1349 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for overall accesses
1350 system.cpu.dcache.overall_mshr_miss_rate::total 0.077055 # mshr miss rate for overall accesses
1351 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13058.435122 # average ReadReq mshr miss latency
1352 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13058.435122 # average ReadReq mshr miss latency
1353 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38620.940551 # average WriteReq mshr miss latency
1354 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38620.940551 # average WriteReq mshr miss latency
1355 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency
1356 system.cpu.dcache.demand_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency
1357 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency
1358 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency
1359 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1360 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1361 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1362 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1363 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1364 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1365 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1366 system.cpu.l2cache.replacements 110887 # number of replacements
1367 system.cpu.l2cache.tagsinuse 64831.056251 # Cycle average of tags in use
1368 system.cpu.l2cache.total_refs 3780740 # Total number of references to valid blocks.
1369 system.cpu.l2cache.sampled_refs 175156 # Sample count of references to valid blocks.
1370 system.cpu.l2cache.avg_refs 21.584987 # Average number of references to valid blocks.
1371 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1372 system.cpu.l2cache.occ_blocks::writebacks 50733.546083 # Average occupied blocks per requestor
1373 system.cpu.l2cache.occ_blocks::cpu.dtb.walker 16.870188 # Average occupied blocks per requestor
1374 system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.435873 # Average occupied blocks per requestor
1375 system.cpu.l2cache.occ_blocks::cpu.inst 3102.105896 # Average occupied blocks per requestor
1376 system.cpu.l2cache.occ_blocks::cpu.data 10978.098210 # Average occupied blocks per requestor
1377 system.cpu.l2cache.occ_percent::writebacks 0.774132 # Average percentage of cache occupancy
1378 system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000257 # Average percentage of cache occupancy
1379 system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy
1380 system.cpu.l2cache.occ_percent::cpu.inst 0.047334 # Average percentage of cache occupancy
1381 system.cpu.l2cache.occ_percent::cpu.data 0.167512 # Average percentage of cache occupancy
1382 system.cpu.l2cache.occ_percent::total 0.989243 # Average percentage of cache occupancy
1383 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63592 # number of ReadReq hits
1384 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7072 # number of ReadReq hits
1385 system.cpu.l2cache.ReadReq_hits::cpu.inst 937746 # number of ReadReq hits
1386 system.cpu.l2cache.ReadReq_hits::cpu.data 1332853 # number of ReadReq hits
1387 system.cpu.l2cache.ReadReq_hits::total 2341263 # number of ReadReq hits
1388 system.cpu.l2cache.Writeback_hits::writebacks 1578360 # number of Writeback hits
1389 system.cpu.l2cache.Writeback_hits::total 1578360 # number of Writeback hits
1390 system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits
1391 system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits
1392 system.cpu.l2cache.ReadExReq_hits::cpu.data 154746 # number of ReadExReq hits
1393 system.cpu.l2cache.ReadExReq_hits::total 154746 # number of ReadExReq hits
1394 system.cpu.l2cache.demand_hits::cpu.dtb.walker 63592 # number of demand (read+write) hits
1395 system.cpu.l2cache.demand_hits::cpu.itb.walker 7072 # number of demand (read+write) hits
1396 system.cpu.l2cache.demand_hits::cpu.inst 937746 # number of demand (read+write) hits
1397 system.cpu.l2cache.demand_hits::cpu.data 1487599 # number of demand (read+write) hits
1398 system.cpu.l2cache.demand_hits::total 2496009 # number of demand (read+write) hits
1399 system.cpu.l2cache.overall_hits::cpu.dtb.walker 63592 # number of overall hits
1400 system.cpu.l2cache.overall_hits::cpu.itb.walker 7072 # number of overall hits
1401 system.cpu.l2cache.overall_hits::cpu.inst 937746 # number of overall hits
1402 system.cpu.l2cache.overall_hits::cpu.data 1487599 # number of overall hits
1403 system.cpu.l2cache.overall_hits::total 2496009 # number of overall hits
1404 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses
1405 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
1406 system.cpu.l2cache.ReadReq_misses::cpu.inst 16053 # number of ReadReq misses
1407 system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
1408 system.cpu.l2cache.ReadReq_misses::total 51995 # number of ReadReq misses
1409 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1482 # number of UpgradeReq misses
1410 system.cpu.l2cache.UpgradeReq_misses::total 1482 # number of UpgradeReq misses
1411 system.cpu.l2cache.ReadExReq_misses::cpu.data 132789 # number of ReadExReq misses
1412 system.cpu.l2cache.ReadExReq_misses::total 132789 # number of ReadExReq misses
1413 system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses
1414 system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
1415 system.cpu.l2cache.demand_misses::cpu.inst 16053 # number of demand (read+write) misses
1416 system.cpu.l2cache.demand_misses::cpu.data 168664 # number of demand (read+write) misses
1417 system.cpu.l2cache.demand_misses::total 184784 # number of demand (read+write) misses
1418 system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses
1419 system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
1420 system.cpu.l2cache.overall_misses::cpu.inst 16053 # number of overall misses
1421 system.cpu.l2cache.overall_misses::cpu.data 168664 # number of overall misses
1422 system.cpu.l2cache.overall_misses::total 184784 # number of overall misses
1423 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6023000 # number of ReadReq miss cycles
1424 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 505500 # number of ReadReq miss cycles
1425 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1392940500 # number of ReadReq miss cycles
1426 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2991754000 # number of ReadReq miss cycles
1427 system.cpu.l2cache.ReadReq_miss_latency::total 4391223000 # number of ReadReq miss cycles
1428 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17604000 # number of UpgradeReq miss cycles
1429 system.cpu.l2cache.UpgradeReq_miss_latency::total 17604000 # number of UpgradeReq miss cycles
1430 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9307246499 # number of ReadExReq miss cycles
1431 system.cpu.l2cache.ReadExReq_miss_latency::total 9307246499 # number of ReadExReq miss cycles
1432 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6023000 # number of demand (read+write) miss cycles
1433 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 505500 # number of demand (read+write) miss cycles
1434 system.cpu.l2cache.demand_miss_latency::cpu.inst 1392940500 # number of demand (read+write) miss cycles
1435 system.cpu.l2cache.demand_miss_latency::cpu.data 12299000499 # number of demand (read+write) miss cycles
1436 system.cpu.l2cache.demand_miss_latency::total 13698469499 # number of demand (read+write) miss cycles
1437 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6023000 # number of overall miss cycles
1438 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 505500 # number of overall miss cycles
1439 system.cpu.l2cache.overall_miss_latency::cpu.inst 1392940500 # number of overall miss cycles
1440 system.cpu.l2cache.overall_miss_latency::cpu.data 12299000499 # number of overall miss cycles
1441 system.cpu.l2cache.overall_miss_latency::total 13698469499 # number of overall miss cycles
1442 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63653 # number of ReadReq accesses(hits+misses)
1443 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7078 # number of ReadReq accesses(hits+misses)
1444 system.cpu.l2cache.ReadReq_accesses::cpu.inst 953799 # number of ReadReq accesses(hits+misses)
1445 system.cpu.l2cache.ReadReq_accesses::cpu.data 1368728 # number of ReadReq accesses(hits+misses)
1446 system.cpu.l2cache.ReadReq_accesses::total 2393258 # number of ReadReq accesses(hits+misses)
1447 system.cpu.l2cache.Writeback_accesses::writebacks 1578360 # number of Writeback accesses(hits+misses)
1448 system.cpu.l2cache.Writeback_accesses::total 1578360 # number of Writeback accesses(hits+misses)
1449 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses)
1450 system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses)
1451 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287535 # number of ReadExReq accesses(hits+misses)
1452 system.cpu.l2cache.ReadExReq_accesses::total 287535 # number of ReadExReq accesses(hits+misses)
1453 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63653 # number of demand (read+write) accesses
1454 system.cpu.l2cache.demand_accesses::cpu.itb.walker 7078 # number of demand (read+write) accesses
1455 system.cpu.l2cache.demand_accesses::cpu.inst 953799 # number of demand (read+write) accesses
1456 system.cpu.l2cache.demand_accesses::cpu.data 1656263 # number of demand (read+write) accesses
1457 system.cpu.l2cache.demand_accesses::total 2680793 # number of demand (read+write) accesses
1458 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63653 # number of overall (read+write) accesses
1459 system.cpu.l2cache.overall_accesses::cpu.itb.walker 7078 # number of overall (read+write) accesses
1460 system.cpu.l2cache.overall_accesses::cpu.inst 953799 # number of overall (read+write) accesses
1461 system.cpu.l2cache.overall_accesses::cpu.data 1656263 # number of overall (read+write) accesses
1462 system.cpu.l2cache.overall_accesses::total 2680793 # number of overall (read+write) accesses
1463 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000958 # miss rate for ReadReq accesses
1464 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000848 # miss rate for ReadReq accesses
1465 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016831 # miss rate for ReadReq accesses
1466 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026210 # miss rate for ReadReq accesses
1467 system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses
1468 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823791 # miss rate for UpgradeReq accesses
1469 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823791 # miss rate for UpgradeReq accesses
1470 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461819 # miss rate for ReadExReq accesses
1471 system.cpu.l2cache.ReadExReq_miss_rate::total 0.461819 # miss rate for ReadExReq accesses
1472 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000958 # miss rate for demand accesses
1473 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000848 # miss rate for demand accesses
1474 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016831 # miss rate for demand accesses
1475 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101834 # miss rate for demand accesses
1476 system.cpu.l2cache.demand_miss_rate::total 0.068929 # miss rate for demand accesses
1477 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000958 # miss rate for overall accesses
1478 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000848 # miss rate for overall accesses
1479 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016831 # miss rate for overall accesses
1480 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101834 # miss rate for overall accesses
1481 system.cpu.l2cache.overall_miss_rate::total 0.068929 # miss rate for overall accesses
1482 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 98737.704918 # average ReadReq miss latency
1483 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84250 # average ReadReq miss latency
1484 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86771.351149 # average ReadReq miss latency
1485 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83393.839721 # average ReadReq miss latency
1486 system.cpu.l2cache.ReadReq_avg_miss_latency::total 84454.716800 # average ReadReq miss latency
1487 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11878.542510 # average UpgradeReq miss latency
1488 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11878.542510 # average UpgradeReq miss latency
1489 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70090.493181 # average ReadExReq miss latency
1490 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70090.493181 # average ReadExReq miss latency
1491 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 98737.704918 # average overall miss latency
1492 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84250 # average overall miss latency
1493 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86771.351149 # average overall miss latency
1494 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72920.128178 # average overall miss latency
1495 system.cpu.l2cache.demand_avg_miss_latency::total 74132.335586 # average overall miss latency
1496 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 98737.704918 # average overall miss latency
1497 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84250 # average overall miss latency
1498 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86771.351149 # average overall miss latency
1499 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72920.128178 # average overall miss latency
1500 system.cpu.l2cache.overall_avg_miss_latency::total 74132.335586 # average overall miss latency
1501 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1502 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1503 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1504 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1505 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1506 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1507 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1508 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1509 system.cpu.l2cache.writebacks::writebacks 101458 # number of writebacks
1510 system.cpu.l2cache.writebacks::total 101458 # number of writebacks
1511 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
1512 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
1513 system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
1514 system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
1515 system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
1516 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
1517 system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
1518 system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
1519 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
1520 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses
1521 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
1522 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16050 # number of ReadReq MSHR misses
1523 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35873 # number of ReadReq MSHR misses
1524 system.cpu.l2cache.ReadReq_mshr_misses::total 51990 # number of ReadReq MSHR misses
1525 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1482 # number of UpgradeReq MSHR misses
1526 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses
1527 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132789 # number of ReadExReq MSHR misses
1528 system.cpu.l2cache.ReadExReq_mshr_misses::total 132789 # number of ReadExReq MSHR misses
1529 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses
1530 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
1531 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16050 # number of demand (read+write) MSHR misses
1532 system.cpu.l2cache.demand_mshr_misses::cpu.data 168662 # number of demand (read+write) MSHR misses
1533 system.cpu.l2cache.demand_mshr_misses::total 184779 # number of demand (read+write) MSHR misses
1534 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses
1535 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
1536 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16050 # number of overall MSHR misses
1537 system.cpu.l2cache.overall_mshr_misses::cpu.data 168662 # number of overall MSHR misses
1538 system.cpu.l2cache.overall_mshr_misses::total 184779 # number of overall MSHR misses
1539 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5260750 # number of ReadReq MSHR miss cycles
1540 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles
1541 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1193323263 # number of ReadReq MSHR miss cycles
1542 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545977303 # number of ReadReq MSHR miss cycles
1543 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3744991316 # number of ReadReq MSHR miss cycles
1544 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15894959 # number of UpgradeReq MSHR miss cycles
1545 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15894959 # number of UpgradeReq MSHR miss cycles
1546 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7671814321 # number of ReadExReq MSHR miss cycles
1547 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7671814321 # number of ReadExReq MSHR miss cycles
1548 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5260750 # number of demand (read+write) MSHR miss cycles
1549 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles
1550 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1193323263 # number of demand (read+write) MSHR miss cycles
1551 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10217791624 # number of demand (read+write) MSHR miss cycles
1552 system.cpu.l2cache.demand_mshr_miss_latency::total 11416805637 # number of demand (read+write) MSHR miss cycles
1553 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5260750 # number of overall MSHR miss cycles
1554 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles
1555 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1193323263 # number of overall MSHR miss cycles
1556 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10217791624 # number of overall MSHR miss cycles
1557 system.cpu.l2cache.overall_mshr_miss_latency::total 11416805637 # number of overall MSHR miss cycles
1558 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236814500 # number of ReadReq MSHR uncacheable cycles
1559 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236814500 # number of ReadReq MSHR uncacheable cycles
1560 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356578000 # number of WriteReq MSHR uncacheable cycles
1561 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356578000 # number of WriteReq MSHR uncacheable cycles
1562 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593392500 # number of overall MSHR uncacheable cycles
1563 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593392500 # number of overall MSHR uncacheable cycles
1564 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses
1565 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for ReadReq accesses
1566 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for ReadReq accesses
1567 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026209 # mshr miss rate for ReadReq accesses
1568 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses
1569 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823791 # mshr miss rate for UpgradeReq accesses
1570 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823791 # mshr miss rate for UpgradeReq accesses
1571 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461819 # mshr miss rate for ReadExReq accesses
1572 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461819 # mshr miss rate for ReadExReq accesses
1573 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses
1574 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for demand accesses
1575 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for demand accesses
1576 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for demand accesses
1577 system.cpu.l2cache.demand_mshr_miss_rate::total 0.068927 # mshr miss rate for demand accesses
1578 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses
1579 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for overall accesses
1580 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for overall accesses
1581 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for overall accesses
1582 system.cpu.l2cache.overall_mshr_miss_rate::total 0.068927 # mshr miss rate for overall accesses
1583 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average ReadReq mshr miss latency
1584 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency
1585 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74350.359065 # average ReadReq mshr miss latency
1586 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70971.965071 # average ReadReq mshr miss latency
1587 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72032.916253 # average ReadReq mshr miss latency
1588 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10725.343455 # average UpgradeReq mshr miss latency
1589 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10725.343455 # average UpgradeReq mshr miss latency
1590 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57774.471688 # average ReadExReq mshr miss latency
1591 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57774.471688 # average ReadExReq mshr miss latency
1592 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency
1593 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency
1594 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency
1595 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency
1596 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency
1597 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency
1598 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency
1599 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency
1600 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency
1601 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency
1602 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1603 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1604 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1605 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1606 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1607 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1608 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1609 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1610 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1612 ---------- End Simulation Statistics ----------
projects / gem5.git / blob