2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.129877 # Number of seconds simulated
4 sim_ticks 5129876981500 # Number of ticks simulated
5 final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 181923 # Simulator instruction rate (inst/s)
8 host_op_rate 359604 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2288414721 # Simulator tick rate (ticks/s)
10 host_mem_usage 752624 # Number of bytes of host memory used
11 host_seconds 2241.67 # Real time elapsed on the host
12 sim_insts 407812863 # Number of instructions simulated
13 sim_ops 806114915 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory
25 system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory
27 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory
34 system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory
36 system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.readReqs 186153 # Number of read requests accepted
55 system.physmem.writeReqs 149802 # Number of write requests accepted
56 system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue
57 system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue
58 system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM
59 system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue
60 system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM
61 system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side
62 system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side
63 system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue
64 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
65 system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write
66 system.physmem.perBankRdBursts::0 11465 # Per bank write bursts
67 system.physmem.perBankRdBursts::1 11004 # Per bank write bursts
68 system.physmem.perBankRdBursts::2 11873 # Per bank write bursts
69 system.physmem.perBankRdBursts::3 11540 # Per bank write bursts
70 system.physmem.perBankRdBursts::4 11961 # Per bank write bursts
71 system.physmem.perBankRdBursts::5 11322 # Per bank write bursts
72 system.physmem.perBankRdBursts::6 11640 # Per bank write bursts
73 system.physmem.perBankRdBursts::7 11420 # Per bank write bursts
74 system.physmem.perBankRdBursts::8 11351 # Per bank write bursts
75 system.physmem.perBankRdBursts::9 11861 # Per bank write bursts
76 system.physmem.perBankRdBursts::10 11826 # Per bank write bursts
77 system.physmem.perBankRdBursts::11 12031 # Per bank write bursts
78 system.physmem.perBankRdBursts::12 11538 # Per bank write bursts
79 system.physmem.perBankRdBursts::13 12375 # Per bank write bursts
80 system.physmem.perBankRdBursts::14 11569 # Per bank write bursts
81 system.physmem.perBankRdBursts::15 11089 # Per bank write bursts
82 system.physmem.perBankWrBursts::0 10234 # Per bank write bursts
83 system.physmem.perBankWrBursts::1 9627 # Per bank write bursts
84 system.physmem.perBankWrBursts::2 9640 # Per bank write bursts
85 system.physmem.perBankWrBursts::3 9149 # Per bank write bursts
86 system.physmem.perBankWrBursts::4 9237 # Per bank write bursts
87 system.physmem.perBankWrBursts::5 9047 # Per bank write bursts
88 system.physmem.perBankWrBursts::6 8744 # Per bank write bursts
89 system.physmem.perBankWrBursts::7 8727 # Per bank write bursts
90 system.physmem.perBankWrBursts::8 9070 # Per bank write bursts
91 system.physmem.perBankWrBursts::9 9221 # Per bank write bursts
92 system.physmem.perBankWrBursts::10 9815 # Per bank write bursts
93 system.physmem.perBankWrBursts::11 9405 # Per bank write bursts
94 system.physmem.perBankWrBursts::12 9499 # Per bank write bursts
95 system.physmem.perBankWrBursts::13 9604 # Per bank write bursts
96 system.physmem.perBankWrBursts::14 9640 # Per bank write bursts
97 system.physmem.perBankWrBursts::15 9124 # Per bank write bursts
98 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99 system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
100 system.physmem.totGap 5129876930000 # Total gap between requests
101 system.physmem.readPktSize::0 0 # Read request sizes (log2)
102 system.physmem.readPktSize::1 0 # Read request sizes (log2)
103 system.physmem.readPktSize::2 0 # Read request sizes (log2)
104 system.physmem.readPktSize::3 0 # Read request sizes (log2)
105 system.physmem.readPktSize::4 0 # Read request sizes (log2)
106 system.physmem.readPktSize::5 0 # Read request sizes (log2)
107 system.physmem.readPktSize::6 186153 # Read request sizes (log2)
108 system.physmem.writePktSize::0 0 # Write request sizes (log2)
109 system.physmem.writePktSize::1 0 # Write request sizes (log2)
110 system.physmem.writePktSize::2 0 # Write request sizes (log2)
111 system.physmem.writePktSize::3 0 # Write request sizes (log2)
112 system.physmem.writePktSize::4 0 # Write request sizes (log2)
113 system.physmem.writePktSize::5 0 # Write request sizes (log2)
114 system.physmem.writePktSize::6 149802 # Write request sizes (log2)
115 system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::17 7174 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::18 7679 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::19 7821 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::27 9218 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::30 7716 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::31 7761 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::32 7619 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::42 102 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::43 101 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::45 129 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::46 110 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
211 system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation
225 system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes
231 system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads
265 system.physmem.totQLat 2030519500 # Total ticks spent queuing
266 system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM
267 system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers
268 system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst
269 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
270 system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst
271 system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
272 system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
273 system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
274 system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
275 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
276 system.physmem.busUtil 0.03 # Data bus utilization in percentage
277 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
278 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
279 system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing
280 system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing
281 system.physmem.readRowHits 152396 # Number of row buffer hits during reads
282 system.physmem.writeRowHits 110551 # Number of row buffer hits during writes
283 system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
284 system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes
285 system.physmem.avgGap 15269535.89 # Average gap between requests
286 system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
287 system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states
288 system.physmem.memoryStateTime::REF 171297620000 # Time in different power states
289 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
290 system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states
291 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
292 system.physmem.actEnergy::0 267480360 # Energy for activate commands per rank (pJ)
293 system.physmem.actEnergy::1 282131640 # Energy for activate commands per rank (pJ)
294 system.physmem.preEnergy::0 145946625 # Energy for precharge commands per rank (pJ)
295 system.physmem.preEnergy::1 153940875 # Energy for precharge commands per rank (pJ)
296 system.physmem.readEnergy::0 719347200 # Energy for read commands per rank (pJ)
297 system.physmem.readEnergy::1 730392000 # Energy for read commands per rank (pJ)
298 system.physmem.writeEnergy::0 482144400 # Energy for write commands per rank (pJ)
299 system.physmem.writeEnergy::1 488449440 # Energy for write commands per rank (pJ)
300 system.physmem.refreshEnergy::0 335058144720 # Energy for refresh commands per rank (pJ)
301 system.physmem.refreshEnergy::1 335058144720 # Energy for refresh commands per rank (pJ)
302 system.physmem.actBackEnergy::0 129492550125 # Energy for active background per rank (pJ)
303 system.physmem.actBackEnergy::1 129753331110 # Energy for active background per rank (pJ)
304 system.physmem.preBackEnergy::0 2964331954500 # Energy for precharge background per rank (pJ)
305 system.physmem.preBackEnergy::1 2964103199250 # Energy for precharge background per rank (pJ)
306 system.physmem.totalEnergy::0 3430497567930 # Total energy per rank (pJ)
307 system.physmem.totalEnergy::1 3430569589035 # Total energy per rank (pJ)
308 system.physmem.averagePower::0 668.729942 # Core power per rank (mW)
309 system.physmem.averagePower::1 668.743982 # Core power per rank (mW)
310 system.membus.trans_dist::ReadReq 662528 # Transaction distribution
311 system.membus.trans_dist::ReadResp 662520 # Transaction distribution
312 system.membus.trans_dist::WriteReq 13776 # Transaction distribution
313 system.membus.trans_dist::WriteResp 13776 # Transaction distribution
314 system.membus.trans_dist::Writeback 103082 # Transaction distribution
315 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
316 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
317 system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution
318 system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution
319 system.membus.trans_dist::ReadExReq 133413 # Transaction distribution
320 system.membus.trans_dist::ReadExResp 133410 # Transaction distribution
321 system.membus.trans_dist::MessageReq 1645 # Transaction distribution
322 system.membus.trans_dist::MessageResp 1645 # Transaction distribution
323 system.membus.trans_dist::BadAddressError 8 # Transaction distribution
324 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
325 system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
326 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
327 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
328 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes)
329 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
330 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes)
331 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes)
332 system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes)
333 system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes)
334 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
335 system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
336 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
337 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
338 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes)
339 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes)
340 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
341 system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
342 system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes)
343 system.membus.snoops 943 # Total snoops (count)
344 system.membus.snoop_fanout::samples 338647 # Request fanout histogram
345 system.membus.snoop_fanout::mean 1 # Request fanout histogram
346 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
347 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
348 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
349 system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram
350 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
351 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
352 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
353 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
354 system.membus.snoop_fanout::total 338647 # Request fanout histogram
355 system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks)
356 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
357 system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks)
358 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
359 system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
360 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
361 system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks)
362 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
363 system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
364 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
365 system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
366 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
367 system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks)
368 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
369 system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks)
370 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
371 system.iocache.tags.replacements 47584 # number of replacements
372 system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use
373 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
374 system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks.
375 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
376 system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit.
377 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor
378 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy
379 system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy
380 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
381 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
382 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
383 system.iocache.tags.tag_accesses 428751 # Number of tag accesses
384 system.iocache.tags.data_accesses 428751 # Number of data accesses
385 system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
386 system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
387 system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses
388 system.iocache.ReadReq_misses::total 919 # number of ReadReq misses
389 system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses
390 system.iocache.demand_misses::total 919 # number of demand (read+write) misses
391 system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses
392 system.iocache.overall_misses::total 919 # number of overall misses
393 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles
394 system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles
395 system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles
396 system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles
397 system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles
398 system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles
399 system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses)
400 system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses)
401 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
402 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
403 system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses
404 system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses
405 system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses
406 system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses
407 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
408 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
409 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
410 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
411 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
412 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
413 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency
414 system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency
415 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
416 system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency
417 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency
418 system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency
419 system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
420 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421 system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
422 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
423 system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
424 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425 system.iocache.fast_writes 46720 # number of fast writes performed
426 system.iocache.cache_copies 0 # number of cache copies performed
427 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses
428 system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses
429 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
430 system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
431 system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses
432 system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses
433 system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses
434 system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses
435 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles
436 system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles
437 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles
438 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles
439 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles
440 system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles
441 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles
442 system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles
443 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
444 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
445 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
446 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
447 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
448 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
449 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
450 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
451 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency
452 system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency
453 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency
454 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency
455 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
456 system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
457 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency
458 system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency
459 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
460 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
461 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
462 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
463 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
464 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
465 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
466 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
467 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
468 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
469 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
470 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
471 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
472 system.iobus.trans_dist::ReadReq 225575 # Transaction distribution
473 system.iobus.trans_dist::ReadResp 225575 # Transaction distribution
474 system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
475 system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
476 system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
477 system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
478 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
479 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
480 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
481 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
482 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
483 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
484 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
485 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
486 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
487 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
488 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
489 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
490 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
491 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
492 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
493 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
494 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
495 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
496 system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
497 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes)
498 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes)
499 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
500 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
501 system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes)
502 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
503 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
504 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
505 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
506 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
507 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
508 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
509 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
510 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
511 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
512 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
513 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
514 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
515 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
516 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
517 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
518 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
519 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
520 system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
521 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes)
522 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes)
523 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
524 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
525 system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes)
526 system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks)
527 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
528 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
529 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
530 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
531 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
532 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
533 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
534 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
535 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
536 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
537 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
538 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
539 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
540 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
541 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
542 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
543 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
544 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
545 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
546 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
547 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
548 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
549 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
550 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
551 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
552 system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
553 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
554 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
555 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
556 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
557 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
558 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
559 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
560 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
561 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
562 system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks)
563 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
564 system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
565 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
566 system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
567 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
568 system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks)
569 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
570 system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
571 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
572 system.cpu_clk_domain.clock 500 # Clock period in ticks
573 system.cpu.branchPred.lookups 86898883 # Number of BP lookups
574 system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted
575 system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect
576 system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups
577 system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits
578 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
579 system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage
580 system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target.
581 system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions.
582 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
583 system.cpu.numCycles 449490093 # number of cpu cycles simulated
584 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
585 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
586 system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss
587 system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed
588 system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered
589 system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken
590 system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked
591 system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing
592 system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb
593 system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
594 system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps
595 system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions
596 system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR
597 system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched
598 system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed
599 system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed
600 system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total)
601 system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total)
602 system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total)
603 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
604 system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total)
605 system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total)
606 system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total)
607 system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total)
608 system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total)
609 system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total)
610 system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total)
611 system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total)
612 system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total)
613 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
614 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
615 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
616 system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total)
617 system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle
618 system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle
619 system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle
620 system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked
621 system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running
622 system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking
623 system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing
624 system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode
625 system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing
626 system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle
627 system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking
628 system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst
629 system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running
630 system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking
631 system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename
632 system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full
633 system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full
634 system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full
635 system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full
636 system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed
637 system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made
638 system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups
639 system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups
640 system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed
641 system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing
642 system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed
643 system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed
644 system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer
645 system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit.
646 system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit.
647 system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads.
648 system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores.
649 system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec)
650 system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ
651 system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued
652 system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued
653 system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling
654 system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph
655 system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed
656 system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle
657 system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle
658 system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle
659 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
660 system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle
661 system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle
662 system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle
663 system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle
664 system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle
665 system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle
666 system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle
667 system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle
668 system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle
669 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
670 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
671 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
672 system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle
673 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
674 system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available
675 system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available
676 system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available
677 system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available
678 system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available
679 system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available
680 system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available
681 system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available
682 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
683 system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available
684 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available
685 system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available
686 system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available
687 system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available
688 system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available
689 system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available
690 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available
691 system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available
692 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available
693 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available
694 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available
695 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available
696 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available
697 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available
698 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available
699 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available
700 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available
701 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available
702 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
703 system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available
704 system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available
705 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
706 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
707 system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued
708 system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued
709 system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued
710 system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued
711 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
712 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
713 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
714 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
715 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
716 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
717 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
718 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
719 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
720 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
721 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
722 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
723 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
724 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
725 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
726 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
727 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
728 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
729 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
730 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
731 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
732 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
733 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
734 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
735 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
736 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
737 system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued
738 system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued
739 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
740 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
741 system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued
742 system.cpu.iq.rate 1.833363 # Inst issue rate
743 system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested
744 system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst)
745 system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads
746 system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes
747 system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses
748 system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads
749 system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes
750 system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses
751 system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses
752 system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
753 system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores
754 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
755 system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed
756 system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed
757 system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations
758 system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed
759 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
760 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
761 system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled
762 system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked
763 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
764 system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing
765 system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking
766 system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking
767 system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ
768 system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch
769 system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions
770 system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions
771 system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions
772 system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall
773 system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall
774 system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations
775 system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly
776 system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly
777 system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute
778 system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions
779 system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed
780 system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute
781 system.cpu.iew.exec_swp 0 # number of swp insts executed
782 system.cpu.iew.exec_nop 0 # number of nop insts executed
783 system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed
784 system.cpu.iew.exec_branches 83289157 # Number of branches executed
785 system.cpu.iew.exec_stores 9174614 # Number of stores executed
786 system.cpu.iew.exec_rate 1.829760 # Inst execution rate
787 system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit
788 system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back
789 system.cpu.iew.wb_producers 640910074 # num instructions producing a value
790 system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value
791 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
792 system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle
793 system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back
794 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
795 system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit
796 system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards
797 system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted
798 system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle
799 system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle
800 system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle
801 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
802 system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle
803 system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle
804 system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle
805 system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle
806 system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle
807 system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle
808 system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle
809 system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle
810 system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle
811 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
812 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
813 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
814 system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle
815 system.cpu.commit.committedInsts 407812863 # Number of instructions committed
816 system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed
817 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
818 system.cpu.commit.refs 22429266 # Number of memory references committed
819 system.cpu.commit.loads 14000019 # Number of loads committed
820 system.cpu.commit.membars 474889 # Number of memory barriers committed
821 system.cpu.commit.branches 82168190 # Number of branches committed
822 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
823 system.cpu.commit.int_insts 734958550 # Number of committed integer instructions.
824 system.cpu.commit.function_calls 1155635 # Number of function calls committed.
825 system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction
826 system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction
827 system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction
828 system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction
829 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
830 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
831 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
832 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
833 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
834 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
835 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
836 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
837 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
838 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
839 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
840 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
841 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
842 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
843 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
844 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
845 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
846 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
847 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
848 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
849 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
850 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
851 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
852 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
853 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
854 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
855 system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction
856 system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction
857 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
858 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
859 system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction
860 system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached
861 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
862 system.cpu.rob.rob_reads 1268217156 # The number of ROB reads
863 system.cpu.rob.rob_writes 1664635865 # The number of ROB writes
864 system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself
865 system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling
866 system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
867 system.cpu.committedInsts 407812863 # Number of Instructions Simulated
868 system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated
869 system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction
870 system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads
871 system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle
872 system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads
873 system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads
874 system.cpu.int_regfile_writes 655932610 # number of integer regfile writes
875 system.cpu.fp_regfile_reads 56 # number of floating regfile reads
876 system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads
877 system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes
878 system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads
879 system.cpu.misc_regfile_writes 402863 # number of misc regfile writes
880 system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution
881 system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution
882 system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution
883 system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution
884 system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution
885 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution
886 system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution
887 system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution
888 system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution
889 system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution
890 system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
891 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes)
892 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes)
893 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes)
894 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes)
895 system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes)
896 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes)
897 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes)
898 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes)
899 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes)
900 system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes)
901 system.cpu.toL2Bus.snoops 61506 # Total snoops (count)
902 system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram
903 system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram
904 system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram
905 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
906 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
907 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
908 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
909 system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram
910 system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram
911 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
912 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
913 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
914 system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram
915 system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks)
916 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
917 system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks)
918 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
919 system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks)
920 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
921 system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks)
922 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
923 system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks)
924 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
925 system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks)
926 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
927 system.cpu.icache.tags.replacements 1003070 # number of replacements
928 system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use
929 system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks.
930 system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks.
931 system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks.
932 system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit.
933 system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor
934 system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy
935 system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy
936 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
937 system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
938 system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id
939 system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
940 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
941 system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses
942 system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses
943 system.cpu.icache.ReadReq_hits::cpu.inst 8117984 # number of ReadReq hits
944 system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits
945 system.cpu.icache.demand_hits::cpu.inst 8117984 # number of demand (read+write) hits
946 system.cpu.icache.demand_hits::total 8117984 # number of demand (read+write) hits
947 system.cpu.icache.overall_hits::cpu.inst 8117984 # number of overall hits
948 system.cpu.icache.overall_hits::total 8117984 # number of overall hits
949 system.cpu.icache.ReadReq_misses::cpu.inst 1066696 # number of ReadReq misses
950 system.cpu.icache.ReadReq_misses::total 1066696 # number of ReadReq misses
951 system.cpu.icache.demand_misses::cpu.inst 1066696 # number of demand (read+write) misses
952 system.cpu.icache.demand_misses::total 1066696 # number of demand (read+write) misses
953 system.cpu.icache.overall_misses::cpu.inst 1066696 # number of overall misses
954 system.cpu.icache.overall_misses::total 1066696 # number of overall misses
955 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14789893561 # number of ReadReq miss cycles
956 system.cpu.icache.ReadReq_miss_latency::total 14789893561 # number of ReadReq miss cycles
957 system.cpu.icache.demand_miss_latency::cpu.inst 14789893561 # number of demand (read+write) miss cycles
958 system.cpu.icache.demand_miss_latency::total 14789893561 # number of demand (read+write) miss cycles
959 system.cpu.icache.overall_miss_latency::cpu.inst 14789893561 # number of overall miss cycles
960 system.cpu.icache.overall_miss_latency::total 14789893561 # number of overall miss cycles
961 system.cpu.icache.ReadReq_accesses::cpu.inst 9184680 # number of ReadReq accesses(hits+misses)
962 system.cpu.icache.ReadReq_accesses::total 9184680 # number of ReadReq accesses(hits+misses)
963 system.cpu.icache.demand_accesses::cpu.inst 9184680 # number of demand (read+write) accesses
964 system.cpu.icache.demand_accesses::total 9184680 # number of demand (read+write) accesses
965 system.cpu.icache.overall_accesses::cpu.inst 9184680 # number of overall (read+write) accesses
966 system.cpu.icache.overall_accesses::total 9184680 # number of overall (read+write) accesses
967 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116139 # miss rate for ReadReq accesses
968 system.cpu.icache.ReadReq_miss_rate::total 0.116139 # miss rate for ReadReq accesses
969 system.cpu.icache.demand_miss_rate::cpu.inst 0.116139 # miss rate for demand accesses
970 system.cpu.icache.demand_miss_rate::total 0.116139 # miss rate for demand accesses
971 system.cpu.icache.overall_miss_rate::cpu.inst 0.116139 # miss rate for overall accesses
972 system.cpu.icache.overall_miss_rate::total 0.116139 # miss rate for overall accesses
973 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922 # average ReadReq miss latency
974 system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922 # average ReadReq miss latency
975 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency
976 system.cpu.icache.demand_avg_miss_latency::total 13865.143922 # average overall miss latency
977 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency
978 system.cpu.icache.overall_avg_miss_latency::total 13865.143922 # average overall miss latency
979 system.cpu.icache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked
980 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
981 system.cpu.icache.blocked::no_mshrs 266 # number of cycles access was blocked
982 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
983 system.cpu.icache.avg_blocked_cycles::no_mshrs 22.943609 # average number of cycles each access was blocked
984 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
985 system.cpu.icache.fast_writes 0 # number of fast writes performed
986 system.cpu.icache.cache_copies 0 # number of cache copies performed
987 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63068 # number of ReadReq MSHR hits
988 system.cpu.icache.ReadReq_mshr_hits::total 63068 # number of ReadReq MSHR hits
989 system.cpu.icache.demand_mshr_hits::cpu.inst 63068 # number of demand (read+write) MSHR hits
990 system.cpu.icache.demand_mshr_hits::total 63068 # number of demand (read+write) MSHR hits
991 system.cpu.icache.overall_mshr_hits::cpu.inst 63068 # number of overall MSHR hits
992 system.cpu.icache.overall_mshr_hits::total 63068 # number of overall MSHR hits
993 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1003628 # number of ReadReq MSHR misses
994 system.cpu.icache.ReadReq_mshr_misses::total 1003628 # number of ReadReq MSHR misses
995 system.cpu.icache.demand_mshr_misses::cpu.inst 1003628 # number of demand (read+write) MSHR misses
996 system.cpu.icache.demand_mshr_misses::total 1003628 # number of demand (read+write) MSHR misses
997 system.cpu.icache.overall_mshr_misses::cpu.inst 1003628 # number of overall MSHR misses
998 system.cpu.icache.overall_mshr_misses::total 1003628 # number of overall MSHR misses
999 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143729999 # number of ReadReq MSHR miss cycles
1000 system.cpu.icache.ReadReq_mshr_miss_latency::total 12143729999 # number of ReadReq MSHR miss cycles
1001 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143729999 # number of demand (read+write) MSHR miss cycles
1002 system.cpu.icache.demand_mshr_miss_latency::total 12143729999 # number of demand (read+write) MSHR miss cycles
1003 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143729999 # number of overall MSHR miss cycles
1004 system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles
1005 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for ReadReq accesses
1006 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses
1007 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for demand accesses
1008 system.cpu.icache.demand_mshr_miss_rate::total 0.109272 # mshr miss rate for demand accesses
1009 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for overall accesses
1010 system.cpu.icache.overall_mshr_miss_rate::total 0.109272 # mshr miss rate for overall accesses
1011 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency
1012 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency
1013 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency
1014 system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency
1015 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency
1016 system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency
1017 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1018 system.cpu.itb_walker_cache.tags.replacements 16690 # number of replacements
1019 system.cpu.itb_walker_cache.tags.tagsinuse 6.006176 # Cycle average of tags in use
1020 system.cpu.itb_walker_cache.tags.total_refs 23588 # Total number of references to valid blocks.
1021 system.cpu.itb_walker_cache.tags.sampled_refs 16704 # Sample count of references to valid blocks.
1022 system.cpu.itb_walker_cache.tags.avg_refs 1.412117 # Average number of references to valid blocks.
1023 system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000 # Cycle when the warmup percentage was hit.
1024 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006176 # Average occupied blocks per requestor
1025 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375386 # Average percentage of cache occupancy
1026 system.cpu.itb_walker_cache.tags.occ_percent::total 0.375386 # Average percentage of cache occupancy
1027 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
1028 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
1029 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
1030 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
1031 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
1032 system.cpu.itb_walker_cache.tags.tag_accesses 99931 # Number of tag accesses
1033 system.cpu.itb_walker_cache.tags.data_accesses 99931 # Number of data accesses
1034 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 23592 # number of ReadReq hits
1035 system.cpu.itb_walker_cache.ReadReq_hits::total 23592 # number of ReadReq hits
1036 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1037 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1038 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 23594 # number of demand (read+write) hits
1039 system.cpu.itb_walker_cache.demand_hits::total 23594 # number of demand (read+write) hits
1040 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 23594 # number of overall hits
1041 system.cpu.itb_walker_cache.overall_hits::total 23594 # number of overall hits
1042 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 17581 # number of ReadReq misses
1043 system.cpu.itb_walker_cache.ReadReq_misses::total 17581 # number of ReadReq misses
1044 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 17581 # number of demand (read+write) misses
1045 system.cpu.itb_walker_cache.demand_misses::total 17581 # number of demand (read+write) misses
1046 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 17581 # number of overall misses
1047 system.cpu.itb_walker_cache.overall_misses::total 17581 # number of overall misses
1048 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 194939990 # number of ReadReq miss cycles
1049 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 194939990 # number of ReadReq miss cycles
1050 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 194939990 # number of demand (read+write) miss cycles
1051 system.cpu.itb_walker_cache.demand_miss_latency::total 194939990 # number of demand (read+write) miss cycles
1052 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 194939990 # number of overall miss cycles
1053 system.cpu.itb_walker_cache.overall_miss_latency::total 194939990 # number of overall miss cycles
1054 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41173 # number of ReadReq accesses(hits+misses)
1055 system.cpu.itb_walker_cache.ReadReq_accesses::total 41173 # number of ReadReq accesses(hits+misses)
1056 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1057 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1058 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41175 # number of demand (read+write) accesses
1059 system.cpu.itb_walker_cache.demand_accesses::total 41175 # number of demand (read+write) accesses
1060 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41175 # number of overall (read+write) accesses
1061 system.cpu.itb_walker_cache.overall_accesses::total 41175 # number of overall (read+write) accesses
1062 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.427003 # miss rate for ReadReq accesses
1063 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.427003 # miss rate for ReadReq accesses
1064 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.426982 # miss rate for demand accesses
1065 system.cpu.itb_walker_cache.demand_miss_rate::total 0.426982 # miss rate for demand accesses
1066 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.426982 # miss rate for overall accesses
1067 system.cpu.itb_walker_cache.overall_miss_rate::total 0.426982 # miss rate for overall accesses
1068 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910 # average ReadReq miss latency
1069 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910 # average ReadReq miss latency
1070 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency
1071 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910 # average overall miss latency
1072 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency
1073 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910 # average overall miss latency
1074 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1075 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1076 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1077 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1078 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1079 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1080 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1081 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1082 system.cpu.itb_walker_cache.writebacks::writebacks 3261 # number of writebacks
1083 system.cpu.itb_walker_cache.writebacks::total 3261 # number of writebacks
1084 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 17581 # number of ReadReq MSHR misses
1085 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 17581 # number of ReadReq MSHR misses
1086 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 17581 # number of demand (read+write) MSHR misses
1087 system.cpu.itb_walker_cache.demand_mshr_misses::total 17581 # number of demand (read+write) MSHR misses
1088 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 17581 # number of overall MSHR misses
1089 system.cpu.itb_walker_cache.overall_mshr_misses::total 17581 # number of overall MSHR misses
1090 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159752038 # number of ReadReq MSHR miss cycles
1091 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159752038 # number of ReadReq MSHR miss cycles
1092 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159752038 # number of demand (read+write) MSHR miss cycles
1093 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159752038 # number of demand (read+write) MSHR miss cycles
1094 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159752038 # number of overall MSHR miss cycles
1095 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159752038 # number of overall MSHR miss cycles
1096 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.427003 # mshr miss rate for ReadReq accesses
1097 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.427003 # mshr miss rate for ReadReq accesses
1098 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for demand accesses
1099 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.426982 # mshr miss rate for demand accesses
1100 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for overall accesses
1101 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.426982 # mshr miss rate for overall accesses
1102 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average ReadReq mshr miss latency
1103 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9086.629771 # average ReadReq mshr miss latency
1104 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency
1105 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency
1106 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency
1107 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency
1108 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1109 system.cpu.dtb_walker_cache.tags.replacements 76771 # number of replacements
1110 system.cpu.dtb_walker_cache.tags.tagsinuse 15.789364 # Cycle average of tags in use
1111 system.cpu.dtb_walker_cache.tags.total_refs 114792 # Total number of references to valid blocks.
1112 system.cpu.dtb_walker_cache.tags.sampled_refs 76787 # Sample count of references to valid blocks.
1113 system.cpu.dtb_walker_cache.tags.avg_refs 1.494941 # Average number of references to valid blocks.
1114 system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000 # Cycle when the warmup percentage was hit.
1115 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.789364 # Average occupied blocks per requestor
1116 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986835 # Average percentage of cache occupancy
1117 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986835 # Average percentage of cache occupancy
1118 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
1119 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1120 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
1121 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
1122 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1123 system.cpu.dtb_walker_cache.tags.tag_accesses 463158 # Number of tag accesses
1124 system.cpu.dtb_walker_cache.tags.data_accesses 463158 # Number of data accesses
1125 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114792 # number of ReadReq hits
1126 system.cpu.dtb_walker_cache.ReadReq_hits::total 114792 # number of ReadReq hits
1127 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114792 # number of demand (read+write) hits
1128 system.cpu.dtb_walker_cache.demand_hits::total 114792 # number of demand (read+write) hits
1129 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114792 # number of overall hits
1130 system.cpu.dtb_walker_cache.overall_hits::total 114792 # number of overall hits
1131 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77858 # number of ReadReq misses
1132 system.cpu.dtb_walker_cache.ReadReq_misses::total 77858 # number of ReadReq misses
1133 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77858 # number of demand (read+write) misses
1134 system.cpu.dtb_walker_cache.demand_misses::total 77858 # number of demand (read+write) misses
1135 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77858 # number of overall misses
1136 system.cpu.dtb_walker_cache.overall_misses::total 77858 # number of overall misses
1137 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 943768714 # number of ReadReq miss cycles
1138 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 943768714 # number of ReadReq miss cycles
1139 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 943768714 # number of demand (read+write) miss cycles
1140 system.cpu.dtb_walker_cache.demand_miss_latency::total 943768714 # number of demand (read+write) miss cycles
1141 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 943768714 # number of overall miss cycles
1142 system.cpu.dtb_walker_cache.overall_miss_latency::total 943768714 # number of overall miss cycles
1143 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192650 # number of ReadReq accesses(hits+misses)
1144 system.cpu.dtb_walker_cache.ReadReq_accesses::total 192650 # number of ReadReq accesses(hits+misses)
1145 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192650 # number of demand (read+write) accesses
1146 system.cpu.dtb_walker_cache.demand_accesses::total 192650 # number of demand (read+write) accesses
1147 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192650 # number of overall (read+write) accesses
1148 system.cpu.dtb_walker_cache.overall_accesses::total 192650 # number of overall (read+write) accesses
1149 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404142 # miss rate for ReadReq accesses
1150 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404142 # miss rate for ReadReq accesses
1151 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404142 # miss rate for demand accesses
1152 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404142 # miss rate for demand accesses
1153 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404142 # miss rate for overall accesses
1154 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404142 # miss rate for overall accesses
1155 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547 # average ReadReq miss latency
1156 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547 # average ReadReq miss latency
1157 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency
1158 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547 # average overall miss latency
1159 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency
1160 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547 # average overall miss latency
1161 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1162 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1163 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1164 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1165 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1166 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1167 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1168 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1169 system.cpu.dtb_walker_cache.writebacks::writebacks 21599 # number of writebacks
1170 system.cpu.dtb_walker_cache.writebacks::total 21599 # number of writebacks
1171 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77858 # number of ReadReq MSHR misses
1172 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77858 # number of ReadReq MSHR misses
1173 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77858 # number of demand (read+write) MSHR misses
1174 system.cpu.dtb_walker_cache.demand_mshr_misses::total 77858 # number of demand (read+write) MSHR misses
1175 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77858 # number of overall MSHR misses
1176 system.cpu.dtb_walker_cache.overall_mshr_misses::total 77858 # number of overall MSHR misses
1177 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 787936434 # number of ReadReq MSHR miss cycles
1178 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 787936434 # number of ReadReq MSHR miss cycles
1179 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 787936434 # number of demand (read+write) MSHR miss cycles
1180 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 787936434 # number of demand (read+write) MSHR miss cycles
1181 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 787936434 # number of overall MSHR miss cycles
1182 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 787936434 # number of overall MSHR miss cycles
1183 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for ReadReq accesses
1184 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404142 # mshr miss rate for ReadReq accesses
1185 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for demand accesses
1186 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404142 # mshr miss rate for demand accesses
1187 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for overall accesses
1188 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404142 # mshr miss rate for overall accesses
1189 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average ReadReq mshr miss latency
1190 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059 # average ReadReq mshr miss latency
1191 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency
1192 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency
1193 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency
1194 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency
1195 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1196 system.cpu.dcache.tags.replacements 1661725 # number of replacements
1197 system.cpu.dcache.tags.tagsinuse 511.996415 # Cycle average of tags in use
1198 system.cpu.dcache.tags.total_refs 19139703 # Total number of references to valid blocks.
1199 system.cpu.dcache.tags.sampled_refs 1662237 # Sample count of references to valid blocks.
1200 system.cpu.dcache.tags.avg_refs 11.514425 # Average number of references to valid blocks.
1201 system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
1202 system.cpu.dcache.tags.occ_blocks::cpu.data 511.996415 # Average occupied blocks per requestor
1203 system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
1204 system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
1205 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1206 system.cpu.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
1207 system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
1208 system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
1209 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1210 system.cpu.dcache.tags.tag_accesses 88377305 # Number of tag accesses
1211 system.cpu.dcache.tags.data_accesses 88377305 # Number of data accesses
1212 system.cpu.dcache.ReadReq_hits::cpu.data 10986051 # number of ReadReq hits
1213 system.cpu.dcache.ReadReq_hits::total 10986051 # number of ReadReq hits
1214 system.cpu.dcache.WriteReq_hits::cpu.data 8085611 # number of WriteReq hits
1215 system.cpu.dcache.WriteReq_hits::total 8085611 # number of WriteReq hits
1216 system.cpu.dcache.SoftPFReq_hits::cpu.data 65242 # number of SoftPFReq hits
1217 system.cpu.dcache.SoftPFReq_hits::total 65242 # number of SoftPFReq hits
1218 system.cpu.dcache.demand_hits::cpu.data 19071662 # number of demand (read+write) hits
1219 system.cpu.dcache.demand_hits::total 19071662 # number of demand (read+write) hits
1220 system.cpu.dcache.overall_hits::cpu.data 19136904 # number of overall hits
1221 system.cpu.dcache.overall_hits::total 19136904 # number of overall hits
1222 system.cpu.dcache.ReadReq_misses::cpu.data 1801162 # number of ReadReq misses
1223 system.cpu.dcache.ReadReq_misses::total 1801162 # number of ReadReq misses
1224 system.cpu.dcache.WriteReq_misses::cpu.data 334073 # number of WriteReq misses
1225 system.cpu.dcache.WriteReq_misses::total 334073 # number of WriteReq misses
1226 system.cpu.dcache.SoftPFReq_misses::cpu.data 406623 # number of SoftPFReq misses
1227 system.cpu.dcache.SoftPFReq_misses::total 406623 # number of SoftPFReq misses
1228 system.cpu.dcache.demand_misses::cpu.data 2135235 # number of demand (read+write) misses
1229 system.cpu.dcache.demand_misses::total 2135235 # number of demand (read+write) misses
1230 system.cpu.dcache.overall_misses::cpu.data 2541858 # number of overall misses
1231 system.cpu.dcache.overall_misses::total 2541858 # number of overall misses
1232 system.cpu.dcache.ReadReq_miss_latency::cpu.data 26563616547 # number of ReadReq miss cycles
1233 system.cpu.dcache.ReadReq_miss_latency::total 26563616547 # number of ReadReq miss cycles
1234 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12873735113 # number of WriteReq miss cycles
1235 system.cpu.dcache.WriteReq_miss_latency::total 12873735113 # number of WriteReq miss cycles
1236 system.cpu.dcache.demand_miss_latency::cpu.data 39437351660 # number of demand (read+write) miss cycles
1237 system.cpu.dcache.demand_miss_latency::total 39437351660 # number of demand (read+write) miss cycles
1238 system.cpu.dcache.overall_miss_latency::cpu.data 39437351660 # number of overall miss cycles
1239 system.cpu.dcache.overall_miss_latency::total 39437351660 # number of overall miss cycles
1240 system.cpu.dcache.ReadReq_accesses::cpu.data 12787213 # number of ReadReq accesses(hits+misses)
1241 system.cpu.dcache.ReadReq_accesses::total 12787213 # number of ReadReq accesses(hits+misses)
1242 system.cpu.dcache.WriteReq_accesses::cpu.data 8419684 # number of WriteReq accesses(hits+misses)
1243 system.cpu.dcache.WriteReq_accesses::total 8419684 # number of WriteReq accesses(hits+misses)
1244 system.cpu.dcache.SoftPFReq_accesses::cpu.data 471865 # number of SoftPFReq accesses(hits+misses)
1245 system.cpu.dcache.SoftPFReq_accesses::total 471865 # number of SoftPFReq accesses(hits+misses)
1246 system.cpu.dcache.demand_accesses::cpu.data 21206897 # number of demand (read+write) accesses
1247 system.cpu.dcache.demand_accesses::total 21206897 # number of demand (read+write) accesses
1248 system.cpu.dcache.overall_accesses::cpu.data 21678762 # number of overall (read+write) accesses
1249 system.cpu.dcache.overall_accesses::total 21678762 # number of overall (read+write) accesses
1250 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140856 # miss rate for ReadReq accesses
1251 system.cpu.dcache.ReadReq_miss_rate::total 0.140856 # miss rate for ReadReq accesses
1252 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039678 # miss rate for WriteReq accesses
1253 system.cpu.dcache.WriteReq_miss_rate::total 0.039678 # miss rate for WriteReq accesses
1254 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.861736 # miss rate for SoftPFReq accesses
1255 system.cpu.dcache.SoftPFReq_miss_rate::total 0.861736 # miss rate for SoftPFReq accesses
1256 system.cpu.dcache.demand_miss_rate::cpu.data 0.100686 # miss rate for demand accesses
1257 system.cpu.dcache.demand_miss_rate::total 0.100686 # miss rate for demand accesses
1258 system.cpu.dcache.overall_miss_rate::cpu.data 0.117251 # miss rate for overall accesses
1259 system.cpu.dcache.overall_miss_rate::total 0.117251 # miss rate for overall accesses
1260 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14748.044067 # average ReadReq miss latency
1261 system.cpu.dcache.ReadReq_avg_miss_latency::total 14748.044067 # average ReadReq miss latency
1262 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38535.694633 # average WriteReq miss latency
1263 system.cpu.dcache.WriteReq_avg_miss_latency::total 38535.694633 # average WriteReq miss latency
1264 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18469.794500 # average overall miss latency
1265 system.cpu.dcache.demand_avg_miss_latency::total 18469.794500 # average overall miss latency
1266 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15515.167118 # average overall miss latency
1267 system.cpu.dcache.overall_avg_miss_latency::total 15515.167118 # average overall miss latency
1268 system.cpu.dcache.blocked_cycles::no_mshrs 377678 # number of cycles access was blocked
1269 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1270 system.cpu.dcache.blocked::no_mshrs 40377 # number of cycles access was blocked
1271 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1272 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353791 # average number of cycles each access was blocked
1273 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1274 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1275 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1276 system.cpu.dcache.writebacks::writebacks 1562629 # number of writebacks
1277 system.cpu.dcache.writebacks::total 1562629 # number of writebacks
1278 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829779 # number of ReadReq MSHR hits
1279 system.cpu.dcache.ReadReq_mshr_hits::total 829779 # number of ReadReq MSHR hits
1280 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44137 # number of WriteReq MSHR hits
1281 system.cpu.dcache.WriteReq_mshr_hits::total 44137 # number of WriteReq MSHR hits
1282 system.cpu.dcache.demand_mshr_hits::cpu.data 873916 # number of demand (read+write) MSHR hits
1283 system.cpu.dcache.demand_mshr_hits::total 873916 # number of demand (read+write) MSHR hits
1284 system.cpu.dcache.overall_mshr_hits::cpu.data 873916 # number of overall MSHR hits
1285 system.cpu.dcache.overall_mshr_hits::total 873916 # number of overall MSHR hits
1286 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971383 # number of ReadReq MSHR misses
1287 system.cpu.dcache.ReadReq_mshr_misses::total 971383 # number of ReadReq MSHR misses
1288 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289936 # number of WriteReq MSHR misses
1289 system.cpu.dcache.WriteReq_mshr_misses::total 289936 # number of WriteReq MSHR misses
1290 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403164 # number of SoftPFReq MSHR misses
1291 system.cpu.dcache.SoftPFReq_mshr_misses::total 403164 # number of SoftPFReq MSHR misses
1292 system.cpu.dcache.demand_mshr_misses::cpu.data 1261319 # number of demand (read+write) MSHR misses
1293 system.cpu.dcache.demand_mshr_misses::total 1261319 # number of demand (read+write) MSHR misses
1294 system.cpu.dcache.overall_mshr_misses::cpu.data 1664483 # number of overall MSHR misses
1295 system.cpu.dcache.overall_mshr_misses::total 1664483 # number of overall MSHR misses
1296 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264764518 # number of ReadReq MSHR miss cycles
1297 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264764518 # number of ReadReq MSHR miss cycles
1298 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11214941849 # number of WriteReq MSHR miss cycles
1299 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11214941849 # number of WriteReq MSHR miss cycles
1300 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5603688502 # number of SoftPFReq MSHR miss cycles
1301 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5603688502 # number of SoftPFReq MSHR miss cycles
1302 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23479706367 # number of demand (read+write) MSHR miss cycles
1303 system.cpu.dcache.demand_mshr_miss_latency::total 23479706367 # number of demand (read+write) MSHR miss cycles
1304 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29083394869 # number of overall MSHR miss cycles
1305 system.cpu.dcache.overall_mshr_miss_latency::total 29083394869 # number of overall MSHR miss cycles
1306 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364659500 # number of ReadReq MSHR uncacheable cycles
1307 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364659500 # number of ReadReq MSHR uncacheable cycles
1308 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538935000 # number of WriteReq MSHR uncacheable cycles
1309 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538935000 # number of WriteReq MSHR uncacheable cycles
1310 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903594500 # number of overall MSHR uncacheable cycles
1311 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903594500 # number of overall MSHR uncacheable cycles
1312 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075965 # mshr miss rate for ReadReq accesses
1313 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075965 # mshr miss rate for ReadReq accesses
1314 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034435 # mshr miss rate for WriteReq accesses
1315 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034435 # mshr miss rate for WriteReq accesses
1316 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854405 # mshr miss rate for SoftPFReq accesses
1317 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854405 # mshr miss rate for SoftPFReq accesses
1318 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059477 # mshr miss rate for demand accesses
1319 system.cpu.dcache.demand_mshr_miss_rate::total 0.059477 # mshr miss rate for demand accesses
1320 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076779 # mshr miss rate for overall accesses
1321 system.cpu.dcache.overall_mshr_miss_rate::total 0.076779 # mshr miss rate for overall accesses
1322 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12626.085198 # average ReadReq mshr miss latency
1323 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12626.085198 # average ReadReq mshr miss latency
1324 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38680.749714 # average WriteReq mshr miss latency
1325 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38680.749714 # average WriteReq mshr miss latency
1326 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966 # average SoftPFReq mshr miss latency
1327 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966 # average SoftPFReq mshr miss latency
1328 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728 # average overall mshr miss latency
1329 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728 # average overall mshr miss latency
1330 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954 # average overall mshr miss latency
1331 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954 # average overall mshr miss latency
1332 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1333 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1334 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1335 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1336 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1337 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1338 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1339 system.cpu.l2cache.tags.replacements 112646 # number of replacements
1340 system.cpu.l2cache.tags.tagsinuse 64814.554294 # Cycle average of tags in use
1341 system.cpu.l2cache.tags.total_refs 3852282 # Total number of references to valid blocks.
1342 system.cpu.l2cache.tags.sampled_refs 176740 # Sample count of references to valid blocks.
1343 system.cpu.l2cache.tags.avg_refs 21.796322 # Average number of references to valid blocks.
1344 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1345 system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869 # Average occupied blocks per requestor
1346 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.791697 # Average occupied blocks per requestor
1347 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140401 # Average occupied blocks per requestor
1348 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3275.059967 # Average occupied blocks per requestor
1349 system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359 # Average occupied blocks per requestor
1350 system.cpu.l2cache.tags.occ_percent::writebacks 0.768329 # Average percentage of cache occupancy
1351 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000241 # Average percentage of cache occupancy
1352 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1353 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049973 # Average percentage of cache occupancy
1354 system.cpu.l2cache.tags.occ_percent::cpu.data 0.170446 # Average percentage of cache occupancy
1355 system.cpu.l2cache.tags.occ_percent::total 0.988992 # Average percentage of cache occupancy
1356 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64094 # Occupied blocks per task id
1357 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
1358 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
1359 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3429 # Occupied blocks per task id
1360 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5695 # Occupied blocks per task id
1361 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54337 # Occupied blocks per task id
1362 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977997 # Percentage of cache occupancy per task id
1363 system.cpu.l2cache.tags.tag_accesses 35174951 # Number of tag accesses
1364 system.cpu.l2cache.tags.data_accesses 35174951 # Number of data accesses
1365 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69400 # number of ReadReq hits
1366 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13641 # number of ReadReq hits
1367 system.cpu.l2cache.ReadReq_hits::cpu.inst 987138 # number of ReadReq hits
1368 system.cpu.l2cache.ReadReq_hits::cpu.data 1338009 # number of ReadReq hits
1369 system.cpu.l2cache.ReadReq_hits::total 2408188 # number of ReadReq hits
1370 system.cpu.l2cache.Writeback_hits::writebacks 1587489 # number of Writeback hits
1371 system.cpu.l2cache.Writeback_hits::total 1587489 # number of Writeback hits
1372 system.cpu.l2cache.UpgradeReq_hits::cpu.data 311 # number of UpgradeReq hits
1373 system.cpu.l2cache.UpgradeReq_hits::total 311 # number of UpgradeReq hits
1374 system.cpu.l2cache.ReadExReq_hits::cpu.data 154123 # number of ReadExReq hits
1375 system.cpu.l2cache.ReadExReq_hits::total 154123 # number of ReadExReq hits
1376 system.cpu.l2cache.demand_hits::cpu.dtb.walker 69400 # number of demand (read+write) hits
1377 system.cpu.l2cache.demand_hits::cpu.itb.walker 13641 # number of demand (read+write) hits
1378 system.cpu.l2cache.demand_hits::cpu.inst 987138 # number of demand (read+write) hits
1379 system.cpu.l2cache.demand_hits::cpu.data 1492132 # number of demand (read+write) hits
1380 system.cpu.l2cache.demand_hits::total 2562311 # number of demand (read+write) hits
1381 system.cpu.l2cache.overall_hits::cpu.dtb.walker 69400 # number of overall hits
1382 system.cpu.l2cache.overall_hits::cpu.itb.walker 13641 # number of overall hits
1383 system.cpu.l2cache.overall_hits::cpu.inst 987138 # number of overall hits
1384 system.cpu.l2cache.overall_hits::cpu.data 1492132 # number of overall hits
1385 system.cpu.l2cache.overall_hits::total 2562311 # number of overall hits
1386 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 64 # number of ReadReq misses
1387 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
1388 system.cpu.l2cache.ReadReq_misses::cpu.inst 16384 # number of ReadReq misses
1389 system.cpu.l2cache.ReadReq_misses::cpu.data 35861 # number of ReadReq misses
1390 system.cpu.l2cache.ReadReq_misses::total 52315 # number of ReadReq misses
1391 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1456 # number of UpgradeReq misses
1392 system.cpu.l2cache.UpgradeReq_misses::total 1456 # number of UpgradeReq misses
1393 system.cpu.l2cache.ReadExReq_misses::cpu.data 133693 # number of ReadExReq misses
1394 system.cpu.l2cache.ReadExReq_misses::total 133693 # number of ReadExReq misses
1395 system.cpu.l2cache.demand_misses::cpu.dtb.walker 64 # number of demand (read+write) misses
1396 system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
1397 system.cpu.l2cache.demand_misses::cpu.inst 16384 # number of demand (read+write) misses
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1400 system.cpu.l2cache.overall_misses::cpu.dtb.walker 64 # number of overall misses
1401 system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
1402 system.cpu.l2cache.overall_misses::cpu.inst 16384 # number of overall misses
1403 system.cpu.l2cache.overall_misses::cpu.data 169554 # number of overall misses
1404 system.cpu.l2cache.overall_misses::total 186008 # number of overall misses
1405 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5398250 # number of ReadReq miss cycles
1406 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467000 # number of ReadReq miss cycles
1407 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1244423000 # number of ReadReq miss cycles
1408 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2844994996 # number of ReadReq miss cycles
1409 system.cpu.l2cache.ReadReq_miss_latency::total 4095283246 # number of ReadReq miss cycles
1410 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17419754 # number of UpgradeReq miss cycles
1411 system.cpu.l2cache.UpgradeReq_miss_latency::total 17419754 # number of UpgradeReq miss cycles
1412 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9341540216 # number of ReadExReq miss cycles
1413 system.cpu.l2cache.ReadExReq_miss_latency::total 9341540216 # number of ReadExReq miss cycles
1414 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5398250 # number of demand (read+write) miss cycles
1415 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467000 # number of demand (read+write) miss cycles
1416 system.cpu.l2cache.demand_miss_latency::cpu.inst 1244423000 # number of demand (read+write) miss cycles
1417 system.cpu.l2cache.demand_miss_latency::cpu.data 12186535212 # number of demand (read+write) miss cycles
1418 system.cpu.l2cache.demand_miss_latency::total 13436823462 # number of demand (read+write) miss cycles
1419 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5398250 # number of overall miss cycles
1420 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467000 # number of overall miss cycles
1421 system.cpu.l2cache.overall_miss_latency::cpu.inst 1244423000 # number of overall miss cycles
1422 system.cpu.l2cache.overall_miss_latency::cpu.data 12186535212 # number of overall miss cycles
1423 system.cpu.l2cache.overall_miss_latency::total 13436823462 # number of overall miss cycles
1424 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69464 # number of ReadReq accesses(hits+misses)
1425 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13647 # number of ReadReq accesses(hits+misses)
1426 system.cpu.l2cache.ReadReq_accesses::cpu.inst 1003522 # number of ReadReq accesses(hits+misses)
1427 system.cpu.l2cache.ReadReq_accesses::cpu.data 1373870 # number of ReadReq accesses(hits+misses)
1428 system.cpu.l2cache.ReadReq_accesses::total 2460503 # number of ReadReq accesses(hits+misses)
1429 system.cpu.l2cache.Writeback_accesses::writebacks 1587489 # number of Writeback accesses(hits+misses)
1430 system.cpu.l2cache.Writeback_accesses::total 1587489 # number of Writeback accesses(hits+misses)
1431 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1767 # number of UpgradeReq accesses(hits+misses)
1432 system.cpu.l2cache.UpgradeReq_accesses::total 1767 # number of UpgradeReq accesses(hits+misses)
1433 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287816 # number of ReadExReq accesses(hits+misses)
1434 system.cpu.l2cache.ReadExReq_accesses::total 287816 # number of ReadExReq accesses(hits+misses)
1435 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69464 # number of demand (read+write) accesses
1436 system.cpu.l2cache.demand_accesses::cpu.itb.walker 13647 # number of demand (read+write) accesses
1437 system.cpu.l2cache.demand_accesses::cpu.inst 1003522 # number of demand (read+write) accesses
1438 system.cpu.l2cache.demand_accesses::cpu.data 1661686 # number of demand (read+write) accesses
1439 system.cpu.l2cache.demand_accesses::total 2748319 # number of demand (read+write) accesses
1440 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69464 # number of overall (read+write) accesses
1441 system.cpu.l2cache.overall_accesses::cpu.itb.walker 13647 # number of overall (read+write) accesses
1442 system.cpu.l2cache.overall_accesses::cpu.inst 1003522 # number of overall (read+write) accesses
1443 system.cpu.l2cache.overall_accesses::cpu.data 1661686 # number of overall (read+write) accesses
1444 system.cpu.l2cache.overall_accesses::total 2748319 # number of overall (read+write) accesses
1445 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
1446 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000440 # miss rate for ReadReq accesses
1447 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016326 # miss rate for ReadReq accesses
1448 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026102 # miss rate for ReadReq accesses
1449 system.cpu.l2cache.ReadReq_miss_rate::total 0.021262 # miss rate for ReadReq accesses
1450 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823995 # miss rate for UpgradeReq accesses
1451 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823995 # miss rate for UpgradeReq accesses
1452 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464509 # miss rate for ReadExReq accesses
1453 system.cpu.l2cache.ReadExReq_miss_rate::total 0.464509 # miss rate for ReadExReq accesses
1454 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
1455 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000440 # miss rate for demand accesses
1456 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016326 # miss rate for demand accesses
1457 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102037 # miss rate for demand accesses
1458 system.cpu.l2cache.demand_miss_rate::total 0.067681 # miss rate for demand accesses
1459 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
1460 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000440 # miss rate for overall accesses
1461 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016326 # miss rate for overall accesses
1462 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102037 # miss rate for overall accesses
1463 system.cpu.l2cache.overall_miss_rate::total 0.067681 # miss rate for overall accesses
1464 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84347.656250 # average ReadReq miss latency
1465 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77833.333333 # average ReadReq miss latency
1466 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75953.552246 # average ReadReq miss latency
1467 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79333.955997 # average ReadReq miss latency
1468 system.cpu.l2cache.ReadReq_avg_miss_latency::total 78281.243353 # average ReadReq miss latency
1469 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11964.116758 # average UpgradeReq miss latency
1470 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11964.116758 # average UpgradeReq miss latency
1471 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69873.069016 # average ReadExReq miss latency
1472 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69873.069016 # average ReadExReq miss latency
1473 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency
1474 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency
1475 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency
1476 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency
1477 system.cpu.l2cache.demand_avg_miss_latency::total 72237.879349 # average overall miss latency
1478 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84347.656250 # average overall miss latency
1479 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77833.333333 # average overall miss latency
1480 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75953.552246 # average overall miss latency
1481 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71874.064970 # average overall miss latency
1482 system.cpu.l2cache.overall_avg_miss_latency::total 72237.879349 # average overall miss latency
1483 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1484 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1485 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1486 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1487 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1488 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1489 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1490 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1491 system.cpu.l2cache.writebacks::writebacks 103082 # number of writebacks
1492 system.cpu.l2cache.writebacks::total 103082 # number of writebacks
1493 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
1494 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1495 system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
1496 system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
1497 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1498 system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
1499 system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
1500 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1501 system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
1502 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 64 # number of ReadReq MSHR misses
1503 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
1504 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16378 # number of ReadReq MSHR misses
1505 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35860 # number of ReadReq MSHR misses
1506 system.cpu.l2cache.ReadReq_mshr_misses::total 52308 # number of ReadReq MSHR misses
1507 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1456 # number of UpgradeReq MSHR misses
1508 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1456 # number of UpgradeReq MSHR misses
1509 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133693 # number of ReadExReq MSHR misses
1510 system.cpu.l2cache.ReadExReq_mshr_misses::total 133693 # number of ReadExReq MSHR misses
1511 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 64 # number of demand (read+write) MSHR misses
1512 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
1513 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16378 # number of demand (read+write) MSHR misses
1514 system.cpu.l2cache.demand_mshr_misses::cpu.data 169553 # number of demand (read+write) MSHR misses
1515 system.cpu.l2cache.demand_mshr_misses::total 186001 # number of demand (read+write) MSHR misses
1516 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 64 # number of overall MSHR misses
1517 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
1518 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16378 # number of overall MSHR misses
1519 system.cpu.l2cache.overall_mshr_misses::cpu.data 169553 # number of overall MSHR misses
1520 system.cpu.l2cache.overall_mshr_misses::total 186001 # number of overall MSHR misses
1521 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4610750 # number of ReadReq MSHR miss cycles
1522 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles
1523 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1038765000 # number of ReadReq MSHR miss cycles
1524 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2399725996 # number of ReadReq MSHR miss cycles
1525 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3443493246 # number of ReadReq MSHR miss cycles
1526 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14596954 # number of UpgradeReq MSHR miss cycles
1527 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14596954 # number of UpgradeReq MSHR miss cycles
1528 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7662739284 # number of ReadExReq MSHR miss cycles
1529 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7662739284 # number of ReadExReq MSHR miss cycles
1530 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4610750 # number of demand (read+write) MSHR miss cycles
1531 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles
1532 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1038765000 # number of demand (read+write) MSHR miss cycles
1533 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10062465280 # number of demand (read+write) MSHR miss cycles
1534 system.cpu.l2cache.demand_mshr_miss_latency::total 11106232530 # number of demand (read+write) MSHR miss cycles
1535 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4610750 # number of overall MSHR miss cycles
1536 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles
1537 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1038765000 # number of overall MSHR miss cycles
1538 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10062465280 # number of overall MSHR miss cycles
1539 system.cpu.l2cache.overall_mshr_miss_latency::total 11106232530 # number of overall MSHR miss cycles
1540 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251418000 # number of ReadReq MSHR uncacheable cycles
1541 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251418000 # number of ReadReq MSHR uncacheable cycles
1542 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373087500 # number of WriteReq MSHR uncacheable cycles
1543 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373087500 # number of WriteReq MSHR uncacheable cycles
1544 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624505500 # number of overall MSHR uncacheable cycles
1545 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624505500 # number of overall MSHR uncacheable cycles
1546 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for ReadReq accesses
1547 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for ReadReq accesses
1548 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for ReadReq accesses
1549 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026101 # mshr miss rate for ReadReq accesses
1550 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses
1551 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses
1552 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses
1553 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses
1554 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses
1555 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses
1556 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses
1557 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses
1558 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses
1559 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses
1560 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses
1561 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses
1562 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses
1563 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses
1564 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses
1565 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency
1566 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
1567 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency
1568 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency
1569 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency
1570 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency
1571 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency
1572 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency
1573 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency
1574 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
1575 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
1576 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
1577 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
1578 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
1579 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency
1580 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
1581 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency
1582 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency
1583 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency
1584 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1585 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1586 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1587 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1588 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1589 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1590 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1591 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1592 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1594 ---------- End Simulation Statistics ----------
projects / gem5.git / blob