2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.155288 # Number of seconds simulated
4 sim_ticks 5155288336500 # Number of ticks simulated
5 final_tick 5155288336500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 187724 # Simulator instruction rate (inst/s)
8 host_op_rate 369929 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2268413480 # Simulator tick rate (ticks/s)
10 host_mem_usage 362380 # Number of bytes of host memory used
11 host_seconds 2272.64 # Real time elapsed on the host
12 sim_insts 426629675 # Number of instructions simulated
13 sim_ops 840716593 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read 15943680 # Number of bytes read from this memory
15 system.physmem.bytes_inst_read 1259264 # Number of instructions bytes read from this memory
16 system.physmem.bytes_written 12043648 # Number of bytes written to this memory
17 system.physmem.num_reads 249120 # Number of read requests responded to by this memory
18 system.physmem.num_writes 188182 # Number of write requests responded to by this memory
19 system.physmem.num_other 0 # Number of other requests responded to by this memory
20 system.physmem.bw_read 3092684 # Total read bandwidth from this memory (bytes/s)
21 system.physmem.bw_inst_read 244266 # Instruction read bandwidth from this memory (bytes/s)
22 system.physmem.bw_write 2336174 # Write bandwidth from this memory (bytes/s)
23 system.physmem.bw_total 5428858 # Total bandwidth to/from this memory (bytes/s)
24 system.l2c.replacements 167456 # number of replacements
25 system.l2c.tagsinuse 37822.927931 # Cycle average of tags in use
26 system.l2c.total_refs 3846980 # Total number of references to valid blocks.
27 system.l2c.sampled_refs 202165 # Sample count of references to valid blocks.
28 system.l2c.avg_refs 19.028912 # Average number of references to valid blocks.
29 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
30 system.l2c.occ_blocks::writebacks 26706.608582 # Average occupied blocks per requestor
31 system.l2c.occ_blocks::cpu.dtb.walker 11.179185 # Average occupied blocks per requestor
32 system.l2c.occ_blocks::cpu.itb.walker 0.034739 # Average occupied blocks per requestor
33 system.l2c.occ_blocks::cpu.inst 2430.963092 # Average occupied blocks per requestor
34 system.l2c.occ_blocks::cpu.data 8674.142332 # Average occupied blocks per requestor
35 system.l2c.occ_percent::writebacks 0.407511 # Average percentage of cache occupancy
36 system.l2c.occ_percent::cpu.dtb.walker 0.000171 # Average percentage of cache occupancy
37 system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
38 system.l2c.occ_percent::cpu.inst 0.037094 # Average percentage of cache occupancy
39 system.l2c.occ_percent::cpu.data 0.132357 # Average percentage of cache occupancy
40 system.l2c.occ_percent::total 0.577132 # Average percentage of cache occupancy
41 system.l2c.ReadReq_hits::cpu.dtb.walker 117941 # number of ReadReq hits
42 system.l2c.ReadReq_hits::cpu.itb.walker 9215 # number of ReadReq hits
43 system.l2c.ReadReq_hits::cpu.inst 1064505 # number of ReadReq hits
44 system.l2c.ReadReq_hits::cpu.data 1335031 # number of ReadReq hits
45 system.l2c.ReadReq_hits::total 2526692 # number of ReadReq hits
46 system.l2c.Writeback_hits::writebacks 1602581 # number of Writeback hits
47 system.l2c.Writeback_hits::total 1602581 # number of Writeback hits
48 system.l2c.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits
49 system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits
50 system.l2c.ReadExReq_hits::cpu.data 151453 # number of ReadExReq hits
51 system.l2c.ReadExReq_hits::total 151453 # number of ReadExReq hits
52 system.l2c.demand_hits::cpu.dtb.walker 117941 # number of demand (read+write) hits
53 system.l2c.demand_hits::cpu.itb.walker 9215 # number of demand (read+write) hits
54 system.l2c.demand_hits::cpu.inst 1064505 # number of demand (read+write) hits
55 system.l2c.demand_hits::cpu.data 1486484 # number of demand (read+write) hits
56 system.l2c.demand_hits::total 2678145 # number of demand (read+write) hits
57 system.l2c.overall_hits::cpu.dtb.walker 117941 # number of overall hits
58 system.l2c.overall_hits::cpu.itb.walker 9215 # number of overall hits
59 system.l2c.overall_hits::cpu.inst 1064505 # number of overall hits
60 system.l2c.overall_hits::cpu.data 1486484 # number of overall hits
61 system.l2c.overall_hits::total 2678145 # number of overall hits
62 system.l2c.ReadReq_misses::cpu.dtb.walker 98 # number of ReadReq misses
63 system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
64 system.l2c.ReadReq_misses::cpu.inst 19677 # number of ReadReq misses
65 system.l2c.ReadReq_misses::cpu.data 45243 # number of ReadReq misses
66 system.l2c.ReadReq_misses::total 65025 # number of ReadReq misses
67 system.l2c.UpgradeReq_misses::cpu.data 2687 # number of UpgradeReq misses
68 system.l2c.UpgradeReq_misses::total 2687 # number of UpgradeReq misses
69 system.l2c.ReadExReq_misses::cpu.data 141494 # number of ReadExReq misses
70 system.l2c.ReadExReq_misses::total 141494 # number of ReadExReq misses
71 system.l2c.demand_misses::cpu.dtb.walker 98 # number of demand (read+write) misses
72 system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
73 system.l2c.demand_misses::cpu.inst 19677 # number of demand (read+write) misses
74 system.l2c.demand_misses::cpu.data 186737 # number of demand (read+write) misses
75 system.l2c.demand_misses::total 206519 # number of demand (read+write) misses
76 system.l2c.overall_misses::cpu.dtb.walker 98 # number of overall misses
77 system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses
78 system.l2c.overall_misses::cpu.inst 19677 # number of overall misses
79 system.l2c.overall_misses::cpu.data 186737 # number of overall misses
80 system.l2c.overall_misses::total 206519 # number of overall misses
81 system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5116000 # number of ReadReq miss cycles
82 system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles
83 system.l2c.ReadReq_miss_latency::cpu.inst 1028234500 # number of ReadReq miss cycles
84 system.l2c.ReadReq_miss_latency::cpu.data 2378237500 # number of ReadReq miss cycles
85 system.l2c.ReadReq_miss_latency::total 3411952000 # number of ReadReq miss cycles
86 system.l2c.UpgradeReq_miss_latency::cpu.data 39192000 # number of UpgradeReq miss cycles
87 system.l2c.UpgradeReq_miss_latency::total 39192000 # number of UpgradeReq miss cycles
88 system.l2c.ReadExReq_miss_latency::cpu.data 7368603000 # number of ReadExReq miss cycles
89 system.l2c.ReadExReq_miss_latency::total 7368603000 # number of ReadExReq miss cycles
90 system.l2c.demand_miss_latency::cpu.dtb.walker 5116000 # number of demand (read+write) miss cycles
91 system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles
92 system.l2c.demand_miss_latency::cpu.inst 1028234500 # number of demand (read+write) miss cycles
93 system.l2c.demand_miss_latency::cpu.data 9746840500 # number of demand (read+write) miss cycles
94 system.l2c.demand_miss_latency::total 10780555000 # number of demand (read+write) miss cycles
95 system.l2c.overall_miss_latency::cpu.dtb.walker 5116000 # number of overall miss cycles
96 system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles
97 system.l2c.overall_miss_latency::cpu.inst 1028234500 # number of overall miss cycles
98 system.l2c.overall_miss_latency::cpu.data 9746840500 # number of overall miss cycles
99 system.l2c.overall_miss_latency::total 10780555000 # number of overall miss cycles
100 system.l2c.ReadReq_accesses::cpu.dtb.walker 118039 # number of ReadReq accesses(hits+misses)
101 system.l2c.ReadReq_accesses::cpu.itb.walker 9222 # number of ReadReq accesses(hits+misses)
102 system.l2c.ReadReq_accesses::cpu.inst 1084182 # number of ReadReq accesses(hits+misses)
103 system.l2c.ReadReq_accesses::cpu.data 1380274 # number of ReadReq accesses(hits+misses)
104 system.l2c.ReadReq_accesses::total 2591717 # number of ReadReq accesses(hits+misses)
105 system.l2c.Writeback_accesses::writebacks 1602581 # number of Writeback accesses(hits+misses)
106 system.l2c.Writeback_accesses::total 1602581 # number of Writeback accesses(hits+misses)
107 system.l2c.UpgradeReq_accesses::cpu.data 3009 # number of UpgradeReq accesses(hits+misses)
108 system.l2c.UpgradeReq_accesses::total 3009 # number of UpgradeReq accesses(hits+misses)
109 system.l2c.ReadExReq_accesses::cpu.data 292947 # number of ReadExReq accesses(hits+misses)
110 system.l2c.ReadExReq_accesses::total 292947 # number of ReadExReq accesses(hits+misses)
111 system.l2c.demand_accesses::cpu.dtb.walker 118039 # number of demand (read+write) accesses
112 system.l2c.demand_accesses::cpu.itb.walker 9222 # number of demand (read+write) accesses
113 system.l2c.demand_accesses::cpu.inst 1084182 # number of demand (read+write) accesses
114 system.l2c.demand_accesses::cpu.data 1673221 # number of demand (read+write) accesses
115 system.l2c.demand_accesses::total 2884664 # number of demand (read+write) accesses
116 system.l2c.overall_accesses::cpu.dtb.walker 118039 # number of overall (read+write) accesses
117 system.l2c.overall_accesses::cpu.itb.walker 9222 # number of overall (read+write) accesses
118 system.l2c.overall_accesses::cpu.inst 1084182 # number of overall (read+write) accesses
119 system.l2c.overall_accesses::cpu.data 1673221 # number of overall (read+write) accesses
120 system.l2c.overall_accesses::total 2884664 # number of overall (read+write) accesses
121 system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000830 # miss rate for ReadReq accesses
122 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000759 # miss rate for ReadReq accesses
123 system.l2c.ReadReq_miss_rate::cpu.inst 0.018149 # miss rate for ReadReq accesses
124 system.l2c.ReadReq_miss_rate::cpu.data 0.032778 # miss rate for ReadReq accesses
125 system.l2c.UpgradeReq_miss_rate::cpu.data 0.892988 # miss rate for UpgradeReq accesses
126 system.l2c.ReadExReq_miss_rate::cpu.data 0.483002 # miss rate for ReadExReq accesses
127 system.l2c.demand_miss_rate::cpu.dtb.walker 0.000830 # miss rate for demand accesses
128 system.l2c.demand_miss_rate::cpu.itb.walker 0.000759 # miss rate for demand accesses
129 system.l2c.demand_miss_rate::cpu.inst 0.018149 # miss rate for demand accesses
130 system.l2c.demand_miss_rate::cpu.data 0.111603 # miss rate for demand accesses
131 system.l2c.overall_miss_rate::cpu.dtb.walker 0.000830 # miss rate for overall accesses
132 system.l2c.overall_miss_rate::cpu.itb.walker 0.000759 # miss rate for overall accesses
133 system.l2c.overall_miss_rate::cpu.inst 0.018149 # miss rate for overall accesses
134 system.l2c.overall_miss_rate::cpu.data 0.111603 # miss rate for overall accesses
135 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52204.081633 # average ReadReq miss latency
136 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
137 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52255.653809 # average ReadReq miss latency
138 system.l2c.ReadReq_avg_miss_latency::cpu.data 52565.866543 # average ReadReq miss latency
139 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 14585.783402 # average UpgradeReq miss latency
140 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.141080 # average ReadExReq miss latency
141 system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52204.081633 # average overall miss latency
142 system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
143 system.l2c.demand_avg_miss_latency::cpu.inst 52255.653809 # average overall miss latency
144 system.l2c.demand_avg_miss_latency::cpu.data 52195.550427 # average overall miss latency
145 system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52204.081633 # average overall miss latency
146 system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
147 system.l2c.overall_avg_miss_latency::cpu.inst 52255.653809 # average overall miss latency
148 system.l2c.overall_avg_miss_latency::cpu.data 52195.550427 # average overall miss latency
149 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
150 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
151 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
152 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
153 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
154 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
155 system.l2c.fast_writes 0 # number of fast writes performed
156 system.l2c.cache_copies 0 # number of cache copies performed
157 system.l2c.writebacks::writebacks 141515 # number of writebacks
158 system.l2c.writebacks::total 141515 # number of writebacks
159 system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
160 system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
161 system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
162 system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
163 system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
164 system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
165 system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
166 system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
167 system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
168 system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 98 # number of ReadReq MSHR misses
169 system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
170 system.l2c.ReadReq_mshr_misses::cpu.inst 19676 # number of ReadReq MSHR misses
171 system.l2c.ReadReq_mshr_misses::cpu.data 45242 # number of ReadReq MSHR misses
172 system.l2c.ReadReq_mshr_misses::total 65023 # number of ReadReq MSHR misses
173 system.l2c.UpgradeReq_mshr_misses::cpu.data 2687 # number of UpgradeReq MSHR misses
174 system.l2c.UpgradeReq_mshr_misses::total 2687 # number of UpgradeReq MSHR misses
175 system.l2c.ReadExReq_mshr_misses::cpu.data 141494 # number of ReadExReq MSHR misses
176 system.l2c.ReadExReq_mshr_misses::total 141494 # number of ReadExReq MSHR misses
177 system.l2c.demand_mshr_misses::cpu.dtb.walker 98 # number of demand (read+write) MSHR misses
178 system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
179 system.l2c.demand_mshr_misses::cpu.inst 19676 # number of demand (read+write) MSHR misses
180 system.l2c.demand_mshr_misses::cpu.data 186736 # number of demand (read+write) MSHR misses
181 system.l2c.demand_mshr_misses::total 206517 # number of demand (read+write) MSHR misses
182 system.l2c.overall_mshr_misses::cpu.dtb.walker 98 # number of overall MSHR misses
183 system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
184 system.l2c.overall_mshr_misses::cpu.inst 19676 # number of overall MSHR misses
185 system.l2c.overall_mshr_misses::cpu.data 186736 # number of overall MSHR misses
186 system.l2c.overall_mshr_misses::total 206517 # number of overall MSHR misses
187 system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 3927500 # number of ReadReq MSHR miss cycles
188 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles
189 system.l2c.ReadReq_mshr_miss_latency::cpu.inst 787879000 # number of ReadReq MSHR miss cycles
190 system.l2c.ReadReq_mshr_miss_latency::cpu.data 1825148000 # number of ReadReq MSHR miss cycles
191 system.l2c.ReadReq_mshr_miss_latency::total 2617234500 # number of ReadReq MSHR miss cycles
192 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 107845000 # number of UpgradeReq MSHR miss cycles
193 system.l2c.UpgradeReq_mshr_miss_latency::total 107845000 # number of UpgradeReq MSHR miss cycles
194 system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5661229500 # number of ReadExReq MSHR miss cycles
195 system.l2c.ReadExReq_mshr_miss_latency::total 5661229500 # number of ReadExReq MSHR miss cycles
196 system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 3927500 # number of demand (read+write) MSHR miss cycles
197 system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
198 system.l2c.demand_mshr_miss_latency::cpu.inst 787879000 # number of demand (read+write) MSHR miss cycles
199 system.l2c.demand_mshr_miss_latency::cpu.data 7486377500 # number of demand (read+write) MSHR miss cycles
200 system.l2c.demand_mshr_miss_latency::total 8278464000 # number of demand (read+write) MSHR miss cycles
201 system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 3927500 # number of overall MSHR miss cycles
202 system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles
203 system.l2c.overall_mshr_miss_latency::cpu.inst 787879000 # number of overall MSHR miss cycles
204 system.l2c.overall_mshr_miss_latency::cpu.data 7486377500 # number of overall MSHR miss cycles
205 system.l2c.overall_mshr_miss_latency::total 8278464000 # number of overall MSHR miss cycles
206 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975987000 # number of ReadReq MSHR uncacheable cycles
207 system.l2c.ReadReq_mshr_uncacheable_latency::total 59975987000 # number of ReadReq MSHR uncacheable cycles
208 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1230144500 # number of WriteReq MSHR uncacheable cycles
209 system.l2c.WriteReq_mshr_uncacheable_latency::total 1230144500 # number of WriteReq MSHR uncacheable cycles
210 system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206131500 # number of overall MSHR uncacheable cycles
211 system.l2c.overall_mshr_uncacheable_latency::total 61206131500 # number of overall MSHR uncacheable cycles
212 system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for ReadReq accesses
213 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for ReadReq accesses
214 system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for ReadReq accesses
215 system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032778 # mshr miss rate for ReadReq accesses
216 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.892988 # mshr miss rate for UpgradeReq accesses
217 system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.483002 # mshr miss rate for ReadExReq accesses
218 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for demand accesses
219 system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for demand accesses
220 system.l2c.demand_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for demand accesses
221 system.l2c.demand_mshr_miss_rate::cpu.data 0.111603 # mshr miss rate for demand accesses
222 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for overall accesses
223 system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for overall accesses
224 system.l2c.overall_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for overall accesses
225 system.l2c.overall_mshr_miss_rate::cpu.data 0.111603 # mshr miss rate for overall accesses
226 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average ReadReq mshr miss latency
227 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
228 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.640781 # average ReadReq mshr miss latency
229 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40341.894700 # average ReadReq mshr miss latency
230 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40135.839226 # average UpgradeReq mshr miss latency
231 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.385599 # average ReadExReq mshr miss latency
232 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency
233 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
234 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency
235 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency
236 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency
237 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
238 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency
239 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency
240 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
241 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
242 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
243 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
244 system.iocache.replacements 47576 # number of replacements
245 system.iocache.tagsinuse 0.159321 # Cycle average of tags in use
246 system.iocache.total_refs 0 # Total number of references to valid blocks.
247 system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
248 system.iocache.avg_refs 0 # Average number of references to valid blocks.
249 system.iocache.warmup_cycle 4996368196000 # Cycle when the warmup percentage was hit.
250 system.iocache.occ_blocks::pc.south_bridge.ide 0.159321 # Average occupied blocks per requestor
251 system.iocache.occ_percent::pc.south_bridge.ide 0.009958 # Average percentage of cache occupancy
252 system.iocache.occ_percent::total 0.009958 # Average percentage of cache occupancy
253 system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
254 system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
255 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
256 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
257 system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
258 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
259 system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
260 system.iocache.overall_misses::total 47631 # number of overall misses
261 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114195932 # number of ReadReq miss cycles
262 system.iocache.ReadReq_miss_latency::total 114195932 # number of ReadReq miss cycles
263 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6370894160 # number of WriteReq miss cycles
264 system.iocache.WriteReq_miss_latency::total 6370894160 # number of WriteReq miss cycles
265 system.iocache.demand_miss_latency::pc.south_bridge.ide 6485090092 # number of demand (read+write) miss cycles
266 system.iocache.demand_miss_latency::total 6485090092 # number of demand (read+write) miss cycles
267 system.iocache.overall_miss_latency::pc.south_bridge.ide 6485090092 # number of overall miss cycles
268 system.iocache.overall_miss_latency::total 6485090092 # number of overall miss cycles
269 system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
270 system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
271 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
272 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
273 system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
274 system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
275 system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
276 system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
277 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
278 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
279 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
280 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
281 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125352.285401 # average ReadReq miss latency
282 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136363.316781 # average WriteReq miss latency
283 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency
284 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency
285 system.iocache.blocked_cycles::no_mshrs 68835510 # number of cycles access was blocked
286 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
287 system.iocache.blocked::no_mshrs 11261 # number of cycles access was blocked
288 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
289 system.iocache.avg_blocked_cycles::no_mshrs 6112.735103 # average number of cycles each access was blocked
290 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
291 system.iocache.fast_writes 0 # number of fast writes performed
292 system.iocache.cache_copies 0 # number of cache copies performed
293 system.iocache.writebacks::writebacks 46667 # number of writebacks
294 system.iocache.writebacks::total 46667 # number of writebacks
295 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
296 system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
297 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
298 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
299 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
300 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
301 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
302 system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
303 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66802976 # number of ReadReq MSHR miss cycles
304 system.iocache.ReadReq_mshr_miss_latency::total 66802976 # number of ReadReq MSHR miss cycles
305 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3941136864 # number of WriteReq MSHR miss cycles
306 system.iocache.WriteReq_mshr_miss_latency::total 3941136864 # number of WriteReq MSHR miss cycles
307 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of demand (read+write) MSHR miss cycles
308 system.iocache.demand_mshr_miss_latency::total 4007939840 # number of demand (read+write) MSHR miss cycles
309 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of overall MSHR miss cycles
310 system.iocache.overall_mshr_miss_latency::total 4007939840 # number of overall MSHR miss cycles
311 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
312 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
313 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
314 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
315 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73329.282108 # average ReadReq mshr miss latency
316 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84356.525342 # average WriteReq mshr miss latency
317 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency
318 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency
319 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
320 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
321 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
322 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
323 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
324 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
325 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
326 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
327 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
328 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
329 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
330 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
331 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
332 system.cpu.numCycles 461736319 # number of cpu cycles simulated
333 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
334 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
335 system.cpu.BPredUnit.lookups 90084371 # Number of BP lookups
336 system.cpu.BPredUnit.condPredicted 90084371 # Number of conditional branches predicted
337 system.cpu.BPredUnit.condIncorrect 1179546 # Number of conditional branches incorrect
338 system.cpu.BPredUnit.BTBLookups 84316538 # Number of BTB lookups
339 system.cpu.BPredUnit.BTBHits 81732802 # Number of BTB hits
340 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
341 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
342 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
343 system.cpu.fetch.icacheStallCycles 29640549 # Number of cycles fetch is stalled on an Icache miss
344 system.cpu.fetch.Insts 447158079 # Number of instructions fetch has processed
345 system.cpu.fetch.Branches 90084371 # Number of branches that fetch encountered
346 system.cpu.fetch.predictedBranches 81732802 # Number of branches that fetch has predicted taken
347 system.cpu.fetch.Cycles 169862026 # Number of cycles fetch has run and was not squashing or blocked
348 system.cpu.fetch.SquashCycles 5320379 # Number of cycles fetch has spent squashing
349 system.cpu.fetch.TlbCycles 145881 # Number of cycles fetch has spent waiting for tlb
350 system.cpu.fetch.BlockedCycles 102119338 # Number of cycles fetch has spent blocked
351 system.cpu.fetch.MiscStallCycles 37850 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
352 system.cpu.fetch.PendingTrapStallCycles 39504 # Number of stall cycles due to pending traps
353 system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR
354 system.cpu.fetch.CacheLines 9392758 # Number of cache lines fetched
355 system.cpu.fetch.IcacheSquashes 524186 # Number of outstanding Icache misses that were squashed
356 system.cpu.fetch.ItlbSquashes 5360 # Number of outstanding ITLB misses that were squashed
357 system.cpu.fetch.rateDist::samples 305948772 # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.rateDist::mean 2.876024 # Number of instructions fetched each cycle (Total)
359 system.cpu.fetch.rateDist::stdev 3.383488 # Number of instructions fetched each cycle (Total)
360 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
361 system.cpu.fetch.rateDist::0 136524607 44.62% 44.62% # Number of instructions fetched each cycle (Total)
362 system.cpu.fetch.rateDist::1 1781462 0.58% 45.21% # Number of instructions fetched each cycle (Total)
363 system.cpu.fetch.rateDist::2 72780882 23.79% 68.99% # Number of instructions fetched each cycle (Total)
364 system.cpu.fetch.rateDist::3 993009 0.32% 69.32% # Number of instructions fetched each cycle (Total)
365 system.cpu.fetch.rateDist::4 1639605 0.54% 69.85% # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::5 3682017 1.20% 71.06% # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::6 1148071 0.38% 71.43% # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::7 1456036 0.48% 71.91% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::8 85943083 28.09% 100.00% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::total 305948772 # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.branchRate 0.195099 # Number of branch fetches per cycle
375 system.cpu.fetch.rate 0.968427 # Number of inst fetches per cycle
376 system.cpu.decode.IdleCycles 34742596 # Number of cycles decode is idle
377 system.cpu.decode.BlockedCycles 98230101 # Number of cycles decode is blocked
378 system.cpu.decode.RunCycles 164036692 # Number of cycles decode is running
379 system.cpu.decode.UnblockCycles 4836131 # Number of cycles decode is unblocking
380 system.cpu.decode.SquashCycles 4103252 # Number of cycles decode is squashing
381 system.cpu.decode.DecodedInsts 876669813 # Number of instructions handled by decode
382 system.cpu.decode.SquashedInsts 827 # Number of squashed instructions handled by decode
383 system.cpu.rename.SquashCycles 4103252 # Number of cycles rename is squashing
384 system.cpu.rename.IdleCycles 39030266 # Number of cycles rename is idle
385 system.cpu.rename.BlockCycles 68185463 # Number of cycles rename is blocking
386 system.cpu.rename.serializeStallCycles 10584671 # count of cycles rename stalled for serializing inst
387 system.cpu.rename.RunCycles 164072016 # Number of cycles rename is running
388 system.cpu.rename.UnblockCycles 19973104 # Number of cycles rename is unblocking
389 system.cpu.rename.RenamedInsts 872862955 # Number of instructions processed by rename
390 system.cpu.rename.ROBFullEvents 10194 # Number of times rename has blocked due to ROB full
391 system.cpu.rename.IQFullEvents 12946310 # Number of times rename has blocked due to IQ full
392 system.cpu.rename.LSQFullEvents 3889382 # Number of times rename has blocked due to LSQ full
393 system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
394 system.cpu.rename.RenamedOperands 874188806 # Number of destination operands rename has renamed
395 system.cpu.rename.RenameLookups 1710305089 # Number of register rename lookups that rename has made
396 system.cpu.rename.int_rename_lookups 1710304369 # Number of integer rename lookups
397 system.cpu.rename.fp_rename_lookups 720 # Number of floating rename lookups
398 system.cpu.rename.CommittedMaps 843320455 # Number of HB maps that are committed
399 system.cpu.rename.UndoneMaps 30868344 # Number of HB maps that are undone due to squashing
400 system.cpu.rename.serializingInsts 477917 # count of serializing insts renamed
401 system.cpu.rename.tempSerializingInsts 485258 # count of temporary serializing insts renamed
402 system.cpu.rename.skidInsts 46626951 # count of insts added to the skid buffer
403 system.cpu.memDep0.insertedLoads 18944692 # Number of loads inserted to the mem dependence unit.
404 system.cpu.memDep0.insertedStores 10483519 # Number of stores inserted to the mem dependence unit.
405 system.cpu.memDep0.conflictingLoads 1301190 # Number of conflicting loads.
406 system.cpu.memDep0.conflictingStores 1038101 # Number of conflicting stores.
407 system.cpu.iq.iqInstsAdded 865973387 # Number of instructions added to the IQ (excludes non-spec)
408 system.cpu.iq.iqNonSpecInstsAdded 1727922 # Number of non-speculative instructions added to the IQ
409 system.cpu.iq.iqInstsIssued 864611178 # Number of instructions issued
410 system.cpu.iq.iqSquashedInstsIssued 114248 # Number of squashed instructions issued
411 system.cpu.iq.iqSquashedInstsExamined 26054957 # Number of squashed instructions iterated over during squash; mainly for profiling
412 system.cpu.iq.iqSquashedOperandsExamined 37073399 # Number of squashed operands that are examined and possibly removed from graph
413 system.cpu.iq.iqSquashedNonSpecRemoved 207270 # Number of squashed non-spec instructions that were removed
414 system.cpu.iq.issued_per_cycle::samples 305948772 # Number of insts issued each cycle
415 system.cpu.iq.issued_per_cycle::mean 2.826000 # Number of insts issued each cycle
416 system.cpu.iq.issued_per_cycle::stdev 2.403043 # Number of insts issued each cycle
417 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
418 system.cpu.iq.issued_per_cycle::0 99370843 32.48% 32.48% # Number of insts issued each cycle
419 system.cpu.iq.issued_per_cycle::1 25451279 8.32% 40.80% # Number of insts issued each cycle
420 system.cpu.iq.issued_per_cycle::2 14262788 4.66% 45.46% # Number of insts issued each cycle
421 system.cpu.iq.issued_per_cycle::3 9410835 3.08% 48.54% # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::4 79123808 25.86% 74.40% # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::5 4863158 1.59% 75.99% # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::6 72802263 23.80% 99.78% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::7 533166 0.17% 99.96% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::8 130632 0.04% 100.00% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::total 305948772 # Number of insts issued each cycle
431 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
432 system.cpu.iq.fu_full::IntAlu 169581 8.02% 8.02% # attempts to use FU when none available
433 system.cpu.iq.fu_full::IntMult 0 0.00% 8.02% # attempts to use FU when none available
434 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.02% # attempts to use FU when none available
435 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.02% # attempts to use FU when none available
436 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.02% # attempts to use FU when none available
437 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.02% # attempts to use FU when none available
438 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.02% # attempts to use FU when none available
439 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.02% # attempts to use FU when none available
440 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.02% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.02% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.02% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.02% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.02% # attempts to use FU when none available
445 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.02% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.02% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.02% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.02% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.02% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.02% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.02% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.02% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.02% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.02% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.02% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.02% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.02% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.02% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.02% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.02% # attempts to use FU when none available
461 system.cpu.iq.fu_full::MemRead 1777046 84.08% 92.11% # attempts to use FU when none available
462 system.cpu.iq.fu_full::MemWrite 166802 7.89% 100.00% # attempts to use FU when none available
463 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
464 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
465 system.cpu.iq.FU_type_0::No_OpClass 304260 0.04% 0.04% # Type of FU issued
466 system.cpu.iq.FU_type_0::IntAlu 829639344 95.96% 95.99% # Type of FU issued
467 system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued
468 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued
469 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued
470 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued
471 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued
472 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued
473 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued
474 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued
479 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued
495 system.cpu.iq.FU_type_0::MemRead 25194661 2.91% 98.90% # Type of FU issued
496 system.cpu.iq.FU_type_0::MemWrite 9472913 1.10% 100.00% # Type of FU issued
497 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
498 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
499 system.cpu.iq.FU_type_0::total 864611178 # Type of FU issued
500 system.cpu.iq.rate 1.872521 # Inst issue rate
501 system.cpu.iq.fu_busy_cnt 2113429 # FU busy when requested
502 system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst)
503 system.cpu.iq.int_inst_queue_reads 2037542293 # Number of integer instruction queue reads
504 system.cpu.iq.int_inst_queue_writes 893767044 # Number of integer instruction queue writes
505 system.cpu.iq.int_inst_queue_wakeup_accesses 854207329 # Number of integer instruction queue wakeup accesses
506 system.cpu.iq.fp_inst_queue_reads 316 # Number of floating instruction queue reads
507 system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes
508 system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
509 system.cpu.iq.int_alu_accesses 866420202 # Number of integer alu accesses
510 system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses
511 system.cpu.iew.lsq.thread0.forwLoads 1589122 # Number of loads that had data forwarded from stores
512 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
513 system.cpu.iew.lsq.thread0.squashedLoads 3614563 # Number of loads squashed
514 system.cpu.iew.lsq.thread0.ignoredResponses 21772 # Number of memory responses ignored because the instruction is squashed
515 system.cpu.iew.lsq.thread0.memOrderViolation 12029 # Number of memory ordering violations
516 system.cpu.iew.lsq.thread0.squashedStores 2051269 # Number of stores squashed
517 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
518 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
519 system.cpu.iew.lsq.thread0.rescheduledLoads 7821662 # Number of loads that were rescheduled
520 system.cpu.iew.lsq.thread0.cacheBlocked 2623 # Number of times an access to memory failed due to the cache being blocked
521 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
522 system.cpu.iew.iewSquashCycles 4103252 # Number of cycles IEW is squashing
523 system.cpu.iew.iewBlockCycles 45514835 # Number of cycles IEW is blocking
524 system.cpu.iew.iewUnblockCycles 6136303 # Number of cycles IEW is unblocking
525 system.cpu.iew.iewDispatchedInsts 867701309 # Number of instructions dispatched to IQ
526 system.cpu.iew.iewDispSquashedInsts 314417 # Number of squashed instructions skipped by dispatch
527 system.cpu.iew.iewDispLoadInsts 18944692 # Number of dispatched load instructions
528 system.cpu.iew.iewDispStoreInsts 10483519 # Number of dispatched store instructions
529 system.cpu.iew.iewDispNonSpecInsts 889203 # Number of dispatched non-speculative instructions
530 system.cpu.iew.iewIQFullEvents 5413874 # Number of times the IQ has become full, causing a stall
531 system.cpu.iew.iewLSQFullEvents 12817 # Number of times the LSQ has become full, causing a stall
532 system.cpu.iew.memOrderViolationEvents 12029 # Number of memory order violations
533 system.cpu.iew.predictedTakenIncorrect 702671 # Number of branches that were predicted taken incorrectly
534 system.cpu.iew.predictedNotTakenIncorrect 628126 # Number of branches that were predicted not taken incorrectly
535 system.cpu.iew.branchMispredicts 1330797 # Number of branch mispredicts detected at execute
536 system.cpu.iew.iewExecutedInsts 862708188 # Number of executed instructions
537 system.cpu.iew.iewExecLoadInsts 24767979 # Number of load instructions executed
538 system.cpu.iew.iewExecSquashedInsts 1902989 # Number of squashed instructions skipped in execute
539 system.cpu.iew.exec_swp 0 # number of swp insts executed
540 system.cpu.iew.exec_nop 0 # number of nop insts executed
541 system.cpu.iew.exec_refs 33996128 # number of memory reference insts executed
542 system.cpu.iew.exec_branches 86527576 # Number of branches executed
543 system.cpu.iew.exec_stores 9228149 # Number of stores executed
544 system.cpu.iew.exec_rate 1.868400 # Inst execution rate
545 system.cpu.iew.wb_sent 862244747 # cumulative count of insts sent to commit
546 system.cpu.iew.wb_count 854207409 # cumulative count of insts written-back
547 system.cpu.iew.wb_producers 668533054 # num instructions producing a value
548 system.cpu.iew.wb_consumers 1167360089 # num instructions consuming a value
549 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
550 system.cpu.iew.wb_rate 1.849990 # insts written-back per cycle
551 system.cpu.iew.wb_fanout 0.572688 # average fanout of values written-back
552 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
553 system.cpu.commit.commitCommittedInsts 426629675 # The number of committed instructions
554 system.cpu.commit.commitCommittedOps 840716593 # The number of committed instructions
555 system.cpu.commit.commitSquashedInsts 26871696 # The number of squashed insts skipped by commit
556 system.cpu.commit.commitNonSpecStalls 1520650 # The number of times commit has been forced to stall to communicate backwards
557 system.cpu.commit.branchMispredicts 1183899 # The number of times a branch was mispredicted
558 system.cpu.commit.committed_per_cycle::samples 301861557 # Number of insts commited each cycle
559 system.cpu.commit.committed_per_cycle::mean 2.785107 # Number of insts commited each cycle
560 system.cpu.commit.committed_per_cycle::stdev 2.863294 # Number of insts commited each cycle
561 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
562 system.cpu.commit.committed_per_cycle::0 121093745 40.12% 40.12% # Number of insts commited each cycle
563 system.cpu.commit.committed_per_cycle::1 14426665 4.78% 44.89% # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::2 4304237 1.43% 46.32% # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::3 76676312 25.40% 71.72% # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::4 3920373 1.30% 73.02% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::5 1782325 0.59% 73.61% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::6 1109784 0.37% 73.98% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::7 71984231 23.85% 97.83% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::8 6563885 2.17% 100.00% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::total 301861557 # Number of insts commited each cycle
575 system.cpu.commit.committedInsts 426629675 # Number of instructions committed
576 system.cpu.commit.committedOps 840716593 # Number of ops (including micro ops) committed
577 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
578 system.cpu.commit.refs 23762376 # Number of memory references committed
579 system.cpu.commit.loads 15330126 # Number of loads committed
580 system.cpu.commit.membars 781563 # Number of memory barriers committed
581 system.cpu.commit.branches 85529575 # Number of branches committed
582 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
583 system.cpu.commit.int_insts 768542107 # Number of committed integer instructions.
584 system.cpu.commit.function_calls 0 # Number of function calls committed.
585 system.cpu.commit.bw_lim_events 6563885 # number cycles where commit BW limit reached
586 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
587 system.cpu.rob.rob_reads 1162802870 # The number of ROB reads
588 system.cpu.rob.rob_writes 1739294618 # The number of ROB writes
589 system.cpu.timesIdled 2882631 # Number of times that the entire CPU went into an idle state and unscheduled itself
590 system.cpu.idleCycles 155787547 # Total number of cycles that the CPU has spent unscheduled due to idling
591 system.cpu.quiesceCycles 9848837790 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
592 system.cpu.committedInsts 426629675 # Number of Instructions Simulated
593 system.cpu.committedOps 840716593 # Number of Ops (including micro ops) Simulated
594 system.cpu.committedInsts_total 426629675 # Number of Instructions Simulated
595 system.cpu.cpi 1.082288 # CPI: Cycles Per Instruction
596 system.cpu.cpi_total 1.082288 # CPI: Total CPI of All Threads
597 system.cpu.ipc 0.923968 # IPC: Instructions Per Cycle
598 system.cpu.ipc_total 0.923968 # IPC: Total IPC of All Threads
599 system.cpu.int_regfile_reads 1404705112 # number of integer regfile reads
600 system.cpu.int_regfile_writes 855482985 # number of integer regfile writes
601 system.cpu.fp_regfile_reads 80 # number of floating regfile reads
602 system.cpu.misc_regfile_reads 281196998 # number of misc regfile reads
603 system.cpu.misc_regfile_writes 410876 # number of misc regfile writes
604 system.cpu.icache.replacements 1083725 # number of replacements
605 system.cpu.icache.tagsinuse 510.022776 # Cycle average of tags in use
606 system.cpu.icache.total_refs 8238065 # Total number of references to valid blocks.
607 system.cpu.icache.sampled_refs 1084236 # Sample count of references to valid blocks.
608 system.cpu.icache.avg_refs 7.598037 # Average number of references to valid blocks.
609 system.cpu.icache.warmup_cycle 56617488000 # Cycle when the warmup percentage was hit.
610 system.cpu.icache.occ_blocks::cpu.inst 510.022776 # Average occupied blocks per requestor
611 system.cpu.icache.occ_percent::cpu.inst 0.996138 # Average percentage of cache occupancy
612 system.cpu.icache.occ_percent::total 0.996138 # Average percentage of cache occupancy
613 system.cpu.icache.ReadReq_hits::cpu.inst 8238065 # number of ReadReq hits
614 system.cpu.icache.ReadReq_hits::total 8238065 # number of ReadReq hits
615 system.cpu.icache.demand_hits::cpu.inst 8238065 # number of demand (read+write) hits
616 system.cpu.icache.demand_hits::total 8238065 # number of demand (read+write) hits
617 system.cpu.icache.overall_hits::cpu.inst 8238065 # number of overall hits
618 system.cpu.icache.overall_hits::total 8238065 # number of overall hits
619 system.cpu.icache.ReadReq_misses::cpu.inst 1154689 # number of ReadReq misses
620 system.cpu.icache.ReadReq_misses::total 1154689 # number of ReadReq misses
621 system.cpu.icache.demand_misses::cpu.inst 1154689 # number of demand (read+write) misses
622 system.cpu.icache.demand_misses::total 1154689 # number of demand (read+write) misses
623 system.cpu.icache.overall_misses::cpu.inst 1154689 # number of overall misses
624 system.cpu.icache.overall_misses::total 1154689 # number of overall misses
625 system.cpu.icache.ReadReq_miss_latency::cpu.inst 17243109487 # number of ReadReq miss cycles
626 system.cpu.icache.ReadReq_miss_latency::total 17243109487 # number of ReadReq miss cycles
627 system.cpu.icache.demand_miss_latency::cpu.inst 17243109487 # number of demand (read+write) miss cycles
628 system.cpu.icache.demand_miss_latency::total 17243109487 # number of demand (read+write) miss cycles
629 system.cpu.icache.overall_miss_latency::cpu.inst 17243109487 # number of overall miss cycles
630 system.cpu.icache.overall_miss_latency::total 17243109487 # number of overall miss cycles
631 system.cpu.icache.ReadReq_accesses::cpu.inst 9392754 # number of ReadReq accesses(hits+misses)
632 system.cpu.icache.ReadReq_accesses::total 9392754 # number of ReadReq accesses(hits+misses)
633 system.cpu.icache.demand_accesses::cpu.inst 9392754 # number of demand (read+write) accesses
634 system.cpu.icache.demand_accesses::total 9392754 # number of demand (read+write) accesses
635 system.cpu.icache.overall_accesses::cpu.inst 9392754 # number of overall (read+write) accesses
636 system.cpu.icache.overall_accesses::total 9392754 # number of overall (read+write) accesses
637 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122934 # miss rate for ReadReq accesses
638 system.cpu.icache.demand_miss_rate::cpu.inst 0.122934 # miss rate for demand accesses
639 system.cpu.icache.overall_miss_rate::cpu.inst 0.122934 # miss rate for overall accesses
640 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14933.120076 # average ReadReq miss latency
641 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency
642 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency
643 system.cpu.icache.blocked_cycles::no_mshrs 2884989 # number of cycles access was blocked
644 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
645 system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked
646 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
647 system.cpu.icache.avg_blocked_cycles::no_mshrs 9616.630000 # average number of cycles each access was blocked
648 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
649 system.cpu.icache.fast_writes 0 # number of fast writes performed
650 system.cpu.icache.cache_copies 0 # number of cache copies performed
651 system.cpu.icache.writebacks::writebacks 1570 # number of writebacks
652 system.cpu.icache.writebacks::total 1570 # number of writebacks
653 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69164 # number of ReadReq MSHR hits
654 system.cpu.icache.ReadReq_mshr_hits::total 69164 # number of ReadReq MSHR hits
655 system.cpu.icache.demand_mshr_hits::cpu.inst 69164 # number of demand (read+write) MSHR hits
656 system.cpu.icache.demand_mshr_hits::total 69164 # number of demand (read+write) MSHR hits
657 system.cpu.icache.overall_mshr_hits::cpu.inst 69164 # number of overall MSHR hits
658 system.cpu.icache.overall_mshr_hits::total 69164 # number of overall MSHR hits
659 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1085525 # number of ReadReq MSHR misses
660 system.cpu.icache.ReadReq_mshr_misses::total 1085525 # number of ReadReq MSHR misses
661 system.cpu.icache.demand_mshr_misses::cpu.inst 1085525 # number of demand (read+write) MSHR misses
662 system.cpu.icache.demand_mshr_misses::total 1085525 # number of demand (read+write) MSHR misses
663 system.cpu.icache.overall_mshr_misses::cpu.inst 1085525 # number of overall MSHR misses
664 system.cpu.icache.overall_mshr_misses::total 1085525 # number of overall MSHR misses
665 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13103385489 # number of ReadReq MSHR miss cycles
666 system.cpu.icache.ReadReq_mshr_miss_latency::total 13103385489 # number of ReadReq MSHR miss cycles
667 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13103385489 # number of demand (read+write) MSHR miss cycles
668 system.cpu.icache.demand_mshr_miss_latency::total 13103385489 # number of demand (read+write) MSHR miss cycles
669 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13103385489 # number of overall MSHR miss cycles
670 system.cpu.icache.overall_mshr_miss_latency::total 13103385489 # number of overall MSHR miss cycles
671 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for ReadReq accesses
672 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for demand accesses
673 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for overall accesses
674 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12071.012173 # average ReadReq mshr miss latency
675 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency
676 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency
677 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
678 system.cpu.itb_walker_cache.replacements 11375 # number of replacements
679 system.cpu.itb_walker_cache.tagsinuse 6.006905 # Cycle average of tags in use
680 system.cpu.itb_walker_cache.total_refs 28918 # Total number of references to valid blocks.
681 system.cpu.itb_walker_cache.sampled_refs 11386 # Sample count of references to valid blocks.
682 system.cpu.itb_walker_cache.avg_refs 2.539786 # Average number of references to valid blocks.
683 system.cpu.itb_walker_cache.warmup_cycle 5142961834000 # Cycle when the warmup percentage was hit.
684 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006905 # Average occupied blocks per requestor
685 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375432 # Average percentage of cache occupancy
686 system.cpu.itb_walker_cache.occ_percent::total 0.375432 # Average percentage of cache occupancy
687 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28987 # number of ReadReq hits
688 system.cpu.itb_walker_cache.ReadReq_hits::total 28987 # number of ReadReq hits
689 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
690 system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
691 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28990 # number of demand (read+write) hits
692 system.cpu.itb_walker_cache.demand_hits::total 28990 # number of demand (read+write) hits
693 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28990 # number of overall hits
694 system.cpu.itb_walker_cache.overall_hits::total 28990 # number of overall hits
695 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12232 # number of ReadReq misses
696 system.cpu.itb_walker_cache.ReadReq_misses::total 12232 # number of ReadReq misses
697 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12232 # number of demand (read+write) misses
698 system.cpu.itb_walker_cache.demand_misses::total 12232 # number of demand (read+write) misses
699 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12232 # number of overall misses
700 system.cpu.itb_walker_cache.overall_misses::total 12232 # number of overall misses
701 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 154656000 # number of ReadReq miss cycles
702 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 154656000 # number of ReadReq miss cycles
703 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 154656000 # number of demand (read+write) miss cycles
704 system.cpu.itb_walker_cache.demand_miss_latency::total 154656000 # number of demand (read+write) miss cycles
705 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 154656000 # number of overall miss cycles
706 system.cpu.itb_walker_cache.overall_miss_latency::total 154656000 # number of overall miss cycles
707 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41219 # number of ReadReq accesses(hits+misses)
708 system.cpu.itb_walker_cache.ReadReq_accesses::total 41219 # number of ReadReq accesses(hits+misses)
709 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
710 system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
711 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41222 # number of demand (read+write) accesses
712 system.cpu.itb_walker_cache.demand_accesses::total 41222 # number of demand (read+write) accesses
713 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41222 # number of overall (read+write) accesses
714 system.cpu.itb_walker_cache.overall_accesses::total 41222 # number of overall (read+write) accesses
715 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.296756 # miss rate for ReadReq accesses
716 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.296735 # miss rate for demand accesses
717 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.296735 # miss rate for overall accesses
718 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12643.557881 # average ReadReq miss latency
719 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency
720 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency
721 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
722 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
723 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
724 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
725 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
726 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
727 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
728 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
729 system.cpu.itb_walker_cache.writebacks::writebacks 1402 # number of writebacks
730 system.cpu.itb_walker_cache.writebacks::total 1402 # number of writebacks
731 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12232 # number of ReadReq MSHR misses
732 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12232 # number of ReadReq MSHR misses
733 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12232 # number of demand (read+write) MSHR misses
734 system.cpu.itb_walker_cache.demand_mshr_misses::total 12232 # number of demand (read+write) MSHR misses
735 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12232 # number of overall MSHR misses
736 system.cpu.itb_walker_cache.overall_mshr_misses::total 12232 # number of overall MSHR misses
737 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 117502000 # number of ReadReq MSHR miss cycles
738 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 117502000 # number of ReadReq MSHR miss cycles
739 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 117502000 # number of demand (read+write) MSHR miss cycles
740 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 117502000 # number of demand (read+write) MSHR miss cycles
741 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 117502000 # number of overall MSHR miss cycles
742 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 117502000 # number of overall MSHR miss cycles
743 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.296756 # mshr miss rate for ReadReq accesses
744 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for demand accesses
745 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for overall accesses
746 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average ReadReq mshr miss latency
747 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency
748 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency
749 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
750 system.cpu.dtb_walker_cache.replacements 125889 # number of replacements
751 system.cpu.dtb_walker_cache.tagsinuse 12.942075 # Cycle average of tags in use
752 system.cpu.dtb_walker_cache.total_refs 147310 # Total number of references to valid blocks.
753 system.cpu.dtb_walker_cache.sampled_refs 125903 # Sample count of references to valid blocks.
754 system.cpu.dtb_walker_cache.avg_refs 1.170028 # Average number of references to valid blocks.
755 system.cpu.dtb_walker_cache.warmup_cycle 5108639465000 # Cycle when the warmup percentage was hit.
756 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942075 # Average occupied blocks per requestor
757 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808880 # Average percentage of cache occupancy
758 system.cpu.dtb_walker_cache.occ_percent::total 0.808880 # Average percentage of cache occupancy
759 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 147324 # number of ReadReq hits
760 system.cpu.dtb_walker_cache.ReadReq_hits::total 147324 # number of ReadReq hits
761 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 147324 # number of demand (read+write) hits
762 system.cpu.dtb_walker_cache.demand_hits::total 147324 # number of demand (read+write) hits
763 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 147324 # number of overall hits
764 system.cpu.dtb_walker_cache.overall_hits::total 147324 # number of overall hits
765 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 126858 # number of ReadReq misses
766 system.cpu.dtb_walker_cache.ReadReq_misses::total 126858 # number of ReadReq misses
767 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 126858 # number of demand (read+write) misses
768 system.cpu.dtb_walker_cache.demand_misses::total 126858 # number of demand (read+write) misses
769 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 126858 # number of overall misses
770 system.cpu.dtb_walker_cache.overall_misses::total 126858 # number of overall misses
771 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1765137000 # number of ReadReq miss cycles
772 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1765137000 # number of ReadReq miss cycles
773 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1765137000 # number of demand (read+write) miss cycles
774 system.cpu.dtb_walker_cache.demand_miss_latency::total 1765137000 # number of demand (read+write) miss cycles
775 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1765137000 # number of overall miss cycles
776 system.cpu.dtb_walker_cache.overall_miss_latency::total 1765137000 # number of overall miss cycles
777 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 274182 # number of ReadReq accesses(hits+misses)
778 system.cpu.dtb_walker_cache.ReadReq_accesses::total 274182 # number of ReadReq accesses(hits+misses)
779 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 274182 # number of demand (read+write) accesses
780 system.cpu.dtb_walker_cache.demand_accesses::total 274182 # number of demand (read+write) accesses
781 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 274182 # number of overall (read+write) accesses
782 system.cpu.dtb_walker_cache.overall_accesses::total 274182 # number of overall (read+write) accesses
783 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.462678 # miss rate for ReadReq accesses
784 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.462678 # miss rate for demand accesses
785 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.462678 # miss rate for overall accesses
786 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13914.274228 # average ReadReq miss latency
787 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency
788 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency
789 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
790 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
791 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
792 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
793 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
794 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
795 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
796 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
797 system.cpu.dtb_walker_cache.writebacks::writebacks 38155 # number of writebacks
798 system.cpu.dtb_walker_cache.writebacks::total 38155 # number of writebacks
799 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 126858 # number of ReadReq MSHR misses
800 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 126858 # number of ReadReq MSHR misses
801 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 126858 # number of demand (read+write) MSHR misses
802 system.cpu.dtb_walker_cache.demand_mshr_misses::total 126858 # number of demand (read+write) MSHR misses
803 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 126858 # number of overall MSHR misses
804 system.cpu.dtb_walker_cache.overall_mshr_misses::total 126858 # number of overall MSHR misses
805 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of ReadReq MSHR miss cycles
806 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1381422000 # number of ReadReq MSHR miss cycles
807 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of demand (read+write) MSHR miss cycles
808 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1381422000 # number of demand (read+write) MSHR miss cycles
809 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of overall MSHR miss cycles
810 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1381422000 # number of overall MSHR miss cycles
811 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for ReadReq accesses
812 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for demand accesses
813 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for overall accesses
814 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average ReadReq mshr miss latency
815 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency
816 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency
817 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
818 system.cpu.dcache.replacements 1673228 # number of replacements
819 system.cpu.dcache.tagsinuse 511.997037 # Cycle average of tags in use
820 system.cpu.dcache.total_refs 19088314 # Total number of references to valid blocks.
821 system.cpu.dcache.sampled_refs 1673740 # Sample count of references to valid blocks.
822 system.cpu.dcache.avg_refs 11.404587 # Average number of references to valid blocks.
823 system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit.
824 system.cpu.dcache.occ_blocks::cpu.data 511.997037 # Average occupied blocks per requestor
825 system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
826 system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
827 system.cpu.dcache.ReadReq_hits::cpu.data 10979879 # number of ReadReq hits
828 system.cpu.dcache.ReadReq_hits::total 10979879 # number of ReadReq hits
829 system.cpu.dcache.WriteReq_hits::cpu.data 8104687 # number of WriteReq hits
830 system.cpu.dcache.WriteReq_hits::total 8104687 # number of WriteReq hits
831 system.cpu.dcache.demand_hits::cpu.data 19084566 # number of demand (read+write) hits
832 system.cpu.dcache.demand_hits::total 19084566 # number of demand (read+write) hits
833 system.cpu.dcache.overall_hits::cpu.data 19084566 # number of overall hits
834 system.cpu.dcache.overall_hits::total 19084566 # number of overall hits
835 system.cpu.dcache.ReadReq_misses::cpu.data 2411794 # number of ReadReq misses
836 system.cpu.dcache.ReadReq_misses::total 2411794 # number of ReadReq misses
837 system.cpu.dcache.WriteReq_misses::cpu.data 318210 # number of WriteReq misses
838 system.cpu.dcache.WriteReq_misses::total 318210 # number of WriteReq misses
839 system.cpu.dcache.demand_misses::cpu.data 2730004 # number of demand (read+write) misses
840 system.cpu.dcache.demand_misses::total 2730004 # number of demand (read+write) misses
841 system.cpu.dcache.overall_misses::cpu.data 2730004 # number of overall misses
842 system.cpu.dcache.overall_misses::total 2730004 # number of overall misses
843 system.cpu.dcache.ReadReq_miss_latency::cpu.data 36160191000 # number of ReadReq miss cycles
844 system.cpu.dcache.ReadReq_miss_latency::total 36160191000 # number of ReadReq miss cycles
845 system.cpu.dcache.WriteReq_miss_latency::cpu.data 10588613980 # number of WriteReq miss cycles
846 system.cpu.dcache.WriteReq_miss_latency::total 10588613980 # number of WriteReq miss cycles
847 system.cpu.dcache.demand_miss_latency::cpu.data 46748804980 # number of demand (read+write) miss cycles
848 system.cpu.dcache.demand_miss_latency::total 46748804980 # number of demand (read+write) miss cycles
849 system.cpu.dcache.overall_miss_latency::cpu.data 46748804980 # number of overall miss cycles
850 system.cpu.dcache.overall_miss_latency::total 46748804980 # number of overall miss cycles
851 system.cpu.dcache.ReadReq_accesses::cpu.data 13391673 # number of ReadReq accesses(hits+misses)
852 system.cpu.dcache.ReadReq_accesses::total 13391673 # number of ReadReq accesses(hits+misses)
853 system.cpu.dcache.WriteReq_accesses::cpu.data 8422897 # number of WriteReq accesses(hits+misses)
854 system.cpu.dcache.WriteReq_accesses::total 8422897 # number of WriteReq accesses(hits+misses)
855 system.cpu.dcache.demand_accesses::cpu.data 21814570 # number of demand (read+write) accesses
856 system.cpu.dcache.demand_accesses::total 21814570 # number of demand (read+write) accesses
857 system.cpu.dcache.overall_accesses::cpu.data 21814570 # number of overall (read+write) accesses
858 system.cpu.dcache.overall_accesses::total 21814570 # number of overall (read+write) accesses
859 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180097 # miss rate for ReadReq accesses
860 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037779 # miss rate for WriteReq accesses
861 system.cpu.dcache.demand_miss_rate::cpu.data 0.125146 # miss rate for demand accesses
862 system.cpu.dcache.overall_miss_rate::cpu.data 0.125146 # miss rate for overall accesses
863 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14993.067816 # average ReadReq miss latency
864 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33275.553817 # average WriteReq miss latency
865 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency
866 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency
867 system.cpu.dcache.blocked_cycles::no_mshrs 23292480 # number of cycles access was blocked
868 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
869 system.cpu.dcache.blocked::no_mshrs 3427 # number of cycles access was blocked
870 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
871 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.755179 # average number of cycles each access was blocked
872 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
873 system.cpu.dcache.fast_writes 0 # number of fast writes performed
874 system.cpu.dcache.cache_copies 0 # number of cache copies performed
875 system.cpu.dcache.writebacks::writebacks 1561454 # number of writebacks
876 system.cpu.dcache.writebacks::total 1561454 # number of writebacks
877 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1030426 # number of ReadReq MSHR hits
878 system.cpu.dcache.ReadReq_mshr_hits::total 1030426 # number of ReadReq MSHR hits
879 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22364 # number of WriteReq MSHR hits
880 system.cpu.dcache.WriteReq_mshr_hits::total 22364 # number of WriteReq MSHR hits
881 system.cpu.dcache.demand_mshr_hits::cpu.data 1052790 # number of demand (read+write) MSHR hits
882 system.cpu.dcache.demand_mshr_hits::total 1052790 # number of demand (read+write) MSHR hits
883 system.cpu.dcache.overall_mshr_hits::cpu.data 1052790 # number of overall MSHR hits
884 system.cpu.dcache.overall_mshr_hits::total 1052790 # number of overall MSHR hits
885 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381368 # number of ReadReq MSHR misses
886 system.cpu.dcache.ReadReq_mshr_misses::total 1381368 # number of ReadReq MSHR misses
887 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295846 # number of WriteReq MSHR misses
888 system.cpu.dcache.WriteReq_mshr_misses::total 295846 # number of WriteReq MSHR misses
889 system.cpu.dcache.demand_mshr_misses::cpu.data 1677214 # number of demand (read+write) MSHR misses
890 system.cpu.dcache.demand_mshr_misses::total 1677214 # number of demand (read+write) MSHR misses
891 system.cpu.dcache.overall_mshr_misses::cpu.data 1677214 # number of overall MSHR misses
892 system.cpu.dcache.overall_mshr_misses::total 1677214 # number of overall MSHR misses
893 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18158276000 # number of ReadReq MSHR miss cycles
894 system.cpu.dcache.ReadReq_mshr_miss_latency::total 18158276000 # number of ReadReq MSHR miss cycles
895 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9372225480 # number of WriteReq MSHR miss cycles
896 system.cpu.dcache.WriteReq_mshr_miss_latency::total 9372225480 # number of WriteReq MSHR miss cycles
897 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27530501480 # number of demand (read+write) MSHR miss cycles
898 system.cpu.dcache.demand_mshr_miss_latency::total 27530501480 # number of demand (read+write) MSHR miss cycles
899 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27530501480 # number of overall MSHR miss cycles
900 system.cpu.dcache.overall_mshr_miss_latency::total 27530501480 # number of overall MSHR miss cycles
901 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208380500 # number of ReadReq MSHR uncacheable cycles
902 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208380500 # number of ReadReq MSHR uncacheable cycles
903 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393791500 # number of WriteReq MSHR uncacheable cycles
904 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393791500 # number of WriteReq MSHR uncacheable cycles
905 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602172000 # number of overall MSHR uncacheable cycles
906 system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602172000 # number of overall MSHR uncacheable cycles
907 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103151 # mshr miss rate for ReadReq accesses
908 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035124 # mshr miss rate for WriteReq accesses
909 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for demand accesses
910 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for overall accesses
911 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13145.140180 # average ReadReq mshr miss latency
912 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31679.405772 # average WriteReq mshr miss latency
913 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency
914 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency
915 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
916 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
917 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
918 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
919 system.cpu.kern.inst.arm 0 # number of arm instructions executed
920 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
922 ---------- End Simulation Statistics ----------
projects / gem5.git / blob