2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.172902 # Number of seconds simulated
4 sim_ticks 5172902281500 # Number of ticks simulated
5 final_tick 5172902281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 117061 # Simulator instruction rate (inst/s)
8 host_op_rate 230687 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1419746087 # Simulator tick rate (ticks/s)
10 host_mem_usage 420308 # Number of bytes of host memory used
11 host_seconds 3643.54 # Real time elapsed on the host
12 sim_insts 426515724 # Number of instructions simulated
13 sim_ops 840516219 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2496512 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 1067840 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10426304 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 13994560 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 1067840 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 1067840 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 9194240 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 9194240 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 39008 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 16685 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 162911 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 218665 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 143660 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 143660 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 482613 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 680 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 206430 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 2015562 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2705359 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 206430 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 206430 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 1777385 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 1777385 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 1777385 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 482613 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 206430 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 2015562 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4482745 # Total bandwidth to/from this memory (bytes/s)
49 system.l2c.replacements 107419 # number of replacements
50 system.l2c.tagsinuse 64844.084797 # Cycle average of tags in use
51 system.l2c.total_refs 3992672 # Total number of references to valid blocks.
52 system.l2c.sampled_refs 171622 # Sample count of references to valid blocks.
53 system.l2c.avg_refs 23.264337 # Average number of references to valid blocks.
54 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
55 system.l2c.occ_blocks::writebacks 50135.967843 # Average occupied blocks per requestor
56 system.l2c.occ_blocks::cpu.dtb.walker 12.897301 # Average occupied blocks per requestor
57 system.l2c.occ_blocks::cpu.itb.walker 0.156788 # Average occupied blocks per requestor
58 system.l2c.occ_blocks::cpu.inst 3372.666022 # Average occupied blocks per requestor
59 system.l2c.occ_blocks::cpu.data 11322.396844 # Average occupied blocks per requestor
60 system.l2c.occ_percent::writebacks 0.765014 # Average percentage of cache occupancy
61 system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy
62 system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
63 system.l2c.occ_percent::cpu.inst 0.051463 # Average percentage of cache occupancy
64 system.l2c.occ_percent::cpu.data 0.172766 # Average percentage of cache occupancy
65 system.l2c.occ_percent::total 0.989442 # Average percentage of cache occupancy
66 system.l2c.ReadReq_hits::cpu.dtb.walker 110667 # number of ReadReq hits
67 system.l2c.ReadReq_hits::cpu.itb.walker 8396 # number of ReadReq hits
68 system.l2c.ReadReq_hits::cpu.inst 1054432 # number of ReadReq hits
69 system.l2c.ReadReq_hits::cpu.data 1345104 # number of ReadReq hits
70 system.l2c.ReadReq_hits::total 2518599 # number of ReadReq hits
71 system.l2c.Writeback_hits::writebacks 1613189 # number of Writeback hits
72 system.l2c.Writeback_hits::total 1613189 # number of Writeback hits
73 system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits
74 system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits
75 system.l2c.ReadExReq_hits::cpu.data 163997 # number of ReadExReq hits
76 system.l2c.ReadExReq_hits::total 163997 # number of ReadExReq hits
77 system.l2c.demand_hits::cpu.dtb.walker 110667 # number of demand (read+write) hits
78 system.l2c.demand_hits::cpu.itb.walker 8396 # number of demand (read+write) hits
79 system.l2c.demand_hits::cpu.inst 1054432 # number of demand (read+write) hits
80 system.l2c.demand_hits::cpu.data 1509101 # number of demand (read+write) hits
81 system.l2c.demand_hits::total 2682596 # number of demand (read+write) hits
82 system.l2c.overall_hits::cpu.dtb.walker 110667 # number of overall hits
83 system.l2c.overall_hits::cpu.itb.walker 8396 # number of overall hits
84 system.l2c.overall_hits::cpu.inst 1054432 # number of overall hits
85 system.l2c.overall_hits::cpu.data 1509101 # number of overall hits
86 system.l2c.overall_hits::total 2682596 # number of overall hits
87 system.l2c.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses
88 system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
89 system.l2c.ReadReq_misses::cpu.inst 16686 # number of ReadReq misses
90 system.l2c.ReadReq_misses::cpu.data 35012 # number of ReadReq misses
91 system.l2c.ReadReq_misses::total 51759 # number of ReadReq misses
92 system.l2c.UpgradeReq_misses::cpu.data 1516 # number of UpgradeReq misses
93 system.l2c.UpgradeReq_misses::total 1516 # number of UpgradeReq misses
94 system.l2c.ReadExReq_misses::cpu.data 128839 # number of ReadExReq misses
95 system.l2c.ReadExReq_misses::total 128839 # number of ReadExReq misses
96 system.l2c.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses
97 system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
98 system.l2c.demand_misses::cpu.inst 16686 # number of demand (read+write) misses
99 system.l2c.demand_misses::cpu.data 163851 # number of demand (read+write) misses
100 system.l2c.demand_misses::total 180598 # number of demand (read+write) misses
101 system.l2c.overall_misses::cpu.dtb.walker 55 # number of overall misses
102 system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses
103 system.l2c.overall_misses::cpu.inst 16686 # number of overall misses
104 system.l2c.overall_misses::cpu.data 163851 # number of overall misses
105 system.l2c.overall_misses::total 180598 # number of overall misses
106 system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2907000 # number of ReadReq miss cycles
107 system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles
108 system.l2c.ReadReq_miss_latency::cpu.inst 885914499 # number of ReadReq miss cycles
109 system.l2c.ReadReq_miss_latency::cpu.data 1865182494 # number of ReadReq miss cycles
110 system.l2c.ReadReq_miss_latency::total 2754315993 # number of ReadReq miss cycles
111 system.l2c.UpgradeReq_miss_latency::cpu.data 39171500 # number of UpgradeReq miss cycles
112 system.l2c.UpgradeReq_miss_latency::total 39171500 # number of UpgradeReq miss cycles
113 system.l2c.ReadExReq_miss_latency::cpu.data 6715513999 # number of ReadExReq miss cycles
114 system.l2c.ReadExReq_miss_latency::total 6715513999 # number of ReadExReq miss cycles
115 system.l2c.demand_miss_latency::cpu.dtb.walker 2907000 # number of demand (read+write) miss cycles
116 system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles
117 system.l2c.demand_miss_latency::cpu.inst 885914499 # number of demand (read+write) miss cycles
118 system.l2c.demand_miss_latency::cpu.data 8580696493 # number of demand (read+write) miss cycles
119 system.l2c.demand_miss_latency::total 9469829992 # number of demand (read+write) miss cycles
120 system.l2c.overall_miss_latency::cpu.dtb.walker 2907000 # number of overall miss cycles
121 system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles
122 system.l2c.overall_miss_latency::cpu.inst 885914499 # number of overall miss cycles
123 system.l2c.overall_miss_latency::cpu.data 8580696493 # number of overall miss cycles
124 system.l2c.overall_miss_latency::total 9469829992 # number of overall miss cycles
125 system.l2c.ReadReq_accesses::cpu.dtb.walker 110722 # number of ReadReq accesses(hits+misses)
126 system.l2c.ReadReq_accesses::cpu.itb.walker 8402 # number of ReadReq accesses(hits+misses)
127 system.l2c.ReadReq_accesses::cpu.inst 1071118 # number of ReadReq accesses(hits+misses)
128 system.l2c.ReadReq_accesses::cpu.data 1380116 # number of ReadReq accesses(hits+misses)
129 system.l2c.ReadReq_accesses::total 2570358 # number of ReadReq accesses(hits+misses)
130 system.l2c.Writeback_accesses::writebacks 1613189 # number of Writeback accesses(hits+misses)
131 system.l2c.Writeback_accesses::total 1613189 # number of Writeback accesses(hits+misses)
132 system.l2c.UpgradeReq_accesses::cpu.data 1853 # number of UpgradeReq accesses(hits+misses)
133 system.l2c.UpgradeReq_accesses::total 1853 # number of UpgradeReq accesses(hits+misses)
134 system.l2c.ReadExReq_accesses::cpu.data 292836 # number of ReadExReq accesses(hits+misses)
135 system.l2c.ReadExReq_accesses::total 292836 # number of ReadExReq accesses(hits+misses)
136 system.l2c.demand_accesses::cpu.dtb.walker 110722 # number of demand (read+write) accesses
137 system.l2c.demand_accesses::cpu.itb.walker 8402 # number of demand (read+write) accesses
138 system.l2c.demand_accesses::cpu.inst 1071118 # number of demand (read+write) accesses
139 system.l2c.demand_accesses::cpu.data 1672952 # number of demand (read+write) accesses
140 system.l2c.demand_accesses::total 2863194 # number of demand (read+write) accesses
141 system.l2c.overall_accesses::cpu.dtb.walker 110722 # number of overall (read+write) accesses
142 system.l2c.overall_accesses::cpu.itb.walker 8402 # number of overall (read+write) accesses
143 system.l2c.overall_accesses::cpu.inst 1071118 # number of overall (read+write) accesses
144 system.l2c.overall_accesses::cpu.data 1672952 # number of overall (read+write) accesses
145 system.l2c.overall_accesses::total 2863194 # number of overall (read+write) accesses
146 system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000497 # miss rate for ReadReq accesses
147 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000714 # miss rate for ReadReq accesses
148 system.l2c.ReadReq_miss_rate::cpu.inst 0.015578 # miss rate for ReadReq accesses
149 system.l2c.ReadReq_miss_rate::cpu.data 0.025369 # miss rate for ReadReq accesses
150 system.l2c.ReadReq_miss_rate::total 0.020137 # miss rate for ReadReq accesses
151 system.l2c.UpgradeReq_miss_rate::cpu.data 0.818133 # miss rate for UpgradeReq accesses
152 system.l2c.UpgradeReq_miss_rate::total 0.818133 # miss rate for UpgradeReq accesses
153 system.l2c.ReadExReq_miss_rate::cpu.data 0.439970 # miss rate for ReadExReq accesses
154 system.l2c.ReadExReq_miss_rate::total 0.439970 # miss rate for ReadExReq accesses
155 system.l2c.demand_miss_rate::cpu.dtb.walker 0.000497 # miss rate for demand accesses
156 system.l2c.demand_miss_rate::cpu.itb.walker 0.000714 # miss rate for demand accesses
157 system.l2c.demand_miss_rate::cpu.inst 0.015578 # miss rate for demand accesses
158 system.l2c.demand_miss_rate::cpu.data 0.097941 # miss rate for demand accesses
159 system.l2c.demand_miss_rate::total 0.063076 # miss rate for demand accesses
160 system.l2c.overall_miss_rate::cpu.dtb.walker 0.000497 # miss rate for overall accesses
161 system.l2c.overall_miss_rate::cpu.itb.walker 0.000714 # miss rate for overall accesses
162 system.l2c.overall_miss_rate::cpu.inst 0.015578 # miss rate for overall accesses
163 system.l2c.overall_miss_rate::cpu.data 0.097941 # miss rate for overall accesses
164 system.l2c.overall_miss_rate::total 0.063076 # miss rate for overall accesses
165 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455 # average ReadReq miss latency
166 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
167 system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733 # average ReadReq miss latency
168 system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487 # average ReadReq miss latency
169 system.l2c.ReadReq_avg_miss_latency::total 53214.242798 # average ReadReq miss latency
170 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317 # average UpgradeReq miss latency
171 system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317 # average UpgradeReq miss latency
172 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167 # average ReadExReq miss latency
173 system.l2c.ReadExReq_avg_miss_latency::total 52123.301167 # average ReadExReq miss latency
174 system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency
175 system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
176 system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency
177 system.l2c.demand_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency
178 system.l2c.demand_avg_miss_latency::total 52435.962702 # average overall miss latency
179 system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency
180 system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
181 system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency
182 system.l2c.overall_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency
183 system.l2c.overall_avg_miss_latency::total 52435.962702 # average overall miss latency
184 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
185 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
186 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
187 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
188 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
189 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
190 system.l2c.fast_writes 0 # number of fast writes performed
191 system.l2c.cache_copies 0 # number of cache copies performed
192 system.l2c.writebacks::writebacks 96993 # number of writebacks
193 system.l2c.writebacks::total 96993 # number of writebacks
194 system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
195 system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
196 system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
197 system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
198 system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
199 system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
200 system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
201 system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
202 system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
203 system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses
204 system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
205 system.l2c.ReadReq_mshr_misses::cpu.inst 16685 # number of ReadReq MSHR misses
206 system.l2c.ReadReq_mshr_misses::cpu.data 35011 # number of ReadReq MSHR misses
207 system.l2c.ReadReq_mshr_misses::total 51757 # number of ReadReq MSHR misses
208 system.l2c.UpgradeReq_mshr_misses::cpu.data 1516 # number of UpgradeReq MSHR misses
209 system.l2c.UpgradeReq_mshr_misses::total 1516 # number of UpgradeReq MSHR misses
210 system.l2c.ReadExReq_mshr_misses::cpu.data 128839 # number of ReadExReq MSHR misses
211 system.l2c.ReadExReq_mshr_misses::total 128839 # number of ReadExReq MSHR misses
212 system.l2c.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses
213 system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
214 system.l2c.demand_mshr_misses::cpu.inst 16685 # number of demand (read+write) MSHR misses
215 system.l2c.demand_mshr_misses::cpu.data 163850 # number of demand (read+write) MSHR misses
216 system.l2c.demand_mshr_misses::total 180596 # number of demand (read+write) MSHR misses
217 system.l2c.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses
218 system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
219 system.l2c.overall_mshr_misses::cpu.inst 16685 # number of overall MSHR misses
220 system.l2c.overall_mshr_misses::cpu.data 163850 # number of overall MSHR misses
221 system.l2c.overall_mshr_misses::total 180596 # number of overall MSHR misses
222 system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2241000 # number of ReadReq MSHR miss cycles
223 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles
224 system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682427500 # number of ReadReq MSHR miss cycles
225 system.l2c.ReadReq_mshr_miss_latency::cpu.data 1437356500 # number of ReadReq MSHR miss cycles
226 system.l2c.ReadReq_mshr_miss_latency::total 2122265000 # number of ReadReq MSHR miss cycles
227 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 61068000 # number of UpgradeReq MSHR miss cycles
228 system.l2c.UpgradeReq_mshr_miss_latency::total 61068000 # number of UpgradeReq MSHR miss cycles
229 system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5163609501 # number of ReadExReq MSHR miss cycles
230 system.l2c.ReadExReq_mshr_miss_latency::total 5163609501 # number of ReadExReq MSHR miss cycles
231 system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2241000 # number of demand (read+write) MSHR miss cycles
232 system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles
233 system.l2c.demand_mshr_miss_latency::cpu.inst 682427500 # number of demand (read+write) MSHR miss cycles
234 system.l2c.demand_mshr_miss_latency::cpu.data 6600966001 # number of demand (read+write) MSHR miss cycles
235 system.l2c.demand_mshr_miss_latency::total 7285874501 # number of demand (read+write) MSHR miss cycles
236 system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2241000 # number of overall MSHR miss cycles
237 system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles
238 system.l2c.overall_mshr_miss_latency::cpu.inst 682427500 # number of overall MSHR miss cycles
239 system.l2c.overall_mshr_miss_latency::cpu.data 6600966001 # number of overall MSHR miss cycles
240 system.l2c.overall_mshr_miss_latency::total 7285874501 # number of overall MSHR miss cycles
241 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192209064 # number of ReadReq MSHR uncacheable cycles
242 system.l2c.ReadReq_mshr_uncacheable_latency::total 59192209064 # number of ReadReq MSHR uncacheable cycles
243 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211526000 # number of WriteReq MSHR uncacheable cycles
244 system.l2c.WriteReq_mshr_uncacheable_latency::total 1211526000 # number of WriteReq MSHR uncacheable cycles
245 system.l2c.overall_mshr_uncacheable_latency::cpu.data 60403735064 # number of overall MSHR uncacheable cycles
246 system.l2c.overall_mshr_uncacheable_latency::total 60403735064 # number of overall MSHR uncacheable cycles
247 system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses
248 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for ReadReq accesses
249 system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for ReadReq accesses
250 system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
251 system.l2c.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses
252 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818133 # mshr miss rate for UpgradeReq accesses
253 system.l2c.UpgradeReq_mshr_miss_rate::total 0.818133 # mshr miss rate for UpgradeReq accesses
254 system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.439970 # mshr miss rate for ReadExReq accesses
255 system.l2c.ReadExReq_mshr_miss_rate::total 0.439970 # mshr miss rate for ReadExReq accesses
256 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses
257 system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for demand accesses
258 system.l2c.demand_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for demand accesses
259 system.l2c.demand_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for demand accesses
260 system.l2c.demand_mshr_miss_rate::total 0.063075 # mshr miss rate for demand accesses
261 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses
262 system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for overall accesses
263 system.l2c.overall_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for overall accesses
264 system.l2c.overall_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for overall accesses
265 system.l2c.overall_mshr_miss_rate::total 0.063075 # mshr miss rate for overall accesses
266 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average ReadReq mshr miss latency
267 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
268 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275 # average ReadReq mshr miss latency
269 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752 # average ReadReq mshr miss latency
270 system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201 # average ReadReq mshr miss latency
271 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900 # average UpgradeReq mshr miss latency
272 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900 # average UpgradeReq mshr miss latency
273 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458 # average ReadExReq mshr miss latency
274 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458 # average ReadExReq mshr miss latency
275 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency
276 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
277 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency
278 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency
279 system.l2c.demand_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency
280 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency
281 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
282 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency
283 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency
284 system.l2c.overall_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency
285 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
286 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
287 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
288 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
289 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
290 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
291 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
292 system.iocache.replacements 47565 # number of replacements
293 system.iocache.tagsinuse 0.200108 # Cycle average of tags in use
294 system.iocache.total_refs 0 # Total number of references to valid blocks.
295 system.iocache.sampled_refs 47581 # Sample count of references to valid blocks.
296 system.iocache.avg_refs 0 # Average number of references to valid blocks.
297 system.iocache.warmup_cycle 5000599162000 # Cycle when the warmup percentage was hit.
298 system.iocache.occ_blocks::pc.south_bridge.ide 0.200108 # Average occupied blocks per requestor
299 system.iocache.occ_percent::pc.south_bridge.ide 0.012507 # Average percentage of cache occupancy
300 system.iocache.occ_percent::total 0.012507 # Average percentage of cache occupancy
301 system.iocache.ReadReq_misses::pc.south_bridge.ide 900 # number of ReadReq misses
302 system.iocache.ReadReq_misses::total 900 # number of ReadReq misses
303 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
304 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
305 system.iocache.demand_misses::pc.south_bridge.ide 47620 # number of demand (read+write) misses
306 system.iocache.demand_misses::total 47620 # number of demand (read+write) misses
307 system.iocache.overall_misses::pc.south_bridge.ide 47620 # number of overall misses
308 system.iocache.overall_misses::total 47620 # number of overall misses
309 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135466932 # number of ReadReq miss cycles
310 system.iocache.ReadReq_miss_latency::total 135466932 # number of ReadReq miss cycles
311 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6926961160 # number of WriteReq miss cycles
312 system.iocache.WriteReq_miss_latency::total 6926961160 # number of WriteReq miss cycles
313 system.iocache.demand_miss_latency::pc.south_bridge.ide 7062428092 # number of demand (read+write) miss cycles
314 system.iocache.demand_miss_latency::total 7062428092 # number of demand (read+write) miss cycles
315 system.iocache.overall_miss_latency::pc.south_bridge.ide 7062428092 # number of overall miss cycles
316 system.iocache.overall_miss_latency::total 7062428092 # number of overall miss cycles
317 system.iocache.ReadReq_accesses::pc.south_bridge.ide 900 # number of ReadReq accesses(hits+misses)
318 system.iocache.ReadReq_accesses::total 900 # number of ReadReq accesses(hits+misses)
319 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
320 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
321 system.iocache.demand_accesses::pc.south_bridge.ide 47620 # number of demand (read+write) accesses
322 system.iocache.demand_accesses::total 47620 # number of demand (read+write) accesses
323 system.iocache.overall_accesses::pc.south_bridge.ide 47620 # number of overall (read+write) accesses
324 system.iocache.overall_accesses::total 47620 # number of overall (read+write) accesses
325 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
326 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
327 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
328 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
329 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
330 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
331 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
332 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
333 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333 # average ReadReq miss latency
334 system.iocache.ReadReq_avg_miss_latency::total 150518.813333 # average ReadReq miss latency
335 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788 # average WriteReq miss latency
336 system.iocache.WriteReq_avg_miss_latency::total 148265.435788 # average WriteReq miss latency
337 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency
338 system.iocache.demand_avg_miss_latency::total 148308.023772 # average overall miss latency
339 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency
340 system.iocache.overall_avg_miss_latency::total 148308.023772 # average overall miss latency
341 system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked
342 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
343 system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked
344 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
345 system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked
346 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
347 system.iocache.fast_writes 0 # number of fast writes performed
348 system.iocache.cache_copies 0 # number of cache copies performed
349 system.iocache.writebacks::writebacks 46667 # number of writebacks
350 system.iocache.writebacks::total 46667 # number of writebacks
351 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 900 # number of ReadReq MSHR misses
352 system.iocache.ReadReq_mshr_misses::total 900 # number of ReadReq MSHR misses
353 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
354 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
355 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47620 # number of demand (read+write) MSHR misses
356 system.iocache.demand_mshr_misses::total 47620 # number of demand (read+write) MSHR misses
357 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47620 # number of overall MSHR misses
358 system.iocache.overall_mshr_misses::total 47620 # number of overall MSHR misses
359 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88635000 # number of ReadReq MSHR miss cycles
360 system.iocache.ReadReq_mshr_miss_latency::total 88635000 # number of ReadReq MSHR miss cycles
361 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4497207944 # number of WriteReq MSHR miss cycles
362 system.iocache.WriteReq_mshr_miss_latency::total 4497207944 # number of WriteReq MSHR miss cycles
363 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of demand (read+write) MSHR miss cycles
364 system.iocache.demand_mshr_miss_latency::total 4585842944 # number of demand (read+write) MSHR miss cycles
365 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of overall MSHR miss cycles
366 system.iocache.overall_mshr_miss_latency::total 4585842944 # number of overall MSHR miss cycles
367 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
368 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
369 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
370 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
371 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
372 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
373 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
374 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
375 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333 # average ReadReq mshr miss latency
376 system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333 # average ReadReq mshr miss latency
377 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678 # average WriteReq mshr miss latency
378 system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678 # average WriteReq mshr miss latency
379 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency
380 system.iocache.demand_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency
381 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency
382 system.iocache.overall_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency
383 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
384 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
385 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
386 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
387 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
388 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
389 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
390 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
391 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
392 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
393 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
394 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
395 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
396 system.cpu.numCycles 472946175 # number of cpu cycles simulated
397 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
398 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
399 system.cpu.BPredUnit.lookups 90027772 # Number of BP lookups
400 system.cpu.BPredUnit.condPredicted 90027772 # Number of conditional branches predicted
401 system.cpu.BPredUnit.condIncorrect 1176455 # Number of conditional branches incorrect
402 system.cpu.BPredUnit.BTBLookups 84282590 # Number of BTB lookups
403 system.cpu.BPredUnit.BTBHits 81704922 # Number of BTB hits
404 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
405 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
406 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
407 system.cpu.fetch.icacheStallCycles 31264026 # Number of cycles fetch is stalled on an Icache miss
408 system.cpu.fetch.Insts 446943348 # Number of instructions fetch has processed
409 system.cpu.fetch.Branches 90027772 # Number of branches that fetch encountered
410 system.cpu.fetch.predictedBranches 81704922 # Number of branches that fetch has predicted taken
411 system.cpu.fetch.Cycles 169792009 # Number of cycles fetch has run and was not squashing or blocked
412 system.cpu.fetch.SquashCycles 5327046 # Number of cycles fetch has spent squashing
413 system.cpu.fetch.TlbCycles 167003 # Number of cycles fetch has spent waiting for tlb
414 system.cpu.fetch.BlockedCycles 104616235 # Number of cycles fetch has spent blocked
415 system.cpu.fetch.MiscStallCycles 37821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416 system.cpu.fetch.PendingTrapStallCycles 45804 # Number of stall cycles due to pending traps
417 system.cpu.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR
418 system.cpu.fetch.CacheLines 9365381 # Number of cache lines fetched
419 system.cpu.fetch.IcacheSquashes 539972 # Number of outstanding Icache misses that were squashed
420 system.cpu.fetch.ItlbSquashes 5058 # Number of outstanding ITLB misses that were squashed
421 system.cpu.fetch.rateDist::samples 310035010 # Number of instructions fetched each cycle (Total)
422 system.cpu.fetch.rateDist::mean 2.836765 # Number of instructions fetched each cycle (Total)
423 system.cpu.fetch.rateDist::stdev 3.376817 # Number of instructions fetched each cycle (Total)
424 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
425 system.cpu.fetch.rateDist::0 140677603 45.37% 45.37% # Number of instructions fetched each cycle (Total)
426 system.cpu.fetch.rateDist::1 1773611 0.57% 45.95% # Number of instructions fetched each cycle (Total)
427 system.cpu.fetch.rateDist::2 72784877 23.48% 69.42% # Number of instructions fetched each cycle (Total)
428 system.cpu.fetch.rateDist::3 988899 0.32% 69.74% # Number of instructions fetched each cycle (Total)
429 system.cpu.fetch.rateDist::4 1639325 0.53% 70.27% # Number of instructions fetched each cycle (Total)
430 system.cpu.fetch.rateDist::5 3670845 1.18% 71.45% # Number of instructions fetched each cycle (Total)
431 system.cpu.fetch.rateDist::6 1138945 0.37% 71.82% # Number of instructions fetched each cycle (Total)
432 system.cpu.fetch.rateDist::7 1446155 0.47% 72.29% # Number of instructions fetched each cycle (Total)
433 system.cpu.fetch.rateDist::8 85914750 27.71% 100.00% # Number of instructions fetched each cycle (Total)
434 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
435 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
436 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
437 system.cpu.fetch.rateDist::total 310035010 # Number of instructions fetched each cycle (Total)
438 system.cpu.fetch.branchRate 0.190355 # Number of branch fetches per cycle
439 system.cpu.fetch.rate 0.945019 # Number of inst fetches per cycle
440 system.cpu.decode.IdleCycles 36438516 # Number of cycles decode is idle
441 system.cpu.decode.BlockedCycles 100672732 # Number of cycles decode is blocked
442 system.cpu.decode.RunCycles 164105371 # Number of cycles decode is running
443 system.cpu.decode.UnblockCycles 4706760 # Number of cycles decode is unblocking
444 system.cpu.decode.SquashCycles 4111631 # Number of cycles decode is squashing
445 system.cpu.decode.DecodedInsts 876235114 # Number of instructions handled by decode
446 system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode
447 system.cpu.rename.SquashCycles 4111631 # Number of cycles rename is squashing
448 system.cpu.rename.IdleCycles 40855551 # Number of cycles rename is idle
449 system.cpu.rename.BlockCycles 44279722 # Number of cycles rename is blocking
450 system.cpu.rename.serializeStallCycles 10981847 # count of cycles rename stalled for serializing inst
451 system.cpu.rename.RunCycles 163785428 # Number of cycles rename is running
452 system.cpu.rename.UnblockCycles 46020831 # Number of cycles rename is unblocking
453 system.cpu.rename.RenamedInsts 872430616 # Number of instructions processed by rename
454 system.cpu.rename.ROBFullEvents 10252 # Number of times rename has blocked due to ROB full
455 system.cpu.rename.IQFullEvents 35253394 # Number of times rename has blocked due to IQ full
456 system.cpu.rename.LSQFullEvents 3952381 # Number of times rename has blocked due to LSQ full
457 system.cpu.rename.FullRegisterEvents 31994944 # Number of times there has been no free registers
458 system.cpu.rename.RenamedOperands 1394146617 # Number of destination operands rename has renamed
459 system.cpu.rename.RenameLookups 2488353855 # Number of register rename lookups that rename has made
460 system.cpu.rename.int_rename_lookups 2488353319 # Number of integer rename lookups
461 system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
462 system.cpu.rename.CommittedMaps 1347546781 # Number of HB maps that are committed
463 system.cpu.rename.UndoneMaps 46599829 # Number of HB maps that are undone due to squashing
464 system.cpu.rename.serializingInsts 470336 # count of serializing insts renamed
465 system.cpu.rename.tempSerializingInsts 478135 # count of temporary serializing insts renamed
466 system.cpu.rename.skidInsts 48126988 # count of insts added to the skid buffer
467 system.cpu.memDep0.insertedLoads 18909339 # Number of loads inserted to the mem dependence unit.
468 system.cpu.memDep0.insertedStores 10455877 # Number of stores inserted to the mem dependence unit.
469 system.cpu.memDep0.conflictingLoads 1294020 # Number of conflicting loads.
470 system.cpu.memDep0.conflictingStores 1017517 # Number of conflicting stores.
471 system.cpu.iq.iqInstsAdded 865756561 # Number of instructions added to the IQ (excludes non-spec)
472 system.cpu.iq.iqNonSpecInstsAdded 1721302 # Number of non-speculative instructions added to the IQ
473 system.cpu.iq.iqInstsIssued 864328719 # Number of instructions issued
474 system.cpu.iq.iqSquashedInstsIssued 124616 # Number of squashed instructions issued
475 system.cpu.iq.iqSquashedInstsExamined 26046990 # Number of squashed instructions iterated over during squash; mainly for profiling
476 system.cpu.iq.iqSquashedOperandsExamined 53600910 # Number of squashed operands that are examined and possibly removed from graph
477 system.cpu.iq.iqSquashedNonSpecRemoved 205527 # Number of squashed non-spec instructions that were removed
478 system.cpu.iq.issued_per_cycle::samples 310035010 # Number of insts issued each cycle
479 system.cpu.iq.issued_per_cycle::mean 2.787842 # Number of insts issued each cycle
480 system.cpu.iq.issued_per_cycle::stdev 2.396151 # Number of insts issued each cycle
481 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
482 system.cpu.iq.issued_per_cycle::0 102334281 33.01% 33.01% # Number of insts issued each cycle
483 system.cpu.iq.issued_per_cycle::1 23751530 7.66% 40.67% # Number of insts issued each cycle
484 system.cpu.iq.issued_per_cycle::2 19011662 6.13% 46.80% # Number of insts issued each cycle
485 system.cpu.iq.issued_per_cycle::3 7830278 2.53% 49.33% # Number of insts issued each cycle
486 system.cpu.iq.issued_per_cycle::4 80611792 26.00% 75.33% # Number of insts issued each cycle
487 system.cpu.iq.issued_per_cycle::5 3104970 1.00% 76.33% # Number of insts issued each cycle
488 system.cpu.iq.issued_per_cycle::6 72755101 23.47% 99.80% # Number of insts issued each cycle
489 system.cpu.iq.issued_per_cycle::7 522761 0.17% 99.96% # Number of insts issued each cycle
490 system.cpu.iq.issued_per_cycle::8 112635 0.04% 100.00% # Number of insts issued each cycle
491 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
492 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
493 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
494 system.cpu.iq.issued_per_cycle::total 310035010 # Number of insts issued each cycle
495 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
496 system.cpu.iq.fu_full::IntAlu 164564 7.88% 7.88% # attempts to use FU when none available
497 system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available
498 system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available
499 system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available
500 system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.88% # attempts to use FU when none available
501 system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.88% # attempts to use FU when none available
502 system.cpu.iq.fu_full::FloatMult 0 0.00% 7.88% # attempts to use FU when none available
503 system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.88% # attempts to use FU when none available
504 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.88% # attempts to use FU when none available
505 system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.88% # attempts to use FU when none available
506 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.88% # attempts to use FU when none available
507 system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.88% # attempts to use FU when none available
508 system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.88% # attempts to use FU when none available
509 system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.88% # attempts to use FU when none available
510 system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.88% # attempts to use FU when none available
511 system.cpu.iq.fu_full::SimdMult 0 0.00% 7.88% # attempts to use FU when none available
512 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.88% # attempts to use FU when none available
513 system.cpu.iq.fu_full::SimdShift 0 0.00% 7.88% # attempts to use FU when none available
514 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.88% # attempts to use FU when none available
515 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.88% # attempts to use FU when none available
516 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.88% # attempts to use FU when none available
517 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.88% # attempts to use FU when none available
518 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.88% # attempts to use FU when none available
519 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.88% # attempts to use FU when none available
520 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.88% # attempts to use FU when none available
521 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # attempts to use FU when none available
522 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available
523 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available
524 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available
525 system.cpu.iq.fu_full::MemRead 1763434 84.48% 92.37% # attempts to use FU when none available
526 system.cpu.iq.fu_full::MemWrite 159280 7.63% 100.00% # attempts to use FU when none available
527 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
528 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
529 system.cpu.iq.FU_type_0::No_OpClass 297202 0.03% 0.03% # Type of FU issued
530 system.cpu.iq.FU_type_0::IntAlu 829439322 95.96% 96.00% # Type of FU issued
531 system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued
532 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued
533 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued
534 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued
535 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued
536 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued
537 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued
538 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued
539 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued
540 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued
541 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued
542 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued
543 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued
544 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued
545 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued
546 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued
547 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued
548 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued
549 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued
550 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued
551 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued
552 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued
553 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued
554 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued
555 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued
556 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued
557 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued
558 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued
559 system.cpu.iq.FU_type_0::MemRead 25154463 2.91% 98.91% # Type of FU issued
560 system.cpu.iq.FU_type_0::MemWrite 9437732 1.09% 100.00% # Type of FU issued
561 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
562 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
563 system.cpu.iq.FU_type_0::total 864328719 # Type of FU issued
564 system.cpu.iq.rate 1.827541 # Inst issue rate
565 system.cpu.iq.fu_busy_cnt 2087278 # FU busy when requested
566 system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst)
567 system.cpu.iq.int_inst_queue_reads 2041042185 # Number of integer instruction queue reads
568 system.cpu.iq.int_inst_queue_writes 893535851 # Number of integer instruction queue writes
569 system.cpu.iq.int_inst_queue_wakeup_accesses 853927067 # Number of integer instruction queue wakeup accesses
570 system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads
571 system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes
572 system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
573 system.cpu.iq.int_alu_accesses 866118699 # Number of integer alu accesses
574 system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses
575 system.cpu.iew.lsq.thread0.forwLoads 1579181 # Number of loads that had data forwarded from stores
576 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
577 system.cpu.iew.lsq.thread0.squashedLoads 3618734 # Number of loads squashed
578 system.cpu.iew.lsq.thread0.ignoredResponses 20083 # Number of memory responses ignored because the instruction is squashed
579 system.cpu.iew.lsq.thread0.memOrderViolation 12084 # Number of memory ordering violations
580 system.cpu.iew.lsq.thread0.squashedStores 2054359 # Number of stores squashed
581 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
582 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
583 system.cpu.iew.lsq.thread0.rescheduledLoads 7821519 # Number of loads that were rescheduled
584 system.cpu.iew.lsq.thread0.cacheBlocked 4487 # Number of times an access to memory failed due to the cache being blocked
585 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
586 system.cpu.iew.iewSquashCycles 4111631 # Number of cycles IEW is squashing
587 system.cpu.iew.iewBlockCycles 27910035 # Number of cycles IEW is blocking
588 system.cpu.iew.iewUnblockCycles 1927143 # Number of cycles IEW is unblocking
589 system.cpu.iew.iewDispatchedInsts 867477863 # Number of instructions dispatched to IQ
590 system.cpu.iew.iewDispSquashedInsts 297836 # Number of squashed instructions skipped by dispatch
591 system.cpu.iew.iewDispLoadInsts 18909339 # Number of dispatched load instructions
592 system.cpu.iew.iewDispStoreInsts 10455877 # Number of dispatched store instructions
593 system.cpu.iew.iewDispNonSpecInsts 883178 # Number of dispatched non-speculative instructions
594 system.cpu.iew.iewIQFullEvents 975186 # Number of times the IQ has become full, causing a stall
595 system.cpu.iew.iewLSQFullEvents 15536 # Number of times the LSQ has become full, causing a stall
596 system.cpu.iew.memOrderViolationEvents 12084 # Number of memory order violations
597 system.cpu.iew.predictedTakenIncorrect 697834 # Number of branches that were predicted taken incorrectly
598 system.cpu.iew.predictedNotTakenIncorrect 626380 # Number of branches that were predicted not taken incorrectly
599 system.cpu.iew.branchMispredicts 1324214 # Number of branch mispredicts detected at execute
600 system.cpu.iew.iewExecutedInsts 862437508 # Number of executed instructions
601 system.cpu.iew.iewExecLoadInsts 24726867 # Number of load instructions executed
602 system.cpu.iew.iewExecSquashedInsts 1891210 # Number of squashed instructions skipped in execute
603 system.cpu.iew.exec_swp 0 # number of swp insts executed
604 system.cpu.iew.exec_nop 0 # number of nop insts executed
605 system.cpu.iew.exec_refs 33920253 # number of memory reference insts executed
606 system.cpu.iew.exec_branches 86495383 # Number of branches executed
607 system.cpu.iew.exec_stores 9193386 # Number of stores executed
608 system.cpu.iew.exec_rate 1.823543 # Inst execution rate
609 system.cpu.iew.wb_sent 861952908 # cumulative count of insts sent to commit
610 system.cpu.iew.wb_count 853927121 # cumulative count of insts written-back
611 system.cpu.iew.wb_producers 669642895 # num instructions producing a value
612 system.cpu.iew.wb_consumers 1918737755 # num instructions consuming a value
613 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
614 system.cpu.iew.wb_rate 1.805548 # insts written-back per cycle
615 system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back
616 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
617 system.cpu.commit.commitCommittedInsts 426515724 # The number of committed instructions
618 system.cpu.commit.commitCommittedOps 840516219 # The number of committed instructions
619 system.cpu.commit.commitSquashedInsts 26857823 # The number of squashed insts skipped by commit
620 system.cpu.commit.commitNonSpecStalls 1515773 # The number of times commit has been forced to stall to communicate backwards
621 system.cpu.commit.branchMispredicts 1181578 # The number of times a branch was mispredicted
622 system.cpu.commit.committed_per_cycle::samples 305938932 # Number of insts commited each cycle
623 system.cpu.commit.committed_per_cycle::mean 2.747333 # Number of insts commited each cycle
624 system.cpu.commit.committed_per_cycle::stdev 2.861326 # Number of insts commited each cycle
625 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
626 system.cpu.commit.committed_per_cycle::0 125006118 40.86% 40.86% # Number of insts commited each cycle
627 system.cpu.commit.committed_per_cycle::1 14720749 4.81% 45.67% # Number of insts commited each cycle
628 system.cpu.commit.committed_per_cycle::2 4254060 1.39% 47.06% # Number of insts commited each cycle
629 system.cpu.commit.committed_per_cycle::3 76641454 25.05% 72.11% # Number of insts commited each cycle
630 system.cpu.commit.committed_per_cycle::4 3896789 1.27% 73.39% # Number of insts commited each cycle
631 system.cpu.commit.committed_per_cycle::5 1794252 0.59% 73.97% # Number of insts commited each cycle
632 system.cpu.commit.committed_per_cycle::6 1101361 0.36% 74.33% # Number of insts commited each cycle
633 system.cpu.commit.committed_per_cycle::7 71996786 23.53% 97.87% # Number of insts commited each cycle
634 system.cpu.commit.committed_per_cycle::8 6527363 2.13% 100.00% # Number of insts commited each cycle
635 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
636 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
637 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
638 system.cpu.commit.committed_per_cycle::total 305938932 # Number of insts commited each cycle
639 system.cpu.commit.committedInsts 426515724 # Number of instructions committed
640 system.cpu.commit.committedOps 840516219 # Number of ops (including micro ops) committed
641 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
642 system.cpu.commit.refs 23692120 # Number of memory references committed
643 system.cpu.commit.loads 15290602 # Number of loads committed
644 system.cpu.commit.membars 781565 # Number of memory barriers committed
645 system.cpu.commit.branches 85505775 # Number of branches committed
646 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
647 system.cpu.commit.int_insts 768334838 # Number of committed integer instructions.
648 system.cpu.commit.function_calls 0 # Number of function calls committed.
649 system.cpu.commit.bw_lim_events 6527363 # number cycles where commit BW limit reached
650 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
651 system.cpu.rob.rob_reads 1166706140 # The number of ROB reads
652 system.cpu.rob.rob_writes 1738874776 # The number of ROB writes
653 system.cpu.timesIdled 2996123 # Number of times that the entire CPU went into an idle state and unscheduled itself
654 system.cpu.idleCycles 162911165 # Total number of cycles that the CPU has spent unscheduled due to idling
655 system.cpu.quiesceCycles 9872855838 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
656 system.cpu.committedInsts 426515724 # Number of Instructions Simulated
657 system.cpu.committedOps 840516219 # Number of Ops (including micro ops) Simulated
658 system.cpu.committedInsts_total 426515724 # Number of Instructions Simulated
659 system.cpu.cpi 1.108860 # CPI: Cycles Per Instruction
660 system.cpu.cpi_total 1.108860 # CPI: Total CPI of All Threads
661 system.cpu.ipc 0.901827 # IPC: Instructions Per Cycle
662 system.cpu.ipc_total 0.901827 # IPC: Total IPC of All Threads
663 system.cpu.int_regfile_reads 2163141042 # number of integer regfile reads
664 system.cpu.int_regfile_writes 1362663536 # number of integer regfile writes
665 system.cpu.fp_regfile_reads 54 # number of floating regfile reads
666 system.cpu.misc_regfile_reads 281062978 # number of misc regfile reads
667 system.cpu.misc_regfile_writes 403820 # number of misc regfile writes
668 system.cpu.icache.replacements 1070658 # number of replacements
669 system.cpu.icache.tagsinuse 510.425099 # Cycle average of tags in use
670 system.cpu.icache.total_refs 8224431 # Total number of references to valid blocks.
671 system.cpu.icache.sampled_refs 1071170 # Sample count of references to valid blocks.
672 system.cpu.icache.avg_refs 7.677989 # Average number of references to valid blocks.
673 system.cpu.icache.warmup_cycle 56932899000 # Cycle when the warmup percentage was hit.
674 system.cpu.icache.occ_blocks::cpu.inst 510.425099 # Average occupied blocks per requestor
675 system.cpu.icache.occ_percent::cpu.inst 0.996924 # Average percentage of cache occupancy
676 system.cpu.icache.occ_percent::total 0.996924 # Average percentage of cache occupancy
677 system.cpu.icache.ReadReq_hits::cpu.inst 8224431 # number of ReadReq hits
678 system.cpu.icache.ReadReq_hits::total 8224431 # number of ReadReq hits
679 system.cpu.icache.demand_hits::cpu.inst 8224431 # number of demand (read+write) hits
680 system.cpu.icache.demand_hits::total 8224431 # number of demand (read+write) hits
681 system.cpu.icache.overall_hits::cpu.inst 8224431 # number of overall hits
682 system.cpu.icache.overall_hits::total 8224431 # number of overall hits
683 system.cpu.icache.ReadReq_misses::cpu.inst 1140947 # number of ReadReq misses
684 system.cpu.icache.ReadReq_misses::total 1140947 # number of ReadReq misses
685 system.cpu.icache.demand_misses::cpu.inst 1140947 # number of demand (read+write) misses
686 system.cpu.icache.demand_misses::total 1140947 # number of demand (read+write) misses
687 system.cpu.icache.overall_misses::cpu.inst 1140947 # number of overall misses
688 system.cpu.icache.overall_misses::total 1140947 # number of overall misses
689 system.cpu.icache.ReadReq_miss_latency::cpu.inst 18841256486 # number of ReadReq miss cycles
690 system.cpu.icache.ReadReq_miss_latency::total 18841256486 # number of ReadReq miss cycles
691 system.cpu.icache.demand_miss_latency::cpu.inst 18841256486 # number of demand (read+write) miss cycles
692 system.cpu.icache.demand_miss_latency::total 18841256486 # number of demand (read+write) miss cycles
693 system.cpu.icache.overall_miss_latency::cpu.inst 18841256486 # number of overall miss cycles
694 system.cpu.icache.overall_miss_latency::total 18841256486 # number of overall miss cycles
695 system.cpu.icache.ReadReq_accesses::cpu.inst 9365378 # number of ReadReq accesses(hits+misses)
696 system.cpu.icache.ReadReq_accesses::total 9365378 # number of ReadReq accesses(hits+misses)
697 system.cpu.icache.demand_accesses::cpu.inst 9365378 # number of demand (read+write) accesses
698 system.cpu.icache.demand_accesses::total 9365378 # number of demand (read+write) accesses
699 system.cpu.icache.overall_accesses::cpu.inst 9365378 # number of overall (read+write) accesses
700 system.cpu.icache.overall_accesses::total 9365378 # number of overall (read+write) accesses
701 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121826 # miss rate for ReadReq accesses
702 system.cpu.icache.ReadReq_miss_rate::total 0.121826 # miss rate for ReadReq accesses
703 system.cpu.icache.demand_miss_rate::cpu.inst 0.121826 # miss rate for demand accesses
704 system.cpu.icache.demand_miss_rate::total 0.121826 # miss rate for demand accesses
705 system.cpu.icache.overall_miss_rate::cpu.inst 0.121826 # miss rate for overall accesses
706 system.cpu.icache.overall_miss_rate::total 0.121826 # miss rate for overall accesses
707 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011 # average ReadReq miss latency
708 system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011 # average ReadReq miss latency
709 system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency
710 system.cpu.icache.demand_avg_miss_latency::total 16513.700011 # average overall miss latency
711 system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency
712 system.cpu.icache.overall_avg_miss_latency::total 16513.700011 # average overall miss latency
713 system.cpu.icache.blocked_cycles::no_mshrs 3271992 # number of cycles access was blocked
714 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
715 system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked
716 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
717 system.cpu.icache.avg_blocked_cycles::no_mshrs 8200.481203 # average number of cycles each access was blocked
718 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
719 system.cpu.icache.fast_writes 0 # number of fast writes performed
720 system.cpu.icache.cache_copies 0 # number of cache copies performed
721 system.cpu.icache.writebacks::writebacks 1605 # number of writebacks
722 system.cpu.icache.writebacks::total 1605 # number of writebacks
723 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69655 # number of ReadReq MSHR hits
724 system.cpu.icache.ReadReq_mshr_hits::total 69655 # number of ReadReq MSHR hits
725 system.cpu.icache.demand_mshr_hits::cpu.inst 69655 # number of demand (read+write) MSHR hits
726 system.cpu.icache.demand_mshr_hits::total 69655 # number of demand (read+write) MSHR hits
727 system.cpu.icache.overall_mshr_hits::cpu.inst 69655 # number of overall MSHR hits
728 system.cpu.icache.overall_mshr_hits::total 69655 # number of overall MSHR hits
729 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071292 # number of ReadReq MSHR misses
730 system.cpu.icache.ReadReq_mshr_misses::total 1071292 # number of ReadReq MSHR misses
731 system.cpu.icache.demand_mshr_misses::cpu.inst 1071292 # number of demand (read+write) MSHR misses
732 system.cpu.icache.demand_mshr_misses::total 1071292 # number of demand (read+write) MSHR misses
733 system.cpu.icache.overall_mshr_misses::cpu.inst 1071292 # number of overall MSHR misses
734 system.cpu.icache.overall_mshr_misses::total 1071292 # number of overall MSHR misses
735 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14719464992 # number of ReadReq MSHR miss cycles
736 system.cpu.icache.ReadReq_mshr_miss_latency::total 14719464992 # number of ReadReq MSHR miss cycles
737 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14719464992 # number of demand (read+write) MSHR miss cycles
738 system.cpu.icache.demand_mshr_miss_latency::total 14719464992 # number of demand (read+write) MSHR miss cycles
739 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14719464992 # number of overall MSHR miss cycles
740 system.cpu.icache.overall_mshr_miss_latency::total 14719464992 # number of overall MSHR miss cycles
741 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for ReadReq accesses
742 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114389 # mshr miss rate for ReadReq accesses
743 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for demand accesses
744 system.cpu.icache.demand_mshr_miss_rate::total 0.114389 # mshr miss rate for demand accesses
745 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for overall accesses
746 system.cpu.icache.overall_mshr_miss_rate::total 0.114389 # mshr miss rate for overall accesses
747 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708 # average ReadReq mshr miss latency
748 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708 # average ReadReq mshr miss latency
749 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency
750 system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency
751 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency
752 system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency
753 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
754 system.cpu.itb_walker_cache.replacements 10504 # number of replacements
755 system.cpu.itb_walker_cache.tagsinuse 6.031363 # Cycle average of tags in use
756 system.cpu.itb_walker_cache.total_refs 31807 # Total number of references to valid blocks.
757 system.cpu.itb_walker_cache.sampled_refs 10516 # Sample count of references to valid blocks.
758 system.cpu.itb_walker_cache.avg_refs 3.024629 # Average number of references to valid blocks.
759 system.cpu.itb_walker_cache.warmup_cycle 5135227037000 # Cycle when the warmup percentage was hit.
760 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.031363 # Average occupied blocks per requestor
761 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376960 # Average percentage of cache occupancy
762 system.cpu.itb_walker_cache.occ_percent::total 0.376960 # Average percentage of cache occupancy
763 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31848 # number of ReadReq hits
764 system.cpu.itb_walker_cache.ReadReq_hits::total 31848 # number of ReadReq hits
765 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
766 system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
767 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31851 # number of demand (read+write) hits
768 system.cpu.itb_walker_cache.demand_hits::total 31851 # number of demand (read+write) hits
769 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31851 # number of overall hits
770 system.cpu.itb_walker_cache.overall_hits::total 31851 # number of overall hits
771 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11386 # number of ReadReq misses
772 system.cpu.itb_walker_cache.ReadReq_misses::total 11386 # number of ReadReq misses
773 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11386 # number of demand (read+write) misses
774 system.cpu.itb_walker_cache.demand_misses::total 11386 # number of demand (read+write) misses
775 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11386 # number of overall misses
776 system.cpu.itb_walker_cache.overall_misses::total 11386 # number of overall misses
777 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 182254500 # number of ReadReq miss cycles
778 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 182254500 # number of ReadReq miss cycles
779 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 182254500 # number of demand (read+write) miss cycles
780 system.cpu.itb_walker_cache.demand_miss_latency::total 182254500 # number of demand (read+write) miss cycles
781 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 182254500 # number of overall miss cycles
782 system.cpu.itb_walker_cache.overall_miss_latency::total 182254500 # number of overall miss cycles
783 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43234 # number of ReadReq accesses(hits+misses)
784 system.cpu.itb_walker_cache.ReadReq_accesses::total 43234 # number of ReadReq accesses(hits+misses)
785 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
786 system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
787 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43237 # number of demand (read+write) accesses
788 system.cpu.itb_walker_cache.demand_accesses::total 43237 # number of demand (read+write) accesses
789 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43237 # number of overall (read+write) accesses
790 system.cpu.itb_walker_cache.overall_accesses::total 43237 # number of overall (read+write) accesses
791 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.263358 # miss rate for ReadReq accesses
792 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.263358 # miss rate for ReadReq accesses
793 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.263339 # miss rate for demand accesses
794 system.cpu.itb_walker_cache.demand_miss_rate::total 0.263339 # miss rate for demand accesses
795 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.263339 # miss rate for overall accesses
796 system.cpu.itb_walker_cache.overall_miss_rate::total 0.263339 # miss rate for overall accesses
797 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432 # average ReadReq miss latency
798 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432 # average ReadReq miss latency
799 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency
800 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432 # average overall miss latency
801 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency
802 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432 # average overall miss latency
803 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
804 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
805 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
806 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
807 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
808 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
809 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
810 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
811 system.cpu.itb_walker_cache.writebacks::writebacks 1641 # number of writebacks
812 system.cpu.itb_walker_cache.writebacks::total 1641 # number of writebacks
813 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11386 # number of ReadReq MSHR misses
814 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11386 # number of ReadReq MSHR misses
815 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11386 # number of demand (read+write) MSHR misses
816 system.cpu.itb_walker_cache.demand_mshr_misses::total 11386 # number of demand (read+write) MSHR misses
817 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11386 # number of overall MSHR misses
818 system.cpu.itb_walker_cache.overall_mshr_misses::total 11386 # number of overall MSHR misses
819 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147453030 # number of ReadReq MSHR miss cycles
820 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147453030 # number of ReadReq MSHR miss cycles
821 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147453030 # number of demand (read+write) MSHR miss cycles
822 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147453030 # number of demand (read+write) MSHR miss cycles
823 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147453030 # number of overall MSHR miss cycles
824 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147453030 # number of overall MSHR miss cycles
825 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.263358 # mshr miss rate for ReadReq accesses
826 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.263358 # mshr miss rate for ReadReq accesses
827 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for demand accesses
828 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.263339 # mshr miss rate for demand accesses
829 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for overall accesses
830 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.263339 # mshr miss rate for overall accesses
831 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average ReadReq mshr miss latency
832 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292 # average ReadReq mshr miss latency
833 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency
834 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency
835 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency
836 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency
837 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
838 system.cpu.dtb_walker_cache.replacements 117278 # number of replacements
839 system.cpu.dtb_walker_cache.tagsinuse 13.523999 # Cycle average of tags in use
840 system.cpu.dtb_walker_cache.total_refs 136775 # Total number of references to valid blocks.
841 system.cpu.dtb_walker_cache.sampled_refs 117293 # Sample count of references to valid blocks.
842 system.cpu.dtb_walker_cache.avg_refs 1.166097 # Average number of references to valid blocks.
843 system.cpu.dtb_walker_cache.warmup_cycle 5112876101000 # Cycle when the warmup percentage was hit.
844 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.523999 # Average occupied blocks per requestor
845 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.845250 # Average percentage of cache occupancy
846 system.cpu.dtb_walker_cache.occ_percent::total 0.845250 # Average percentage of cache occupancy
847 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 136779 # number of ReadReq hits
848 system.cpu.dtb_walker_cache.ReadReq_hits::total 136779 # number of ReadReq hits
849 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 136779 # number of demand (read+write) hits
850 system.cpu.dtb_walker_cache.demand_hits::total 136779 # number of demand (read+write) hits
851 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 136779 # number of overall hits
852 system.cpu.dtb_walker_cache.overall_hits::total 136779 # number of overall hits
853 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118304 # number of ReadReq misses
854 system.cpu.dtb_walker_cache.ReadReq_misses::total 118304 # number of ReadReq misses
855 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118304 # number of demand (read+write) misses
856 system.cpu.dtb_walker_cache.demand_misses::total 118304 # number of demand (read+write) misses
857 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118304 # number of overall misses
858 system.cpu.dtb_walker_cache.overall_misses::total 118304 # number of overall misses
859 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2123660000 # number of ReadReq miss cycles
860 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2123660000 # number of ReadReq miss cycles
861 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2123660000 # number of demand (read+write) miss cycles
862 system.cpu.dtb_walker_cache.demand_miss_latency::total 2123660000 # number of demand (read+write) miss cycles
863 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2123660000 # number of overall miss cycles
864 system.cpu.dtb_walker_cache.overall_miss_latency::total 2123660000 # number of overall miss cycles
865 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255083 # number of ReadReq accesses(hits+misses)
866 system.cpu.dtb_walker_cache.ReadReq_accesses::total 255083 # number of ReadReq accesses(hits+misses)
867 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255083 # number of demand (read+write) accesses
868 system.cpu.dtb_walker_cache.demand_accesses::total 255083 # number of demand (read+write) accesses
869 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255083 # number of overall (read+write) accesses
870 system.cpu.dtb_walker_cache.overall_accesses::total 255083 # number of overall (read+write) accesses
871 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463786 # miss rate for ReadReq accesses
872 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463786 # miss rate for ReadReq accesses
873 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463786 # miss rate for demand accesses
874 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463786 # miss rate for demand accesses
875 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463786 # miss rate for overall accesses
876 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463786 # miss rate for overall accesses
877 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329 # average ReadReq miss latency
878 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329 # average ReadReq miss latency
879 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency
880 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329 # average overall miss latency
881 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency
882 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329 # average overall miss latency
883 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
884 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
885 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
886 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
887 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
888 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
889 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
890 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
891 system.cpu.dtb_walker_cache.writebacks::writebacks 37674 # number of writebacks
892 system.cpu.dtb_walker_cache.writebacks::total 37674 # number of writebacks
893 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118304 # number of ReadReq MSHR misses
894 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118304 # number of ReadReq MSHR misses
895 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118304 # number of demand (read+write) MSHR misses
896 system.cpu.dtb_walker_cache.demand_mshr_misses::total 118304 # number of demand (read+write) MSHR misses
897 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118304 # number of overall MSHR misses
898 system.cpu.dtb_walker_cache.overall_mshr_misses::total 118304 # number of overall MSHR misses
899 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of ReadReq MSHR miss cycles
900 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1766049009 # number of ReadReq MSHR miss cycles
901 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of demand (read+write) MSHR miss cycles
902 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1766049009 # number of demand (read+write) MSHR miss cycles
903 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of overall MSHR miss cycles
904 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1766049009 # number of overall MSHR miss cycles
905 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for ReadReq accesses
906 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463786 # mshr miss rate for ReadReq accesses
907 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for demand accesses
908 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463786 # mshr miss rate for demand accesses
909 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for overall accesses
910 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463786 # mshr miss rate for overall accesses
911 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average ReadReq mshr miss latency
912 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299 # average ReadReq mshr miss latency
913 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency
914 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency
915 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency
916 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency
917 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
918 system.cpu.dcache.replacements 1673136 # number of replacements
919 system.cpu.dcache.tagsinuse 511.997556 # Cycle average of tags in use
920 system.cpu.dcache.total_refs 19006106 # Total number of references to valid blocks.
921 system.cpu.dcache.sampled_refs 1673648 # Sample count of references to valid blocks.
922 system.cpu.dcache.avg_refs 11.356095 # Average number of references to valid blocks.
923 system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit.
924 system.cpu.dcache.occ_blocks::cpu.data 511.997556 # Average occupied blocks per requestor
925 system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
926 system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
927 system.cpu.dcache.ReadReq_hits::cpu.data 10928708 # number of ReadReq hits
928 system.cpu.dcache.ReadReq_hits::total 10928708 # number of ReadReq hits
929 system.cpu.dcache.WriteReq_hits::cpu.data 8074811 # number of WriteReq hits
930 system.cpu.dcache.WriteReq_hits::total 8074811 # number of WriteReq hits
931 system.cpu.dcache.demand_hits::cpu.data 19003519 # number of demand (read+write) hits
932 system.cpu.dcache.demand_hits::total 19003519 # number of demand (read+write) hits
933 system.cpu.dcache.overall_hits::cpu.data 19003519 # number of overall hits
934 system.cpu.dcache.overall_hits::total 19003519 # number of overall hits
935 system.cpu.dcache.ReadReq_misses::cpu.data 2430538 # number of ReadReq misses
936 system.cpu.dcache.ReadReq_misses::total 2430538 # number of ReadReq misses
937 system.cpu.dcache.WriteReq_misses::cpu.data 317333 # number of WriteReq misses
938 system.cpu.dcache.WriteReq_misses::total 317333 # number of WriteReq misses
939 system.cpu.dcache.demand_misses::cpu.data 2747871 # number of demand (read+write) misses
940 system.cpu.dcache.demand_misses::total 2747871 # number of demand (read+write) misses
941 system.cpu.dcache.overall_misses::cpu.data 2747871 # number of overall misses
942 system.cpu.dcache.overall_misses::total 2747871 # number of overall misses
943 system.cpu.dcache.ReadReq_miss_latency::cpu.data 45186101000 # number of ReadReq miss cycles
944 system.cpu.dcache.ReadReq_miss_latency::total 45186101000 # number of ReadReq miss cycles
945 system.cpu.dcache.WriteReq_miss_latency::cpu.data 10603069990 # number of WriteReq miss cycles
946 system.cpu.dcache.WriteReq_miss_latency::total 10603069990 # number of WriteReq miss cycles
947 system.cpu.dcache.demand_miss_latency::cpu.data 55789170990 # number of demand (read+write) miss cycles
948 system.cpu.dcache.demand_miss_latency::total 55789170990 # number of demand (read+write) miss cycles
949 system.cpu.dcache.overall_miss_latency::cpu.data 55789170990 # number of overall miss cycles
950 system.cpu.dcache.overall_miss_latency::total 55789170990 # number of overall miss cycles
951 system.cpu.dcache.ReadReq_accesses::cpu.data 13359246 # number of ReadReq accesses(hits+misses)
952 system.cpu.dcache.ReadReq_accesses::total 13359246 # number of ReadReq accesses(hits+misses)
953 system.cpu.dcache.WriteReq_accesses::cpu.data 8392144 # number of WriteReq accesses(hits+misses)
954 system.cpu.dcache.WriteReq_accesses::total 8392144 # number of WriteReq accesses(hits+misses)
955 system.cpu.dcache.demand_accesses::cpu.data 21751390 # number of demand (read+write) accesses
956 system.cpu.dcache.demand_accesses::total 21751390 # number of demand (read+write) accesses
957 system.cpu.dcache.overall_accesses::cpu.data 21751390 # number of overall (read+write) accesses
958 system.cpu.dcache.overall_accesses::total 21751390 # number of overall (read+write) accesses
959 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181937 # miss rate for ReadReq accesses
960 system.cpu.dcache.ReadReq_miss_rate::total 0.181937 # miss rate for ReadReq accesses
961 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses
962 system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses
963 system.cpu.dcache.demand_miss_rate::cpu.data 0.126331 # miss rate for demand accesses
964 system.cpu.dcache.demand_miss_rate::total 0.126331 # miss rate for demand accesses
965 system.cpu.dcache.overall_miss_rate::cpu.data 0.126331 # miss rate for overall accesses
966 system.cpu.dcache.overall_miss_rate::total 0.126331 # miss rate for overall accesses
967 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263 # average ReadReq miss latency
968 system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263 # average ReadReq miss latency
969 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781 # average WriteReq miss latency
970 system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781 # average WriteReq miss latency
971 system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency
972 system.cpu.dcache.demand_avg_miss_latency::total 20302.689242 # average overall miss latency
973 system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency
974 system.cpu.dcache.overall_avg_miss_latency::total 20302.689242 # average overall miss latency
975 system.cpu.dcache.blocked_cycles::no_mshrs 27875990 # number of cycles access was blocked
976 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
977 system.cpu.dcache.blocked::no_mshrs 4957 # number of cycles access was blocked
978 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
979 system.cpu.dcache.avg_blocked_cycles::no_mshrs 5623.560621 # average number of cycles each access was blocked
980 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
981 system.cpu.dcache.fast_writes 0 # number of fast writes performed
982 system.cpu.dcache.cache_copies 0 # number of cache copies performed
983 system.cpu.dcache.writebacks::writebacks 1572269 # number of writebacks
984 system.cpu.dcache.writebacks::total 1572269 # number of writebacks
985 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049151 # number of ReadReq MSHR hits
986 system.cpu.dcache.ReadReq_mshr_hits::total 1049151 # number of ReadReq MSHR hits
987 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22726 # number of WriteReq MSHR hits
988 system.cpu.dcache.WriteReq_mshr_hits::total 22726 # number of WriteReq MSHR hits
989 system.cpu.dcache.demand_mshr_hits::cpu.data 1071877 # number of demand (read+write) MSHR hits
990 system.cpu.dcache.demand_mshr_hits::total 1071877 # number of demand (read+write) MSHR hits
991 system.cpu.dcache.overall_mshr_hits::cpu.data 1071877 # number of overall MSHR hits
992 system.cpu.dcache.overall_mshr_hits::total 1071877 # number of overall MSHR hits
993 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381387 # number of ReadReq MSHR misses
994 system.cpu.dcache.ReadReq_mshr_misses::total 1381387 # number of ReadReq MSHR misses
995 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294607 # number of WriteReq MSHR misses
996 system.cpu.dcache.WriteReq_mshr_misses::total 294607 # number of WriteReq MSHR misses
997 system.cpu.dcache.demand_mshr_misses::cpu.data 1675994 # number of demand (read+write) MSHR misses
998 system.cpu.dcache.demand_mshr_misses::total 1675994 # number of demand (read+write) MSHR misses
999 system.cpu.dcache.overall_mshr_misses::cpu.data 1675994 # number of overall MSHR misses
1000 system.cpu.dcache.overall_mshr_misses::total 1675994 # number of overall MSHR misses
1001 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23290713035 # number of ReadReq MSHR miss cycles
1002 system.cpu.dcache.ReadReq_mshr_miss_latency::total 23290713035 # number of ReadReq MSHR miss cycles
1003 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9337845997 # number of WriteReq MSHR miss cycles
1004 system.cpu.dcache.WriteReq_mshr_miss_latency::total 9337845997 # number of WriteReq MSHR miss cycles
1005 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32628559032 # number of demand (read+write) MSHR miss cycles
1006 system.cpu.dcache.demand_mshr_miss_latency::total 32628559032 # number of demand (read+write) MSHR miss cycles
1007 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32628559032 # number of overall MSHR miss cycles
1008 system.cpu.dcache.overall_mshr_miss_latency::total 32628559032 # number of overall MSHR miss cycles
1009 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207723000 # number of ReadReq MSHR uncacheable cycles
1010 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207723000 # number of ReadReq MSHR uncacheable cycles
1011 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386731000 # number of WriteReq MSHR uncacheable cycles
1012 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386731000 # number of WriteReq MSHR uncacheable cycles
1013 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594454000 # number of overall MSHR uncacheable cycles
1014 system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594454000 # number of overall MSHR uncacheable cycles
1015 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103403 # mshr miss rate for ReadReq accesses
1016 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103403 # mshr miss rate for ReadReq accesses
1017 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035105 # mshr miss rate for WriteReq accesses
1018 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035105 # mshr miss rate for WriteReq accesses
1019 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for demand accesses
1020 system.cpu.dcache.demand_mshr_miss_rate::total 0.077052 # mshr miss rate for demand accesses
1021 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for overall accesses
1022 system.cpu.dcache.overall_mshr_miss_rate::total 0.077052 # mshr miss rate for overall accesses
1023 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380 # average ReadReq mshr miss latency
1024 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380 # average ReadReq mshr miss latency
1025 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684 # average WriteReq mshr miss latency
1026 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684 # average WriteReq mshr miss latency
1027 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency
1028 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency
1029 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency
1030 system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency
1031 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1032 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1033 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1034 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1035 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1036 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1037 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1038 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1039 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1041 ---------- End Simulation Statistics ----------
projects / gem5.git / blob