2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.163317 # Number of seconds simulated
4 sim_ticks 5163317092500 # Number of ticks simulated
5 final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 210982 # Simulator instruction rate (inst/s)
8 host_tick_rate 1295931182 # Simulator tick rate (ticks/s)
9 host_mem_usage 391560 # Number of bytes of host memory used
10 host_seconds 3984.25 # Real time elapsed on the host
11 sim_insts 840604148 # Number of instructions simulated
12 system.physmem.bytes_read 15861056 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 1233408 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 12134976 # Number of bytes written to this memory
15 system.physmem.num_reads 247829 # Number of read requests responded to by this memory
16 system.physmem.num_writes 189609 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 3071873 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 238879 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 2350229 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 5422102 # Total bandwidth to/from this memory (bytes/s)
22 system.l2c.replacements 168510 # number of replacements
23 system.l2c.tagsinuse 37865.450237 # Cycle average of tags in use
24 system.l2c.total_refs 3777661 # Total number of references to valid blocks.
25 system.l2c.sampled_refs 200841 # Sample count of references to valid blocks.
26 system.l2c.avg_refs 18.809212 # Average number of references to valid blocks.
27 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
28 system.l2c.occ_blocks::0 11087.594784 # Average occupied blocks per context
29 system.l2c.occ_blocks::1 26777.855453 # Average occupied blocks per context
30 system.l2c.occ_percent::0 0.169183 # Average percentage of cache occupancy
31 system.l2c.occ_percent::1 0.408598 # Average percentage of cache occupancy
32 system.l2c.ReadReq_hits::0 2326799 # number of ReadReq hits
33 system.l2c.ReadReq_hits::1 141457 # number of ReadReq hits
34 system.l2c.ReadReq_hits::total 2468256 # number of ReadReq hits
35 system.l2c.Writeback_hits::0 1603120 # number of Writeback hits
36 system.l2c.Writeback_hits::total 1603120 # number of Writeback hits
37 system.l2c.UpgradeReq_hits::0 322 # number of UpgradeReq hits
38 system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits
39 system.l2c.ReadExReq_hits::0 150704 # number of ReadExReq hits
40 system.l2c.ReadExReq_hits::total 150704 # number of ReadExReq hits
41 system.l2c.demand_hits::0 2477503 # number of demand (read+write) hits
42 system.l2c.demand_hits::1 141457 # number of demand (read+write) hits
43 system.l2c.demand_hits::total 2618960 # number of demand (read+write) hits
44 system.l2c.overall_hits::0 2477503 # number of overall hits
45 system.l2c.overall_hits::1 141457 # number of overall hits
46 system.l2c.overall_hits::total 2618960 # number of overall hits
47 system.l2c.ReadReq_misses::0 64223 # number of ReadReq misses
48 system.l2c.ReadReq_misses::1 92 # number of ReadReq misses
49 system.l2c.ReadReq_misses::total 64315 # number of ReadReq misses
50 system.l2c.UpgradeReq_misses::0 5079 # number of UpgradeReq misses
51 system.l2c.UpgradeReq_misses::total 5079 # number of UpgradeReq misses
52 system.l2c.ReadExReq_misses::0 141389 # number of ReadExReq misses
53 system.l2c.ReadExReq_misses::total 141389 # number of ReadExReq misses
54 system.l2c.demand_misses::0 205612 # number of demand (read+write) misses
55 system.l2c.demand_misses::1 92 # number of demand (read+write) misses
56 system.l2c.demand_misses::total 205704 # number of demand (read+write) misses
57 system.l2c.overall_misses::0 205612 # number of overall misses
58 system.l2c.overall_misses::1 92 # number of overall misses
59 system.l2c.overall_misses::total 205704 # number of overall misses
60 system.l2c.ReadReq_miss_latency 3374675500 # number of ReadReq miss cycles
61 system.l2c.UpgradeReq_miss_latency 37477500 # number of UpgradeReq miss cycles
62 system.l2c.ReadExReq_miss_latency 7363267000 # number of ReadExReq miss cycles
63 system.l2c.demand_miss_latency 10737942500 # number of demand (read+write) miss cycles
64 system.l2c.overall_miss_latency 10737942500 # number of overall miss cycles
65 system.l2c.ReadReq_accesses::0 2391022 # number of ReadReq accesses(hits+misses)
66 system.l2c.ReadReq_accesses::1 141549 # number of ReadReq accesses(hits+misses)
67 system.l2c.ReadReq_accesses::total 2532571 # number of ReadReq accesses(hits+misses)
68 system.l2c.Writeback_accesses::0 1603120 # number of Writeback accesses(hits+misses)
69 system.l2c.Writeback_accesses::total 1603120 # number of Writeback accesses(hits+misses)
70 system.l2c.UpgradeReq_accesses::0 5401 # number of UpgradeReq accesses(hits+misses)
71 system.l2c.UpgradeReq_accesses::total 5401 # number of UpgradeReq accesses(hits+misses)
72 system.l2c.ReadExReq_accesses::0 292093 # number of ReadExReq accesses(hits+misses)
73 system.l2c.ReadExReq_accesses::total 292093 # number of ReadExReq accesses(hits+misses)
74 system.l2c.demand_accesses::0 2683115 # number of demand (read+write) accesses
75 system.l2c.demand_accesses::1 141549 # number of demand (read+write) accesses
76 system.l2c.demand_accesses::total 2824664 # number of demand (read+write) accesses
77 system.l2c.overall_accesses::0 2683115 # number of overall (read+write) accesses
78 system.l2c.overall_accesses::1 141549 # number of overall (read+write) accesses
79 system.l2c.overall_accesses::total 2824664 # number of overall (read+write) accesses
80 system.l2c.ReadReq_miss_rate::0 0.026860 # miss rate for ReadReq accesses
81 system.l2c.ReadReq_miss_rate::1 0.000650 # miss rate for ReadReq accesses
82 system.l2c.ReadReq_miss_rate::total 0.027510 # miss rate for ReadReq accesses
83 system.l2c.UpgradeReq_miss_rate::0 0.940381 # miss rate for UpgradeReq accesses
84 system.l2c.ReadExReq_miss_rate::0 0.484055 # miss rate for ReadExReq accesses
85 system.l2c.demand_miss_rate::0 0.076632 # miss rate for demand accesses
86 system.l2c.demand_miss_rate::1 0.000650 # miss rate for demand accesses
87 system.l2c.demand_miss_rate::total 0.077282 # miss rate for demand accesses
88 system.l2c.overall_miss_rate::0 0.076632 # miss rate for overall accesses
89 system.l2c.overall_miss_rate::1 0.000650 # miss rate for overall accesses
90 system.l2c.overall_miss_rate::total 0.077282 # miss rate for overall accesses
91 system.l2c.ReadReq_avg_miss_latency::0 52546.213973 # average ReadReq miss latency
92 system.l2c.ReadReq_avg_miss_latency::1 36681255.434783 # average ReadReq miss latency
93 system.l2c.ReadReq_avg_miss_latency::total 36733801.648756 # average ReadReq miss latency
94 system.l2c.UpgradeReq_avg_miss_latency::0 7378.913172 # average UpgradeReq miss latency
95 system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
96 system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
97 system.l2c.ReadExReq_avg_miss_latency::0 52078.075381 # average ReadExReq miss latency
98 system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
99 system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
100 system.l2c.demand_avg_miss_latency::0 52224.298679 # average overall miss latency
101 system.l2c.demand_avg_miss_latency::1 116716766.304348 # average overall miss latency
102 system.l2c.demand_avg_miss_latency::total 116768990.603027 # average overall miss latency
103 system.l2c.overall_avg_miss_latency::0 52224.298679 # average overall miss latency
104 system.l2c.overall_avg_miss_latency::1 116716766.304348 # average overall miss latency
105 system.l2c.overall_avg_miss_latency::total 116768990.603027 # average overall miss latency
106 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
107 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
108 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
109 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
110 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
111 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
112 system.l2c.fast_writes 0 # number of fast writes performed
113 system.l2c.cache_copies 0 # number of cache copies performed
114 system.l2c.writebacks 142942 # number of writebacks
115 system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
116 system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits
117 system.l2c.overall_mshr_hits 2 # number of overall MSHR hits
118 system.l2c.ReadReq_mshr_misses 64313 # number of ReadReq MSHR misses
119 system.l2c.UpgradeReq_mshr_misses 5079 # number of UpgradeReq MSHR misses
120 system.l2c.ReadExReq_mshr_misses 141389 # number of ReadExReq MSHR misses
121 system.l2c.demand_mshr_misses 205702 # number of demand (read+write) MSHR misses
122 system.l2c.overall_mshr_misses 205702 # number of overall MSHR misses
123 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
124 system.l2c.ReadReq_mshr_miss_latency 2588909500 # number of ReadReq MSHR miss cycles
125 system.l2c.UpgradeReq_mshr_miss_latency 203533000 # number of UpgradeReq MSHR miss cycles
126 system.l2c.ReadExReq_mshr_miss_latency 5656832000 # number of ReadExReq MSHR miss cycles
127 system.l2c.demand_mshr_miss_latency 8245741500 # number of demand (read+write) MSHR miss cycles
128 system.l2c.overall_mshr_miss_latency 8245741500 # number of overall MSHR miss cycles
129 system.l2c.ReadReq_mshr_uncacheable_latency 59975483500 # number of ReadReq MSHR uncacheable cycles
130 system.l2c.WriteReq_mshr_uncacheable_latency 1228994000 # number of WriteReq MSHR uncacheable cycles
131 system.l2c.overall_mshr_uncacheable_latency 61204477500 # number of overall MSHR uncacheable cycles
132 system.l2c.ReadReq_mshr_miss_rate::0 0.026898 # mshr miss rate for ReadReq accesses
133 system.l2c.ReadReq_mshr_miss_rate::1 0.454351 # mshr miss rate for ReadReq accesses
134 system.l2c.ReadReq_mshr_miss_rate::total 0.481249 # mshr miss rate for ReadReq accesses
135 system.l2c.UpgradeReq_mshr_miss_rate::0 0.940381 # mshr miss rate for UpgradeReq accesses
136 system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
137 system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
138 system.l2c.ReadExReq_mshr_miss_rate::0 0.484055 # mshr miss rate for ReadExReq accesses
139 system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
140 system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
141 system.l2c.demand_mshr_miss_rate::0 0.076665 # mshr miss rate for demand accesses
142 system.l2c.demand_mshr_miss_rate::1 1.453221 # mshr miss rate for demand accesses
143 system.l2c.demand_mshr_miss_rate::total 1.529887 # mshr miss rate for demand accesses
144 system.l2c.overall_mshr_miss_rate::0 0.076665 # mshr miss rate for overall accesses
145 system.l2c.overall_mshr_miss_rate::1 1.453221 # mshr miss rate for overall accesses
146 system.l2c.overall_mshr_miss_rate::total 1.529887 # mshr miss rate for overall accesses
147 system.l2c.ReadReq_avg_mshr_miss_latency 40254.839613 # average ReadReq mshr miss latency
148 system.l2c.UpgradeReq_avg_mshr_miss_latency 40073.439653 # average UpgradeReq mshr miss latency
149 system.l2c.ReadExReq_avg_mshr_miss_latency 40008.996457 # average ReadExReq mshr miss latency
150 system.l2c.demand_avg_mshr_miss_latency 40085.859642 # average overall mshr miss latency
151 system.l2c.overall_avg_mshr_miss_latency 40085.859642 # average overall mshr miss latency
152 system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
153 system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
154 system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
155 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
156 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
157 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
158 system.iocache.replacements 47580 # number of replacements
159 system.iocache.tagsinuse 0.183883 # Cycle average of tags in use
160 system.iocache.total_refs 0 # Total number of references to valid blocks.
161 system.iocache.sampled_refs 47596 # Sample count of references to valid blocks.
162 system.iocache.avg_refs 0 # Average number of references to valid blocks.
163 system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit.
164 system.iocache.occ_blocks::1 0.183883 # Average occupied blocks per context
165 system.iocache.occ_percent::1 0.011493 # Average percentage of cache occupancy
166 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
167 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
168 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
169 system.iocache.overall_hits::0 0 # number of overall hits
170 system.iocache.overall_hits::1 0 # number of overall hits
171 system.iocache.overall_hits::total 0 # number of overall hits
172 system.iocache.ReadReq_misses::1 915 # number of ReadReq misses
173 system.iocache.ReadReq_misses::total 915 # number of ReadReq misses
174 system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
175 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
176 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
177 system.iocache.demand_misses::1 47635 # number of demand (read+write) misses
178 system.iocache.demand_misses::total 47635 # number of demand (read+write) misses
179 system.iocache.overall_misses::0 0 # number of overall misses
180 system.iocache.overall_misses::1 47635 # number of overall misses
181 system.iocache.overall_misses::total 47635 # number of overall misses
182 system.iocache.ReadReq_miss_latency 114575932 # number of ReadReq miss cycles
183 system.iocache.WriteReq_miss_latency 6365614160 # number of WriteReq miss cycles
184 system.iocache.demand_miss_latency 6480190092 # number of demand (read+write) miss cycles
185 system.iocache.overall_miss_latency 6480190092 # number of overall miss cycles
186 system.iocache.ReadReq_accesses::1 915 # number of ReadReq accesses(hits+misses)
187 system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
188 system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
189 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
190 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
191 system.iocache.demand_accesses::1 47635 # number of demand (read+write) accesses
192 system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses
193 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
194 system.iocache.overall_accesses::1 47635 # number of overall (read+write) accesses
195 system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses
196 system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
197 system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
198 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
199 system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
200 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
201 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
202 system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
203 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
204 system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
205 system.iocache.ReadReq_avg_miss_latency::1 125219.597814 # average ReadReq miss latency
206 system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
207 system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
208 system.iocache.WriteReq_avg_miss_latency::1 136250.303082 # average WriteReq miss latency
209 system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
210 system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
211 system.iocache.demand_avg_miss_latency::1 136038.419062 # average overall miss latency
212 system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
213 system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
214 system.iocache.overall_avg_miss_latency::1 136038.419062 # average overall miss latency
215 system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
216 system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked
217 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
218 system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked
219 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
220 system.iocache.avg_blocked_cycles::no_mshrs 6082.729550 # average number of cycles each access was blocked
221 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
222 system.iocache.fast_writes 0 # number of fast writes performed
223 system.iocache.cache_copies 0 # number of cache copies performed
224 system.iocache.writebacks 46667 # number of writebacks
225 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
226 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
227 system.iocache.ReadReq_mshr_misses 915 # number of ReadReq MSHR misses
228 system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses
229 system.iocache.demand_mshr_misses 47635 # number of demand (read+write) MSHR misses
230 system.iocache.overall_mshr_misses 47635 # number of overall MSHR misses
231 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
232 system.iocache.ReadReq_mshr_miss_latency 66972982 # number of ReadReq MSHR miss cycles
233 system.iocache.WriteReq_mshr_miss_latency 3935855798 # number of WriteReq MSHR miss cycles
234 system.iocache.demand_mshr_miss_latency 4002828780 # number of demand (read+write) MSHR miss cycles
235 system.iocache.overall_mshr_miss_latency 4002828780 # number of overall MSHR miss cycles
236 system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
237 system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
238 system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
239 system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
240 system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
241 system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
242 system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
243 system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
244 system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
245 system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
246 system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
247 system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
248 system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
249 system.iocache.ReadReq_avg_mshr_miss_latency 73194.515847 # average ReadReq mshr miss latency
250 system.iocache.WriteReq_avg_mshr_miss_latency 84243.488827 # average WriteReq mshr miss latency
251 system.iocache.demand_avg_mshr_miss_latency 84031.253910 # average overall mshr miss latency
252 system.iocache.overall_avg_mshr_miss_latency 84031.253910 # average overall mshr miss latency
253 system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
254 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
255 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
256 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
257 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
258 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
259 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
260 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
261 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
262 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
263 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
264 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
265 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
266 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
267 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
268 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
269 system.cpu.numCycles 462460674 # number of cpu cycles simulated
270 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
271 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
272 system.cpu.BPredUnit.lookups 91001984 # Number of BP lookups
273 system.cpu.BPredUnit.condPredicted 91001984 # Number of conditional branches predicted
274 system.cpu.BPredUnit.condIncorrect 1246670 # Number of conditional branches incorrect
275 system.cpu.BPredUnit.BTBLookups 89740974 # Number of BTB lookups
276 system.cpu.BPredUnit.BTBHits 83587498 # Number of BTB hits
277 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
278 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
279 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
280 system.cpu.fetch.icacheStallCycles 28956413 # Number of cycles fetch is stalled on an Icache miss
281 system.cpu.fetch.Insts 449639850 # Number of instructions fetch has processed
282 system.cpu.fetch.Branches 91001984 # Number of branches that fetch encountered
283 system.cpu.fetch.predictedBranches 83587498 # Number of branches that fetch has predicted taken
284 system.cpu.fetch.Cycles 171222727 # Number of cycles fetch has run and was not squashing or blocked
285 system.cpu.fetch.SquashCycles 5870168 # Number of cycles fetch has spent squashing
286 system.cpu.fetch.TlbCycles 127753 # Number of cycles fetch has spent waiting for tlb
287 system.cpu.fetch.BlockedCycles 101915873 # Number of cycles fetch has spent blocked
288 system.cpu.fetch.MiscStallCycles 36574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
289 system.cpu.fetch.PendingTrapStallCycles 38952 # Number of stall cycles due to pending traps
290 system.cpu.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR
291 system.cpu.fetch.CacheLines 9672092 # Number of cache lines fetched
292 system.cpu.fetch.IcacheSquashes 512695 # Number of outstanding Icache misses that were squashed
293 system.cpu.fetch.ItlbSquashes 3312 # Number of outstanding ITLB misses that were squashed
294 system.cpu.fetch.rateDist::samples 306883426 # Number of instructions fetched each cycle (Total)
295 system.cpu.fetch.rateDist::mean 2.884320 # Number of instructions fetched each cycle (Total)
296 system.cpu.fetch.rateDist::stdev 3.377751 # Number of instructions fetched each cycle (Total)
297 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
298 system.cpu.fetch.rateDist::0 136151197 44.37% 44.37% # Number of instructions fetched each cycle (Total)
299 system.cpu.fetch.rateDist::1 1833476 0.60% 44.96% # Number of instructions fetched each cycle (Total)
300 system.cpu.fetch.rateDist::2 72801112 23.72% 68.69% # Number of instructions fetched each cycle (Total)
301 system.cpu.fetch.rateDist::3 1413943 0.46% 69.15% # Number of instructions fetched each cycle (Total)
302 system.cpu.fetch.rateDist::4 1812929 0.59% 69.74% # Number of instructions fetched each cycle (Total)
303 system.cpu.fetch.rateDist::5 3984448 1.30% 71.04% # Number of instructions fetched each cycle (Total)
304 system.cpu.fetch.rateDist::6 1563806 0.51% 71.55% # Number of instructions fetched each cycle (Total)
305 system.cpu.fetch.rateDist::7 1664583 0.54% 72.09% # Number of instructions fetched each cycle (Total)
306 system.cpu.fetch.rateDist::8 85657932 27.91% 100.00% # Number of instructions fetched each cycle (Total)
307 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
308 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
309 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
310 system.cpu.fetch.rateDist::total 306883426 # Number of instructions fetched each cycle (Total)
311 system.cpu.fetch.branchRate 0.196778 # Number of branch fetches per cycle
312 system.cpu.fetch.rate 0.972277 # Number of inst fetches per cycle
313 system.cpu.decode.IdleCycles 34101035 # Number of cycles decode is idle
314 system.cpu.decode.BlockedCycles 98103338 # Number of cycles decode is blocked
315 system.cpu.decode.RunCycles 165554285 # Number of cycles decode is running
316 system.cpu.decode.UnblockCycles 4539875 # Number of cycles decode is unblocking
317 system.cpu.decode.SquashCycles 4584893 # Number of cycles decode is squashing
318 system.cpu.decode.DecodedInsts 881320225 # Number of instructions handled by decode
319 system.cpu.decode.SquashedInsts 609 # Number of squashed instructions handled by decode
320 system.cpu.rename.SquashCycles 4584893 # Number of cycles rename is squashing
321 system.cpu.rename.IdleCycles 38485909 # Number of cycles rename is idle
322 system.cpu.rename.BlockCycles 67729275 # Number of cycles rename is blocking
323 system.cpu.rename.serializeStallCycles 11421097 # count of cycles rename stalled for serializing inst
324 system.cpu.rename.RunCycles 165177226 # Number of cycles rename is running
325 system.cpu.rename.UnblockCycles 19485026 # Number of cycles rename is unblocking
326 system.cpu.rename.RenamedInsts 876989303 # Number of instructions processed by rename
327 system.cpu.rename.ROBFullEvents 10814 # Number of times rename has blocked due to ROB full
328 system.cpu.rename.IQFullEvents 12483638 # Number of times rename has blocked due to IQ full
329 system.cpu.rename.LSQFullEvents 3869558 # Number of times rename has blocked due to LSQ full
330 system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers
331 system.cpu.rename.RenamedOperands 878639289 # Number of destination operands rename has renamed
332 system.cpu.rename.RenameLookups 1719877661 # Number of register rename lookups that rename has made
333 system.cpu.rename.int_rename_lookups 1719877141 # Number of integer rename lookups
334 system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups
335 system.cpu.rename.CommittedMaps 843209199 # Number of HB maps that are committed
336 system.cpu.rename.UndoneMaps 35430083 # Number of HB maps that are undone due to squashing
337 system.cpu.rename.serializingInsts 491480 # count of serializing insts renamed
338 system.cpu.rename.tempSerializingInsts 496551 # count of temporary serializing insts renamed
339 system.cpu.rename.skidInsts 46051608 # count of insts added to the skid buffer
340 system.cpu.memDep0.insertedLoads 19446241 # Number of loads inserted to the mem dependence unit.
341 system.cpu.memDep0.insertedStores 10506071 # Number of stores inserted to the mem dependence unit.
342 system.cpu.memDep0.conflictingLoads 1193626 # Number of conflicting loads.
343 system.cpu.memDep0.conflictingStores 915732 # Number of conflicting stores.
344 system.cpu.iq.iqInstsAdded 869497074 # Number of instructions added to the IQ (excludes non-spec)
345 system.cpu.iq.iqNonSpecInstsAdded 1725725 # Number of non-speculative instructions added to the IQ
346 system.cpu.iq.iqInstsIssued 866404799 # Number of instructions issued
347 system.cpu.iq.iqSquashedInstsIssued 123854 # Number of squashed instructions issued
348 system.cpu.iq.iqSquashedInstsExamined 29753009 # Number of squashed instructions iterated over during squash; mainly for profiling
349 system.cpu.iq.iqSquashedOperandsExamined 42786279 # Number of squashed operands that are examined and possibly removed from graph
350 system.cpu.iq.iqSquashedNonSpecRemoved 206033 # Number of squashed non-spec instructions that were removed
351 system.cpu.iq.issued_per_cycle::samples 306883426 # Number of insts issued each cycle
352 system.cpu.iq.issued_per_cycle::mean 2.823238 # Number of insts issued each cycle
353 system.cpu.iq.issued_per_cycle::stdev 2.403588 # Number of insts issued each cycle
354 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
355 system.cpu.iq.issued_per_cycle::0 100067522 32.61% 32.61% # Number of insts issued each cycle
356 system.cpu.iq.issued_per_cycle::1 25349299 8.26% 40.87% # Number of insts issued each cycle
357 system.cpu.iq.issued_per_cycle::2 13936726 4.54% 45.41% # Number of insts issued each cycle
358 system.cpu.iq.issued_per_cycle::3 9650933 3.14% 48.55% # Number of insts issued each cycle
359 system.cpu.iq.issued_per_cycle::4 79503599 25.91% 74.46% # Number of insts issued each cycle
360 system.cpu.iq.issued_per_cycle::5 4853866 1.58% 76.04% # Number of insts issued each cycle
361 system.cpu.iq.issued_per_cycle::6 72832557 23.73% 99.78% # Number of insts issued each cycle
362 system.cpu.iq.issued_per_cycle::7 561211 0.18% 99.96% # Number of insts issued each cycle
363 system.cpu.iq.issued_per_cycle::8 127713 0.04% 100.00% # Number of insts issued each cycle
364 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
365 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
366 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
367 system.cpu.iq.issued_per_cycle::total 306883426 # Number of insts issued each cycle
368 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
369 system.cpu.iq.fu_full::IntAlu 188296 8.84% 8.84% # attempts to use FU when none available
370 system.cpu.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available
371 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available
372 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available
373 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available
374 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available
375 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available
376 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available
377 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available
378 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available
379 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available
380 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available
381 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available
382 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available
384 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available
385 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available
386 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available
387 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available
388 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available
389 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available
390 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available
391 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available
392 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available
393 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available
394 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available
395 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available
396 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available
397 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available
398 system.cpu.iq.fu_full::MemRead 1773429 83.29% 92.13% # attempts to use FU when none available
399 system.cpu.iq.fu_full::MemWrite 167520 7.87% 100.00% # attempts to use FU when none available
400 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
401 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
402 system.cpu.iq.FU_type_0::No_OpClass 304337 0.04% 0.04% # Type of FU issued
403 system.cpu.iq.FU_type_0::IntAlu 831186392 95.94% 95.97% # Type of FU issued
404 system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued
405 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued
406 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued
407 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued
408 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued
409 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued
410 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued
411 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued
412 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued
413 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued
414 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued
415 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued
416 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued
418 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued
419 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued
420 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued
421 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued
422 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued
423 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued
424 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued
425 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued
426 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued
427 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued
428 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued
429 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued
430 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued
431 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued
432 system.cpu.iq.FU_type_0::MemRead 25424398 2.93% 98.90% # Type of FU issued
433 system.cpu.iq.FU_type_0::MemWrite 9489672 1.10% 100.00% # Type of FU issued
434 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
435 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
436 system.cpu.iq.FU_type_0::total 866404799 # Type of FU issued
437 system.cpu.iq.rate 1.873467 # Inst issue rate
438 system.cpu.iq.fu_busy_cnt 2129245 # FU busy when requested
439 system.cpu.iq.fu_busy_rate 0.002458 # FU busy rate (busy events/executed inst)
440 system.cpu.iq.int_inst_queue_reads 2042097119 # Number of integer instruction queue reads
441 system.cpu.iq.int_inst_queue_writes 900986111 # Number of integer instruction queue writes
442 system.cpu.iq.int_inst_queue_wakeup_accesses 855761606 # Number of integer instruction queue wakeup accesses
443 system.cpu.iq.fp_inst_queue_reads 229 # Number of floating instruction queue reads
444 system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes
445 system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses
446 system.cpu.iq.int_alu_accesses 868229599 # Number of integer alu accesses
447 system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses
448 system.cpu.iew.lsq.thread0.forwLoads 1634850 # Number of loads that had data forwarded from stores
449 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
450 system.cpu.iew.lsq.thread0.squashedLoads 4122229 # Number of loads squashed
451 system.cpu.iew.lsq.thread0.ignoredResponses 17231 # Number of memory responses ignored because the instruction is squashed
452 system.cpu.iew.lsq.thread0.memOrderViolation 11383 # Number of memory ordering violations
453 system.cpu.iew.lsq.thread0.squashedStores 2082513 # Number of stores squashed
454 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
455 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
456 system.cpu.iew.lsq.thread0.rescheduledLoads 7821289 # Number of loads that were rescheduled
457 system.cpu.iew.lsq.thread0.cacheBlocked 4333 # Number of times an access to memory failed due to the cache being blocked
458 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
459 system.cpu.iew.iewSquashCycles 4584893 # Number of cycles IEW is squashing
460 system.cpu.iew.iewBlockCycles 45441721 # Number of cycles IEW is blocking
461 system.cpu.iew.iewUnblockCycles 6142722 # Number of cycles IEW is unblocking
462 system.cpu.iew.iewDispatchedInsts 871222799 # Number of instructions dispatched to IQ
463 system.cpu.iew.iewDispSquashedInsts 285751 # Number of squashed instructions skipped by dispatch
464 system.cpu.iew.iewDispLoadInsts 19446241 # Number of dispatched load instructions
465 system.cpu.iew.iewDispStoreInsts 10506071 # Number of dispatched store instructions
466 system.cpu.iew.iewDispNonSpecInsts 891740 # Number of dispatched non-speculative instructions
467 system.cpu.iew.iewIQFullEvents 5368443 # Number of times the IQ has become full, causing a stall
468 system.cpu.iew.iewLSQFullEvents 12385 # Number of times the LSQ has become full, causing a stall
469 system.cpu.iew.memOrderViolationEvents 11383 # Number of memory order violations
470 system.cpu.iew.predictedTakenIncorrect 896223 # Number of branches that were predicted taken incorrectly
471 system.cpu.iew.predictedNotTakenIncorrect 525625 # Number of branches that were predicted not taken incorrectly
472 system.cpu.iew.branchMispredicts 1421848 # Number of branch mispredicts detected at execute
473 system.cpu.iew.iewExecutedInsts 864338156 # Number of executed instructions
474 system.cpu.iew.iewExecLoadInsts 24982156 # Number of load instructions executed
475 system.cpu.iew.iewExecSquashedInsts 2066642 # Number of squashed instructions skipped in execute
476 system.cpu.iew.exec_swp 0 # number of swp insts executed
477 system.cpu.iew.exec_nop 0 # number of nop insts executed
478 system.cpu.iew.exec_refs 34234409 # number of memory reference insts executed
479 system.cpu.iew.exec_branches 86668621 # Number of branches executed
480 system.cpu.iew.exec_stores 9252253 # Number of stores executed
481 system.cpu.iew.exec_rate 1.868998 # Inst execution rate
482 system.cpu.iew.wb_sent 863811947 # cumulative count of insts sent to commit
483 system.cpu.iew.wb_count 855761668 # cumulative count of insts written-back
484 system.cpu.iew.wb_producers 670084242 # num instructions producing a value
485 system.cpu.iew.wb_consumers 1169301773 # num instructions consuming a value
486 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
487 system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle
488 system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back
489 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
490 system.cpu.commit.commitCommittedInsts 840604148 # The number of committed instructions
491 system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit
492 system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards
493 system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted
494 system.cpu.commit.committed_per_cycle::samples 302314482 # Number of insts commited each cycle
495 system.cpu.commit.committed_per_cycle::mean 2.780562 # Number of insts commited each cycle
496 system.cpu.commit.committed_per_cycle::stdev 2.862970 # Number of insts commited each cycle
497 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
498 system.cpu.commit.committed_per_cycle::0 121547491 40.21% 40.21% # Number of insts commited each cycle
499 system.cpu.commit.committed_per_cycle::1 14447999 4.78% 44.98% # Number of insts commited each cycle
500 system.cpu.commit.committed_per_cycle::2 4300765 1.42% 46.41% # Number of insts commited each cycle
501 system.cpu.commit.committed_per_cycle::3 76650469 25.35% 71.76% # Number of insts commited each cycle
502 system.cpu.commit.committed_per_cycle::4 3947228 1.31% 73.07% # Number of insts commited each cycle
503 system.cpu.commit.committed_per_cycle::5 1803648 0.60% 73.66% # Number of insts commited each cycle
504 system.cpu.commit.committed_per_cycle::6 1077125 0.36% 74.02% # Number of insts commited each cycle
505 system.cpu.commit.committed_per_cycle::7 71984746 23.81% 97.83% # Number of insts commited each cycle
506 system.cpu.commit.committed_per_cycle::8 6555011 2.17% 100.00% # Number of insts commited each cycle
507 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
508 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
509 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
510 system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle
511 system.cpu.commit.count 840604148 # Number of instructions committed
512 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
513 system.cpu.commit.refs 23747567 # Number of memory references committed
514 system.cpu.commit.loads 15324009 # Number of loads committed
515 system.cpu.commit.membars 781567 # Number of memory barriers committed
516 system.cpu.commit.branches 85515141 # Number of branches committed
517 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
518 system.cpu.commit.int_insts 768433298 # Number of committed integer instructions.
519 system.cpu.commit.function_calls 0 # Number of function calls committed.
520 system.cpu.commit.bw_lim_events 6555011 # number cycles where commit BW limit reached
521 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
522 system.cpu.rob.rob_reads 1166791668 # The number of ROB reads
523 system.cpu.rob.rob_writes 1746826364 # The number of ROB writes
524 system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself
525 system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling
526 system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
527 system.cpu.committedInsts 840604148 # Number of Instructions Simulated
528 system.cpu.committedInsts_total 840604148 # Number of Instructions Simulated
529 system.cpu.cpi 0.550153 # CPI: Cycles Per Instruction
530 system.cpu.cpi_total 0.550153 # CPI: Total CPI of All Threads
531 system.cpu.ipc 1.817677 # IPC: Instructions Per Cycle
532 system.cpu.ipc_total 1.817677 # IPC: Total IPC of All Threads
533 system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads
534 system.cpu.int_regfile_writes 857070459 # number of integer regfile writes
535 system.cpu.fp_regfile_reads 62 # number of floating regfile reads
536 system.cpu.misc_regfile_reads 281985005 # number of misc regfile reads
537 system.cpu.misc_regfile_writes 409504 # number of misc regfile writes
538 system.cpu.icache.replacements 1020153 # number of replacements
539 system.cpu.icache.tagsinuse 509.928344 # Cycle average of tags in use
540 system.cpu.icache.total_refs 8587640 # Total number of references to valid blocks.
541 system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks.
542 system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks.
543 system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit.
544 system.cpu.icache.occ_blocks::0 509.928344 # Average occupied blocks per context
545 system.cpu.icache.occ_percent::0 0.995954 # Average percentage of cache occupancy
546 system.cpu.icache.ReadReq_hits::0 8587640 # number of ReadReq hits
547 system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits
548 system.cpu.icache.demand_hits::0 8587640 # number of demand (read+write) hits
549 system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
550 system.cpu.icache.demand_hits::total 8587640 # number of demand (read+write) hits
551 system.cpu.icache.overall_hits::0 8587640 # number of overall hits
552 system.cpu.icache.overall_hits::1 0 # number of overall hits
553 system.cpu.icache.overall_hits::total 8587640 # number of overall hits
554 system.cpu.icache.ReadReq_misses::0 1084449 # number of ReadReq misses
555 system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses
556 system.cpu.icache.demand_misses::0 1084449 # number of demand (read+write) misses
557 system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
558 system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses
559 system.cpu.icache.overall_misses::0 1084449 # number of overall misses
560 system.cpu.icache.overall_misses::1 0 # number of overall misses
561 system.cpu.icache.overall_misses::total 1084449 # number of overall misses
562 system.cpu.icache.ReadReq_miss_latency 16282601991 # number of ReadReq miss cycles
563 system.cpu.icache.demand_miss_latency 16282601991 # number of demand (read+write) miss cycles
564 system.cpu.icache.overall_miss_latency 16282601991 # number of overall miss cycles
565 system.cpu.icache.ReadReq_accesses::0 9672089 # number of ReadReq accesses(hits+misses)
566 system.cpu.icache.ReadReq_accesses::total 9672089 # number of ReadReq accesses(hits+misses)
567 system.cpu.icache.demand_accesses::0 9672089 # number of demand (read+write) accesses
568 system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
569 system.cpu.icache.demand_accesses::total 9672089 # number of demand (read+write) accesses
570 system.cpu.icache.overall_accesses::0 9672089 # number of overall (read+write) accesses
571 system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
572 system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses
573 system.cpu.icache.ReadReq_miss_rate::0 0.112121 # miss rate for ReadReq accesses
574 system.cpu.icache.demand_miss_rate::0 0.112121 # miss rate for demand accesses
575 system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
576 system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
577 system.cpu.icache.overall_miss_rate::0 0.112121 # miss rate for overall accesses
578 system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
579 system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
580 system.cpu.icache.ReadReq_avg_miss_latency::0 15014.631385 # average ReadReq miss latency
581 system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
582 system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
583 system.cpu.icache.demand_avg_miss_latency::0 15014.631385 # average overall miss latency
584 system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
585 system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
586 system.cpu.icache.overall_avg_miss_latency::0 15014.631385 # average overall miss latency
587 system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
588 system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
589 system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked
590 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
591 system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked
592 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
593 system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730 # average number of cycles each access was blocked
594 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
595 system.cpu.icache.fast_writes 0 # number of fast writes performed
596 system.cpu.icache.cache_copies 0 # number of cache copies performed
597 system.cpu.icache.writebacks 1551 # number of writebacks
598 system.cpu.icache.ReadReq_mshr_hits 60108 # number of ReadReq MSHR hits
599 system.cpu.icache.demand_mshr_hits 60108 # number of demand (read+write) MSHR hits
600 system.cpu.icache.overall_mshr_hits 60108 # number of overall MSHR hits
601 system.cpu.icache.ReadReq_mshr_misses 1024341 # number of ReadReq MSHR misses
602 system.cpu.icache.demand_mshr_misses 1024341 # number of demand (read+write) MSHR misses
603 system.cpu.icache.overall_mshr_misses 1024341 # number of overall MSHR misses
604 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
605 system.cpu.icache.ReadReq_mshr_miss_latency 12392610492 # number of ReadReq MSHR miss cycles
606 system.cpu.icache.demand_mshr_miss_latency 12392610492 # number of demand (read+write) MSHR miss cycles
607 system.cpu.icache.overall_mshr_miss_latency 12392610492 # number of overall MSHR miss cycles
608 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
609 system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105907 # mshr miss rate for ReadReq accesses
610 system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
611 system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
612 system.cpu.icache.demand_mshr_miss_rate::0 0.105907 # mshr miss rate for demand accesses
613 system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
614 system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
615 system.cpu.icache.overall_mshr_miss_rate::0 0.105907 # mshr miss rate for overall accesses
616 system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
617 system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
618 system.cpu.icache.ReadReq_avg_mshr_miss_latency 12098.129912 # average ReadReq mshr miss latency
619 system.cpu.icache.demand_avg_mshr_miss_latency 12098.129912 # average overall mshr miss latency
620 system.cpu.icache.overall_avg_mshr_miss_latency 12098.129912 # average overall mshr miss latency
621 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
622 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
623 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
624 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
625 system.cpu.itb_walker_cache.replacements 8553 # number of replacements
626 system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use
627 system.cpu.itb_walker_cache.total_refs 26637 # Total number of references to valid blocks.
628 system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks.
629 system.cpu.itb_walker_cache.avg_refs 3.110346 # Average number of references to valid blocks.
630 system.cpu.itb_walker_cache.warmup_cycle 5140402124000 # Cycle when the warmup percentage was hit.
631 system.cpu.itb_walker_cache.occ_blocks::1 6.010935 # Average occupied blocks per context
632 system.cpu.itb_walker_cache.occ_percent::1 0.375683 # Average percentage of cache occupancy
633 system.cpu.itb_walker_cache.ReadReq_hits::1 26742 # number of ReadReq hits
634 system.cpu.itb_walker_cache.ReadReq_hits::total 26742 # number of ReadReq hits
635 system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits
636 system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
637 system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
638 system.cpu.itb_walker_cache.demand_hits::1 26745 # number of demand (read+write) hits
639 system.cpu.itb_walker_cache.demand_hits::total 26745 # number of demand (read+write) hits
640 system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
641 system.cpu.itb_walker_cache.overall_hits::1 26745 # number of overall hits
642 system.cpu.itb_walker_cache.overall_hits::total 26745 # number of overall hits
643 system.cpu.itb_walker_cache.ReadReq_misses::1 9424 # number of ReadReq misses
644 system.cpu.itb_walker_cache.ReadReq_misses::total 9424 # number of ReadReq misses
645 system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
646 system.cpu.itb_walker_cache.demand_misses::1 9424 # number of demand (read+write) misses
647 system.cpu.itb_walker_cache.demand_misses::total 9424 # number of demand (read+write) misses
648 system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
649 system.cpu.itb_walker_cache.overall_misses::1 9424 # number of overall misses
650 system.cpu.itb_walker_cache.overall_misses::total 9424 # number of overall misses
651 system.cpu.itb_walker_cache.ReadReq_miss_latency 120935500 # number of ReadReq miss cycles
652 system.cpu.itb_walker_cache.demand_miss_latency 120935500 # number of demand (read+write) miss cycles
653 system.cpu.itb_walker_cache.overall_miss_latency 120935500 # number of overall miss cycles
654 system.cpu.itb_walker_cache.ReadReq_accesses::1 36166 # number of ReadReq accesses(hits+misses)
655 system.cpu.itb_walker_cache.ReadReq_accesses::total 36166 # number of ReadReq accesses(hits+misses)
656 system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses)
657 system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
658 system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
659 system.cpu.itb_walker_cache.demand_accesses::1 36169 # number of demand (read+write) accesses
660 system.cpu.itb_walker_cache.demand_accesses::total 36169 # number of demand (read+write) accesses
661 system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
662 system.cpu.itb_walker_cache.overall_accesses::1 36169 # number of overall (read+write) accesses
663 system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses
664 system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.260576 # miss rate for ReadReq accesses
665 system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
666 system.cpu.itb_walker_cache.demand_miss_rate::1 0.260555 # miss rate for demand accesses
667 system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
668 system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
669 system.cpu.itb_walker_cache.overall_miss_rate::1 0.260555 # miss rate for overall accesses
670 system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
671 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
672 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12832.714346 # average ReadReq miss latency
673 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
674 system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
675 system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12832.714346 # average overall miss latency
676 system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
677 system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
678 system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12832.714346 # average overall miss latency
679 system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
680 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
683 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
684 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
685 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
686 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
687 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
688 system.cpu.itb_walker_cache.writebacks 1616 # number of writebacks
689 system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
690 system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
691 system.cpu.itb_walker_cache.ReadReq_mshr_misses 9424 # number of ReadReq MSHR misses
692 system.cpu.itb_walker_cache.demand_mshr_misses 9424 # number of demand (read+write) MSHR misses
693 system.cpu.itb_walker_cache.overall_mshr_misses 9424 # number of overall MSHR misses
694 system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
695 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 92324000 # number of ReadReq MSHR miss cycles
696 system.cpu.itb_walker_cache.demand_mshr_miss_latency 92324000 # number of demand (read+write) MSHR miss cycles
697 system.cpu.itb_walker_cache.overall_mshr_miss_latency 92324000 # number of overall MSHR miss cycles
698 system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
699 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
700 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.260576 # mshr miss rate for ReadReq accesses
701 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
702 system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
703 system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.260555 # mshr miss rate for demand accesses
704 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
705 system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
706 system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.260555 # mshr miss rate for overall accesses
707 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
708 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9796.689304 # average ReadReq mshr miss latency
709 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9796.689304 # average overall mshr miss latency
710 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9796.689304 # average overall mshr miss latency
711 system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
712 system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
713 system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
714 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
715 system.cpu.dtb_walker_cache.replacements 140574 # number of replacements
716 system.cpu.dtb_walker_cache.tagsinuse 13.858803 # Cycle average of tags in use
717 system.cpu.dtb_walker_cache.total_refs 148049 # Total number of references to valid blocks.
718 system.cpu.dtb_walker_cache.sampled_refs 140589 # Sample count of references to valid blocks.
719 system.cpu.dtb_walker_cache.avg_refs 1.053062 # Average number of references to valid blocks.
720 system.cpu.dtb_walker_cache.warmup_cycle 5108661869000 # Cycle when the warmup percentage was hit.
721 system.cpu.dtb_walker_cache.occ_blocks::1 13.858803 # Average occupied blocks per context
722 system.cpu.dtb_walker_cache.occ_percent::1 0.866175 # Average percentage of cache occupancy
723 system.cpu.dtb_walker_cache.ReadReq_hits::1 148058 # number of ReadReq hits
724 system.cpu.dtb_walker_cache.ReadReq_hits::total 148058 # number of ReadReq hits
725 system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
726 system.cpu.dtb_walker_cache.demand_hits::1 148058 # number of demand (read+write) hits
727 system.cpu.dtb_walker_cache.demand_hits::total 148058 # number of demand (read+write) hits
728 system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
729 system.cpu.dtb_walker_cache.overall_hits::1 148058 # number of overall hits
730 system.cpu.dtb_walker_cache.overall_hits::total 148058 # number of overall hits
731 system.cpu.dtb_walker_cache.ReadReq_misses::1 141571 # number of ReadReq misses
732 system.cpu.dtb_walker_cache.ReadReq_misses::total 141571 # number of ReadReq misses
733 system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
734 system.cpu.dtb_walker_cache.demand_misses::1 141571 # number of demand (read+write) misses
735 system.cpu.dtb_walker_cache.demand_misses::total 141571 # number of demand (read+write) misses
736 system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
737 system.cpu.dtb_walker_cache.overall_misses::1 141571 # number of overall misses
738 system.cpu.dtb_walker_cache.overall_misses::total 141571 # number of overall misses
739 system.cpu.dtb_walker_cache.ReadReq_miss_latency 1989434500 # number of ReadReq miss cycles
740 system.cpu.dtb_walker_cache.demand_miss_latency 1989434500 # number of demand (read+write) miss cycles
741 system.cpu.dtb_walker_cache.overall_miss_latency 1989434500 # number of overall miss cycles
742 system.cpu.dtb_walker_cache.ReadReq_accesses::1 289629 # number of ReadReq accesses(hits+misses)
743 system.cpu.dtb_walker_cache.ReadReq_accesses::total 289629 # number of ReadReq accesses(hits+misses)
744 system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
745 system.cpu.dtb_walker_cache.demand_accesses::1 289629 # number of demand (read+write) accesses
746 system.cpu.dtb_walker_cache.demand_accesses::total 289629 # number of demand (read+write) accesses
747 system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
748 system.cpu.dtb_walker_cache.overall_accesses::1 289629 # number of overall (read+write) accesses
749 system.cpu.dtb_walker_cache.overall_accesses::total 289629 # number of overall (read+write) accesses
750 system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.488801 # miss rate for ReadReq accesses
751 system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
752 system.cpu.dtb_walker_cache.demand_miss_rate::1 0.488801 # miss rate for demand accesses
753 system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
754 system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
755 system.cpu.dtb_walker_cache.overall_miss_rate::1 0.488801 # miss rate for overall accesses
756 system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
757 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
758 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14052.556668 # average ReadReq miss latency
759 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
760 system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
761 system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14052.556668 # average overall miss latency
762 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
763 system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
764 system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14052.556668 # average overall miss latency
765 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
766 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
767 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
768 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
769 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
770 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
771 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
772 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
773 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
774 system.cpu.dtb_walker_cache.writebacks 49457 # number of writebacks
775 system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
776 system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
777 system.cpu.dtb_walker_cache.ReadReq_mshr_misses 141571 # number of ReadReq MSHR misses
778 system.cpu.dtb_walker_cache.demand_mshr_misses 141571 # number of demand (read+write) MSHR misses
779 system.cpu.dtb_walker_cache.overall_mshr_misses 141571 # number of overall MSHR misses
780 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
781 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1560743500 # number of ReadReq MSHR miss cycles
782 system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1560743500 # number of demand (read+write) MSHR miss cycles
783 system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1560743500 # number of overall MSHR miss cycles
784 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
785 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
786 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.488801 # mshr miss rate for ReadReq accesses
787 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
788 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
789 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.488801 # mshr miss rate for demand accesses
790 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
791 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
792 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.488801 # mshr miss rate for overall accesses
793 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
794 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 11024.457693 # average ReadReq mshr miss latency
795 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 11024.457693 # average overall mshr miss latency
796 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 11024.457693 # average overall mshr miss latency
797 system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
798 system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
799 system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
800 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
801 system.cpu.dcache.replacements 1662584 # number of replacements
802 system.cpu.dcache.tagsinuse 511.995323 # Cycle average of tags in use
803 system.cpu.dcache.total_refs 19274168 # Total number of references to valid blocks.
804 system.cpu.dcache.sampled_refs 1663096 # Sample count of references to valid blocks.
805 system.cpu.dcache.avg_refs 11.589330 # Average number of references to valid blocks.
806 system.cpu.dcache.warmup_cycle 34335000 # Cycle when the warmup percentage was hit.
807 system.cpu.dcache.occ_blocks::0 511.995323 # Average occupied blocks per context
808 system.cpu.dcache.occ_percent::0 0.999991 # Average percentage of cache occupancy
809 system.cpu.dcache.ReadReq_hits::0 11173849 # number of ReadReq hits
810 system.cpu.dcache.ReadReq_hits::total 11173849 # number of ReadReq hits
811 system.cpu.dcache.WriteReq_hits::0 8093995 # number of WriteReq hits
812 system.cpu.dcache.WriteReq_hits::total 8093995 # number of WriteReq hits
813 system.cpu.dcache.demand_hits::0 19267844 # number of demand (read+write) hits
814 system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
815 system.cpu.dcache.demand_hits::total 19267844 # number of demand (read+write) hits
816 system.cpu.dcache.overall_hits::0 19267844 # number of overall hits
817 system.cpu.dcache.overall_hits::1 0 # number of overall hits
818 system.cpu.dcache.overall_hits::total 19267844 # number of overall hits
819 system.cpu.dcache.ReadReq_misses::0 2389581 # number of ReadReq misses
820 system.cpu.dcache.ReadReq_misses::total 2389581 # number of ReadReq misses
821 system.cpu.dcache.WriteReq_misses::0 320205 # number of WriteReq misses
822 system.cpu.dcache.WriteReq_misses::total 320205 # number of WriteReq misses
823 system.cpu.dcache.demand_misses::0 2709786 # number of demand (read+write) misses
824 system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
825 system.cpu.dcache.demand_misses::total 2709786 # number of demand (read+write) misses
826 system.cpu.dcache.overall_misses::0 2709786 # number of overall misses
827 system.cpu.dcache.overall_misses::1 0 # number of overall misses
828 system.cpu.dcache.overall_misses::total 2709786 # number of overall misses
829 system.cpu.dcache.ReadReq_miss_latency 35746262500 # number of ReadReq miss cycles
830 system.cpu.dcache.WriteReq_miss_latency 10712131492 # number of WriteReq miss cycles
831 system.cpu.dcache.demand_miss_latency 46458393992 # number of demand (read+write) miss cycles
832 system.cpu.dcache.overall_miss_latency 46458393992 # number of overall miss cycles
833 system.cpu.dcache.ReadReq_accesses::0 13563430 # number of ReadReq accesses(hits+misses)
834 system.cpu.dcache.ReadReq_accesses::total 13563430 # number of ReadReq accesses(hits+misses)
835 system.cpu.dcache.WriteReq_accesses::0 8414200 # number of WriteReq accesses(hits+misses)
836 system.cpu.dcache.WriteReq_accesses::total 8414200 # number of WriteReq accesses(hits+misses)
837 system.cpu.dcache.demand_accesses::0 21977630 # number of demand (read+write) accesses
838 system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
839 system.cpu.dcache.demand_accesses::total 21977630 # number of demand (read+write) accesses
840 system.cpu.dcache.overall_accesses::0 21977630 # number of overall (read+write) accesses
841 system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
842 system.cpu.dcache.overall_accesses::total 21977630 # number of overall (read+write) accesses
843 system.cpu.dcache.ReadReq_miss_rate::0 0.176178 # miss rate for ReadReq accesses
844 system.cpu.dcache.WriteReq_miss_rate::0 0.038055 # miss rate for WriteReq accesses
845 system.cpu.dcache.demand_miss_rate::0 0.123297 # miss rate for demand accesses
846 system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
847 system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
848 system.cpu.dcache.overall_miss_rate::0 0.123297 # miss rate for overall accesses
849 system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
850 system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
851 system.cpu.dcache.ReadReq_avg_miss_latency::0 14959.217746 # average ReadReq miss latency
852 system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
853 system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
854 system.cpu.dcache.WriteReq_avg_miss_latency::0 33453.979457 # average WriteReq miss latency
855 system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
856 system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
857 system.cpu.dcache.demand_avg_miss_latency::0 17144.672676 # average overall miss latency
858 system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
859 system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
860 system.cpu.dcache.overall_avg_miss_latency::0 17144.672676 # average overall miss latency
861 system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
862 system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
863 system.cpu.dcache.blocked_cycles::no_mshrs 27702492 # number of cycles access was blocked
864 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
865 system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked
866 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
867 system.cpu.dcache.avg_blocked_cycles::no_mshrs 5780.987479 # average number of cycles each access was blocked
868 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
869 system.cpu.dcache.fast_writes 0 # number of fast writes performed
870 system.cpu.dcache.cache_copies 0 # number of cache copies performed
871 system.cpu.dcache.writebacks 1550496 # number of writebacks
872 system.cpu.dcache.ReadReq_mshr_hits 1018010 # number of ReadReq MSHR hits
873 system.cpu.dcache.WriteReq_mshr_hits 22803 # number of WriteReq MSHR hits
874 system.cpu.dcache.demand_mshr_hits 1040813 # number of demand (read+write) MSHR hits
875 system.cpu.dcache.overall_mshr_hits 1040813 # number of overall MSHR hits
876 system.cpu.dcache.ReadReq_mshr_misses 1371571 # number of ReadReq MSHR misses
877 system.cpu.dcache.WriteReq_mshr_misses 297402 # number of WriteReq MSHR misses
878 system.cpu.dcache.demand_mshr_misses 1668973 # number of demand (read+write) MSHR misses
879 system.cpu.dcache.overall_mshr_misses 1668973 # number of overall MSHR misses
880 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
881 system.cpu.dcache.ReadReq_mshr_miss_latency 18013626000 # number of ReadReq MSHR miss cycles
882 system.cpu.dcache.WriteReq_mshr_miss_latency 9484899492 # number of WriteReq MSHR miss cycles
883 system.cpu.dcache.demand_mshr_miss_latency 27498525492 # number of demand (read+write) MSHR miss cycles
884 system.cpu.dcache.overall_mshr_miss_latency 27498525492 # number of overall MSHR miss cycles
885 system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85207760000 # number of ReadReq MSHR uncacheable cycles
886 system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1392508500 # number of WriteReq MSHR uncacheable cycles
887 system.cpu.dcache.overall_mshr_uncacheable_latency 86600268500 # number of overall MSHR uncacheable cycles
888 system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.101123 # mshr miss rate for ReadReq accesses
889 system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
890 system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
891 system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035345 # mshr miss rate for WriteReq accesses
892 system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
893 system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
894 system.cpu.dcache.demand_mshr_miss_rate::0 0.075940 # mshr miss rate for demand accesses
895 system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
896 system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
897 system.cpu.dcache.overall_mshr_miss_rate::0 0.075940 # mshr miss rate for overall accesses
898 system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
899 system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
900 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13133.571649 # average ReadReq mshr miss latency
901 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31892.520871 # average WriteReq mshr miss latency
902 system.cpu.dcache.demand_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency
903 system.cpu.dcache.overall_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency
904 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
905 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
906 system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
907 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
908 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
909 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
910 system.cpu.kern.inst.arm 0 # number of arm instructions executed
911 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
913 ---------- End Simulation Statistics ----------
projects / gem5.git / blob