2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.132866 # Number of seconds simulated
4 sim_ticks 5132865528000 # Number of ticks simulated
5 final_tick 5132865528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 61482 # Simulator instruction rate (inst/s)
8 host_op_rate 121532 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 773550742 # Simulator tick rate (ticks/s)
10 host_mem_usage 771808 # Number of bytes of host memory used
11 host_seconds 6635.46 # Real time elapsed on the host
12 sim_insts 407963797 # Number of instructions simulated
13 sim_ops 806422961 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2435200 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 1080768 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10867584 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 14387264 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 1080768 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 1080768 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 9583040 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 9583040 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 38050 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 16887 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 169806 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 224801 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 149735 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 149735 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 474433 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 210558 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 2117255 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2802969 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 210558 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 210558 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 1866996 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 1866996 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 1866996 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 474433 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 210558 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 2117255 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4669965 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.readReqs 224801 # Total number of read requests seen
50 system.physmem.writeReqs 149735 # Total number of write requests seen
51 system.physmem.cpureqs 378687 # Reqs generatd by CPU via cache - shady
52 system.physmem.bytesRead 14387264 # Total number of bytes read from memory
53 system.physmem.bytesWritten 9583040 # Total number of bytes written to memory
54 system.physmem.bytesConsumedRd 14387264 # bytesRead derated as per pkt->getSize()
55 system.physmem.bytesConsumedWr 9583040 # bytesWritten derated as per pkt->getSize()
56 system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q
57 system.physmem.neitherReadNorWrite 4143 # Reqs where no action is needed
58 system.physmem.perBankRdReqs::0 14181 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::1 13154 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::2 13072 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::3 16238 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::4 13617 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::5 13098 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::6 13611 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::7 16569 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::8 13873 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::9 13226 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::10 13363 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::11 15769 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::12 13267 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::13 12663 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis
74 system.physmem.perBankWrReqs::0 9192 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::1 8646 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::2 8408 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::3 11578 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::4 8737 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::5 8467 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::6 8901 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::7 11873 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::8 9014 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::9 8670 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::10 8751 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::11 11255 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::12 8399 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::13 8107 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::14 8591 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::15 11146 # Track writes on a per bank basis
90 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
91 system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
92 system.physmem.totGap 5132865474500 # Total gap between requests
93 system.physmem.readPktSize::0 0 # Categorize read packet sizes
94 system.physmem.readPktSize::1 0 # Categorize read packet sizes
95 system.physmem.readPktSize::2 0 # Categorize read packet sizes
96 system.physmem.readPktSize::3 0 # Categorize read packet sizes
97 system.physmem.readPktSize::4 0 # Categorize read packet sizes
98 system.physmem.readPktSize::5 0 # Categorize read packet sizes
99 system.physmem.readPktSize::6 224801 # Categorize read packet sizes
100 system.physmem.writePktSize::0 0 # Categorize write packet sizes
101 system.physmem.writePktSize::1 0 # Categorize write packet sizes
102 system.physmem.writePktSize::2 0 # Categorize write packet sizes
103 system.physmem.writePktSize::3 0 # Categorize write packet sizes
104 system.physmem.writePktSize::4 0 # Categorize write packet sizes
105 system.physmem.writePktSize::5 0 # Categorize write packet sizes
106 system.physmem.writePktSize::6 149735 # Categorize write packet sizes
107 system.physmem.rdQLenPdf::0 174182 # What read queue length does an incoming req see
108 system.physmem.rdQLenPdf::1 19233 # What read queue length does an incoming req see
109 system.physmem.rdQLenPdf::2 7394 # What read queue length does an incoming req see
110 system.physmem.rdQLenPdf::3 3462 # What read queue length does an incoming req see
111 system.physmem.rdQLenPdf::4 2978 # What read queue length does an incoming req see
112 system.physmem.rdQLenPdf::5 2373 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::6 1871 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::8 1730 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::9 1664 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::10 1149 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::11 1011 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::12 945 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::13 877 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::15 787 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::16 920 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::18 409 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::19 232 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
139 system.physmem.wrQLenPdf::0 5387 # What write queue length does an incoming req see
140 system.physmem.wrQLenPdf::1 5729 # What write queue length does an incoming req see
141 system.physmem.wrQLenPdf::2 6323 # What write queue length does an incoming req see
142 system.physmem.wrQLenPdf::3 6403 # What write queue length does an incoming req see
143 system.physmem.wrQLenPdf::4 6452 # What write queue length does an incoming req see
144 system.physmem.wrQLenPdf::5 6475 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::6 6492 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::7 6496 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::8 6498 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::9 6510 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::10 6510 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::11 6510 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::12 6510 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::13 6510 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::14 6510 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::15 6510 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::16 6510 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::17 6510 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::18 6510 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::19 6510 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::20 6510 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::21 6510 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::22 6510 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::23 1124 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::25 188 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::26 108 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::27 59 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
171 system.physmem.totQLat 4748150250 # Total cycles spent in queuing delays
172 system.physmem.totMemAccLat 9279735250 # Sum of mem lat for all requests
173 system.physmem.totBusLat 1123565000 # Total cycles spent in databus access
174 system.physmem.totBankLat 3408020000 # Total cycles spent in bank access
175 system.physmem.avgQLat 21129.84 # Average queueing delay per request
176 system.physmem.avgBankLat 15166.10 # Average bank access latency per request
177 system.physmem.avgBusLat 5000.00 # Average bus latency per request
178 system.physmem.avgMemAccLat 41295.94 # Average memory access latency
179 system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
180 system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
181 system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
182 system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
183 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
184 system.physmem.busUtil 0.04 # Data bus utilization in percentage
185 system.physmem.avgRdQLen 0.00 # Average read queue length over time
186 system.physmem.avgWrQLen 10.74 # Average write queue length over time
187 system.physmem.readRowHits 193533 # Number of row buffer hits during reads
188 system.physmem.writeRowHits 105971 # Number of row buffer hits during writes
189 system.physmem.readRowHitRate 86.12 # Row buffer hit rate for reads
190 system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes
191 system.physmem.avgGap 13704598.42 # Average gap between requests
192 system.iocache.replacements 47575 # number of replacements
193 system.iocache.tagsinuse 0.104035 # Cycle average of tags in use
194 system.iocache.total_refs 0 # Total number of references to valid blocks.
195 system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.
196 system.iocache.avg_refs 0 # Average number of references to valid blocks.
197 system.iocache.warmup_cycle 4991882227000 # Cycle when the warmup percentage was hit.
198 system.iocache.occ_blocks::pc.south_bridge.ide 0.104035 # Average occupied blocks per requestor
199 system.iocache.occ_percent::pc.south_bridge.ide 0.006502 # Average percentage of cache occupancy
200 system.iocache.occ_percent::total 0.006502 # Average percentage of cache occupancy
201 system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
202 system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
203 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
204 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
205 system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
206 system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
207 system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
208 system.iocache.overall_misses::total 47630 # number of overall misses
209 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142432660 # number of ReadReq miss cycles
210 system.iocache.ReadReq_miss_latency::total 142432660 # number of ReadReq miss cycles
211 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10000305290 # number of WriteReq miss cycles
212 system.iocache.WriteReq_miss_latency::total 10000305290 # number of WriteReq miss cycles
213 system.iocache.demand_miss_latency::pc.south_bridge.ide 10142737950 # number of demand (read+write) miss cycles
214 system.iocache.demand_miss_latency::total 10142737950 # number of demand (read+write) miss cycles
215 system.iocache.overall_miss_latency::pc.south_bridge.ide 10142737950 # number of overall miss cycles
216 system.iocache.overall_miss_latency::total 10142737950 # number of overall miss cycles
217 system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
218 system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
219 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
220 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
221 system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
222 system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
223 system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
224 system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
225 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
226 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
227 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
228 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
229 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
230 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
231 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
232 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
233 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156519.406593 # average ReadReq miss latency
234 system.iocache.ReadReq_avg_miss_latency::total 156519.406593 # average ReadReq miss latency
235 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214047.630351 # average WriteReq miss latency
236 system.iocache.WriteReq_avg_miss_latency::total 214047.630351 # average WriteReq miss latency
237 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency
238 system.iocache.demand_avg_miss_latency::total 212948.518791 # average overall miss latency
239 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 212948.518791 # average overall miss latency
240 system.iocache.overall_avg_miss_latency::total 212948.518791 # average overall miss latency
241 system.iocache.blocked_cycles::no_mshrs 135861 # number of cycles access was blocked
242 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
243 system.iocache.blocked::no_mshrs 12418 # number of cycles access was blocked
244 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
245 system.iocache.avg_blocked_cycles::no_mshrs 10.940651 # average number of cycles each access was blocked
246 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
247 system.iocache.fast_writes 0 # number of fast writes performed
248 system.iocache.cache_copies 0 # number of cache copies performed
249 system.iocache.writebacks::writebacks 46667 # number of writebacks
250 system.iocache.writebacks::total 46667 # number of writebacks
251 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
252 system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
253 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
254 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
255 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses
256 system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses
257 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses
258 system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses
259 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95090941 # number of ReadReq MSHR miss cycles
260 system.iocache.ReadReq_mshr_miss_latency::total 95090941 # number of ReadReq MSHR miss cycles
261 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7569522729 # number of WriteReq MSHR miss cycles
262 system.iocache.WriteReq_mshr_miss_latency::total 7569522729 # number of WriteReq MSHR miss cycles
263 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of demand (read+write) MSHR miss cycles
264 system.iocache.demand_mshr_miss_latency::total 7664613670 # number of demand (read+write) MSHR miss cycles
265 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7664613670 # number of overall MSHR miss cycles
266 system.iocache.overall_mshr_miss_latency::total 7664613670 # number of overall MSHR miss cycles
267 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
268 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
269 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
270 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
271 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
272 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
273 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
274 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
275 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104495.539560 # average ReadReq mshr miss latency
276 system.iocache.ReadReq_avg_mshr_miss_latency::total 104495.539560 # average ReadReq mshr miss latency
277 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162018.894028 # average WriteReq mshr miss latency
278 system.iocache.WriteReq_avg_mshr_miss_latency::total 162018.894028 # average WriteReq mshr miss latency
279 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
280 system.iocache.demand_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
281 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
282 system.iocache.overall_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
283 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
284 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
285 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
286 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
287 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
288 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
289 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
290 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
291 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
292 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
293 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
294 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
295 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
296 system.cpu.branchPred.lookups 86256793 # Number of BP lookups
297 system.cpu.branchPred.condPredicted 86256793 # Number of conditional branches predicted
298 system.cpu.branchPred.condIncorrect 1113068 # Number of conditional branches incorrect
299 system.cpu.branchPred.BTBLookups 81525739 # Number of BTB lookups
300 system.cpu.branchPred.BTBHits 79259204 # Number of BTB hits
301 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
302 system.cpu.branchPred.BTBHitPct 97.219853 # BTB Hit Percentage
303 system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
304 system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
305 system.cpu.numCycles 448546895 # number of cpu cycles simulated
306 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
307 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
308 system.cpu.fetch.icacheStallCycles 27629675 # Number of cycles fetch is stalled on an Icache miss
309 system.cpu.fetch.Insts 426131263 # Number of instructions fetch has processed
310 system.cpu.fetch.Branches 86256793 # Number of branches that fetch encountered
311 system.cpu.fetch.predictedBranches 79259204 # Number of branches that fetch has predicted taken
312 system.cpu.fetch.Cycles 163637829 # Number of cycles fetch has run and was not squashing or blocked
313 system.cpu.fetch.SquashCycles 4743979 # Number of cycles fetch has spent squashing
314 system.cpu.fetch.TlbCycles 122519 # Number of cycles fetch has spent waiting for tlb
315 system.cpu.fetch.BlockedCycles 63152705 # Number of cycles fetch has spent blocked
316 system.cpu.fetch.MiscStallCycles 36413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
317 system.cpu.fetch.PendingTrapStallCycles 51550 # Number of stall cycles due to pending traps
318 system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR
319 system.cpu.fetch.CacheLines 9043434 # Number of cache lines fetched
320 system.cpu.fetch.IcacheSquashes 488848 # Number of outstanding Icache misses that were squashed
321 system.cpu.fetch.ItlbSquashes 3024 # Number of outstanding ITLB misses that were squashed
322 system.cpu.fetch.rateDist::samples 258223805 # Number of instructions fetched each cycle (Total)
323 system.cpu.fetch.rateDist::mean 3.257780 # Number of instructions fetched each cycle (Total)
324 system.cpu.fetch.rateDist::stdev 3.417802 # Number of instructions fetched each cycle (Total)
325 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
326 system.cpu.fetch.rateDist::0 95012138 36.79% 36.79% # Number of instructions fetched each cycle (Total)
327 system.cpu.fetch.rateDist::1 1565899 0.61% 37.40% # Number of instructions fetched each cycle (Total)
328 system.cpu.fetch.rateDist::2 71926197 27.85% 65.26% # Number of instructions fetched each cycle (Total)
329 system.cpu.fetch.rateDist::3 935616 0.36% 65.62% # Number of instructions fetched each cycle (Total)
330 system.cpu.fetch.rateDist::4 1604506 0.62% 66.24% # Number of instructions fetched each cycle (Total)
331 system.cpu.fetch.rateDist::5 2433567 0.94% 67.18% # Number of instructions fetched each cycle (Total)
332 system.cpu.fetch.rateDist::6 1079084 0.42% 67.60% # Number of instructions fetched each cycle (Total)
333 system.cpu.fetch.rateDist::7 1383528 0.54% 68.13% # Number of instructions fetched each cycle (Total)
334 system.cpu.fetch.rateDist::8 82283270 31.87% 100.00% # Number of instructions fetched each cycle (Total)
335 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
336 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
337 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::total 258223805 # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.branchRate 0.192303 # Number of branch fetches per cycle
340 system.cpu.fetch.rate 0.950026 # Number of inst fetches per cycle
341 system.cpu.decode.IdleCycles 31307096 # Number of cycles decode is idle
342 system.cpu.decode.BlockedCycles 60630076 # Number of cycles decode is blocked
343 system.cpu.decode.RunCycles 159436775 # Number of cycles decode is running
344 system.cpu.decode.UnblockCycles 3257103 # Number of cycles decode is unblocking
345 system.cpu.decode.SquashCycles 3592755 # Number of cycles decode is squashing
346 system.cpu.decode.DecodedInsts 838113616 # Number of instructions handled by decode
347 system.cpu.decode.SquashedInsts 880 # Number of squashed instructions handled by decode
348 system.cpu.rename.SquashCycles 3592755 # Number of cycles rename is squashing
349 system.cpu.rename.IdleCycles 34040592 # Number of cycles rename is idle
350 system.cpu.rename.BlockCycles 37476959 # Number of cycles rename is blocking
351 system.cpu.rename.serializeStallCycles 11041434 # count of cycles rename stalled for serializing inst
352 system.cpu.rename.RunCycles 159631550 # Number of cycles rename is running
353 system.cpu.rename.UnblockCycles 12440515 # Number of cycles rename is unblocking
354 system.cpu.rename.RenamedInsts 834468110 # Number of instructions processed by rename
355 system.cpu.rename.ROBFullEvents 19385 # Number of times rename has blocked due to ROB full
356 system.cpu.rename.IQFullEvents 5834152 # Number of times rename has blocked due to IQ full
357 system.cpu.rename.LSQFullEvents 4771877 # Number of times rename has blocked due to LSQ full
358 system.cpu.rename.FullRegisterEvents 8971 # Number of times there has been no free registers
359 system.cpu.rename.RenamedOperands 996054249 # Number of destination operands rename has renamed
360 system.cpu.rename.RenameLookups 1811560635 # Number of register rename lookups that rename has made
361 system.cpu.rename.int_rename_lookups 1811560099 # Number of integer rename lookups
362 system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
363 system.cpu.rename.CommittedMaps 964410768 # Number of HB maps that are committed
364 system.cpu.rename.UndoneMaps 31643474 # Number of HB maps that are undone due to squashing
365 system.cpu.rename.serializingInsts 457361 # count of serializing insts renamed
366 system.cpu.rename.tempSerializingInsts 464527 # count of temporary serializing insts renamed
367 system.cpu.rename.skidInsts 28752334 # count of insts added to the skid buffer
368 system.cpu.memDep0.insertedLoads 17095902 # Number of loads inserted to the mem dependence unit.
369 system.cpu.memDep0.insertedStores 10132687 # Number of stores inserted to the mem dependence unit.
370 system.cpu.memDep0.conflictingLoads 1166436 # Number of conflicting loads.
371 system.cpu.memDep0.conflictingStores 902107 # Number of conflicting stores.
372 system.cpu.iq.iqInstsAdded 828339786 # Number of instructions added to the IQ (excludes non-spec)
373 system.cpu.iq.iqNonSpecInstsAdded 1247404 # Number of non-speculative instructions added to the IQ
374 system.cpu.iq.iqInstsIssued 823331592 # Number of instructions issued
375 system.cpu.iq.iqSquashedInstsIssued 149918 # Number of squashed instructions issued
376 system.cpu.iq.iqSquashedInstsExamined 22245950 # Number of squashed instructions iterated over during squash; mainly for profiling
377 system.cpu.iq.iqSquashedOperandsExamined 33811662 # Number of squashed operands that are examined and possibly removed from graph
378 system.cpu.iq.iqSquashedNonSpecRemoved 194652 # Number of squashed non-spec instructions that were removed
379 system.cpu.iq.issued_per_cycle::samples 258223805 # Number of insts issued each cycle
380 system.cpu.iq.issued_per_cycle::mean 3.188442 # Number of insts issued each cycle
381 system.cpu.iq.issued_per_cycle::stdev 2.385103 # Number of insts issued each cycle
382 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
383 system.cpu.iq.issued_per_cycle::0 71699549 27.77% 27.77% # Number of insts issued each cycle
384 system.cpu.iq.issued_per_cycle::1 15529974 6.01% 33.78% # Number of insts issued each cycle
385 system.cpu.iq.issued_per_cycle::2 10286408 3.98% 37.76% # Number of insts issued each cycle
386 system.cpu.iq.issued_per_cycle::3 7471868 2.89% 40.66% # Number of insts issued each cycle
387 system.cpu.iq.issued_per_cycle::4 75917572 29.40% 70.06% # Number of insts issued each cycle
388 system.cpu.iq.issued_per_cycle::5 3857166 1.49% 71.55% # Number of insts issued each cycle
389 system.cpu.iq.issued_per_cycle::6 72524361 28.09% 99.64% # Number of insts issued each cycle
390 system.cpu.iq.issued_per_cycle::7 784342 0.30% 99.94% # Number of insts issued each cycle
391 system.cpu.iq.issued_per_cycle::8 152565 0.06% 100.00% # Number of insts issued each cycle
392 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
393 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::total 258223805 # Number of insts issued each cycle
396 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
397 system.cpu.iq.fu_full::IntAlu 368681 34.39% 34.39% # attempts to use FU when none available
398 system.cpu.iq.fu_full::IntMult 0 0.00% 34.39% # attempts to use FU when none available
399 system.cpu.iq.fu_full::IntDiv 0 0.00% 34.39% # attempts to use FU when none available
400 system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.39% # attempts to use FU when none available
401 system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.39% # attempts to use FU when none available
402 system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.39% # attempts to use FU when none available
403 system.cpu.iq.fu_full::FloatMult 0 0.00% 34.39% # attempts to use FU when none available
404 system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.39% # attempts to use FU when none available
405 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
406 system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.39% # attempts to use FU when none available
407 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.39% # attempts to use FU when none available
408 system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.39% # attempts to use FU when none available
409 system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.39% # attempts to use FU when none available
410 system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.39% # attempts to use FU when none available
411 system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.39% # attempts to use FU when none available
412 system.cpu.iq.fu_full::SimdMult 0 0.00% 34.39% # attempts to use FU when none available
413 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.39% # attempts to use FU when none available
414 system.cpu.iq.fu_full::SimdShift 0 0.00% 34.39% # attempts to use FU when none available
415 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.39% # attempts to use FU when none available
416 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.39% # attempts to use FU when none available
417 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.39% # attempts to use FU when none available
418 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.39% # attempts to use FU when none available
419 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.39% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.39% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.39% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.39% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.39% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.39% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
426 system.cpu.iq.fu_full::MemRead 552933 51.58% 85.98% # attempts to use FU when none available
427 system.cpu.iq.fu_full::MemWrite 150329 14.02% 100.00% # attempts to use FU when none available
428 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
429 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
430 system.cpu.iq.FU_type_0::No_OpClass 310005 0.04% 0.04% # Type of FU issued
431 system.cpu.iq.FU_type_0::IntAlu 795767028 96.65% 96.69% # Type of FU issued
432 system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
433 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
434 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
435 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
436 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
437 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
438 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
439 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
440 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
441 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
442 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
443 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
444 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
445 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
446 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
447 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
448 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
449 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
450 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
451 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
452 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
453 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
460 system.cpu.iq.FU_type_0::MemRead 17865255 2.17% 98.86% # Type of FU issued
461 system.cpu.iq.FU_type_0::MemWrite 9389304 1.14% 100.00% # Type of FU issued
462 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
463 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
464 system.cpu.iq.FU_type_0::total 823331592 # Type of FU issued
465 system.cpu.iq.rate 1.835553 # Inst issue rate
466 system.cpu.iq.fu_busy_cnt 1071943 # FU busy when requested
467 system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst)
468 system.cpu.iq.int_inst_queue_reads 1906239242 # Number of integer instruction queue reads
469 system.cpu.iq.int_inst_queue_writes 851843261 # Number of integer instruction queue writes
470 system.cpu.iq.int_inst_queue_wakeup_accesses 818849223 # Number of integer instruction queue wakeup accesses
471 system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads
472 system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
473 system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
474 system.cpu.iq.int_alu_accesses 824093432 # Number of integer alu accesses
475 system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses
476 system.cpu.iew.lsq.thread0.forwLoads 1643495 # Number of loads that had data forwarded from stores
477 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
478 system.cpu.iew.lsq.thread0.squashedLoads 3116410 # Number of loads squashed
479 system.cpu.iew.lsq.thread0.ignoredResponses 23570 # Number of memory responses ignored because the instruction is squashed
480 system.cpu.iew.lsq.thread0.memOrderViolation 11612 # Number of memory ordering violations
481 system.cpu.iew.lsq.thread0.squashedStores 1711798 # Number of stores squashed
482 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
483 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
484 system.cpu.iew.lsq.thread0.rescheduledLoads 1932508 # Number of loads that were rescheduled
485 system.cpu.iew.lsq.thread0.cacheBlocked 11844 # Number of times an access to memory failed due to the cache being blocked
486 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
487 system.cpu.iew.iewSquashCycles 3592755 # Number of cycles IEW is squashing
488 system.cpu.iew.iewBlockCycles 26248050 # Number of cycles IEW is blocking
489 system.cpu.iew.iewUnblockCycles 2110636 # Number of cycles IEW is unblocking
490 system.cpu.iew.iewDispatchedInsts 829587190 # Number of instructions dispatched to IQ
491 system.cpu.iew.iewDispSquashedInsts 321004 # Number of squashed instructions skipped by dispatch
492 system.cpu.iew.iewDispLoadInsts 17095902 # Number of dispatched load instructions
493 system.cpu.iew.iewDispStoreInsts 10132687 # Number of dispatched store instructions
494 system.cpu.iew.iewDispNonSpecInsts 717072 # Number of dispatched non-speculative instructions
495 system.cpu.iew.iewIQFullEvents 1612321 # Number of times the IQ has become full, causing a stall
496 system.cpu.iew.iewLSQFullEvents 11848 # Number of times the LSQ has become full, causing a stall
497 system.cpu.iew.memOrderViolationEvents 11612 # Number of memory order violations
498 system.cpu.iew.predictedTakenIncorrect 657039 # Number of branches that were predicted taken incorrectly
499 system.cpu.iew.predictedNotTakenIncorrect 595254 # Number of branches that were predicted not taken incorrectly
500 system.cpu.iew.branchMispredicts 1252293 # Number of branch mispredicts detected at execute
501 system.cpu.iew.iewExecutedInsts 821445338 # Number of executed instructions
502 system.cpu.iew.iewExecLoadInsts 17448687 # Number of load instructions executed
503 system.cpu.iew.iewExecSquashedInsts 1886253 # Number of squashed instructions skipped in execute
504 system.cpu.iew.exec_swp 0 # number of swp insts executed
505 system.cpu.iew.exec_nop 0 # number of nop insts executed
506 system.cpu.iew.exec_refs 26607218 # number of memory reference insts executed
507 system.cpu.iew.exec_branches 83228491 # Number of branches executed
508 system.cpu.iew.exec_stores 9158531 # Number of stores executed
509 system.cpu.iew.exec_rate 1.831348 # Inst execution rate
510 system.cpu.iew.wb_sent 820983226 # cumulative count of insts sent to commit
511 system.cpu.iew.wb_count 818849277 # cumulative count of insts written-back
512 system.cpu.iew.wb_producers 639988645 # num instructions producing a value
513 system.cpu.iew.wb_consumers 1045811759 # num instructions consuming a value
514 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
515 system.cpu.iew.wb_rate 1.825560 # insts written-back per cycle
516 system.cpu.iew.wb_fanout 0.611954 # average fanout of values written-back
517 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
518 system.cpu.commit.commitSquashedInsts 23057499 # The number of squashed insts skipped by commit
519 system.cpu.commit.commitNonSpecStalls 1052750 # The number of times commit has been forced to stall to communicate backwards
520 system.cpu.commit.branchMispredicts 1117600 # The number of times a branch was mispredicted
521 system.cpu.commit.committed_per_cycle::samples 254631050 # Number of insts commited each cycle
522 system.cpu.commit.committed_per_cycle::mean 3.167025 # Number of insts commited each cycle
523 system.cpu.commit.committed_per_cycle::stdev 2.854459 # Number of insts commited each cycle
524 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
525 system.cpu.commit.committed_per_cycle::0 82837862 32.53% 32.53% # Number of insts commited each cycle
526 system.cpu.commit.committed_per_cycle::1 11822724 4.64% 37.18% # Number of insts commited each cycle
527 system.cpu.commit.committed_per_cycle::2 3905327 1.53% 38.71% # Number of insts commited each cycle
528 system.cpu.commit.committed_per_cycle::3 74951929 29.44% 68.14% # Number of insts commited each cycle
529 system.cpu.commit.committed_per_cycle::4 2438342 0.96% 69.10% # Number of insts commited each cycle
530 system.cpu.commit.committed_per_cycle::5 1480698 0.58% 69.68% # Number of insts commited each cycle
531 system.cpu.commit.committed_per_cycle::6 927919 0.36% 70.05% # Number of insts commited each cycle
532 system.cpu.commit.committed_per_cycle::7 70920568 27.85% 97.90% # Number of insts commited each cycle
533 system.cpu.commit.committed_per_cycle::8 5345681 2.10% 100.00% # Number of insts commited each cycle
534 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
535 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::total 254631050 # Number of insts commited each cycle
538 system.cpu.commit.committedInsts 407963797 # Number of instructions committed
539 system.cpu.commit.committedOps 806422961 # Number of ops (including micro ops) committed
540 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
541 system.cpu.commit.refs 22400378 # Number of memory references committed
542 system.cpu.commit.loads 13979489 # Number of loads committed
543 system.cpu.commit.membars 473507 # Number of memory barriers committed
544 system.cpu.commit.branches 82198469 # Number of branches committed
545 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
546 system.cpu.commit.int_insts 735362199 # Number of committed integer instructions.
547 system.cpu.commit.function_calls 0 # Number of function calls committed.
548 system.cpu.commit.bw_lim_events 5345681 # number cycles where commit BW limit reached
549 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
550 system.cpu.rob.rob_reads 1078687614 # The number of ROB reads
551 system.cpu.rob.rob_writes 1662572605 # The number of ROB writes
552 system.cpu.timesIdled 1222238 # Number of times that the entire CPU went into an idle state and unscheduled itself
553 system.cpu.idleCycles 190323090 # Total number of cycles that the CPU has spent unscheduled due to idling
554 system.cpu.quiesceCycles 9817181581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
555 system.cpu.committedInsts 407963797 # Number of Instructions Simulated
556 system.cpu.committedOps 806422961 # Number of Ops (including micro ops) Simulated
557 system.cpu.committedInsts_total 407963797 # Number of Instructions Simulated
558 system.cpu.cpi 1.099477 # CPI: Cycles Per Instruction
559 system.cpu.cpi_total 1.099477 # CPI: Total CPI of All Threads
560 system.cpu.ipc 0.909523 # IPC: Instructions Per Cycle
561 system.cpu.ipc_total 0.909523 # IPC: Total IPC of All Threads
562 system.cpu.int_regfile_reads 1507059295 # number of integer regfile reads
563 system.cpu.int_regfile_writes 977046319 # number of integer regfile writes
564 system.cpu.fp_regfile_reads 54 # number of floating regfile reads
565 system.cpu.misc_regfile_reads 264741173 # number of misc regfile reads
566 system.cpu.misc_regfile_writes 402265 # number of misc regfile writes
567 system.cpu.icache.replacements 1056074 # number of replacements
568 system.cpu.icache.tagsinuse 510.395640 # Cycle average of tags in use
569 system.cpu.icache.total_refs 7921465 # Total number of references to valid blocks.
570 system.cpu.icache.sampled_refs 1056586 # Sample count of references to valid blocks.
571 system.cpu.icache.avg_refs 7.497227 # Average number of references to valid blocks.
572 system.cpu.icache.warmup_cycle 56044666000 # Cycle when the warmup percentage was hit.
573 system.cpu.icache.occ_blocks::cpu.inst 510.395640 # Average occupied blocks per requestor
574 system.cpu.icache.occ_percent::cpu.inst 0.996866 # Average percentage of cache occupancy
575 system.cpu.icache.occ_percent::total 0.996866 # Average percentage of cache occupancy
576 system.cpu.icache.ReadReq_hits::cpu.inst 7921465 # number of ReadReq hits
577 system.cpu.icache.ReadReq_hits::total 7921465 # number of ReadReq hits
578 system.cpu.icache.demand_hits::cpu.inst 7921465 # number of demand (read+write) hits
579 system.cpu.icache.demand_hits::total 7921465 # number of demand (read+write) hits
580 system.cpu.icache.overall_hits::cpu.inst 7921465 # number of overall hits
581 system.cpu.icache.overall_hits::total 7921465 # number of overall hits
582 system.cpu.icache.ReadReq_misses::cpu.inst 1121968 # number of ReadReq misses
583 system.cpu.icache.ReadReq_misses::total 1121968 # number of ReadReq misses
584 system.cpu.icache.demand_misses::cpu.inst 1121968 # number of demand (read+write) misses
585 system.cpu.icache.demand_misses::total 1121968 # number of demand (read+write) misses
586 system.cpu.icache.overall_misses::cpu.inst 1121968 # number of overall misses
587 system.cpu.icache.overall_misses::total 1121968 # number of overall misses
588 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15396039491 # number of ReadReq miss cycles
589 system.cpu.icache.ReadReq_miss_latency::total 15396039491 # number of ReadReq miss cycles
590 system.cpu.icache.demand_miss_latency::cpu.inst 15396039491 # number of demand (read+write) miss cycles
591 system.cpu.icache.demand_miss_latency::total 15396039491 # number of demand (read+write) miss cycles
592 system.cpu.icache.overall_miss_latency::cpu.inst 15396039491 # number of overall miss cycles
593 system.cpu.icache.overall_miss_latency::total 15396039491 # number of overall miss cycles
594 system.cpu.icache.ReadReq_accesses::cpu.inst 9043433 # number of ReadReq accesses(hits+misses)
595 system.cpu.icache.ReadReq_accesses::total 9043433 # number of ReadReq accesses(hits+misses)
596 system.cpu.icache.demand_accesses::cpu.inst 9043433 # number of demand (read+write) accesses
597 system.cpu.icache.demand_accesses::total 9043433 # number of demand (read+write) accesses
598 system.cpu.icache.overall_accesses::cpu.inst 9043433 # number of overall (read+write) accesses
599 system.cpu.icache.overall_accesses::total 9043433 # number of overall (read+write) accesses
600 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124064 # miss rate for ReadReq accesses
601 system.cpu.icache.ReadReq_miss_rate::total 0.124064 # miss rate for ReadReq accesses
602 system.cpu.icache.demand_miss_rate::cpu.inst 0.124064 # miss rate for demand accesses
603 system.cpu.icache.demand_miss_rate::total 0.124064 # miss rate for demand accesses
604 system.cpu.icache.overall_miss_rate::cpu.inst 0.124064 # miss rate for overall accesses
605 system.cpu.icache.overall_miss_rate::total 0.124064 # miss rate for overall accesses
606 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13722.351699 # average ReadReq miss latency
607 system.cpu.icache.ReadReq_avg_miss_latency::total 13722.351699 # average ReadReq miss latency
608 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency
609 system.cpu.icache.demand_avg_miss_latency::total 13722.351699 # average overall miss latency
610 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency
611 system.cpu.icache.overall_avg_miss_latency::total 13722.351699 # average overall miss latency
612 system.cpu.icache.blocked_cycles::no_mshrs 11326 # number of cycles access was blocked
613 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
614 system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked
615 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
616 system.cpu.icache.avg_blocked_cycles::no_mshrs 43.229008 # average number of cycles each access was blocked
617 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
618 system.cpu.icache.fast_writes 0 # number of fast writes performed
619 system.cpu.icache.cache_copies 0 # number of cache copies performed
620 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62943 # number of ReadReq MSHR hits
621 system.cpu.icache.ReadReq_mshr_hits::total 62943 # number of ReadReq MSHR hits
622 system.cpu.icache.demand_mshr_hits::cpu.inst 62943 # number of demand (read+write) MSHR hits
623 system.cpu.icache.demand_mshr_hits::total 62943 # number of demand (read+write) MSHR hits
624 system.cpu.icache.overall_mshr_hits::cpu.inst 62943 # number of overall MSHR hits
625 system.cpu.icache.overall_mshr_hits::total 62943 # number of overall MSHR hits
626 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1059025 # number of ReadReq MSHR misses
627 system.cpu.icache.ReadReq_mshr_misses::total 1059025 # number of ReadReq MSHR misses
628 system.cpu.icache.demand_mshr_misses::cpu.inst 1059025 # number of demand (read+write) MSHR misses
629 system.cpu.icache.demand_mshr_misses::total 1059025 # number of demand (read+write) MSHR misses
630 system.cpu.icache.overall_mshr_misses::cpu.inst 1059025 # number of overall MSHR misses
631 system.cpu.icache.overall_mshr_misses::total 1059025 # number of overall MSHR misses
632 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12680665992 # number of ReadReq MSHR miss cycles
633 system.cpu.icache.ReadReq_mshr_miss_latency::total 12680665992 # number of ReadReq MSHR miss cycles
634 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12680665992 # number of demand (read+write) MSHR miss cycles
635 system.cpu.icache.demand_mshr_miss_latency::total 12680665992 # number of demand (read+write) MSHR miss cycles
636 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12680665992 # number of overall MSHR miss cycles
637 system.cpu.icache.overall_mshr_miss_latency::total 12680665992 # number of overall MSHR miss cycles
638 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for ReadReq accesses
639 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117104 # mshr miss rate for ReadReq accesses
640 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for demand accesses
641 system.cpu.icache.demand_mshr_miss_rate::total 0.117104 # mshr miss rate for demand accesses
642 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for overall accesses
643 system.cpu.icache.overall_mshr_miss_rate::total 0.117104 # mshr miss rate for overall accesses
644 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11973.906180 # average ReadReq mshr miss latency
645 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11973.906180 # average ReadReq mshr miss latency
646 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11973.906180 # average overall mshr miss latency
647 system.cpu.icache.demand_avg_mshr_miss_latency::total 11973.906180 # average overall mshr miss latency
648 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11973.906180 # average overall mshr miss latency
649 system.cpu.icache.overall_avg_mshr_miss_latency::total 11973.906180 # average overall mshr miss latency
650 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
651 system.cpu.itb_walker_cache.replacements 9902 # number of replacements
652 system.cpu.itb_walker_cache.tagsinuse 6.007248 # Cycle average of tags in use
653 system.cpu.itb_walker_cache.total_refs 25368 # Total number of references to valid blocks.
654 system.cpu.itb_walker_cache.sampled_refs 9915 # Sample count of references to valid blocks.
655 system.cpu.itb_walker_cache.avg_refs 2.558548 # Average number of references to valid blocks.
656 system.cpu.itb_walker_cache.warmup_cycle 5106962474500 # Cycle when the warmup percentage was hit.
657 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.007248 # Average occupied blocks per requestor
658 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375453 # Average percentage of cache occupancy
659 system.cpu.itb_walker_cache.occ_percent::total 0.375453 # Average percentage of cache occupancy
660 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25400 # number of ReadReq hits
661 system.cpu.itb_walker_cache.ReadReq_hits::total 25400 # number of ReadReq hits
662 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
663 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
664 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25402 # number of demand (read+write) hits
665 system.cpu.itb_walker_cache.demand_hits::total 25402 # number of demand (read+write) hits
666 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25402 # number of overall hits
667 system.cpu.itb_walker_cache.overall_hits::total 25402 # number of overall hits
668 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10789 # number of ReadReq misses
669 system.cpu.itb_walker_cache.ReadReq_misses::total 10789 # number of ReadReq misses
670 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10789 # number of demand (read+write) misses
671 system.cpu.itb_walker_cache.demand_misses::total 10789 # number of demand (read+write) misses
672 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10789 # number of overall misses
673 system.cpu.itb_walker_cache.overall_misses::total 10789 # number of overall misses
674 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118480500 # number of ReadReq miss cycles
675 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118480500 # number of ReadReq miss cycles
676 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118480500 # number of demand (read+write) miss cycles
677 system.cpu.itb_walker_cache.demand_miss_latency::total 118480500 # number of demand (read+write) miss cycles
678 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118480500 # number of overall miss cycles
679 system.cpu.itb_walker_cache.overall_miss_latency::total 118480500 # number of overall miss cycles
680 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36189 # number of ReadReq accesses(hits+misses)
681 system.cpu.itb_walker_cache.ReadReq_accesses::total 36189 # number of ReadReq accesses(hits+misses)
682 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
683 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
684 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36191 # number of demand (read+write) accesses
685 system.cpu.itb_walker_cache.demand_accesses::total 36191 # number of demand (read+write) accesses
686 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36191 # number of overall (read+write) accesses
687 system.cpu.itb_walker_cache.overall_accesses::total 36191 # number of overall (read+write) accesses
688 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298129 # miss rate for ReadReq accesses
689 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298129 # miss rate for ReadReq accesses
690 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298113 # miss rate for demand accesses
691 system.cpu.itb_walker_cache.demand_miss_rate::total 0.298113 # miss rate for demand accesses
692 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298113 # miss rate for overall accesses
693 system.cpu.itb_walker_cache.overall_miss_rate::total 0.298113 # miss rate for overall accesses
694 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10981.601631 # average ReadReq miss latency
695 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10981.601631 # average ReadReq miss latency
696 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency
697 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10981.601631 # average overall miss latency
698 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10981.601631 # average overall miss latency
699 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10981.601631 # average overall miss latency
700 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
701 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
702 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
703 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
704 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
705 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
706 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
707 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
708 system.cpu.itb_walker_cache.writebacks::writebacks 2074 # number of writebacks
709 system.cpu.itb_walker_cache.writebacks::total 2074 # number of writebacks
710 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10789 # number of ReadReq MSHR misses
711 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10789 # number of ReadReq MSHR misses
712 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10789 # number of demand (read+write) MSHR misses
713 system.cpu.itb_walker_cache.demand_mshr_misses::total 10789 # number of demand (read+write) MSHR misses
714 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10789 # number of overall MSHR misses
715 system.cpu.itb_walker_cache.overall_mshr_misses::total 10789 # number of overall MSHR misses
716 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96902500 # number of ReadReq MSHR miss cycles
717 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96902500 # number of ReadReq MSHR miss cycles
718 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96902500 # number of demand (read+write) MSHR miss cycles
719 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96902500 # number of demand (read+write) MSHR miss cycles
720 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96902500 # number of overall MSHR miss cycles
721 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96902500 # number of overall MSHR miss cycles
722 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298129 # mshr miss rate for ReadReq accesses
723 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298129 # mshr miss rate for ReadReq accesses
724 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for demand accesses
725 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298113 # mshr miss rate for demand accesses
726 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298113 # mshr miss rate for overall accesses
727 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298113 # mshr miss rate for overall accesses
728 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average ReadReq mshr miss latency
729 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8981.601631 # average ReadReq mshr miss latency
730 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency
731 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency
732 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8981.601631 # average overall mshr miss latency
733 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8981.601631 # average overall mshr miss latency
734 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
735 system.cpu.dtb_walker_cache.replacements 112679 # number of replacements
736 system.cpu.dtb_walker_cache.tagsinuse 13.888368 # Cycle average of tags in use
737 system.cpu.dtb_walker_cache.total_refs 129664 # Total number of references to valid blocks.
738 system.cpu.dtb_walker_cache.sampled_refs 112694 # Sample count of references to valid blocks.
739 system.cpu.dtb_walker_cache.avg_refs 1.150585 # Average number of references to valid blocks.
740 system.cpu.dtb_walker_cache.warmup_cycle 5099752322000 # Cycle when the warmup percentage was hit.
741 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.888368 # Average occupied blocks per requestor
742 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.868023 # Average percentage of cache occupancy
743 system.cpu.dtb_walker_cache.occ_percent::total 0.868023 # Average percentage of cache occupancy
744 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 129683 # number of ReadReq hits
745 system.cpu.dtb_walker_cache.ReadReq_hits::total 129683 # number of ReadReq hits
746 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 129683 # number of demand (read+write) hits
747 system.cpu.dtb_walker_cache.demand_hits::total 129683 # number of demand (read+write) hits
748 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 129683 # number of overall hits
749 system.cpu.dtb_walker_cache.overall_hits::total 129683 # number of overall hits
750 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113702 # number of ReadReq misses
751 system.cpu.dtb_walker_cache.ReadReq_misses::total 113702 # number of ReadReq misses
752 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113702 # number of demand (read+write) misses
753 system.cpu.dtb_walker_cache.demand_misses::total 113702 # number of demand (read+write) misses
754 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113702 # number of overall misses
755 system.cpu.dtb_walker_cache.overall_misses::total 113702 # number of overall misses
756 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1421375500 # number of ReadReq miss cycles
757 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1421375500 # number of ReadReq miss cycles
758 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1421375500 # number of demand (read+write) miss cycles
759 system.cpu.dtb_walker_cache.demand_miss_latency::total 1421375500 # number of demand (read+write) miss cycles
760 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1421375500 # number of overall miss cycles
761 system.cpu.dtb_walker_cache.overall_miss_latency::total 1421375500 # number of overall miss cycles
762 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243385 # number of ReadReq accesses(hits+misses)
763 system.cpu.dtb_walker_cache.ReadReq_accesses::total 243385 # number of ReadReq accesses(hits+misses)
764 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243385 # number of demand (read+write) accesses
765 system.cpu.dtb_walker_cache.demand_accesses::total 243385 # number of demand (read+write) accesses
766 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243385 # number of overall (read+write) accesses
767 system.cpu.dtb_walker_cache.overall_accesses::total 243385 # number of overall (read+write) accesses
768 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.467169 # miss rate for ReadReq accesses
769 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.467169 # miss rate for ReadReq accesses
770 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.467169 # miss rate for demand accesses
771 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.467169 # miss rate for demand accesses
772 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.467169 # miss rate for overall accesses
773 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.467169 # miss rate for overall accesses
774 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12500.883889 # average ReadReq miss latency
775 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12500.883889 # average ReadReq miss latency
776 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
777 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12500.883889 # average overall miss latency
778 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
779 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12500.883889 # average overall miss latency
780 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
781 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
782 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
783 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
784 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
785 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
786 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
787 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
788 system.cpu.dtb_walker_cache.writebacks::writebacks 35808 # number of writebacks
789 system.cpu.dtb_walker_cache.writebacks::total 35808 # number of writebacks
790 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113702 # number of ReadReq MSHR misses
791 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113702 # number of ReadReq MSHR misses
792 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113702 # number of demand (read+write) MSHR misses
793 system.cpu.dtb_walker_cache.demand_mshr_misses::total 113702 # number of demand (read+write) MSHR misses
794 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113702 # number of overall MSHR misses
795 system.cpu.dtb_walker_cache.overall_mshr_misses::total 113702 # number of overall MSHR misses
796 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of ReadReq MSHR miss cycles
797 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1193971500 # number of ReadReq MSHR miss cycles
798 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of demand (read+write) MSHR miss cycles
799 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1193971500 # number of demand (read+write) MSHR miss cycles
800 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1193971500 # number of overall MSHR miss cycles
801 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1193971500 # number of overall MSHR miss cycles
802 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for ReadReq accesses
803 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.467169 # mshr miss rate for ReadReq accesses
804 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for demand accesses
805 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.467169 # mshr miss rate for demand accesses
806 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.467169 # mshr miss rate for overall accesses
807 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.467169 # mshr miss rate for overall accesses
808 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average ReadReq mshr miss latency
809 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10500.883889 # average ReadReq mshr miss latency
810 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average overall mshr miss latency
811 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10500.883889 # average overall mshr miss latency
812 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889 # average overall mshr miss latency
813 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10500.883889 # average overall mshr miss latency
814 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
815 system.cpu.dcache.replacements 1659172 # number of replacements
816 system.cpu.dcache.tagsinuse 511.998283 # Cycle average of tags in use
817 system.cpu.dcache.total_refs 19096669 # Total number of references to valid blocks.
818 system.cpu.dcache.sampled_refs 1659684 # Sample count of references to valid blocks.
819 system.cpu.dcache.avg_refs 11.506208 # Average number of references to valid blocks.
820 system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit.
821 system.cpu.dcache.occ_blocks::cpu.data 511.998283 # Average occupied blocks per requestor
822 system.cpu.dcache.occ_percent::cpu.data 0.999997 # Average percentage of cache occupancy
823 system.cpu.dcache.occ_percent::total 0.999997 # Average percentage of cache occupancy
824 system.cpu.dcache.ReadReq_hits::cpu.data 10998697 # number of ReadReq hits
825 system.cpu.dcache.ReadReq_hits::total 10998697 # number of ReadReq hits
826 system.cpu.dcache.WriteReq_hits::cpu.data 8092860 # number of WriteReq hits
827 system.cpu.dcache.WriteReq_hits::total 8092860 # number of WriteReq hits
828 system.cpu.dcache.demand_hits::cpu.data 19091557 # number of demand (read+write) hits
829 system.cpu.dcache.demand_hits::total 19091557 # number of demand (read+write) hits
830 system.cpu.dcache.overall_hits::cpu.data 19091557 # number of overall hits
831 system.cpu.dcache.overall_hits::total 19091557 # number of overall hits
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833 system.cpu.dcache.ReadReq_misses::total 2244277 # number of ReadReq misses
834 system.cpu.dcache.WriteReq_misses::cpu.data 318772 # number of WriteReq misses
835 system.cpu.dcache.WriteReq_misses::total 318772 # number of WriteReq misses
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837 system.cpu.dcache.demand_misses::total 2563049 # number of demand (read+write) misses
838 system.cpu.dcache.overall_misses::cpu.data 2563049 # number of overall misses
839 system.cpu.dcache.overall_misses::total 2563049 # number of overall misses
840 system.cpu.dcache.ReadReq_miss_latency::cpu.data 32186629000 # number of ReadReq miss cycles
841 system.cpu.dcache.ReadReq_miss_latency::total 32186629000 # number of ReadReq miss cycles
842 system.cpu.dcache.WriteReq_miss_latency::cpu.data 9715417494 # number of WriteReq miss cycles
843 system.cpu.dcache.WriteReq_miss_latency::total 9715417494 # number of WriteReq miss cycles
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845 system.cpu.dcache.demand_miss_latency::total 41902046494 # number of demand (read+write) miss cycles
846 system.cpu.dcache.overall_miss_latency::cpu.data 41902046494 # number of overall miss cycles
847 system.cpu.dcache.overall_miss_latency::total 41902046494 # number of overall miss cycles
848 system.cpu.dcache.ReadReq_accesses::cpu.data 13242974 # number of ReadReq accesses(hits+misses)
849 system.cpu.dcache.ReadReq_accesses::total 13242974 # number of ReadReq accesses(hits+misses)
850 system.cpu.dcache.WriteReq_accesses::cpu.data 8411632 # number of WriteReq accesses(hits+misses)
851 system.cpu.dcache.WriteReq_accesses::total 8411632 # number of WriteReq accesses(hits+misses)
852 system.cpu.dcache.demand_accesses::cpu.data 21654606 # number of demand (read+write) accesses
853 system.cpu.dcache.demand_accesses::total 21654606 # number of demand (read+write) accesses
854 system.cpu.dcache.overall_accesses::cpu.data 21654606 # number of overall (read+write) accesses
855 system.cpu.dcache.overall_accesses::total 21654606 # number of overall (read+write) accesses
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857 system.cpu.dcache.ReadReq_miss_rate::total 0.169469 # miss rate for ReadReq accesses
858 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037897 # miss rate for WriteReq accesses
859 system.cpu.dcache.WriteReq_miss_rate::total 0.037897 # miss rate for WriteReq accesses
860 system.cpu.dcache.demand_miss_rate::cpu.data 0.118360 # miss rate for demand accesses
861 system.cpu.dcache.demand_miss_rate::total 0.118360 # miss rate for demand accesses
862 system.cpu.dcache.overall_miss_rate::cpu.data 0.118360 # miss rate for overall accesses
863 system.cpu.dcache.overall_miss_rate::total 0.118360 # miss rate for overall accesses
864 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14341.647221 # average ReadReq miss latency
865 system.cpu.dcache.ReadReq_avg_miss_latency::total 14341.647221 # average ReadReq miss latency
866 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30477.637603 # average WriteReq miss latency
867 system.cpu.dcache.WriteReq_avg_miss_latency::total 30477.637603 # average WriteReq miss latency
868 system.cpu.dcache.demand_avg_miss_latency::cpu.data 16348.515574 # average overall miss latency
869 system.cpu.dcache.demand_avg_miss_latency::total 16348.515574 # average overall miss latency
870 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16348.515574 # average overall miss latency
871 system.cpu.dcache.overall_avg_miss_latency::total 16348.515574 # average overall miss latency
872 system.cpu.dcache.blocked_cycles::no_mshrs 394709 # number of cycles access was blocked
873 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
874 system.cpu.dcache.blocked::no_mshrs 43025 # number of cycles access was blocked
875 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
876 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.173945 # average number of cycles each access was blocked
877 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
878 system.cpu.dcache.fast_writes 0 # number of fast writes performed
879 system.cpu.dcache.cache_copies 0 # number of cache copies performed
880 system.cpu.dcache.writebacks::writebacks 1560811 # number of writebacks
881 system.cpu.dcache.writebacks::total 1560811 # number of writebacks
882 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 872480 # number of ReadReq MSHR hits
883 system.cpu.dcache.ReadReq_mshr_hits::total 872480 # number of ReadReq MSHR hits
884 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26264 # number of WriteReq MSHR hits
885 system.cpu.dcache.WriteReq_mshr_hits::total 26264 # number of WriteReq MSHR hits
886 system.cpu.dcache.demand_mshr_hits::cpu.data 898744 # number of demand (read+write) MSHR hits
887 system.cpu.dcache.demand_mshr_hits::total 898744 # number of demand (read+write) MSHR hits
888 system.cpu.dcache.overall_mshr_hits::cpu.data 898744 # number of overall MSHR hits
889 system.cpu.dcache.overall_mshr_hits::total 898744 # number of overall MSHR hits
890 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371797 # number of ReadReq MSHR misses
891 system.cpu.dcache.ReadReq_mshr_misses::total 1371797 # number of ReadReq MSHR misses
892 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292508 # number of WriteReq MSHR misses
893 system.cpu.dcache.WriteReq_mshr_misses::total 292508 # number of WriteReq MSHR misses
894 system.cpu.dcache.demand_mshr_misses::cpu.data 1664305 # number of demand (read+write) MSHR misses
895 system.cpu.dcache.demand_mshr_misses::total 1664305 # number of demand (read+write) MSHR misses
896 system.cpu.dcache.overall_mshr_misses::cpu.data 1664305 # number of overall MSHR misses
897 system.cpu.dcache.overall_mshr_misses::total 1664305 # number of overall MSHR misses
898 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17453179000 # number of ReadReq MSHR miss cycles
899 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17453179000 # number of ReadReq MSHR miss cycles
900 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8875888494 # number of WriteReq MSHR miss cycles
901 system.cpu.dcache.WriteReq_mshr_miss_latency::total 8875888494 # number of WriteReq MSHR miss cycles
902 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26329067494 # number of demand (read+write) MSHR miss cycles
903 system.cpu.dcache.demand_mshr_miss_latency::total 26329067494 # number of demand (read+write) MSHR miss cycles
904 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26329067494 # number of overall MSHR miss cycles
905 system.cpu.dcache.overall_mshr_miss_latency::total 26329067494 # number of overall MSHR miss cycles
906 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97298479500 # number of ReadReq MSHR uncacheable cycles
907 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97298479500 # number of ReadReq MSHR uncacheable cycles
908 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473755000 # number of WriteReq MSHR uncacheable cycles
909 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473755000 # number of WriteReq MSHR uncacheable cycles
910 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99772234500 # number of overall MSHR uncacheable cycles
911 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99772234500 # number of overall MSHR uncacheable cycles
912 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103587 # mshr miss rate for ReadReq accesses
913 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103587 # mshr miss rate for ReadReq accesses
914 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034774 # mshr miss rate for WriteReq accesses
915 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034774 # mshr miss rate for WriteReq accesses
916 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076857 # mshr miss rate for demand accesses
917 system.cpu.dcache.demand_mshr_miss_rate::total 0.076857 # mshr miss rate for demand accesses
918 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076857 # mshr miss rate for overall accesses
919 system.cpu.dcache.overall_mshr_miss_rate::total 0.076857 # mshr miss rate for overall accesses
920 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12722.858411 # average ReadReq mshr miss latency
921 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12722.858411 # average ReadReq mshr miss latency
922 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30344.088004 # average WriteReq mshr miss latency
923 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30344.088004 # average WriteReq mshr miss latency
924 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15819.857234 # average overall mshr miss latency
925 system.cpu.dcache.demand_avg_mshr_miss_latency::total 15819.857234 # average overall mshr miss latency
926 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15819.857234 # average overall mshr miss latency
927 system.cpu.dcache.overall_avg_mshr_miss_latency::total 15819.857234 # average overall mshr miss latency
928 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
929 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
930 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
931 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
932 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
933 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
934 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
935 system.cpu.l2cache.replacements 113709 # number of replacements
936 system.cpu.l2cache.tagsinuse 64835.556178 # Cycle average of tags in use
937 system.cpu.l2cache.total_refs 3943740 # Total number of references to valid blocks.
938 system.cpu.l2cache.sampled_refs 177736 # Sample count of references to valid blocks.
939 system.cpu.l2cache.avg_refs 22.188752 # Average number of references to valid blocks.
940 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
941 system.cpu.l2cache.occ_blocks::writebacks 50100.135073 # Average occupied blocks per requestor
942 system.cpu.l2cache.occ_blocks::cpu.dtb.walker 8.974222 # Average occupied blocks per requestor
943 system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131215 # Average occupied blocks per requestor
944 system.cpu.l2cache.occ_blocks::cpu.inst 3272.117566 # Average occupied blocks per requestor
945 system.cpu.l2cache.occ_blocks::cpu.data 11454.198102 # Average occupied blocks per requestor
946 system.cpu.l2cache.occ_percent::writebacks 0.764467 # Average percentage of cache occupancy
947 system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000137 # Average percentage of cache occupancy
948 system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
949 system.cpu.l2cache.occ_percent::cpu.inst 0.049929 # Average percentage of cache occupancy
950 system.cpu.l2cache.occ_percent::cpu.data 0.174777 # Average percentage of cache occupancy
951 system.cpu.l2cache.occ_percent::total 0.989312 # Average percentage of cache occupancy
952 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 105558 # number of ReadReq hits
953 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8113 # number of ReadReq hits
954 system.cpu.l2cache.ReadReq_hits::cpu.inst 1039658 # number of ReadReq hits
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956 system.cpu.l2cache.ReadReq_hits::total 2487057 # number of ReadReq hits
957 system.cpu.l2cache.Writeback_hits::writebacks 1598693 # number of Writeback hits
958 system.cpu.l2cache.Writeback_hits::total 1598693 # number of Writeback hits
959 system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits
960 system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits
961 system.cpu.l2cache.ReadExReq_hits::cpu.data 154593 # number of ReadExReq hits
962 system.cpu.l2cache.ReadExReq_hits::total 154593 # number of ReadExReq hits
963 system.cpu.l2cache.demand_hits::cpu.dtb.walker 105558 # number of demand (read+write) hits
964 system.cpu.l2cache.demand_hits::cpu.itb.walker 8113 # number of demand (read+write) hits
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968 system.cpu.l2cache.overall_hits::cpu.dtb.walker 105558 # number of overall hits
969 system.cpu.l2cache.overall_hits::cpu.itb.walker 8113 # number of overall hits
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979 system.cpu.l2cache.UpgradeReq_misses::total 3866 # number of UpgradeReq misses
980 system.cpu.l2cache.ReadExReq_misses::cpu.data 133854 # number of ReadExReq misses
981 system.cpu.l2cache.ReadExReq_misses::total 133854 # number of ReadExReq misses
982 system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses
983 system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
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987 system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses
988 system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
989 system.cpu.l2cache.overall_misses::cpu.inst 16888 # number of overall misses
990 system.cpu.l2cache.overall_misses::cpu.data 170754 # number of overall misses
991 system.cpu.l2cache.overall_misses::total 187700 # number of overall misses
992 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4568000 # number of ReadReq miss cycles
993 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles
994 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1172288500 # number of ReadReq miss cycles
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997 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17446500 # number of UpgradeReq miss cycles
998 system.cpu.l2cache.UpgradeReq_miss_latency::total 17446500 # number of UpgradeReq miss cycles
999 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6941993500 # number of ReadExReq miss cycles
1000 system.cpu.l2cache.ReadExReq_miss_latency::total 6941993500 # number of ReadExReq miss cycles
1001 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4568000 # number of demand (read+write) miss cycles
1002 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles
1003 system.cpu.l2cache.demand_miss_latency::cpu.inst 1172288500 # number of demand (read+write) miss cycles
1004 system.cpu.l2cache.demand_miss_latency::cpu.data 9460176999 # number of demand (read+write) miss cycles
1005 system.cpu.l2cache.demand_miss_latency::total 10637422999 # number of demand (read+write) miss cycles
1006 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4568000 # number of overall miss cycles
1007 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles
1008 system.cpu.l2cache.overall_miss_latency::cpu.inst 1172288500 # number of overall miss cycles
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1010 system.cpu.l2cache.overall_miss_latency::total 10637422999 # number of overall miss cycles
1011 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 105610 # number of ReadReq accesses(hits+misses)
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1015 system.cpu.l2cache.ReadReq_accesses::total 2540903 # number of ReadReq accesses(hits+misses)
1016 system.cpu.l2cache.Writeback_accesses::writebacks 1598693 # number of Writeback accesses(hits+misses)
1017 system.cpu.l2cache.Writeback_accesses::total 1598693 # number of Writeback accesses(hits+misses)
1018 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4187 # number of UpgradeReq accesses(hits+misses)
1019 system.cpu.l2cache.UpgradeReq_accesses::total 4187 # number of UpgradeReq accesses(hits+misses)
1020 system.cpu.l2cache.ReadExReq_accesses::cpu.data 288447 # number of ReadExReq accesses(hits+misses)
1021 system.cpu.l2cache.ReadExReq_accesses::total 288447 # number of ReadExReq accesses(hits+misses)
1022 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 105610 # number of demand (read+write) accesses
1023 system.cpu.l2cache.demand_accesses::cpu.itb.walker 8119 # number of demand (read+write) accesses
1024 system.cpu.l2cache.demand_accesses::cpu.inst 1056546 # number of demand (read+write) accesses
1025 system.cpu.l2cache.demand_accesses::cpu.data 1659075 # number of demand (read+write) accesses
1026 system.cpu.l2cache.demand_accesses::total 2829350 # number of demand (read+write) accesses
1027 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 105610 # number of overall (read+write) accesses
1028 system.cpu.l2cache.overall_accesses::cpu.itb.walker 8119 # number of overall (read+write) accesses
1029 system.cpu.l2cache.overall_accesses::cpu.inst 1056546 # number of overall (read+write) accesses
1030 system.cpu.l2cache.overall_accesses::cpu.data 1659075 # number of overall (read+write) accesses
1031 system.cpu.l2cache.overall_accesses::total 2829350 # number of overall (read+write) accesses
1032 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000492 # miss rate for ReadReq accesses
1033 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000739 # miss rate for ReadReq accesses
1034 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015984 # miss rate for ReadReq accesses
1035 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026922 # miss rate for ReadReq accesses
1036 system.cpu.l2cache.ReadReq_miss_rate::total 0.021192 # miss rate for ReadReq accesses
1037 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.923334 # miss rate for UpgradeReq accesses
1038 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.923334 # miss rate for UpgradeReq accesses
1039 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464051 # miss rate for ReadExReq accesses
1040 system.cpu.l2cache.ReadExReq_miss_rate::total 0.464051 # miss rate for ReadExReq accesses
1041 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000492 # miss rate for demand accesses
1042 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000739 # miss rate for demand accesses
1043 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015984 # miss rate for demand accesses
1044 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102921 # miss rate for demand accesses
1045 system.cpu.l2cache.demand_miss_rate::total 0.066340 # miss rate for demand accesses
1046 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000492 # miss rate for overall accesses
1047 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000739 # miss rate for overall accesses
1048 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015984 # miss rate for overall accesses
1049 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102921 # miss rate for overall accesses
1050 system.cpu.l2cache.overall_miss_rate::total 0.066340 # miss rate for overall accesses
1051 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87846.153846 # average ReadReq miss latency
1052 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency
1053 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69415.472525 # average ReadReq miss latency
1054 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68243.455257 # average ReadReq miss latency
1055 system.cpu.l2cache.ReadReq_avg_miss_latency::total 68629.601066 # average ReadReq miss latency
1056 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4512.803932 # average UpgradeReq miss latency
1057 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4512.803932 # average UpgradeReq miss latency
1058 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51862.428467 # average ReadExReq miss latency
1059 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51862.428467 # average ReadExReq miss latency
1060 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87846.153846 # average overall miss latency
1061 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
1062 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69415.472525 # average overall miss latency
1063 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55402.374170 # average overall miss latency
1064 system.cpu.l2cache.demand_avg_miss_latency::total 56672.472025 # average overall miss latency
1065 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87846.153846 # average overall miss latency
1066 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
1067 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69415.472525 # average overall miss latency
1068 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55402.374170 # average overall miss latency
1069 system.cpu.l2cache.overall_avg_miss_latency::total 56672.472025 # average overall miss latency
1070 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1071 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1072 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1073 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1074 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1075 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1076 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1077 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1078 system.cpu.l2cache.writebacks::writebacks 103068 # number of writebacks
1079 system.cpu.l2cache.writebacks::total 103068 # number of writebacks
1080 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1081 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1082 system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
1083 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1084 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1085 system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
1086 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1087 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1088 system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
1089 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses
1090 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
1091 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16887 # number of ReadReq MSHR misses
1092 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36899 # number of ReadReq MSHR misses
1093 system.cpu.l2cache.ReadReq_mshr_misses::total 53844 # number of ReadReq MSHR misses
1094 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3866 # number of UpgradeReq MSHR misses
1095 system.cpu.l2cache.UpgradeReq_mshr_misses::total 3866 # number of UpgradeReq MSHR misses
1096 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133854 # number of ReadExReq MSHR misses
1097 system.cpu.l2cache.ReadExReq_mshr_misses::total 133854 # number of ReadExReq MSHR misses
1098 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses
1099 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
1100 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16887 # number of demand (read+write) MSHR misses
1101 system.cpu.l2cache.demand_mshr_misses::cpu.data 170753 # number of demand (read+write) MSHR misses
1102 system.cpu.l2cache.demand_mshr_misses::total 187698 # number of demand (read+write) MSHR misses
1103 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses
1104 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
1105 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16887 # number of overall MSHR misses
1106 system.cpu.l2cache.overall_mshr_misses::cpu.data 170753 # number of overall MSHR misses
1107 system.cpu.l2cache.overall_mshr_misses::total 187698 # number of overall MSHR misses
1108 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3916050 # number of ReadReq MSHR miss cycles
1109 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles
1110 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 962195275 # number of ReadReq MSHR miss cycles
1111 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2059471232 # number of ReadReq MSHR miss cycles
1112 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3025896812 # number of ReadReq MSHR miss cycles
1113 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39657846 # number of UpgradeReq MSHR miss cycles
1114 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39657846 # number of UpgradeReq MSHR miss cycles
1115 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5291032825 # number of ReadExReq MSHR miss cycles
1116 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5291032825 # number of ReadExReq MSHR miss cycles
1117 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3916050 # number of demand (read+write) MSHR miss cycles
1118 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles
1119 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 962195275 # number of demand (read+write) MSHR miss cycles
1120 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7350504057 # number of demand (read+write) MSHR miss cycles
1121 system.cpu.l2cache.demand_mshr_miss_latency::total 8316929637 # number of demand (read+write) MSHR miss cycles
1122 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3916050 # number of overall MSHR miss cycles
1123 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles
1124 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 962195275 # number of overall MSHR miss cycles
1125 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7350504057 # number of overall MSHR miss cycles
1126 system.cpu.l2cache.overall_mshr_miss_latency::total 8316929637 # number of overall MSHR miss cycles
1127 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89189069500 # number of ReadReq MSHR uncacheable cycles
1128 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89189069500 # number of ReadReq MSHR uncacheable cycles
1129 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2311324000 # number of WriteReq MSHR uncacheable cycles
1130 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2311324000 # number of WriteReq MSHR uncacheable cycles
1131 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91500393500 # number of overall MSHR uncacheable cycles
1132 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91500393500 # number of overall MSHR uncacheable cycles
1133 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses
1134 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for ReadReq accesses
1135 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for ReadReq accesses
1136 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026921 # mshr miss rate for ReadReq accesses
1137 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021191 # mshr miss rate for ReadReq accesses
1138 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.923334 # mshr miss rate for UpgradeReq accesses
1139 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.923334 # mshr miss rate for UpgradeReq accesses
1140 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464051 # mshr miss rate for ReadExReq accesses
1141 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464051 # mshr miss rate for ReadExReq accesses
1142 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for demand accesses
1143 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for demand accesses
1144 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for demand accesses
1145 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for demand accesses
1146 system.cpu.l2cache.demand_mshr_miss_rate::total 0.066340 # mshr miss rate for demand accesses
1147 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000492 # mshr miss rate for overall accesses
1148 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for overall accesses
1149 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for overall accesses
1150 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for overall accesses
1151 system.cpu.l2cache.overall_mshr_miss_rate::total 0.066340 # mshr miss rate for overall accesses
1152 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average ReadReq mshr miss latency
1153 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency
1154 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56978.461242 # average ReadReq mshr miss latency
1155 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55813.741077 # average ReadReq mshr miss latency
1156 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56197.474408 # average ReadReq mshr miss latency
1157 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10258.108122 # average UpgradeReq mshr miss latency
1158 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10258.108122 # average UpgradeReq mshr miss latency
1159 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39528.387833 # average ReadExReq mshr miss latency
1160 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39528.387833 # average ReadExReq mshr miss latency
1161 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency
1162 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
1163 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency
1164 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency
1165 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency
1166 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency
1167 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
1168 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency
1169 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency
1170 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency
1171 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1172 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1173 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1174 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1175 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1176 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1177 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1178 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1179 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1181 ---------- End Simulation Statistics ----------
projects / gem5.git / blob