2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.141960 # Number of seconds simulated
4 sim_ticks 5141959613000 # Number of ticks simulated
5 final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 152486 # Simulator instruction rate (inst/s)
8 host_op_rate 301416 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1922658876 # Simulator tick rate (ticks/s)
10 host_mem_usage 770128 # Number of bytes of host memory used
11 host_seconds 2674.40 # Real time elapsed on the host
12 sim_insts 407807707 # Number of instructions simulated
13 sim_ops 806107146 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory
26 system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory
34 system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 222895 # Number of read requests accepted
52 system.physmem.writeReqs 148771 # Number of write requests accepted
53 system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 14406 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 13692 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 14137 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 13444 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 14027 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 13372 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 13359 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 13805 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 13762 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 13592 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 13956 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 13564 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 14528 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 14698 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 14291 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 14126 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 9807 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9166 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 9421 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 8835 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9422 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 8917 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 8763 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 9221 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 9116 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 9134 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 9470 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 8904 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9718 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9806 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 9580 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9471 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
97 system.physmem.totGap 5141959559500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 222895 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 148771 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads
261 system.physmem.totQLat 4923822749 # Total ticks spent queuing
262 system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM
263 system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers
264 system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst
265 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
266 system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst
267 system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s
268 system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
269 system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s
270 system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
271 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
272 system.physmem.busUtil 0.04 # Data bus utilization in percentage
273 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
274 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
275 system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
276 system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing
277 system.physmem.readRowHits 186870 # Number of row buffer hits during reads
278 system.physmem.writeRowHits 110052 # Number of row buffer hits during writes
279 system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads
280 system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes
281 system.physmem.avgGap 13834893.59 # Average gap between requests
282 system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined
283 system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states
284 system.physmem.memoryStateTime::REF 171701140000 # Time in different power states
285 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
286 system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states
287 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
288 system.membus.throughput 5095093 # Throughput (bytes/s)
289 system.membus.trans_dist::ReadReq 662466 # Transaction distribution
290 system.membus.trans_dist::ReadResp 662464 # Transaction distribution
291 system.membus.trans_dist::WriteReq 13782 # Transaction distribution
292 system.membus.trans_dist::WriteResp 13782 # Transaction distribution
293 system.membus.trans_dist::Writeback 148771 # Transaction distribution
294 system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution
295 system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution
296 system.membus.trans_dist::ReadExReq 179320 # Transaction distribution
297 system.membus.trans_dist::ReadExResp 179319 # Transaction distribution
298 system.membus.trans_dist::MessageReq 1645 # Transaction distribution
299 system.membus.trans_dist::MessageResp 1645 # Transaction distribution
300 system.membus.trans_dist::BadAddressError 2 # Transaction distribution
301 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
302 system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
303 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
304 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes)
305 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes)
306 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
307 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes)
308 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes)
309 system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes)
310 system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes)
311 system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
312 system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
313 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
314 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes)
315 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes)
316 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes)
317 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes)
318 system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes)
319 system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes)
320 system.membus.data_through_bus 25585193 # Total data (bytes)
321 system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes)
322 system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks)
323 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
324 system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks)
325 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
326 system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
327 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
328 system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks)
329 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
330 system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
331 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
332 system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
333 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
334 system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks)
335 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
336 system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks)
337 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
338 system.iocache.tags.replacements 47571 # number of replacements
339 system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use
340 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
341 system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks.
342 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
343 system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit.
344 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor
345 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy
346 system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy
347 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
348 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
349 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
350 system.iocache.tags.tag_accesses 428634 # Number of tag accesses
351 system.iocache.tags.data_accesses 428634 # Number of data accesses
352 system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses
353 system.iocache.ReadReq_misses::total 906 # number of ReadReq misses
354 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
355 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
356 system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses
357 system.iocache.demand_misses::total 47626 # number of demand (read+write) misses
358 system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses
359 system.iocache.overall_misses::total 47626 # number of overall misses
360 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles
361 system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles
362 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles
363 system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles
364 system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles
365 system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles
366 system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles
367 system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles
368 system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses)
369 system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses)
370 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
371 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
372 system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses
373 system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses
374 system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses
375 system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses
376 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
377 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
378 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
379 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
380 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
381 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
382 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
383 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
384 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency
385 system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency
386 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency
387 system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency
388 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency
389 system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency
390 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency
391 system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency
392 system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked
393 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
394 system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked
395 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
396 system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked
397 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
398 system.iocache.fast_writes 0 # number of fast writes performed
399 system.iocache.cache_copies 0 # number of cache copies performed
400 system.iocache.writebacks::writebacks 46667 # number of writebacks
401 system.iocache.writebacks::total 46667 # number of writebacks
402 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses
403 system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses
404 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
405 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
406 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses
407 system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses
408 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses
409 system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses
410 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles
411 system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles
412 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles
413 system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles
414 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles
415 system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles
416 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles
417 system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles
418 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
419 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
420 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
421 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
422 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
423 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
424 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
425 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
426 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency
427 system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency
428 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency
429 system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency
430 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency
431 system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency
432 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency
433 system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency
434 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
435 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
436 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
437 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
438 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
439 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
440 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
441 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
442 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
443 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
444 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
445 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
446 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
447 system.iobus.throughput 637150 # Throughput (bytes/s)
448 system.iobus.trans_dist::ReadReq 225562 # Transaction distribution
449 system.iobus.trans_dist::ReadResp 225562 # Transaction distribution
450 system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
451 system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
452 system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
453 system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
454 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
455 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
456 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
457 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
458 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
459 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
460 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
461 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
462 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
463 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
464 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
465 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
466 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
467 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
468 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
469 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
470 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
471 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
472 system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
473 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes)
474 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes)
475 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
476 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
477 system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes)
478 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
479 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
480 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
481 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
482 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
483 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
484 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
485 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
486 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
487 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
488 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
489 system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
490 system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
491 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
492 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
493 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
494 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
495 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
496 system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
497 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes)
498 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes)
499 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
500 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
501 system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes)
502 system.iobus.data_through_bus 3276200 # Total data (bytes)
503 system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks)
504 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
505 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
506 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
507 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
508 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
509 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
510 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
511 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
512 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
513 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
514 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
515 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
516 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
517 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
518 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
519 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
520 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
521 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
522 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
523 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
524 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
525 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
526 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
527 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
528 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
529 system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
530 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
531 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
532 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
533 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
534 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
535 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
536 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
537 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
538 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
539 system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks)
540 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
541 system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
542 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
543 system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
544 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
545 system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks)
546 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
547 system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
548 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
549 system.cpu_clk_domain.clock 500 # Clock period in ticks
550 system.cpu.branchPred.lookups 85633263 # Number of BP lookups
551 system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted
552 system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect
553 system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups
554 system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits
555 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
556 system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage
557 system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target.
558 system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions.
559 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
560 system.cpu.numCycles 453234333 # number of cpu cycles simulated
561 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
562 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
563 system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss
564 system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed
565 system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered
566 system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken
567 system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked
568 system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing
569 system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb
570 system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked
571 system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
572 system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps
573 system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
574 system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched
575 system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed
576 system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed
577 system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total)
578 system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total)
579 system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total)
580 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
581 system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total)
582 system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total)
583 system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total)
584 system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total)
585 system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total)
586 system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total)
587 system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total)
588 system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total)
589 system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total)
590 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
591 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
592 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
593 system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total)
594 system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle
595 system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle
596 system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle
597 system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked
598 system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running
599 system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking
600 system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing
601 system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode
602 system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode
603 system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing
604 system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle
605 system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking
606 system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst
607 system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running
608 system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking
609 system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename
610 system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full
611 system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full
612 system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full
613 system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed
614 system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made
615 system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups
616 system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups
617 system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed
618 system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing
619 system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed
620 system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed
621 system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer
622 system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit.
623 system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit.
624 system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads.
625 system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores.
626 system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec)
627 system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ
628 system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued
629 system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued
630 system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling
631 system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph
632 system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed
633 system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle
634 system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle
635 system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle
636 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
637 system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle
638 system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle
639 system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle
640 system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle
641 system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle
642 system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle
643 system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle
644 system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle
645 system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle
646 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
647 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
648 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
649 system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle
650 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
651 system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available
652 system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available
653 system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available
654 system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available
655 system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available
656 system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available
657 system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available
658 system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available
659 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available
660 system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available
661 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available
662 system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available
663 system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available
664 system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available
665 system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available
666 system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available
667 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available
668 system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available
669 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available
670 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available
671 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available
672 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available
673 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available
674 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available
675 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available
676 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available
677 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available
678 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available
679 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available
680 system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available
681 system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available
682 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
683 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
684 system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued
685 system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued
686 system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued
687 system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued
688 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
689 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
690 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
691 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
692 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
693 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
694 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
695 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
696 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
697 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
698 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
699 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
700 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
701 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
702 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
703 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
704 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
705 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
706 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
707 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
708 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
709 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
710 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
711 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
712 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
713 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
714 system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued
715 system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued
716 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
717 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
718 system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued
719 system.cpu.iq.rate 1.811536 # Inst issue rate
720 system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested
721 system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst)
722 system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads
723 system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes
724 system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses
725 system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads
726 system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes
727 system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
728 system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses
729 system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses
730 system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores
731 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
732 system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed
733 system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed
734 system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations
735 system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed
736 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
737 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
738 system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled
739 system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked
740 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
741 system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing
742 system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking
743 system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking
744 system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ
745 system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch
746 system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions
747 system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions
748 system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions
749 system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall
750 system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall
751 system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations
752 system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly
753 system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly
754 system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute
755 system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions
756 system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed
757 system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute
758 system.cpu.iew.exec_swp 0 # number of swp insts executed
759 system.cpu.iew.exec_nop 0 # number of nop insts executed
760 system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed
761 system.cpu.iew.exec_branches 83104184 # Number of branches executed
762 system.cpu.iew.exec_stores 9044810 # Number of stores executed
763 system.cpu.iew.exec_rate 1.808423 # Inst execution rate
764 system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit
765 system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back
766 system.cpu.iew.wb_producers 638623234 # num instructions producing a value
767 system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value
768 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
769 system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle
770 system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back
771 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
772 system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit
773 system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards
774 system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted
775 system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle
776 system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle
777 system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle
778 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
779 system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle
780 system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle
781 system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle
782 system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle
783 system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle
784 system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle
785 system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle
786 system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle
787 system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle
788 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
789 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
790 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
791 system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle
792 system.cpu.commit.committedInsts 407807707 # Number of instructions committed
793 system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed
794 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
795 system.cpu.commit.refs 22429955 # Number of memory references committed
796 system.cpu.commit.loads 14000617 # Number of loads committed
797 system.cpu.commit.membars 474711 # Number of memory barriers committed
798 system.cpu.commit.branches 82167469 # Number of branches committed
799 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
800 system.cpu.commit.int_insts 734952495 # Number of committed integer instructions.
801 system.cpu.commit.function_calls 1155627 # Number of function calls committed.
802 system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction
803 system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction
804 system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction
805 system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction
806 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
807 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
808 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
809 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
810 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
811 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
812 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
813 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
814 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
815 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
816 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
817 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
818 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
819 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
820 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
821 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
822 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
823 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
824 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
825 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
826 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
827 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
828 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
829 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
830 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
831 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
832 system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction
833 system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction
834 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
835 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
836 system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction
837 system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached
838 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
839 system.cpu.rob.rob_reads 1079887016 # The number of ROB reads
840 system.cpu.rob.rob_writes 1655298855 # The number of ROB writes
841 system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself
842 system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling
843 system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
844 system.cpu.committedInsts 407807707 # Number of Instructions Simulated
845 system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated
846 system.cpu.committedInsts_total 407807707 # Number of Instructions Simulated
847 system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction
848 system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads
849 system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle
850 system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads
851 system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads
852 system.cpu.int_regfile_writes 653876789 # number of integer regfile writes
853 system.cpu.fp_regfile_reads 50 # number of floating regfile reads
854 system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads
855 system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes
856 system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads
857 system.cpu.misc_regfile_writes 402672 # number of misc regfile writes
858 system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s)
859 system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution
860 system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution
861 system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution
862 system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution
863 system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution
864 system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution
865 system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution
866 system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution
867 system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution
868 system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
869 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes)
870 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes)
871 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes)
872 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes)
873 system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes)
874 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes)
875 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes)
876 system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes)
877 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes)
878 system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes)
879 system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes)
880 system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes)
881 system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks)
882 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
883 system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks)
884 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
885 system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks)
886 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
887 system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks)
888 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
889 system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks)
890 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
891 system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks)
892 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
893 system.cpu.icache.tags.replacements 953583 # number of replacements
894 system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use
895 system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks.
896 system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks.
897 system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks.
898 system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit.
899 system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor
900 system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy
901 system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy
902 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
903 system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
904 system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
905 system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id
906 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
907 system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses
908 system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses
909 system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits
910 system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits
911 system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits
912 system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits
913 system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits
914 system.cpu.icache.overall_hits::total 7479724 # number of overall hits
915 system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses
916 system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses
917 system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses
918 system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses
919 system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses
920 system.cpu.icache.overall_misses::total 1007844 # number of overall misses
921 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles
922 system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles
923 system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles
924 system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles
925 system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles
926 system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles
927 system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # number of ReadReq accesses(hits+misses)
928 system.cpu.icache.ReadReq_accesses::total 8487568 # number of ReadReq accesses(hits+misses)
929 system.cpu.icache.demand_accesses::cpu.inst 8487568 # number of demand (read+write) accesses
930 system.cpu.icache.demand_accesses::total 8487568 # number of demand (read+write) accesses
931 system.cpu.icache.overall_accesses::cpu.inst 8487568 # number of overall (read+write) accesses
932 system.cpu.icache.overall_accesses::total 8487568 # number of overall (read+write) accesses
933 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118744 # miss rate for ReadReq accesses
934 system.cpu.icache.ReadReq_miss_rate::total 0.118744 # miss rate for ReadReq accesses
935 system.cpu.icache.demand_miss_rate::cpu.inst 0.118744 # miss rate for demand accesses
936 system.cpu.icache.demand_miss_rate::total 0.118744 # miss rate for demand accesses
937 system.cpu.icache.overall_miss_rate::cpu.inst 0.118744 # miss rate for overall accesses
938 system.cpu.icache.overall_miss_rate::total 0.118744 # miss rate for overall accesses
939 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990 # average ReadReq miss latency
940 system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990 # average ReadReq miss latency
941 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency
942 system.cpu.icache.demand_avg_miss_latency::total 13926.343990 # average overall miss latency
943 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency
944 system.cpu.icache.overall_avg_miss_latency::total 13926.343990 # average overall miss latency
945 system.cpu.icache.blocked_cycles::no_mshrs 4168 # number of cycles access was blocked
946 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
947 system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked
948 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
949 system.cpu.icache.avg_blocked_cycles::no_mshrs 21.936842 # average number of cycles each access was blocked
950 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
951 system.cpu.icache.fast_writes 0 # number of fast writes performed
952 system.cpu.icache.cache_copies 0 # number of cache copies performed
953 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53688 # number of ReadReq MSHR hits
954 system.cpu.icache.ReadReq_mshr_hits::total 53688 # number of ReadReq MSHR hits
955 system.cpu.icache.demand_mshr_hits::cpu.inst 53688 # number of demand (read+write) MSHR hits
956 system.cpu.icache.demand_mshr_hits::total 53688 # number of demand (read+write) MSHR hits
957 system.cpu.icache.overall_mshr_hits::cpu.inst 53688 # number of overall MSHR hits
958 system.cpu.icache.overall_mshr_hits::total 53688 # number of overall MSHR hits
959 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954156 # number of ReadReq MSHR misses
960 system.cpu.icache.ReadReq_mshr_misses::total 954156 # number of ReadReq MSHR misses
961 system.cpu.icache.demand_mshr_misses::cpu.inst 954156 # number of demand (read+write) MSHR misses
962 system.cpu.icache.demand_mshr_misses::total 954156 # number of demand (read+write) MSHR misses
963 system.cpu.icache.overall_mshr_misses::cpu.inst 954156 # number of overall MSHR misses
964 system.cpu.icache.overall_mshr_misses::total 954156 # number of overall MSHR misses
965 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587558437 # number of ReadReq MSHR miss cycles
966 system.cpu.icache.ReadReq_mshr_miss_latency::total 11587558437 # number of ReadReq MSHR miss cycles
967 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587558437 # number of demand (read+write) MSHR miss cycles
968 system.cpu.icache.demand_mshr_miss_latency::total 11587558437 # number of demand (read+write) MSHR miss cycles
969 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587558437 # number of overall MSHR miss cycles
970 system.cpu.icache.overall_mshr_miss_latency::total 11587558437 # number of overall MSHR miss cycles
971 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for ReadReq accesses
972 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112418 # mshr miss rate for ReadReq accesses
973 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for demand accesses
974 system.cpu.icache.demand_mshr_miss_rate::total 0.112418 # mshr miss rate for demand accesses
975 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for overall accesses
976 system.cpu.icache.overall_mshr_miss_rate::total 0.112418 # mshr miss rate for overall accesses
977 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809 # average ReadReq mshr miss latency
978 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809 # average ReadReq mshr miss latency
979 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency
980 system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency
981 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency
982 system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency
983 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
984 system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements
985 system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use
986 system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks.
987 system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks.
988 system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks.
989 system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit.
990 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor
991 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy
992 system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy
993 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
994 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
995 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
996 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
997 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
998 system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses
999 system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses
1000 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits
1001 system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # number of ReadReq hits
1002 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1003 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1004 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21136 # number of demand (read+write) hits
1005 system.cpu.itb_walker_cache.demand_hits::total 21136 # number of demand (read+write) hits
1006 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # number of overall hits
1007 system.cpu.itb_walker_cache.overall_hits::total 21136 # number of overall hits
1008 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses
1009 system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses
1010 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses
1011 system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses
1012 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses
1013 system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses
1014 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 107949749 # number of ReadReq miss cycles
1015 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 107949749 # number of ReadReq miss cycles
1016 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 107949749 # number of demand (read+write) miss cycles
1017 system.cpu.itb_walker_cache.demand_miss_latency::total 107949749 # number of demand (read+write) miss cycles
1018 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles
1019 system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles
1020 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses)
1021 system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses)
1022 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1023 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1024 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses
1025 system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses
1026 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses
1027 system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses
1028 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses
1029 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses
1030 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # miss rate for demand accesses
1031 system.cpu.itb_walker_cache.demand_miss_rate::total 0.317291 # miss rate for demand accesses
1032 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.317291 # miss rate for overall accesses
1033 system.cpu.itb_walker_cache.overall_miss_rate::total 0.317291 # miss rate for overall accesses
1034 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853 # average ReadReq miss latency
1035 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853 # average ReadReq miss latency
1036 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency
1037 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853 # average overall miss latency
1038 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency
1039 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853 # average overall miss latency
1040 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1041 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1042 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1043 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1044 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1045 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1046 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1047 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1048 system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks
1049 system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks
1050 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses
1051 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses
1052 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses
1053 system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses
1054 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses
1055 system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses
1056 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles
1057 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles
1058 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles
1059 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles
1060 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles
1061 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles
1062 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses
1063 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses
1064 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses
1065 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses
1066 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses
1067 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses
1068 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency
1069 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency
1070 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency
1071 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency
1072 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency
1073 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency
1074 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1075 system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements
1076 system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use
1077 system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks.
1078 system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks.
1079 system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks.
1080 system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit.
1081 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor
1082 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy
1083 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy
1084 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
1085 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
1086 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
1087 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
1088 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1089 system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses
1090 system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses
1091 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits
1092 system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits
1093 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits
1094 system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits
1095 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits
1096 system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits
1097 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses
1098 system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses
1099 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses
1100 system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses
1101 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses
1102 system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses
1103 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles
1104 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles
1105 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles
1106 system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles
1107 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles
1108 system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles
1109 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses)
1110 system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses)
1111 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses
1112 system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses
1113 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses
1114 system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses
1115 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses
1116 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses
1117 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses
1118 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses
1119 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses
1120 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses
1121 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency
1122 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency
1123 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency
1124 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency
1125 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency
1126 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency
1127 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1128 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1129 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1130 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1131 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1132 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1133 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1134 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1135 system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks
1136 system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks
1137 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses
1138 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses
1139 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses
1140 system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses
1141 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses
1142 system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses
1143 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles
1144 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles
1145 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles
1146 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles
1147 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles
1148 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles
1149 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses
1150 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses
1151 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses
1152 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses
1153 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses
1154 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses
1155 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency
1156 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency
1157 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency
1158 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency
1159 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency
1160 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency
1161 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1162 system.cpu.dcache.tags.replacements 1658766 # number of replacements
1163 system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use
1164 system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks.
1165 system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks.
1166 system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks.
1167 system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit.
1168 system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor
1169 system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
1170 system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
1171 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1172 system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
1173 system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id
1174 system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
1175 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1176 system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses
1177 system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses
1178 system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits
1179 system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits
1180 system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits
1181 system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits
1182 system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits
1183 system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits
1184 system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits
1185 system.cpu.dcache.overall_hits::total 19000217 # number of overall hits
1186 system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses
1187 system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses
1188 system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses
1189 system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses
1190 system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses
1191 system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses
1192 system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses
1193 system.cpu.dcache.overall_misses::total 2553579 # number of overall misses
1194 system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles
1195 system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles
1196 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles
1197 system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles
1198 system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles
1199 system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles
1200 system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles
1201 system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles
1202 system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses)
1203 system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses)
1204 system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses)
1205 system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses)
1206 system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses
1207 system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses
1208 system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses
1209 system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses
1210 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses
1211 system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses
1212 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses
1213 system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses
1214 system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses
1215 system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses
1216 system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses
1217 system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses
1218 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency
1219 system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency
1220 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency
1221 system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency
1222 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency
1223 system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency
1224 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency
1225 system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency
1226 system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked
1227 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1228 system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked
1229 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1230 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked
1231 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1232 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1233 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1234 system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks
1235 system.cpu.dcache.writebacks::total 1559977 # number of writebacks
1236 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits
1237 system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits
1238 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits
1239 system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits
1240 system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits
1241 system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits
1242 system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits
1243 system.cpu.dcache.overall_mshr_hits::total 892034 # number of overall MSHR hits
1244 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369712 # number of ReadReq MSHR misses
1245 system.cpu.dcache.ReadReq_mshr_misses::total 1369712 # number of ReadReq MSHR misses
1246 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291833 # number of WriteReq MSHR misses
1247 system.cpu.dcache.WriteReq_mshr_misses::total 291833 # number of WriteReq MSHR misses
1248 system.cpu.dcache.demand_mshr_misses::cpu.data 1661545 # number of demand (read+write) MSHR misses
1249 system.cpu.dcache.demand_mshr_misses::total 1661545 # number of demand (read+write) MSHR misses
1250 system.cpu.dcache.overall_mshr_misses::cpu.data 1661545 # number of overall MSHR misses
1251 system.cpu.dcache.overall_mshr_misses::total 1661545 # number of overall MSHR misses
1252 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17680675970 # number of ReadReq MSHR miss cycles
1253 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17680675970 # number of ReadReq MSHR miss cycles
1254 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11138475501 # number of WriteReq MSHR miss cycles
1255 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11138475501 # number of WriteReq MSHR miss cycles
1256 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28819151471 # number of demand (read+write) MSHR miss cycles
1257 system.cpu.dcache.demand_mshr_miss_latency::total 28819151471 # number of demand (read+write) MSHR miss cycles
1258 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28819151471 # number of overall MSHR miss cycles
1259 system.cpu.dcache.overall_mshr_miss_latency::total 28819151471 # number of overall MSHR miss cycles
1260 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364609500 # number of ReadReq MSHR uncacheable cycles
1261 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364609500 # number of ReadReq MSHR uncacheable cycles
1262 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539074000 # number of WriteReq MSHR uncacheable cycles
1263 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539074000 # number of WriteReq MSHR uncacheable cycles
1264 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903683500 # number of overall MSHR uncacheable cycles
1265 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903683500 # number of overall MSHR uncacheable cycles
1266 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104287 # mshr miss rate for ReadReq accesses
1267 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104287 # mshr miss rate for ReadReq accesses
1268 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034660 # mshr miss rate for WriteReq accesses
1269 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034660 # mshr miss rate for WriteReq accesses
1270 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses
1271 system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses
1272 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses
1273 system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses
1274 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471 # average ReadReq mshr miss latency
1275 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency
1276 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency
1277 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency
1278 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency
1279 system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency
1280 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency
1281 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency
1282 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1283 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1284 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1285 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1286 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1287 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1288 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1289 system.cpu.l2cache.tags.replacements 111887 # number of replacements
1290 system.cpu.l2cache.tags.tagsinuse 64820.177016 # Cycle average of tags in use
1291 system.cpu.l2cache.tags.total_refs 3787056 # Total number of references to valid blocks.
1292 system.cpu.l2cache.tags.sampled_refs 176012 # Sample count of references to valid blocks.
1293 system.cpu.l2cache.tags.avg_refs 21.515897 # Average number of references to valid blocks.
1294 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1295 system.cpu.l2cache.tags.occ_blocks::writebacks 50551.329322 # Average occupied blocks per requestor
1296 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.553377 # Average occupied blocks per requestor
1297 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.127382 # Average occupied blocks per requestor
1298 system.cpu.l2cache.tags.occ_blocks::cpu.inst 2956.401453 # Average occupied blocks per requestor
1299 system.cpu.l2cache.tags.occ_blocks::cpu.data 11298.765482 # Average occupied blocks per requestor
1300 system.cpu.l2cache.tags.occ_percent::writebacks 0.771352 # Average percentage of cache occupancy
1301 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy
1302 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1303 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045111 # Average percentage of cache occupancy
1304 system.cpu.l2cache.tags.occ_percent::cpu.data 0.172405 # Average percentage of cache occupancy
1305 system.cpu.l2cache.tags.occ_percent::total 0.989077 # Average percentage of cache occupancy
1306 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64125 # Occupied blocks per task id
1307 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
1308 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id
1309 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3391 # Occupied blocks per task id
1310 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id
1311 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54885 # Occupied blocks per task id
1312 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978470 # Percentage of cache occupancy per task id
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1320 system.cpu.l2cache.Writeback_hits::writebacks 1584798 # number of Writeback hits
1321 system.cpu.l2cache.Writeback_hits::total 1584798 # number of Writeback hits
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1323 system.cpu.l2cache.UpgradeReq_hits::total 327 # number of UpgradeReq hits
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1357 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1233234983 # number of ReadReq miss cycles
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1370 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 378250 # number of overall miss cycles
1371 system.cpu.l2cache.overall_miss_latency::cpu.inst 1233234983 # number of overall miss cycles
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1378 system.cpu.l2cache.ReadReq_accesses::total 2395333 # number of ReadReq accesses(hits+misses)
1379 system.cpu.l2cache.Writeback_accesses::writebacks 1584798 # number of Writeback accesses(hits+misses)
1380 system.cpu.l2cache.Writeback_accesses::total 1584798 # number of Writeback accesses(hits+misses)
1381 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1764 # number of UpgradeReq accesses(hits+misses)
1382 system.cpu.l2cache.UpgradeReq_accesses::total 1764 # number of UpgradeReq accesses(hits+misses)
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1384 system.cpu.l2cache.ReadExReq_accesses::total 289674 # number of ReadExReq accesses(hits+misses)
1385 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64898 # number of demand (read+write) accesses
1386 system.cpu.l2cache.demand_accesses::cpu.itb.walker 7512 # number of demand (read+write) accesses
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1390 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64898 # number of overall (read+write) accesses
1391 system.cpu.l2cache.overall_accesses::cpu.itb.walker 7512 # number of overall (read+write) accesses
1392 system.cpu.l2cache.overall_accesses::cpu.inst 954049 # number of overall (read+write) accesses
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1395 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000925 # miss rate for ReadReq accesses
1396 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000666 # miss rate for ReadReq accesses
1397 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016954 # miss rate for ReadReq accesses
1398 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026316 # miss rate for ReadReq accesses
1399 system.cpu.l2cache.ReadReq_miss_rate::total 0.021819 # miss rate for ReadReq accesses
1400 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814626 # miss rate for UpgradeReq accesses
1401 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814626 # miss rate for UpgradeReq accesses
1402 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.458657 # miss rate for ReadExReq accesses
1403 system.cpu.l2cache.ReadExReq_miss_rate::total 0.458657 # miss rate for ReadExReq accesses
1404 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000925 # miss rate for demand accesses
1405 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000666 # miss rate for demand accesses
1406 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016954 # miss rate for demand accesses
1407 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101826 # miss rate for demand accesses
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1410 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000666 # miss rate for overall accesses
1411 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016954 # miss rate for overall accesses
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1413 system.cpu.l2cache.overall_miss_rate::total 0.068947 # miss rate for overall accesses
1414 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84445.833333 # average ReadReq miss latency
1415 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75650 # average ReadReq miss latency
1416 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76243.275611 # average ReadReq miss latency
1417 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77417.176776 # average ReadReq miss latency
1418 system.cpu.l2cache.ReadReq_avg_miss_latency::total 77061.763427 # average ReadReq miss latency
1419 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11934.461378 # average UpgradeReq miss latency
1420 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11934.461378 # average UpgradeReq miss latency
1421 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69506.318084 # average ReadExReq miss latency
1422 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69506.318084 # average ReadExReq miss latency
1423 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency
1424 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency
1425 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency
1426 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency
1427 system.cpu.l2cache.demand_avg_miss_latency::total 71639.322125 # average overall miss latency
1428 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency
1429 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency
1430 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency
1431 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency
1432 system.cpu.l2cache.overall_avg_miss_latency::total 71639.322125 # average overall miss latency
1433 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1434 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1435 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1436 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1437 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1438 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1439 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1440 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1441 system.cpu.l2cache.writebacks::writebacks 102104 # number of writebacks
1442 system.cpu.l2cache.writebacks::total 102104 # number of writebacks
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1444 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
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1457 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1437 # number of UpgradeReq MSHR misses
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1459 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132861 # number of ReadExReq MSHR misses
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1480 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4324750 # number of demand (read+write) MSHR miss cycles
1481 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles
1482 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1030094767 # number of demand (read+write) MSHR miss cycles
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1485 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4324750 # number of overall MSHR miss cycles
1486 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles
1487 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1030094767 # number of overall MSHR miss cycles
1488 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9906472112 # number of overall MSHR miss cycles
1489 system.cpu.l2cache.overall_mshr_miss_latency::total 10941206879 # number of overall MSHR miss cycles
1490 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251381500 # number of ReadReq MSHR uncacheable cycles
1491 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251381500 # number of ReadReq MSHR uncacheable cycles
1492 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373144500 # number of WriteReq MSHR uncacheable cycles
1493 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373144500 # number of WriteReq MSHR uncacheable cycles
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1495 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624526000 # number of overall MSHR uncacheable cycles
1496 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for ReadReq accesses
1497 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for ReadReq accesses
1498 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for ReadReq accesses
1499 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026314 # mshr miss rate for ReadReq accesses
1500 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021817 # mshr miss rate for ReadReq accesses
1501 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814626 # mshr miss rate for UpgradeReq accesses
1502 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814626 # mshr miss rate for UpgradeReq accesses
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1505 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for demand accesses
1506 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for demand accesses
1507 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for demand accesses
1508 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for demand accesses
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1510 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for overall accesses
1511 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for overall accesses
1512 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for overall accesses
1513 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for overall accesses
1514 system.cpu.l2cache.overall_mshr_miss_rate::total 0.068946 # mshr miss rate for overall accesses
1515 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average ReadReq mshr miss latency
1516 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency
1517 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency
1518 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency
1519 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency
1520 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency
1521 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency
1522 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency
1523 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency
1524 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency
1525 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
1526 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency
1527 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency
1528 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency
1529 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency
1530 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
1531 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency
1532 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency
1533 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency
1534 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1535 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1536 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1537 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1538 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1539 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1540 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1541 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1542 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1544 ---------- End Simulation Statistics ----------
projects / gem5.git / blob