2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.144266 # Number of seconds simulated
4 sim_ticks 5144265998000 # Number of ticks simulated
5 final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 171354 # Simulator instruction rate (inst/s)
8 host_op_rate 338701 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2161855241 # Simulator tick rate (ticks/s)
10 host_mem_usage 817304 # Number of bytes of host memory used
11 host_seconds 2379.56 # Real time elapsed on the host
12 sim_insts 407746267 # Number of instructions simulated
13 sim_ops 805959101 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 184401 # Number of read requests accepted
52 system.physmem.writeReqs 148992 # Number of write requests accepted
53 system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11512 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 10865 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 12624 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11646 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11360 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11063 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 11424 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11380 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11354 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 10854 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 10623 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11335 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 12163 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12460 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11874 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11688 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 9762 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9087 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 9770 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 9357 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9485 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 8994 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 9154 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 8718 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 8812 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 9056 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 8954 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 9300 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9801 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9709 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 9528 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9485 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
97 system.physmem.totGap 5144265948500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 184401 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 148992 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads
259 system.physmem.totQLat 2113024695 # Total ticks spent queuing
260 system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM
261 system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers
262 system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst
263 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
264 system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst
265 system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
266 system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
267 system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
268 system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
269 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
270 system.physmem.busUtil 0.03 # Data bus utilization in percentage
271 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
272 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
273 system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
274 system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing
275 system.physmem.readRowHits 150283 # Number of row buffer hits during reads
276 system.physmem.writeRowHits 109804 # Number of row buffer hits during writes
277 system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads
278 system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes
279 system.physmem.avgGap 15430035.87 # Average gap between requests
280 system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined
281 system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ)
282 system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ)
283 system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ)
284 system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ)
285 system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ)
286 system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ)
287 system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ)
288 system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ)
289 system.physmem_0.averagePower 668.806670 # Core power per rank (mW)
290 system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states
291 system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states
292 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
293 system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states
294 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
295 system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ)
296 system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ)
297 system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ)
298 system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ)
299 system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ)
300 system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ)
301 system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ)
302 system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ)
303 system.physmem_1.averagePower 668.811201 # Core power per rank (mW)
304 system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states
305 system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states
306 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
307 system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states
308 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
309 system.cpu.branchPred.lookups 86512376 # Number of BP lookups
310 system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted
311 system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect
312 system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups
313 system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits
314 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
315 system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage
316 system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target.
317 system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions.
318 system.cpu_clk_domain.clock 500 # Clock period in ticks
319 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
320 system.cpu.numCycles 465431904 # number of cpu cycles simulated
321 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
322 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
323 system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss
324 system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed
325 system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered
326 system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken
327 system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked
328 system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing
329 system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb
330 system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
331 system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps
332 system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions
333 system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR
334 system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched
335 system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed
336 system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed
337 system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle
355 system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle
356 system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle
357 system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked
358 system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running
359 system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking
360 system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing
361 system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode
362 system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing
363 system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle
364 system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking
365 system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst
366 system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running
367 system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking
368 system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename
369 system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full
370 system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full
371 system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full
372 system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full
373 system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed
374 system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made
375 system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups
376 system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups
377 system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed
378 system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing
379 system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed
380 system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed
381 system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer
382 system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit.
383 system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit.
384 system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads.
385 system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores.
386 system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec)
387 system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ
388 system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued
389 system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued
390 system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling
391 system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph
392 system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed
393 system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle
394 system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle
410 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
411 system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available
412 system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available
413 system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available
414 system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available
415 system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available
416 system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available
417 system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available
420 system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available
440 system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available
441 system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available
442 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
443 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
444 system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued
445 system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued
446 system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued
447 system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued
448 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued
449 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued
450 system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued
451 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued
454 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued
474 system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued
475 system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued
476 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
477 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
478 system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued
479 system.cpu.iq.rate 1.767144 # Inst issue rate
480 system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested
481 system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst)
482 system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads
483 system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes
484 system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses
485 system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads
486 system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes
487 system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses
488 system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses
489 system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses
490 system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores
491 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
492 system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed
493 system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed
494 system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations
495 system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed
496 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
497 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
498 system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled
499 system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked
500 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
501 system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing
502 system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking
503 system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking
504 system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ
505 system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch
506 system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions
507 system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions
508 system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions
509 system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall
510 system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall
511 system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations
512 system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly
513 system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly
514 system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute
515 system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions
516 system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed
517 system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute
518 system.cpu.iew.exec_swp 0 # number of swp insts executed
519 system.cpu.iew.exec_nop 0 # number of nop insts executed
520 system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed
521 system.cpu.iew.exec_branches 83147027 # Number of branches executed
522 system.cpu.iew.exec_stores 9067588 # Number of stores executed
523 system.cpu.iew.exec_rate 1.763892 # Inst execution rate
524 system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit
525 system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back
526 system.cpu.iew.wb_producers 639862073 # num instructions producing a value
527 system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value
528 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
529 system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle
530 system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back
531 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
532 system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit
533 system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards
534 system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted
535 system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle
552 system.cpu.commit.committedInsts 407746267 # Number of instructions committed
553 system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed
554 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
555 system.cpu.commit.refs 22407791 # Number of memory references committed
556 system.cpu.commit.loads 13985627 # Number of loads committed
557 system.cpu.commit.membars 468163 # Number of memory barriers committed
558 system.cpu.commit.branches 82155343 # Number of branches committed
559 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
560 system.cpu.commit.int_insts 734813827 # Number of committed integer instructions.
561 system.cpu.commit.function_calls 1155420 # Number of function calls committed.
562 system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction
563 system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction
564 system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction
565 system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction
566 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
567 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
568 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
569 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
570 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction
593 system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction
594 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
595 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
596 system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction
597 system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached
598 system.cpu.rob.rob_reads 1281402583 # The number of ROB reads
599 system.cpu.rob.rob_writes 1659991505 # The number of ROB writes
600 system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself
601 system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling
602 system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
603 system.cpu.committedInsts 407746267 # Number of Instructions Simulated
604 system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated
605 system.cpu.cpi 1.141474 # CPI: Cycles Per Instruction
606 system.cpu.cpi_total 1.141474 # CPI: Total CPI of All Threads
607 system.cpu.ipc 0.876060 # IPC: Instructions Per Cycle
608 system.cpu.ipc_total 0.876060 # IPC: Total IPC of All Threads
609 system.cpu.int_regfile_reads 1090398458 # number of integer regfile reads
610 system.cpu.int_regfile_writes 654801015 # number of integer regfile writes
611 system.cpu.fp_regfile_reads 178 # number of floating regfile reads
612 system.cpu.cc_regfile_reads 415698435 # number of cc regfile reads
613 system.cpu.cc_regfile_writes 321644299 # number of cc regfile writes
614 system.cpu.misc_regfile_reads 264872577 # number of misc regfile reads
615 system.cpu.misc_regfile_writes 400155 # number of misc regfile writes
616 system.cpu.dcache.tags.replacements 1656886 # number of replacements
617 system.cpu.dcache.tags.tagsinuse 511.993571 # Cycle average of tags in use
618 system.cpu.dcache.tags.total_refs 18963252 # Total number of references to valid blocks.
619 system.cpu.dcache.tags.sampled_refs 1657398 # Sample count of references to valid blocks.
620 system.cpu.dcache.tags.avg_refs 11.441580 # Average number of references to valid blocks.
621 system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit.
622 system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor
623 system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
624 system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
625 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
626 system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
627 system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
628 system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
629 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
630 system.cpu.dcache.tags.tag_accesses 87668549 # Number of tag accesses
631 system.cpu.dcache.tags.data_accesses 87668549 # Number of data accesses
632 system.cpu.dcache.ReadReq_hits::cpu.data 10819943 # number of ReadReq hits
633 system.cpu.dcache.ReadReq_hits::total 10819943 # number of ReadReq hits
634 system.cpu.dcache.WriteReq_hits::cpu.data 8077328 # number of WriteReq hits
635 system.cpu.dcache.WriteReq_hits::total 8077328 # number of WriteReq hits
636 system.cpu.dcache.SoftPFReq_hits::cpu.data 63083 # number of SoftPFReq hits
637 system.cpu.dcache.SoftPFReq_hits::total 63083 # number of SoftPFReq hits
638 system.cpu.dcache.demand_hits::cpu.data 18897271 # number of demand (read+write) hits
639 system.cpu.dcache.demand_hits::total 18897271 # number of demand (read+write) hits
640 system.cpu.dcache.overall_hits::cpu.data 18960354 # number of overall hits
641 system.cpu.dcache.overall_hits::total 18960354 # number of overall hits
642 system.cpu.dcache.ReadReq_misses::cpu.data 1800618 # number of ReadReq misses
643 system.cpu.dcache.ReadReq_misses::total 1800618 # number of ReadReq misses
644 system.cpu.dcache.WriteReq_misses::cpu.data 335187 # number of WriteReq misses
645 system.cpu.dcache.WriteReq_misses::total 335187 # number of WriteReq misses
646 system.cpu.dcache.SoftPFReq_misses::cpu.data 406619 # number of SoftPFReq misses
647 system.cpu.dcache.SoftPFReq_misses::total 406619 # number of SoftPFReq misses
648 system.cpu.dcache.demand_misses::cpu.data 2135805 # number of demand (read+write) misses
649 system.cpu.dcache.demand_misses::total 2135805 # number of demand (read+write) misses
650 system.cpu.dcache.overall_misses::cpu.data 2542424 # number of overall misses
651 system.cpu.dcache.overall_misses::total 2542424 # number of overall misses
652 system.cpu.dcache.ReadReq_miss_latency::cpu.data 29915350500 # number of ReadReq miss cycles
653 system.cpu.dcache.ReadReq_miss_latency::total 29915350500 # number of ReadReq miss cycles
654 system.cpu.dcache.WriteReq_miss_latency::cpu.data 21131383234 # number of WriteReq miss cycles
655 system.cpu.dcache.WriteReq_miss_latency::total 21131383234 # number of WriteReq miss cycles
656 system.cpu.dcache.demand_miss_latency::cpu.data 51046733734 # number of demand (read+write) miss cycles
657 system.cpu.dcache.demand_miss_latency::total 51046733734 # number of demand (read+write) miss cycles
658 system.cpu.dcache.overall_miss_latency::cpu.data 51046733734 # number of overall miss cycles
659 system.cpu.dcache.overall_miss_latency::total 51046733734 # number of overall miss cycles
660 system.cpu.dcache.ReadReq_accesses::cpu.data 12620561 # number of ReadReq accesses(hits+misses)
661 system.cpu.dcache.ReadReq_accesses::total 12620561 # number of ReadReq accesses(hits+misses)
662 system.cpu.dcache.WriteReq_accesses::cpu.data 8412515 # number of WriteReq accesses(hits+misses)
663 system.cpu.dcache.WriteReq_accesses::total 8412515 # number of WriteReq accesses(hits+misses)
664 system.cpu.dcache.SoftPFReq_accesses::cpu.data 469702 # number of SoftPFReq accesses(hits+misses)
665 system.cpu.dcache.SoftPFReq_accesses::total 469702 # number of SoftPFReq accesses(hits+misses)
666 system.cpu.dcache.demand_accesses::cpu.data 21033076 # number of demand (read+write) accesses
667 system.cpu.dcache.demand_accesses::total 21033076 # number of demand (read+write) accesses
668 system.cpu.dcache.overall_accesses::cpu.data 21502778 # number of overall (read+write) accesses
669 system.cpu.dcache.overall_accesses::total 21502778 # number of overall (read+write) accesses
670 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142673 # miss rate for ReadReq accesses
671 system.cpu.dcache.ReadReq_miss_rate::total 0.142673 # miss rate for ReadReq accesses
672 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039844 # miss rate for WriteReq accesses
673 system.cpu.dcache.WriteReq_miss_rate::total 0.039844 # miss rate for WriteReq accesses
674 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865696 # miss rate for SoftPFReq accesses
675 system.cpu.dcache.SoftPFReq_miss_rate::total 0.865696 # miss rate for SoftPFReq accesses
676 system.cpu.dcache.demand_miss_rate::cpu.data 0.101545 # miss rate for demand accesses
677 system.cpu.dcache.demand_miss_rate::total 0.101545 # miss rate for demand accesses
678 system.cpu.dcache.overall_miss_rate::cpu.data 0.118237 # miss rate for overall accesses
679 system.cpu.dcache.overall_miss_rate::total 0.118237 # miss rate for overall accesses
680 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049 # average ReadReq miss latency
681 system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049 # average ReadReq miss latency
682 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440 # average WriteReq miss latency
683 system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440 # average WriteReq miss latency
684 system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508 # average overall miss latency
685 system.cpu.dcache.demand_avg_miss_latency::total 23900.465508 # average overall miss latency
686 system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234 # average overall miss latency
687 system.cpu.dcache.overall_avg_miss_latency::total 20077.978234 # average overall miss latency
688 system.cpu.dcache.blocked_cycles::no_mshrs 549742 # number of cycles access was blocked
689 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
690 system.cpu.dcache.blocked::no_mshrs 52309 # number of cycles access was blocked
691 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
692 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.509511 # average number of cycles each access was blocked
693 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
694 system.cpu.dcache.fast_writes 0 # number of fast writes performed
695 system.cpu.dcache.cache_copies 0 # number of cache copies performed
696 system.cpu.dcache.writebacks::writebacks 1559463 # number of writebacks
697 system.cpu.dcache.writebacks::total 1559463 # number of writebacks
698 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834370 # number of ReadReq MSHR hits
699 system.cpu.dcache.ReadReq_mshr_hits::total 834370 # number of ReadReq MSHR hits
700 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44863 # number of WriteReq MSHR hits
701 system.cpu.dcache.WriteReq_mshr_hits::total 44863 # number of WriteReq MSHR hits
702 system.cpu.dcache.demand_mshr_hits::cpu.data 879233 # number of demand (read+write) MSHR hits
703 system.cpu.dcache.demand_mshr_hits::total 879233 # number of demand (read+write) MSHR hits
704 system.cpu.dcache.overall_mshr_hits::cpu.data 879233 # number of overall MSHR hits
705 system.cpu.dcache.overall_mshr_hits::total 879233 # number of overall MSHR hits
706 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966248 # number of ReadReq MSHR misses
707 system.cpu.dcache.ReadReq_mshr_misses::total 966248 # number of ReadReq MSHR misses
708 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290324 # number of WriteReq MSHR misses
709 system.cpu.dcache.WriteReq_mshr_misses::total 290324 # number of WriteReq MSHR misses
710 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403128 # number of SoftPFReq MSHR misses
711 system.cpu.dcache.SoftPFReq_mshr_misses::total 403128 # number of SoftPFReq MSHR misses
712 system.cpu.dcache.demand_mshr_misses::cpu.data 1256572 # number of demand (read+write) MSHR misses
713 system.cpu.dcache.demand_mshr_misses::total 1256572 # number of demand (read+write) MSHR misses
714 system.cpu.dcache.overall_mshr_misses::cpu.data 1659700 # number of overall MSHR misses
715 system.cpu.dcache.overall_mshr_misses::total 1659700 # number of overall MSHR misses
716 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable
717 system.cpu.dcache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable
718 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable
719 system.cpu.dcache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable
720 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses
721 system.cpu.dcache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses
722 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14275238000 # number of ReadReq MSHR miss cycles
723 system.cpu.dcache.ReadReq_mshr_miss_latency::total 14275238000 # number of ReadReq MSHR miss cycles
724 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179377736 # number of WriteReq MSHR miss cycles
725 system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179377736 # number of WriteReq MSHR miss cycles
726 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6821935500 # number of SoftPFReq MSHR miss cycles
727 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6821935500 # number of SoftPFReq MSHR miss cycles
728 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33454615736 # number of demand (read+write) MSHR miss cycles
729 system.cpu.dcache.demand_mshr_miss_latency::total 33454615736 # number of demand (read+write) MSHR miss cycles
730 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40276551236 # number of overall MSHR miss cycles
731 system.cpu.dcache.overall_mshr_miss_latency::total 40276551236 # number of overall MSHR miss cycles
732 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793888500 # number of ReadReq MSHR uncacheable cycles
733 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793888500 # number of ReadReq MSHR uncacheable cycles
734 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2616393000 # number of WriteReq MSHR uncacheable cycles
735 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2616393000 # number of WriteReq MSHR uncacheable cycles
736 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500 # number of overall MSHR uncacheable cycles
737 system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500 # number of overall MSHR uncacheable cycles
738 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076561 # mshr miss rate for ReadReq accesses
739 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076561 # mshr miss rate for ReadReq accesses
740 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034511 # mshr miss rate for WriteReq accesses
741 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034511 # mshr miss rate for WriteReq accesses
742 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858263 # mshr miss rate for SoftPFReq accesses
743 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858263 # mshr miss rate for SoftPFReq accesses
744 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses
745 system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses
746 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077185 # mshr miss rate for overall accesses
747 system.cpu.dcache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses
748 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207 # average ReadReq mshr miss latency
749 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207 # average ReadReq mshr miss latency
750 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121 # average WriteReq mshr miss latency
751 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121 # average WriteReq mshr miss latency
752 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763 # average SoftPFReq mshr miss latency
753 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763 # average SoftPFReq mshr miss latency
754 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741 # average overall mshr miss latency
755 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741 # average overall mshr miss latency
756 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341 # average overall mshr miss latency
757 system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341 # average overall mshr miss latency
758 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505 # average ReadReq mshr uncacheable latency
759 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505 # average ReadReq mshr uncacheable latency
760 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994 # average WriteReq mshr uncacheable latency
761 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994 # average WriteReq mshr uncacheable latency
762 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909 # average overall mshr uncacheable latency
763 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency
764 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
765 system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements
766 system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use
767 system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks.
768 system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks.
769 system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks.
770 system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit.
771 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor
772 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy
773 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy
774 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
775 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
776 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
777 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
778 system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses
779 system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses
780 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits
781 system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits
782 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits
783 system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits
784 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits
785 system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits
786 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses
787 system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses
788 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses
789 system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses
790 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses
791 system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses
792 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles
793 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles
794 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles
795 system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles
796 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles
797 system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles
798 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses)
799 system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses)
800 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses
801 system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses
802 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses
803 system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses
804 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses
805 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses
806 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses
807 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses
808 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses
809 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses
810 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency
811 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency
812 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency
813 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency
814 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency
815 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency
816 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
817 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
818 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
819 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
820 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
821 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
822 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
823 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
824 system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks
825 system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks
826 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses
827 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses
828 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses
829 system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses
830 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses
831 system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses
832 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles
833 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles
834 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles
835 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles
836 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles
837 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles
838 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses
839 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses
840 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses
841 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses
842 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses
843 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses
844 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency
845 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency
846 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency
847 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency
848 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency
849 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency
850 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
851 system.cpu.icache.tags.replacements 979952 # number of replacements
852 system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use
853 system.cpu.icache.tags.total_refs 7892668 # Total number of references to valid blocks.
854 system.cpu.icache.tags.sampled_refs 980464 # Sample count of references to valid blocks.
855 system.cpu.icache.tags.avg_refs 8.049931 # Average number of references to valid blocks.
856 system.cpu.icache.tags.warmup_cycle 150322947500 # Cycle when the warmup percentage was hit.
857 system.cpu.icache.tags.occ_blocks::cpu.inst 509.399185 # Average occupied blocks per requestor
858 system.cpu.icache.tags.occ_percent::cpu.inst 0.994920 # Average percentage of cache occupancy
859 system.cpu.icache.tags.occ_percent::total 0.994920 # Average percentage of cache occupancy
860 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
861 system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
862 system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
863 system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id
864 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
865 system.cpu.icache.tags.tag_accesses 9920034 # Number of tag accesses
866 system.cpu.icache.tags.data_accesses 9920034 # Number of data accesses
867 system.cpu.icache.ReadReq_hits::cpu.inst 7892668 # number of ReadReq hits
868 system.cpu.icache.ReadReq_hits::total 7892668 # number of ReadReq hits
869 system.cpu.icache.demand_hits::cpu.inst 7892668 # number of demand (read+write) hits
870 system.cpu.icache.demand_hits::total 7892668 # number of demand (read+write) hits
871 system.cpu.icache.overall_hits::cpu.inst 7892668 # number of overall hits
872 system.cpu.icache.overall_hits::total 7892668 # number of overall hits
873 system.cpu.icache.ReadReq_misses::cpu.inst 1046827 # number of ReadReq misses
874 system.cpu.icache.ReadReq_misses::total 1046827 # number of ReadReq misses
875 system.cpu.icache.demand_misses::cpu.inst 1046827 # number of demand (read+write) misses
876 system.cpu.icache.demand_misses::total 1046827 # number of demand (read+write) misses
877 system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses
878 system.cpu.icache.overall_misses::total 1046827 # number of overall misses
879 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles
880 system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles
881 system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles
882 system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles
883 system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles
884 system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles
885 system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses)
886 system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses)
887 system.cpu.icache.demand_accesses::cpu.inst 8939495 # number of demand (read+write) accesses
888 system.cpu.icache.demand_accesses::total 8939495 # number of demand (read+write) accesses
889 system.cpu.icache.overall_accesses::cpu.inst 8939495 # number of overall (read+write) accesses
890 system.cpu.icache.overall_accesses::total 8939495 # number of overall (read+write) accesses
891 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117101 # miss rate for ReadReq accesses
892 system.cpu.icache.ReadReq_miss_rate::total 0.117101 # miss rate for ReadReq accesses
893 system.cpu.icache.demand_miss_rate::cpu.inst 0.117101 # miss rate for demand accesses
894 system.cpu.icache.demand_miss_rate::total 0.117101 # miss rate for demand accesses
895 system.cpu.icache.overall_miss_rate::cpu.inst 0.117101 # miss rate for overall accesses
896 system.cpu.icache.overall_miss_rate::total 0.117101 # miss rate for overall accesses
897 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745 # average ReadReq miss latency
898 system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745 # average ReadReq miss latency
899 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency
900 system.cpu.icache.demand_avg_miss_latency::total 14978.489745 # average overall miss latency
901 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency
902 system.cpu.icache.overall_avg_miss_latency::total 14978.489745 # average overall miss latency
903 system.cpu.icache.blocked_cycles::no_mshrs 13392 # number of cycles access was blocked
904 system.cpu.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked
905 system.cpu.icache.blocked::no_mshrs 457 # number of cycles access was blocked
906 system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
907 system.cpu.icache.avg_blocked_cycles::no_mshrs 29.304158 # average number of cycles each access was blocked
908 system.cpu.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked
909 system.cpu.icache.fast_writes 0 # number of fast writes performed
910 system.cpu.icache.cache_copies 0 # number of cache copies performed
911 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66288 # number of ReadReq MSHR hits
912 system.cpu.icache.ReadReq_mshr_hits::total 66288 # number of ReadReq MSHR hits
913 system.cpu.icache.demand_mshr_hits::cpu.inst 66288 # number of demand (read+write) MSHR hits
914 system.cpu.icache.demand_mshr_hits::total 66288 # number of demand (read+write) MSHR hits
915 system.cpu.icache.overall_mshr_hits::cpu.inst 66288 # number of overall MSHR hits
916 system.cpu.icache.overall_mshr_hits::total 66288 # number of overall MSHR hits
917 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980539 # number of ReadReq MSHR misses
918 system.cpu.icache.ReadReq_mshr_misses::total 980539 # number of ReadReq MSHR misses
919 system.cpu.icache.demand_mshr_misses::cpu.inst 980539 # number of demand (read+write) MSHR misses
920 system.cpu.icache.demand_mshr_misses::total 980539 # number of demand (read+write) MSHR misses
921 system.cpu.icache.overall_mshr_misses::cpu.inst 980539 # number of overall MSHR misses
922 system.cpu.icache.overall_mshr_misses::total 980539 # number of overall MSHR misses
923 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13806283989 # number of ReadReq MSHR miss cycles
924 system.cpu.icache.ReadReq_mshr_miss_latency::total 13806283989 # number of ReadReq MSHR miss cycles
925 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13806283989 # number of demand (read+write) MSHR miss cycles
926 system.cpu.icache.demand_mshr_miss_latency::total 13806283989 # number of demand (read+write) MSHR miss cycles
927 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13806283989 # number of overall MSHR miss cycles
928 system.cpu.icache.overall_mshr_miss_latency::total 13806283989 # number of overall MSHR miss cycles
929 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for ReadReq accesses
930 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109686 # mshr miss rate for ReadReq accesses
931 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for demand accesses
932 system.cpu.icache.demand_mshr_miss_rate::total 0.109686 # mshr miss rate for demand accesses
933 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for overall accesses
934 system.cpu.icache.overall_mshr_miss_rate::total 0.109686 # mshr miss rate for overall accesses
935 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721 # average ReadReq mshr miss latency
936 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721 # average ReadReq mshr miss latency
937 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency
938 system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency
939 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency
940 system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency
941 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
942 system.cpu.itb_walker_cache.tags.replacements 19284 # number of replacements
943 system.cpu.itb_walker_cache.tags.tagsinuse 6.025119 # Cycle average of tags in use
944 system.cpu.itb_walker_cache.tags.total_refs 17613 # Total number of references to valid blocks.
945 system.cpu.itb_walker_cache.tags.sampled_refs 19298 # Sample count of references to valid blocks.
946 system.cpu.itb_walker_cache.tags.avg_refs 0.912685 # Average number of references to valid blocks.
947 system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000 # Cycle when the warmup percentage was hit.
948 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.025119 # Average occupied blocks per requestor
949 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376570 # Average percentage of cache occupancy
950 system.cpu.itb_walker_cache.tags.occ_percent::total 0.376570 # Average percentage of cache occupancy
951 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
952 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
953 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
954 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
955 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
956 system.cpu.itb_walker_cache.tags.tag_accesses 95741 # Number of tag accesses
957 system.cpu.itb_walker_cache.tags.data_accesses 95741 # Number of data accesses
958 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 17618 # number of ReadReq hits
959 system.cpu.itb_walker_cache.ReadReq_hits::total 17618 # number of ReadReq hits
960 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
961 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
962 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 17620 # number of demand (read+write) hits
963 system.cpu.itb_walker_cache.demand_hits::total 17620 # number of demand (read+write) hits
964 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 17620 # number of overall hits
965 system.cpu.itb_walker_cache.overall_hits::total 17620 # number of overall hits
966 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 20167 # number of ReadReq misses
967 system.cpu.itb_walker_cache.ReadReq_misses::total 20167 # number of ReadReq misses
968 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 20167 # number of demand (read+write) misses
969 system.cpu.itb_walker_cache.demand_misses::total 20167 # number of demand (read+write) misses
970 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 20167 # number of overall misses
971 system.cpu.itb_walker_cache.overall_misses::total 20167 # number of overall misses
972 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 233184000 # number of ReadReq miss cycles
973 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 233184000 # number of ReadReq miss cycles
974 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 233184000 # number of demand (read+write) miss cycles
975 system.cpu.itb_walker_cache.demand_miss_latency::total 233184000 # number of demand (read+write) miss cycles
976 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 233184000 # number of overall miss cycles
977 system.cpu.itb_walker_cache.overall_miss_latency::total 233184000 # number of overall miss cycles
978 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37785 # number of ReadReq accesses(hits+misses)
979 system.cpu.itb_walker_cache.ReadReq_accesses::total 37785 # number of ReadReq accesses(hits+misses)
980 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
981 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
982 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37787 # number of demand (read+write) accesses
983 system.cpu.itb_walker_cache.demand_accesses::total 37787 # number of demand (read+write) accesses
984 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37787 # number of overall (read+write) accesses
985 system.cpu.itb_walker_cache.overall_accesses::total 37787 # number of overall (read+write) accesses
986 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.533730 # miss rate for ReadReq accesses
987 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.533730 # miss rate for ReadReq accesses
988 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.533702 # miss rate for demand accesses
989 system.cpu.itb_walker_cache.demand_miss_rate::total 0.533702 # miss rate for demand accesses
990 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.533702 # miss rate for overall accesses
991 system.cpu.itb_walker_cache.overall_miss_rate::total 0.533702 # miss rate for overall accesses
992 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857 # average ReadReq miss latency
993 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857 # average ReadReq miss latency
994 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency
995 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857 # average overall miss latency
996 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency
997 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857 # average overall miss latency
998 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
999 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1000 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1001 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1002 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1003 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1004 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1005 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1006 system.cpu.itb_walker_cache.writebacks::writebacks 3197 # number of writebacks
1007 system.cpu.itb_walker_cache.writebacks::total 3197 # number of writebacks
1008 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 20167 # number of ReadReq MSHR misses
1009 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 20167 # number of ReadReq MSHR misses
1010 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 20167 # number of demand (read+write) MSHR misses
1011 system.cpu.itb_walker_cache.demand_mshr_misses::total 20167 # number of demand (read+write) MSHR misses
1012 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 20167 # number of overall MSHR misses
1013 system.cpu.itb_walker_cache.overall_mshr_misses::total 20167 # number of overall MSHR misses
1014 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 213017000 # number of ReadReq MSHR miss cycles
1015 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 213017000 # number of ReadReq MSHR miss cycles
1016 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 213017000 # number of demand (read+write) MSHR miss cycles
1017 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 213017000 # number of demand (read+write) MSHR miss cycles
1018 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 213017000 # number of overall MSHR miss cycles
1019 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 213017000 # number of overall MSHR miss cycles
1020 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.533730 # mshr miss rate for ReadReq accesses
1021 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.533730 # mshr miss rate for ReadReq accesses
1022 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for demand accesses
1023 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.533702 # mshr miss rate for demand accesses
1024 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for overall accesses
1025 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.533702 # mshr miss rate for overall accesses
1026 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average ReadReq mshr miss latency
1027 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857 # average ReadReq mshr miss latency
1028 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency
1029 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency
1030 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency
1031 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency
1032 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1033 system.cpu.l2cache.tags.replacements 111670 # number of replacements
1034 system.cpu.l2cache.tags.tagsinuse 64798.131266 # Cycle average of tags in use
1035 system.cpu.l2cache.tags.total_refs 4919632 # Total number of references to valid blocks.
1036 system.cpu.l2cache.tags.sampled_refs 175949 # Sample count of references to valid blocks.
1037 system.cpu.l2cache.tags.avg_refs 27.960557 # Average number of references to valid blocks.
1038 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1039 system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380 # Average occupied blocks per requestor
1040 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.940071 # Average occupied blocks per requestor
1041 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139536 # Average occupied blocks per requestor
1042 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3193.810391 # Average occupied blocks per requestor
1043 system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889 # Average occupied blocks per requestor
1044 system.cpu.l2cache.tags.occ_percent::writebacks 0.770836 # Average percentage of cache occupancy
1045 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000167 # Average percentage of cache occupancy
1046 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1047 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048734 # Average percentage of cache occupancy
1048 system.cpu.l2cache.tags.occ_percent::cpu.data 0.169002 # Average percentage of cache occupancy
1049 system.cpu.l2cache.tags.occ_percent::total 0.988741 # Average percentage of cache occupancy
1050 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64279 # Occupied blocks per task id
1051 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
1052 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 676 # Occupied blocks per task id
1053 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3413 # Occupied blocks per task id
1054 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5955 # Occupied blocks per task id
1055 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54192 # Occupied blocks per task id
1056 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980820 # Percentage of cache occupancy per task id
1057 system.cpu.l2cache.tags.tag_accesses 43682151 # Number of tag accesses
1058 system.cpu.l2cache.tags.data_accesses 43682151 # Number of data accesses
1059 system.cpu.l2cache.Writeback_hits::writebacks 1585410 # number of Writeback hits
1060 system.cpu.l2cache.Writeback_hits::total 1585410 # number of Writeback hits
1061 system.cpu.l2cache.UpgradeReq_hits::cpu.data 346 # number of UpgradeReq hits
1062 system.cpu.l2cache.UpgradeReq_hits::total 346 # number of UpgradeReq hits
1063 system.cpu.l2cache.ReadExReq_hits::cpu.data 155314 # number of ReadExReq hits
1064 system.cpu.l2cache.ReadExReq_hits::total 155314 # number of ReadExReq hits
1065 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 964131 # number of ReadCleanReq hits
1066 system.cpu.l2cache.ReadCleanReq_hits::total 964131 # number of ReadCleanReq hits
1067 system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 75809 # number of ReadSharedReq hits
1068 system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 15497 # number of ReadSharedReq hits
1069 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332951 # number of ReadSharedReq hits
1070 system.cpu.l2cache.ReadSharedReq_hits::total 1424257 # number of ReadSharedReq hits
1071 system.cpu.l2cache.demand_hits::cpu.dtb.walker 75809 # number of demand (read+write) hits
1072 system.cpu.l2cache.demand_hits::cpu.itb.walker 15497 # number of demand (read+write) hits
1073 system.cpu.l2cache.demand_hits::cpu.inst 964131 # number of demand (read+write) hits
1074 system.cpu.l2cache.demand_hits::cpu.data 1488265 # number of demand (read+write) hits
1075 system.cpu.l2cache.demand_hits::total 2543702 # number of demand (read+write) hits
1076 system.cpu.l2cache.overall_hits::cpu.dtb.walker 75809 # number of overall hits
1077 system.cpu.l2cache.overall_hits::cpu.itb.walker 15497 # number of overall hits
1078 system.cpu.l2cache.overall_hits::cpu.inst 964131 # number of overall hits
1079 system.cpu.l2cache.overall_hits::cpu.data 1488265 # number of overall hits
1080 system.cpu.l2cache.overall_hits::total 2543702 # number of overall hits
1081 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses
1082 system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses
1083 system.cpu.l2cache.ReadExReq_misses::cpu.data 132872 # number of ReadExReq misses
1084 system.cpu.l2cache.ReadExReq_misses::total 132872 # number of ReadExReq misses
1085 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16267 # number of ReadCleanReq misses
1086 system.cpu.l2cache.ReadCleanReq_misses::total 16267 # number of ReadCleanReq misses
1087 system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 62 # number of ReadSharedReq misses
1088 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
1089 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35699 # number of ReadSharedReq misses
1090 system.cpu.l2cache.ReadSharedReq_misses::total 35766 # number of ReadSharedReq misses
1091 system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses
1092 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1093 system.cpu.l2cache.demand_misses::cpu.inst 16267 # number of demand (read+write) misses
1094 system.cpu.l2cache.demand_misses::cpu.data 168571 # number of demand (read+write) misses
1095 system.cpu.l2cache.demand_misses::total 184905 # number of demand (read+write) misses
1096 system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses
1097 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1098 system.cpu.l2cache.overall_misses::cpu.inst 16267 # number of overall misses
1099 system.cpu.l2cache.overall_misses::cpu.data 168571 # number of overall misses
1100 system.cpu.l2cache.overall_misses::total 184905 # number of overall misses
1101 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 58198000 # number of UpgradeReq miss cycles
1102 system.cpu.l2cache.UpgradeReq_miss_latency::total 58198000 # number of UpgradeReq miss cycles
1103 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16980826000 # number of ReadExReq miss cycles
1104 system.cpu.l2cache.ReadExReq_miss_latency::total 16980826000 # number of ReadExReq miss cycles
1105 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2184446000 # number of ReadCleanReq miss cycles
1106 system.cpu.l2cache.ReadCleanReq_miss_latency::total 2184446000 # number of ReadCleanReq miss cycles
1107 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9139000 # number of ReadSharedReq miss cycles
1108 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 679500 # number of ReadSharedReq miss cycles
1109 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4828291000 # number of ReadSharedReq miss cycles
1110 system.cpu.l2cache.ReadSharedReq_miss_latency::total 4838109500 # number of ReadSharedReq miss cycles
1111 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9139000 # number of demand (read+write) miss cycles
1112 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 679500 # number of demand (read+write) miss cycles
1113 system.cpu.l2cache.demand_miss_latency::cpu.inst 2184446000 # number of demand (read+write) miss cycles
1114 system.cpu.l2cache.demand_miss_latency::cpu.data 21809117000 # number of demand (read+write) miss cycles
1115 system.cpu.l2cache.demand_miss_latency::total 24003381500 # number of demand (read+write) miss cycles
1116 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9139000 # number of overall miss cycles
1117 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679500 # number of overall miss cycles
1118 system.cpu.l2cache.overall_miss_latency::cpu.inst 2184446000 # number of overall miss cycles
1119 system.cpu.l2cache.overall_miss_latency::cpu.data 21809117000 # number of overall miss cycles
1120 system.cpu.l2cache.overall_miss_latency::total 24003381500 # number of overall miss cycles
1121 system.cpu.l2cache.Writeback_accesses::writebacks 1585410 # number of Writeback accesses(hits+misses)
1122 system.cpu.l2cache.Writeback_accesses::total 1585410 # number of Writeback accesses(hits+misses)
1123 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1808 # number of UpgradeReq accesses(hits+misses)
1124 system.cpu.l2cache.UpgradeReq_accesses::total 1808 # number of UpgradeReq accesses(hits+misses)
1125 system.cpu.l2cache.ReadExReq_accesses::cpu.data 288186 # number of ReadExReq accesses(hits+misses)
1126 system.cpu.l2cache.ReadExReq_accesses::total 288186 # number of ReadExReq accesses(hits+misses)
1127 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 980398 # number of ReadCleanReq accesses(hits+misses)
1128 system.cpu.l2cache.ReadCleanReq_accesses::total 980398 # number of ReadCleanReq accesses(hits+misses)
1129 system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 75871 # number of ReadSharedReq accesses(hits+misses)
1130 system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 15502 # number of ReadSharedReq accesses(hits+misses)
1131 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368650 # number of ReadSharedReq accesses(hits+misses)
1132 system.cpu.l2cache.ReadSharedReq_accesses::total 1460023 # number of ReadSharedReq accesses(hits+misses)
1133 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 75871 # number of demand (read+write) accesses
1134 system.cpu.l2cache.demand_accesses::cpu.itb.walker 15502 # number of demand (read+write) accesses
1135 system.cpu.l2cache.demand_accesses::cpu.inst 980398 # number of demand (read+write) accesses
1136 system.cpu.l2cache.demand_accesses::cpu.data 1656836 # number of demand (read+write) accesses
1137 system.cpu.l2cache.demand_accesses::total 2728607 # number of demand (read+write) accesses
1138 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 75871 # number of overall (read+write) accesses
1139 system.cpu.l2cache.overall_accesses::cpu.itb.walker 15502 # number of overall (read+write) accesses
1140 system.cpu.l2cache.overall_accesses::cpu.inst 980398 # number of overall (read+write) accesses
1141 system.cpu.l2cache.overall_accesses::cpu.data 1656836 # number of overall (read+write) accesses
1142 system.cpu.l2cache.overall_accesses::total 2728607 # number of overall (read+write) accesses
1143 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808628 # miss rate for UpgradeReq accesses
1144 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808628 # miss rate for UpgradeReq accesses
1145 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461063 # miss rate for ReadExReq accesses
1146 system.cpu.l2cache.ReadExReq_miss_rate::total 0.461063 # miss rate for ReadExReq accesses
1147 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016592 # miss rate for ReadCleanReq accesses
1148 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016592 # miss rate for ReadCleanReq accesses
1149 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000817 # miss rate for ReadSharedReq accesses
1150 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000323 # miss rate for ReadSharedReq accesses
1151 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026083 # miss rate for ReadSharedReq accesses
1152 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024497 # miss rate for ReadSharedReq accesses
1153 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000817 # miss rate for demand accesses
1154 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000323 # miss rate for demand accesses
1155 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016592 # miss rate for demand accesses
1156 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101743 # miss rate for demand accesses
1157 system.cpu.l2cache.demand_miss_rate::total 0.067765 # miss rate for demand accesses
1158 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000817 # miss rate for overall accesses
1159 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000323 # miss rate for overall accesses
1160 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016592 # miss rate for overall accesses
1161 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101743 # miss rate for overall accesses
1162 system.cpu.l2cache.overall_miss_rate::total 0.067765 # miss rate for overall accesses
1163 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39807.113543 # average UpgradeReq miss latency
1164 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39807.113543 # average UpgradeReq miss latency
1165 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127798.377386 # average ReadExReq miss latency
1166 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127798.377386 # average ReadExReq miss latency
1167 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134286.961333 # average ReadCleanReq miss latency
1168 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134286.961333 # average ReadCleanReq miss latency
1169 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147403.225806 # average ReadSharedReq miss latency
1170 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135900 # average ReadSharedReq miss latency
1171 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135250.035015 # average ReadSharedReq miss latency
1172 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135271.193312 # average ReadSharedReq miss latency
1173 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147403.225806 # average overall miss latency
1174 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135900 # average overall miss latency
1175 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134286.961333 # average overall miss latency
1176 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129376.446720 # average overall miss latency
1177 system.cpu.l2cache.demand_avg_miss_latency::total 129814.669695 # average overall miss latency
1178 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147403.225806 # average overall miss latency
1179 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135900 # average overall miss latency
1180 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134286.961333 # average overall miss latency
1181 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129376.446720 # average overall miss latency
1182 system.cpu.l2cache.overall_avg_miss_latency::total 129814.669695 # average overall miss latency
1183 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1184 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1185 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1186 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1187 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1188 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1189 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1190 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1191 system.cpu.l2cache.writebacks::writebacks 102325 # number of writebacks
1192 system.cpu.l2cache.writebacks::total 102325 # number of writebacks
1193 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
1194 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
1195 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 2 # number of ReadSharedReq MSHR hits
1196 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
1197 system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
1198 system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
1199 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
1200 system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
1201 system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
1202 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
1203 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses
1204 system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses
1205 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses
1206 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses
1207 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132872 # number of ReadExReq MSHR misses
1208 system.cpu.l2cache.ReadExReq_mshr_misses::total 132872 # number of ReadExReq MSHR misses
1209 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16264 # number of ReadCleanReq MSHR misses
1210 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16264 # number of ReadCleanReq MSHR misses
1211 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 62 # number of ReadSharedReq MSHR misses
1212 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
1213 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35697 # number of ReadSharedReq MSHR misses
1214 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35764 # number of ReadSharedReq MSHR misses
1215 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses
1216 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1217 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16264 # number of demand (read+write) MSHR misses
1218 system.cpu.l2cache.demand_mshr_misses::cpu.data 168569 # number of demand (read+write) MSHR misses
1219 system.cpu.l2cache.demand_mshr_misses::total 184900 # number of demand (read+write) MSHR misses
1220 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses
1221 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1222 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16264 # number of overall MSHR misses
1223 system.cpu.l2cache.overall_mshr_misses::cpu.data 168569 # number of overall MSHR misses
1224 system.cpu.l2cache.overall_mshr_misses::total 184900 # number of overall MSHR misses
1225 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable
1226 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable
1227 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable
1228 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable
1229 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses
1230 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses
1231 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104470500 # number of UpgradeReq MSHR miss cycles
1232 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104470500 # number of UpgradeReq MSHR miss cycles
1233 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15652106000 # number of ReadExReq MSHR miss cycles
1234 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15652106000 # number of ReadExReq MSHR miss cycles
1235 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2021465000 # number of ReadCleanReq MSHR miss cycles
1236 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2021465000 # number of ReadCleanReq MSHR miss cycles
1237 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8519000 # number of ReadSharedReq MSHR miss cycles
1238 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 629500 # number of ReadSharedReq MSHR miss cycles
1239 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4471847000 # number of ReadSharedReq MSHR miss cycles
1240 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4480995500 # number of ReadSharedReq MSHR miss cycles
1241 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8519000 # number of demand (read+write) MSHR miss cycles
1242 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 629500 # number of demand (read+write) MSHR miss cycles
1243 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2021465000 # number of demand (read+write) MSHR miss cycles
1244 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20123953000 # number of demand (read+write) MSHR miss cycles
1245 system.cpu.l2cache.demand_mshr_miss_latency::total 22154566500 # number of demand (read+write) MSHR miss cycles
1246 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8519000 # number of overall MSHR miss cycles
1247 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 629500 # number of overall MSHR miss cycles
1248 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2021465000 # number of overall MSHR miss cycles
1249 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20123953000 # number of overall MSHR miss cycles
1250 system.cpu.l2cache.overall_mshr_miss_latency::total 22154566500 # number of overall MSHR miss cycles
1251 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257667000 # number of ReadReq MSHR uncacheable cycles
1252 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257667000 # number of ReadReq MSHR uncacheable cycles
1253 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2456737500 # number of WriteReq MSHR uncacheable cycles
1254 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2456737500 # number of WriteReq MSHR uncacheable cycles
1255 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92714404500 # number of overall MSHR uncacheable cycles
1256 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92714404500 # number of overall MSHR uncacheable cycles
1257 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1258 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1259 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses
1260 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses
1261 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses
1262 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses
1263 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses
1264 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses
1265 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses
1266 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses
1267 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses
1268 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses
1269 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses
1270 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses
1271 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses
1272 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses
1273 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses
1274 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses
1275 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses
1276 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses
1277 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses
1278 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses
1279 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency
1280 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency
1281 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency
1282 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency
1283 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency
1284 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency
1285 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency
1286 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency
1287 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency
1288 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency
1289 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency
1290 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency
1291 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency
1292 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency
1293 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency
1294 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency
1295 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency
1296 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency
1297 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency
1298 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency
1299 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency
1300 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency
1301 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency
1302 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency
1303 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency
1304 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency
1305 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1306 system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter.
1307 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1308 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1309 system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter.
1310 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1311 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1312 system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution
1315 system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution
1316 system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution
1317 system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution
1318 system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution
1319 system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution
1320 system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution
1321 system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution
1322 system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution
1323 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution
1324 system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution
1325 system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
1326 system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1327 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes)
1328 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes)
1329 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes)
1330 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes)
1331 system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes)
1332 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes)
1333 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes)
1334 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes)
1335 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes)
1336 system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes)
1337 system.cpu.toL2Bus.snoops 226924 # Total snoops (count)
1338 system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram
1339 system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram
1340 system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram
1341 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1342 system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram
1343 system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram
1344 system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram
1345 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
1346 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1347 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1348 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1349 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1350 system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram
1351 system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks)
1352 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1353 system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks)
1354 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1355 system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks)
1356 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1357 system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks)
1358 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1359 system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks)
1360 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1361 system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks)
1362 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1363 system.iobus.trans_dist::ReadReq 222097 # Transaction distribution
1364 system.iobus.trans_dist::ReadResp 222097 # Transaction distribution
1365 system.iobus.trans_dist::WriteReq 57711 # Transaction distribution
1366 system.iobus.trans_dist::WriteResp 57711 # Transaction distribution
1367 system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
1368 system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
1369 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1386 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1387 system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes)
1388 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
1389 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
1390 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
1391 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
1392 system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1410 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1411 system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes)
1412 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
1413 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
1414 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
1415 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
1416 system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes)
1417 system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks)
1418 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1419 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1420 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1421 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1422 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1423 system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks)
1424 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1426 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1428 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
1430 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1432 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1434 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks)
1436 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1438 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1439 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1440 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1441 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1442 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1443 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1444 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1445 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1446 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1447 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1448 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1449 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1450 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1451 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1452 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1453 system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks)
1454 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1455 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1456 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1457 system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks)
1458 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1459 system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks)
1460 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1461 system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
1462 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1463 system.iocache.tags.replacements 47574 # number of replacements
1464 system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use
1465 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1466 system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
1467 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1468 system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit.
1469 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor
1470 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy
1471 system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy
1472 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1473 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1474 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1475 system.iocache.tags.tag_accesses 428661 # Number of tag accesses
1476 system.iocache.tags.data_accesses 428661 # Number of data accesses
1477 system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
1478 system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
1479 system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1480 system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
1481 system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
1482 system.iocache.demand_misses::total 909 # number of demand (read+write) misses
1483 system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
1484 system.iocache.overall_misses::total 909 # number of overall misses
1485 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles
1486 system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles
1487 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles
1488 system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles
1489 system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles
1490 system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles
1491 system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles
1492 system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles
1493 system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
1494 system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
1495 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1496 system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
1497 system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses
1498 system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses
1499 system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses
1500 system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses
1501 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1502 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1503 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1504 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1505 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1506 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1507 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1508 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1509 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency
1510 system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency
1511 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency
1512 system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency
1513 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency
1514 system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency
1515 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency
1516 system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency
1517 system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
1518 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1519 system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked
1520 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1521 system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked
1522 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1523 system.iocache.fast_writes 0 # number of fast writes performed
1524 system.iocache.cache_copies 0 # number of cache copies performed
1525 system.iocache.writebacks::writebacks 46667 # number of writebacks
1526 system.iocache.writebacks::total 46667 # number of writebacks
1527 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
1528 system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
1529 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1530 system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
1531 system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses
1532 system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses
1533 system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses
1534 system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses
1535 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles
1536 system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles
1537 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles
1538 system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles
1539 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles
1540 system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles
1541 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles
1542 system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles
1543 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1544 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1545 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1546 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1547 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1548 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1549 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1550 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1551 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency
1552 system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency
1553 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency
1554 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency
1555 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency
1556 system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency
1557 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency
1558 system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency
1559 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1560 system.membus.trans_dist::ReadReq 602897 # Transaction distribution
1561 system.membus.trans_dist::ReadResp 655826 # Transaction distribution
1562 system.membus.trans_dist::WriteReq 13882 # Transaction distribution
1563 system.membus.trans_dist::WriteResp 13882 # Transaction distribution
1564 system.membus.trans_dist::Writeback 148992 # Transaction distribution
1565 system.membus.trans_dist::CleanEvict 9700 # Transaction distribution
1566 system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution
1567 system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution
1568 system.membus.trans_dist::ReadExReq 132608 # Transaction distribution
1569 system.membus.trans_dist::ReadExResp 132605 # Transaction distribution
1570 system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution
1571 system.membus.trans_dist::MessageReq 1645 # Transaction distribution
1572 system.membus.trans_dist::MessageResp 1645 # Transaction distribution
1573 system.membus.trans_dist::BadAddressError 8 # Transaction distribution
1574 system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
1575 system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
1576 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
1577 system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
1578 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes)
1579 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes)
1580 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes)
1581 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
1582 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes)
1583 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes)
1584 system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes)
1585 system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes)
1586 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
1587 system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
1588 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes)
1589 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes)
1590 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes)
1591 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes)
1592 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
1593 system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
1594 system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes)
1595 system.membus.snoops 1616 # Total snoops (count)
1596 system.membus.snoop_fanout::samples 1012128 # Request fanout histogram
1597 system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram
1598 system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram
1599 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1600 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1601 system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram
1602 system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram
1603 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1604 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1605 system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1606 system.membus.snoop_fanout::total 1012128 # Request fanout histogram
1607 system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks)
1608 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1609 system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks)
1610 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1611 system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
1612 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1613 system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks)
1614 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1615 system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
1616 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1617 system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
1618 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1619 system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks)
1620 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1621 system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks)
1622 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1623 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1624 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1625 system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
1626 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1627 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1628 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1629 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1630 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1631 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1632 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1633 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1634 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1635 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1636 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1638 ---------- End Simulation Statistics ----------
projects / gem5.git / blob