2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.122213 # Number of seconds simulated
4 sim_ticks 5122212682000 # Number of ticks simulated
5 final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 178126 # Simulator instruction rate (inst/s)
8 host_op_rate 352092 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2236626113 # Simulator tick rate (ticks/s)
10 host_mem_usage 810964 # Number of bytes of host memory used
11 host_seconds 2290.15 # Real time elapsed on the host
12 sim_insts 407934867 # Number of instructions simulated
13 sim_ops 806343968 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11881280 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9569088 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9569088 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168768 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185645 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149517 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149517 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 825 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 204424 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2108689 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2319560 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 204424 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 204424 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1868155 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1868155 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1868155 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 825 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 204424 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2108689 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4187715 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185645 # Number of read requests accepted
52 system.physmem.writeReqs 196237 # Number of write requests accepted
53 system.physmem.readBursts 185645 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 196237 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11872960 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 10880320 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11881280 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 12559168 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 26214 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1708 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11253 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 10547 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 11972 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11655 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11971 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11254 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 11364 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11315 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11445 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11672 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11062 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11423 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 12308 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12737 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11748 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11789 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 11864 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 10686 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 10651 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 9860 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 10294 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 10368 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 9733 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 9712 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 9632 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 10471 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 10725 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 10392 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 11457 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 11384 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 11667 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 11109 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
97 system.physmem.totGap 5122212630000 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185645 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 196237 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 171240 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11542 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 1948 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 451 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 1627 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 1832 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 6256 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 6771 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 7099 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 7167 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 7342 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 7542 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 7845 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 7971 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 9622 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 8300 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 7727 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 10480 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8737 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 8045 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 7914 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 1477 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 1264 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 1705 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 2725 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 2849 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 2539 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 2444 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 3285 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 2479 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 2385 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 2208 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 2459 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 2080 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 1741 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 1599 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 1189 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 975 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 399 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 342 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 363 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 239 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 292 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 197 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 189 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 194 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 152 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 120 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 73901 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 307.887796 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 180.352303 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 329.737558 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 28243 38.22% 38.22% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17330 23.45% 61.67% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7468 10.11% 71.77% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4217 5.71% 77.48% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 3016 4.08% 81.56% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 1973 2.67% 84.23% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1390 1.88% 86.11% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1267 1.71% 87.83% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 8997 12.17% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 73901 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 6788 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 27.329258 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 584.024068 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 6787 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 6788 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 6788 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 25.044932 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.591825 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 43.260290 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-31 6382 94.02% 94.02% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::32-47 87 1.28% 95.30% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::48-63 9 0.13% 95.43% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::64-79 9 0.13% 95.57% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::80-95 22 0.32% 95.89% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::96-111 15 0.22% 96.11% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::112-127 29 0.43% 96.54% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::128-143 26 0.38% 96.92% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::144-159 35 0.52% 97.44% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::160-175 9 0.13% 97.57% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::176-191 41 0.60% 98.17% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::192-207 54 0.80% 98.97% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::208-223 7 0.10% 99.07% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::224-239 6 0.09% 99.16% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::256-271 1 0.01% 99.18% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::272-287 4 0.06% 99.23% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::288-303 2 0.03% 99.26% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::304-319 4 0.06% 99.32% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::320-335 3 0.04% 99.37% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::336-351 5 0.07% 99.44% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::352-367 19 0.28% 99.72% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::368-383 6 0.09% 99.81% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::384-399 1 0.01% 99.82% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::400-415 1 0.01% 99.84% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::464-479 1 0.01% 99.85% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::480-495 1 0.01% 99.87% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::496-511 3 0.04% 99.91% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::560-575 4 0.06% 100.00% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::total 6788 # Writes before turning the bus around for reads
263 system.physmem.totQLat 2015945224 # Total ticks spent queuing
264 system.physmem.totMemAccLat 5494351474 # Total ticks spent from burst creation until serviced by the DRAM
265 system.physmem.totBusLat 927575000 # Total ticks spent in databus transfers
266 system.physmem.avgQLat 10866.75 # Average queueing delay per DRAM burst
267 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268 system.physmem.avgMemAccLat 29616.75 # Average memory access latency per DRAM burst
269 system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
270 system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s
271 system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
272 system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
273 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274 system.physmem.busUtil 0.03 # Data bus utilization in percentage
275 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
276 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
277 system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
278 system.physmem.avgWrQLen 22.03 # Average write queue length when enqueuing
279 system.physmem.readRowHits 152167 # Number of row buffer hits during reads
280 system.physmem.writeRowHits 129451 # Number of row buffer hits during writes
281 system.physmem.readRowHitRate 82.02 # Row buffer hit rate for reads
282 system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
283 system.physmem.avgGap 13413076.89 # Average gap between requests
284 system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined
285 system.physmem_0.actEnergy 269256960 # Energy for activate commands per rank (pJ)
286 system.physmem_0.preEnergy 146916000 # Energy for precharge commands per rank (pJ)
287 system.physmem_0.readEnergy 712374000 # Energy for read commands per rank (pJ)
288 system.physmem_0.writeEnergy 538928640 # Energy for write commands per rank (pJ)
289 system.physmem_0.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
290 system.physmem_0.actBackEnergy 129214187775 # Energy for active background per rank (pJ)
291 system.physmem_0.preBackEnergy 2959979121750 # Energy for precharge background per rank (pJ)
292 system.physmem_0.totalEnergy 3425418506805 # Total energy per rank (pJ)
293 system.physmem_0.averagePower 668.738637 # Core power per rank (mW)
294 system.physmem_0.memoryStateTime::IDLE 4924130039468 # Time in different power states
295 system.physmem_0.memoryStateTime::REF 171041780000 # Time in different power states
296 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297 system.physmem_0.memoryStateTime::ACT 27040752032 # Time in different power states
298 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299 system.physmem_1.actEnergy 289434600 # Energy for activate commands per rank (pJ)
300 system.physmem_1.preEnergy 157925625 # Energy for precharge commands per rank (pJ)
301 system.physmem_1.readEnergy 734635200 # Energy for read commands per rank (pJ)
302 system.physmem_1.writeEnergy 562703760 # Energy for write commands per rank (pJ)
303 system.physmem_1.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ)
304 system.physmem_1.actBackEnergy 129751534755 # Energy for active background per rank (pJ)
305 system.physmem_1.preBackEnergy 2959507764750 # Energy for precharge background per rank (pJ)
306 system.physmem_1.totalEnergy 3425561720370 # Total energy per rank (pJ)
307 system.physmem_1.averagePower 668.766596 # Core power per rank (mW)
308 system.physmem_1.memoryStateTime::IDLE 4923333713433 # Time in different power states
309 system.physmem_1.memoryStateTime::REF 171041780000 # Time in different power states
310 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311 system.physmem_1.memoryStateTime::ACT 27832687817 # Time in different power states
312 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
313 system.cpu.branchPred.lookups 86818912 # Number of BP lookups
314 system.cpu.branchPred.condPredicted 86818912 # Number of conditional branches predicted
315 system.cpu.branchPred.condIncorrect 895085 # Number of conditional branches incorrect
316 system.cpu.branchPred.BTBLookups 80098723 # Number of BTB lookups
317 system.cpu.branchPred.BTBHits 78142837 # Number of BTB hits
318 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
319 system.cpu.branchPred.BTBHitPct 97.558156 # BTB Hit Percentage
320 system.cpu.branchPred.usedRAS 1551403 # Number of times the RAS was used to get a target.
321 system.cpu.branchPred.RASInCorrect 180089 # Number of incorrect RAS predictions.
322 system.cpu_clk_domain.clock 500 # Clock period in ticks
323 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
324 system.cpu.numCycles 449999443 # number of cpu cycles simulated
325 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
326 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
327 system.cpu.fetch.icacheStallCycles 27536923 # Number of cycles fetch is stalled on an Icache miss
328 system.cpu.fetch.Insts 428761982 # Number of instructions fetch has processed
329 system.cpu.fetch.Branches 86818912 # Number of branches that fetch encountered
330 system.cpu.fetch.predictedBranches 79694240 # Number of branches that fetch has predicted taken
331 system.cpu.fetch.Cycles 418469892 # Number of cycles fetch has run and was not squashing or blocked
332 system.cpu.fetch.SquashCycles 1877186 # Number of cycles fetch has spent squashing
333 system.cpu.fetch.TlbCycles 142405 # Number of cycles fetch has spent waiting for tlb
334 system.cpu.fetch.MiscStallCycles 58257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
335 system.cpu.fetch.PendingTrapStallCycles 203994 # Number of stall cycles due to pending traps
336 system.cpu.fetch.PendingQuiesceStallCycles 110 # Number of stall cycles due to pending quiesce instructions
337 system.cpu.fetch.IcacheWaitRetryStallCycles 541 # Number of stall cycles due to full MSHR
338 system.cpu.fetch.CacheLines 9116293 # Number of cache lines fetched
339 system.cpu.fetch.IcacheSquashes 453128 # Number of outstanding Icache misses that were squashed
340 system.cpu.fetch.ItlbSquashes 4723 # Number of outstanding ITLB misses that were squashed
341 system.cpu.fetch.rateDist::samples 447350715 # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::mean 1.891249 # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::stdev 3.050769 # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::0 282061925 63.05% 63.05% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::1 2147503 0.48% 63.53% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::2 72168287 16.13% 79.66% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::3 1568006 0.35% 80.01% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::4 2127596 0.48% 80.49% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::5 2318806 0.52% 81.01% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::6 1512611 0.34% 81.35% # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::7 1884650 0.42% 81.77% # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::8 81561331 18.23% 100.00% # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
355 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
357 system.cpu.fetch.rateDist::total 447350715 # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.branchRate 0.192931 # Number of branch fetches per cycle
359 system.cpu.fetch.rate 0.952806 # Number of inst fetches per cycle
360 system.cpu.decode.IdleCycles 22908567 # Number of cycles decode is idle
361 system.cpu.decode.BlockedCycles 265367852 # Number of cycles decode is blocked
362 system.cpu.decode.RunCycles 150702709 # Number of cycles decode is running
363 system.cpu.decode.UnblockCycles 7432994 # Number of cycles decode is unblocking
364 system.cpu.decode.SquashCycles 938593 # Number of cycles decode is squashing
365 system.cpu.decode.DecodedInsts 837990299 # Number of instructions handled by decode
366 system.cpu.rename.SquashCycles 938593 # Number of cycles rename is squashing
367 system.cpu.rename.IdleCycles 25758226 # Number of cycles rename is idle
368 system.cpu.rename.BlockCycles 223276953 # Number of cycles rename is blocking
369 system.cpu.rename.serializeStallCycles 12890661 # count of cycles rename stalled for serializing inst
370 system.cpu.rename.RunCycles 154592541 # Number of cycles rename is running
371 system.cpu.rename.UnblockCycles 29893741 # Number of cycles rename is unblocking
372 system.cpu.rename.RenamedInsts 834466404 # Number of instructions processed by rename
373 system.cpu.rename.ROBFullEvents 451836 # Number of times rename has blocked due to ROB full
374 system.cpu.rename.IQFullEvents 12178537 # Number of times rename has blocked due to IQ full
375 system.cpu.rename.LQFullEvents 145180 # Number of times rename has blocked due to LQ full
376 system.cpu.rename.SQFullEvents 14794285 # Number of times rename has blocked due to SQ full
377 system.cpu.rename.RenamedOperands 996780528 # Number of destination operands rename has renamed
378 system.cpu.rename.RenameLookups 1812316725 # Number of register rename lookups that rename has made
379 system.cpu.rename.int_rename_lookups 1114082490 # Number of integer rename lookups
380 system.cpu.rename.fp_rename_lookups 470 # Number of floating rename lookups
381 system.cpu.rename.CommittedMaps 964296204 # Number of HB maps that are committed
382 system.cpu.rename.UndoneMaps 32484322 # Number of HB maps that are undone due to squashing
383 system.cpu.rename.serializingInsts 461178 # count of serializing insts renamed
384 system.cpu.rename.tempSerializingInsts 464876 # count of temporary serializing insts renamed
385 system.cpu.rename.skidInsts 38644871 # count of insts added to the skid buffer
386 system.cpu.memDep0.insertedLoads 17242919 # Number of loads inserted to the mem dependence unit.
387 system.cpu.memDep0.insertedStores 10123129 # Number of stores inserted to the mem dependence unit.
388 system.cpu.memDep0.conflictingLoads 1280249 # Number of conflicting loads.
389 system.cpu.memDep0.conflictingStores 1072002 # Number of conflicting stores.
390 system.cpu.iq.iqInstsAdded 828945592 # Number of instructions added to the IQ (excludes non-spec)
391 system.cpu.iq.iqNonSpecInstsAdded 1192163 # Number of non-speculative instructions added to the IQ
392 system.cpu.iq.iqInstsIssued 823760090 # Number of instructions issued
393 system.cpu.iq.iqSquashedInstsIssued 244912 # Number of squashed instructions issued
394 system.cpu.iq.iqSquashedInstsExamined 23793782 # Number of squashed instructions iterated over during squash; mainly for profiling
395 system.cpu.iq.iqSquashedOperandsExamined 35793426 # Number of squashed operands that are examined and possibly removed from graph
396 system.cpu.iq.iqSquashedNonSpecRemoved 146866 # Number of squashed non-spec instructions that were removed
397 system.cpu.iq.issued_per_cycle::samples 447350715 # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::mean 1.841419 # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::stdev 2.417821 # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::0 263279849 58.85% 58.85% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::1 13891965 3.11% 61.96% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::2 9851915 2.20% 64.16% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::3 7048956 1.58% 65.74% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::4 74303394 16.61% 82.35% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::5 4391366 0.98% 83.33% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::6 72807233 16.28% 99.60% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::7 1204673 0.27% 99.87% # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::8 571364 0.13% 100.00% # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
411 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
412 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
413 system.cpu.iq.issued_per_cycle::total 447350715 # Number of insts issued each cycle
414 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
415 system.cpu.iq.fu_full::IntAlu 1986394 72.18% 72.18% # attempts to use FU when none available
416 system.cpu.iq.fu_full::IntMult 0 0.00% 72.18% # attempts to use FU when none available
417 system.cpu.iq.fu_full::IntDiv 0 0.00% 72.18% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.18% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.18% # attempts to use FU when none available
420 system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.18% # attempts to use FU when none available
421 system.cpu.iq.fu_full::FloatMult 0 0.00% 72.18% # attempts to use FU when none available
422 system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.18% # attempts to use FU when none available
423 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.18% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.18% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.18% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.18% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.18% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.18% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdMult 0 0.00% 72.18% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.18% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdShift 0 0.00% 72.18% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.18% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.18% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.18% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.18% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.18% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.18% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.18% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.18% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.18% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.18% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.18% # attempts to use FU when none available
444 system.cpu.iq.fu_full::MemRead 608344 22.10% 94.28% # attempts to use FU when none available
445 system.cpu.iq.fu_full::MemWrite 157420 5.72% 100.00% # attempts to use FU when none available
446 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
447 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
448 system.cpu.iq.FU_type_0::No_OpClass 285236 0.03% 0.03% # Type of FU issued
449 system.cpu.iq.FU_type_0::IntAlu 795541833 96.57% 96.61% # Type of FU issued
450 system.cpu.iq.FU_type_0::IntMult 150365 0.02% 96.63% # Type of FU issued
451 system.cpu.iq.FU_type_0::IntDiv 127447 0.02% 96.64% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatCvt 108 0.00% 96.64% # Type of FU issued
455 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued
456 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued
457 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued
478 system.cpu.iq.FU_type_0::MemRead 18320687 2.22% 98.87% # Type of FU issued
479 system.cpu.iq.FU_type_0::MemWrite 9334414 1.13% 100.00% # Type of FU issued
480 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
481 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
482 system.cpu.iq.FU_type_0::total 823760090 # Type of FU issued
483 system.cpu.iq.rate 1.830580 # Inst issue rate
484 system.cpu.iq.fu_busy_cnt 2752158 # FU busy when requested
485 system.cpu.iq.fu_busy_rate 0.003341 # FU busy rate (busy events/executed inst)
486 system.cpu.iq.int_inst_queue_reads 2097867450 # Number of integer instruction queue reads
487 system.cpu.iq.int_inst_queue_writes 853943468 # Number of integer instruction queue writes
488 system.cpu.iq.int_inst_queue_wakeup_accesses 819213197 # Number of integer instruction queue wakeup accesses
489 system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads
490 system.cpu.iq.fp_inst_queue_writes 630 # Number of floating instruction queue writes
491 system.cpu.iq.fp_inst_queue_wakeup_accesses 182 # Number of floating instruction queue wakeup accesses
492 system.cpu.iq.int_alu_accesses 826226763 # Number of integer alu accesses
493 system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses
494 system.cpu.iew.lsq.thread0.forwLoads 1860072 # Number of loads that had data forwarded from stores
495 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
496 system.cpu.iew.lsq.thread0.squashedLoads 3252614 # Number of loads squashed
497 system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed
498 system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations
499 system.cpu.iew.lsq.thread0.squashedStores 1702580 # Number of stores squashed
500 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
501 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
502 system.cpu.iew.lsq.thread0.rescheduledLoads 2208153 # Number of loads that were rescheduled
503 system.cpu.iew.lsq.thread0.cacheBlocked 72229 # Number of times an access to memory failed due to the cache being blocked
504 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
505 system.cpu.iew.iewSquashCycles 938593 # Number of cycles IEW is squashing
506 system.cpu.iew.iewBlockCycles 204923881 # Number of cycles IEW is blocking
507 system.cpu.iew.iewUnblockCycles 10223668 # Number of cycles IEW is unblocking
508 system.cpu.iew.iewDispatchedInsts 830137755 # Number of instructions dispatched to IQ
509 system.cpu.iew.iewDispSquashedInsts 158534 # Number of squashed instructions skipped by dispatch
510 system.cpu.iew.iewDispLoadInsts 17242919 # Number of dispatched load instructions
511 system.cpu.iew.iewDispStoreInsts 10123129 # Number of dispatched store instructions
512 system.cpu.iew.iewDispNonSpecInsts 698460 # Number of dispatched non-speculative instructions
513 system.cpu.iew.iewIQFullEvents 397050 # Number of times the IQ has become full, causing a stall
514 system.cpu.iew.iewLSQFullEvents 8973453 # Number of times the LSQ has become full, causing a stall
515 system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations
516 system.cpu.iew.predictedTakenIncorrect 514177 # Number of branches that were predicted taken incorrectly
517 system.cpu.iew.predictedNotTakenIncorrect 531213 # Number of branches that were predicted not taken incorrectly
518 system.cpu.iew.branchMispredicts 1045390 # Number of branch mispredicts detected at execute
519 system.cpu.iew.iewExecutedInsts 822137992 # Number of executed instructions
520 system.cpu.iew.iewExecLoadInsts 17928402 # Number of load instructions executed
521 system.cpu.iew.iewExecSquashedInsts 1491599 # Number of squashed instructions skipped in execute
522 system.cpu.iew.exec_swp 0 # number of swp insts executed
523 system.cpu.iew.exec_nop 0 # number of nop insts executed
524 system.cpu.iew.exec_refs 27038601 # number of memory reference insts executed
525 system.cpu.iew.exec_branches 83256358 # Number of branches executed
526 system.cpu.iew.exec_stores 9110199 # Number of stores executed
527 system.cpu.iew.exec_rate 1.826976 # Inst execution rate
528 system.cpu.iew.wb_sent 821634339 # cumulative count of insts sent to commit
529 system.cpu.iew.wb_count 819213379 # cumulative count of insts written-back
530 system.cpu.iew.wb_producers 640695638 # num instructions producing a value
531 system.cpu.iew.wb_consumers 1049922326 # num instructions consuming a value
532 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
533 system.cpu.iew.wb_rate 1.820476 # insts written-back per cycle
534 system.cpu.iew.wb_fanout 0.610231 # average fanout of values written-back
535 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
536 system.cpu.commit.commitSquashedInsts 23667492 # The number of squashed insts skipped by commit
537 system.cpu.commit.commitNonSpecStalls 1045297 # The number of times commit has been forced to stall to communicate backwards
538 system.cpu.commit.branchMispredicts 906773 # The number of times a branch was mispredicted
539 system.cpu.commit.committed_per_cycle::samples 443789392 # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::mean 1.816952 # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::stdev 2.674122 # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::0 272960111 61.51% 61.51% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::1 11180384 2.52% 64.03% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::2 3592831 0.81% 64.84% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::3 74586039 16.81% 81.64% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::4 2426818 0.55% 82.19% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::5 1631046 0.37% 82.56% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::6 941888 0.21% 82.77% # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::7 71056225 16.01% 98.78% # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::8 5414050 1.22% 100.00% # Number of insts commited each cycle
552 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
553 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
554 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
555 system.cpu.commit.committed_per_cycle::total 443789392 # Number of insts commited each cycle
556 system.cpu.commit.committedInsts 407934867 # Number of instructions committed
557 system.cpu.commit.committedOps 806343968 # Number of ops (including micro ops) committed
558 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
559 system.cpu.commit.refs 22410853 # Number of memory references committed
560 system.cpu.commit.loads 13990304 # Number of loads committed
561 system.cpu.commit.membars 471837 # Number of memory barriers committed
562 system.cpu.commit.branches 82192569 # Number of branches committed
563 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
564 system.cpu.commit.int_insts 735158454 # Number of committed integer instructions.
565 system.cpu.commit.function_calls 1155650 # Number of function calls committed.
566 system.cpu.commit.op_class_0::No_OpClass 171552 0.02% 0.02% # Class of committed instruction
567 system.cpu.commit.op_class_0::IntAlu 783497766 97.17% 97.19% # Class of committed instruction
568 system.cpu.commit.op_class_0::IntMult 144918 0.02% 97.21% # Class of committed instruction
569 system.cpu.commit.op_class_0::IntDiv 121442 0.02% 97.22% # Class of committed instruction
570 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
572 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
573 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
574 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
575 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
593 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
595 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
596 system.cpu.commit.op_class_0::MemRead 13987725 1.73% 98.96% # Class of committed instruction
597 system.cpu.commit.op_class_0::MemWrite 8420549 1.04% 100.00% # Class of committed instruction
598 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
599 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
600 system.cpu.commit.op_class_0::total 806343968 # Class of committed instruction
601 system.cpu.commit.bw_lim_events 5414050 # number cycles where commit BW limit reached
602 system.cpu.rob.rob_reads 1268308634 # The number of ROB reads
603 system.cpu.rob.rob_writes 1663603607 # The number of ROB writes
604 system.cpu.timesIdled 289860 # Number of times that the entire CPU went into an idle state and unscheduled itself
605 system.cpu.idleCycles 2648728 # Total number of cycles that the CPU has spent unscheduled due to idling
606 system.cpu.quiesceCycles 9794423343 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
607 system.cpu.committedInsts 407934867 # Number of Instructions Simulated
608 system.cpu.committedOps 806343968 # Number of Ops (including micro ops) Simulated
609 system.cpu.cpi 1.103116 # CPI: Cycles Per Instruction
610 system.cpu.cpi_total 1.103116 # CPI: Total CPI of All Threads
611 system.cpu.ipc 0.906523 # IPC: Instructions Per Cycle
612 system.cpu.ipc_total 0.906523 # IPC: Total IPC of All Threads
613 system.cpu.int_regfile_reads 1091825743 # number of integer regfile reads
614 system.cpu.int_regfile_writes 655727641 # number of integer regfile writes
615 system.cpu.fp_regfile_reads 182 # number of floating regfile reads
616 system.cpu.cc_regfile_reads 416065488 # number of cc regfile reads
617 system.cpu.cc_regfile_writes 321934300 # number of cc regfile writes
618 system.cpu.misc_regfile_reads 265346710 # number of misc regfile reads
619 system.cpu.misc_regfile_writes 399949 # number of misc regfile writes
620 system.cpu.dcache.tags.replacements 1659310 # number of replacements
621 system.cpu.dcache.tags.tagsinuse 511.993990 # Cycle average of tags in use
622 system.cpu.dcache.tags.total_refs 19061899 # Total number of references to valid blocks.
623 system.cpu.dcache.tags.sampled_refs 1659822 # Sample count of references to valid blocks.
624 system.cpu.dcache.tags.avg_refs 11.484303 # Average number of references to valid blocks.
625 system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit.
626 system.cpu.dcache.tags.occ_blocks::cpu.data 511.993990 # Average occupied blocks per requestor
627 system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
628 system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
629 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
630 system.cpu.dcache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
631 system.cpu.dcache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
632 system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
633 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
634 system.cpu.dcache.tags.tag_accesses 88087332 # Number of tag accesses
635 system.cpu.dcache.tags.data_accesses 88087332 # Number of data accesses
636 system.cpu.dcache.ReadReq_hits::cpu.data 10917280 # number of ReadReq hits
637 system.cpu.dcache.ReadReq_hits::total 10917280 # number of ReadReq hits
638 system.cpu.dcache.WriteReq_hits::cpu.data 8077307 # number of WriteReq hits
639 system.cpu.dcache.WriteReq_hits::total 8077307 # number of WriteReq hits
640 system.cpu.dcache.SoftPFReq_hits::cpu.data 64579 # number of SoftPFReq hits
641 system.cpu.dcache.SoftPFReq_hits::total 64579 # number of SoftPFReq hits
642 system.cpu.dcache.demand_hits::cpu.data 18994587 # number of demand (read+write) hits
643 system.cpu.dcache.demand_hits::total 18994587 # number of demand (read+write) hits
644 system.cpu.dcache.overall_hits::cpu.data 19059166 # number of overall hits
645 system.cpu.dcache.overall_hits::total 19059166 # number of overall hits
646 system.cpu.dcache.ReadReq_misses::cpu.data 1807757 # number of ReadReq misses
647 system.cpu.dcache.ReadReq_misses::total 1807757 # number of ReadReq misses
648 system.cpu.dcache.WriteReq_misses::cpu.data 333541 # number of WriteReq misses
649 system.cpu.dcache.WriteReq_misses::total 333541 # number of WriteReq misses
650 system.cpu.dcache.SoftPFReq_misses::cpu.data 406408 # number of SoftPFReq misses
651 system.cpu.dcache.SoftPFReq_misses::total 406408 # number of SoftPFReq misses
652 system.cpu.dcache.demand_misses::cpu.data 2141298 # number of demand (read+write) misses
653 system.cpu.dcache.demand_misses::total 2141298 # number of demand (read+write) misses
654 system.cpu.dcache.overall_misses::cpu.data 2547706 # number of overall misses
655 system.cpu.dcache.overall_misses::total 2547706 # number of overall misses
656 system.cpu.dcache.ReadReq_miss_latency::cpu.data 27202744445 # number of ReadReq miss cycles
657 system.cpu.dcache.ReadReq_miss_latency::total 27202744445 # number of ReadReq miss cycles
658 system.cpu.dcache.WriteReq_miss_latency::cpu.data 13955718277 # number of WriteReq miss cycles
659 system.cpu.dcache.WriteReq_miss_latency::total 13955718277 # number of WriteReq miss cycles
660 system.cpu.dcache.demand_miss_latency::cpu.data 41158462722 # number of demand (read+write) miss cycles
661 system.cpu.dcache.demand_miss_latency::total 41158462722 # number of demand (read+write) miss cycles
662 system.cpu.dcache.overall_miss_latency::cpu.data 41158462722 # number of overall miss cycles
663 system.cpu.dcache.overall_miss_latency::total 41158462722 # number of overall miss cycles
664 system.cpu.dcache.ReadReq_accesses::cpu.data 12725037 # number of ReadReq accesses(hits+misses)
665 system.cpu.dcache.ReadReq_accesses::total 12725037 # number of ReadReq accesses(hits+misses)
666 system.cpu.dcache.WriteReq_accesses::cpu.data 8410848 # number of WriteReq accesses(hits+misses)
667 system.cpu.dcache.WriteReq_accesses::total 8410848 # number of WriteReq accesses(hits+misses)
668 system.cpu.dcache.SoftPFReq_accesses::cpu.data 470987 # number of SoftPFReq accesses(hits+misses)
669 system.cpu.dcache.SoftPFReq_accesses::total 470987 # number of SoftPFReq accesses(hits+misses)
670 system.cpu.dcache.demand_accesses::cpu.data 21135885 # number of demand (read+write) accesses
671 system.cpu.dcache.demand_accesses::total 21135885 # number of demand (read+write) accesses
672 system.cpu.dcache.overall_accesses::cpu.data 21606872 # number of overall (read+write) accesses
673 system.cpu.dcache.overall_accesses::total 21606872 # number of overall (read+write) accesses
674 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142063 # miss rate for ReadReq accesses
675 system.cpu.dcache.ReadReq_miss_rate::total 0.142063 # miss rate for ReadReq accesses
676 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039656 # miss rate for WriteReq accesses
677 system.cpu.dcache.WriteReq_miss_rate::total 0.039656 # miss rate for WriteReq accesses
678 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862886 # miss rate for SoftPFReq accesses
679 system.cpu.dcache.SoftPFReq_miss_rate::total 0.862886 # miss rate for SoftPFReq accesses
680 system.cpu.dcache.demand_miss_rate::cpu.data 0.101311 # miss rate for demand accesses
681 system.cpu.dcache.demand_miss_rate::total 0.101311 # miss rate for demand accesses
682 system.cpu.dcache.overall_miss_rate::cpu.data 0.117912 # miss rate for overall accesses
683 system.cpu.dcache.overall_miss_rate::total 0.117912 # miss rate for overall accesses
684 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196 # average ReadReq miss latency
685 system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196 # average ReadReq miss latency
686 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833 # average WriteReq miss latency
687 system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833 # average WriteReq miss latency
688 system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998 # average overall miss latency
689 system.cpu.dcache.demand_avg_miss_latency::total 19221.267998 # average overall miss latency
690 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877 # average overall miss latency
691 system.cpu.dcache.overall_avg_miss_latency::total 16155.106877 # average overall miss latency
692 system.cpu.dcache.blocked_cycles::no_mshrs 414660 # number of cycles access was blocked
693 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
694 system.cpu.dcache.blocked::no_mshrs 43514 # number of cycles access was blocked
695 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
696 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.529347 # average number of cycles each access was blocked
697 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
698 system.cpu.dcache.fast_writes 0 # number of fast writes performed
699 system.cpu.dcache.cache_copies 0 # number of cache copies performed
700 system.cpu.dcache.writebacks::writebacks 1560749 # number of writebacks
701 system.cpu.dcache.writebacks::total 1560749 # number of writebacks
702 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 839489 # number of ReadReq MSHR hits
703 system.cpu.dcache.ReadReq_mshr_hits::total 839489 # number of ReadReq MSHR hits
704 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42702 # number of WriteReq MSHR hits
705 system.cpu.dcache.WriteReq_mshr_hits::total 42702 # number of WriteReq MSHR hits
706 system.cpu.dcache.demand_mshr_hits::cpu.data 882191 # number of demand (read+write) MSHR hits
707 system.cpu.dcache.demand_mshr_hits::total 882191 # number of demand (read+write) MSHR hits
708 system.cpu.dcache.overall_mshr_hits::cpu.data 882191 # number of overall MSHR hits
709 system.cpu.dcache.overall_mshr_hits::total 882191 # number of overall MSHR hits
710 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968268 # number of ReadReq MSHR misses
711 system.cpu.dcache.ReadReq_mshr_misses::total 968268 # number of ReadReq MSHR misses
712 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses
713 system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses
714 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses
715 system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses
716 system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses
717 system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
718 system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
719 system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses
720 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
721 system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
722 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
723 system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
724 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
725 system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
726 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
727 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
728 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
729 system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles
730 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles
731 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles
732 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles
733 system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles
734 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles
735 system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles
736 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles
737 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles
738 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles
739 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles
740 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles
741 system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles
742 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses
743 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses
744 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses
745 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses
746 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses
747 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses
748 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses
749 system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses
750 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses
751 system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses
752 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency
753 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency
754 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency
755 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency
756 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency
757 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency
758 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency
759 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
760 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
761 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency
762 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency
763 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency
764 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency
765 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency
766 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency
767 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency
768 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
769 system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
770 system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
771 system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks.
772 system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks.
773 system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks.
774 system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit.
775 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor
776 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy
777 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy
778 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
779 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
780 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
781 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
782 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
783 system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses
784 system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses
785 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits
786 system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits
787 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits
788 system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits
789 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits
790 system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits
791 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses
792 system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses
793 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses
794 system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses
795 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses
796 system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses
797 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles
798 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles
799 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles
800 system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles
801 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles
802 system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles
803 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses)
804 system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses)
805 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses
806 system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses
807 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses
808 system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses
809 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses
810 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses
811 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses
812 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses
813 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses
814 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses
815 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency
816 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency
817 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
818 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency
819 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency
820 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency
821 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
822 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
823 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
824 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
825 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
826 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
827 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
828 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
829 system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks
830 system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks
831 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses
832 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses
833 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses
834 system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses
835 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses
836 system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses
837 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles
838 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles
839 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles
840 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles
841 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles
842 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles
843 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses
844 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses
845 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses
846 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses
847 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses
848 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses
849 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency
850 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency
851 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
852 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
853 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency
854 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency
855 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
856 system.cpu.icache.tags.replacements 996925 # number of replacements
857 system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use
858 system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks.
859 system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks.
860 system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks.
861 system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit.
862 system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor
863 system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy
864 system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy
865 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
866 system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
867 system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
868 system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id
869 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
870 system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses
871 system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses
872 system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits
873 system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits
874 system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits
875 system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits
876 system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits
877 system.cpu.icache.overall_hits::total 8050243 # number of overall hits
878 system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses
879 system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses
880 system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses
881 system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses
882 system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses
883 system.cpu.icache.overall_misses::total 1066046 # number of overall misses
884 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles
885 system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles
886 system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles
887 system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles
888 system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles
889 system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles
890 system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses)
891 system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses)
892 system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses
893 system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses
894 system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses
895 system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses
896 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses
897 system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses
898 system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses
899 system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses
900 system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses
901 system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses
902 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency
903 system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency
904 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
905 system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency
906 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency
907 system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency
908 system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked
909 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
910 system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
911 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
912 system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked
913 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
914 system.cpu.icache.fast_writes 0 # number of fast writes performed
915 system.cpu.icache.cache_copies 0 # number of cache copies performed
916 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits
917 system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits
918 system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits
919 system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits
920 system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits
921 system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits
922 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses
923 system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses
924 system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses
925 system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses
926 system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses
927 system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses
928 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles
929 system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles
930 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles
931 system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles
932 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles
933 system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles
934 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses
935 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses
936 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses
937 system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses
938 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses
939 system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses
940 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency
941 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency
942 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
943 system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
944 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency
945 system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency
946 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
947 system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements
948 system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use
949 system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks.
950 system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks.
951 system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks.
952 system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit.
953 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor
954 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy
955 system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy
956 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
957 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
958 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
959 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
960 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
961 system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses
962 system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses
963 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits
964 system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits
965 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
966 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
967 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits
968 system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits
969 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits
970 system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits
971 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses
972 system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses
973 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses
974 system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses
975 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses
976 system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses
977 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles
978 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles
979 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles
980 system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles
981 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles
982 system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles
983 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses)
984 system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses)
985 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
986 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
987 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses
988 system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses
989 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses
990 system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses
991 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses
992 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses
993 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses
994 system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses
995 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses
996 system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses
997 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency
998 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency
999 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
1000 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency
1001 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency
1002 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency
1003 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1004 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1005 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1006 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1007 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1008 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1009 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1010 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1011 system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks
1012 system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks
1013 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses
1014 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses
1015 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses
1016 system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses
1017 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses
1018 system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses
1019 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles
1020 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles
1021 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles
1022 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles
1023 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles
1024 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles
1025 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses
1026 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses
1027 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses
1028 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses
1029 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses
1030 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses
1031 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency
1032 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency
1033 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
1034 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
1035 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency
1036 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency
1037 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1038 system.cpu.l2cache.tags.replacements 112729 # number of replacements
1039 system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use
1040 system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks.
1041 system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks.
1042 system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks.
1043 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1044 system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor
1045 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor
1046 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor
1047 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor
1048 system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor
1049 system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy
1050 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy
1051 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy
1052 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy
1053 system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy
1054 system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy
1055 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
1056 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
1057 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id
1058 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id
1059 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id
1060 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id
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1128 system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses)
1129 system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses)
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1134 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses
1135 system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses
1136 system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses
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1140 system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses
1141 system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses
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1145 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses
1146 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses
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1148 system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses
1149 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses
1150 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses
1151 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses
1152 system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses
1153 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
1154 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses
1155 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses
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1158 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
1159 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses
1160 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses
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1164 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency
1165 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency
1166 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency
1167 system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency
1168 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency
1169 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency
1170 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency
1171 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency
1172 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
1173 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
1174 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
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1177 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency
1178 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency
1179 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency
1180 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency
1181 system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency
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1183 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1184 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1185 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1186 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1187 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1188 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1189 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1190 system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks
1191 system.cpu.l2cache.writebacks::total 102850 # number of writebacks
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1198 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
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1206 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses
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1222 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
1223 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
1224 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
1225 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
1226 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
1227 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
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1231 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles
1232 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles
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1234 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles
1235 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles
1236 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles
1237 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles
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1240 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles
1241 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles
1242 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles
1243 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles
1244 system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles
1245 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles
1246 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles
1247 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles
1248 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles
1249 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles
1250 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles
1251 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
1252 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses
1253 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses
1254 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses
1255 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses
1256 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses
1257 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses
1258 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses
1259 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses
1260 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
1261 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses
1262 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses
1263 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses
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1265 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
1266 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses
1267 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses
1268 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses
1269 system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses
1270 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency
1271 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency
1272 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency
1273 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency
1274 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency
1275 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency
1276 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency
1277 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency
1278 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency
1279 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
1280 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
1281 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
1282 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
1283 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
1284 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency
1285 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency
1286 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
1287 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
1288 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
1289 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency
1290 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency
1291 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency
1292 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency
1293 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency
1294 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency
1295 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1296 system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
1297 system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
1298 system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
1299 system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
1300 system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution
1301 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution
1302 system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
1303 system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
1304 system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
1305 system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution
1306 system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution
1307 system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
1308 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
1309 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
1310 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes)
1311 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes)
1312 system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes)
1313 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes)
1314 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes)
1315 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
1316 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
1317 system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)
1318 system.cpu.toL2Bus.snoops 63315 # Total snoops (count)
1319 system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram
1320 system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram
1321 system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram
1322 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1323 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1324 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1325 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1326 system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram
1327 system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram
1328 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1329 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1330 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1331 system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram
1332 system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
1333 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1334 system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
1335 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1336 system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks)
1337 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1338 system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks)
1339 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1340 system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks)
1341 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1342 system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks)
1343 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1344 system.iobus.trans_dist::ReadReq 223899 # Transaction distribution
1345 system.iobus.trans_dist::ReadResp 223899 # Transaction distribution
1346 system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
1347 system.iobus.trans_dist::WriteResp 11033 # Transaction distribution
1348 system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1349 system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
1350 system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
1351 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1352 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1353 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1354 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1355 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1356 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1357 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1358 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1359 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes)
1360 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1361 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1362 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1363 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1364 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1365 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1366 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1367 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1368 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1376 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1377 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1378 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1379 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1380 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1381 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1382 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1383 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes)
1384 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1385 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1386 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1387 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1388 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1389 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1390 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1391 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks)
1400 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1401 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1402 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1403 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1404 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1405 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1406 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1407 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1408 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1409 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1410 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1411 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1412 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1413 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1414 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1415 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1416 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1417 system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks)
1418 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1419 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1420 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1421 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1422 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1423 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1424 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1426 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1428 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1430 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1432 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1434 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks)
1436 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1438 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1439 system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks)
1440 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1441 system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks)
1442 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1443 system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
1444 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1445 system.iocache.tags.replacements 47572 # number of replacements
1446 system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use
1447 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1448 system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
1449 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1450 system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit.
1451 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor
1452 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy
1453 system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy
1454 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1455 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1456 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1457 system.iocache.tags.tag_accesses 428643 # Number of tag accesses
1458 system.iocache.tags.data_accesses 428643 # Number of data accesses
1459 system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
1460 system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
1461 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1462 system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1463 system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
1464 system.iocache.demand_misses::total 907 # number of demand (read+write) misses
1465 system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
1466 system.iocache.overall_misses::total 907 # number of overall misses
1467 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles
1468 system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles
1469 system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles
1470 system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles
1471 system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles
1472 system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles
1473 system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles
1474 system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles
1475 system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
1476 system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
1477 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1478 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1479 system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
1480 system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
1481 system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
1482 system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
1483 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1484 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1485 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1486 system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1487 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1488 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1489 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1490 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1491 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency
1492 system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency
1493 system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency
1494 system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency
1495 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
1496 system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency
1497 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency
1498 system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency
1499 system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked
1500 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1501 system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked
1502 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1503 system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked
1504 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1505 system.iocache.fast_writes 0 # number of fast writes performed
1506 system.iocache.cache_copies 0 # number of cache copies performed
1507 system.iocache.writebacks::writebacks 46667 # number of writebacks
1508 system.iocache.writebacks::total 46667 # number of writebacks
1509 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
1510 system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
1511 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1512 system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1513 system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
1514 system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
1515 system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
1516 system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
1517 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles
1518 system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles
1519 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles
1520 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles
1521 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles
1522 system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles
1523 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles
1524 system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles
1525 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1526 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1527 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1528 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1529 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1530 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1531 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1532 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1533 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency
1534 system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency
1535 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency
1536 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency
1537 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
1538 system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
1539 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency
1540 system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency
1541 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1542 system.membus.trans_dist::ReadReq 657725 # Transaction distribution
1543 system.membus.trans_dist::ReadResp 657721 # Transaction distribution
1544 system.membus.trans_dist::WriteReq 13919 # Transaction distribution
1545 system.membus.trans_dist::WriteResp 13919 # Transaction distribution
1546 system.membus.trans_dist::Writeback 149517 # Transaction distribution
1547 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1548 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1549 system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution
1550 system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution
1551 system.membus.trans_dist::ReadExReq 133760 # Transaction distribution
1552 system.membus.trans_dist::ReadExResp 133758 # Transaction distribution
1553 system.membus.trans_dist::MessageReq 1643 # Transaction distribution
1554 system.membus.trans_dist::MessageResp 1643 # Transaction distribution
1555 system.membus.trans_dist::BadAddressError 4 # Transaction distribution
1556 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
1557 system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
1558 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes)
1559 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes)
1560 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes)
1561 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes)
1562 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes)
1563 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes)
1564 system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes)
1565 system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes)
1566 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
1567 system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1568 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes)
1569 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes)
1570 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes)
1571 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes)
1572 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1573 system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1574 system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
1575 system.membus.snoops 1635 # Total snoops (count)
1576 system.membus.snoop_fanout::samples 1005577 # Request fanout histogram
1577 system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram
1578 system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram
1579 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1580 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1581 system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram
1582 system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram
1583 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1584 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1585 system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1586 system.membus.snoop_fanout::total 1005577 # Request fanout histogram
1587 system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks)
1588 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1589 system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks)
1590 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1591 system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
1592 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1593 system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks)
1594 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1595 system.membus.reqLayer4.occupancy 5000 # Layer occupancy (ticks)
1596 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1597 system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
1598 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1599 system.membus.respLayer2.occupancy 2211768878 # Layer occupancy (ticks)
1600 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1601 system.membus.respLayer4.occupancy 51465743 # Layer occupancy (ticks)
1602 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1603 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1604 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1605 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1606 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1607 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1608 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1609 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1610 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1611 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1612 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1613 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1614 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1615 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1616 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1618 ---------- End Simulation Statistics ----------
projects / gem5.git / blob