2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.125902 # Number of seconds simulated
4 sim_ticks 5125902116500 # Number of ticks simulated
5 final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 196886 # Simulator instruction rate (inst/s)
8 host_op_rate 389187 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2473535129 # Simulator tick rate (ticks/s)
10 host_mem_usage 743248 # Number of bytes of host memory used
11 host_seconds 2072.30 # Real time elapsed on the host
12 sim_insts 408006726 # Number of instructions simulated
13 sim_ops 806511598 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory
25 system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
26 system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
27 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory
32 system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory
33 system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory
34 system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
35 system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
36 system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)
41 system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s)
42 system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s)
43 system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s)
44 system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s)
45 system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s)
46 system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s)
47 system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
52 system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)
53 system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s)
54 system.physmem.readReqs 185800 # Number of read requests accepted
55 system.physmem.writeReqs 149916 # Number of write requests accepted
56 system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue
57 system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue
58 system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM
59 system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue
60 system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM
61 system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side
62 system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side
63 system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue
64 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
65 system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write
66 system.physmem.perBankRdBursts::0 11489 # Per bank write bursts
67 system.physmem.perBankRdBursts::1 10946 # Per bank write bursts
68 system.physmem.perBankRdBursts::2 11982 # Per bank write bursts
69 system.physmem.perBankRdBursts::3 11463 # Per bank write bursts
70 system.physmem.perBankRdBursts::4 11671 # Per bank write bursts
71 system.physmem.perBankRdBursts::5 11298 # Per bank write bursts
72 system.physmem.perBankRdBursts::6 11252 # Per bank write bursts
73 system.physmem.perBankRdBursts::7 11687 # Per bank write bursts
74 system.physmem.perBankRdBursts::8 11071 # Per bank write bursts
75 system.physmem.perBankRdBursts::9 11217 # Per bank write bursts
76 system.physmem.perBankRdBursts::10 11355 # Per bank write bursts
77 system.physmem.perBankRdBursts::11 12125 # Per bank write bursts
78 system.physmem.perBankRdBursts::12 11861 # Per bank write bursts
79 system.physmem.perBankRdBursts::13 12651 # Per bank write bursts
80 system.physmem.perBankRdBursts::14 12184 # Per bank write bursts
81 system.physmem.perBankRdBursts::15 11314 # Per bank write bursts
82 system.physmem.perBankWrBursts::0 9710 # Per bank write bursts
83 system.physmem.perBankWrBursts::1 9082 # Per bank write bursts
84 system.physmem.perBankWrBursts::2 8978 # Per bank write bursts
85 system.physmem.perBankWrBursts::3 8996 # Per bank write bursts
86 system.physmem.perBankWrBursts::4 9462 # Per bank write bursts
87 system.physmem.perBankWrBursts::5 9601 # Per bank write bursts
88 system.physmem.perBankWrBursts::6 9097 # Per bank write bursts
89 system.physmem.perBankWrBursts::7 8837 # Per bank write bursts
90 system.physmem.perBankWrBursts::8 9327 # Per bank write bursts
91 system.physmem.perBankWrBursts::9 9159 # Per bank write bursts
92 system.physmem.perBankWrBursts::10 9532 # Per bank write bursts
93 system.physmem.perBankWrBursts::11 9463 # Per bank write bursts
94 system.physmem.perBankWrBursts::12 9618 # Per bank write bursts
95 system.physmem.perBankWrBursts::13 9862 # Per bank write bursts
96 system.physmem.perBankWrBursts::14 9881 # Per bank write bursts
97 system.physmem.perBankWrBursts::15 9285 # Per bank write bursts
98 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99 system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
100 system.physmem.totGap 5125902065000 # Total gap between requests
101 system.physmem.readPktSize::0 0 # Read request sizes (log2)
102 system.physmem.readPktSize::1 0 # Read request sizes (log2)
103 system.physmem.readPktSize::2 0 # Read request sizes (log2)
104 system.physmem.readPktSize::3 0 # Read request sizes (log2)
105 system.physmem.readPktSize::4 0 # Read request sizes (log2)
106 system.physmem.readPktSize::5 0 # Read request sizes (log2)
107 system.physmem.readPktSize::6 185800 # Read request sizes (log2)
108 system.physmem.writePktSize::0 0 # Write request sizes (log2)
109 system.physmem.writePktSize::1 0 # Write request sizes (log2)
110 system.physmem.writePktSize::2 0 # Write request sizes (log2)
111 system.physmem.writePktSize::3 0 # Write request sizes (log2)
112 system.physmem.writePktSize::4 0 # Write request sizes (log2)
113 system.physmem.writePktSize::5 0 # Write request sizes (log2)
114 system.physmem.writePktSize::6 149916 # Write request sizes (log2)
115 system.physmem.rdQLenPdf::0 170703 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::1 12067 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::2 2038 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::3 421 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::15 2237 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::16 2934 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::17 7172 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::18 7637 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::19 7787 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::20 8527 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::21 8842 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::22 9565 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::23 10246 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::24 11384 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::25 10610 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::26 9929 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::27 9208 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::28 9073 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::29 7958 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::30 7723 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::31 7760 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::32 7617 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::33 249 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::37 222 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
211 system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation
225 system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes
228 system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes
229 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
230 system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes
231 system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads
265 system.physmem.totQLat 2068154250 # Total ticks spent queuing
266 system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM
267 system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers
268 system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst
269 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
270 system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst
271 system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
272 system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
273 system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
274 system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
275 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
276 system.physmem.busUtil 0.03 # Data bus utilization in percentage
277 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
278 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
279 system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
280 system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing
281 system.physmem.readRowHits 151753 # Number of row buffer hits during reads
282 system.physmem.writeRowHits 110856 # Number of row buffer hits during writes
283 system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
284 system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes
285 system.physmem.avgGap 15268566.48 # Average gap between requests
286 system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined
287 system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states
288 system.physmem.memoryStateTime::REF 171165020000 # Time in different power states
289 system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
290 system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states
291 system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
292 system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ)
293 system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ)
294 system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ)
295 system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ)
296 system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ)
297 system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ)
298 system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ)
299 system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ)
300 system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ)
301 system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ)
302 system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ)
303 system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ)
304 system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ)
305 system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ)
306 system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ)
307 system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ)
308 system.physmem.averagePower::0 668.726542 # Core power per rank (mW)
309 system.physmem.averagePower::1 668.742609 # Core power per rank (mW)
310 system.membus.trans_dist::ReadReq 662592 # Transaction distribution
311 system.membus.trans_dist::ReadResp 662582 # Transaction distribution
312 system.membus.trans_dist::WriteReq 13889 # Transaction distribution
313 system.membus.trans_dist::WriteResp 13889 # Transaction distribution
314 system.membus.trans_dist::Writeback 103196 # Transaction distribution
315 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
316 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
317 system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
318 system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
319 system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
320 system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
321 system.membus.trans_dist::MessageReq 1644 # Transaction distribution
322 system.membus.trans_dist::MessageResp 1644 # Transaction distribution
323 system.membus.trans_dist::BadAddressError 10 # Transaction distribution
324 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
325 system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
326 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
327 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
328 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
329 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
330 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
331 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
332 system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
333 system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
334 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
335 system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
336 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
337 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
338 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
339 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
340 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
341 system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
342 system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
343 system.membus.snoops 949 # Total snoops (count)
344 system.membus.snoop_fanout::samples 338415 # Request fanout histogram
345 system.membus.snoop_fanout::mean 1 # Request fanout histogram
346 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
347 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
348 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
349 system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
350 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
351 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
352 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
353 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
354 system.membus.snoop_fanout::total 338415 # Request fanout histogram
355 system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
356 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
357 system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
358 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
359 system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
360 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
361 system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
362 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
363 system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
364 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
365 system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
366 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
367 system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
368 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
369 system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
370 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
371 system.iocache.tags.replacements 47575 # number of replacements
372 system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
373 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
374 system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
375 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
376 system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
377 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
378 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
379 system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
380 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
381 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
382 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
383 system.iocache.tags.tag_accesses 428670 # Number of tag accesses
384 system.iocache.tags.data_accesses 428670 # Number of data accesses
385 system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
386 system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
387 system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
388 system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
389 system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
390 system.iocache.demand_misses::total 910 # number of demand (read+write) misses
391 system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
392 system.iocache.overall_misses::total 910 # number of overall misses
393 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
394 system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
395 system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
396 system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
397 system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
398 system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
399 system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
400 system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
401 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
402 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
403 system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
404 system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
405 system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
406 system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
407 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
408 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
409 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
410 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
411 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
412 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
413 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
414 system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
415 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
416 system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
417 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
418 system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
419 system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
420 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
421 system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
422 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
423 system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
424 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
425 system.iocache.fast_writes 46720 # number of fast writes performed
426 system.iocache.cache_copies 0 # number of cache copies performed
427 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
428 system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
429 system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
430 system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
431 system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
432 system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
433 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
434 system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
435 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
436 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
437 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
438 system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
439 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
440 system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
441 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
442 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
443 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
444 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
445 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
446 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
447 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
448 system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
449 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
450 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
451 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
452 system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
453 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
454 system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
455 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
456 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
457 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
458 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
459 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
460 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
461 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
462 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
463 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
464 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
465 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
466 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
467 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
468 system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
469 system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
470 system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
471 system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
472 system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
473 system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
474 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
475 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
476 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
477 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
478 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
479 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
480 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
481 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
482 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
483 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
484 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
485 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
486 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
487 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
488 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
489 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
490 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
491 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
492 system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
493 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
494 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
495 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
496 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
497 system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
498 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
499 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
500 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
501 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
502 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
503 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
504 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
505 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
506 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
507 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
508 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
509 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
510 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
511 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
512 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
513 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
514 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
515 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
516 system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
517 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
518 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
519 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
520 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
521 system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
522 system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
523 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
524 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
525 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
526 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
527 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
528 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
529 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
530 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
531 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
532 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
533 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
534 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
535 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
536 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
537 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
538 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
539 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
540 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
541 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
542 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
543 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
544 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
545 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
546 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
547 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
548 system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
549 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
550 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
551 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
552 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
553 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
554 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
555 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
556 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
557 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
558 system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
559 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
560 system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
561 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
562 system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
563 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
564 system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
565 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
566 system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
567 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
568 system.cpu_clk_domain.clock 500 # Clock period in ticks
569 system.cpu.branchPred.lookups 86911006 # Number of BP lookups
570 system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
571 system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
572 system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups
573 system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits
574 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
575 system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
576 system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
577 system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.
578 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
579 system.cpu.numCycles 449563158 # number of cpu cycles simulated
580 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
581 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
582 system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss
583 system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed
584 system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered
585 system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken
586 system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked
587 system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing
588 system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb
589 system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
590 system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps
591 system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions
592 system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR
593 system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched
594 system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed
595 system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed
596 system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total)
597 system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total)
598 system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total)
599 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
600 system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total)
601 system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total)
602 system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total)
603 system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total)
604 system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total)
605 system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total)
606 system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total)
607 system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total)
608 system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total)
609 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
610 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
611 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
612 system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total)
613 system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle
614 system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle
615 system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle
616 system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked
617 system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running
618 system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking
619 system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing
620 system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode
621 system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing
622 system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle
623 system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking
624 system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst
625 system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running
626 system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking
627 system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename
628 system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full
629 system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full
630 system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full
631 system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full
632 system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed
633 system.cpu.rename.RenameLookups 1813799496 # Number of register rename lookups that rename has made
634 system.cpu.rename.int_rename_lookups 1115056771 # Number of integer rename lookups
635 system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups
636 system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed
637 system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing
638 system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed
639 system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed
640 system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer
641 system.cpu.memDep0.insertedLoads 17327061 # Number of loads inserted to the mem dependence unit.
642 system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit.
643 system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads.
644 system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores.
645 system.cpu.iq.iqInstsAdded 829577981 # Number of instructions added to the IQ (excludes non-spec)
646 system.cpu.iq.iqNonSpecInstsAdded 1211612 # Number of non-speculative instructions added to the IQ
647 system.cpu.iq.iqInstsIssued 824337261 # Number of instructions issued
648 system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued
649 system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling
650 system.cpu.iq.iqSquashedOperandsExamined 36066463 # Number of squashed operands that are examined and possibly removed from graph
651 system.cpu.iq.iqSquashedNonSpecRemoved 155823 # Number of squashed non-spec instructions that were removed
652 system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle
653 system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle
654 system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle
655 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
656 system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle
657 system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle
658 system.cpu.iq.issued_per_cycle::2 10080748 2.26% 64.14% # Number of insts issued each cycle
659 system.cpu.iq.issued_per_cycle::3 6920312 1.55% 65.68% # Number of insts issued each cycle
660 system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle
661 system.cpu.iq.issued_per_cycle::5 4460813 1.00% 83.32% # Number of insts issued each cycle
662 system.cpu.iq.issued_per_cycle::6 72820654 16.29% 99.61% # Number of insts issued each cycle
663 system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle
664 system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle
665 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
666 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
667 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
668 system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle
669 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
670 system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available
671 system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available
672 system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available
673 system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available
674 system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available
675 system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available
676 system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available
677 system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available
678 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
679 system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available
680 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available
681 system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available
682 system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available
683 system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available
684 system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available
685 system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available
686 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available
687 system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available
688 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available
689 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available
690 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available
691 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available
692 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available
693 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available
694 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available
695 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available
696 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available
697 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available
698 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
699 system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available
700 system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available
701 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
702 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
703 system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued
704 system.cpu.iq.FU_type_0::IntAlu 795957786 96.56% 96.59% # Type of FU issued
705 system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued
706 system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued
707 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
708 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
709 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
710 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
711 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
712 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
713 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
714 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
715 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
716 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
717 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
718 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
719 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
720 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
721 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
722 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
723 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
724 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
725 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
726 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
727 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
728 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
729 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
730 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
731 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
732 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
733 system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued
734 system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued
735 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
736 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
737 system.cpu.iq.FU_type_0::total 824337261 # Type of FU issued
738 system.cpu.iq.rate 1.833641 # Inst issue rate
739 system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested
740 system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst)
741 system.cpu.iq.int_inst_queue_reads 2098683900 # Number of integer instruction queue reads
742 system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes
743 system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses
744 system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
745 system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes
746 system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
747 system.cpu.iq.int_alu_accesses 826797417 # Number of integer alu accesses
748 system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
749 system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores
750 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
751 system.cpu.iew.lsq.thread0.squashedLoads 3325389 # Number of loads squashed
752 system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed
753 system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations
754 system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed
755 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
756 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
757 system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled
758 system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked
759 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
760 system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing
761 system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking
762 system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking
763 system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ
764 system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch
765 system.cpu.iew.iewDispLoadInsts 17327061 # Number of dispatched load instructions
766 system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions
767 system.cpu.iew.iewDispNonSpecInsts 714336 # Number of dispatched non-speculative instructions
768 system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall
769 system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
770 system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
771 system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly
772 system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly
773 system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute
774 system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
775 system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
776 system.cpu.iew.iewExecSquashedInsts 1477345 # Number of squashed instructions skipped in execute
777 system.cpu.iew.exec_swp 0 # number of swp insts executed
778 system.cpu.iew.exec_nop 0 # number of nop insts executed
779 system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed
780 system.cpu.iew.exec_branches 83308581 # Number of branches executed
781 system.cpu.iew.exec_stores 9169768 # Number of stores executed
782 system.cpu.iew.exec_rate 1.830056 # Inst execution rate
783 system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit
784 system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back
785 system.cpu.iew.wb_producers 641108962 # num instructions producing a value
786 system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value
787 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
788 system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle
789 system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back
790 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
791 system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit
792 system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards
793 system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted
794 system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle
795 system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle
796 system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle
797 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
798 system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle
799 system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle
800 system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle
801 system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle
802 system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle
803 system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle
804 system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle
805 system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle
806 system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle
807 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
808 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
809 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
810 system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle
811 system.cpu.commit.committedInsts 408006726 # Number of instructions committed
812 system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed
813 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
814 system.cpu.commit.refs 22429273 # Number of memory references committed
815 system.cpu.commit.loads 14001671 # Number of loads committed
816 system.cpu.commit.membars 475333 # Number of memory barriers committed
817 system.cpu.commit.branches 82207365 # Number of branches committed
818 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
819 system.cpu.commit.int_insts 735317995 # Number of committed integer instructions.
820 system.cpu.commit.function_calls 1155841 # Number of function calls committed.
821 system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction
822 system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction
823 system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction
824 system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction
825 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
826 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
827 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
828 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
829 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
830 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
831 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
832 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
833 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
834 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
835 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
836 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
837 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
838 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
839 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
840 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
841 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
842 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
843 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
844 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
845 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
846 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
847 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
848 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
849 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
850 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
851 system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction
852 system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction
853 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
854 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
855 system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction
856 system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached
857 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
858 system.cpu.rob.rob_reads 1268507964 # The number of ROB reads
859 system.cpu.rob.rob_writes 1665044622 # The number of ROB writes
860 system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself
861 system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling
862 system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
863 system.cpu.committedInsts 408006726 # Number of Instructions Simulated
864 system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated
865 system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction
866 system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads
867 system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle
868 system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads
869 system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads
870 system.cpu.int_regfile_writes 656162059 # number of integer regfile writes
871 system.cpu.fp_regfile_reads 61 # number of floating regfile reads
872 system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads
873 system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
874 system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
875 system.cpu.misc_regfile_writes 402647 # number of misc regfile writes
876 system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
877 system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
878 system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
879 system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
880 system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
881 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
882 system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
883 system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
884 system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
885 system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
886 system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
887 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
888 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
889 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
890 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
891 system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
892 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
893 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
894 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
895 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
896 system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
897 system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
898 system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
899 system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
900 system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
901 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
902 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
903 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
904 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
905 system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
906 system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
907 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
908 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
909 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
910 system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
911 system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
912 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
913 system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
914 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
915 system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
916 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
917 system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
918 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
919 system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
920 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
921 system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
922 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
923 system.cpu.icache.tags.replacements 994393 # number of replacements
924 system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use
925 system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks.
926 system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks.
927 system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks.
928 system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
929 system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor
930 system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy
931 system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy
932 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
933 system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
934 system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
935 system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id
936 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
937 system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses
938 system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses
939 system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits
940 system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits
941 system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits
942 system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits
943 system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits
944 system.cpu.icache.overall_hits::total 8125717 # number of overall hits
945 system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses
946 system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses
947 system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses
948 system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses
949 system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses
950 system.cpu.icache.overall_misses::total 1058185 # number of overall misses
951 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles
952 system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles
953 system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles
954 system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles
955 system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles
956 system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles
957 system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses)
958 system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses)
959 system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses
960 system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses
961 system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses
962 system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses
963 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses
964 system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses
965 system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses
966 system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses
967 system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses
968 system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses
969 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency
970 system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency
971 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
972 system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency
973 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
974 system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency
975 system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked
976 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
977 system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
978 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
979 system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked
980 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
981 system.cpu.icache.fast_writes 0 # number of fast writes performed
982 system.cpu.icache.cache_copies 0 # number of cache copies performed
983 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits
984 system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits
985 system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits
986 system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits
987 system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits
988 system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits
989 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses
990 system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses
991 system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses
992 system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses
993 system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses
994 system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses
995 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles
996 system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles
997 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles
998 system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles
999 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles
1000 system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles
1001 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses
1002 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses
1003 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses
1004 system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses
1005 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses
1006 system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses
1007 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency
1008 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency
1009 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
1010 system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
1011 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
1012 system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
1013 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1014 system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements
1015 system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use
1016 system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks.
1017 system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks.
1018 system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks.
1019 system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit.
1020 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor
1021 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy
1022 system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy
1023 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
1024 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1025 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
1026 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
1027 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
1028 system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses
1029 system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses
1030 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits
1031 system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits
1032 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1033 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1034 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits
1035 system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits
1036 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits
1037 system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits
1038 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses
1039 system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses
1040 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses
1041 system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses
1042 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses
1043 system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses
1044 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles
1045 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles
1046 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles
1047 system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles
1048 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles
1049 system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles
1050 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses)
1051 system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses)
1052 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1053 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1054 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses
1055 system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses
1056 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses
1057 system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses
1058 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses
1059 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses
1060 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses
1061 system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses
1062 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses
1063 system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses
1064 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency
1065 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency
1066 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
1067 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency
1068 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
1069 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency
1070 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1071 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1072 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1073 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1074 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1075 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1076 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1077 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1078 system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks
1079 system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks
1080 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses
1081 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses
1082 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses
1083 system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses
1084 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses
1085 system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses
1086 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles
1087 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles
1088 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles
1089 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles
1090 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles
1091 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles
1092 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses
1093 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses
1094 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses
1095 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses
1096 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses
1097 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses
1098 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency
1099 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency
1100 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
1101 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
1102 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
1103 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
1104 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1105 system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements
1106 system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use
1107 system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks.
1108 system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks.
1109 system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks.
1110 system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
1111 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor
1112 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy
1113 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy
1114 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
1115 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
1116 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
1117 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
1118 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
1119 system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses
1120 system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses
1121 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits
1122 system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits
1123 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits
1124 system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits
1125 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits
1126 system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits
1127 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses
1128 system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses
1129 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses
1130 system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses
1131 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses
1132 system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses
1133 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles
1134 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles
1135 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles
1136 system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles
1137 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles
1138 system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles
1139 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses)
1140 system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses)
1141 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses
1142 system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses
1143 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses
1144 system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses
1145 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses
1146 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses
1147 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses
1148 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses
1149 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses
1150 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses
1151 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency
1152 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency
1153 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
1154 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency
1155 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
1156 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency
1157 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1158 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1159 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1160 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1161 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1162 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1163 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1164 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1165 system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks
1166 system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks
1167 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses
1168 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses
1169 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses
1170 system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses
1171 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses
1172 system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses
1173 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles
1174 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles
1175 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles
1176 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles
1177 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles
1178 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles
1179 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses
1180 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses
1181 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses
1182 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses
1183 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses
1184 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses
1185 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency
1186 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency
1187 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
1188 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
1189 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
1190 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
1191 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1192 system.cpu.dcache.tags.replacements 1657683 # number of replacements
1193 system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use
1194 system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks.
1195 system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks.
1196 system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks.
1197 system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
1198 system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor
1199 system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
1200 system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
1201 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1202 system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
1203 system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
1204 system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
1205 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1206 system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses
1207 system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses
1208 system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits
1209 system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits
1210 system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits
1211 system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits
1212 system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits
1213 system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits
1214 system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits
1215 system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits
1216 system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits
1217 system.cpu.dcache.overall_hits::total 19128334 # number of overall hits
1218 system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses
1219 system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses
1220 system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses
1221 system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses
1222 system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses
1223 system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses
1224 system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses
1225 system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses
1226 system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses
1227 system.cpu.dcache.overall_misses::total 2535648 # number of overall misses
1228 system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles
1229 system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles
1230 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles
1231 system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles
1232 system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles
1233 system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles
1234 system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles
1235 system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles
1236 system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses)
1237 system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses)
1238 system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses)
1239 system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses)
1240 system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses)
1241 system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses)
1242 system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses
1243 system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses
1244 system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses
1245 system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses
1246 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses
1247 system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses
1248 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses
1249 system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses
1250 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses
1251 system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses
1252 system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses
1253 system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses
1254 system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses
1255 system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses
1256 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency
1257 system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency
1258 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency
1259 system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency
1260 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency
1261 system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency
1262 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency
1263 system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency
1264 system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked
1265 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1266 system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked
1267 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1268 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked
1269 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1270 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1271 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1272 system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks
1273 system.cpu.dcache.writebacks::total 1559289 # number of writebacks
1274 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits
1275 system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits
1276 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits
1277 system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits
1278 system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits
1279 system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits
1280 system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits
1281 system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits
1282 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses
1283 system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses
1284 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses
1285 system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses
1286 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses
1287 system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses
1288 system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses
1289 system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses
1290 system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses
1291 system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses
1292 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles
1293 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles
1294 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles
1295 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles
1296 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles
1297 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles
1298 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles
1299 system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles
1300 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles
1301 system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles
1302 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles
1303 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles
1304 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles
1305 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles
1306 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles
1307 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles
1308 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses
1309 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses
1310 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses
1311 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses
1312 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses
1313 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses
1314 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses
1315 system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses
1316 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses
1317 system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses
1318 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency
1319 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency
1320 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency
1321 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency
1322 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency
1323 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency
1324 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency
1325 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency
1326 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency
1327 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency
1328 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1329 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1330 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1331 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1332 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1333 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1334 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1335 system.cpu.l2cache.tags.replacements 113085 # number of replacements
1336 system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use
1337 system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks.
1338 system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks.
1339 system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks.
1340 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1341 system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor
1342 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor
1343 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor
1344 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor
1345 system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor
1346 system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy
1347 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy
1348 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1349 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy
1350 system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy
1351 system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy
1352 system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id
1353 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
1354 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id
1355 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id
1356 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id
1357 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id
1358 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id
1359 system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses
1360 system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses
1361 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits
1362 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits
1363 system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits
1364 system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits
1365 system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits
1366 system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits
1367 system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits
1368 system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
1369 system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
1370 system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits
1371 system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits
1372 system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits
1373 system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits
1374 system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits
1375 system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits
1376 system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits
1377 system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits
1378 system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits
1379 system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits
1380 system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits
1381 system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits
1382 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses
1383 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
1384 system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses
1385 system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
1386 system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses
1387 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
1388 system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
1389 system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses
1390 system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses
1391 system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses
1392 system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
1393 system.cpu.l2cache.demand_misses::cpu.inst 16312 # number of demand (read+write) misses
1394 system.cpu.l2cache.demand_misses::cpu.data 169268 # number of demand (read+write) misses
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1396 system.cpu.l2cache.overall_misses::cpu.dtb.walker 75 # number of overall misses
1397 system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
1398 system.cpu.l2cache.overall_misses::cpu.inst 16312 # number of overall misses
1399 system.cpu.l2cache.overall_misses::cpu.data 169268 # number of overall misses
1400 system.cpu.l2cache.overall_misses::total 185662 # number of overall misses
1401 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6508500 # number of ReadReq miss cycles
1402 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 560500 # number of ReadReq miss cycles
1403 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1253827000 # number of ReadReq miss cycles
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1405 system.cpu.l2cache.ReadReq_miss_latency::total 4145309497 # number of ReadReq miss cycles
1406 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16150808 # number of UpgradeReq miss cycles
1407 system.cpu.l2cache.UpgradeReq_miss_latency::total 16150808 # number of UpgradeReq miss cycles
1408 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313802457 # number of ReadExReq miss cycles
1409 system.cpu.l2cache.ReadExReq_miss_latency::total 9313802457 # number of ReadExReq miss cycles
1410 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6508500 # number of demand (read+write) miss cycles
1411 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 560500 # number of demand (read+write) miss cycles
1412 system.cpu.l2cache.demand_miss_latency::cpu.inst 1253827000 # number of demand (read+write) miss cycles
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1415 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6508500 # number of overall miss cycles
1416 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 560500 # number of overall miss cycles
1417 system.cpu.l2cache.overall_miss_latency::cpu.inst 1253827000 # number of overall miss cycles
1418 system.cpu.l2cache.overall_miss_latency::cpu.data 12198215954 # number of overall miss cycles
1419 system.cpu.l2cache.overall_miss_latency::total 13459111954 # number of overall miss cycles
1420 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68607 # number of ReadReq accesses(hits+misses)
1421 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12508 # number of ReadReq accesses(hits+misses)
1422 system.cpu.l2cache.ReadReq_accesses::cpu.inst 994860 # number of ReadReq accesses(hits+misses)
1423 system.cpu.l2cache.ReadReq_accesses::cpu.data 1370499 # number of ReadReq accesses(hits+misses)
1424 system.cpu.l2cache.ReadReq_accesses::total 2446474 # number of ReadReq accesses(hits+misses)
1425 system.cpu.l2cache.Writeback_accesses::writebacks 1584468 # number of Writeback accesses(hits+misses)
1426 system.cpu.l2cache.Writeback_accesses::total 1584468 # number of Writeback accesses(hits+misses)
1427 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1753 # number of UpgradeReq accesses(hits+misses)
1428 system.cpu.l2cache.UpgradeReq_accesses::total 1753 # number of UpgradeReq accesses(hits+misses)
1429 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287062 # number of ReadExReq accesses(hits+misses)
1430 system.cpu.l2cache.ReadExReq_accesses::total 287062 # number of ReadExReq accesses(hits+misses)
1431 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68607 # number of demand (read+write) accesses
1432 system.cpu.l2cache.demand_accesses::cpu.itb.walker 12508 # number of demand (read+write) accesses
1433 system.cpu.l2cache.demand_accesses::cpu.inst 994860 # number of demand (read+write) accesses
1434 system.cpu.l2cache.demand_accesses::cpu.data 1657561 # number of demand (read+write) accesses
1435 system.cpu.l2cache.demand_accesses::total 2733536 # number of demand (read+write) accesses
1436 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68607 # number of overall (read+write) accesses
1437 system.cpu.l2cache.overall_accesses::cpu.itb.walker 12508 # number of overall (read+write) accesses
1438 system.cpu.l2cache.overall_accesses::cpu.inst 994860 # number of overall (read+write) accesses
1439 system.cpu.l2cache.overall_accesses::cpu.data 1657561 # number of overall (read+write) accesses
1440 system.cpu.l2cache.overall_accesses::total 2733536 # number of overall (read+write) accesses
1441 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001093 # miss rate for ReadReq accesses
1442 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000560 # miss rate for ReadReq accesses
1443 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016396 # miss rate for ReadReq accesses
1444 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026177 # miss rate for ReadReq accesses
1445 system.cpu.l2cache.ReadReq_miss_rate::total 0.021365 # miss rate for ReadReq accesses
1446 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823731 # miss rate for UpgradeReq accesses
1447 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823731 # miss rate for UpgradeReq accesses
1448 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464684 # miss rate for ReadExReq accesses
1449 system.cpu.l2cache.ReadExReq_miss_rate::total 0.464684 # miss rate for ReadExReq accesses
1450 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001093 # miss rate for demand accesses
1451 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000560 # miss rate for demand accesses
1452 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016396 # miss rate for demand accesses
1453 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102119 # miss rate for demand accesses
1454 system.cpu.l2cache.demand_miss_rate::total 0.067920 # miss rate for demand accesses
1455 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001093 # miss rate for overall accesses
1456 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000560 # miss rate for overall accesses
1457 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016396 # miss rate for overall accesses
1458 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102119 # miss rate for overall accesses
1459 system.cpu.l2cache.overall_miss_rate::total 0.067920 # miss rate for overall accesses
1460 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86780 # average ReadReq miss latency
1461 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency
1462 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency
1463 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951 # average ReadReq miss latency
1464 system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936 # average ReadReq miss latency
1465 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083 # average UpgradeReq miss latency
1466 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency
1467 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency
1468 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency
1469 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
1470 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
1471 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
1472 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
1473 system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732 # average overall miss latency
1474 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
1475 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
1476 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
1477 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
1478 system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency
1479 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1480 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1481 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1482 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1483 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1484 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1485 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1486 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1487 system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks
1488 system.cpu.l2cache.writebacks::total 103196 # number of writebacks
1489 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1490 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1491 system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1492 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1493 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1494 system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1495 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1496 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1497 system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1498 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses
1499 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1500 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses
1501 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses
1502 system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses
1503 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
1504 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
1505 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses
1506 system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses
1507 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses
1508 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1509 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses
1510 system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses
1511 system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses
1512 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses
1513 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1514 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses
1515 system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses
1516 system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses
1517 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles
1518 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles
1519 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles
1520 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles
1521 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles
1522 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles
1523 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles
1524 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles
1525 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles
1526 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles
1527 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles
1528 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles
1529 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles
1530 system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles
1531 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles
1532 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles
1533 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles
1534 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles
1535 system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles
1536 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles
1537 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles
1538 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles
1539 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles
1540 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles
1541 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles
1542 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses
1543 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses
1544 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses
1545 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses
1546 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses
1547 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses
1548 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses
1549 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses
1550 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses
1551 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses
1552 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses
1553 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses
1554 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses
1555 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses
1556 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses
1557 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses
1558 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses
1559 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses
1560 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses
1561 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency
1562 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency
1563 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency
1564 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency
1565 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency
1566 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency
1567 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency
1568 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency
1569 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency
1570 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
1571 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
1572 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
1573 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
1574 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
1575 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
1576 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
1577 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
1578 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
1579 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
1580 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1581 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1582 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1583 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1584 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1585 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1586 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1587 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1588 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1590 ---------- End Simulation Statistics ----------
projects / gem5.git / blob