2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.154240 # Number of seconds simulated
4 sim_ticks 5154239928000 # Number of ticks simulated
5 final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 177928 # Simulator instruction rate (inst/s)
8 host_op_rate 351699 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2247974259 # Simulator tick rate (ticks/s)
10 host_mem_usage 809460 # Number of bytes of host memory used
11 host_seconds 2292.84 # Real time elapsed on the host
12 sim_insts 407959851 # Number of instructions simulated
13 sim_ops 806389826 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185029 # Number of read requests accepted
52 system.physmem.writeReqs 196407 # Number of write requests accepted
53 system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11576 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 11057 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 12153 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11198 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11802 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11348 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 11143 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11153 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11425 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11213 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11332 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11504 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 11762 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12902 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11974 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11385 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 11439 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 10429 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 10485 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 9453 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 11713 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 11103 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 10277 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 10587 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 10639 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 10347 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 10880 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 10311 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 10712 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 11096 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 11110 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9917 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 48 # Number of times write queue was full causing retry
97 system.physmem.totGap 5154239876000 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185029 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 196407 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 170541 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11600 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 1966 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 1926 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 6237 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 6870 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 7193 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 7339 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 7830 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 8415 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 7894 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 8094 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 9954 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 8496 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 7725 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 10840 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8567 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 8107 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 7987 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 1631 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 1321 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 1459 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 2521 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 2967 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 2476 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 2901 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 3411 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 2551 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 2324 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 2194 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 2613 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 2036 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 1490 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 1243 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 899 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 438 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 382 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 298 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 222 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 192 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 102 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 73580 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 27722 37.68% 37.68% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17426 23.68% 61.36% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7585 10.31% 71.67% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4195 5.70% 77.37% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1416 1.92% 86.12% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1303 1.77% 87.89% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 6767 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 6767 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 6767 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 25.195508 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.700984 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 42.210035 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-31 6335 93.62% 93.62% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::32-47 84 1.24% 94.86% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::48-63 17 0.25% 95.11% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::64-79 17 0.25% 95.36% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::80-95 19 0.28% 95.64% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::96-111 20 0.30% 95.94% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::112-127 33 0.49% 96.42% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::128-143 32 0.47% 96.90% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::144-159 26 0.38% 97.28% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::160-175 8 0.12% 97.40% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::176-191 61 0.90% 98.30% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::192-207 50 0.74% 99.04% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::208-223 12 0.18% 99.22% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::224-239 1 0.01% 99.23% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::272-287 3 0.04% 99.31% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::304-319 2 0.03% 99.36% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::320-335 4 0.06% 99.42% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::336-351 9 0.13% 99.56% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::352-367 14 0.21% 99.76% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::368-383 6 0.09% 99.85% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::384-399 1 0.01% 99.87% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::400-415 1 0.01% 99.88% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads
261 system.physmem.totQLat 2002245948 # Total ticks spent queuing
262 system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM
263 system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers
264 system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst
265 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
266 system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst
267 system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s
268 system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s
269 system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s
270 system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s
271 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
272 system.physmem.busUtil 0.03 # Data bus utilization in percentage
273 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
274 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
275 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
276 system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing
277 system.physmem.readRowHits 151945 # Number of row buffer hits during reads
278 system.physmem.writeRowHits 129899 # Number of row buffer hits during writes
279 system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads
280 system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes
281 system.physmem.avgGap 13512725.27 # Average gap between requests
282 system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined
283 system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ)
284 system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ)
285 system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ)
286 system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ)
287 system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ)
288 system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ)
289 system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ)
290 system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ)
291 system.physmem_0.averagePower 668.747042 # Core power per rank (mW)
292 system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states
293 system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states
294 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
295 system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states
296 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
297 system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ)
298 system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ)
299 system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ)
300 system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ)
301 system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ)
302 system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ)
303 system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ)
304 system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ)
305 system.physmem_1.averagePower 668.766215 # Core power per rank (mW)
306 system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states
307 system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states
308 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
309 system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states
310 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
311 system.cpu.branchPred.lookups 86886659 # Number of BP lookups
312 system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted
313 system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect
314 system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups
315 system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits
316 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
317 system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage
318 system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target.
319 system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions.
320 system.cpu_clk_domain.clock 500 # Clock period in ticks
321 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
322 system.cpu.numCycles 452015949 # number of cpu cycles simulated
323 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
324 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
325 system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss
326 system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed
327 system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered
328 system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken
329 system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked
330 system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing
331 system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb
332 system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
333 system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps
334 system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions
335 system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR
336 system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched
337 system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed
338 system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed
339 system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
355 system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle
357 system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle
358 system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle
359 system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked
360 system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running
361 system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking
362 system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing
363 system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode
364 system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing
365 system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle
366 system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking
367 system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst
368 system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running
369 system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking
370 system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename
371 system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full
372 system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full
373 system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full
374 system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full
375 system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed
376 system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made
377 system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups
378 system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups
379 system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed
380 system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing
381 system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed
382 system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed
383 system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer
384 system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit.
385 system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit.
386 system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads.
387 system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores.
388 system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec)
389 system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ
390 system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued
391 system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued
392 system.cpu.iq.iqSquashedInstsExamined 23349289 # Number of squashed instructions iterated over during squash; mainly for profiling
393 system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph
394 system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed
395 system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
411 system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle
412 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
413 system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available
414 system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available
415 system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available
416 system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available
417 system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available
420 system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available
421 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available
442 system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available
443 system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available
444 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
445 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
446 system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued
447 system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued
448 system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued
449 system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued
450 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
451 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
455 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
476 system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued
477 system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued
478 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
479 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
480 system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued
481 system.cpu.iq.rate 1.823454 # Inst issue rate
482 system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested
483 system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst)
484 system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads
485 system.cpu.iq.int_inst_queue_writes 854027763 # Number of integer instruction queue writes
486 system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses
487 system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads
488 system.cpu.iq.fp_inst_queue_writes 488 # Number of floating instruction queue writes
489 system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
490 system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses
491 system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses
492 system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores
493 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
494 system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed
495 system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed
496 system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations
497 system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed
498 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
499 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
500 system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled
501 system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked
502 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
503 system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing
504 system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking
505 system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking
506 system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ
507 system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch
508 system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions
509 system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions
510 system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions
511 system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall
512 system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall
513 system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations
514 system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly
515 system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly
516 system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute
517 system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions
518 system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed
519 system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute
520 system.cpu.iew.exec_swp 0 # number of swp insts executed
521 system.cpu.iew.exec_nop 0 # number of nop insts executed
522 system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed
523 system.cpu.iew.exec_branches 83301836 # Number of branches executed
524 system.cpu.iew.exec_stores 9170146 # Number of stores executed
525 system.cpu.iew.exec_rate 1.819883 # Inst execution rate
526 system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit
527 system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back
528 system.cpu.iew.wb_producers 640992347 # num instructions producing a value
529 system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value
530 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
531 system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle
532 system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back
533 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
534 system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit
535 system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards
536 system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted
537 system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
552 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
553 system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle
554 system.cpu.commit.committedInsts 407959851 # Number of instructions committed
555 system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed
556 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
557 system.cpu.commit.refs 22418298 # Number of memory references committed
558 system.cpu.commit.loads 13992664 # Number of loads committed
559 system.cpu.commit.membars 471797 # Number of memory barriers committed
560 system.cpu.commit.branches 82198639 # Number of branches committed
561 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
562 system.cpu.commit.int_insts 735203522 # Number of committed integer instructions.
563 system.cpu.commit.function_calls 1155963 # Number of function calls committed.
564 system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction
565 system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction
566 system.cpu.commit.op_class_0::IntMult 144976 0.02% 97.21% # Class of committed instruction
567 system.cpu.commit.op_class_0::IntDiv 121468 0.02% 97.22% # Class of committed instruction
568 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
569 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
570 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
572 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
573 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
593 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction
595 system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction
596 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
597 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
598 system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction
599 system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached
600 system.cpu.rob.rob_reads 1270729806 # The number of ROB reads
601 system.cpu.rob.rob_writes 1664729387 # The number of ROB writes
602 system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself
603 system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling
604 system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
605 system.cpu.committedInsts 407959851 # Number of Instructions Simulated
606 system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated
607 system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction
608 system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads
609 system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle
610 system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads
611 system.cpu.int_regfile_reads 1092541258 # number of integer regfile reads
612 system.cpu.int_regfile_writes 656084038 # number of integer regfile writes
613 system.cpu.fp_regfile_reads 176 # number of floating regfile reads
614 system.cpu.cc_regfile_reads 416293281 # number of cc regfile reads
615 system.cpu.cc_regfile_writes 322054452 # number of cc regfile writes
616 system.cpu.misc_regfile_reads 265591845 # number of misc regfile reads
617 system.cpu.misc_regfile_writes 400328 # number of misc regfile writes
618 system.cpu.dcache.tags.replacements 1659836 # number of replacements
619 system.cpu.dcache.tags.tagsinuse 511.989699 # Cycle average of tags in use
620 system.cpu.dcache.tags.total_refs 19130413 # Total number of references to valid blocks.
621 system.cpu.dcache.tags.sampled_refs 1660348 # Sample count of references to valid blocks.
622 system.cpu.dcache.tags.avg_refs 11.521930 # Average number of references to valid blocks.
623 system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit.
624 system.cpu.dcache.tags.occ_blocks::cpu.data 511.989699 # Average occupied blocks per requestor
625 system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy
626 system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy
627 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
628 system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
629 system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
630 system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
631 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
632 system.cpu.dcache.tags.tag_accesses 88364873 # Number of tag accesses
633 system.cpu.dcache.tags.data_accesses 88364873 # Number of data accesses
634 system.cpu.dcache.ReadReq_hits::cpu.data 10981747 # number of ReadReq hits
635 system.cpu.dcache.ReadReq_hits::total 10981747 # number of ReadReq hits
636 system.cpu.dcache.WriteReq_hits::cpu.data 8081553 # number of WriteReq hits
637 system.cpu.dcache.WriteReq_hits::total 8081553 # number of WriteReq hits
638 system.cpu.dcache.SoftPFReq_hits::cpu.data 64328 # number of SoftPFReq hits
639 system.cpu.dcache.SoftPFReq_hits::total 64328 # number of SoftPFReq hits
640 system.cpu.dcache.demand_hits::cpu.data 19063300 # number of demand (read+write) hits
641 system.cpu.dcache.demand_hits::total 19063300 # number of demand (read+write) hits
642 system.cpu.dcache.overall_hits::cpu.data 19127628 # number of overall hits
643 system.cpu.dcache.overall_hits::total 19127628 # number of overall hits
644 system.cpu.dcache.ReadReq_misses::cpu.data 1807734 # number of ReadReq misses
645 system.cpu.dcache.ReadReq_misses::total 1807734 # number of ReadReq misses
646 system.cpu.dcache.WriteReq_misses::cpu.data 334390 # number of WriteReq misses
647 system.cpu.dcache.WriteReq_misses::total 334390 # number of WriteReq misses
648 system.cpu.dcache.SoftPFReq_misses::cpu.data 406367 # number of SoftPFReq misses
649 system.cpu.dcache.SoftPFReq_misses::total 406367 # number of SoftPFReq misses
650 system.cpu.dcache.demand_misses::cpu.data 2142124 # number of demand (read+write) misses
651 system.cpu.dcache.demand_misses::total 2142124 # number of demand (read+write) misses
652 system.cpu.dcache.overall_misses::cpu.data 2548491 # number of overall misses
653 system.cpu.dcache.overall_misses::total 2548491 # number of overall misses
654 system.cpu.dcache.ReadReq_miss_latency::cpu.data 27237843437 # number of ReadReq miss cycles
655 system.cpu.dcache.ReadReq_miss_latency::total 27237843437 # number of ReadReq miss cycles
656 system.cpu.dcache.WriteReq_miss_latency::cpu.data 13894605384 # number of WriteReq miss cycles
657 system.cpu.dcache.WriteReq_miss_latency::total 13894605384 # number of WriteReq miss cycles
658 system.cpu.dcache.demand_miss_latency::cpu.data 41132448821 # number of demand (read+write) miss cycles
659 system.cpu.dcache.demand_miss_latency::total 41132448821 # number of demand (read+write) miss cycles
660 system.cpu.dcache.overall_miss_latency::cpu.data 41132448821 # number of overall miss cycles
661 system.cpu.dcache.overall_miss_latency::total 41132448821 # number of overall miss cycles
662 system.cpu.dcache.ReadReq_accesses::cpu.data 12789481 # number of ReadReq accesses(hits+misses)
663 system.cpu.dcache.ReadReq_accesses::total 12789481 # number of ReadReq accesses(hits+misses)
664 system.cpu.dcache.WriteReq_accesses::cpu.data 8415943 # number of WriteReq accesses(hits+misses)
665 system.cpu.dcache.WriteReq_accesses::total 8415943 # number of WriteReq accesses(hits+misses)
666 system.cpu.dcache.SoftPFReq_accesses::cpu.data 470695 # number of SoftPFReq accesses(hits+misses)
667 system.cpu.dcache.SoftPFReq_accesses::total 470695 # number of SoftPFReq accesses(hits+misses)
668 system.cpu.dcache.demand_accesses::cpu.data 21205424 # number of demand (read+write) accesses
669 system.cpu.dcache.demand_accesses::total 21205424 # number of demand (read+write) accesses
670 system.cpu.dcache.overall_accesses::cpu.data 21676119 # number of overall (read+write) accesses
671 system.cpu.dcache.overall_accesses::total 21676119 # number of overall (read+write) accesses
672 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.141345 # miss rate for ReadReq accesses
673 system.cpu.dcache.ReadReq_miss_rate::total 0.141345 # miss rate for ReadReq accesses
674 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039733 # miss rate for WriteReq accesses
675 system.cpu.dcache.WriteReq_miss_rate::total 0.039733 # miss rate for WriteReq accesses
676 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863334 # miss rate for SoftPFReq accesses
677 system.cpu.dcache.SoftPFReq_miss_rate::total 0.863334 # miss rate for SoftPFReq accesses
678 system.cpu.dcache.demand_miss_rate::cpu.data 0.101018 # miss rate for demand accesses
679 system.cpu.dcache.demand_miss_rate::total 0.101018 # miss rate for demand accesses
680 system.cpu.dcache.overall_miss_rate::cpu.data 0.117571 # miss rate for overall accesses
681 system.cpu.dcache.overall_miss_rate::total 0.117571 # miss rate for overall accesses
682 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666 # average ReadReq miss latency
683 system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666 # average ReadReq miss latency
684 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008 # average WriteReq miss latency
685 system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008 # average WriteReq miss latency
686 system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329 # average overall miss latency
687 system.cpu.dcache.demand_avg_miss_latency::total 19201.712329 # average overall miss latency
688 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124 # average overall miss latency
689 system.cpu.dcache.overall_avg_miss_latency::total 16139.923124 # average overall miss latency
690 system.cpu.dcache.blocked_cycles::no_mshrs 413510 # number of cycles access was blocked
691 system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked
692 system.cpu.dcache.blocked::no_mshrs 44186 # number of cycles access was blocked
693 system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
694 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.358394 # average number of cycles each access was blocked
695 system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
696 system.cpu.dcache.fast_writes 0 # number of fast writes performed
697 system.cpu.dcache.cache_copies 0 # number of cache copies performed
698 system.cpu.dcache.writebacks::writebacks 1561658 # number of writebacks
699 system.cpu.dcache.writebacks::total 1561658 # number of writebacks
700 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 837908 # number of ReadReq MSHR hits
701 system.cpu.dcache.ReadReq_mshr_hits::total 837908 # number of ReadReq MSHR hits
702 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44444 # number of WriteReq MSHR hits
703 system.cpu.dcache.WriteReq_mshr_hits::total 44444 # number of WriteReq MSHR hits
704 system.cpu.dcache.demand_mshr_hits::cpu.data 882352 # number of demand (read+write) MSHR hits
705 system.cpu.dcache.demand_mshr_hits::total 882352 # number of demand (read+write) MSHR hits
706 system.cpu.dcache.overall_mshr_hits::cpu.data 882352 # number of overall MSHR hits
707 system.cpu.dcache.overall_mshr_hits::total 882352 # number of overall MSHR hits
708 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969826 # number of ReadReq MSHR misses
709 system.cpu.dcache.ReadReq_mshr_misses::total 969826 # number of ReadReq MSHR misses
710 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289946 # number of WriteReq MSHR misses
711 system.cpu.dcache.WriteReq_mshr_misses::total 289946 # number of WriteReq MSHR misses
712 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402900 # number of SoftPFReq MSHR misses
713 system.cpu.dcache.SoftPFReq_mshr_misses::total 402900 # number of SoftPFReq MSHR misses
714 system.cpu.dcache.demand_mshr_misses::cpu.data 1259772 # number of demand (read+write) MSHR misses
715 system.cpu.dcache.demand_mshr_misses::total 1259772 # number of demand (read+write) MSHR misses
716 system.cpu.dcache.overall_mshr_misses::cpu.data 1662672 # number of overall MSHR misses
717 system.cpu.dcache.overall_mshr_misses::total 1662672 # number of overall MSHR misses
718 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12862571524 # number of ReadReq MSHR miss cycles
719 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12862571524 # number of ReadReq MSHR miss cycles
720 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12285238213 # number of WriteReq MSHR miss cycles
721 system.cpu.dcache.WriteReq_mshr_miss_latency::total 12285238213 # number of WriteReq MSHR miss cycles
722 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5938147500 # number of SoftPFReq MSHR miss cycles
723 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5938147500 # number of SoftPFReq MSHR miss cycles
724 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25147809737 # number of demand (read+write) MSHR miss cycles
725 system.cpu.dcache.demand_mshr_miss_latency::total 25147809737 # number of demand (read+write) MSHR miss cycles
726 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31085957237 # number of overall MSHR miss cycles
727 system.cpu.dcache.overall_mshr_miss_latency::total 31085957237 # number of overall MSHR miss cycles
728 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97453049000 # number of ReadReq MSHR uncacheable cycles
729 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97453049000 # number of ReadReq MSHR uncacheable cycles
730 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2592894500 # number of WriteReq MSHR uncacheable cycles
731 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2592894500 # number of WriteReq MSHR uncacheable cycles
732 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500 # number of overall MSHR uncacheable cycles
733 system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500 # number of overall MSHR uncacheable cycles
734 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075830 # mshr miss rate for ReadReq accesses
735 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075830 # mshr miss rate for ReadReq accesses
736 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034452 # mshr miss rate for WriteReq accesses
737 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034452 # mshr miss rate for WriteReq accesses
738 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855968 # mshr miss rate for SoftPFReq accesses
739 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855968 # mshr miss rate for SoftPFReq accesses
740 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059408 # mshr miss rate for demand accesses
741 system.cpu.dcache.demand_mshr_miss_rate::total 0.059408 # mshr miss rate for demand accesses
742 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076705 # mshr miss rate for overall accesses
743 system.cpu.dcache.overall_mshr_miss_rate::total 0.076705 # mshr miss rate for overall accesses
744 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108 # average ReadReq mshr miss latency
745 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108 # average ReadReq mshr miss latency
746 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121 # average WriteReq mshr miss latency
747 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121 # average WriteReq mshr miss latency
748 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520 # average SoftPFReq mshr miss latency
749 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520 # average SoftPFReq mshr miss latency
750 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362 # average overall mshr miss latency
751 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362 # average overall mshr miss latency
752 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840 # average overall mshr miss latency
753 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840 # average overall mshr miss latency
754 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
755 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
756 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
757 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
758 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
759 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
760 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
761 system.cpu.dtb_walker_cache.tags.replacements 73822 # number of replacements
762 system.cpu.dtb_walker_cache.tags.tagsinuse 15.784353 # Cycle average of tags in use
763 system.cpu.dtb_walker_cache.tags.total_refs 116295 # Total number of references to valid blocks.
764 system.cpu.dtb_walker_cache.tags.sampled_refs 73836 # Sample count of references to valid blocks.
765 system.cpu.dtb_walker_cache.tags.avg_refs 1.575045 # Average number of references to valid blocks.
766 system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit.
767 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.784353 # Average occupied blocks per requestor
768 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986522 # Average percentage of cache occupancy
769 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986522 # Average percentage of cache occupancy
770 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
771 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
772 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
773 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
774 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
775 system.cpu.dtb_walker_cache.tags.tag_accesses 457427 # Number of tag accesses
776 system.cpu.dtb_walker_cache.tags.data_accesses 457427 # Number of data accesses
777 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116311 # number of ReadReq hits
778 system.cpu.dtb_walker_cache.ReadReq_hits::total 116311 # number of ReadReq hits
779 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116311 # number of demand (read+write) hits
780 system.cpu.dtb_walker_cache.demand_hits::total 116311 # number of demand (read+write) hits
781 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116311 # number of overall hits
782 system.cpu.dtb_walker_cache.overall_hits::total 116311 # number of overall hits
783 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74935 # number of ReadReq misses
784 system.cpu.dtb_walker_cache.ReadReq_misses::total 74935 # number of ReadReq misses
785 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74935 # number of demand (read+write) misses
786 system.cpu.dtb_walker_cache.demand_misses::total 74935 # number of demand (read+write) misses
787 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74935 # number of overall misses
788 system.cpu.dtb_walker_cache.overall_misses::total 74935 # number of overall misses
789 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914897711 # number of ReadReq miss cycles
790 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914897711 # number of ReadReq miss cycles
791 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914897711 # number of demand (read+write) miss cycles
792 system.cpu.dtb_walker_cache.demand_miss_latency::total 914897711 # number of demand (read+write) miss cycles
793 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914897711 # number of overall miss cycles
794 system.cpu.dtb_walker_cache.overall_miss_latency::total 914897711 # number of overall miss cycles
795 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191246 # number of ReadReq accesses(hits+misses)
796 system.cpu.dtb_walker_cache.ReadReq_accesses::total 191246 # number of ReadReq accesses(hits+misses)
797 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191246 # number of demand (read+write) accesses
798 system.cpu.dtb_walker_cache.demand_accesses::total 191246 # number of demand (read+write) accesses
799 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191246 # number of overall (read+write) accesses
800 system.cpu.dtb_walker_cache.overall_accesses::total 191246 # number of overall (read+write) accesses
801 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391825 # miss rate for ReadReq accesses
802 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391825 # miss rate for ReadReq accesses
803 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391825 # miss rate for demand accesses
804 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391825 # miss rate for demand accesses
805 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391825 # miss rate for overall accesses
806 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391825 # miss rate for overall accesses
807 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468 # average ReadReq miss latency
808 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468 # average ReadReq miss latency
809 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency
810 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468 # average overall miss latency
811 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency
812 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468 # average overall miss latency
813 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
814 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
816 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
817 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
818 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
819 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
820 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
821 system.cpu.dtb_walker_cache.writebacks::writebacks 20337 # number of writebacks
822 system.cpu.dtb_walker_cache.writebacks::total 20337 # number of writebacks
823 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74935 # number of ReadReq MSHR misses
824 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74935 # number of ReadReq MSHR misses
825 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74935 # number of demand (read+write) MSHR misses
826 system.cpu.dtb_walker_cache.demand_mshr_misses::total 74935 # number of demand (read+write) MSHR misses
827 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74935 # number of overall MSHR misses
828 system.cpu.dtb_walker_cache.overall_mshr_misses::total 74935 # number of overall MSHR misses
829 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 802357975 # number of ReadReq MSHR miss cycles
830 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 802357975 # number of ReadReq MSHR miss cycles
831 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 802357975 # number of demand (read+write) MSHR miss cycles
832 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 802357975 # number of demand (read+write) MSHR miss cycles
833 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 802357975 # number of overall MSHR miss cycles
834 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 802357975 # number of overall MSHR miss cycles
835 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for ReadReq accesses
836 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391825 # mshr miss rate for ReadReq accesses
837 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for demand accesses
838 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391825 # mshr miss rate for demand accesses
839 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for overall accesses
840 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391825 # mshr miss rate for overall accesses
841 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average ReadReq mshr miss latency
842 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068 # average ReadReq mshr miss latency
843 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency
844 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency
845 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency
846 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency
847 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
848 system.cpu.icache.tags.replacements 1000631 # number of replacements
849 system.cpu.icache.tags.tagsinuse 508.729229 # Cycle average of tags in use
850 system.cpu.icache.tags.total_refs 8114183 # Total number of references to valid blocks.
851 system.cpu.icache.tags.sampled_refs 1001143 # Sample count of references to valid blocks.
852 system.cpu.icache.tags.avg_refs 8.104919 # Average number of references to valid blocks.
853 system.cpu.icache.tags.warmup_cycle 148026169000 # Cycle when the warmup percentage was hit.
854 system.cpu.icache.tags.occ_blocks::cpu.inst 508.729229 # Average occupied blocks per requestor
855 system.cpu.icache.tags.occ_percent::cpu.inst 0.993612 # Average percentage of cache occupancy
856 system.cpu.icache.tags.occ_percent::total 0.993612 # Average percentage of cache occupancy
857 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
858 system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
859 system.cpu.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
860 system.cpu.icache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id
861 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
862 system.cpu.icache.tags.tag_accesses 10182374 # Number of tag accesses
863 system.cpu.icache.tags.data_accesses 10182374 # Number of data accesses
864 system.cpu.icache.ReadReq_hits::cpu.inst 8114183 # number of ReadReq hits
865 system.cpu.icache.ReadReq_hits::total 8114183 # number of ReadReq hits
866 system.cpu.icache.demand_hits::cpu.inst 8114183 # number of demand (read+write) hits
867 system.cpu.icache.demand_hits::total 8114183 # number of demand (read+write) hits
868 system.cpu.icache.overall_hits::cpu.inst 8114183 # number of overall hits
869 system.cpu.icache.overall_hits::total 8114183 # number of overall hits
870 system.cpu.icache.ReadReq_misses::cpu.inst 1066954 # number of ReadReq misses
871 system.cpu.icache.ReadReq_misses::total 1066954 # number of ReadReq misses
872 system.cpu.icache.demand_misses::cpu.inst 1066954 # number of demand (read+write) misses
873 system.cpu.icache.demand_misses::total 1066954 # number of demand (read+write) misses
874 system.cpu.icache.overall_misses::cpu.inst 1066954 # number of overall misses
875 system.cpu.icache.overall_misses::total 1066954 # number of overall misses
876 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14925731792 # number of ReadReq miss cycles
877 system.cpu.icache.ReadReq_miss_latency::total 14925731792 # number of ReadReq miss cycles
878 system.cpu.icache.demand_miss_latency::cpu.inst 14925731792 # number of demand (read+write) miss cycles
879 system.cpu.icache.demand_miss_latency::total 14925731792 # number of demand (read+write) miss cycles
880 system.cpu.icache.overall_miss_latency::cpu.inst 14925731792 # number of overall miss cycles
881 system.cpu.icache.overall_miss_latency::total 14925731792 # number of overall miss cycles
882 system.cpu.icache.ReadReq_accesses::cpu.inst 9181137 # number of ReadReq accesses(hits+misses)
883 system.cpu.icache.ReadReq_accesses::total 9181137 # number of ReadReq accesses(hits+misses)
884 system.cpu.icache.demand_accesses::cpu.inst 9181137 # number of demand (read+write) accesses
885 system.cpu.icache.demand_accesses::total 9181137 # number of demand (read+write) accesses
886 system.cpu.icache.overall_accesses::cpu.inst 9181137 # number of overall (read+write) accesses
887 system.cpu.icache.overall_accesses::total 9181137 # number of overall (read+write) accesses
888 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116212 # miss rate for ReadReq accesses
889 system.cpu.icache.ReadReq_miss_rate::total 0.116212 # miss rate for ReadReq accesses
890 system.cpu.icache.demand_miss_rate::cpu.inst 0.116212 # miss rate for demand accesses
891 system.cpu.icache.demand_miss_rate::total 0.116212 # miss rate for demand accesses
892 system.cpu.icache.overall_miss_rate::cpu.inst 0.116212 # miss rate for overall accesses
893 system.cpu.icache.overall_miss_rate::total 0.116212 # miss rate for overall accesses
894 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240 # average ReadReq miss latency
895 system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240 # average ReadReq miss latency
896 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency
897 system.cpu.icache.demand_avg_miss_latency::total 13989.105240 # average overall miss latency
898 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency
899 system.cpu.icache.overall_avg_miss_latency::total 13989.105240 # average overall miss latency
900 system.cpu.icache.blocked_cycles::no_mshrs 10002 # number of cycles access was blocked
901 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
902 system.cpu.icache.blocked::no_mshrs 328 # number of cycles access was blocked
903 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
904 system.cpu.icache.avg_blocked_cycles::no_mshrs 30.493902 # average number of cycles each access was blocked
905 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
906 system.cpu.icache.fast_writes 0 # number of fast writes performed
907 system.cpu.icache.cache_copies 0 # number of cache copies performed
908 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65717 # number of ReadReq MSHR hits
909 system.cpu.icache.ReadReq_mshr_hits::total 65717 # number of ReadReq MSHR hits
910 system.cpu.icache.demand_mshr_hits::cpu.inst 65717 # number of demand (read+write) MSHR hits
911 system.cpu.icache.demand_mshr_hits::total 65717 # number of demand (read+write) MSHR hits
912 system.cpu.icache.overall_mshr_hits::cpu.inst 65717 # number of overall MSHR hits
913 system.cpu.icache.overall_mshr_hits::total 65717 # number of overall MSHR hits
914 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001237 # number of ReadReq MSHR misses
915 system.cpu.icache.ReadReq_mshr_misses::total 1001237 # number of ReadReq MSHR misses
916 system.cpu.icache.demand_mshr_misses::cpu.inst 1001237 # number of demand (read+write) MSHR misses
917 system.cpu.icache.demand_mshr_misses::total 1001237 # number of demand (read+write) MSHR misses
918 system.cpu.icache.overall_mshr_misses::cpu.inst 1001237 # number of overall MSHR misses
919 system.cpu.icache.overall_mshr_misses::total 1001237 # number of overall MSHR misses
920 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12740674547 # number of ReadReq MSHR miss cycles
921 system.cpu.icache.ReadReq_mshr_miss_latency::total 12740674547 # number of ReadReq MSHR miss cycles
922 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12740674547 # number of demand (read+write) MSHR miss cycles
923 system.cpu.icache.demand_mshr_miss_latency::total 12740674547 # number of demand (read+write) MSHR miss cycles
924 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12740674547 # number of overall MSHR miss cycles
925 system.cpu.icache.overall_mshr_miss_latency::total 12740674547 # number of overall MSHR miss cycles
926 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for ReadReq accesses
927 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109054 # mshr miss rate for ReadReq accesses
928 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for demand accesses
929 system.cpu.icache.demand_mshr_miss_rate::total 0.109054 # mshr miss rate for demand accesses
930 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for overall accesses
931 system.cpu.icache.overall_mshr_miss_rate::total 0.109054 # mshr miss rate for overall accesses
932 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804 # average ReadReq mshr miss latency
933 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804 # average ReadReq mshr miss latency
934 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency
935 system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency
936 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency
937 system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency
938 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
939 system.cpu.itb_walker_cache.tags.replacements 14933 # number of replacements
940 system.cpu.itb_walker_cache.tags.tagsinuse 6.063651 # Cycle average of tags in use
941 system.cpu.itb_walker_cache.tags.total_refs 25583 # Total number of references to valid blocks.
942 system.cpu.itb_walker_cache.tags.sampled_refs 14948 # Sample count of references to valid blocks.
943 system.cpu.itb_walker_cache.tags.avg_refs 1.711466 # Average number of references to valid blocks.
944 system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500 # Cycle when the warmup percentage was hit.
945 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.063651 # Average occupied blocks per requestor
946 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.378978 # Average percentage of cache occupancy
947 system.cpu.itb_walker_cache.tags.occ_percent::total 0.378978 # Average percentage of cache occupancy
948 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
949 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
950 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
951 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
952 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
953 system.cpu.itb_walker_cache.tags.tag_accesses 98613 # Number of tag accesses
954 system.cpu.itb_walker_cache.tags.data_accesses 98613 # Number of data accesses
955 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25588 # number of ReadReq hits
956 system.cpu.itb_walker_cache.ReadReq_hits::total 25588 # number of ReadReq hits
957 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
958 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
959 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25590 # number of demand (read+write) hits
960 system.cpu.itb_walker_cache.demand_hits::total 25590 # number of demand (read+write) hits
961 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25590 # number of overall hits
962 system.cpu.itb_walker_cache.overall_hits::total 25590 # number of overall hits
963 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15811 # number of ReadReq misses
964 system.cpu.itb_walker_cache.ReadReq_misses::total 15811 # number of ReadReq misses
965 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15811 # number of demand (read+write) misses
966 system.cpu.itb_walker_cache.demand_misses::total 15811 # number of demand (read+write) misses
967 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15811 # number of overall misses
968 system.cpu.itb_walker_cache.overall_misses::total 15811 # number of overall misses
969 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183242996 # number of ReadReq miss cycles
970 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183242996 # number of ReadReq miss cycles
971 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183242996 # number of demand (read+write) miss cycles
972 system.cpu.itb_walker_cache.demand_miss_latency::total 183242996 # number of demand (read+write) miss cycles
973 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183242996 # number of overall miss cycles
974 system.cpu.itb_walker_cache.overall_miss_latency::total 183242996 # number of overall miss cycles
975 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41399 # number of ReadReq accesses(hits+misses)
976 system.cpu.itb_walker_cache.ReadReq_accesses::total 41399 # number of ReadReq accesses(hits+misses)
977 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
978 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
979 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41401 # number of demand (read+write) accesses
980 system.cpu.itb_walker_cache.demand_accesses::total 41401 # number of demand (read+write) accesses
981 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41401 # number of overall (read+write) accesses
982 system.cpu.itb_walker_cache.overall_accesses::total 41401 # number of overall (read+write) accesses
983 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381917 # miss rate for ReadReq accesses
984 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381917 # miss rate for ReadReq accesses
985 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381899 # miss rate for demand accesses
986 system.cpu.itb_walker_cache.demand_miss_rate::total 0.381899 # miss rate for demand accesses
987 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381899 # miss rate for overall accesses
988 system.cpu.itb_walker_cache.overall_miss_rate::total 0.381899 # miss rate for overall accesses
989 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273 # average ReadReq miss latency
990 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273 # average ReadReq miss latency
991 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency
992 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency
993 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency
994 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency
995 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
996 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
997 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
998 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
999 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1000 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1001 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1002 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1003 system.cpu.itb_walker_cache.writebacks::writebacks 3310 # number of writebacks
1004 system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks
1005 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15811 # number of ReadReq MSHR misses
1006 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses
1007 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15811 # number of demand (read+write) MSHR misses
1008 system.cpu.itb_walker_cache.demand_mshr_misses::total 15811 # number of demand (read+write) MSHR misses
1009 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15811 # number of overall MSHR misses
1010 system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses
1011 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159511522 # number of ReadReq MSHR miss cycles
1012 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159511522 # number of ReadReq MSHR miss cycles
1013 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles
1014 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159511522 # number of demand (read+write) MSHR miss cycles
1015 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles
1016 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles
1017 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381917 # mshr miss rate for ReadReq accesses
1018 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381917 # mshr miss rate for ReadReq accesses
1019 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for demand accesses
1020 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381899 # mshr miss rate for demand accesses
1021 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for overall accesses
1022 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381899 # mshr miss rate for overall accesses
1023 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average ReadReq mshr miss latency
1024 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211 # average ReadReq mshr miss latency
1025 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency
1026 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency
1027 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency
1028 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency
1029 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1030 system.cpu.l2cache.tags.replacements 112684 # number of replacements
1031 system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use
1032 system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks.
1033 system.cpu.l2cache.tags.sampled_refs 176714 # Sample count of references to valid blocks.
1034 system.cpu.l2cache.tags.avg_refs 21.765089 # Average number of references to valid blocks.
1035 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1036 system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250 # Average occupied blocks per requestor
1037 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.517179 # Average occupied blocks per requestor
1038 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.137228 # Average occupied blocks per requestor
1039 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3161.997282 # Average occupied blocks per requestor
1040 system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561 # Average occupied blocks per requestor
1041 system.cpu.l2cache.tags.occ_percent::writebacks 0.768450 # Average percentage of cache occupancy
1042 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000237 # Average percentage of cache occupancy
1043 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1044 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048248 # Average percentage of cache occupancy
1045 system.cpu.l2cache.tags.occ_percent::cpu.data 0.172226 # Average percentage of cache occupancy
1046 system.cpu.l2cache.tags.occ_percent::total 0.989163 # Average percentage of cache occupancy
1047 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64030 # Occupied blocks per task id
1048 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
1049 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id
1050 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3484 # Occupied blocks per task id
1051 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5616 # Occupied blocks per task id
1052 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id
1053 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977020 # Percentage of cache occupancy per task id
1054 system.cpu.l2cache.tags.tag_accesses 35101682 # Number of tag accesses
1055 system.cpu.l2cache.tags.data_accesses 35101682 # Number of data accesses
1056 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67331 # number of ReadReq hits
1057 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13137 # number of ReadReq hits
1058 system.cpu.l2cache.ReadReq_hits::cpu.inst 984666 # number of ReadReq hits
1059 system.cpu.l2cache.ReadReq_hits::cpu.data 1336353 # number of ReadReq hits
1060 system.cpu.l2cache.ReadReq_hits::total 2401487 # number of ReadReq hits
1061 system.cpu.l2cache.Writeback_hits::writebacks 1585305 # number of Writeback hits
1062 system.cpu.l2cache.Writeback_hits::total 1585305 # number of Writeback hits
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1120 system.cpu.l2cache.Writeback_accesses::writebacks 1585305 # number of Writeback accesses(hits+misses)
1121 system.cpu.l2cache.Writeback_accesses::total 1585305 # number of Writeback accesses(hits+misses)
1122 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses)
1123 system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses)
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1125 system.cpu.l2cache.ReadExReq_accesses::total 287805 # number of ReadExReq accesses(hits+misses)
1126 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67397 # number of demand (read+write) accesses
1127 system.cpu.l2cache.demand_accesses::cpu.itb.walker 13142 # number of demand (read+write) accesses
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1132 system.cpu.l2cache.overall_accesses::cpu.itb.walker 13142 # number of overall (read+write) accesses
1133 system.cpu.l2cache.overall_accesses::cpu.inst 1001057 # number of overall (read+write) accesses
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1135 system.cpu.l2cache.overall_accesses::total 2741377 # number of overall (read+write) accesses
1136 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000979 # miss rate for ReadReq accesses
1137 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000380 # miss rate for ReadReq accesses
1138 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016374 # miss rate for ReadReq accesses
1139 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025965 # miss rate for ReadReq accesses
1140 system.cpu.l2cache.ReadReq_miss_rate::total 0.021228 # miss rate for ReadReq accesses
1141 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818788 # miss rate for UpgradeReq accesses
1142 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses
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1144 system.cpu.l2cache.ReadExReq_miss_rate::total 0.463713 # miss rate for ReadExReq accesses
1145 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000979 # miss rate for demand accesses
1146 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000380 # miss rate for demand accesses
1147 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016374 # miss rate for demand accesses
1148 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101870 # miss rate for demand accesses
1149 system.cpu.l2cache.demand_miss_rate::total 0.067683 # miss rate for demand accesses
1150 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000979 # miss rate for overall accesses
1151 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000380 # miss rate for overall accesses
1152 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016374 # miss rate for overall accesses
1153 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101870 # miss rate for overall accesses
1154 system.cpu.l2cache.overall_miss_rate::total 0.067683 # miss rate for overall accesses
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1156 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89200 # average ReadReq miss latency
1157 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849 # average ReadReq miss latency
1158 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708 # average ReadReq miss latency
1159 system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432 # average ReadReq miss latency
1160 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714 # average UpgradeReq miss latency
1161 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714 # average UpgradeReq miss latency
1162 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891 # average ReadExReq miss latency
1163 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891 # average ReadExReq miss latency
1164 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency
1165 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency
1166 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency
1167 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency
1168 system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776 # average overall miss latency
1169 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency
1170 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency
1171 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency
1172 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency
1173 system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776 # average overall miss latency
1174 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1175 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1176 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1177 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1178 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1179 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1180 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1181 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1182 system.cpu.l2cache.writebacks::writebacks 103019 # number of writebacks
1183 system.cpu.l2cache.writebacks::total 103019 # number of writebacks
1184 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
1185 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1186 system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
1187 system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
1188 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1189 system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
1190 system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
1191 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
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1193 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
1194 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
1195 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16388 # number of ReadReq MSHR misses
1196 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35622 # number of ReadReq MSHR misses
1197 system.cpu.l2cache.ReadReq_mshr_misses::total 52081 # number of ReadReq MSHR misses
1198 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1473 # number of UpgradeReq MSHR misses
1199 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1473 # number of UpgradeReq MSHR misses
1200 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133459 # number of ReadExReq MSHR misses
1201 system.cpu.l2cache.ReadExReq_mshr_misses::total 133459 # number of ReadExReq MSHR misses
1202 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
1203 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1204 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16388 # number of demand (read+write) MSHR misses
1205 system.cpu.l2cache.demand_mshr_misses::cpu.data 169081 # number of demand (read+write) MSHR misses
1206 system.cpu.l2cache.demand_mshr_misses::total 185540 # number of demand (read+write) MSHR misses
1207 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
1208 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1209 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16388 # number of overall MSHR misses
1210 system.cpu.l2cache.overall_mshr_misses::cpu.data 169081 # number of overall MSHR misses
1211 system.cpu.l2cache.overall_mshr_misses::total 185540 # number of overall MSHR misses
1212 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5361750 # number of ReadReq MSHR miss cycles
1213 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 383000 # number of ReadReq MSHR miss cycles
1214 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1170197226 # number of ReadReq MSHR miss cycles
1215 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2615090750 # number of ReadReq MSHR miss cycles
1216 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3791032726 # number of ReadReq MSHR miss cycles
1217 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27003455 # number of UpgradeReq MSHR miss cycles
1218 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27003455 # number of UpgradeReq MSHR miss cycles
1219 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8650755527 # number of ReadExReq MSHR miss cycles
1220 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8650755527 # number of ReadExReq MSHR miss cycles
1221 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5361750 # number of demand (read+write) MSHR miss cycles
1222 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 383000 # number of demand (read+write) MSHR miss cycles
1223 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170197226 # number of demand (read+write) MSHR miss cycles
1224 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11265846277 # number of demand (read+write) MSHR miss cycles
1225 system.cpu.l2cache.demand_mshr_miss_latency::total 12441788253 # number of demand (read+write) MSHR miss cycles
1226 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5361750 # number of overall MSHR miss cycles
1227 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 383000 # number of overall MSHR miss cycles
1228 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170197226 # number of overall MSHR miss cycles
1229 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11265846277 # number of overall MSHR miss cycles
1230 system.cpu.l2cache.overall_mshr_miss_latency::total 12441788253 # number of overall MSHR miss cycles
1231 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88987317500 # number of ReadReq MSHR uncacheable cycles
1232 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88987317500 # number of ReadReq MSHR uncacheable cycles
1233 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2410942500 # number of WriteReq MSHR uncacheable cycles
1234 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2410942500 # number of WriteReq MSHR uncacheable cycles
1235 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91398260000 # number of overall MSHR uncacheable cycles
1236 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91398260000 # number of overall MSHR uncacheable cycles
1237 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for ReadReq accesses
1238 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for ReadReq accesses
1239 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for ReadReq accesses
1240 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025964 # mshr miss rate for ReadReq accesses
1241 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021227 # mshr miss rate for ReadReq accesses
1242 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818788 # mshr miss rate for UpgradeReq accesses
1243 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818788 # mshr miss rate for UpgradeReq accesses
1244 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463713 # mshr miss rate for ReadExReq accesses
1245 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463713 # mshr miss rate for ReadExReq accesses
1246 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for demand accesses
1247 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for demand accesses
1248 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for demand accesses
1249 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for demand accesses
1250 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067681 # mshr miss rate for demand accesses
1251 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for overall accesses
1252 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for overall accesses
1253 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for overall accesses
1254 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for overall accesses
1255 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067681 # mshr miss rate for overall accesses
1256 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average ReadReq mshr miss latency
1257 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76600 # average ReadReq mshr miss latency
1258 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491 # average ReadReq mshr miss latency
1259 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224 # average ReadReq mshr miss latency
1260 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380 # average ReadReq mshr miss latency
1261 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18332.284453 # average UpgradeReq mshr miss latency
1262 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453 # average UpgradeReq mshr miss latency
1263 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004 # average ReadExReq mshr miss latency
1264 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004 # average ReadExReq mshr miss latency
1265 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency
1266 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency
1267 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency
1268 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency
1269 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency
1270 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency
1271 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency
1272 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency
1273 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency
1274 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency
1275 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1276 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1277 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1278 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1279 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1280 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1281 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1282 system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution
1283 system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution
1284 system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
1285 system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
1286 system.cpu.toL2Bus.trans_dist::Writeback 1585305 # Transaction distribution
1287 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46754 # Transaction distribution
1288 system.cpu.toL2Bus.trans_dist::UpgradeReq 2280 # Transaction distribution
1289 system.cpu.toL2Bus.trans_dist::UpgradeResp 2280 # Transaction distribution
1290 system.cpu.toL2Bus.trans_dist::ReadExReq 287814 # Transaction distribution
1291 system.cpu.toL2Bus.trans_dist::ReadExResp 287814 # Transaction distribution
1292 system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
1293 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002294 # Packet count per connected master and slave (bytes)
1294 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123530 # Packet count per connected master and slave (bytes)
1295 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32263 # Packet count per connected master and slave (bytes)
1296 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162669 # Packet count per connected master and slave (bytes)
1297 system.cpu.toL2Bus.pkt_count::total 8320756 # Packet count per connected master and slave (bytes)
1298 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64067648 # Cumulative packet size per connected master and slave (bytes)
1299 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207974818 # Cumulative packet size per connected master and slave (bytes)
1300 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1052928 # Cumulative packet size per connected master and slave (bytes)
1301 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5614976 # Cumulative packet size per connected master and slave (bytes)
1302 system.cpu.toL2Bus.pkt_size::total 278710370 # Cumulative packet size per connected master and slave (bytes)
1303 system.cpu.toL2Bus.snoops 59545 # Total snoops (count)
1304 system.cpu.toL2Bus.snoop_fanout::samples 4387643 # Request fanout histogram
1305 system.cpu.toL2Bus.snoop_fanout::mean 3.010865 # Request fanout histogram
1306 system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram
1307 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1308 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1309 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1310 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1311 system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram
1312 system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram
1313 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1314 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1315 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1316 system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram
1317 system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks)
1318 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1319 system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks)
1320 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1321 system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks)
1322 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1323 system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks)
1324 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1325 system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks)
1326 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1327 system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks)
1328 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1329 system.iobus.trans_dist::ReadReq 223900 # Transaction distribution
1330 system.iobus.trans_dist::ReadResp 223900 # Transaction distribution
1331 system.iobus.trans_dist::WriteReq 57738 # Transaction distribution
1332 system.iobus.trans_dist::WriteResp 11018 # Transaction distribution
1333 system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1334 system.iobus.trans_dist::MessageReq 1650 # Transaction distribution
1335 system.iobus.trans_dist::MessageResp 1650 # Transaction distribution
1336 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1337 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1338 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
1339 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1340 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1341 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1342 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1343 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1344 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes)
1345 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1346 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1347 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1348 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1349 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1350 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1351 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1352 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1353 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1354 system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes)
1355 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes)
1356 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes)
1357 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes)
1358 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes)
1359 system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes)
1360 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1361 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1362 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
1363 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1364 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1365 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1366 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1367 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1368 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes)
1369 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1370 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1371 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1372 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1373 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1374 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1375 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1376 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1377 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1378 system.iobus.pkt_size_system.bridge.master::total 240285 # Cumulative packet size per connected master and slave (bytes)
1379 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes)
1380 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes)
1381 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes)
1382 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes)
1383 system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes)
1384 system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks)
1385 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1386 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1387 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1388 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1389 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1390 system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
1391 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1392 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1393 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1394 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1395 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1396 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1397 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1398 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1399 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1400 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1401 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1402 system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks)
1403 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1404 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1405 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1406 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1407 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1408 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1409 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1410 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1411 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1412 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1413 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1414 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1415 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1416 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1417 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1418 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1419 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1420 system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks)
1421 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1422 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1423 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1424 system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks)
1425 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1426 system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks)
1427 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1428 system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks)
1429 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1430 system.iocache.tags.replacements 47582 # number of replacements
1431 system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use
1432 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1433 system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks.
1434 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1435 system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit.
1436 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor
1437 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011120 # Average percentage of cache occupancy
1438 system.iocache.tags.occ_percent::total 0.011120 # Average percentage of cache occupancy
1439 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1440 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1441 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1442 system.iocache.tags.tag_accesses 428724 # Number of tag accesses
1443 system.iocache.tags.data_accesses 428724 # Number of data accesses
1444 system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses
1445 system.iocache.ReadReq_misses::total 916 # number of ReadReq misses
1446 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1447 system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1448 system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses
1449 system.iocache.demand_misses::total 916 # number of demand (read+write) misses
1450 system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses
1451 system.iocache.overall_misses::total 916 # number of overall misses
1452 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144791938 # number of ReadReq miss cycles
1453 system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles
1454 system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles
1455 system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles
1456 system.iocache.demand_miss_latency::pc.south_bridge.ide 144791938 # number of demand (read+write) miss cycles
1457 system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles
1458 system.iocache.overall_miss_latency::pc.south_bridge.ide 144791938 # number of overall miss cycles
1459 system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles
1460 system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses)
1461 system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses)
1462 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1463 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1464 system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses
1465 system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses
1466 system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses
1467 system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses
1468 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1469 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1470 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1471 system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1472 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1473 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1474 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1475 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1476 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency
1477 system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency
1478 system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency
1479 system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency
1480 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency
1481 system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency
1482 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency
1483 system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency
1484 system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked
1485 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1486 system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked
1487 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1488 system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked
1489 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1490 system.iocache.fast_writes 0 # number of fast writes performed
1491 system.iocache.cache_copies 0 # number of cache copies performed
1492 system.iocache.writebacks::writebacks 46668 # number of writebacks
1493 system.iocache.writebacks::total 46668 # number of writebacks
1494 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses
1495 system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
1496 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1497 system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1498 system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses
1499 system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
1500 system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses
1501 system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses
1502 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles
1503 system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles
1504 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles
1505 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles
1506 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles
1507 system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles
1508 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles
1509 system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles
1510 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1511 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1512 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1513 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1514 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1515 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1516 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1517 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1518 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency
1519 system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency
1520 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency
1521 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency
1522 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency
1523 system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency
1524 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency
1525 system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency
1526 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1527 system.membus.trans_dist::ReadReq 657690 # Transaction distribution
1528 system.membus.trans_dist::ReadResp 657682 # Transaction distribution
1529 system.membus.trans_dist::WriteReq 13919 # Transaction distribution
1530 system.membus.trans_dist::WriteResp 13919 # Transaction distribution
1531 system.membus.trans_dist::Writeback 149687 # Transaction distribution
1532 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1533 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1534 system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution
1535 system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution
1536 system.membus.trans_dist::ReadExReq 133182 # Transaction distribution
1537 system.membus.trans_dist::ReadExResp 133180 # Transaction distribution
1538 system.membus.trans_dist::MessageReq 1650 # Transaction distribution
1539 system.membus.trans_dist::MessageResp 1650 # Transaction distribution
1540 system.membus.trans_dist::BadAddressError 8 # Transaction distribution
1541 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes)
1542 system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes)
1543 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes)
1544 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes)
1545 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes)
1546 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
1547 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes)
1548 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes)
1549 system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes)
1550 system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes)
1551 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes)
1552 system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes)
1553 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes)
1554 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes)
1555 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes)
1556 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes)
1557 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes)
1558 system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes)
1559 system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes)
1560 system.membus.snoops 1640 # Total snoops (count)
1561 system.membus.snoop_fanout::samples 384867 # Request fanout histogram
1562 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1563 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1564 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1565 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1566 system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram
1567 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1568 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1569 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1570 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1571 system.membus.snoop_fanout::total 384867 # Request fanout histogram
1572 system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks)
1573 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1574 system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks)
1575 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1576 system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks)
1577 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1578 system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks)
1579 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1580 system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
1581 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1582 system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks)
1583 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1584 system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks)
1585 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1586 system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks)
1587 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1588 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1589 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1590 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
1591 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1592 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1593 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1594 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1595 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1596 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1597 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1598 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1599 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1600 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1601 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1603 ---------- End Simulation Statistics ----------
projects / gem5.git / blob