2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.130109 # Number of seconds simulated
4 sim_ticks 5130108675000 # Number of ticks simulated
5 final_tick 5130108675000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 172691 # Simulator instruction rate (inst/s)
8 host_op_rate 341343 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2172133567 # Simulator tick rate (ticks/s)
10 host_mem_usage 759908 # Number of bytes of host memory used
11 host_seconds 2361.78 # Real time elapsed on the host
12 sim_insts 407858109 # Number of instructions simulated
13 sim_ops 806179275 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 4288 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1044544 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10779584 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11857088 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1044544 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1044544 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9583168 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9583168 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 67 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16321 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168431 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185267 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149737 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149737 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 836 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 203611 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2101239 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2311274 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 203611 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 203611 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1868024 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1868024 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1868024 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 836 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 203611 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2101239 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4179299 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185267 # Number of read requests accepted
52 system.physmem.writeReqs 149737 # Number of write requests accepted
53 system.physmem.readBursts 185267 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 149737 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11846656 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9581440 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11857088 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9583168 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 48775 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11590 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 11256 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 12288 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11911 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11840 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11665 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 10867 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 10808 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11222 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11056 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11302 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11775 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 11547 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12196 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11932 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11849 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 10246 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9545 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 9025 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 8913 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9024 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 9097 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 8779 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 8697 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 8886 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 9043 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 9545 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 9380 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9802 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9849 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 10052 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9827 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
97 system.physmem.totGap 5130108625500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185267 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 149737 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 170610 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11668 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 2033 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 465 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 36 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2238 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 2978 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 7955 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 7943 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 7727 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 7753 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 7793 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 9624 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 9979 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 11771 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 10405 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 9975 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 8508 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 9054 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 9102 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 7802 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 7701 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 7621 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 246 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 204 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 210 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 220 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 177 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 127 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 163 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 93 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 72239 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 296.626919 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 176.108811 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 319.147383 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 27668 38.30% 38.30% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17613 24.38% 62.68% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7498 10.38% 73.06% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4242 5.87% 78.93% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 2823 3.91% 82.84% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 1928 2.67% 85.51% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1515 2.10% 87.61% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1131 1.57% 89.17% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 7821 10.83% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 72239 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7351 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 25.179159 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 561.374907 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7350 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7351 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7351 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 20.365937 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.603384 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 13.112022 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6287 85.53% 85.53% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 96 1.31% 86.83% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 185 2.52% 89.35% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 82 1.12% 90.46% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 111 1.51% 91.97% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 202 2.75% 94.72% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 31 0.42% 95.14% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 14 0.19% 95.33% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 14 0.19% 95.52% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 10 0.14% 95.66% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 9 0.12% 95.78% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 5 0.07% 95.85% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 246 3.35% 99.20% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 8 0.11% 99.47% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::100-103 7 0.10% 99.61% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::108-111 1 0.01% 99.62% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::112-115 2 0.03% 99.65% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::124-127 2 0.03% 99.67% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::128-131 14 0.19% 99.86% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::140-143 1 0.01% 99.88% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::152-155 2 0.03% 99.92% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::164-167 2 0.03% 99.95% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::176-179 3 0.04% 99.99% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::total 7351 # Writes before turning the bus around for reads
262 system.physmem.totQLat 1992019456 # Total ticks spent queuing
263 system.physmem.totMemAccLat 5462719456 # Total ticks spent from burst creation until serviced by the DRAM
264 system.physmem.totBusLat 925520000 # Total ticks spent in databus transfers
265 system.physmem.avgQLat 10761.62 # Average queueing delay per DRAM burst
266 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
267 system.physmem.avgMemAccLat 29511.62 # Average memory access latency per DRAM burst
268 system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
269 system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
270 system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s
271 system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
272 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
273 system.physmem.busUtil 0.03 # Data bus utilization in percentage
274 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
275 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
276 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
277 system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing
278 system.physmem.readRowHits 151846 # Number of row buffer hits during reads
279 system.physmem.writeRowHits 110728 # Number of row buffer hits during writes
280 system.physmem.readRowHitRate 82.03 # Row buffer hit rate for reads
281 system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes
282 system.physmem.avgGap 15313574.24 # Average gap between requests
283 system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined
284 system.physmem_0.actEnergy 269393040 # Energy for activate commands per rank (pJ)
285 system.physmem_0.preEnergy 146990250 # Energy for precharge commands per rank (pJ)
286 system.physmem_0.readEnergy 719355000 # Energy for read commands per rank (pJ)
287 system.physmem_0.writeEnergy 475152480 # Energy for write commands per rank (pJ)
288 system.physmem_0.refreshEnergy 335073401520 # Energy for refresh commands per rank (pJ)
289 system.physmem_0.actBackEnergy 129448929735 # Energy for active background per rank (pJ)
290 system.physmem_0.preBackEnergy 2964510370500 # Energy for precharge background per rank (pJ)
291 system.physmem_0.totalEnergy 3430643592525 # Total energy per rank (pJ)
292 system.physmem_0.averagePower 668.727957 # Core power per rank (mW)
293 system.physmem_0.memoryStateTime::IDLE 4931666056220 # Time in different power states
294 system.physmem_0.memoryStateTime::REF 171305420000 # Time in different power states
295 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
296 system.physmem_0.memoryStateTime::ACT 27131976280 # Time in different power states
297 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
298 system.physmem_1.actEnergy 276733800 # Energy for activate commands per rank (pJ)
299 system.physmem_1.preEnergy 150995625 # Energy for precharge commands per rank (pJ)
300 system.physmem_1.readEnergy 724448400 # Energy for read commands per rank (pJ)
301 system.physmem_1.writeEnergy 494968320 # Energy for write commands per rank (pJ)
302 system.physmem_1.refreshEnergy 335073401520 # Energy for refresh commands per rank (pJ)
303 system.physmem_1.actBackEnergy 129698055360 # Energy for active background per rank (pJ)
304 system.physmem_1.preBackEnergy 2964291831000 # Energy for precharge background per rank (pJ)
305 system.physmem_1.totalEnergy 3430710434025 # Total energy per rank (pJ)
306 system.physmem_1.averagePower 668.740988 # Core power per rank (mW)
307 system.physmem_1.memoryStateTime::IDLE 4931307220986 # Time in different power states
308 system.physmem_1.memoryStateTime::REF 171305420000 # Time in different power states
309 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
310 system.physmem_1.memoryStateTime::ACT 27495924014 # Time in different power states
311 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
312 system.cpu.branchPred.lookups 86802866 # Number of BP lookups
313 system.cpu.branchPred.condPredicted 86802866 # Number of conditional branches predicted
314 system.cpu.branchPred.condIncorrect 898884 # Number of conditional branches incorrect
315 system.cpu.branchPred.BTBLookups 79915985 # Number of BTB lookups
316 system.cpu.branchPred.BTBHits 78142205 # Number of BTB hits
317 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
318 system.cpu.branchPred.BTBHitPct 97.780444 # BTB Hit Percentage
319 system.cpu.branchPred.usedRAS 1557172 # Number of times the RAS was used to get a target.
320 system.cpu.branchPred.RASInCorrect 181109 # Number of incorrect RAS predictions.
321 system.cpu_clk_domain.clock 500 # Clock period in ticks
322 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
323 system.cpu.numCycles 449354840 # number of cpu cycles simulated
324 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
325 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
326 system.cpu.fetch.icacheStallCycles 27419696 # Number of cycles fetch is stalled on an Icache miss
327 system.cpu.fetch.Insts 428691862 # Number of instructions fetch has processed
328 system.cpu.fetch.Branches 86802866 # Number of branches that fetch encountered
329 system.cpu.fetch.predictedBranches 79699377 # Number of branches that fetch has predicted taken
330 system.cpu.fetch.Cycles 417944649 # Number of cycles fetch has run and was not squashing or blocked
331 system.cpu.fetch.SquashCycles 1884104 # Number of cycles fetch has spent squashing
332 system.cpu.fetch.TlbCycles 141232 # Number of cycles fetch has spent waiting for tlb
333 system.cpu.fetch.MiscStallCycles 57475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
334 system.cpu.fetch.PendingTrapStallCycles 210217 # Number of stall cycles due to pending traps
335 system.cpu.fetch.PendingQuiesceStallCycles 60 # Number of stall cycles due to pending quiesce instructions
336 system.cpu.fetch.IcacheWaitRetryStallCycles 747 # Number of stall cycles due to full MSHR
337 system.cpu.fetch.CacheLines 9135683 # Number of cache lines fetched
338 system.cpu.fetch.IcacheSquashes 451645 # Number of outstanding Icache misses that were squashed
339 system.cpu.fetch.ItlbSquashes 5364 # Number of outstanding ITLB misses that were squashed
340 system.cpu.fetch.rateDist::samples 446716128 # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::mean 1.893620 # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::stdev 3.051973 # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::0 281460190 63.01% 63.01% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::1 2138894 0.48% 63.49% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::2 72152839 16.15% 79.64% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::3 1576063 0.35% 79.99% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::4 2129707 0.48% 80.47% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::5 2325949 0.52% 80.99% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::6 1505469 0.34% 81.32% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::7 1859854 0.42% 81.74% # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::8 81567163 18.26% 100.00% # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
355 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.rateDist::total 446716128 # Number of instructions fetched each cycle (Total)
357 system.cpu.fetch.branchRate 0.193172 # Number of branch fetches per cycle
358 system.cpu.fetch.rate 0.954016 # Number of inst fetches per cycle
359 system.cpu.decode.IdleCycles 22817532 # Number of cycles decode is idle
360 system.cpu.decode.BlockedCycles 264818622 # Number of cycles decode is blocked
361 system.cpu.decode.RunCycles 150719822 # Number of cycles decode is running
362 system.cpu.decode.UnblockCycles 7418100 # Number of cycles decode is unblocking
363 system.cpu.decode.SquashCycles 942052 # Number of cycles decode is squashing
364 system.cpu.decode.DecodedInsts 837890793 # Number of instructions handled by decode
365 system.cpu.rename.SquashCycles 942052 # Number of cycles rename is squashing
366 system.cpu.rename.IdleCycles 25656597 # Number of cycles rename is idle
367 system.cpu.rename.BlockCycles 222831809 # Number of cycles rename is blocking
368 system.cpu.rename.serializeStallCycles 12884327 # count of cycles rename stalled for serializing inst
369 system.cpu.rename.RunCycles 154608390 # Number of cycles rename is running
370 system.cpu.rename.UnblockCycles 29792953 # Number of cycles rename is unblocking
371 system.cpu.rename.RenamedInsts 834381209 # Number of instructions processed by rename
372 system.cpu.rename.ROBFullEvents 449377 # Number of times rename has blocked due to ROB full
373 system.cpu.rename.IQFullEvents 12218260 # Number of times rename has blocked due to IQ full
374 system.cpu.rename.LQFullEvents 146025 # Number of times rename has blocked due to LQ full
375 system.cpu.rename.SQFullEvents 14738284 # Number of times rename has blocked due to SQ full
376 system.cpu.rename.RenamedOperands 996692347 # Number of destination operands rename has renamed
377 system.cpu.rename.RenameLookups 1812155414 # Number of register rename lookups that rename has made
378 system.cpu.rename.int_rename_lookups 1113986633 # Number of integer rename lookups
379 system.cpu.rename.fp_rename_lookups 357 # Number of floating rename lookups
380 system.cpu.rename.CommittedMaps 964101925 # Number of HB maps that are committed
381 system.cpu.rename.UndoneMaps 32590420 # Number of HB maps that are undone due to squashing
382 system.cpu.rename.serializingInsts 461964 # count of serializing insts renamed
383 system.cpu.rename.tempSerializingInsts 466029 # count of temporary serializing insts renamed
384 system.cpu.rename.skidInsts 38550499 # count of insts added to the skid buffer
385 system.cpu.memDep0.insertedLoads 17267645 # Number of loads inserted to the mem dependence unit.
386 system.cpu.memDep0.insertedStores 10120270 # Number of stores inserted to the mem dependence unit.
387 system.cpu.memDep0.conflictingLoads 1295034 # Number of conflicting loads.
388 system.cpu.memDep0.conflictingStores 1078818 # Number of conflicting stores.
389 system.cpu.iq.iqInstsAdded 828854264 # Number of instructions added to the IQ (excludes non-spec)
390 system.cpu.iq.iqNonSpecInstsAdded 1188467 # Number of non-speculative instructions added to the IQ
391 system.cpu.iq.iqInstsIssued 823634023 # Number of instructions issued
392 system.cpu.iq.iqSquashedInstsIssued 239226 # Number of squashed instructions issued
393 system.cpu.iq.iqSquashedInstsExamined 23863451 # Number of squashed instructions iterated over during squash; mainly for profiling
394 system.cpu.iq.iqSquashedOperandsExamined 35922872 # Number of squashed operands that are examined and possibly removed from graph
395 system.cpu.iq.iqSquashedNonSpecRemoved 148640 # Number of squashed non-spec instructions that were removed
396 system.cpu.iq.issued_per_cycle::samples 446716128 # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::mean 1.843753 # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::stdev 2.418621 # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::0 262749029 58.82% 58.82% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::1 13824325 3.09% 61.91% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::2 9784338 2.19% 64.10% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::3 7058515 1.58% 65.68% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::4 74344613 16.64% 82.33% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::5 4389971 0.98% 83.31% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::6 72797188 16.30% 99.60% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::7 1191150 0.27% 99.87% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::8 576999 0.13% 100.00% # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
411 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
412 system.cpu.iq.issued_per_cycle::total 446716128 # Number of insts issued each cycle
413 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
414 system.cpu.iq.fu_full::IntAlu 1965794 71.96% 71.96% # attempts to use FU when none available
415 system.cpu.iq.fu_full::IntMult 0 0.00% 71.96% # attempts to use FU when none available
416 system.cpu.iq.fu_full::IntDiv 0 0.00% 71.96% # attempts to use FU when none available
417 system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.96% # attempts to use FU when none available
420 system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available
421 system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available
422 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available
443 system.cpu.iq.fu_full::MemRead 607707 22.24% 94.20% # attempts to use FU when none available
444 system.cpu.iq.fu_full::MemWrite 158405 5.80% 100.00% # attempts to use FU when none available
445 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
446 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
447 system.cpu.iq.FU_type_0::No_OpClass 286388 0.03% 0.03% # Type of FU issued
448 system.cpu.iq.FU_type_0::IntAlu 795396124 96.57% 96.61% # Type of FU issued
449 system.cpu.iq.FU_type_0::IntMult 150331 0.02% 96.62% # Type of FU issued
450 system.cpu.iq.FU_type_0::IntDiv 127202 0.02% 96.64% # Type of FU issued
451 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatCvt 98 0.00% 96.64% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued
455 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued
456 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued
477 system.cpu.iq.FU_type_0::MemRead 18333764 2.23% 98.87% # Type of FU issued
478 system.cpu.iq.FU_type_0::MemWrite 9340116 1.13% 100.00% # Type of FU issued
479 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
480 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
481 system.cpu.iq.FU_type_0::total 823634023 # Type of FU issued
482 system.cpu.iq.rate 1.832926 # Inst issue rate
483 system.cpu.iq.fu_busy_cnt 2731906 # FU busy when requested
484 system.cpu.iq.fu_busy_rate 0.003317 # FU busy rate (busy events/executed inst)
485 system.cpu.iq.int_inst_queue_reads 2096954851 # Number of integer instruction queue reads
486 system.cpu.iq.int_inst_queue_writes 853918294 # Number of integer instruction queue writes
487 system.cpu.iq.int_inst_queue_wakeup_accesses 819080568 # Number of integer instruction queue wakeup accesses
488 system.cpu.iq.fp_inst_queue_reads 454 # Number of floating instruction queue reads
489 system.cpu.iq.fp_inst_queue_writes 494 # Number of floating instruction queue writes
490 system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses
491 system.cpu.iq.int_alu_accesses 826079323 # Number of integer alu accesses
492 system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses
493 system.cpu.iew.lsq.thread0.forwLoads 1864091 # Number of loads that had data forwarded from stores
494 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
495 system.cpu.iew.lsq.thread0.squashedLoads 3276332 # Number of loads squashed
496 system.cpu.iew.lsq.thread0.ignoredResponses 15288 # Number of memory responses ignored because the instruction is squashed
497 system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations
498 system.cpu.iew.lsq.thread0.squashedStores 1695886 # Number of stores squashed
499 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
500 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
501 system.cpu.iew.lsq.thread0.rescheduledLoads 2207587 # Number of loads that were rescheduled
502 system.cpu.iew.lsq.thread0.cacheBlocked 71306 # Number of times an access to memory failed due to the cache being blocked
503 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
504 system.cpu.iew.iewSquashCycles 942052 # Number of cycles IEW is squashing
505 system.cpu.iew.iewBlockCycles 204779875 # Number of cycles IEW is blocking
506 system.cpu.iew.iewUnblockCycles 9950427 # Number of cycles IEW is unblocking
507 system.cpu.iew.iewDispatchedInsts 830042731 # Number of instructions dispatched to IQ
508 system.cpu.iew.iewDispSquashedInsts 154301 # Number of squashed instructions skipped by dispatch
509 system.cpu.iew.iewDispLoadInsts 17267645 # Number of dispatched load instructions
510 system.cpu.iew.iewDispStoreInsts 10120270 # Number of dispatched store instructions
511 system.cpu.iew.iewDispNonSpecInsts 698404 # Number of dispatched non-speculative instructions
512 system.cpu.iew.iewIQFullEvents 395340 # Number of times the IQ has become full, causing a stall
513 system.cpu.iew.iewLSQFullEvents 8703386 # Number of times the LSQ has become full, causing a stall
514 system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations
515 system.cpu.iew.predictedTakenIncorrect 517416 # Number of branches that were predicted taken incorrectly
516 system.cpu.iew.predictedNotTakenIncorrect 531852 # Number of branches that were predicted not taken incorrectly
517 system.cpu.iew.branchMispredicts 1049268 # Number of branch mispredicts detected at execute
518 system.cpu.iew.iewExecutedInsts 822011733 # Number of executed instructions
519 system.cpu.iew.iewExecLoadInsts 17933627 # Number of load instructions executed
520 system.cpu.iew.iewExecSquashedInsts 1492341 # Number of squashed instructions skipped in execute
521 system.cpu.iew.exec_swp 0 # number of swp insts executed
522 system.cpu.iew.exec_nop 0 # number of nop insts executed
523 system.cpu.iew.exec_refs 27049256 # number of memory reference insts executed
524 system.cpu.iew.exec_branches 83240327 # Number of branches executed
525 system.cpu.iew.exec_stores 9115629 # Number of stores executed
526 system.cpu.iew.exec_rate 1.829315 # Inst execution rate
527 system.cpu.iew.wb_sent 821506514 # cumulative count of insts sent to commit
528 system.cpu.iew.wb_count 819080726 # cumulative count of insts written-back
529 system.cpu.iew.wb_producers 640638640 # num instructions producing a value
530 system.cpu.iew.wb_consumers 1049832937 # num instructions consuming a value
531 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
532 system.cpu.iew.wb_rate 1.822793 # insts written-back per cycle
533 system.cpu.iew.wb_fanout 0.610229 # average fanout of values written-back
534 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
535 system.cpu.commit.commitSquashedInsts 23734474 # The number of squashed insts skipped by commit
536 system.cpu.commit.commitNonSpecStalls 1039827 # The number of times commit has been forced to stall to communicate backwards
537 system.cpu.commit.branchMispredicts 910229 # The number of times a branch was mispredicted
538 system.cpu.commit.committed_per_cycle::samples 443141458 # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::mean 1.819237 # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::stdev 2.674506 # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::0 272292366 61.45% 61.45% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::1 11181272 2.52% 63.97% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::2 3605802 0.81% 64.78% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::3 74611152 16.84% 81.62% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::4 2465682 0.56% 82.18% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::5 1626284 0.37% 82.54% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::6 958421 0.22% 82.76% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::7 70995563 16.02% 98.78% # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::8 5404916 1.22% 100.00% # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
552 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
553 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
554 system.cpu.commit.committed_per_cycle::total 443141458 # Number of insts commited each cycle
555 system.cpu.commit.committedInsts 407858109 # Number of instructions committed
556 system.cpu.commit.committedOps 806179275 # Number of ops (including micro ops) committed
557 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
558 system.cpu.commit.refs 22415696 # Number of memory references committed
559 system.cpu.commit.loads 13991312 # Number of loads committed
560 system.cpu.commit.membars 468143 # Number of memory barriers committed
561 system.cpu.commit.branches 82176077 # Number of branches committed
562 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
563 system.cpu.commit.int_insts 735014201 # Number of committed integer instructions.
564 system.cpu.commit.function_calls 1155537 # Number of function calls committed.
565 system.cpu.commit.op_class_0::No_OpClass 171593 0.02% 0.02% # Class of committed instruction
566 system.cpu.commit.op_class_0::IntAlu 783328307 97.17% 97.19% # Class of committed instruction
567 system.cpu.commit.op_class_0::IntMult 144946 0.02% 97.20% # Class of committed instruction
568 system.cpu.commit.op_class_0::IntDiv 121298 0.02% 97.22% # Class of committed instruction
569 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
570 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
572 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
573 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
574 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
593 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
595 system.cpu.commit.op_class_0::MemRead 13988731 1.74% 98.96% # Class of committed instruction
596 system.cpu.commit.op_class_0::MemWrite 8424384 1.04% 100.00% # Class of committed instruction
597 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
598 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
599 system.cpu.commit.op_class_0::total 806179275 # Class of committed instruction
600 system.cpu.commit.bw_lim_events 5404916 # number cycles where commit BW limit reached
601 system.cpu.rob.rob_reads 1267572015 # The number of ROB reads
602 system.cpu.rob.rob_writes 1663421472 # The number of ROB writes
603 system.cpu.timesIdled 288126 # Number of times that the entire CPU went into an idle state and unscheduled itself
604 system.cpu.idleCycles 2638712 # Total number of cycles that the CPU has spent unscheduled due to idling
605 system.cpu.quiesceCycles 9810859930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
606 system.cpu.committedInsts 407858109 # Number of Instructions Simulated
607 system.cpu.committedOps 806179275 # Number of Ops (including micro ops) Simulated
608 system.cpu.cpi 1.101743 # CPI: Cycles Per Instruction
609 system.cpu.cpi_total 1.101743 # CPI: Total CPI of All Threads
610 system.cpu.ipc 0.907653 # IPC: Instructions Per Cycle
611 system.cpu.ipc_total 0.907653 # IPC: Total IPC of All Threads
612 system.cpu.int_regfile_reads 1091670765 # number of integer regfile reads
613 system.cpu.int_regfile_writes 655627629 # number of integer regfile writes
614 system.cpu.fp_regfile_reads 158 # number of floating regfile reads
615 system.cpu.cc_regfile_reads 416000684 # number of cc regfile reads
616 system.cpu.cc_regfile_writes 321879904 # number of cc regfile writes
617 system.cpu.misc_regfile_reads 265310647 # number of misc regfile reads
618 system.cpu.misc_regfile_writes 400047 # number of misc regfile writes
619 system.cpu.dcache.tags.replacements 1661478 # number of replacements
620 system.cpu.dcache.tags.tagsinuse 511.997539 # Cycle average of tags in use
621 system.cpu.dcache.tags.total_refs 19061070 # Total number of references to valid blocks.
622 system.cpu.dcache.tags.sampled_refs 1661990 # Sample count of references to valid blocks.
623 system.cpu.dcache.tags.avg_refs 11.468824 # Average number of references to valid blocks.
624 system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit.
625 system.cpu.dcache.tags.occ_blocks::cpu.data 511.997539 # Average occupied blocks per requestor
626 system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
627 system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
628 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
629 system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id
630 system.cpu.dcache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id
631 system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
632 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
633 system.cpu.dcache.tags.tag_accesses 88124232 # Number of tag accesses
634 system.cpu.dcache.tags.data_accesses 88124232 # Number of data accesses
635 system.cpu.dcache.ReadReq_hits::cpu.data 10914055 # number of ReadReq hits
636 system.cpu.dcache.ReadReq_hits::total 10914055 # number of ReadReq hits
637 system.cpu.dcache.WriteReq_hits::cpu.data 8079827 # number of WriteReq hits
638 system.cpu.dcache.WriteReq_hits::total 8079827 # number of WriteReq hits
639 system.cpu.dcache.SoftPFReq_hits::cpu.data 64080 # number of SoftPFReq hits
640 system.cpu.dcache.SoftPFReq_hits::total 64080 # number of SoftPFReq hits
641 system.cpu.dcache.demand_hits::cpu.data 18993882 # number of demand (read+write) hits
642 system.cpu.dcache.demand_hits::total 18993882 # number of demand (read+write) hits
643 system.cpu.dcache.overall_hits::cpu.data 19057962 # number of overall hits
644 system.cpu.dcache.overall_hits::total 19057962 # number of overall hits
645 system.cpu.dcache.ReadReq_misses::cpu.data 1815960 # number of ReadReq misses
646 system.cpu.dcache.ReadReq_misses::total 1815960 # number of ReadReq misses
647 system.cpu.dcache.WriteReq_misses::cpu.data 334906 # number of WriteReq misses
648 system.cpu.dcache.WriteReq_misses::total 334906 # number of WriteReq misses
649 system.cpu.dcache.SoftPFReq_misses::cpu.data 406730 # number of SoftPFReq misses
650 system.cpu.dcache.SoftPFReq_misses::total 406730 # number of SoftPFReq misses
651 system.cpu.dcache.demand_misses::cpu.data 2150866 # number of demand (read+write) misses
652 system.cpu.dcache.demand_misses::total 2150866 # number of demand (read+write) misses
653 system.cpu.dcache.overall_misses::cpu.data 2557596 # number of overall misses
654 system.cpu.dcache.overall_misses::total 2557596 # number of overall misses
655 system.cpu.dcache.ReadReq_miss_latency::cpu.data 27033028000 # number of ReadReq miss cycles
656 system.cpu.dcache.ReadReq_miss_latency::total 27033028000 # number of ReadReq miss cycles
657 system.cpu.dcache.WriteReq_miss_latency::cpu.data 13819339247 # number of WriteReq miss cycles
658 system.cpu.dcache.WriteReq_miss_latency::total 13819339247 # number of WriteReq miss cycles
659 system.cpu.dcache.demand_miss_latency::cpu.data 40852367247 # number of demand (read+write) miss cycles
660 system.cpu.dcache.demand_miss_latency::total 40852367247 # number of demand (read+write) miss cycles
661 system.cpu.dcache.overall_miss_latency::cpu.data 40852367247 # number of overall miss cycles
662 system.cpu.dcache.overall_miss_latency::total 40852367247 # number of overall miss cycles
663 system.cpu.dcache.ReadReq_accesses::cpu.data 12730015 # number of ReadReq accesses(hits+misses)
664 system.cpu.dcache.ReadReq_accesses::total 12730015 # number of ReadReq accesses(hits+misses)
665 system.cpu.dcache.WriteReq_accesses::cpu.data 8414733 # number of WriteReq accesses(hits+misses)
666 system.cpu.dcache.WriteReq_accesses::total 8414733 # number of WriteReq accesses(hits+misses)
667 system.cpu.dcache.SoftPFReq_accesses::cpu.data 470810 # number of SoftPFReq accesses(hits+misses)
668 system.cpu.dcache.SoftPFReq_accesses::total 470810 # number of SoftPFReq accesses(hits+misses)
669 system.cpu.dcache.demand_accesses::cpu.data 21144748 # number of demand (read+write) accesses
670 system.cpu.dcache.demand_accesses::total 21144748 # number of demand (read+write) accesses
671 system.cpu.dcache.overall_accesses::cpu.data 21615558 # number of overall (read+write) accesses
672 system.cpu.dcache.overall_accesses::total 21615558 # number of overall (read+write) accesses
673 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142652 # miss rate for ReadReq accesses
674 system.cpu.dcache.ReadReq_miss_rate::total 0.142652 # miss rate for ReadReq accesses
675 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039800 # miss rate for WriteReq accesses
676 system.cpu.dcache.WriteReq_miss_rate::total 0.039800 # miss rate for WriteReq accesses
677 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863894 # miss rate for SoftPFReq accesses
678 system.cpu.dcache.SoftPFReq_miss_rate::total 0.863894 # miss rate for SoftPFReq accesses
679 system.cpu.dcache.demand_miss_rate::cpu.data 0.101721 # miss rate for demand accesses
680 system.cpu.dcache.demand_miss_rate::total 0.101721 # miss rate for demand accesses
681 system.cpu.dcache.overall_miss_rate::cpu.data 0.118322 # miss rate for overall accesses
682 system.cpu.dcache.overall_miss_rate::total 0.118322 # miss rate for overall accesses
683 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14886.356528 # average ReadReq miss latency
684 system.cpu.dcache.ReadReq_avg_miss_latency::total 14886.356528 # average ReadReq miss latency
685 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41263.337316 # average WriteReq miss latency
686 system.cpu.dcache.WriteReq_avg_miss_latency::total 41263.337316 # average WriteReq miss latency
687 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18993.450660 # average overall miss latency
688 system.cpu.dcache.demand_avg_miss_latency::total 18993.450660 # average overall miss latency
689 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15972.955559 # average overall miss latency
690 system.cpu.dcache.overall_avg_miss_latency::total 15972.955559 # average overall miss latency
691 system.cpu.dcache.blocked_cycles::no_mshrs 469124 # number of cycles access was blocked
692 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693 system.cpu.dcache.blocked::no_mshrs 51580 # number of cycles access was blocked
694 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
695 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.095076 # average number of cycles each access was blocked
696 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697 system.cpu.dcache.fast_writes 0 # number of fast writes performed
698 system.cpu.dcache.cache_copies 0 # number of cache copies performed
699 system.cpu.dcache.writebacks::writebacks 1562865 # number of writebacks
700 system.cpu.dcache.writebacks::total 1562865 # number of writebacks
701 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845003 # number of ReadReq MSHR hits
702 system.cpu.dcache.ReadReq_mshr_hits::total 845003 # number of ReadReq MSHR hits
703 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44547 # number of WriteReq MSHR hits
704 system.cpu.dcache.WriteReq_mshr_hits::total 44547 # number of WriteReq MSHR hits
705 system.cpu.dcache.demand_mshr_hits::cpu.data 889550 # number of demand (read+write) MSHR hits
706 system.cpu.dcache.demand_mshr_hits::total 889550 # number of demand (read+write) MSHR hits
707 system.cpu.dcache.overall_mshr_hits::cpu.data 889550 # number of overall MSHR hits
708 system.cpu.dcache.overall_mshr_hits::total 889550 # number of overall MSHR hits
709 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970957 # number of ReadReq MSHR misses
710 system.cpu.dcache.ReadReq_mshr_misses::total 970957 # number of ReadReq MSHR misses
711 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290359 # number of WriteReq MSHR misses
712 system.cpu.dcache.WriteReq_mshr_misses::total 290359 # number of WriteReq MSHR misses
713 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403239 # number of SoftPFReq MSHR misses
714 system.cpu.dcache.SoftPFReq_mshr_misses::total 403239 # number of SoftPFReq MSHR misses
715 system.cpu.dcache.demand_mshr_misses::cpu.data 1261316 # number of demand (read+write) MSHR misses
716 system.cpu.dcache.demand_mshr_misses::total 1261316 # number of demand (read+write) MSHR misses
717 system.cpu.dcache.overall_mshr_misses::cpu.data 1664555 # number of overall MSHR misses
718 system.cpu.dcache.overall_mshr_misses::total 1664555 # number of overall MSHR misses
719 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable
720 system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable
721 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13875 # number of WriteReq MSHR uncacheable
722 system.cpu.dcache.WriteReq_mshr_uncacheable::total 13875 # number of WriteReq MSHR uncacheable
723 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616771 # number of overall MSHR uncacheable misses
724 system.cpu.dcache.overall_mshr_uncacheable_misses::total 616771 # number of overall MSHR uncacheable misses
725 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13333994500 # number of ReadReq MSHR miss cycles
726 system.cpu.dcache.ReadReq_mshr_miss_latency::total 13333994500 # number of ReadReq MSHR miss cycles
727 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12420799750 # number of WriteReq MSHR miss cycles
728 system.cpu.dcache.WriteReq_mshr_miss_latency::total 12420799750 # number of WriteReq MSHR miss cycles
729 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6058828500 # number of SoftPFReq MSHR miss cycles
730 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6058828500 # number of SoftPFReq MSHR miss cycles
731 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25754794250 # number of demand (read+write) MSHR miss cycles
732 system.cpu.dcache.demand_mshr_miss_latency::total 25754794250 # number of demand (read+write) MSHR miss cycles
733 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31813622750 # number of overall MSHR miss cycles
734 system.cpu.dcache.overall_mshr_miss_latency::total 31813622750 # number of overall MSHR miss cycles
735 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793670000 # number of ReadReq MSHR uncacheable cycles
736 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793670000 # number of ReadReq MSHR uncacheable cycles
737 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2615433000 # number of WriteReq MSHR uncacheable cycles
738 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2615433000 # number of WriteReq MSHR uncacheable cycles
739 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100409103000 # number of overall MSHR uncacheable cycles
740 system.cpu.dcache.overall_mshr_uncacheable_latency::total 100409103000 # number of overall MSHR uncacheable cycles
741 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076273 # mshr miss rate for ReadReq accesses
742 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076273 # mshr miss rate for ReadReq accesses
743 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034506 # mshr miss rate for WriteReq accesses
744 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034506 # mshr miss rate for WriteReq accesses
745 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.856479 # mshr miss rate for SoftPFReq accesses
746 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.856479 # mshr miss rate for SoftPFReq accesses
747 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059652 # mshr miss rate for demand accesses
748 system.cpu.dcache.demand_mshr_miss_rate::total 0.059652 # mshr miss rate for demand accesses
749 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077007 # mshr miss rate for overall accesses
750 system.cpu.dcache.overall_mshr_miss_rate::total 0.077007 # mshr miss rate for overall accesses
751 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13732.837294 # average ReadReq mshr miss latency
752 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13732.837294 # average ReadReq mshr miss latency
753 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42777.388509 # average WriteReq mshr miss latency
754 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42777.388509 # average WriteReq mshr miss latency
755 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15025.403049 # average SoftPFReq mshr miss latency
756 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15025.403049 # average SoftPFReq mshr miss latency
757 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20418.986400 # average overall mshr miss latency
758 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20418.986400 # average overall mshr miss latency
759 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19112.389047 # average overall mshr miss latency
760 system.cpu.dcache.overall_avg_mshr_miss_latency::total 19112.389047 # average overall mshr miss latency
761 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.533133 # average ReadReq mshr uncacheable latency
762 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.533133 # average ReadReq mshr uncacheable latency
763 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188499.675676 # average WriteReq mshr uncacheable latency
764 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188499.675676 # average WriteReq mshr uncacheable latency
765 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162798.028766 # average overall mshr uncacheable latency
766 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162798.028766 # average overall mshr uncacheable latency
767 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
768 system.cpu.dtb_walker_cache.tags.replacements 72618 # number of replacements
769 system.cpu.dtb_walker_cache.tags.tagsinuse 14.793557 # Cycle average of tags in use
770 system.cpu.dtb_walker_cache.tags.total_refs 113213 # Total number of references to valid blocks.
771 system.cpu.dtb_walker_cache.tags.sampled_refs 72633 # Sample count of references to valid blocks.
772 system.cpu.dtb_walker_cache.tags.avg_refs 1.558699 # Average number of references to valid blocks.
773 system.cpu.dtb_walker_cache.tags.warmup_cycle 5097094340500 # Cycle when the warmup percentage was hit.
774 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.793557 # Average occupied blocks per requestor
775 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.924597 # Average percentage of cache occupancy
776 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.924597 # Average percentage of cache occupancy
777 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
778 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
779 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
780 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
781 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
782 system.cpu.dtb_walker_cache.tags.tag_accesses 447394 # Number of tag accesses
783 system.cpu.dtb_walker_cache.tags.data_accesses 447394 # Number of data accesses
784 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113219 # number of ReadReq hits
785 system.cpu.dtb_walker_cache.ReadReq_hits::total 113219 # number of ReadReq hits
786 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113219 # number of demand (read+write) hits
787 system.cpu.dtb_walker_cache.demand_hits::total 113219 # number of demand (read+write) hits
788 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113219 # number of overall hits
789 system.cpu.dtb_walker_cache.overall_hits::total 113219 # number of overall hits
790 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 73652 # number of ReadReq misses
791 system.cpu.dtb_walker_cache.ReadReq_misses::total 73652 # number of ReadReq misses
792 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 73652 # number of demand (read+write) misses
793 system.cpu.dtb_walker_cache.demand_misses::total 73652 # number of demand (read+write) misses
794 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 73652 # number of overall misses
795 system.cpu.dtb_walker_cache.overall_misses::total 73652 # number of overall misses
796 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 910717000 # number of ReadReq miss cycles
797 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 910717000 # number of ReadReq miss cycles
798 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 910717000 # number of demand (read+write) miss cycles
799 system.cpu.dtb_walker_cache.demand_miss_latency::total 910717000 # number of demand (read+write) miss cycles
800 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 910717000 # number of overall miss cycles
801 system.cpu.dtb_walker_cache.overall_miss_latency::total 910717000 # number of overall miss cycles
802 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 186871 # number of ReadReq accesses(hits+misses)
803 system.cpu.dtb_walker_cache.ReadReq_accesses::total 186871 # number of ReadReq accesses(hits+misses)
804 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 186871 # number of demand (read+write) accesses
805 system.cpu.dtb_walker_cache.demand_accesses::total 186871 # number of demand (read+write) accesses
806 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 186871 # number of overall (read+write) accesses
807 system.cpu.dtb_walker_cache.overall_accesses::total 186871 # number of overall (read+write) accesses
808 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394133 # miss rate for ReadReq accesses
809 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394133 # miss rate for ReadReq accesses
810 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394133 # miss rate for demand accesses
811 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394133 # miss rate for demand accesses
812 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394133 # miss rate for overall accesses
813 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394133 # miss rate for overall accesses
814 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12365.136045 # average ReadReq miss latency
815 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12365.136045 # average ReadReq miss latency
816 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12365.136045 # average overall miss latency
817 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12365.136045 # average overall miss latency
818 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12365.136045 # average overall miss latency
819 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12365.136045 # average overall miss latency
820 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
821 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
822 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
823 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
824 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
825 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
826 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
827 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
828 system.cpu.dtb_walker_cache.writebacks::writebacks 18815 # number of writebacks
829 system.cpu.dtb_walker_cache.writebacks::total 18815 # number of writebacks
830 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 73652 # number of ReadReq MSHR misses
831 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 73652 # number of ReadReq MSHR misses
832 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 73652 # number of demand (read+write) MSHR misses
833 system.cpu.dtb_walker_cache.demand_mshr_misses::total 73652 # number of demand (read+write) MSHR misses
834 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 73652 # number of overall MSHR misses
835 system.cpu.dtb_walker_cache.overall_mshr_misses::total 73652 # number of overall MSHR misses
836 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 837065000 # number of ReadReq MSHR miss cycles
837 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 837065000 # number of ReadReq MSHR miss cycles
838 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 837065000 # number of demand (read+write) MSHR miss cycles
839 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 837065000 # number of demand (read+write) MSHR miss cycles
840 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 837065000 # number of overall MSHR miss cycles
841 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 837065000 # number of overall MSHR miss cycles
842 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for ReadReq accesses
843 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394133 # mshr miss rate for ReadReq accesses
844 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for demand accesses
845 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394133 # mshr miss rate for demand accesses
846 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for overall accesses
847 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394133 # mshr miss rate for overall accesses
848 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average ReadReq mshr miss latency
849 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11365.136045 # average ReadReq mshr miss latency
850 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average overall mshr miss latency
851 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11365.136045 # average overall mshr miss latency
852 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average overall mshr miss latency
853 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11365.136045 # average overall mshr miss latency
854 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
855 system.cpu.icache.tags.replacements 991040 # number of replacements
856 system.cpu.icache.tags.tagsinuse 509.607437 # Cycle average of tags in use
857 system.cpu.icache.tags.total_refs 8073267 # Total number of references to valid blocks.
858 system.cpu.icache.tags.sampled_refs 991552 # Sample count of references to valid blocks.
859 system.cpu.icache.tags.avg_refs 8.142051 # Average number of references to valid blocks.
860 system.cpu.icache.tags.warmup_cycle 147914027500 # Cycle when the warmup percentage was hit.
861 system.cpu.icache.tags.occ_blocks::cpu.inst 509.607437 # Average occupied blocks per requestor
862 system.cpu.icache.tags.occ_percent::cpu.inst 0.995327 # Average percentage of cache occupancy
863 system.cpu.icache.tags.occ_percent::total 0.995327 # Average percentage of cache occupancy
864 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
865 system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
866 system.cpu.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
867 system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
868 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
869 system.cpu.icache.tags.tag_accesses 10127588 # Number of tag accesses
870 system.cpu.icache.tags.data_accesses 10127588 # Number of data accesses
871 system.cpu.icache.ReadReq_hits::cpu.inst 8073267 # number of ReadReq hits
872 system.cpu.icache.ReadReq_hits::total 8073267 # number of ReadReq hits
873 system.cpu.icache.demand_hits::cpu.inst 8073267 # number of demand (read+write) hits
874 system.cpu.icache.demand_hits::total 8073267 # number of demand (read+write) hits
875 system.cpu.icache.overall_hits::cpu.inst 8073267 # number of overall hits
876 system.cpu.icache.overall_hits::total 8073267 # number of overall hits
877 system.cpu.icache.ReadReq_misses::cpu.inst 1062411 # number of ReadReq misses
878 system.cpu.icache.ReadReq_misses::total 1062411 # number of ReadReq misses
879 system.cpu.icache.demand_misses::cpu.inst 1062411 # number of demand (read+write) misses
880 system.cpu.icache.demand_misses::total 1062411 # number of demand (read+write) misses
881 system.cpu.icache.overall_misses::cpu.inst 1062411 # number of overall misses
882 system.cpu.icache.overall_misses::total 1062411 # number of overall misses
883 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14792091486 # number of ReadReq miss cycles
884 system.cpu.icache.ReadReq_miss_latency::total 14792091486 # number of ReadReq miss cycles
885 system.cpu.icache.demand_miss_latency::cpu.inst 14792091486 # number of demand (read+write) miss cycles
886 system.cpu.icache.demand_miss_latency::total 14792091486 # number of demand (read+write) miss cycles
887 system.cpu.icache.overall_miss_latency::cpu.inst 14792091486 # number of overall miss cycles
888 system.cpu.icache.overall_miss_latency::total 14792091486 # number of overall miss cycles
889 system.cpu.icache.ReadReq_accesses::cpu.inst 9135678 # number of ReadReq accesses(hits+misses)
890 system.cpu.icache.ReadReq_accesses::total 9135678 # number of ReadReq accesses(hits+misses)
891 system.cpu.icache.demand_accesses::cpu.inst 9135678 # number of demand (read+write) accesses
892 system.cpu.icache.demand_accesses::total 9135678 # number of demand (read+write) accesses
893 system.cpu.icache.overall_accesses::cpu.inst 9135678 # number of overall (read+write) accesses
894 system.cpu.icache.overall_accesses::total 9135678 # number of overall (read+write) accesses
895 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116293 # miss rate for ReadReq accesses
896 system.cpu.icache.ReadReq_miss_rate::total 0.116293 # miss rate for ReadReq accesses
897 system.cpu.icache.demand_miss_rate::cpu.inst 0.116293 # miss rate for demand accesses
898 system.cpu.icache.demand_miss_rate::total 0.116293 # miss rate for demand accesses
899 system.cpu.icache.overall_miss_rate::cpu.inst 0.116293 # miss rate for overall accesses
900 system.cpu.icache.overall_miss_rate::total 0.116293 # miss rate for overall accesses
901 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.134725 # average ReadReq miss latency
902 system.cpu.icache.ReadReq_avg_miss_latency::total 13923.134725 # average ReadReq miss latency
903 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.134725 # average overall miss latency
904 system.cpu.icache.demand_avg_miss_latency::total 13923.134725 # average overall miss latency
905 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.134725 # average overall miss latency
906 system.cpu.icache.overall_avg_miss_latency::total 13923.134725 # average overall miss latency
907 system.cpu.icache.blocked_cycles::no_mshrs 7978 # number of cycles access was blocked
908 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
909 system.cpu.icache.blocked::no_mshrs 382 # number of cycles access was blocked
910 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
911 system.cpu.icache.avg_blocked_cycles::no_mshrs 20.884817 # average number of cycles each access was blocked
912 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
913 system.cpu.icache.fast_writes 0 # number of fast writes performed
914 system.cpu.icache.cache_copies 0 # number of cache copies performed
915 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70501 # number of ReadReq MSHR hits
916 system.cpu.icache.ReadReq_mshr_hits::total 70501 # number of ReadReq MSHR hits
917 system.cpu.icache.demand_mshr_hits::cpu.inst 70501 # number of demand (read+write) MSHR hits
918 system.cpu.icache.demand_mshr_hits::total 70501 # number of demand (read+write) MSHR hits
919 system.cpu.icache.overall_mshr_hits::cpu.inst 70501 # number of overall MSHR hits
920 system.cpu.icache.overall_mshr_hits::total 70501 # number of overall MSHR hits
921 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991910 # number of ReadReq MSHR misses
922 system.cpu.icache.ReadReq_mshr_misses::total 991910 # number of ReadReq MSHR misses
923 system.cpu.icache.demand_mshr_misses::cpu.inst 991910 # number of demand (read+write) MSHR misses
924 system.cpu.icache.demand_mshr_misses::total 991910 # number of demand (read+write) MSHR misses
925 system.cpu.icache.overall_mshr_misses::cpu.inst 991910 # number of overall MSHR misses
926 system.cpu.icache.overall_mshr_misses::total 991910 # number of overall MSHR misses
927 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13114232487 # number of ReadReq MSHR miss cycles
928 system.cpu.icache.ReadReq_mshr_miss_latency::total 13114232487 # number of ReadReq MSHR miss cycles
929 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13114232487 # number of demand (read+write) MSHR miss cycles
930 system.cpu.icache.demand_mshr_miss_latency::total 13114232487 # number of demand (read+write) MSHR miss cycles
931 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13114232487 # number of overall MSHR miss cycles
932 system.cpu.icache.overall_mshr_miss_latency::total 13114232487 # number of overall MSHR miss cycles
933 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for ReadReq accesses
934 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108575 # mshr miss rate for ReadReq accesses
935 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for demand accesses
936 system.cpu.icache.demand_mshr_miss_rate::total 0.108575 # mshr miss rate for demand accesses
937 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for overall accesses
938 system.cpu.icache.overall_mshr_miss_rate::total 0.108575 # mshr miss rate for overall accesses
939 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13221.191930 # average ReadReq mshr miss latency
940 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13221.191930 # average ReadReq mshr miss latency
941 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13221.191930 # average overall mshr miss latency
942 system.cpu.icache.demand_avg_mshr_miss_latency::total 13221.191930 # average overall mshr miss latency
943 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13221.191930 # average overall mshr miss latency
944 system.cpu.icache.overall_avg_mshr_miss_latency::total 13221.191930 # average overall mshr miss latency
945 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
946 system.cpu.itb_walker_cache.tags.replacements 15565 # number of replacements
947 system.cpu.itb_walker_cache.tags.tagsinuse 6.022675 # Cycle average of tags in use
948 system.cpu.itb_walker_cache.tags.total_refs 26231 # Total number of references to valid blocks.
949 system.cpu.itb_walker_cache.tags.sampled_refs 15578 # Sample count of references to valid blocks.
950 system.cpu.itb_walker_cache.tags.avg_refs 1.683849 # Average number of references to valid blocks.
951 system.cpu.itb_walker_cache.tags.warmup_cycle 5102115273500 # Cycle when the warmup percentage was hit.
952 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022675 # Average occupied blocks per requestor
953 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376417 # Average percentage of cache occupancy
954 system.cpu.itb_walker_cache.tags.occ_percent::total 0.376417 # Average percentage of cache occupancy
955 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
956 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
957 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
958 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
959 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
960 system.cpu.itb_walker_cache.tags.tag_accesses 101828 # Number of tag accesses
961 system.cpu.itb_walker_cache.tags.data_accesses 101828 # Number of data accesses
962 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26240 # number of ReadReq hits
963 system.cpu.itb_walker_cache.ReadReq_hits::total 26240 # number of ReadReq hits
964 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
965 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
966 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26242 # number of demand (read+write) hits
967 system.cpu.itb_walker_cache.demand_hits::total 26242 # number of demand (read+write) hits
968 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26242 # number of overall hits
969 system.cpu.itb_walker_cache.overall_hits::total 26242 # number of overall hits
970 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16448 # number of ReadReq misses
971 system.cpu.itb_walker_cache.ReadReq_misses::total 16448 # number of ReadReq misses
972 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16448 # number of demand (read+write) misses
973 system.cpu.itb_walker_cache.demand_misses::total 16448 # number of demand (read+write) misses
974 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16448 # number of overall misses
975 system.cpu.itb_walker_cache.overall_misses::total 16448 # number of overall misses
976 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193358500 # number of ReadReq miss cycles
977 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193358500 # number of ReadReq miss cycles
978 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193358500 # number of demand (read+write) miss cycles
979 system.cpu.itb_walker_cache.demand_miss_latency::total 193358500 # number of demand (read+write) miss cycles
980 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193358500 # number of overall miss cycles
981 system.cpu.itb_walker_cache.overall_miss_latency::total 193358500 # number of overall miss cycles
982 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42688 # number of ReadReq accesses(hits+misses)
983 system.cpu.itb_walker_cache.ReadReq_accesses::total 42688 # number of ReadReq accesses(hits+misses)
984 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
985 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
986 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42690 # number of demand (read+write) accesses
987 system.cpu.itb_walker_cache.demand_accesses::total 42690 # number of demand (read+write) accesses
988 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42690 # number of overall (read+write) accesses
989 system.cpu.itb_walker_cache.overall_accesses::total 42690 # number of overall (read+write) accesses
990 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.385307 # miss rate for ReadReq accesses
991 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.385307 # miss rate for ReadReq accesses
992 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.385289 # miss rate for demand accesses
993 system.cpu.itb_walker_cache.demand_miss_rate::total 0.385289 # miss rate for demand accesses
994 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.385289 # miss rate for overall accesses
995 system.cpu.itb_walker_cache.overall_miss_rate::total 0.385289 # miss rate for overall accesses
996 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11755.745379 # average ReadReq miss latency
997 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11755.745379 # average ReadReq miss latency
998 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11755.745379 # average overall miss latency
999 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11755.745379 # average overall miss latency
1000 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11755.745379 # average overall miss latency
1001 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11755.745379 # average overall miss latency
1002 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1003 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1004 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1005 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1006 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1007 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1008 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1009 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1010 system.cpu.itb_walker_cache.writebacks::writebacks 3018 # number of writebacks
1011 system.cpu.itb_walker_cache.writebacks::total 3018 # number of writebacks
1012 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16448 # number of ReadReq MSHR misses
1013 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16448 # number of ReadReq MSHR misses
1014 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16448 # number of demand (read+write) MSHR misses
1015 system.cpu.itb_walker_cache.demand_mshr_misses::total 16448 # number of demand (read+write) MSHR misses
1016 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16448 # number of overall MSHR misses
1017 system.cpu.itb_walker_cache.overall_mshr_misses::total 16448 # number of overall MSHR misses
1018 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 176910500 # number of ReadReq MSHR miss cycles
1019 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 176910500 # number of ReadReq MSHR miss cycles
1020 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 176910500 # number of demand (read+write) MSHR miss cycles
1021 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 176910500 # number of demand (read+write) MSHR miss cycles
1022 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 176910500 # number of overall MSHR miss cycles
1023 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 176910500 # number of overall MSHR miss cycles
1024 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.385307 # mshr miss rate for ReadReq accesses
1025 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.385307 # mshr miss rate for ReadReq accesses
1026 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.385289 # mshr miss rate for demand accesses
1027 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.385289 # mshr miss rate for demand accesses
1028 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.385289 # mshr miss rate for overall accesses
1029 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.385289 # mshr miss rate for overall accesses
1030 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average ReadReq mshr miss latency
1031 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10755.745379 # average ReadReq mshr miss latency
1032 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average overall mshr miss latency
1033 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10755.745379 # average overall mshr miss latency
1034 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average overall mshr miss latency
1035 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10755.745379 # average overall mshr miss latency
1036 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1037 system.cpu.l2cache.tags.replacements 112892 # number of replacements
1038 system.cpu.l2cache.tags.tagsinuse 64819.691770 # Cycle average of tags in use
1039 system.cpu.l2cache.tags.total_refs 4938747 # Total number of references to valid blocks.
1040 system.cpu.l2cache.tags.sampled_refs 176773 # Sample count of references to valid blocks.
1041 system.cpu.l2cache.tags.avg_refs 27.938356 # Average number of references to valid blocks.
1042 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1043 system.cpu.l2cache.tags.occ_blocks::writebacks 50529.309735 # Average occupied blocks per requestor
1044 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 20.322898 # Average occupied blocks per requestor
1045 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.136173 # Average occupied blocks per requestor
1046 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3138.561208 # Average occupied blocks per requestor
1047 system.cpu.l2cache.tags.occ_blocks::cpu.data 11131.361756 # Average occupied blocks per requestor
1048 system.cpu.l2cache.tags.occ_percent::writebacks 0.771016 # Average percentage of cache occupancy
1049 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000310 # Average percentage of cache occupancy
1050 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1051 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047891 # Average percentage of cache occupancy
1052 system.cpu.l2cache.tags.occ_percent::cpu.data 0.169851 # Average percentage of cache occupancy
1053 system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy
1054 system.cpu.l2cache.tags.occ_task_id_blocks::1024 63881 # Occupied blocks per task id
1055 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
1056 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id
1057 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id
1058 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id
1059 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54573 # Occupied blocks per task id
1060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974747 # Percentage of cache occupancy per task id
1061 system.cpu.l2cache.tags.tag_accesses 43864381 # Number of tag accesses
1062 system.cpu.l2cache.tags.data_accesses 43864381 # Number of data accesses
1063 system.cpu.l2cache.Writeback_hits::writebacks 1584698 # number of Writeback hits
1064 system.cpu.l2cache.Writeback_hits::total 1584698 # number of Writeback hits
1065 system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits
1066 system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits
1067 system.cpu.l2cache.ReadExReq_hits::cpu.data 154215 # number of ReadExReq hits
1068 system.cpu.l2cache.ReadExReq_hits::total 154215 # number of ReadExReq hits
1069 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 975190 # number of ReadCleanReq hits
1070 system.cpu.l2cache.ReadCleanReq_hits::total 975190 # number of ReadCleanReq hits
1071 system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 67279 # number of ReadSharedReq hits
1072 system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13917 # number of ReadSharedReq hits
1073 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1337816 # number of ReadSharedReq hits
1074 system.cpu.l2cache.ReadSharedReq_hits::total 1419012 # number of ReadSharedReq hits
1075 system.cpu.l2cache.demand_hits::cpu.dtb.walker 67279 # number of demand (read+write) hits
1076 system.cpu.l2cache.demand_hits::cpu.itb.walker 13917 # number of demand (read+write) hits
1077 system.cpu.l2cache.demand_hits::cpu.inst 975190 # number of demand (read+write) hits
1078 system.cpu.l2cache.demand_hits::cpu.data 1492031 # number of demand (read+write) hits
1079 system.cpu.l2cache.demand_hits::total 2548417 # number of demand (read+write) hits
1080 system.cpu.l2cache.overall_hits::cpu.dtb.walker 67279 # number of overall hits
1081 system.cpu.l2cache.overall_hits::cpu.itb.walker 13917 # number of overall hits
1082 system.cpu.l2cache.overall_hits::cpu.inst 975190 # number of overall hits
1083 system.cpu.l2cache.overall_hits::cpu.data 1492031 # number of overall hits
1084 system.cpu.l2cache.overall_hits::total 2548417 # number of overall hits
1085 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1787 # number of UpgradeReq misses
1086 system.cpu.l2cache.UpgradeReq_misses::total 1787 # number of UpgradeReq misses
1087 system.cpu.l2cache.ReadExReq_misses::cpu.data 133737 # number of ReadExReq misses
1088 system.cpu.l2cache.ReadExReq_misses::total 133737 # number of ReadExReq misses
1089 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16323 # number of ReadCleanReq misses
1090 system.cpu.l2cache.ReadCleanReq_misses::total 16323 # number of ReadCleanReq misses
1091 system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 67 # number of ReadSharedReq misses
1092 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
1093 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35675 # number of ReadSharedReq misses
1094 system.cpu.l2cache.ReadSharedReq_misses::total 35747 # number of ReadSharedReq misses
1095 system.cpu.l2cache.demand_misses::cpu.dtb.walker 67 # number of demand (read+write) misses
1096 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1097 system.cpu.l2cache.demand_misses::cpu.inst 16323 # number of demand (read+write) misses
1098 system.cpu.l2cache.demand_misses::cpu.data 169412 # number of demand (read+write) misses
1099 system.cpu.l2cache.demand_misses::total 185807 # number of demand (read+write) misses
1100 system.cpu.l2cache.overall_misses::cpu.dtb.walker 67 # number of overall misses
1101 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1102 system.cpu.l2cache.overall_misses::cpu.inst 16323 # number of overall misses
1103 system.cpu.l2cache.overall_misses::cpu.data 169412 # number of overall misses
1104 system.cpu.l2cache.overall_misses::total 185807 # number of overall misses
1105 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23917000 # number of UpgradeReq miss cycles
1106 system.cpu.l2cache.UpgradeReq_miss_latency::total 23917000 # number of UpgradeReq miss cycles
1107 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10298204500 # number of ReadExReq miss cycles
1108 system.cpu.l2cache.ReadExReq_miss_latency::total 10298204500 # number of ReadExReq miss cycles
1109 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1359330500 # number of ReadCleanReq miss cycles
1110 system.cpu.l2cache.ReadCleanReq_miss_latency::total 1359330500 # number of ReadCleanReq miss cycles
1111 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 6177500 # number of ReadSharedReq miss cycles
1112 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 415000 # number of ReadSharedReq miss cycles
1113 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3065419500 # number of ReadSharedReq miss cycles
1114 system.cpu.l2cache.ReadSharedReq_miss_latency::total 3072012000 # number of ReadSharedReq miss cycles
1115 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6177500 # number of demand (read+write) miss cycles
1116 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 415000 # number of demand (read+write) miss cycles
1117 system.cpu.l2cache.demand_miss_latency::cpu.inst 1359330500 # number of demand (read+write) miss cycles
1118 system.cpu.l2cache.demand_miss_latency::cpu.data 13363624000 # number of demand (read+write) miss cycles
1119 system.cpu.l2cache.demand_miss_latency::total 14729547000 # number of demand (read+write) miss cycles
1120 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6177500 # number of overall miss cycles
1121 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 415000 # number of overall miss cycles
1122 system.cpu.l2cache.overall_miss_latency::cpu.inst 1359330500 # number of overall miss cycles
1123 system.cpu.l2cache.overall_miss_latency::cpu.data 13363624000 # number of overall miss cycles
1124 system.cpu.l2cache.overall_miss_latency::total 14729547000 # number of overall miss cycles
1125 system.cpu.l2cache.Writeback_accesses::writebacks 1584698 # number of Writeback accesses(hits+misses)
1126 system.cpu.l2cache.Writeback_accesses::total 1584698 # number of Writeback accesses(hits+misses)
1127 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2097 # number of UpgradeReq accesses(hits+misses)
1128 system.cpu.l2cache.UpgradeReq_accesses::total 2097 # number of UpgradeReq accesses(hits+misses)
1129 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287952 # number of ReadExReq accesses(hits+misses)
1130 system.cpu.l2cache.ReadExReq_accesses::total 287952 # number of ReadExReq accesses(hits+misses)
1131 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 991513 # number of ReadCleanReq accesses(hits+misses)
1132 system.cpu.l2cache.ReadCleanReq_accesses::total 991513 # number of ReadCleanReq accesses(hits+misses)
1133 system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 67346 # number of ReadSharedReq accesses(hits+misses)
1134 system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13922 # number of ReadSharedReq accesses(hits+misses)
1135 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1373491 # number of ReadSharedReq accesses(hits+misses)
1136 system.cpu.l2cache.ReadSharedReq_accesses::total 1454759 # number of ReadSharedReq accesses(hits+misses)
1137 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67346 # number of demand (read+write) accesses
1138 system.cpu.l2cache.demand_accesses::cpu.itb.walker 13922 # number of demand (read+write) accesses
1139 system.cpu.l2cache.demand_accesses::cpu.inst 991513 # number of demand (read+write) accesses
1140 system.cpu.l2cache.demand_accesses::cpu.data 1661443 # number of demand (read+write) accesses
1141 system.cpu.l2cache.demand_accesses::total 2734224 # number of demand (read+write) accesses
1142 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67346 # number of overall (read+write) accesses
1143 system.cpu.l2cache.overall_accesses::cpu.itb.walker 13922 # number of overall (read+write) accesses
1144 system.cpu.l2cache.overall_accesses::cpu.inst 991513 # number of overall (read+write) accesses
1145 system.cpu.l2cache.overall_accesses::cpu.data 1661443 # number of overall (read+write) accesses
1146 system.cpu.l2cache.overall_accesses::total 2734224 # number of overall (read+write) accesses
1147 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.852170 # miss rate for UpgradeReq accesses
1148 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.852170 # miss rate for UpgradeReq accesses
1149 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464442 # miss rate for ReadExReq accesses
1150 system.cpu.l2cache.ReadExReq_miss_rate::total 0.464442 # miss rate for ReadExReq accesses
1151 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016463 # miss rate for ReadCleanReq accesses
1152 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016463 # miss rate for ReadCleanReq accesses
1153 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000995 # miss rate for ReadSharedReq accesses
1154 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000359 # miss rate for ReadSharedReq accesses
1155 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.025974 # miss rate for ReadSharedReq accesses
1156 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024572 # miss rate for ReadSharedReq accesses
1157 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000995 # miss rate for demand accesses
1158 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000359 # miss rate for demand accesses
1159 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016463 # miss rate for demand accesses
1160 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101967 # miss rate for demand accesses
1161 system.cpu.l2cache.demand_miss_rate::total 0.067956 # miss rate for demand accesses
1162 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000995 # miss rate for overall accesses
1163 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000359 # miss rate for overall accesses
1164 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016463 # miss rate for overall accesses
1165 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101967 # miss rate for overall accesses
1166 system.cpu.l2cache.overall_miss_rate::total 0.067956 # miss rate for overall accesses
1167 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13383.883604 # average UpgradeReq miss latency
1168 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13383.883604 # average UpgradeReq miss latency
1169 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77003.405939 # average ReadExReq miss latency
1170 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77003.405939 # average ReadExReq miss latency
1171 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83277.001777 # average ReadCleanReq miss latency
1172 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83277.001777 # average ReadCleanReq miss latency
1173 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 92201.492537 # average ReadSharedReq miss latency
1174 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadSharedReq miss latency
1175 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85926.264891 # average ReadSharedReq miss latency
1176 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85937.617143 # average ReadSharedReq miss latency
1177 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92201.492537 # average overall miss latency
1178 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
1179 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83277.001777 # average overall miss latency
1180 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78882.393219 # average overall miss latency
1181 system.cpu.l2cache.demand_avg_miss_latency::total 79273.369679 # average overall miss latency
1182 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92201.492537 # average overall miss latency
1183 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
1184 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83277.001777 # average overall miss latency
1185 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78882.393219 # average overall miss latency
1186 system.cpu.l2cache.overall_avg_miss_latency::total 79273.369679 # average overall miss latency
1187 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1188 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1189 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1190 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1191 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1192 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1193 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1194 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1195 system.cpu.l2cache.writebacks::writebacks 103070 # number of writebacks
1196 system.cpu.l2cache.writebacks::total 103070 # number of writebacks
1197 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
1198 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1199 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits
1200 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits
1201 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1202 system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
1203 system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
1204 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1205 system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
1206 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
1207 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 90 # number of CleanEvict MSHR misses
1208 system.cpu.l2cache.CleanEvict_mshr_misses::total 90 # number of CleanEvict MSHR misses
1209 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1787 # number of UpgradeReq MSHR misses
1210 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1787 # number of UpgradeReq MSHR misses
1211 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133737 # number of ReadExReq MSHR misses
1212 system.cpu.l2cache.ReadExReq_mshr_misses::total 133737 # number of ReadExReq MSHR misses
1213 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16321 # number of ReadCleanReq MSHR misses
1214 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16321 # number of ReadCleanReq MSHR misses
1215 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 67 # number of ReadSharedReq MSHR misses
1216 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
1217 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35671 # number of ReadSharedReq MSHR misses
1218 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35743 # number of ReadSharedReq MSHR misses
1219 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 67 # number of demand (read+write) MSHR misses
1220 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1221 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16321 # number of demand (read+write) MSHR misses
1222 system.cpu.l2cache.demand_mshr_misses::cpu.data 169408 # number of demand (read+write) MSHR misses
1223 system.cpu.l2cache.demand_mshr_misses::total 185801 # number of demand (read+write) MSHR misses
1224 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 67 # number of overall MSHR misses
1225 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1226 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16321 # number of overall MSHR misses
1227 system.cpu.l2cache.overall_mshr_misses::cpu.data 169408 # number of overall MSHR misses
1228 system.cpu.l2cache.overall_mshr_misses::total 185801 # number of overall MSHR misses
1229 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable
1230 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable
1231 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13875 # number of WriteReq MSHR uncacheable
1232 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13875 # number of WriteReq MSHR uncacheable
1233 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616771 # number of overall MSHR uncacheable misses
1234 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616771 # number of overall MSHR uncacheable misses
1235 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37875000 # number of UpgradeReq MSHR miss cycles
1236 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37875000 # number of UpgradeReq MSHR miss cycles
1237 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8960834500 # number of ReadExReq MSHR miss cycles
1238 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8960834500 # number of ReadExReq MSHR miss cycles
1239 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1195971500 # number of ReadCleanReq MSHR miss cycles
1240 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1195971500 # number of ReadCleanReq MSHR miss cycles
1241 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 5507500 # number of ReadSharedReq MSHR miss cycles
1242 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 365000 # number of ReadSharedReq MSHR miss cycles
1243 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2711142000 # number of ReadSharedReq MSHR miss cycles
1244 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2717014500 # number of ReadSharedReq MSHR miss cycles
1245 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5507500 # number of demand (read+write) MSHR miss cycles
1246 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) MSHR miss cycles
1247 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1195971500 # number of demand (read+write) MSHR miss cycles
1248 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11671976500 # number of demand (read+write) MSHR miss cycles
1249 system.cpu.l2cache.demand_mshr_miss_latency::total 12873820500 # number of demand (read+write) MSHR miss cycles
1250 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5507500 # number of overall MSHR miss cycles
1251 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 365000 # number of overall MSHR miss cycles
1252 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1195971500 # number of overall MSHR miss cycles
1253 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11671976500 # number of overall MSHR miss cycles
1254 system.cpu.l2cache.overall_mshr_miss_latency::total 12873820500 # number of overall MSHR miss cycles
1255 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257461500 # number of ReadReq MSHR uncacheable cycles
1256 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257461500 # number of ReadReq MSHR uncacheable cycles
1257 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2455867500 # number of WriteReq MSHR uncacheable cycles
1258 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2455867500 # number of WriteReq MSHR uncacheable cycles
1259 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92713329000 # number of overall MSHR uncacheable cycles
1260 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92713329000 # number of overall MSHR uncacheable cycles
1261 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1262 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1263 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.852170 # mshr miss rate for UpgradeReq accesses
1264 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.852170 # mshr miss rate for UpgradeReq accesses
1265 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464442 # mshr miss rate for ReadExReq accesses
1266 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464442 # mshr miss rate for ReadExReq accesses
1267 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for ReadCleanReq accesses
1268 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016461 # mshr miss rate for ReadCleanReq accesses
1269 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for ReadSharedReq accesses
1270 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for ReadSharedReq accesses
1271 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025971 # mshr miss rate for ReadSharedReq accesses
1272 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024570 # mshr miss rate for ReadSharedReq accesses
1273 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for demand accesses
1274 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for demand accesses
1275 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for demand accesses
1276 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101964 # mshr miss rate for demand accesses
1277 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067954 # mshr miss rate for demand accesses
1278 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for overall accesses
1279 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for overall accesses
1280 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for overall accesses
1281 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101964 # mshr miss rate for overall accesses
1282 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067954 # mshr miss rate for overall accesses
1283 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21194.739787 # average UpgradeReq mshr miss latency
1284 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21194.739787 # average UpgradeReq mshr miss latency
1285 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67003.405939 # average ReadExReq mshr miss latency
1286 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67003.405939 # average ReadExReq mshr miss latency
1287 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73278.077324 # average ReadCleanReq mshr miss latency
1288 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73278.077324 # average ReadCleanReq mshr miss latency
1289 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average ReadSharedReq mshr miss latency
1290 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadSharedReq mshr miss latency
1291 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76004.092961 # average ReadSharedReq mshr miss latency
1292 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76015.289707 # average ReadSharedReq mshr miss latency
1293 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average overall mshr miss latency
1294 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency
1295 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73278.077324 # average overall mshr miss latency
1296 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68898.614587 # average overall mshr miss latency
1297 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69288.219654 # average overall mshr miss latency
1298 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average overall mshr miss latency
1299 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency
1300 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73278.077324 # average overall mshr miss latency
1301 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68898.614587 # average overall mshr miss latency
1302 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69288.219654 # average overall mshr miss latency
1303 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.519035 # average ReadReq mshr uncacheable latency
1304 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.519035 # average ReadReq mshr uncacheable latency
1305 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176999.459459 # average WriteReq mshr uncacheable latency
1306 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176999.459459 # average WriteReq mshr uncacheable latency
1307 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.506314 # average overall mshr uncacheable latency
1308 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.506314 # average overall mshr uncacheable latency
1309 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1310 system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution
1311 system.cpu.toL2Bus.trans_dist::ReadResp 3059319 # Transaction distribution
1312 system.cpu.toL2Bus.trans_dist::WriteReq 13875 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::WriteResp 13875 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::Writeback 1734439 # Transaction distribution
1315 system.cpu.toL2Bus.trans_dist::CleanEvict 1113474 # Transaction distribution
1316 system.cpu.toL2Bus.trans_dist::UpgradeReq 2547 # Transaction distribution
1317 system.cpu.toL2Bus.trans_dist::UpgradeResp 2547 # Transaction distribution
1318 system.cpu.toL2Bus.trans_dist::ReadExReq 287963 # Transaction distribution
1319 system.cpu.toL2Bus.trans_dist::ReadExResp 287963 # Transaction distribution
1320 system.cpu.toL2Bus.trans_dist::ReadCleanReq 991910 # Transaction distribution
1321 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1465068 # Transaction distribution
1322 system.cpu.toL2Bus.trans_dist::MessageReq 1642 # Transaction distribution
1323 system.cpu.toL2Bus.trans_dist::BadAddressError 22 # Transaction distribution
1324 system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1325 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2973341 # Packet count per connected master and slave (bytes)
1326 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6222105 # Packet count per connected master and slave (bytes)
1327 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 35861 # Packet count per connected master and slave (bytes)
1328 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 172954 # Packet count per connected master and slave (bytes)
1329 system.cpu.toL2Bus.pkt_count::total 9404261 # Packet count per connected master and slave (bytes)
1330 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63456832 # Cumulative packet size per connected master and slave (bytes)
1331 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208155201 # Cumulative packet size per connected master and slave (bytes)
1332 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1084160 # Cumulative packet size per connected master and slave (bytes)
1333 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5514304 # Cumulative packet size per connected master and slave (bytes)
1334 system.cpu.toL2Bus.pkt_size::total 278210497 # Cumulative packet size per connected master and slave (bytes)
1335 system.cpu.toL2Bus.snoops 220375 # Total snoops (count)
1336 system.cpu.toL2Bus.snoop_fanout::samples 6313792 # Request fanout histogram
1337 system.cpu.toL2Bus.snoop_fanout::mean 3.033219 # Request fanout histogram
1338 system.cpu.toL2Bus.snoop_fanout::stdev 0.179209 # Request fanout histogram
1339 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1340 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1341 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1342 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1343 system.cpu.toL2Bus.snoop_fanout::3 6104051 96.68% 96.68% # Request fanout histogram
1344 system.cpu.toL2Bus.snoop_fanout::4 209741 3.32% 100.00% # Request fanout histogram
1345 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1346 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1347 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1348 system.cpu.toL2Bus.snoop_fanout::total 6313792 # Request fanout histogram
1349 system.cpu.toL2Bus.reqLayer0.occupancy 4643672976 # Layer occupancy (ticks)
1350 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1351 system.cpu.toL2Bus.snoopLayer0.occupancy 564000 # Layer occupancy (ticks)
1352 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1353 system.cpu.toL2Bus.respLayer0.occupancy 1489388443 # Layer occupancy (ticks)
1354 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1355 system.cpu.toL2Bus.respLayer1.occupancy 3104272690 # Layer occupancy (ticks)
1356 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1357 system.cpu.toL2Bus.respLayer2.occupancy 24683477 # Layer occupancy (ticks)
1358 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1359 system.cpu.toL2Bus.respLayer3.occupancy 110523908 # Layer occupancy (ticks)
1360 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1361 system.iobus.trans_dist::ReadReq 222096 # Transaction distribution
1362 system.iobus.trans_dist::ReadResp 222096 # Transaction distribution
1363 system.iobus.trans_dist::WriteReq 57708 # Transaction distribution
1364 system.iobus.trans_dist::WriteResp 57708 # Transaction distribution
1365 system.iobus.trans_dist::MessageReq 1642 # Transaction distribution
1366 system.iobus.trans_dist::MessageResp 1642 # Transaction distribution
1367 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1368 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes)
1386 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
1387 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
1388 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
1389 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
1390 system.iobus.pkt_count::total 562892 # Packet count per connected master and slave (bytes)
1391 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes)
1410 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
1411 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
1412 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
1413 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
1414 system.iobus.pkt_size::total 3272836 # Cumulative packet size per connected master and slave (bytes)
1415 system.iobus.reqLayer0.occupancy 3914184 # Layer occupancy (ticks)
1416 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1417 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1418 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1419 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1420 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1421 system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks)
1422 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1423 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1424 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1426 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1428 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1430 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1432 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks)
1434 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1436 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1438 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1439 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1440 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1441 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1442 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1443 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1444 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1445 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1446 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1447 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1448 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1449 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1450 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1451 system.iobus.reqLayer19.occupancy 242657095 # Layer occupancy (ticks)
1452 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1453 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1454 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1455 system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks)
1456 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1457 system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks)
1458 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1459 system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks)
1460 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1461 system.iocache.tags.replacements 47574 # number of replacements
1462 system.iocache.tags.tagsinuse 0.103760 # Cycle average of tags in use
1463 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1464 system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
1465 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1466 system.iocache.tags.warmup_cycle 4993210499000 # Cycle when the warmup percentage was hit.
1467 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103760 # Average occupied blocks per requestor
1468 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006485 # Average percentage of cache occupancy
1469 system.iocache.tags.occ_percent::total 0.006485 # Average percentage of cache occupancy
1470 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1471 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1472 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1473 system.iocache.tags.tag_accesses 428661 # Number of tag accesses
1474 system.iocache.tags.data_accesses 428661 # Number of data accesses
1475 system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
1476 system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
1477 system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1478 system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
1479 system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
1480 system.iocache.demand_misses::total 909 # number of demand (read+write) misses
1481 system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
1482 system.iocache.overall_misses::total 909 # number of overall misses
1483 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141558677 # number of ReadReq miss cycles
1484 system.iocache.ReadReq_miss_latency::total 141558677 # number of ReadReq miss cycles
1485 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5512975418 # number of WriteLineReq miss cycles
1486 system.iocache.WriteLineReq_miss_latency::total 5512975418 # number of WriteLineReq miss cycles
1487 system.iocache.demand_miss_latency::pc.south_bridge.ide 141558677 # number of demand (read+write) miss cycles
1488 system.iocache.demand_miss_latency::total 141558677 # number of demand (read+write) miss cycles
1489 system.iocache.overall_miss_latency::pc.south_bridge.ide 141558677 # number of overall miss cycles
1490 system.iocache.overall_miss_latency::total 141558677 # number of overall miss cycles
1491 system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
1492 system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
1493 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1494 system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
1495 system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses
1496 system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses
1497 system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses
1498 system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses
1499 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1500 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1501 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1502 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1503 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1504 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1505 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1506 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1507 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average ReadReq miss latency
1508 system.iocache.ReadReq_avg_miss_latency::total 155730.117712 # average ReadReq miss latency
1509 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118000.330009 # average WriteLineReq miss latency
1510 system.iocache.WriteLineReq_avg_miss_latency::total 118000.330009 # average WriteLineReq miss latency
1511 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average overall miss latency
1512 system.iocache.demand_avg_miss_latency::total 155730.117712 # average overall miss latency
1513 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average overall miss latency
1514 system.iocache.overall_avg_miss_latency::total 155730.117712 # average overall miss latency
1515 system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked
1516 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1517 system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked
1518 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1519 system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked
1520 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1521 system.iocache.fast_writes 0 # number of fast writes performed
1522 system.iocache.cache_copies 0 # number of cache copies performed
1523 system.iocache.writebacks::writebacks 46667 # number of writebacks
1524 system.iocache.writebacks::total 46667 # number of writebacks
1525 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
1526 system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
1527 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1528 system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
1529 system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses
1530 system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses
1531 system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses
1532 system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses
1533 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of ReadReq MSHR miss cycles
1534 system.iocache.ReadReq_mshr_miss_latency::total 96108677 # number of ReadReq MSHR miss cycles
1535 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3176975418 # number of WriteLineReq MSHR miss cycles
1536 system.iocache.WriteLineReq_mshr_miss_latency::total 3176975418 # number of WriteLineReq MSHR miss cycles
1537 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of demand (read+write) MSHR miss cycles
1538 system.iocache.demand_mshr_miss_latency::total 96108677 # number of demand (read+write) MSHR miss cycles
1539 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of overall MSHR miss cycles
1540 system.iocache.overall_mshr_miss_latency::total 96108677 # number of overall MSHR miss cycles
1541 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1542 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1543 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1544 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1545 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1546 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1547 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1548 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1549 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average ReadReq mshr miss latency
1550 system.iocache.ReadReq_avg_mshr_miss_latency::total 105730.117712 # average ReadReq mshr miss latency
1551 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68000.330009 # average WriteLineReq mshr miss latency
1552 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68000.330009 # average WriteLineReq mshr miss latency
1553 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average overall mshr miss latency
1554 system.iocache.demand_avg_mshr_miss_latency::total 105730.117712 # average overall mshr miss latency
1555 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average overall mshr miss latency
1556 system.iocache.overall_avg_mshr_miss_latency::total 105730.117712 # average overall mshr miss latency
1557 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1558 system.membus.trans_dist::ReadReq 602896 # Transaction distribution
1559 system.membus.trans_dist::ReadResp 655847 # Transaction distribution
1560 system.membus.trans_dist::WriteReq 13875 # Transaction distribution
1561 system.membus.trans_dist::WriteResp 13875 # Transaction distribution
1562 system.membus.trans_dist::Writeback 149737 # Transaction distribution
1563 system.membus.trans_dist::CleanEvict 10183 # Transaction distribution
1564 system.membus.trans_dist::UpgradeReq 2524 # Transaction distribution
1565 system.membus.trans_dist::UpgradeResp 2074 # Transaction distribution
1566 system.membus.trans_dist::ReadExReq 133454 # Transaction distribution
1567 system.membus.trans_dist::ReadExResp 133450 # Transaction distribution
1568 system.membus.trans_dist::ReadSharedReq 52973 # Transaction distribution
1569 system.membus.trans_dist::MessageReq 1642 # Transaction distribution
1570 system.membus.trans_dist::MessageResp 1642 # Transaction distribution
1571 system.membus.trans_dist::BadAddressError 22 # Transaction distribution
1572 system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
1573 system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
1574 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
1575 system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
1576 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes)
1577 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769192 # Packet count per connected master and slave (bytes)
1578 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 487788 # Packet count per connected master and slave (bytes)
1579 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 44 # Packet count per connected master and slave (bytes)
1580 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721374 # Packet count per connected master and slave (bytes)
1581 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141823 # Packet count per connected master and slave (bytes)
1582 system.membus.pkt_count_system.iocache.mem_side::total 141823 # Packet count per connected master and slave (bytes)
1583 system.membus.pkt_count::total 1866481 # Packet count per connected master and slave (bytes)
1584 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
1585 system.membus.pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
1586 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes)
1587 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538381 # Cumulative packet size per connected master and slave (bytes)
1588 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18425216 # Cumulative packet size per connected master and slave (bytes)
1589 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20202049 # Cumulative packet size per connected master and slave (bytes)
1590 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
1591 system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
1592 system.membus.pkt_size::total 23223657 # Cumulative packet size per connected master and slave (bytes)
1593 system.membus.snoops 1607 # Total snoops (count)
1594 system.membus.snoop_fanout::samples 1014551 # Request fanout histogram
1595 system.membus.snoop_fanout::mean 1.001618 # Request fanout histogram
1596 system.membus.snoop_fanout::stdev 0.040197 # Request fanout histogram
1597 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1598 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1599 system.membus.snoop_fanout::1 1012909 99.84% 99.84% # Request fanout histogram
1600 system.membus.snoop_fanout::2 1642 0.16% 100.00% # Request fanout histogram
1601 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1602 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1603 system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1604 system.membus.snoop_fanout::total 1014551 # Request fanout histogram
1605 system.membus.reqLayer0.occupancy 354940000 # Layer occupancy (ticks)
1606 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1607 system.membus.reqLayer1.occupancy 388594500 # Layer occupancy (ticks)
1608 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1609 system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
1610 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1611 system.membus.reqLayer3.occupancy 1018302522 # Layer occupancy (ticks)
1612 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1613 system.membus.reqLayer4.occupancy 27500 # Layer occupancy (ticks)
1614 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1615 system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
1616 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1617 system.membus.respLayer2.occupancy 2206598693 # Layer occupancy (ticks)
1618 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1619 system.membus.respLayer4.occupancy 86075861 # Layer occupancy (ticks)
1620 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1621 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1622 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1623 system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
1624 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1625 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1626 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1627 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1628 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1629 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1630 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1631 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1632 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1633 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1634 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1636 ---------- End Simulation Statistics ----------
projects / gem5.git / blob