2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.144275 # Number of seconds simulated
4 sim_ticks 5144274809000 # Number of ticks simulated
5 final_tick 5144274809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 169693 # Simulator instruction rate (inst/s)
8 host_op_rate 335427 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2145113000 # Simulator tick rate (ticks/s)
10 host_mem_usage 770200 # Number of bytes of host memory used
11 host_seconds 2398.14 # Real time elapsed on the host
12 sim_insts 406947274 # Number of instructions simulated
13 sim_ops 804399711 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1034048 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10709312 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11775872 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1034048 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1034048 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9547776 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9547776 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16157 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 167333 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 183998 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149184 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149184 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 746 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 201009 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2081792 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2289122 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 201009 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 201009 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1856000 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1856000 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1856000 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 746 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 201009 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2081792 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4145122 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 183998 # Number of read requests accepted
52 system.physmem.writeReqs 149184 # Number of write requests accepted
53 system.physmem.readBursts 183998 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 149184 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11761088 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 14784 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9546240 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11775872 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9547776 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 231 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 58239 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11315 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 10581 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 12129 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11752 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11319 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 10663 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 10930 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11239 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 10920 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11403 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11471 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11421 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 12415 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12512 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11823 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11874 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 9756 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9158 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 9767 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 9469 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9300 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 9148 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 8815 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 8963 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 8876 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 9249 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 9141 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 9048 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9841 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 9635 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9295 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
97 system.physmem.totGap 5144274759500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 183998 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 149184 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 169620 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11412 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 450 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 36 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 38 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 2916 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 7399 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 7449 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 8122 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 8310 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 9443 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 8747 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 9907 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 10037 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 9884 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 11487 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 9002 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 8428 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 8682 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8054 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 7610 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 7540 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 268 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 294 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 158 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 126 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 170 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 70 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 72943 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 292.108413 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 174.353373 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 313.792232 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 28114 38.54% 38.54% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17711 24.28% 62.82% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7670 10.52% 73.34% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4213 5.78% 79.11% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 2951 4.05% 83.16% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2449 3.36% 86.52% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1349 1.85% 88.37% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1138 1.56% 89.93% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 7348 10.07% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 72943 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7277 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 25.251615 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 563.083563 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7276 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7277 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7277 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 20.497458 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.666266 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 13.148532 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6223 85.52% 85.52% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 179 2.46% 87.98% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 37 0.51% 88.48% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 181 2.49% 90.97% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 17 0.23% 91.21% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 151 2.08% 93.28% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 102 1.40% 94.68% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 5 0.07% 94.75% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 29 0.40% 95.15% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 31 0.43% 95.58% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 5 0.07% 95.64% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 9 0.12% 95.77% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 222 3.05% 98.82% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 6 0.08% 98.90% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 6 0.08% 98.98% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 40 0.55% 99.53% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 1 0.01% 99.55% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::92-95 1 0.01% 99.56% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::100-103 5 0.07% 99.63% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::112-115 1 0.01% 99.64% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::128-131 17 0.23% 99.92% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::144-147 1 0.01% 99.95% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::164-167 1 0.01% 99.99% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::168-171 1 0.01% 100.00% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::total 7277 # Writes before turning the bus around for reads
261 system.physmem.totQLat 2097648589 # Total ticks spent queuing
262 system.physmem.totMemAccLat 5543279839 # Total ticks spent from burst creation until serviced by the DRAM
263 system.physmem.totBusLat 918835000 # Total ticks spent in databus transfers
264 system.physmem.avgQLat 11414.72 # Average queueing delay per DRAM burst
265 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
266 system.physmem.avgMemAccLat 30164.72 # Average memory access latency per DRAM burst
267 system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
268 system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s
269 system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
270 system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s
271 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
272 system.physmem.busUtil 0.03 # Data bus utilization in percentage
273 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
274 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
275 system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
276 system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing
277 system.physmem.readRowHits 150147 # Number of row buffer hits during reads
278 system.physmem.writeRowHits 109836 # Number of row buffer hits during writes
279 system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads
280 system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes
281 system.physmem.avgGap 15439833.96 # Average gap between requests
282 system.physmem.pageHitRate 78.08 # Row buffer hit rate, read and write combined
283 system.physmem_0.actEnergy 269030160 # Energy for activate commands per rank (pJ)
284 system.physmem_0.preEnergy 146792250 # Energy for precharge commands per rank (pJ)
285 system.physmem_0.readEnergy 701430600 # Energy for read commands per rank (pJ)
286 system.physmem_0.writeEnergy 481956480 # Energy for write commands per rank (pJ)
287 system.physmem_0.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ)
288 system.physmem_0.actBackEnergy 132992885070 # Energy for active background per rank (pJ)
289 system.physmem_0.preBackEnergy 2969904214500 # Energy for precharge background per rank (pJ)
290 system.physmem_0.totalEnergy 3440495289780 # Total energy per rank (pJ)
291 system.physmem_0.averagePower 668.800889 # Core power per rank (mW)
292 system.physmem_0.memoryStateTime::IDLE 4940616567724 # Time in different power states
293 system.physmem_0.memoryStateTime::REF 171778620000 # Time in different power states
294 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
295 system.physmem_0.memoryStateTime::ACT 31879461276 # Time in different power states
296 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
297 system.physmem_1.actEnergy 282418920 # Energy for activate commands per rank (pJ)
298 system.physmem_1.preEnergy 154097625 # Energy for precharge commands per rank (pJ)
299 system.physmem_1.readEnergy 731944200 # Energy for read commands per rank (pJ)
300 system.physmem_1.writeEnergy 484600320 # Energy for write commands per rank (pJ)
301 system.physmem_1.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ)
302 system.physmem_1.actBackEnergy 133085381535 # Energy for active background per rank (pJ)
303 system.physmem_1.preBackEnergy 2969823077250 # Energy for precharge background per rank (pJ)
304 system.physmem_1.totalEnergy 3440560500570 # Total energy per rank (pJ)
305 system.physmem_1.averagePower 668.813565 # Core power per rank (mW)
306 system.physmem_1.memoryStateTime::IDLE 4940481114488 # Time in different power states
307 system.physmem_1.memoryStateTime::REF 171778620000 # Time in different power states
308 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
309 system.physmem_1.memoryStateTime::ACT 32014679262 # Time in different power states
310 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
311 system.cpu.branchPred.lookups 86341843 # Number of BP lookups
312 system.cpu.branchPred.condPredicted 86341843 # Number of conditional branches predicted
313 system.cpu.branchPred.condIncorrect 843606 # Number of conditional branches incorrect
314 system.cpu.branchPred.BTBLookups 79482226 # Number of BTB lookups
315 system.cpu.branchPred.BTBHits 77803537 # Number of BTB hits
316 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
317 system.cpu.branchPred.BTBHitPct 97.887969 # BTB Hit Percentage
318 system.cpu.branchPred.usedRAS 1532975 # Number of times the RAS was used to get a target.
319 system.cpu.branchPred.RASInCorrect 177711 # Number of incorrect RAS predictions.
320 system.cpu_clk_domain.clock 500 # Clock period in ticks
321 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
322 system.cpu.numCycles 465489033 # number of cpu cycles simulated
323 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
324 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
325 system.cpu.fetch.icacheStallCycles 27349012 # Number of cycles fetch is stalled on an Icache miss
326 system.cpu.fetch.Insts 426558725 # Number of instructions fetch has processed
327 system.cpu.fetch.Branches 86341843 # Number of branches that fetch encountered
328 system.cpu.fetch.predictedBranches 79336512 # Number of branches that fetch has predicted taken
329 system.cpu.fetch.Cycles 433328456 # Number of cycles fetch has run and was not squashing or blocked
330 system.cpu.fetch.SquashCycles 1773234 # Number of cycles fetch has spent squashing
331 system.cpu.fetch.TlbCycles 140367 # Number of cycles fetch has spent waiting for tlb
332 system.cpu.fetch.MiscStallCycles 61411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
333 system.cpu.fetch.PendingTrapStallCycles 195746 # Number of stall cycles due to pending traps
334 system.cpu.fetch.PendingQuiesceStallCycles 62 # Number of stall cycles due to pending quiesce instructions
335 system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR
336 system.cpu.fetch.CacheLines 8924695 # Number of cache lines fetched
337 system.cpu.fetch.IcacheSquashes 425342 # Number of outstanding Icache misses that were squashed
338 system.cpu.fetch.ItlbSquashes 4681 # Number of outstanding ITLB misses that were squashed
339 system.cpu.fetch.rateDist::samples 461962620 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::mean 1.822369 # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::stdev 3.015343 # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::0 297385469 64.37% 64.37% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::1 2141918 0.46% 64.84% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::2 72009169 15.59% 80.43% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::3 1542851 0.33% 80.76% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::4 2093373 0.45% 81.21% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::5 2277762 0.49% 81.71% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::6 1468275 0.32% 82.02% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::7 1844826 0.40% 82.42% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::8 81198977 17.58% 100.00% # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
355 system.cpu.fetch.rateDist::total 461962620 # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.branchRate 0.185486 # Number of branch fetches per cycle
357 system.cpu.fetch.rate 0.916367 # Number of inst fetches per cycle
358 system.cpu.decode.IdleCycles 23051751 # Number of cycles decode is idle
359 system.cpu.decode.BlockedCycles 281963390 # Number of cycles decode is blocked
360 system.cpu.decode.RunCycles 147749616 # Number of cycles decode is running
361 system.cpu.decode.UnblockCycles 8311246 # Number of cycles decode is unblocking
362 system.cpu.decode.SquashCycles 886617 # Number of cycles decode is squashing
363 system.cpu.decode.DecodedInsts 834090099 # Number of instructions handled by decode
364 system.cpu.rename.SquashCycles 886617 # Number of cycles rename is squashing
365 system.cpu.rename.IdleCycles 26334343 # Number of cycles rename is idle
366 system.cpu.rename.BlockCycles 229948938 # Number of cycles rename is blocking
367 system.cpu.rename.serializeStallCycles 14545958 # count of cycles rename stalled for serializing inst
368 system.cpu.rename.RunCycles 152100341 # Number of cycles rename is running
369 system.cpu.rename.UnblockCycles 38146423 # Number of cycles rename is unblocking
370 system.cpu.rename.RenamedInsts 830806639 # Number of instructions processed by rename
371 system.cpu.rename.ROBFullEvents 454355 # Number of times rename has blocked due to ROB full
372 system.cpu.rename.IQFullEvents 12555277 # Number of times rename has blocked due to IQ full
373 system.cpu.rename.LQFullEvents 214921 # Number of times rename has blocked due to LQ full
374 system.cpu.rename.SQFullEvents 22219847 # Number of times rename has blocked due to SQ full
375 system.cpu.rename.RenamedOperands 992487524 # Number of destination operands rename has renamed
376 system.cpu.rename.RenameLookups 1803840100 # Number of register rename lookups that rename has made
377 system.cpu.rename.int_rename_lookups 1108929979 # Number of integer rename lookups
378 system.cpu.rename.fp_rename_lookups 295 # Number of floating rename lookups
379 system.cpu.rename.CommittedMaps 961885153 # Number of HB maps that are committed
380 system.cpu.rename.UndoneMaps 30602369 # Number of HB maps that are undone due to squashing
381 system.cpu.rename.serializingInsts 460175 # count of serializing insts renamed
382 system.cpu.rename.tempSerializingInsts 463946 # count of temporary serializing insts renamed
383 system.cpu.rename.skidInsts 42648824 # count of insts added to the skid buffer
384 system.cpu.memDep0.insertedLoads 17020536 # Number of loads inserted to the mem dependence unit.
385 system.cpu.memDep0.insertedStores 10013615 # Number of stores inserted to the mem dependence unit.
386 system.cpu.memDep0.conflictingLoads 1265948 # Number of conflicting loads.
387 system.cpu.memDep0.conflictingStores 1065839 # Number of conflicting stores.
388 system.cpu.iq.iqInstsAdded 825617137 # Number of instructions added to the IQ (excludes non-spec)
389 system.cpu.iq.iqNonSpecInstsAdded 1152647 # Number of non-speculative instructions added to the IQ
390 system.cpu.iq.iqInstsIssued 820744592 # Number of instructions issued
391 system.cpu.iq.iqSquashedInstsIssued 214843 # Number of squashed instructions issued
392 system.cpu.iq.iqSquashedInstsExamined 22370068 # Number of squashed instructions iterated over during squash; mainly for profiling
393 system.cpu.iq.iqSquashedOperandsExamined 33775079 # Number of squashed operands that are examined and possibly removed from graph
394 system.cpu.iq.iqSquashedNonSpecRemoved 142908 # Number of squashed non-spec instructions that were removed
395 system.cpu.iq.issued_per_cycle::samples 461962620 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::mean 1.776647 # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::stdev 2.400230 # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::0 278779319 60.35% 60.35% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::1 13677385 2.96% 63.31% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::2 9694463 2.10% 65.41% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::3 7479161 1.62% 67.02% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::4 73155086 15.84% 82.86% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::5 4780135 1.03% 83.90% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::6 72637826 15.72% 99.62% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::7 1181137 0.26% 99.87% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::8 578108 0.13% 100.00% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
411 system.cpu.iq.issued_per_cycle::total 461962620 # Number of insts issued each cycle
412 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
413 system.cpu.iq.fu_full::IntAlu 2412123 76.39% 76.39% # attempts to use FU when none available
414 system.cpu.iq.fu_full::IntMult 0 0.00% 76.39% # attempts to use FU when none available
415 system.cpu.iq.fu_full::IntDiv 0 0.00% 76.39% # attempts to use FU when none available
416 system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.39% # attempts to use FU when none available
417 system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.39% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.39% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatMult 0 0.00% 76.39% # attempts to use FU when none available
420 system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.39% # attempts to use FU when none available
421 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.39% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.39% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.39% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.39% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.39% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.39% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.39% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdMult 0 0.00% 76.39% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.39% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdShift 0 0.00% 76.39% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.39% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.39% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.39% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.39% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.39% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.39% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.39% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.39% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.39% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.39% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.39% # attempts to use FU when none available
442 system.cpu.iq.fu_full::MemRead 586072 18.56% 94.95% # attempts to use FU when none available
443 system.cpu.iq.fu_full::MemWrite 159607 5.05% 100.00% # attempts to use FU when none available
444 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
445 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
446 system.cpu.iq.FU_type_0::No_OpClass 284241 0.03% 0.03% # Type of FU issued
447 system.cpu.iq.FU_type_0::IntAlu 792878234 96.60% 96.64% # Type of FU issued
448 system.cpu.iq.FU_type_0::IntMult 149840 0.02% 96.66% # Type of FU issued
449 system.cpu.iq.FU_type_0::IntDiv 126459 0.02% 96.67% # Type of FU issued
450 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued
451 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatCvt 91 0.00% 96.67% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued
455 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.67% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.67% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.67% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.67% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.67% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.67% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.67% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.67% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.67% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.67% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.67% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.67% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.67% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.67% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.67% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.67% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued
476 system.cpu.iq.FU_type_0::MemRead 18033989 2.20% 98.87% # Type of FU issued
477 system.cpu.iq.FU_type_0::MemWrite 9271738 1.13% 100.00% # Type of FU issued
478 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
479 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
480 system.cpu.iq.FU_type_0::total 820744592 # Type of FU issued
481 system.cpu.iq.rate 1.763188 # Inst issue rate
482 system.cpu.iq.fu_busy_cnt 3157802 # FU busy when requested
483 system.cpu.iq.fu_busy_rate 0.003847 # FU busy rate (busy events/executed inst)
484 system.cpu.iq.int_inst_queue_reads 2106824012 # Number of integer instruction queue reads
485 system.cpu.iq.int_inst_queue_writes 849151947 # Number of integer instruction queue writes
486 system.cpu.iq.int_inst_queue_wakeup_accesses 816471101 # Number of integer instruction queue wakeup accesses
487 system.cpu.iq.fp_inst_queue_reads 436 # Number of floating instruction queue reads
488 system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes
489 system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses
490 system.cpu.iq.int_alu_accesses 823617942 # Number of integer alu accesses
491 system.cpu.iq.fp_alu_accesses 211 # Number of floating point alu accesses
492 system.cpu.iew.lsq.thread0.forwLoads 1861954 # Number of loads that had data forwarded from stores
493 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
494 system.cpu.iew.lsq.thread0.squashedLoads 3065804 # Number of loads squashed
495 system.cpu.iew.lsq.thread0.ignoredResponses 14153 # Number of memory responses ignored because the instruction is squashed
496 system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations
497 system.cpu.iew.lsq.thread0.squashedStores 1593948 # Number of stores squashed
498 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
499 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
500 system.cpu.iew.lsq.thread0.rescheduledLoads 2095806 # Number of loads that were rescheduled
501 system.cpu.iew.lsq.thread0.cacheBlocked 68873 # Number of times an access to memory failed due to the cache being blocked
502 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
503 system.cpu.iew.iewSquashCycles 886617 # Number of cycles IEW is squashing
504 system.cpu.iew.iewBlockCycles 206103955 # Number of cycles IEW is blocking
505 system.cpu.iew.iewUnblockCycles 15659492 # Number of cycles IEW is unblocking
506 system.cpu.iew.iewDispatchedInsts 826769784 # Number of instructions dispatched to IQ
507 system.cpu.iew.iewDispSquashedInsts 162986 # Number of squashed instructions skipped by dispatch
508 system.cpu.iew.iewDispLoadInsts 17020536 # Number of dispatched load instructions
509 system.cpu.iew.iewDispStoreInsts 10013615 # Number of dispatched store instructions
510 system.cpu.iew.iewDispNonSpecInsts 683525 # Number of dispatched non-speculative instructions
511 system.cpu.iew.iewIQFullEvents 383471 # Number of times the IQ has become full, causing a stall
512 system.cpu.iew.iewLSQFullEvents 14451239 # Number of times the LSQ has become full, causing a stall
513 system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations
514 system.cpu.iew.predictedTakenIncorrect 476576 # Number of branches that were predicted taken incorrectly
515 system.cpu.iew.predictedNotTakenIncorrect 506351 # Number of branches that were predicted not taken incorrectly
516 system.cpu.iew.branchMispredicts 982927 # Number of branch mispredicts detected at execute
517 system.cpu.iew.iewExecutedInsts 819239221 # Number of executed instructions
518 system.cpu.iew.iewExecLoadInsts 17663851 # Number of load instructions executed
519 system.cpu.iew.iewExecSquashedInsts 1381012 # Number of squashed instructions skipped in execute
520 system.cpu.iew.exec_swp 0 # number of swp insts executed
521 system.cpu.iew.exec_nop 0 # number of nop insts executed
522 system.cpu.iew.exec_refs 26724913 # number of memory reference insts executed
523 system.cpu.iew.exec_branches 82983667 # Number of branches executed
524 system.cpu.iew.exec_stores 9061062 # Number of stores executed
525 system.cpu.iew.exec_rate 1.759954 # Inst execution rate
526 system.cpu.iew.wb_sent 818769187 # cumulative count of insts sent to commit
527 system.cpu.iew.wb_count 816471257 # cumulative count of insts written-back
528 system.cpu.iew.wb_producers 638649867 # num instructions producing a value
529 system.cpu.iew.wb_consumers 1046653125 # num instructions consuming a value
530 system.cpu.iew.wb_rate 1.754008 # insts written-back per cycle
531 system.cpu.iew.wb_fanout 0.610183 # average fanout of values written-back
532 system.cpu.commit.commitSquashedInsts 22245724 # The number of squashed insts skipped by commit
533 system.cpu.commit.commitNonSpecStalls 1009739 # The number of times commit has been forced to stall to communicate backwards
534 system.cpu.commit.branchMispredicts 854697 # The number of times a branch was mispredicted
535 system.cpu.commit.committed_per_cycle::samples 458607756 # Number of insts commited each cycle
536 system.cpu.commit.committed_per_cycle::mean 1.754004 # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::stdev 2.647518 # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::0 288145143 62.83% 62.83% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::1 11087272 2.42% 65.25% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::2 3640468 0.79% 66.04% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::3 74478879 16.24% 82.28% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::4 2430107 0.53% 82.81% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::5 1625402 0.35% 83.17% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::6 1001040 0.22% 83.38% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::7 70854372 15.45% 98.83% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::8 5345073 1.17% 100.00% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::total 458607756 # Number of insts commited each cycle
552 system.cpu.commit.committedInsts 406947274 # Number of instructions committed
553 system.cpu.commit.committedOps 804399711 # Number of ops (including micro ops) committed
554 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
555 system.cpu.commit.refs 22374398 # Number of memory references committed
556 system.cpu.commit.loads 13954731 # Number of loads committed
557 system.cpu.commit.membars 448033 # Number of memory barriers committed
558 system.cpu.commit.branches 81999646 # Number of branches committed
559 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
560 system.cpu.commit.int_insts 733379682 # Number of committed integer instructions.
561 system.cpu.commit.function_calls 1155571 # Number of function calls committed.
562 system.cpu.commit.op_class_0::No_OpClass 171831 0.02% 0.02% # Class of committed instruction
563 system.cpu.commit.op_class_0::IntAlu 781589650 97.16% 97.19% # Class of committed instruction
564 system.cpu.commit.op_class_0::IntMult 144528 0.02% 97.20% # Class of committed instruction
565 system.cpu.commit.op_class_0::IntDiv 121874 0.02% 97.22% # Class of committed instruction
566 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
567 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
568 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
569 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
570 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
572 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
573 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
574 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
575 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
576 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::MemRead 13952145 1.73% 98.95% # Class of committed instruction
593 system.cpu.commit.op_class_0::MemWrite 8419667 1.05% 100.00% # Class of committed instruction
594 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
595 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
596 system.cpu.commit.op_class_0::total 804399711 # Class of committed instruction
597 system.cpu.commit.bw_lim_events 5345073 # number cycles where commit BW limit reached
598 system.cpu.rob.rob_reads 1279829790 # The number of ROB reads
599 system.cpu.rob.rob_writes 1656663443 # The number of ROB writes
600 system.cpu.timesIdled 287506 # Number of times that the entire CPU went into an idle state and unscheduled itself
601 system.cpu.idleCycles 3526413 # Total number of cycles that the CPU has spent unscheduled due to idling
602 system.cpu.quiesceCycles 9823058000 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
603 system.cpu.committedInsts 406947274 # Number of Instructions Simulated
604 system.cpu.committedOps 804399711 # Number of Ops (including micro ops) Simulated
605 system.cpu.cpi 1.143856 # CPI: Cycles Per Instruction
606 system.cpu.cpi_total 1.143856 # CPI: Total CPI of All Threads
607 system.cpu.ipc 0.874236 # IPC: Instructions Per Cycle
608 system.cpu.ipc_total 0.874236 # IPC: Total IPC of All Threads
609 system.cpu.int_regfile_reads 1088022059 # number of integer regfile reads
610 system.cpu.int_regfile_writes 653481018 # number of integer regfile writes
611 system.cpu.fp_regfile_reads 156 # number of floating regfile reads
612 system.cpu.cc_regfile_reads 414844045 # number of cc regfile reads
613 system.cpu.cc_regfile_writes 320950754 # number of cc regfile writes
614 system.cpu.misc_regfile_reads 264261421 # number of misc regfile reads
615 system.cpu.misc_regfile_writes 400173 # number of misc regfile writes
616 system.cpu.dcache.tags.replacements 1656014 # number of replacements
617 system.cpu.dcache.tags.tagsinuse 511.995636 # Cycle average of tags in use
618 system.cpu.dcache.tags.total_refs 18946459 # Total number of references to valid blocks.
619 system.cpu.dcache.tags.sampled_refs 1656526 # Sample count of references to valid blocks.
620 system.cpu.dcache.tags.avg_refs 11.437466 # Average number of references to valid blocks.
621 system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit.
622 system.cpu.dcache.tags.occ_blocks::cpu.data 511.995636 # Average occupied blocks per requestor
623 system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
624 system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy
625 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
626 system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id
627 system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
628 system.cpu.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
629 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
630 system.cpu.dcache.tags.tag_accesses 87599396 # Number of tag accesses
631 system.cpu.dcache.tags.data_accesses 87599396 # Number of data accesses
632 system.cpu.dcache.ReadReq_hits::cpu.data 10805755 # number of ReadReq hits
633 system.cpu.dcache.ReadReq_hits::total 10805755 # number of ReadReq hits
634 system.cpu.dcache.WriteReq_hits::cpu.data 8075007 # number of WriteReq hits
635 system.cpu.dcache.WriteReq_hits::total 8075007 # number of WriteReq hits
636 system.cpu.dcache.SoftPFReq_hits::cpu.data 62855 # number of SoftPFReq hits
637 system.cpu.dcache.SoftPFReq_hits::total 62855 # number of SoftPFReq hits
638 system.cpu.dcache.demand_hits::cpu.data 18880762 # number of demand (read+write) hits
639 system.cpu.dcache.demand_hits::total 18880762 # number of demand (read+write) hits
640 system.cpu.dcache.overall_hits::cpu.data 18943617 # number of overall hits
641 system.cpu.dcache.overall_hits::total 18943617 # number of overall hits
642 system.cpu.dcache.ReadReq_misses::cpu.data 1800696 # number of ReadReq misses
643 system.cpu.dcache.ReadReq_misses::total 1800696 # number of ReadReq misses
644 system.cpu.dcache.WriteReq_misses::cpu.data 334991 # number of WriteReq misses
645 system.cpu.dcache.WriteReq_misses::total 334991 # number of WriteReq misses
646 system.cpu.dcache.SoftPFReq_misses::cpu.data 406405 # number of SoftPFReq misses
647 system.cpu.dcache.SoftPFReq_misses::total 406405 # number of SoftPFReq misses
648 system.cpu.dcache.demand_misses::cpu.data 2135687 # number of demand (read+write) misses
649 system.cpu.dcache.demand_misses::total 2135687 # number of demand (read+write) misses
650 system.cpu.dcache.overall_misses::cpu.data 2542092 # number of overall misses
651 system.cpu.dcache.overall_misses::total 2542092 # number of overall misses
652 system.cpu.dcache.ReadReq_miss_latency::cpu.data 30137867500 # number of ReadReq miss cycles
653 system.cpu.dcache.ReadReq_miss_latency::total 30137867500 # number of ReadReq miss cycles
654 system.cpu.dcache.WriteReq_miss_latency::cpu.data 21089945740 # number of WriteReq miss cycles
655 system.cpu.dcache.WriteReq_miss_latency::total 21089945740 # number of WriteReq miss cycles
656 system.cpu.dcache.demand_miss_latency::cpu.data 51227813240 # number of demand (read+write) miss cycles
657 system.cpu.dcache.demand_miss_latency::total 51227813240 # number of demand (read+write) miss cycles
658 system.cpu.dcache.overall_miss_latency::cpu.data 51227813240 # number of overall miss cycles
659 system.cpu.dcache.overall_miss_latency::total 51227813240 # number of overall miss cycles
660 system.cpu.dcache.ReadReq_accesses::cpu.data 12606451 # number of ReadReq accesses(hits+misses)
661 system.cpu.dcache.ReadReq_accesses::total 12606451 # number of ReadReq accesses(hits+misses)
662 system.cpu.dcache.WriteReq_accesses::cpu.data 8409998 # number of WriteReq accesses(hits+misses)
663 system.cpu.dcache.WriteReq_accesses::total 8409998 # number of WriteReq accesses(hits+misses)
664 system.cpu.dcache.SoftPFReq_accesses::cpu.data 469260 # number of SoftPFReq accesses(hits+misses)
665 system.cpu.dcache.SoftPFReq_accesses::total 469260 # number of SoftPFReq accesses(hits+misses)
666 system.cpu.dcache.demand_accesses::cpu.data 21016449 # number of demand (read+write) accesses
667 system.cpu.dcache.demand_accesses::total 21016449 # number of demand (read+write) accesses
668 system.cpu.dcache.overall_accesses::cpu.data 21485709 # number of overall (read+write) accesses
669 system.cpu.dcache.overall_accesses::total 21485709 # number of overall (read+write) accesses
670 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142839 # miss rate for ReadReq accesses
671 system.cpu.dcache.ReadReq_miss_rate::total 0.142839 # miss rate for ReadReq accesses
672 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039832 # miss rate for WriteReq accesses
673 system.cpu.dcache.WriteReq_miss_rate::total 0.039832 # miss rate for WriteReq accesses
674 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.866055 # miss rate for SoftPFReq accesses
675 system.cpu.dcache.SoftPFReq_miss_rate::total 0.866055 # miss rate for SoftPFReq accesses
676 system.cpu.dcache.demand_miss_rate::cpu.data 0.101620 # miss rate for demand accesses
677 system.cpu.dcache.demand_miss_rate::total 0.101620 # miss rate for demand accesses
678 system.cpu.dcache.overall_miss_rate::cpu.data 0.118315 # miss rate for overall accesses
679 system.cpu.dcache.overall_miss_rate::total 0.118315 # miss rate for overall accesses
680 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16736.788164 # average ReadReq miss latency
681 system.cpu.dcache.ReadReq_avg_miss_latency::total 16736.788164 # average ReadReq miss latency
682 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62956.753286 # average WriteReq miss latency
683 system.cpu.dcache.WriteReq_avg_miss_latency::total 62956.753286 # average WriteReq miss latency
684 system.cpu.dcache.demand_avg_miss_latency::cpu.data 23986.573519 # average overall miss latency
685 system.cpu.dcache.demand_avg_miss_latency::total 23986.573519 # average overall miss latency
686 system.cpu.dcache.overall_avg_miss_latency::cpu.data 20151.832916 # average overall miss latency
687 system.cpu.dcache.overall_avg_miss_latency::total 20151.832916 # average overall miss latency
688 system.cpu.dcache.blocked_cycles::no_mshrs 556428 # number of cycles access was blocked
689 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
690 system.cpu.dcache.blocked::no_mshrs 52454 # number of cycles access was blocked
691 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
692 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.607923 # average number of cycles each access was blocked
693 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
694 system.cpu.dcache.fast_writes 0 # number of fast writes performed
695 system.cpu.dcache.cache_copies 0 # number of cache copies performed
696 system.cpu.dcache.writebacks::writebacks 1558074 # number of writebacks
697 system.cpu.dcache.writebacks::total 1558074 # number of writebacks
698 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834885 # number of ReadReq MSHR hits
699 system.cpu.dcache.ReadReq_mshr_hits::total 834885 # number of ReadReq MSHR hits
700 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44903 # number of WriteReq MSHR hits
701 system.cpu.dcache.WriteReq_mshr_hits::total 44903 # number of WriteReq MSHR hits
702 system.cpu.dcache.demand_mshr_hits::cpu.data 879788 # number of demand (read+write) MSHR hits
703 system.cpu.dcache.demand_mshr_hits::total 879788 # number of demand (read+write) MSHR hits
704 system.cpu.dcache.overall_mshr_hits::cpu.data 879788 # number of overall MSHR hits
705 system.cpu.dcache.overall_mshr_hits::total 879788 # number of overall MSHR hits
706 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965811 # number of ReadReq MSHR misses
707 system.cpu.dcache.ReadReq_mshr_misses::total 965811 # number of ReadReq MSHR misses
708 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290088 # number of WriteReq MSHR misses
709 system.cpu.dcache.WriteReq_mshr_misses::total 290088 # number of WriteReq MSHR misses
710 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402915 # number of SoftPFReq MSHR misses
711 system.cpu.dcache.SoftPFReq_mshr_misses::total 402915 # number of SoftPFReq MSHR misses
712 system.cpu.dcache.demand_mshr_misses::cpu.data 1255899 # number of demand (read+write) MSHR misses
713 system.cpu.dcache.demand_mshr_misses::total 1255899 # number of demand (read+write) MSHR misses
714 system.cpu.dcache.overall_mshr_misses::cpu.data 1658814 # number of overall MSHR misses
715 system.cpu.dcache.overall_mshr_misses::total 1658814 # number of overall MSHR misses
716 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable
717 system.cpu.dcache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable
718 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable
719 system.cpu.dcache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable
720 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses
721 system.cpu.dcache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses
722 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14288232000 # number of ReadReq MSHR miss cycles
723 system.cpu.dcache.ReadReq_mshr_miss_latency::total 14288232000 # number of ReadReq MSHR miss cycles
724 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19138141242 # number of WriteReq MSHR miss cycles
725 system.cpu.dcache.WriteReq_mshr_miss_latency::total 19138141242 # number of WriteReq MSHR miss cycles
726 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6806565500 # number of SoftPFReq MSHR miss cycles
727 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6806565500 # number of SoftPFReq MSHR miss cycles
728 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33426373242 # number of demand (read+write) MSHR miss cycles
729 system.cpu.dcache.demand_mshr_miss_latency::total 33426373242 # number of demand (read+write) MSHR miss cycles
730 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40232938742 # number of overall MSHR miss cycles
731 system.cpu.dcache.overall_mshr_miss_latency::total 40232938742 # number of overall MSHR miss cycles
732 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98114325000 # number of ReadReq MSHR uncacheable cycles
733 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98114325000 # number of ReadReq MSHR uncacheable cycles
734 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778681500 # number of WriteReq MSHR uncacheable cycles
735 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778681500 # number of WriteReq MSHR uncacheable cycles
736 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100893006500 # number of overall MSHR uncacheable cycles
737 system.cpu.dcache.overall_mshr_uncacheable_latency::total 100893006500 # number of overall MSHR uncacheable cycles
738 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076612 # mshr miss rate for ReadReq accesses
739 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076612 # mshr miss rate for ReadReq accesses
740 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034493 # mshr miss rate for WriteReq accesses
741 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034493 # mshr miss rate for WriteReq accesses
742 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858618 # mshr miss rate for SoftPFReq accesses
743 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858618 # mshr miss rate for SoftPFReq accesses
744 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059758 # mshr miss rate for demand accesses
745 system.cpu.dcache.demand_mshr_miss_rate::total 0.059758 # mshr miss rate for demand accesses
746 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077205 # mshr miss rate for overall accesses
747 system.cpu.dcache.overall_mshr_miss_rate::total 0.077205 # mshr miss rate for overall accesses
748 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14794.024918 # average ReadReq mshr miss latency
749 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14794.024918 # average ReadReq mshr miss latency
750 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65973.570923 # average WriteReq mshr miss latency
751 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65973.570923 # average WriteReq mshr miss latency
752 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16893.303799 # average SoftPFReq mshr miss latency
753 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16893.303799 # average SoftPFReq mshr miss latency
754 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26615.494751 # average overall mshr miss latency
755 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26615.494751 # average overall mshr miss latency
756 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24254.038573 # average overall mshr miss latency
757 system.cpu.dcache.overall_avg_mshr_miss_latency::total 24254.038573 # average overall mshr miss latency
758 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.837269 # average ReadReq mshr uncacheable latency
759 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.837269 # average ReadReq mshr uncacheable latency
760 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199919.526585 # average WriteReq mshr uncacheable latency
761 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199919.526585 # average WriteReq mshr uncacheable latency
762 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171774.002782 # average overall mshr uncacheable latency
763 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171774.002782 # average overall mshr uncacheable latency
764 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
765 system.cpu.dtb_walker_cache.tags.replacements 76780 # number of replacements
766 system.cpu.dtb_walker_cache.tags.tagsinuse 15.821773 # Cycle average of tags in use
767 system.cpu.dtb_walker_cache.tags.total_refs 101894 # Total number of references to valid blocks.
768 system.cpu.dtb_walker_cache.tags.sampled_refs 76796 # Sample count of references to valid blocks.
769 system.cpu.dtb_walker_cache.tags.avg_refs 1.326814 # Average number of references to valid blocks.
770 system.cpu.dtb_walker_cache.tags.warmup_cycle 199830391500 # Cycle when the warmup percentage was hit.
771 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821773 # Average occupied blocks per requestor
772 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988861 # Average percentage of cache occupancy
773 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988861 # Average percentage of cache occupancy
774 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
775 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
776 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
777 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
778 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
779 system.cpu.dtb_walker_cache.tags.tag_accesses 437119 # Number of tag accesses
780 system.cpu.dtb_walker_cache.tags.data_accesses 437119 # Number of data accesses
781 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 101894 # number of ReadReq hits
782 system.cpu.dtb_walker_cache.ReadReq_hits::total 101894 # number of ReadReq hits
783 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 101894 # number of demand (read+write) hits
784 system.cpu.dtb_walker_cache.demand_hits::total 101894 # number of demand (read+write) hits
785 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 101894 # number of overall hits
786 system.cpu.dtb_walker_cache.overall_hits::total 101894 # number of overall hits
787 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77777 # number of ReadReq misses
788 system.cpu.dtb_walker_cache.ReadReq_misses::total 77777 # number of ReadReq misses
789 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77777 # number of demand (read+write) misses
790 system.cpu.dtb_walker_cache.demand_misses::total 77777 # number of demand (read+write) misses
791 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77777 # number of overall misses
792 system.cpu.dtb_walker_cache.overall_misses::total 77777 # number of overall misses
793 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 965958500 # number of ReadReq miss cycles
794 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 965958500 # number of ReadReq miss cycles
795 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 965958500 # number of demand (read+write) miss cycles
796 system.cpu.dtb_walker_cache.demand_miss_latency::total 965958500 # number of demand (read+write) miss cycles
797 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 965958500 # number of overall miss cycles
798 system.cpu.dtb_walker_cache.overall_miss_latency::total 965958500 # number of overall miss cycles
799 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 179671 # number of ReadReq accesses(hits+misses)
800 system.cpu.dtb_walker_cache.ReadReq_accesses::total 179671 # number of ReadReq accesses(hits+misses)
801 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 179671 # number of demand (read+write) accesses
802 system.cpu.dtb_walker_cache.demand_accesses::total 179671 # number of demand (read+write) accesses
803 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 179671 # number of overall (read+write) accesses
804 system.cpu.dtb_walker_cache.overall_accesses::total 179671 # number of overall (read+write) accesses
805 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432886 # miss rate for ReadReq accesses
806 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432886 # miss rate for ReadReq accesses
807 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432886 # miss rate for demand accesses
808 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432886 # miss rate for demand accesses
809 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432886 # miss rate for overall accesses
810 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432886 # miss rate for overall accesses
811 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12419.590624 # average ReadReq miss latency
812 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12419.590624 # average ReadReq miss latency
813 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency
814 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12419.590624 # average overall miss latency
815 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency
816 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12419.590624 # average overall miss latency
817 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
818 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
819 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
820 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
821 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
822 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
823 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
824 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
825 system.cpu.dtb_walker_cache.writebacks::writebacks 21553 # number of writebacks
826 system.cpu.dtb_walker_cache.writebacks::total 21553 # number of writebacks
827 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77777 # number of ReadReq MSHR misses
828 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77777 # number of ReadReq MSHR misses
829 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77777 # number of demand (read+write) MSHR misses
830 system.cpu.dtb_walker_cache.demand_mshr_misses::total 77777 # number of demand (read+write) MSHR misses
831 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77777 # number of overall MSHR misses
832 system.cpu.dtb_walker_cache.overall_mshr_misses::total 77777 # number of overall MSHR misses
833 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 888181500 # number of ReadReq MSHR miss cycles
834 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 888181500 # number of ReadReq MSHR miss cycles
835 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 888181500 # number of demand (read+write) MSHR miss cycles
836 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 888181500 # number of demand (read+write) MSHR miss cycles
837 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 888181500 # number of overall MSHR miss cycles
838 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 888181500 # number of overall MSHR miss cycles
839 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for ReadReq accesses
840 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432886 # mshr miss rate for ReadReq accesses
841 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for demand accesses
842 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432886 # mshr miss rate for demand accesses
843 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for overall accesses
844 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432886 # mshr miss rate for overall accesses
845 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average ReadReq mshr miss latency
846 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11419.590624 # average ReadReq mshr miss latency
847 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency
848 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency
849 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency
850 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency
851 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
852 system.cpu.icache.tags.replacements 981325 # number of replacements
853 system.cpu.icache.tags.tagsinuse 508.752321 # Cycle average of tags in use
854 system.cpu.icache.tags.total_refs 7876209 # Total number of references to valid blocks.
855 system.cpu.icache.tags.sampled_refs 981837 # Sample count of references to valid blocks.
856 system.cpu.icache.tags.avg_refs 8.021911 # Average number of references to valid blocks.
857 system.cpu.icache.tags.warmup_cycle 150355632500 # Cycle when the warmup percentage was hit.
858 system.cpu.icache.tags.occ_blocks::cpu.inst 508.752321 # Average occupied blocks per requestor
859 system.cpu.icache.tags.occ_percent::cpu.inst 0.993657 # Average percentage of cache occupancy
860 system.cpu.icache.tags.occ_percent::total 0.993657 # Average percentage of cache occupancy
861 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
862 system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
863 system.cpu.icache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id
864 system.cpu.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
865 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
866 system.cpu.icache.tags.tag_accesses 9906588 # Number of tag accesses
867 system.cpu.icache.tags.data_accesses 9906588 # Number of data accesses
868 system.cpu.icache.ReadReq_hits::cpu.inst 7876209 # number of ReadReq hits
869 system.cpu.icache.ReadReq_hits::total 7876209 # number of ReadReq hits
870 system.cpu.icache.demand_hits::cpu.inst 7876209 # number of demand (read+write) hits
871 system.cpu.icache.demand_hits::total 7876209 # number of demand (read+write) hits
872 system.cpu.icache.overall_hits::cpu.inst 7876209 # number of overall hits
873 system.cpu.icache.overall_hits::total 7876209 # number of overall hits
874 system.cpu.icache.ReadReq_misses::cpu.inst 1048476 # number of ReadReq misses
875 system.cpu.icache.ReadReq_misses::total 1048476 # number of ReadReq misses
876 system.cpu.icache.demand_misses::cpu.inst 1048476 # number of demand (read+write) misses
877 system.cpu.icache.demand_misses::total 1048476 # number of demand (read+write) misses
878 system.cpu.icache.overall_misses::cpu.inst 1048476 # number of overall misses
879 system.cpu.icache.overall_misses::total 1048476 # number of overall misses
880 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15750091989 # number of ReadReq miss cycles
881 system.cpu.icache.ReadReq_miss_latency::total 15750091989 # number of ReadReq miss cycles
882 system.cpu.icache.demand_miss_latency::cpu.inst 15750091989 # number of demand (read+write) miss cycles
883 system.cpu.icache.demand_miss_latency::total 15750091989 # number of demand (read+write) miss cycles
884 system.cpu.icache.overall_miss_latency::cpu.inst 15750091989 # number of overall miss cycles
885 system.cpu.icache.overall_miss_latency::total 15750091989 # number of overall miss cycles
886 system.cpu.icache.ReadReq_accesses::cpu.inst 8924685 # number of ReadReq accesses(hits+misses)
887 system.cpu.icache.ReadReq_accesses::total 8924685 # number of ReadReq accesses(hits+misses)
888 system.cpu.icache.demand_accesses::cpu.inst 8924685 # number of demand (read+write) accesses
889 system.cpu.icache.demand_accesses::total 8924685 # number of demand (read+write) accesses
890 system.cpu.icache.overall_accesses::cpu.inst 8924685 # number of overall (read+write) accesses
891 system.cpu.icache.overall_accesses::total 8924685 # number of overall (read+write) accesses
892 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117480 # miss rate for ReadReq accesses
893 system.cpu.icache.ReadReq_miss_rate::total 0.117480 # miss rate for ReadReq accesses
894 system.cpu.icache.demand_miss_rate::cpu.inst 0.117480 # miss rate for demand accesses
895 system.cpu.icache.demand_miss_rate::total 0.117480 # miss rate for demand accesses
896 system.cpu.icache.overall_miss_rate::cpu.inst 0.117480 # miss rate for overall accesses
897 system.cpu.icache.overall_miss_rate::total 0.117480 # miss rate for overall accesses
898 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15021.890810 # average ReadReq miss latency
899 system.cpu.icache.ReadReq_avg_miss_latency::total 15021.890810 # average ReadReq miss latency
900 system.cpu.icache.demand_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency
901 system.cpu.icache.demand_avg_miss_latency::total 15021.890810 # average overall miss latency
902 system.cpu.icache.overall_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency
903 system.cpu.icache.overall_avg_miss_latency::total 15021.890810 # average overall miss latency
904 system.cpu.icache.blocked_cycles::no_mshrs 14497 # number of cycles access was blocked
905 system.cpu.icache.blocked_cycles::no_targets 291 # number of cycles access was blocked
906 system.cpu.icache.blocked::no_mshrs 495 # number of cycles access was blocked
907 system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
908 system.cpu.icache.avg_blocked_cycles::no_mshrs 29.286869 # average number of cycles each access was blocked
909 system.cpu.icache.avg_blocked_cycles::no_targets 72.750000 # average number of cycles each access was blocked
910 system.cpu.icache.fast_writes 0 # number of fast writes performed
911 system.cpu.icache.cache_copies 0 # number of cache copies performed
912 system.cpu.icache.writebacks::writebacks 981325 # number of writebacks
913 system.cpu.icache.writebacks::total 981325 # number of writebacks
914 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66573 # number of ReadReq MSHR hits
915 system.cpu.icache.ReadReq_mshr_hits::total 66573 # number of ReadReq MSHR hits
916 system.cpu.icache.demand_mshr_hits::cpu.inst 66573 # number of demand (read+write) MSHR hits
917 system.cpu.icache.demand_mshr_hits::total 66573 # number of demand (read+write) MSHR hits
918 system.cpu.icache.overall_mshr_hits::cpu.inst 66573 # number of overall MSHR hits
919 system.cpu.icache.overall_mshr_hits::total 66573 # number of overall MSHR hits
920 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981903 # number of ReadReq MSHR misses
921 system.cpu.icache.ReadReq_mshr_misses::total 981903 # number of ReadReq MSHR misses
922 system.cpu.icache.demand_mshr_misses::cpu.inst 981903 # number of demand (read+write) MSHR misses
923 system.cpu.icache.demand_mshr_misses::total 981903 # number of demand (read+write) MSHR misses
924 system.cpu.icache.overall_mshr_misses::cpu.inst 981903 # number of overall MSHR misses
925 system.cpu.icache.overall_mshr_misses::total 981903 # number of overall MSHR misses
926 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13872010992 # number of ReadReq MSHR miss cycles
927 system.cpu.icache.ReadReq_mshr_miss_latency::total 13872010992 # number of ReadReq MSHR miss cycles
928 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13872010992 # number of demand (read+write) MSHR miss cycles
929 system.cpu.icache.demand_mshr_miss_latency::total 13872010992 # number of demand (read+write) MSHR miss cycles
930 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13872010992 # number of overall MSHR miss cycles
931 system.cpu.icache.overall_mshr_miss_latency::total 13872010992 # number of overall MSHR miss cycles
932 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for ReadReq accesses
933 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.110021 # mshr miss rate for ReadReq accesses
934 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for demand accesses
935 system.cpu.icache.demand_mshr_miss_rate::total 0.110021 # mshr miss rate for demand accesses
936 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for overall accesses
937 system.cpu.icache.overall_mshr_miss_rate::total 0.110021 # mshr miss rate for overall accesses
938 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14127.679610 # average ReadReq mshr miss latency
939 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14127.679610 # average ReadReq mshr miss latency
940 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency
941 system.cpu.icache.demand_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency
942 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency
943 system.cpu.icache.overall_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency
944 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
945 system.cpu.itb_walker_cache.tags.replacements 13612 # number of replacements
946 system.cpu.itb_walker_cache.tags.tagsinuse 6.021123 # Cycle average of tags in use
947 system.cpu.itb_walker_cache.tags.total_refs 25352 # Total number of references to valid blocks.
948 system.cpu.itb_walker_cache.tags.sampled_refs 13625 # Sample count of references to valid blocks.
949 system.cpu.itb_walker_cache.tags.avg_refs 1.860697 # Average number of references to valid blocks.
950 system.cpu.itb_walker_cache.tags.warmup_cycle 5116302133500 # Cycle when the warmup percentage was hit.
951 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.021123 # Average occupied blocks per requestor
952 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376320 # Average percentage of cache occupancy
953 system.cpu.itb_walker_cache.tags.occ_percent::total 0.376320 # Average percentage of cache occupancy
954 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
955 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
956 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
957 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
958 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
959 system.cpu.itb_walker_cache.tags.tag_accesses 94236 # Number of tag accesses
960 system.cpu.itb_walker_cache.tags.data_accesses 94236 # Number of data accesses
961 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25363 # number of ReadReq hits
962 system.cpu.itb_walker_cache.ReadReq_hits::total 25363 # number of ReadReq hits
963 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
964 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
965 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25365 # number of demand (read+write) hits
966 system.cpu.itb_walker_cache.demand_hits::total 25365 # number of demand (read+write) hits
967 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25365 # number of overall hits
968 system.cpu.itb_walker_cache.overall_hits::total 25365 # number of overall hits
969 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14502 # number of ReadReq misses
970 system.cpu.itb_walker_cache.ReadReq_misses::total 14502 # number of ReadReq misses
971 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14502 # number of demand (read+write) misses
972 system.cpu.itb_walker_cache.demand_misses::total 14502 # number of demand (read+write) misses
973 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14502 # number of overall misses
974 system.cpu.itb_walker_cache.overall_misses::total 14502 # number of overall misses
975 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176957500 # number of ReadReq miss cycles
976 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176957500 # number of ReadReq miss cycles
977 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176957500 # number of demand (read+write) miss cycles
978 system.cpu.itb_walker_cache.demand_miss_latency::total 176957500 # number of demand (read+write) miss cycles
979 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176957500 # number of overall miss cycles
980 system.cpu.itb_walker_cache.overall_miss_latency::total 176957500 # number of overall miss cycles
981 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39865 # number of ReadReq accesses(hits+misses)
982 system.cpu.itb_walker_cache.ReadReq_accesses::total 39865 # number of ReadReq accesses(hits+misses)
983 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
984 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
985 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39867 # number of demand (read+write) accesses
986 system.cpu.itb_walker_cache.demand_accesses::total 39867 # number of demand (read+write) accesses
987 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39867 # number of overall (read+write) accesses
988 system.cpu.itb_walker_cache.overall_accesses::total 39867 # number of overall (read+write) accesses
989 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363778 # miss rate for ReadReq accesses
990 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363778 # miss rate for ReadReq accesses
991 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363760 # miss rate for demand accesses
992 system.cpu.itb_walker_cache.demand_miss_rate::total 0.363760 # miss rate for demand accesses
993 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363760 # miss rate for overall accesses
994 system.cpu.itb_walker_cache.overall_miss_rate::total 0.363760 # miss rate for overall accesses
995 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12202.282444 # average ReadReq miss latency
996 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12202.282444 # average ReadReq miss latency
997 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency
998 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12202.282444 # average overall miss latency
999 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency
1000 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12202.282444 # average overall miss latency
1001 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1002 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1003 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1004 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1005 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1006 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1007 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1008 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1009 system.cpu.itb_walker_cache.writebacks::writebacks 2767 # number of writebacks
1010 system.cpu.itb_walker_cache.writebacks::total 2767 # number of writebacks
1011 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14502 # number of ReadReq MSHR misses
1012 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14502 # number of ReadReq MSHR misses
1013 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14502 # number of demand (read+write) MSHR misses
1014 system.cpu.itb_walker_cache.demand_mshr_misses::total 14502 # number of demand (read+write) MSHR misses
1015 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14502 # number of overall MSHR misses
1016 system.cpu.itb_walker_cache.overall_mshr_misses::total 14502 # number of overall MSHR misses
1017 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 162455500 # number of ReadReq MSHR miss cycles
1018 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 162455500 # number of ReadReq MSHR miss cycles
1019 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 162455500 # number of demand (read+write) MSHR miss cycles
1020 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 162455500 # number of demand (read+write) MSHR miss cycles
1021 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 162455500 # number of overall MSHR miss cycles
1022 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 162455500 # number of overall MSHR miss cycles
1023 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363778 # mshr miss rate for ReadReq accesses
1024 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363778 # mshr miss rate for ReadReq accesses
1025 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for demand accesses
1026 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363760 # mshr miss rate for demand accesses
1027 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for overall accesses
1028 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363760 # mshr miss rate for overall accesses
1029 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average ReadReq mshr miss latency
1030 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11202.282444 # average ReadReq mshr miss latency
1031 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency
1032 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency
1033 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency
1034 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency
1035 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1036 system.cpu.l2cache.tags.replacements 112087 # number of replacements
1037 system.cpu.l2cache.tags.tagsinuse 64799.238973 # Cycle average of tags in use
1038 system.cpu.l2cache.tags.total_refs 4898447 # Total number of references to valid blocks.
1039 system.cpu.l2cache.tags.sampled_refs 176177 # Sample count of references to valid blocks.
1040 system.cpu.l2cache.tags.avg_refs 27.804123 # Average number of references to valid blocks.
1041 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1042 system.cpu.l2cache.tags.occ_blocks::writebacks 50590.672109 # Average occupied blocks per requestor
1043 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.620858 # Average occupied blocks per requestor
1044 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139554 # Average occupied blocks per requestor
1045 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3112.121923 # Average occupied blocks per requestor
1046 system.cpu.l2cache.tags.occ_blocks::cpu.data 11083.684529 # Average occupied blocks per requestor
1047 system.cpu.l2cache.tags.occ_percent::writebacks 0.771952 # Average percentage of cache occupancy
1048 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000193 # Average percentage of cache occupancy
1049 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1050 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047487 # Average percentage of cache occupancy
1051 system.cpu.l2cache.tags.occ_percent::cpu.data 0.169124 # Average percentage of cache occupancy
1052 system.cpu.l2cache.tags.occ_percent::total 0.988758 # Average percentage of cache occupancy
1053 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64090 # Occupied blocks per task id
1054 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
1055 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 706 # Occupied blocks per task id
1056 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id
1057 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6108 # Occupied blocks per task id
1058 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53982 # Occupied blocks per task id
1059 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977936 # Percentage of cache occupancy per task id
1060 system.cpu.l2cache.tags.tag_accesses 43579518 # Number of tag accesses
1061 system.cpu.l2cache.tags.data_accesses 43579518 # Number of data accesses
1062 system.cpu.l2cache.WritebackDirty_hits::writebacks 1582394 # number of WritebackDirty hits
1063 system.cpu.l2cache.WritebackDirty_hits::total 1582394 # number of WritebackDirty hits
1064 system.cpu.l2cache.WritebackClean_hits::writebacks 980190 # number of WritebackClean hits
1065 system.cpu.l2cache.WritebackClean_hits::total 980190 # number of WritebackClean hits
1066 system.cpu.l2cache.UpgradeReq_hits::cpu.data 342 # number of UpgradeReq hits
1067 system.cpu.l2cache.UpgradeReq_hits::total 342 # number of UpgradeReq hits
1068 system.cpu.l2cache.ReadExReq_hits::cpu.data 155444 # number of ReadExReq hits
1069 system.cpu.l2cache.ReadExReq_hits::total 155444 # number of ReadExReq hits
1070 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 965615 # number of ReadCleanReq hits
1071 system.cpu.l2cache.ReadCleanReq_hits::total 965615 # number of ReadCleanReq hits
1072 system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 66816 # number of ReadSharedReq hits
1073 system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12095 # number of ReadSharedReq hits
1074 system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332257 # number of ReadSharedReq hits
1075 system.cpu.l2cache.ReadSharedReq_hits::total 1411168 # number of ReadSharedReq hits
1076 system.cpu.l2cache.demand_hits::cpu.dtb.walker 66816 # number of demand (read+write) hits
1077 system.cpu.l2cache.demand_hits::cpu.itb.walker 12095 # number of demand (read+write) hits
1078 system.cpu.l2cache.demand_hits::cpu.inst 965615 # number of demand (read+write) hits
1079 system.cpu.l2cache.demand_hits::cpu.data 1487701 # number of demand (read+write) hits
1080 system.cpu.l2cache.demand_hits::total 2532227 # number of demand (read+write) hits
1081 system.cpu.l2cache.overall_hits::cpu.dtb.walker 66816 # number of overall hits
1082 system.cpu.l2cache.overall_hits::cpu.itb.walker 12095 # number of overall hits
1083 system.cpu.l2cache.overall_hits::cpu.inst 965615 # number of overall hits
1084 system.cpu.l2cache.overall_hits::cpu.data 1487701 # number of overall hits
1085 system.cpu.l2cache.overall_hits::total 2532227 # number of overall hits
1086 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1438 # number of UpgradeReq misses
1087 system.cpu.l2cache.UpgradeReq_misses::total 1438 # number of UpgradeReq misses
1088 system.cpu.l2cache.ReadExReq_misses::cpu.data 132521 # number of ReadExReq misses
1089 system.cpu.l2cache.ReadExReq_misses::total 132521 # number of ReadExReq misses
1090 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16160 # number of ReadCleanReq misses
1091 system.cpu.l2cache.ReadCleanReq_misses::total 16160 # number of ReadCleanReq misses
1092 system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 60 # number of ReadSharedReq misses
1093 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
1094 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35761 # number of ReadSharedReq misses
1095 system.cpu.l2cache.ReadSharedReq_misses::total 35826 # number of ReadSharedReq misses
1096 system.cpu.l2cache.demand_misses::cpu.dtb.walker 60 # number of demand (read+write) misses
1097 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1098 system.cpu.l2cache.demand_misses::cpu.inst 16160 # number of demand (read+write) misses
1099 system.cpu.l2cache.demand_misses::cpu.data 168282 # number of demand (read+write) misses
1100 system.cpu.l2cache.demand_misses::total 184507 # number of demand (read+write) misses
1101 system.cpu.l2cache.overall_misses::cpu.dtb.walker 60 # number of overall misses
1102 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1103 system.cpu.l2cache.overall_misses::cpu.inst 16160 # number of overall misses
1104 system.cpu.l2cache.overall_misses::cpu.data 168282 # number of overall misses
1105 system.cpu.l2cache.overall_misses::total 184507 # number of overall misses
1106 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 57872000 # number of UpgradeReq miss cycles
1107 system.cpu.l2cache.UpgradeReq_miss_latency::total 57872000 # number of UpgradeReq miss cycles
1108 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16936777500 # number of ReadExReq miss cycles
1109 system.cpu.l2cache.ReadExReq_miss_latency::total 16936777500 # number of ReadExReq miss cycles
1110 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2166148500 # number of ReadCleanReq miss cycles
1111 system.cpu.l2cache.ReadCleanReq_miss_latency::total 2166148500 # number of ReadCleanReq miss cycles
1112 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 8579000 # number of ReadSharedReq miss cycles
1113 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 679000 # number of ReadSharedReq miss cycles
1114 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4824922500 # number of ReadSharedReq miss cycles
1115 system.cpu.l2cache.ReadSharedReq_miss_latency::total 4834180500 # number of ReadSharedReq miss cycles
1116 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 8579000 # number of demand (read+write) miss cycles
1117 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 679000 # number of demand (read+write) miss cycles
1118 system.cpu.l2cache.demand_miss_latency::cpu.inst 2166148500 # number of demand (read+write) miss cycles
1119 system.cpu.l2cache.demand_miss_latency::cpu.data 21761700000 # number of demand (read+write) miss cycles
1120 system.cpu.l2cache.demand_miss_latency::total 23937106500 # number of demand (read+write) miss cycles
1121 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 8579000 # number of overall miss cycles
1122 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679000 # number of overall miss cycles
1123 system.cpu.l2cache.overall_miss_latency::cpu.inst 2166148500 # number of overall miss cycles
1124 system.cpu.l2cache.overall_miss_latency::cpu.data 21761700000 # number of overall miss cycles
1125 system.cpu.l2cache.overall_miss_latency::total 23937106500 # number of overall miss cycles
1126 system.cpu.l2cache.WritebackDirty_accesses::writebacks 1582394 # number of WritebackDirty accesses(hits+misses)
1127 system.cpu.l2cache.WritebackDirty_accesses::total 1582394 # number of WritebackDirty accesses(hits+misses)
1128 system.cpu.l2cache.WritebackClean_accesses::writebacks 980190 # number of WritebackClean accesses(hits+misses)
1129 system.cpu.l2cache.WritebackClean_accesses::total 980190 # number of WritebackClean accesses(hits+misses)
1130 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1780 # number of UpgradeReq accesses(hits+misses)
1131 system.cpu.l2cache.UpgradeReq_accesses::total 1780 # number of UpgradeReq accesses(hits+misses)
1132 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287965 # number of ReadExReq accesses(hits+misses)
1133 system.cpu.l2cache.ReadExReq_accesses::total 287965 # number of ReadExReq accesses(hits+misses)
1134 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 981775 # number of ReadCleanReq accesses(hits+misses)
1135 system.cpu.l2cache.ReadCleanReq_accesses::total 981775 # number of ReadCleanReq accesses(hits+misses)
1136 system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 66876 # number of ReadSharedReq accesses(hits+misses)
1137 system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12100 # number of ReadSharedReq accesses(hits+misses)
1138 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368018 # number of ReadSharedReq accesses(hits+misses)
1139 system.cpu.l2cache.ReadSharedReq_accesses::total 1446994 # number of ReadSharedReq accesses(hits+misses)
1140 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 66876 # number of demand (read+write) accesses
1141 system.cpu.l2cache.demand_accesses::cpu.itb.walker 12100 # number of demand (read+write) accesses
1142 system.cpu.l2cache.demand_accesses::cpu.inst 981775 # number of demand (read+write) accesses
1143 system.cpu.l2cache.demand_accesses::cpu.data 1655983 # number of demand (read+write) accesses
1144 system.cpu.l2cache.demand_accesses::total 2716734 # number of demand (read+write) accesses
1145 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 66876 # number of overall (read+write) accesses
1146 system.cpu.l2cache.overall_accesses::cpu.itb.walker 12100 # number of overall (read+write) accesses
1147 system.cpu.l2cache.overall_accesses::cpu.inst 981775 # number of overall (read+write) accesses
1148 system.cpu.l2cache.overall_accesses::cpu.data 1655983 # number of overall (read+write) accesses
1149 system.cpu.l2cache.overall_accesses::total 2716734 # number of overall (read+write) accesses
1150 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807865 # miss rate for UpgradeReq accesses
1151 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807865 # miss rate for UpgradeReq accesses
1152 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460198 # miss rate for ReadExReq accesses
1153 system.cpu.l2cache.ReadExReq_miss_rate::total 0.460198 # miss rate for ReadExReq accesses
1154 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016460 # miss rate for ReadCleanReq accesses
1155 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016460 # miss rate for ReadCleanReq accesses
1156 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000897 # miss rate for ReadSharedReq accesses
1157 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000413 # miss rate for ReadSharedReq accesses
1158 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026141 # miss rate for ReadSharedReq accesses
1159 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024759 # miss rate for ReadSharedReq accesses
1160 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000897 # miss rate for demand accesses
1161 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000413 # miss rate for demand accesses
1162 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016460 # miss rate for demand accesses
1163 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101621 # miss rate for demand accesses
1164 system.cpu.l2cache.demand_miss_rate::total 0.067915 # miss rate for demand accesses
1165 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000897 # miss rate for overall accesses
1166 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000413 # miss rate for overall accesses
1167 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016460 # miss rate for overall accesses
1168 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101621 # miss rate for overall accesses
1169 system.cpu.l2cache.overall_miss_rate::total 0.067915 # miss rate for overall accesses
1170 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40244.784423 # average UpgradeReq miss latency
1171 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40244.784423 # average UpgradeReq miss latency
1172 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127804.480045 # average ReadExReq miss latency
1173 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127804.480045 # average ReadExReq miss latency
1174 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134043.842822 # average ReadCleanReq miss latency
1175 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134043.842822 # average ReadCleanReq miss latency
1176 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 142983.333333 # average ReadSharedReq miss latency
1177 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135800 # average ReadSharedReq miss latency
1178 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134921.352870 # average ReadSharedReq miss latency
1179 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134934.977391 # average ReadSharedReq miss latency
1180 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 142983.333333 # average overall miss latency
1181 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135800 # average overall miss latency
1182 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134043.842822 # average overall miss latency
1183 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129316.860983 # average overall miss latency
1184 system.cpu.l2cache.demand_avg_miss_latency::total 129735.492420 # average overall miss latency
1185 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 142983.333333 # average overall miss latency
1186 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135800 # average overall miss latency
1187 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134043.842822 # average overall miss latency
1188 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129316.860983 # average overall miss latency
1189 system.cpu.l2cache.overall_avg_miss_latency::total 129735.492420 # average overall miss latency
1190 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1191 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1192 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1193 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1194 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1195 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1196 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1197 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1198 system.cpu.l2cache.writebacks::writebacks 102517 # number of writebacks
1199 system.cpu.l2cache.writebacks::total 102517 # number of writebacks
1200 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
1201 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
1202 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1 # number of ReadSharedReq MSHR hits
1203 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
1204 system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
1205 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1206 system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
1207 system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
1208 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1209 system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
1210 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses
1211 system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses
1212 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1438 # number of UpgradeReq MSHR misses
1213 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1438 # number of UpgradeReq MSHR misses
1214 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132521 # number of ReadExReq MSHR misses
1215 system.cpu.l2cache.ReadExReq_mshr_misses::total 132521 # number of ReadExReq MSHR misses
1216 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16157 # number of ReadCleanReq MSHR misses
1217 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16157 # number of ReadCleanReq MSHR misses
1218 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 60 # number of ReadSharedReq MSHR misses
1219 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
1220 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35760 # number of ReadSharedReq MSHR misses
1221 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35825 # number of ReadSharedReq MSHR misses
1222 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 60 # number of demand (read+write) MSHR misses
1223 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1224 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16157 # number of demand (read+write) MSHR misses
1225 system.cpu.l2cache.demand_mshr_misses::cpu.data 168281 # number of demand (read+write) MSHR misses
1226 system.cpu.l2cache.demand_mshr_misses::total 184503 # number of demand (read+write) MSHR misses
1227 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 60 # number of overall MSHR misses
1228 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1229 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16157 # number of overall MSHR misses
1230 system.cpu.l2cache.overall_mshr_misses::cpu.data 168281 # number of overall MSHR misses
1231 system.cpu.l2cache.overall_mshr_misses::total 184503 # number of overall MSHR misses
1232 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable
1233 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable
1234 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable
1235 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable
1236 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses
1237 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses
1238 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102774999 # number of UpgradeReq MSHR miss cycles
1239 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102774999 # number of UpgradeReq MSHR miss cycles
1240 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15611567500 # number of ReadExReq MSHR miss cycles
1241 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15611567500 # number of ReadExReq MSHR miss cycles
1242 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2004346500 # number of ReadCleanReq MSHR miss cycles
1243 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2004346500 # number of ReadCleanReq MSHR miss cycles
1244 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 7979000 # number of ReadSharedReq MSHR miss cycles
1245 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles
1246 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4468306500 # number of ReadSharedReq MSHR miss cycles
1247 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4476914500 # number of ReadSharedReq MSHR miss cycles
1248 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 7979000 # number of demand (read+write) MSHR miss cycles
1249 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 629000 # number of demand (read+write) MSHR miss cycles
1250 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2004346500 # number of demand (read+write) MSHR miss cycles
1251 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20079874000 # number of demand (read+write) MSHR miss cycles
1252 system.cpu.l2cache.demand_mshr_miss_latency::total 22092828500 # number of demand (read+write) MSHR miss cycles
1253 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 7979000 # number of overall MSHR miss cycles
1254 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 629000 # number of overall MSHR miss cycles
1255 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2004346500 # number of overall MSHR miss cycles
1256 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20079874000 # number of overall MSHR miss cycles
1257 system.cpu.l2cache.overall_mshr_miss_latency::total 22092828500 # number of overall MSHR miss cycles
1258 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90946019500 # number of ReadReq MSHR uncacheable cycles
1259 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90946019500 # number of ReadReq MSHR uncacheable cycles
1260 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2618766000 # number of WriteReq MSHR uncacheable cycles
1261 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2618766000 # number of WriteReq MSHR uncacheable cycles
1262 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93564785500 # number of overall MSHR uncacheable cycles
1263 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93564785500 # number of overall MSHR uncacheable cycles
1264 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1265 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1266 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807865 # mshr miss rate for UpgradeReq accesses
1267 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807865 # mshr miss rate for UpgradeReq accesses
1268 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460198 # mshr miss rate for ReadExReq accesses
1269 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460198 # mshr miss rate for ReadExReq accesses
1270 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for ReadCleanReq accesses
1271 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016457 # mshr miss rate for ReadCleanReq accesses
1272 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for ReadSharedReq accesses
1273 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for ReadSharedReq accesses
1274 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026140 # mshr miss rate for ReadSharedReq accesses
1275 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024758 # mshr miss rate for ReadSharedReq accesses
1276 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for demand accesses
1277 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for demand accesses
1278 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for demand accesses
1279 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for demand accesses
1280 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067914 # mshr miss rate for demand accesses
1281 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for overall accesses
1282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for overall accesses
1283 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for overall accesses
1284 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for overall accesses
1285 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067914 # mshr miss rate for overall accesses
1286 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71470.792072 # average UpgradeReq mshr miss latency
1287 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71470.792072 # average UpgradeReq mshr miss latency
1288 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117804.480045 # average ReadExReq mshr miss latency
1289 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117804.480045 # average ReadExReq mshr miss latency
1290 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124054.372718 # average ReadCleanReq mshr miss latency
1291 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124054.372718 # average ReadCleanReq mshr miss latency
1292 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average ReadSharedReq mshr miss latency
1293 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125800 # average ReadSharedReq mshr miss latency
1294 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124952.642617 # average ReadSharedReq mshr miss latency
1295 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124966.210747 # average ReadSharedReq mshr miss latency
1296 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency
1297 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency
1298 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency
1299 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency
1300 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency
1301 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency
1302 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency
1303 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency
1304 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency
1305 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency
1306 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.740488 # average ReadReq mshr uncacheable latency
1307 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.740488 # average ReadReq mshr uncacheable latency
1308 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188413.986618 # average WriteReq mshr uncacheable latency
1309 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188413.986618 # average WriteReq mshr uncacheable latency
1310 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159297.440747 # average overall mshr uncacheable latency
1311 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159297.440747 # average overall mshr uncacheable latency
1312 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1313 system.cpu.toL2Bus.snoop_filter.tot_requests 5460741 # Total number of requests made to the snoop filter.
1314 system.cpu.toL2Bus.snoop_filter.hit_single_requests 2718937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1315 system.cpu.toL2Bus.snoop_filter.hit_multi_requests 72407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1316 system.cpu.toL2Bus.snoop_filter.tot_snoops 1221 # Total number of snoops made to the snoop filter.
1317 system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1221 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1318 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1319 system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution
1320 system.cpu.toL2Bus.trans_dist::ReadResp 3016607 # Transaction distribution
1321 system.cpu.toL2Bus.trans_dist::WriteReq 13899 # Transaction distribution
1322 system.cpu.toL2Bus.trans_dist::WriteResp 13899 # Transaction distribution
1323 system.cpu.toL2Bus.trans_dist::WritebackDirty 1731587 # Transaction distribution
1324 system.cpu.toL2Bus.trans_dist::WritebackClean 980190 # Transaction distribution
1325 system.cpu.toL2Bus.trans_dist::CleanEvict 117679 # Transaction distribution
1326 system.cpu.toL2Bus.trans_dist::UpgradeReq 2259 # Transaction distribution
1327 system.cpu.toL2Bus.trans_dist::UpgradeResp 2259 # Transaction distribution
1328 system.cpu.toL2Bus.trans_dist::ReadExReq 287973 # Transaction distribution
1329 system.cpu.toL2Bus.trans_dist::ReadExResp 287973 # Transaction distribution
1330 system.cpu.toL2Bus.trans_dist::ReadCleanReq 981903 # Transaction distribution
1331 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1461779 # Transaction distribution
1332 system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution
1333 system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution
1334 system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1335 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2943868 # Packet count per connected master and slave (bytes)
1336 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146532 # Packet count per connected master and slave (bytes)
1337 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31429 # Packet count per connected master and slave (bytes)
1338 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 174582 # Packet count per connected master and slave (bytes)
1339 system.cpu.toL2Bus.pkt_count::total 9296411 # Packet count per connected master and slave (bytes)
1340 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125565760 # Cumulative packet size per connected master and slave (bytes)
1341 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207412623 # Cumulative packet size per connected master and slave (bytes)
1342 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 951488 # Cumulative packet size per connected master and slave (bytes)
1343 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5659456 # Cumulative packet size per connected master and slave (bytes)
1344 system.cpu.toL2Bus.pkt_size::total 339589327 # Cumulative packet size per connected master and slave (bytes)
1345 system.cpu.toL2Bus.snoops 223808 # Total snoops (count)
1346 system.cpu.toL2Bus.snoop_fanout::samples 3529303 # Request fanout histogram
1347 system.cpu.toL2Bus.snoop_fanout::mean 0.021448 # Request fanout histogram
1348 system.cpu.toL2Bus.snoop_fanout::stdev 0.165576 # Request fanout histogram
1349 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1350 system.cpu.toL2Bus.snoop_fanout::0 3464951 98.18% 98.18% # Request fanout histogram
1351 system.cpu.toL2Bus.snoop_fanout::1 53009 1.50% 99.68% # Request fanout histogram
1352 system.cpu.toL2Bus.snoop_fanout::2 11343 0.32% 100.00% # Request fanout histogram
1353 system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
1354 system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1355 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1356 system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1357 system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1358 system.cpu.toL2Bus.snoop_fanout::total 3529303 # Request fanout histogram
1359 system.cpu.toL2Bus.reqLayer0.occupancy 5594725985 # Layer occupancy (ticks)
1360 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1361 system.cpu.toL2Bus.snoopLayer0.occupancy 671790 # Layer occupancy (ticks)
1362 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1363 system.cpu.toL2Bus.respLayer0.occupancy 1474740212 # Layer occupancy (ticks)
1364 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1365 system.cpu.toL2Bus.respLayer1.occupancy 3066745270 # Layer occupancy (ticks)
1366 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1367 system.cpu.toL2Bus.respLayer2.occupancy 21763478 # Layer occupancy (ticks)
1368 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1369 system.cpu.toL2Bus.respLayer3.occupancy 116728873 # Layer occupancy (ticks)
1370 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1371 system.iobus.trans_dist::ReadReq 212016 # Transaction distribution
1372 system.iobus.trans_dist::ReadResp 212016 # Transaction distribution
1373 system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
1374 system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
1375 system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
1376 system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
1377 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1386 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1387 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1388 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1389 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1390 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1391 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1392 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1393 system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
1394 system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes)
1395 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes)
1396 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes)
1397 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
1398 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
1399 system.iobus.pkt_count::total 542774 # Packet count per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1410 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1411 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1412 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1413 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1414 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1415 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1416 system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
1417 system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes)
1418 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes)
1419 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes)
1420 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
1421 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
1422 system.iobus.pkt_size::total 3262754 # Cumulative packet size per connected master and slave (bytes)
1423 system.iobus.reqLayer0.occupancy 3980596 # Layer occupancy (ticks)
1424 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
1426 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks)
1428 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer3.occupancy 10514500 # Layer occupancy (ticks)
1430 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer4.occupancy 1031500 # Layer occupancy (ticks)
1432 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks)
1434 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
1436 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer7.occupancy 32500 # Layer occupancy (ticks)
1438 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1439 system.iobus.reqLayer8.occupancy 300003000 # Layer occupancy (ticks)
1440 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1441 system.iobus.reqLayer9.occupancy 1175500 # Layer occupancy (ticks)
1442 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1443 system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
1444 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1445 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
1446 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1447 system.iobus.reqLayer13.occupancy 24561500 # Layer occupancy (ticks)
1448 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1449 system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
1450 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1451 system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
1452 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1453 system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks)
1454 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1455 system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
1456 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1457 system.iobus.reqLayer18.occupancy 241121329 # Layer occupancy (ticks)
1458 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1459 system.iobus.reqLayer19.occupancy 1231500 # Layer occupancy (ticks)
1460 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1461 system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks)
1462 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1463 system.iobus.respLayer1.occupancy 50160000 # Layer occupancy (ticks)
1464 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1465 system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
1466 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1467 system.iocache.tags.replacements 47569 # number of replacements
1468 system.iocache.tags.tagsinuse 0.116025 # Cycle average of tags in use
1469 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1470 system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
1471 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1472 system.iocache.tags.warmup_cycle 4999365177000 # Cycle when the warmup percentage was hit.
1473 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116025 # Average occupied blocks per requestor
1474 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007252 # Average percentage of cache occupancy
1475 system.iocache.tags.occ_percent::total 0.007252 # Average percentage of cache occupancy
1476 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1477 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1478 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1479 system.iocache.tags.tag_accesses 428616 # Number of tag accesses
1480 system.iocache.tags.data_accesses 428616 # Number of data accesses
1481 system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
1482 system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
1483 system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1484 system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
1485 system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
1486 system.iocache.demand_misses::total 904 # number of demand (read+write) misses
1487 system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
1488 system.iocache.overall_misses::total 904 # number of overall misses
1489 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145501183 # number of ReadReq miss cycles
1490 system.iocache.ReadReq_miss_latency::total 145501183 # number of ReadReq miss cycles
1491 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6077027146 # number of WriteLineReq miss cycles
1492 system.iocache.WriteLineReq_miss_latency::total 6077027146 # number of WriteLineReq miss cycles
1493 system.iocache.demand_miss_latency::pc.south_bridge.ide 145501183 # number of demand (read+write) miss cycles
1494 system.iocache.demand_miss_latency::total 145501183 # number of demand (read+write) miss cycles
1495 system.iocache.overall_miss_latency::pc.south_bridge.ide 145501183 # number of overall miss cycles
1496 system.iocache.overall_miss_latency::total 145501183 # number of overall miss cycles
1497 system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
1498 system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
1499 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1500 system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
1501 system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
1502 system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
1503 system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
1504 system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
1505 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1506 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1507 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1508 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1509 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1510 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1511 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1512 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1513 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average ReadReq miss latency
1514 system.iocache.ReadReq_avg_miss_latency::total 160952.636062 # average ReadReq miss latency
1515 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 130073.355009 # average WriteLineReq miss latency
1516 system.iocache.WriteLineReq_avg_miss_latency::total 130073.355009 # average WriteLineReq miss latency
1517 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency
1518 system.iocache.demand_avg_miss_latency::total 160952.636062 # average overall miss latency
1519 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency
1520 system.iocache.overall_avg_miss_latency::total 160952.636062 # average overall miss latency
1521 system.iocache.blocked_cycles::no_mshrs 1232 # number of cycles access was blocked
1522 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1523 system.iocache.blocked::no_mshrs 114 # number of cycles access was blocked
1524 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1525 system.iocache.avg_blocked_cycles::no_mshrs 10.807018 # average number of cycles each access was blocked
1526 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1527 system.iocache.fast_writes 0 # number of fast writes performed
1528 system.iocache.cache_copies 0 # number of cache copies performed
1529 system.iocache.writebacks::writebacks 46667 # number of writebacks
1530 system.iocache.writebacks::total 46667 # number of writebacks
1531 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses
1532 system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses
1533 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1534 system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
1535 system.iocache.demand_mshr_misses::pc.south_bridge.ide 904 # number of demand (read+write) MSHR misses
1536 system.iocache.demand_mshr_misses::total 904 # number of demand (read+write) MSHR misses
1537 system.iocache.overall_mshr_misses::pc.south_bridge.ide 904 # number of overall MSHR misses
1538 system.iocache.overall_mshr_misses::total 904 # number of overall MSHR misses
1539 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of ReadReq MSHR miss cycles
1540 system.iocache.ReadReq_mshr_miss_latency::total 100301183 # number of ReadReq MSHR miss cycles
1541 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3741027146 # number of WriteLineReq MSHR miss cycles
1542 system.iocache.WriteLineReq_mshr_miss_latency::total 3741027146 # number of WriteLineReq MSHR miss cycles
1543 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of demand (read+write) MSHR miss cycles
1544 system.iocache.demand_mshr_miss_latency::total 100301183 # number of demand (read+write) MSHR miss cycles
1545 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of overall MSHR miss cycles
1546 system.iocache.overall_mshr_miss_latency::total 100301183 # number of overall MSHR miss cycles
1547 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1548 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1549 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1550 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1551 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1552 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1553 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1554 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1555 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average ReadReq mshr miss latency
1556 system.iocache.ReadReq_avg_mshr_miss_latency::total 110952.636062 # average ReadReq mshr miss latency
1557 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80073.355009 # average WriteLineReq mshr miss latency
1558 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80073.355009 # average WriteLineReq mshr miss latency
1559 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency
1560 system.iocache.demand_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency
1561 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency
1562 system.iocache.overall_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency
1563 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1564 system.membus.trans_dist::ReadReq 573460 # Transaction distribution
1565 system.membus.trans_dist::ReadResp 626337 # Transaction distribution
1566 system.membus.trans_dist::WriteReq 13899 # Transaction distribution
1567 system.membus.trans_dist::WriteResp 13899 # Transaction distribution
1568 system.membus.trans_dist::WritebackDirty 149184 # Transaction distribution
1569 system.membus.trans_dist::CleanEvict 9829 # Transaction distribution
1570 system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution
1571 system.membus.trans_dist::UpgradeResp 1709 # Transaction distribution
1572 system.membus.trans_dist::ReadExReq 132252 # Transaction distribution
1573 system.membus.trans_dist::ReadExResp 132250 # Transaction distribution
1574 system.membus.trans_dist::ReadSharedReq 52886 # Transaction distribution
1575 system.membus.trans_dist::MessageReq 1645 # Transaction distribution
1576 system.membus.trans_dist::MessageResp 1645 # Transaction distribution
1577 system.membus.trans_dist::BadAddressError 9 # Transaction distribution
1578 system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
1579 system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
1580 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
1581 system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
1582 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes)
1583 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730482 # Packet count per connected master and slave (bytes)
1584 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 483648 # Packet count per connected master and slave (bytes)
1585 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes)
1586 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658384 # Packet count per connected master and slave (bytes)
1587 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141810 # Packet count per connected master and slave (bytes)
1588 system.membus.pkt_count_system.iocache.mem_side::total 141810 # Packet count per connected master and slave (bytes)
1589 system.membus.pkt_count::total 1803484 # Packet count per connected master and slave (bytes)
1590 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
1591 system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
1592 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes)
1593 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460961 # Cumulative packet size per connected master and slave (bytes)
1594 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18308608 # Cumulative packet size per connected master and slave (bytes)
1595 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19997967 # Cumulative packet size per connected master and slave (bytes)
1596 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
1597 system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
1598 system.membus.pkt_size::total 23019587 # Cumulative packet size per connected master and slave (bytes)
1599 system.membus.snoops 1629 # Total snoops (count)
1600 system.membus.snoop_fanout::samples 982619 # Request fanout histogram
1601 system.membus.snoop_fanout::mean 1.001674 # Request fanout histogram
1602 system.membus.snoop_fanout::stdev 0.040881 # Request fanout histogram
1603 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1604 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1605 system.membus.snoop_fanout::1 980974 99.83% 99.83% # Request fanout histogram
1606 system.membus.snoop_fanout::2 1645 0.17% 100.00% # Request fanout histogram
1607 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1608 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1609 system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1610 system.membus.snoop_fanout::total 982619 # Request fanout histogram
1611 system.membus.reqLayer0.occupancy 339006500 # Layer occupancy (ticks)
1612 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1613 system.membus.reqLayer1.occupancy 369115500 # Layer occupancy (ticks)
1614 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1615 system.membus.reqLayer2.occupancy 3980404 # Layer occupancy (ticks)
1616 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1617 system.membus.reqLayer3.occupancy 1013900787 # Layer occupancy (ticks)
1618 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1619 system.membus.reqLayer4.occupancy 12000 # Layer occupancy (ticks)
1620 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1621 system.membus.respLayer0.occupancy 2335404 # Layer occupancy (ticks)
1622 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1623 system.membus.respLayer2.occupancy 2139201818 # Layer occupancy (ticks)
1624 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1625 system.membus.respLayer4.occupancy 85763851 # Layer occupancy (ticks)
1626 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1627 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1628 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1629 system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
1630 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1631 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1632 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1633 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1634 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1635 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1636 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1637 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1638 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1639 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1640 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1642 ---------- End Simulation Statistics ----------
projects / gem5.git / blob