2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.154115 # Number of seconds simulated
4 sim_ticks 5154115247000 # Number of ticks simulated
5 final_tick 5154115247000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 128017 # Simulator instruction rate (inst/s)
8 host_op_rate 253040 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1617614851 # Simulator tick rate (ticks/s)
10 host_mem_usage 806232 # Number of bytes of host memory used
11 host_seconds 3186.24 # Real time elapsed on the host
12 sim_insts 407894468 # Number of instructions simulated
13 sim_ops 806246903 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 4480 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10813376 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11893632 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9584064 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9584064 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 70 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168959 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185838 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149751 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149751 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 869 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 203159 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2098008 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2307599 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 203159 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 203159 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1859497 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1859497 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1859497 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 869 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 203159 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2098008 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4167097 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185838 # Number of read requests accepted
52 system.physmem.writeReqs 149751 # Number of write requests accepted
53 system.physmem.readBursts 185838 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 149751 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11883456 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9582144 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11893632 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9584064 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11738 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 11323 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 11916 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11912 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 12271 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11705 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 10605 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 10992 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11596 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11415 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11752 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11610 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 11474 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12022 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11655 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11693 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 10141 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9357 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 8826 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 8882 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9347 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 9205 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 8767 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 8936 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 9149 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 9192 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 10057 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 9346 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9689 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9578 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 9663 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9586 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
97 system.physmem.totGap 5154115197500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185838 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 149751 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 171307 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11621 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 1958 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 473 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 54 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2253 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 2875 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 7881 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 7883 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 7770 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 7889 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 7857 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 9606 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 9971 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 11760 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 10283 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 9854 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 8546 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 9083 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 9183 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 7802 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 7680 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 7594 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 297 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 201 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 191 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 136 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 87 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 121 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 85 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 72428 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 296.370685 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 175.530831 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 319.820481 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 27904 38.53% 38.53% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17658 24.38% 62.91% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7456 10.29% 73.20% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4108 5.67% 78.87% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 2731 3.77% 82.64% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 1986 2.74% 85.39% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1581 2.18% 87.57% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1174 1.62% 89.19% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 7830 10.81% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 72428 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7352 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 25.252992 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 561.335686 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7351 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7352 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7352 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 20.364663 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 18.601623 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 13.168660 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6294 85.61% 85.61% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 82 1.12% 86.72% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 194 2.64% 89.36% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 86 1.17% 90.53% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 99 1.35% 91.88% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 218 2.97% 94.84% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 33 0.45% 95.29% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 11 0.15% 95.44% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 15 0.20% 95.65% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 6 0.08% 95.73% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 3 0.04% 95.77% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 3 0.04% 95.81% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 253 3.44% 99.25% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 5 0.07% 99.32% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 3 0.04% 99.36% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 7 0.10% 99.46% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 4 0.05% 99.51% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::100-103 3 0.04% 99.58% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::120-123 1 0.01% 99.59% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::124-127 3 0.04% 99.63% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::128-131 15 0.20% 99.84% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::total 7352 # Writes before turning the bus around for reads
264 system.physmem.totQLat 2003475850 # Total ticks spent queuing
265 system.physmem.totMemAccLat 5484957100 # Total ticks spent from burst creation until serviced by the DRAM
266 system.physmem.totBusLat 928395000 # Total ticks spent in databus transfers
267 system.physmem.avgQLat 10790.00 # Average queueing delay per DRAM burst
268 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
269 system.physmem.avgMemAccLat 29540.00 # Average memory access latency per DRAM burst
270 system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
271 system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s
272 system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s
273 system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s
274 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
275 system.physmem.busUtil 0.03 # Data bus utilization in percentage
276 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
277 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
278 system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
279 system.physmem.avgWrQLen 24.16 # Average write queue length when enqueuing
280 system.physmem.readRowHits 152313 # Number of row buffer hits during reads
281 system.physmem.writeRowHits 110658 # Number of row buffer hits during writes
282 system.physmem.readRowHitRate 82.03 # Row buffer hit rate for reads
283 system.physmem.writeRowHitRate 73.89 # Row buffer hit rate for writes
284 system.physmem.avgGap 15358415.20 # Average gap between requests
285 system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined
286 system.physmem_0.actEnergy 270738720 # Energy for activate commands per rank (pJ)
287 system.physmem_0.preEnergy 147724500 # Energy for precharge commands per rank (pJ)
288 system.physmem_0.readEnergy 721203600 # Energy for read commands per rank (pJ)
289 system.physmem_0.writeEnergy 476027280 # Energy for write commands per rank (pJ)
290 system.physmem_0.refreshEnergy 336641292000 # Energy for refresh commands per rank (pJ)
291 system.physmem_0.actBackEnergy 130240416060 # Energy for active background per rank (pJ)
292 system.physmem_0.preBackEnergy 2978219081250 # Energy for precharge background per rank (pJ)
293 system.physmem_0.totalEnergy 3446716483410 # Total energy per rank (pJ)
294 system.physmem_0.averagePower 668.731853 # Core power per rank (mW)
295 system.physmem_0.memoryStateTime::IDLE 4954469478230 # Time in different power states
296 system.physmem_0.memoryStateTime::REF 172107000000 # Time in different power states
297 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
298 system.physmem_0.memoryStateTime::ACT 27531969270 # Time in different power states
299 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
300 system.physmem_1.actEnergy 276816960 # Energy for activate commands per rank (pJ)
301 system.physmem_1.preEnergy 151041000 # Energy for precharge commands per rank (pJ)
302 system.physmem_1.readEnergy 727084800 # Energy for read commands per rank (pJ)
303 system.physmem_1.writeEnergy 494164800 # Energy for write commands per rank (pJ)
304 system.physmem_1.refreshEnergy 336641292000 # Energy for refresh commands per rank (pJ)
305 system.physmem_1.actBackEnergy 130162900905 # Energy for active background per rank (pJ)
306 system.physmem_1.preBackEnergy 2978287085250 # Energy for precharge background per rank (pJ)
307 system.physmem_1.totalEnergy 3446740385715 # Total energy per rank (pJ)
308 system.physmem_1.averagePower 668.736489 # Core power per rank (mW)
309 system.physmem_1.memoryStateTime::IDLE 4954592740478 # Time in different power states
310 system.physmem_1.memoryStateTime::REF 172107000000 # Time in different power states
311 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
312 system.physmem_1.memoryStateTime::ACT 27415396022 # Time in different power states
313 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
314 system.cpu.branchPred.lookups 86789700 # Number of BP lookups
315 system.cpu.branchPred.condPredicted 86789700 # Number of conditional branches predicted
316 system.cpu.branchPred.condIncorrect 894071 # Number of conditional branches incorrect
317 system.cpu.branchPred.BTBLookups 80040540 # Number of BTB lookups
318 system.cpu.branchPred.BTBHits 78122239 # Number of BTB hits
319 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
320 system.cpu.branchPred.BTBHitPct 97.603338 # BTB Hit Percentage
321 system.cpu.branchPred.usedRAS 1558682 # Number of times the RAS was used to get a target.
322 system.cpu.branchPred.RASInCorrect 180590 # Number of incorrect RAS predictions.
323 system.cpu_clk_domain.clock 500 # Clock period in ticks
324 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
325 system.cpu.numCycles 449504376 # number of cpu cycles simulated
326 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
327 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
328 system.cpu.fetch.icacheStallCycles 27485279 # Number of cycles fetch is stalled on an Icache miss
329 system.cpu.fetch.Insts 428718572 # Number of instructions fetch has processed
330 system.cpu.fetch.Branches 86789700 # Number of branches that fetch encountered
331 system.cpu.fetch.predictedBranches 79680921 # Number of branches that fetch has predicted taken
332 system.cpu.fetch.Cycles 418030666 # Number of cycles fetch has run and was not squashing or blocked
333 system.cpu.fetch.SquashCycles 1875632 # Number of cycles fetch has spent squashing
334 system.cpu.fetch.TlbCycles 150798 # Number of cycles fetch has spent waiting for tlb
335 system.cpu.fetch.MiscStallCycles 59488 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
336 system.cpu.fetch.PendingTrapStallCycles 208856 # Number of stall cycles due to pending traps
337 system.cpu.fetch.PendingQuiesceStallCycles 90 # Number of stall cycles due to pending quiesce instructions
338 system.cpu.fetch.IcacheWaitRetryStallCycles 672 # Number of stall cycles due to full MSHR
339 system.cpu.fetch.CacheLines 9123295 # Number of cache lines fetched
340 system.cpu.fetch.IcacheSquashes 449746 # Number of outstanding Icache misses that were squashed
341 system.cpu.fetch.ItlbSquashes 4755 # Number of outstanding ITLB misses that were squashed
342 system.cpu.fetch.rateDist::samples 446873665 # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::mean 1.892893 # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::stdev 3.051645 # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::0 281625965 63.02% 63.02% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::1 2138685 0.48% 63.50% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::2 72155487 16.15% 79.65% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::3 1568927 0.35% 80.00% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::4 2122343 0.47% 80.47% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::5 2325830 0.52% 80.99% # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::6 1507660 0.34% 81.33% # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::7 1867139 0.42% 81.75% # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.rateDist::8 81561629 18.25% 100.00% # Number of instructions fetched each cycle (Total)
355 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
356 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
357 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
358 system.cpu.fetch.rateDist::total 446873665 # Number of instructions fetched each cycle (Total)
359 system.cpu.fetch.branchRate 0.193079 # Number of branch fetches per cycle
360 system.cpu.fetch.rate 0.953758 # Number of inst fetches per cycle
361 system.cpu.decode.IdleCycles 22890187 # Number of cycles decode is idle
362 system.cpu.decode.BlockedCycles 264923803 # Number of cycles decode is blocked
363 system.cpu.decode.RunCycles 150702566 # Number of cycles decode is running
364 system.cpu.decode.UnblockCycles 7419293 # Number of cycles decode is unblocking
365 system.cpu.decode.SquashCycles 937816 # Number of cycles decode is squashing
366 system.cpu.decode.DecodedInsts 837865741 # Number of instructions handled by decode
367 system.cpu.rename.SquashCycles 937816 # Number of cycles rename is squashing
368 system.cpu.rename.IdleCycles 25728184 # Number of cycles rename is idle
369 system.cpu.rename.BlockCycles 222903682 # Number of cycles rename is blocking
370 system.cpu.rename.serializeStallCycles 12889746 # count of cycles rename stalled for serializing inst
371 system.cpu.rename.RunCycles 154594835 # Number of cycles rename is running
372 system.cpu.rename.UnblockCycles 29819402 # Number of cycles rename is unblocking
373 system.cpu.rename.RenamedInsts 834359795 # Number of instructions processed by rename
374 system.cpu.rename.ROBFullEvents 448369 # Number of times rename has blocked due to ROB full
375 system.cpu.rename.IQFullEvents 12212745 # Number of times rename has blocked due to IQ full
376 system.cpu.rename.LQFullEvents 141423 # Number of times rename has blocked due to LQ full
377 system.cpu.rename.SQFullEvents 14773604 # Number of times rename has blocked due to SQ full
378 system.cpu.rename.RenamedOperands 996662587 # Number of destination operands rename has renamed
379 system.cpu.rename.RenameLookups 1812180036 # Number of register rename lookups that rename has made
380 system.cpu.rename.int_rename_lookups 1114009606 # Number of integer rename lookups
381 system.cpu.rename.fp_rename_lookups 309 # Number of floating rename lookups
382 system.cpu.rename.CommittedMaps 964181963 # Number of HB maps that are committed
383 system.cpu.rename.UndoneMaps 32480622 # Number of HB maps that are undone due to squashing
384 system.cpu.rename.serializingInsts 461875 # count of serializing insts renamed
385 system.cpu.rename.tempSerializingInsts 465908 # count of temporary serializing insts renamed
386 system.cpu.rename.skidInsts 38538990 # count of insts added to the skid buffer
387 system.cpu.memDep0.insertedLoads 17255328 # Number of loads inserted to the mem dependence unit.
388 system.cpu.memDep0.insertedStores 10136845 # Number of stores inserted to the mem dependence unit.
389 system.cpu.memDep0.conflictingLoads 1286418 # Number of conflicting loads.
390 system.cpu.memDep0.conflictingStores 1053742 # Number of conflicting stores.
391 system.cpu.iq.iqInstsAdded 828858399 # Number of instructions added to the IQ (excludes non-spec)
392 system.cpu.iq.iqNonSpecInstsAdded 1188333 # Number of non-speculative instructions added to the IQ
393 system.cpu.iq.iqInstsIssued 823669123 # Number of instructions issued
394 system.cpu.iq.iqSquashedInstsIssued 243637 # Number of squashed instructions issued
395 system.cpu.iq.iqSquashedInstsExamined 23799824 # Number of squashed instructions iterated over during squash; mainly for profiling
396 system.cpu.iq.iqSquashedOperandsExamined 35821203 # Number of squashed operands that are examined and possibly removed from graph
397 system.cpu.iq.iqSquashedNonSpecRemoved 147900 # Number of squashed non-spec instructions that were removed
398 system.cpu.iq.issued_per_cycle::samples 446873665 # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::mean 1.843181 # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::stdev 2.418517 # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::0 262902763 58.83% 58.83% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::1 13828746 3.09% 61.93% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::2 9781500 2.19% 64.11% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::3 7055144 1.58% 65.69% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::4 74339132 16.64% 82.33% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::5 4387820 0.98% 83.31% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::6 72808347 16.29% 99.60% # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::7 1195469 0.27% 99.87% # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::8 574744 0.13% 100.00% # Number of insts issued each cycle
411 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
412 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
413 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
414 system.cpu.iq.issued_per_cycle::total 446873665 # Number of insts issued each cycle
415 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
416 system.cpu.iq.fu_full::IntAlu 1974081 71.95% 71.95% # attempts to use FU when none available
417 system.cpu.iq.fu_full::IntMult 0 0.00% 71.95% # attempts to use FU when none available
418 system.cpu.iq.fu_full::IntDiv 0 0.00% 71.95% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.95% # attempts to use FU when none available
420 system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.95% # attempts to use FU when none available
421 system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.95% # attempts to use FU when none available
422 system.cpu.iq.fu_full::FloatMult 0 0.00% 71.95% # attempts to use FU when none available
423 system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.95% # attempts to use FU when none available
424 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.95% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.95% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.95% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.95% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.95% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.95% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.95% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdMult 0 0.00% 71.95% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.95% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdShift 0 0.00% 71.95% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.95% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.95% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.95% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.95% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.95% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.95% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.95% # attempts to use FU when none available
441 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.95% # attempts to use FU when none available
442 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.95% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.95% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.95% # attempts to use FU when none available
445 system.cpu.iq.fu_full::MemRead 609151 22.20% 94.16% # attempts to use FU when none available
446 system.cpu.iq.fu_full::MemWrite 160307 5.84% 100.00% # attempts to use FU when none available
447 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
448 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
449 system.cpu.iq.FU_type_0::No_OpClass 285084 0.03% 0.03% # Type of FU issued
450 system.cpu.iq.FU_type_0::IntAlu 795424559 96.57% 96.61% # Type of FU issued
451 system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.62% # Type of FU issued
452 system.cpu.iq.FU_type_0::IntDiv 127671 0.02% 96.64% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued
455 system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.64% # Type of FU issued
456 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued
457 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued
458 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued
475 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued
476 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued
479 system.cpu.iq.FU_type_0::MemRead 18333357 2.23% 98.87% # Type of FU issued
480 system.cpu.iq.FU_type_0::MemWrite 9347919 1.13% 100.00% # Type of FU issued
481 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
482 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
483 system.cpu.iq.FU_type_0::total 823669123 # Type of FU issued
484 system.cpu.iq.rate 1.832394 # Inst issue rate
485 system.cpu.iq.fu_busy_cnt 2743541 # FU busy when requested
486 system.cpu.iq.fu_busy_rate 0.003331 # FU busy rate (busy events/executed inst)
487 system.cpu.iq.int_inst_queue_reads 2097198642 # Number of integer instruction queue reads
488 system.cpu.iq.int_inst_queue_writes 853858757 # Number of integer instruction queue writes
489 system.cpu.iq.int_inst_queue_wakeup_accesses 819128971 # Number of integer instruction queue wakeup accesses
490 system.cpu.iq.fp_inst_queue_reads 446 # Number of floating instruction queue reads
491 system.cpu.iq.fp_inst_queue_writes 432 # Number of floating instruction queue writes
492 system.cpu.iq.fp_inst_queue_wakeup_accesses 155 # Number of floating instruction queue wakeup accesses
493 system.cpu.iq.int_alu_accesses 826127364 # Number of integer alu accesses
494 system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses
495 system.cpu.iew.lsq.thread0.forwLoads 1863869 # Number of loads that had data forwarded from stores
496 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
497 system.cpu.iew.lsq.thread0.squashedLoads 3260732 # Number of loads squashed
498 system.cpu.iew.lsq.thread0.ignoredResponses 15309 # Number of memory responses ignored because the instruction is squashed
499 system.cpu.iew.lsq.thread0.memOrderViolation 14369 # Number of memory ordering violations
500 system.cpu.iew.lsq.thread0.squashedStores 1707925 # Number of stores squashed
501 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
502 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
503 system.cpu.iew.lsq.thread0.rescheduledLoads 2207612 # Number of loads that were rescheduled
504 system.cpu.iew.lsq.thread0.cacheBlocked 70919 # Number of times an access to memory failed due to the cache being blocked
505 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
506 system.cpu.iew.iewSquashCycles 937816 # Number of cycles IEW is squashing
507 system.cpu.iew.iewBlockCycles 204799790 # Number of cycles IEW is blocking
508 system.cpu.iew.iewUnblockCycles 10007204 # Number of cycles IEW is unblocking
509 system.cpu.iew.iewDispatchedInsts 830046732 # Number of instructions dispatched to IQ
510 system.cpu.iew.iewDispSquashedInsts 155850 # Number of squashed instructions skipped by dispatch
511 system.cpu.iew.iewDispLoadInsts 17255344 # Number of dispatched load instructions
512 system.cpu.iew.iewDispStoreInsts 10136845 # Number of dispatched store instructions
513 system.cpu.iew.iewDispNonSpecInsts 698572 # Number of dispatched non-speculative instructions
514 system.cpu.iew.iewIQFullEvents 395239 # Number of times the IQ has become full, causing a stall
515 system.cpu.iew.iewLSQFullEvents 8760495 # Number of times the LSQ has become full, causing a stall
516 system.cpu.iew.memOrderViolationEvents 14369 # Number of memory order violations
517 system.cpu.iew.predictedTakenIncorrect 514805 # Number of branches that were predicted taken incorrectly
518 system.cpu.iew.predictedNotTakenIncorrect 529588 # Number of branches that were predicted not taken incorrectly
519 system.cpu.iew.branchMispredicts 1044393 # Number of branch mispredicts detected at execute
520 system.cpu.iew.iewExecutedInsts 822053660 # Number of executed instructions
521 system.cpu.iew.iewExecLoadInsts 17935902 # Number of load instructions executed
522 system.cpu.iew.iewExecSquashedInsts 1483234 # Number of squashed instructions skipped in execute
523 system.cpu.iew.exec_swp 0 # number of swp insts executed
524 system.cpu.iew.exec_nop 0 # number of nop insts executed
525 system.cpu.iew.exec_refs 27057833 # number of memory reference insts executed
526 system.cpu.iew.exec_branches 83242296 # Number of branches executed
527 system.cpu.iew.exec_stores 9121931 # Number of stores executed
528 system.cpu.iew.exec_rate 1.828800 # Inst execution rate
529 system.cpu.iew.wb_sent 821550761 # cumulative count of insts sent to commit
530 system.cpu.iew.wb_count 819129126 # cumulative count of insts written-back
531 system.cpu.iew.wb_producers 640649566 # num instructions producing a value
532 system.cpu.iew.wb_consumers 1049893259 # num instructions consuming a value
533 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
534 system.cpu.iew.wb_rate 1.822294 # insts written-back per cycle
535 system.cpu.iew.wb_fanout 0.610204 # average fanout of values written-back
536 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
537 system.cpu.commit.commitSquashedInsts 23669936 # The number of squashed insts skipped by commit
538 system.cpu.commit.commitNonSpecStalls 1040433 # The number of times commit has been forced to stall to communicate backwards
539 system.cpu.commit.branchMispredicts 905908 # The number of times a branch was mispredicted
540 system.cpu.commit.committed_per_cycle::samples 443311497 # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::mean 1.818692 # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::stdev 2.674309 # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::0 272449194 61.46% 61.46% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::1 11181690 2.52% 63.98% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::2 3605884 0.81% 64.79% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::3 74618286 16.83% 81.63% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::4 2464935 0.56% 82.18% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::5 1628465 0.37% 82.55% # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::6 954634 0.22% 82.76% # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::7 70998554 16.02% 98.78% # Number of insts commited each cycle
552 system.cpu.commit.committed_per_cycle::8 5409855 1.22% 100.00% # Number of insts commited each cycle
553 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
554 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
555 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
556 system.cpu.commit.committed_per_cycle::total 443311497 # Number of insts commited each cycle
557 system.cpu.commit.committedInsts 407894468 # Number of instructions committed
558 system.cpu.commit.committedOps 806246903 # Number of ops (including micro ops) committed
559 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
560 system.cpu.commit.refs 22423531 # Number of memory references committed
561 system.cpu.commit.loads 13994611 # Number of loads committed
562 system.cpu.commit.membars 468283 # Number of memory barriers committed
563 system.cpu.commit.branches 82184111 # Number of branches committed
564 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
565 system.cpu.commit.int_insts 735078702 # Number of committed integer instructions.
566 system.cpu.commit.function_calls 1156217 # Number of function calls committed.
567 system.cpu.commit.op_class_0::No_OpClass 171842 0.02% 0.02% # Class of committed instruction
568 system.cpu.commit.op_class_0::IntAlu 783387641 97.16% 97.19% # Class of committed instruction
569 system.cpu.commit.op_class_0::IntMult 145035 0.02% 97.20% # Class of committed instruction
570 system.cpu.commit.op_class_0::IntDiv 121422 0.02% 97.22% # Class of committed instruction
571 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
572 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
573 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
574 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
575 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
576 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
577 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
578 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
579 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
580 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
581 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
582 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
583 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
584 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
585 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
586 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
587 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
588 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
593 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
595 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
596 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
597 system.cpu.commit.op_class_0::MemRead 13992027 1.74% 98.95% # Class of committed instruction
598 system.cpu.commit.op_class_0::MemWrite 8428920 1.05% 100.00% # Class of committed instruction
599 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
600 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
601 system.cpu.commit.op_class_0::total 806246903 # Class of committed instruction
602 system.cpu.commit.bw_lim_events 5409855 # number cycles where commit BW limit reached
603 system.cpu.rob.rob_reads 1267740043 # The number of ROB reads
604 system.cpu.rob.rob_writes 1663415417 # The number of ROB writes
605 system.cpu.timesIdled 288487 # Number of times that the entire CPU went into an idle state and unscheduled itself
606 system.cpu.idleCycles 2630711 # Total number of cycles that the CPU has spent unscheduled due to idling
607 system.cpu.quiesceCycles 9858723524 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
608 system.cpu.committedInsts 407894468 # Number of Instructions Simulated
609 system.cpu.committedOps 806246903 # Number of Ops (including micro ops) Simulated
610 system.cpu.cpi 1.102011 # CPI: Cycles Per Instruction
611 system.cpu.cpi_total 1.102011 # CPI: Total CPI of All Threads
612 system.cpu.ipc 0.907432 # IPC: Instructions Per Cycle
613 system.cpu.ipc_total 0.907432 # IPC: Total IPC of All Threads
614 system.cpu.int_regfile_reads 1091775121 # number of integer regfile reads
615 system.cpu.int_regfile_writes 655663425 # number of integer regfile writes
616 system.cpu.fp_regfile_reads 155 # number of floating regfile reads
617 system.cpu.cc_regfile_reads 416039105 # number of cc regfile reads
618 system.cpu.cc_regfile_writes 321913343 # number of cc regfile writes
619 system.cpu.misc_regfile_reads 265322894 # number of misc regfile reads
620 system.cpu.misc_regfile_writes 400562 # number of misc regfile writes
621 system.cpu.dcache.tags.replacements 1662098 # number of replacements
622 system.cpu.dcache.tags.tagsinuse 511.990156 # Cycle average of tags in use
623 system.cpu.dcache.tags.total_refs 19068760 # Total number of references to valid blocks.
624 system.cpu.dcache.tags.sampled_refs 1662610 # Sample count of references to valid blocks.
625 system.cpu.dcache.tags.avg_refs 11.469172 # Average number of references to valid blocks.
626 system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit.
627 system.cpu.dcache.tags.occ_blocks::cpu.data 511.990156 # Average occupied blocks per requestor
628 system.cpu.dcache.tags.occ_percent::cpu.data 0.999981 # Average percentage of cache occupancy
629 system.cpu.dcache.tags.occ_percent::total 0.999981 # Average percentage of cache occupancy
630 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
631 system.cpu.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
632 system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
633 system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
634 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
635 system.cpu.dcache.tags.tag_accesses 88153475 # Number of tag accesses
636 system.cpu.dcache.tags.data_accesses 88153475 # Number of data accesses
637 system.cpu.dcache.ReadReq_hits::cpu.data 10917190 # number of ReadReq hits
638 system.cpu.dcache.ReadReq_hits::total 10917190 # number of ReadReq hits
639 system.cpu.dcache.WriteReq_hits::cpu.data 8084600 # number of WriteReq hits
640 system.cpu.dcache.WriteReq_hits::total 8084600 # number of WriteReq hits
641 system.cpu.dcache.SoftPFReq_hits::cpu.data 64210 # number of SoftPFReq hits
642 system.cpu.dcache.SoftPFReq_hits::total 64210 # number of SoftPFReq hits
643 system.cpu.dcache.demand_hits::cpu.data 19001790 # number of demand (read+write) hits
644 system.cpu.dcache.demand_hits::total 19001790 # number of demand (read+write) hits
645 system.cpu.dcache.overall_hits::cpu.data 19066000 # number of overall hits
646 system.cpu.dcache.overall_hits::total 19066000 # number of overall hits
647 system.cpu.dcache.ReadReq_misses::cpu.data 1815691 # number of ReadReq misses
648 system.cpu.dcache.ReadReq_misses::total 1815691 # number of ReadReq misses
649 system.cpu.dcache.WriteReq_misses::cpu.data 334621 # number of WriteReq misses
650 system.cpu.dcache.WriteReq_misses::total 334621 # number of WriteReq misses
651 system.cpu.dcache.SoftPFReq_misses::cpu.data 406397 # number of SoftPFReq misses
652 system.cpu.dcache.SoftPFReq_misses::total 406397 # number of SoftPFReq misses
653 system.cpu.dcache.demand_misses::cpu.data 2150312 # number of demand (read+write) misses
654 system.cpu.dcache.demand_misses::total 2150312 # number of demand (read+write) misses
655 system.cpu.dcache.overall_misses::cpu.data 2556709 # number of overall misses
656 system.cpu.dcache.overall_misses::total 2556709 # number of overall misses
657 system.cpu.dcache.ReadReq_miss_latency::cpu.data 27046737500 # number of ReadReq miss cycles
658 system.cpu.dcache.ReadReq_miss_latency::total 27046737500 # number of ReadReq miss cycles
659 system.cpu.dcache.WriteReq_miss_latency::cpu.data 13846171242 # number of WriteReq miss cycles
660 system.cpu.dcache.WriteReq_miss_latency::total 13846171242 # number of WriteReq miss cycles
661 system.cpu.dcache.demand_miss_latency::cpu.data 40892908742 # number of demand (read+write) miss cycles
662 system.cpu.dcache.demand_miss_latency::total 40892908742 # number of demand (read+write) miss cycles
663 system.cpu.dcache.overall_miss_latency::cpu.data 40892908742 # number of overall miss cycles
664 system.cpu.dcache.overall_miss_latency::total 40892908742 # number of overall miss cycles
665 system.cpu.dcache.ReadReq_accesses::cpu.data 12732881 # number of ReadReq accesses(hits+misses)
666 system.cpu.dcache.ReadReq_accesses::total 12732881 # number of ReadReq accesses(hits+misses)
667 system.cpu.dcache.WriteReq_accesses::cpu.data 8419221 # number of WriteReq accesses(hits+misses)
668 system.cpu.dcache.WriteReq_accesses::total 8419221 # number of WriteReq accesses(hits+misses)
669 system.cpu.dcache.SoftPFReq_accesses::cpu.data 470607 # number of SoftPFReq accesses(hits+misses)
670 system.cpu.dcache.SoftPFReq_accesses::total 470607 # number of SoftPFReq accesses(hits+misses)
671 system.cpu.dcache.demand_accesses::cpu.data 21152102 # number of demand (read+write) accesses
672 system.cpu.dcache.demand_accesses::total 21152102 # number of demand (read+write) accesses
673 system.cpu.dcache.overall_accesses::cpu.data 21622709 # number of overall (read+write) accesses
674 system.cpu.dcache.overall_accesses::total 21622709 # number of overall (read+write) accesses
675 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142599 # miss rate for ReadReq accesses
676 system.cpu.dcache.ReadReq_miss_rate::total 0.142599 # miss rate for ReadReq accesses
677 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039745 # miss rate for WriteReq accesses
678 system.cpu.dcache.WriteReq_miss_rate::total 0.039745 # miss rate for WriteReq accesses
679 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863559 # miss rate for SoftPFReq accesses
680 system.cpu.dcache.SoftPFReq_miss_rate::total 0.863559 # miss rate for SoftPFReq accesses
681 system.cpu.dcache.demand_miss_rate::cpu.data 0.101659 # miss rate for demand accesses
682 system.cpu.dcache.demand_miss_rate::total 0.101659 # miss rate for demand accesses
683 system.cpu.dcache.overall_miss_rate::cpu.data 0.118242 # miss rate for overall accesses
684 system.cpu.dcache.overall_miss_rate::total 0.118242 # miss rate for overall accesses
685 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14896.112554 # average ReadReq miss latency
686 system.cpu.dcache.ReadReq_avg_miss_latency::total 14896.112554 # average ReadReq miss latency
687 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.667932 # average WriteReq miss latency
688 system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.667932 # average WriteReq miss latency
689 system.cpu.dcache.demand_avg_miss_latency::cpu.data 19017.197849 # average overall miss latency
690 system.cpu.dcache.demand_avg_miss_latency::total 19017.197849 # average overall miss latency
691 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15994.353969 # average overall miss latency
692 system.cpu.dcache.overall_avg_miss_latency::total 15994.353969 # average overall miss latency
693 system.cpu.dcache.blocked_cycles::no_mshrs 467851 # number of cycles access was blocked
694 system.cpu.dcache.blocked_cycles::no_targets 84 # number of cycles access was blocked
695 system.cpu.dcache.blocked::no_mshrs 51332 # number of cycles access was blocked
696 system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
697 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.114217 # average number of cycles each access was blocked
698 system.cpu.dcache.avg_blocked_cycles::no_targets 84 # average number of cycles each access was blocked
699 system.cpu.dcache.fast_writes 0 # number of fast writes performed
700 system.cpu.dcache.cache_copies 0 # number of cache copies performed
701 system.cpu.dcache.writebacks::writebacks 1563047 # number of writebacks
702 system.cpu.dcache.writebacks::total 1563047 # number of writebacks
703 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 843909 # number of ReadReq MSHR hits
704 system.cpu.dcache.ReadReq_mshr_hits::total 843909 # number of ReadReq MSHR hits
705 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44439 # number of WriteReq MSHR hits
706 system.cpu.dcache.WriteReq_mshr_hits::total 44439 # number of WriteReq MSHR hits
707 system.cpu.dcache.demand_mshr_hits::cpu.data 888348 # number of demand (read+write) MSHR hits
708 system.cpu.dcache.demand_mshr_hits::total 888348 # number of demand (read+write) MSHR hits
709 system.cpu.dcache.overall_mshr_hits::cpu.data 888348 # number of overall MSHR hits
710 system.cpu.dcache.overall_mshr_hits::total 888348 # number of overall MSHR hits
711 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971782 # number of ReadReq MSHR misses
712 system.cpu.dcache.ReadReq_mshr_misses::total 971782 # number of ReadReq MSHR misses
713 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290182 # number of WriteReq MSHR misses
714 system.cpu.dcache.WriteReq_mshr_misses::total 290182 # number of WriteReq MSHR misses
715 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402906 # number of SoftPFReq MSHR misses
716 system.cpu.dcache.SoftPFReq_mshr_misses::total 402906 # number of SoftPFReq MSHR misses
717 system.cpu.dcache.demand_mshr_misses::cpu.data 1261964 # number of demand (read+write) MSHR misses
718 system.cpu.dcache.demand_mshr_misses::total 1261964 # number of demand (read+write) MSHR misses
719 system.cpu.dcache.overall_mshr_misses::cpu.data 1664870 # number of overall MSHR misses
720 system.cpu.dcache.overall_mshr_misses::total 1664870 # number of overall MSHR misses
721 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602920 # number of ReadReq MSHR uncacheable
722 system.cpu.dcache.ReadReq_mshr_uncacheable::total 602920 # number of ReadReq MSHR uncacheable
723 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13934 # number of WriteReq MSHR uncacheable
724 system.cpu.dcache.WriteReq_mshr_uncacheable::total 13934 # number of WriteReq MSHR uncacheable
725 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616854 # number of overall MSHR uncacheable misses
726 system.cpu.dcache.overall_mshr_uncacheable_misses::total 616854 # number of overall MSHR uncacheable misses
727 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13356525500 # number of ReadReq MSHR miss cycles
728 system.cpu.dcache.ReadReq_mshr_miss_latency::total 13356525500 # number of ReadReq MSHR miss cycles
729 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12439701244 # number of WriteReq MSHR miss cycles
730 system.cpu.dcache.WriteReq_mshr_miss_latency::total 12439701244 # number of WriteReq MSHR miss cycles
731 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6060856500 # number of SoftPFReq MSHR miss cycles
732 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6060856500 # number of SoftPFReq MSHR miss cycles
733 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25796226744 # number of demand (read+write) MSHR miss cycles
734 system.cpu.dcache.demand_mshr_miss_latency::total 25796226744 # number of demand (read+write) MSHR miss cycles
735 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31857083244 # number of overall MSHR miss cycles
736 system.cpu.dcache.overall_mshr_miss_latency::total 31857083244 # number of overall MSHR miss cycles
737 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97797423500 # number of ReadReq MSHR uncacheable cycles
738 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97797423500 # number of ReadReq MSHR uncacheable cycles
739 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2624129500 # number of WriteReq MSHR uncacheable cycles
740 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2624129500 # number of WriteReq MSHR uncacheable cycles
741 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100421553000 # number of overall MSHR uncacheable cycles
742 system.cpu.dcache.overall_mshr_uncacheable_latency::total 100421553000 # number of overall MSHR uncacheable cycles
743 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076321 # mshr miss rate for ReadReq accesses
744 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076321 # mshr miss rate for ReadReq accesses
745 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034467 # mshr miss rate for WriteReq accesses
746 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034467 # mshr miss rate for WriteReq accesses
747 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.856141 # mshr miss rate for SoftPFReq accesses
748 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.856141 # mshr miss rate for SoftPFReq accesses
749 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059661 # mshr miss rate for demand accesses
750 system.cpu.dcache.demand_mshr_miss_rate::total 0.059661 # mshr miss rate for demand accesses
751 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076996 # mshr miss rate for overall accesses
752 system.cpu.dcache.overall_mshr_miss_rate::total 0.076996 # mshr miss rate for overall accesses
753 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.363962 # average ReadReq mshr miss latency
754 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.363962 # average ReadReq mshr miss latency
755 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42868.617778 # average WriteReq mshr miss latency
756 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42868.617778 # average WriteReq mshr miss latency
757 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15042.854909 # average SoftPFReq mshr miss latency
758 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15042.854909 # average SoftPFReq mshr miss latency
759 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20441.333306 # average overall mshr miss latency
760 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20441.333306 # average overall mshr miss latency
761 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19134.877344 # average overall mshr miss latency
762 system.cpu.dcache.overall_avg_mshr_miss_latency::total 19134.877344 # average overall mshr miss latency
763 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.301831 # average ReadReq mshr uncacheable latency
764 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.301831 # average ReadReq mshr uncacheable latency
765 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188325.642314 # average WriteReq mshr uncacheable latency
766 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188325.642314 # average WriteReq mshr uncacheable latency
767 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162796.306744 # average overall mshr uncacheable latency
768 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162796.306744 # average overall mshr uncacheable latency
769 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
770 system.cpu.dtb_walker_cache.tags.replacements 73546 # number of replacements
771 system.cpu.dtb_walker_cache.tags.tagsinuse 14.805379 # Cycle average of tags in use
772 system.cpu.dtb_walker_cache.tags.total_refs 113695 # Total number of references to valid blocks.
773 system.cpu.dtb_walker_cache.tags.sampled_refs 73561 # Sample count of references to valid blocks.
774 system.cpu.dtb_walker_cache.tags.avg_refs 1.545588 # Average number of references to valid blocks.
775 system.cpu.dtb_walker_cache.tags.warmup_cycle 5097093086500 # Cycle when the warmup percentage was hit.
776 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.805379 # Average occupied blocks per requestor
777 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.925336 # Average percentage of cache occupancy
778 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.925336 # Average percentage of cache occupancy
779 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
780 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
781 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
782 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
783 system.cpu.dtb_walker_cache.tags.tag_accesses 451096 # Number of tag accesses
784 system.cpu.dtb_walker_cache.tags.data_accesses 451096 # Number of data accesses
785 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113711 # number of ReadReq hits
786 system.cpu.dtb_walker_cache.ReadReq_hits::total 113711 # number of ReadReq hits
787 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113711 # number of demand (read+write) hits
788 system.cpu.dtb_walker_cache.demand_hits::total 113711 # number of demand (read+write) hits
789 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113711 # number of overall hits
790 system.cpu.dtb_walker_cache.overall_hits::total 113711 # number of overall hits
791 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74558 # number of ReadReq misses
792 system.cpu.dtb_walker_cache.ReadReq_misses::total 74558 # number of ReadReq misses
793 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74558 # number of demand (read+write) misses
794 system.cpu.dtb_walker_cache.demand_misses::total 74558 # number of demand (read+write) misses
795 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74558 # number of overall misses
796 system.cpu.dtb_walker_cache.overall_misses::total 74558 # number of overall misses
797 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 932190000 # number of ReadReq miss cycles
798 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 932190000 # number of ReadReq miss cycles
799 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 932190000 # number of demand (read+write) miss cycles
800 system.cpu.dtb_walker_cache.demand_miss_latency::total 932190000 # number of demand (read+write) miss cycles
801 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 932190000 # number of overall miss cycles
802 system.cpu.dtb_walker_cache.overall_miss_latency::total 932190000 # number of overall miss cycles
803 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 188269 # number of ReadReq accesses(hits+misses)
804 system.cpu.dtb_walker_cache.ReadReq_accesses::total 188269 # number of ReadReq accesses(hits+misses)
805 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 188269 # number of demand (read+write) accesses
806 system.cpu.dtb_walker_cache.demand_accesses::total 188269 # number of demand (read+write) accesses
807 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 188269 # number of overall (read+write) accesses
808 system.cpu.dtb_walker_cache.overall_accesses::total 188269 # number of overall (read+write) accesses
809 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396018 # miss rate for ReadReq accesses
810 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396018 # miss rate for ReadReq accesses
811 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396018 # miss rate for demand accesses
812 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396018 # miss rate for demand accesses
813 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396018 # miss rate for overall accesses
814 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396018 # miss rate for overall accesses
815 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12502.883661 # average ReadReq miss latency
816 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12502.883661 # average ReadReq miss latency
817 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12502.883661 # average overall miss latency
818 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12502.883661 # average overall miss latency
819 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12502.883661 # average overall miss latency
820 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12502.883661 # average overall miss latency
821 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
822 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
823 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
824 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
825 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
826 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
827 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
828 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
829 system.cpu.dtb_walker_cache.writebacks::writebacks 13222 # number of writebacks
830 system.cpu.dtb_walker_cache.writebacks::total 13222 # number of writebacks
831 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74558 # number of ReadReq MSHR misses
832 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74558 # number of ReadReq MSHR misses
833 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74558 # number of demand (read+write) MSHR misses
834 system.cpu.dtb_walker_cache.demand_mshr_misses::total 74558 # number of demand (read+write) MSHR misses
835 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74558 # number of overall MSHR misses
836 system.cpu.dtb_walker_cache.overall_mshr_misses::total 74558 # number of overall MSHR misses
837 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 857632000 # number of ReadReq MSHR miss cycles
838 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 857632000 # number of ReadReq MSHR miss cycles
839 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 857632000 # number of demand (read+write) MSHR miss cycles
840 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 857632000 # number of demand (read+write) MSHR miss cycles
841 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 857632000 # number of overall MSHR miss cycles
842 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 857632000 # number of overall MSHR miss cycles
843 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss rate for ReadReq accesses
844 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396018 # mshr miss rate for ReadReq accesses
845 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss rate for demand accesses
846 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396018 # mshr miss rate for demand accesses
847 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss rate for overall accesses
848 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396018 # mshr miss rate for overall accesses
849 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average ReadReq mshr miss latency
850 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11502.883661 # average ReadReq mshr miss latency
851 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average overall mshr miss latency
852 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11502.883661 # average overall mshr miss latency
853 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average overall mshr miss latency
854 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11502.883661 # average overall mshr miss latency
855 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
856 system.cpu.icache.tags.replacements 993321 # number of replacements
857 system.cpu.icache.tags.tagsinuse 508.961085 # Cycle average of tags in use
858 system.cpu.icache.tags.total_refs 8058871 # Total number of references to valid blocks.
859 system.cpu.icache.tags.sampled_refs 993832 # Sample count of references to valid blocks.
860 system.cpu.icache.tags.avg_refs 8.108887 # Average number of references to valid blocks.
861 system.cpu.icache.tags.warmup_cycle 147914027500 # Cycle when the warmup percentage was hit.
862 system.cpu.icache.tags.occ_blocks::cpu.inst 508.961085 # Average occupied blocks per requestor
863 system.cpu.icache.tags.occ_percent::cpu.inst 0.994065 # Average percentage of cache occupancy
864 system.cpu.icache.tags.occ_percent::total 0.994065 # Average percentage of cache occupancy
865 system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
866 system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
867 system.cpu.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
868 system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id
869 system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
870 system.cpu.icache.tags.tag_accesses 10117194 # Number of tag accesses
871 system.cpu.icache.tags.data_accesses 10117194 # Number of data accesses
872 system.cpu.icache.ReadReq_hits::cpu.inst 8058871 # number of ReadReq hits
873 system.cpu.icache.ReadReq_hits::total 8058871 # number of ReadReq hits
874 system.cpu.icache.demand_hits::cpu.inst 8058871 # number of demand (read+write) hits
875 system.cpu.icache.demand_hits::total 8058871 # number of demand (read+write) hits
876 system.cpu.icache.overall_hits::cpu.inst 8058871 # number of overall hits
877 system.cpu.icache.overall_hits::total 8058871 # number of overall hits
878 system.cpu.icache.ReadReq_misses::cpu.inst 1064420 # number of ReadReq misses
879 system.cpu.icache.ReadReq_misses::total 1064420 # number of ReadReq misses
880 system.cpu.icache.demand_misses::cpu.inst 1064420 # number of demand (read+write) misses
881 system.cpu.icache.demand_misses::total 1064420 # number of demand (read+write) misses
882 system.cpu.icache.overall_misses::cpu.inst 1064420 # number of overall misses
883 system.cpu.icache.overall_misses::total 1064420 # number of overall misses
884 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14809433489 # number of ReadReq miss cycles
885 system.cpu.icache.ReadReq_miss_latency::total 14809433489 # number of ReadReq miss cycles
886 system.cpu.icache.demand_miss_latency::cpu.inst 14809433489 # number of demand (read+write) miss cycles
887 system.cpu.icache.demand_miss_latency::total 14809433489 # number of demand (read+write) miss cycles
888 system.cpu.icache.overall_miss_latency::cpu.inst 14809433489 # number of overall miss cycles
889 system.cpu.icache.overall_miss_latency::total 14809433489 # number of overall miss cycles
890 system.cpu.icache.ReadReq_accesses::cpu.inst 9123291 # number of ReadReq accesses(hits+misses)
891 system.cpu.icache.ReadReq_accesses::total 9123291 # number of ReadReq accesses(hits+misses)
892 system.cpu.icache.demand_accesses::cpu.inst 9123291 # number of demand (read+write) accesses
893 system.cpu.icache.demand_accesses::total 9123291 # number of demand (read+write) accesses
894 system.cpu.icache.overall_accesses::cpu.inst 9123291 # number of overall (read+write) accesses
895 system.cpu.icache.overall_accesses::total 9123291 # number of overall (read+write) accesses
896 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116671 # miss rate for ReadReq accesses
897 system.cpu.icache.ReadReq_miss_rate::total 0.116671 # miss rate for ReadReq accesses
898 system.cpu.icache.demand_miss_rate::cpu.inst 0.116671 # miss rate for demand accesses
899 system.cpu.icache.demand_miss_rate::total 0.116671 # miss rate for demand accesses
900 system.cpu.icache.overall_miss_rate::cpu.inst 0.116671 # miss rate for overall accesses
901 system.cpu.icache.overall_miss_rate::total 0.116671 # miss rate for overall accesses
902 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13913.148465 # average ReadReq miss latency
903 system.cpu.icache.ReadReq_avg_miss_latency::total 13913.148465 # average ReadReq miss latency
904 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13913.148465 # average overall miss latency
905 system.cpu.icache.demand_avg_miss_latency::total 13913.148465 # average overall miss latency
906 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13913.148465 # average overall miss latency
907 system.cpu.icache.overall_avg_miss_latency::total 13913.148465 # average overall miss latency
908 system.cpu.icache.blocked_cycles::no_mshrs 6712 # number of cycles access was blocked
909 system.cpu.icache.blocked_cycles::no_targets 16 # number of cycles access was blocked
910 system.cpu.icache.blocked::no_mshrs 348 # number of cycles access was blocked
911 system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
912 system.cpu.icache.avg_blocked_cycles::no_mshrs 19.287356 # average number of cycles each access was blocked
913 system.cpu.icache.avg_blocked_cycles::no_targets 16 # average number of cycles each access was blocked
914 system.cpu.icache.fast_writes 0 # number of fast writes performed
915 system.cpu.icache.cache_copies 0 # number of cache copies performed
916 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70517 # number of ReadReq MSHR hits
917 system.cpu.icache.ReadReq_mshr_hits::total 70517 # number of ReadReq MSHR hits
918 system.cpu.icache.demand_mshr_hits::cpu.inst 70517 # number of demand (read+write) MSHR hits
919 system.cpu.icache.demand_mshr_hits::total 70517 # number of demand (read+write) MSHR hits
920 system.cpu.icache.overall_mshr_hits::cpu.inst 70517 # number of overall MSHR hits
921 system.cpu.icache.overall_mshr_hits::total 70517 # number of overall MSHR hits
922 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 993903 # number of ReadReq MSHR misses
923 system.cpu.icache.ReadReq_mshr_misses::total 993903 # number of ReadReq MSHR misses
924 system.cpu.icache.demand_mshr_misses::cpu.inst 993903 # number of demand (read+write) MSHR misses
925 system.cpu.icache.demand_mshr_misses::total 993903 # number of demand (read+write) MSHR misses
926 system.cpu.icache.overall_mshr_misses::cpu.inst 993903 # number of overall MSHR misses
927 system.cpu.icache.overall_mshr_misses::total 993903 # number of overall MSHR misses
928 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13139309991 # number of ReadReq MSHR miss cycles
929 system.cpu.icache.ReadReq_mshr_miss_latency::total 13139309991 # number of ReadReq MSHR miss cycles
930 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13139309991 # number of demand (read+write) MSHR miss cycles
931 system.cpu.icache.demand_mshr_miss_latency::total 13139309991 # number of demand (read+write) MSHR miss cycles
932 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13139309991 # number of overall MSHR miss cycles
933 system.cpu.icache.overall_mshr_miss_latency::total 13139309991 # number of overall MSHR miss cycles
934 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for ReadReq accesses
935 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108941 # mshr miss rate for ReadReq accesses
936 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for demand accesses
937 system.cpu.icache.demand_mshr_miss_rate::total 0.108941 # mshr miss rate for demand accesses
938 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for overall accesses
939 system.cpu.icache.overall_mshr_miss_rate::total 0.108941 # mshr miss rate for overall accesses
940 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13219.911793 # average ReadReq mshr miss latency
941 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13219.911793 # average ReadReq mshr miss latency
942 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13219.911793 # average overall mshr miss latency
943 system.cpu.icache.demand_avg_mshr_miss_latency::total 13219.911793 # average overall mshr miss latency
944 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13219.911793 # average overall mshr miss latency
945 system.cpu.icache.overall_avg_mshr_miss_latency::total 13219.911793 # average overall mshr miss latency
946 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
947 system.cpu.itb_walker_cache.tags.replacements 13951 # number of replacements
948 system.cpu.itb_walker_cache.tags.tagsinuse 6.067078 # Cycle average of tags in use
949 system.cpu.itb_walker_cache.tags.total_refs 26495 # Total number of references to valid blocks.
950 system.cpu.itb_walker_cache.tags.sampled_refs 13966 # Sample count of references to valid blocks.
951 system.cpu.itb_walker_cache.tags.avg_refs 1.897107 # Average number of references to valid blocks.
952 system.cpu.itb_walker_cache.tags.warmup_cycle 5104644726500 # Cycle when the warmup percentage was hit.
953 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.067078 # Average occupied blocks per requestor
954 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.379192 # Average percentage of cache occupancy
955 system.cpu.itb_walker_cache.tags.occ_percent::total 0.379192 # Average percentage of cache occupancy
956 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
957 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
958 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
959 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
960 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
961 system.cpu.itb_walker_cache.tags.tag_accesses 97508 # Number of tag accesses
962 system.cpu.itb_walker_cache.tags.data_accesses 97508 # Number of data accesses
963 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26495 # number of ReadReq hits
964 system.cpu.itb_walker_cache.ReadReq_hits::total 26495 # number of ReadReq hits
965 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
966 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
967 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26497 # number of demand (read+write) hits
968 system.cpu.itb_walker_cache.demand_hits::total 26497 # number of demand (read+write) hits
969 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26497 # number of overall hits
970 system.cpu.itb_walker_cache.overall_hits::total 26497 # number of overall hits
971 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14838 # number of ReadReq misses
972 system.cpu.itb_walker_cache.ReadReq_misses::total 14838 # number of ReadReq misses
973 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14838 # number of demand (read+write) misses
974 system.cpu.itb_walker_cache.demand_misses::total 14838 # number of demand (read+write) misses
975 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14838 # number of overall misses
976 system.cpu.itb_walker_cache.overall_misses::total 14838 # number of overall misses
977 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176788000 # number of ReadReq miss cycles
978 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176788000 # number of ReadReq miss cycles
979 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176788000 # number of demand (read+write) miss cycles
980 system.cpu.itb_walker_cache.demand_miss_latency::total 176788000 # number of demand (read+write) miss cycles
981 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176788000 # number of overall miss cycles
982 system.cpu.itb_walker_cache.overall_miss_latency::total 176788000 # number of overall miss cycles
983 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41333 # number of ReadReq accesses(hits+misses)
984 system.cpu.itb_walker_cache.ReadReq_accesses::total 41333 # number of ReadReq accesses(hits+misses)
985 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
986 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
987 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41335 # number of demand (read+write) accesses
988 system.cpu.itb_walker_cache.demand_accesses::total 41335 # number of demand (read+write) accesses
989 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41335 # number of overall (read+write) accesses
990 system.cpu.itb_walker_cache.overall_accesses::total 41335 # number of overall (read+write) accesses
991 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358987 # miss rate for ReadReq accesses
992 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358987 # miss rate for ReadReq accesses
993 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358969 # miss rate for demand accesses
994 system.cpu.itb_walker_cache.demand_miss_rate::total 0.358969 # miss rate for demand accesses
995 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358969 # miss rate for overall accesses
996 system.cpu.itb_walker_cache.overall_miss_rate::total 0.358969 # miss rate for overall accesses
997 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11914.543739 # average ReadReq miss latency
998 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11914.543739 # average ReadReq miss latency
999 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11914.543739 # average overall miss latency
1000 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11914.543739 # average overall miss latency
1001 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11914.543739 # average overall miss latency
1002 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11914.543739 # average overall miss latency
1003 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1004 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1005 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1006 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1007 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1008 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1009 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1010 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1011 system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks
1012 system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks
1013 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14838 # number of ReadReq MSHR misses
1014 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14838 # number of ReadReq MSHR misses
1015 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14838 # number of demand (read+write) MSHR misses
1016 system.cpu.itb_walker_cache.demand_mshr_misses::total 14838 # number of demand (read+write) MSHR misses
1017 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14838 # number of overall MSHR misses
1018 system.cpu.itb_walker_cache.overall_mshr_misses::total 14838 # number of overall MSHR misses
1019 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 161950000 # number of ReadReq MSHR miss cycles
1020 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 161950000 # number of ReadReq MSHR miss cycles
1021 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 161950000 # number of demand (read+write) MSHR miss cycles
1022 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 161950000 # number of demand (read+write) MSHR miss cycles
1023 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 161950000 # number of overall MSHR miss cycles
1024 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161950000 # number of overall MSHR miss cycles
1025 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358987 # mshr miss rate for ReadReq accesses
1026 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358987 # mshr miss rate for ReadReq accesses
1027 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358969 # mshr miss rate for demand accesses
1028 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358969 # mshr miss rate for demand accesses
1029 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358969 # mshr miss rate for overall accesses
1030 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358969 # mshr miss rate for overall accesses
1031 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average ReadReq mshr miss latency
1032 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10914.543739 # average ReadReq mshr miss latency
1033 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average overall mshr miss latency
1034 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10914.543739 # average overall mshr miss latency
1035 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average overall mshr miss latency
1036 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10914.543739 # average overall mshr miss latency
1037 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1038 system.cpu.l2cache.tags.replacements 112938 # number of replacements
1039 system.cpu.l2cache.tags.tagsinuse 64810.238427 # Cycle average of tags in use
1040 system.cpu.l2cache.tags.total_refs 4946164 # Total number of references to valid blocks.
1041 system.cpu.l2cache.tags.sampled_refs 176935 # Sample count of references to valid blocks.
1042 system.cpu.l2cache.tags.avg_refs 27.954695 # Average number of references to valid blocks.
1043 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1044 system.cpu.l2cache.tags.occ_blocks::writebacks 50458.579366 # Average occupied blocks per requestor
1045 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 20.514879 # Average occupied blocks per requestor
1046 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139418 # Average occupied blocks per requestor
1047 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3172.056588 # Average occupied blocks per requestor
1048 system.cpu.l2cache.tags.occ_blocks::cpu.data 11158.948175 # Average occupied blocks per requestor
1049 system.cpu.l2cache.tags.occ_percent::writebacks 0.769937 # Average percentage of cache occupancy
1050 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000313 # Average percentage of cache occupancy
1051 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1052 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048402 # Average percentage of cache occupancy
1053 system.cpu.l2cache.tags.occ_percent::cpu.data 0.170272 # Average percentage of cache occupancy
1054 system.cpu.l2cache.tags.occ_percent::total 0.988926 # Average percentage of cache occupancy
1055 system.cpu.l2cache.tags.occ_task_id_blocks::1024 63997 # Occupied blocks per task id
1056 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
1057 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id
1058 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id
1059 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5567 # Occupied blocks per task id
1060 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54302 # Occupied blocks per task id
1061 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976517 # Percentage of cache occupancy per task id
1062 system.cpu.l2cache.tags.tag_accesses 43925036 # Number of tag accesses
1063 system.cpu.l2cache.tags.data_accesses 43925036 # Number of data accesses
1064 system.cpu.l2cache.Writeback_hits::writebacks 1577768 # number of Writeback hits
1065 system.cpu.l2cache.Writeback_hits::total 1577768 # number of Writeback hits
1066 system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
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1071 system.cpu.l2cache.ReadCleanReq_hits::total 977435 # number of ReadCleanReq hits
1072 system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 69221 # number of ReadSharedReq hits
1073 system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12891 # number of ReadSharedReq hits
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1076 system.cpu.l2cache.demand_hits::cpu.dtb.walker 69221 # number of demand (read+write) hits
1077 system.cpu.l2cache.demand_hits::cpu.itb.walker 12891 # number of demand (read+write) hits
1078 system.cpu.l2cache.demand_hits::cpu.inst 977435 # number of demand (read+write) hits
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1081 system.cpu.l2cache.overall_hits::cpu.dtb.walker 69221 # number of overall hits
1082 system.cpu.l2cache.overall_hits::cpu.itb.walker 12891 # number of overall hits
1083 system.cpu.l2cache.overall_hits::cpu.inst 977435 # number of overall hits
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1085 system.cpu.l2cache.overall_hits::total 2551723 # number of overall hits
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1087 system.cpu.l2cache.UpgradeReq_misses::total 1505 # number of UpgradeReq misses
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1089 system.cpu.l2cache.ReadExReq_misses::total 134154 # number of ReadExReq misses
1090 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16363 # number of ReadCleanReq misses
1091 system.cpu.l2cache.ReadCleanReq_misses::total 16363 # number of ReadCleanReq misses
1092 system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 70 # number of ReadSharedReq misses
1093 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
1094 system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35783 # number of ReadSharedReq misses
1095 system.cpu.l2cache.ReadSharedReq_misses::total 35858 # number of ReadSharedReq misses
1096 system.cpu.l2cache.demand_misses::cpu.dtb.walker 70 # number of demand (read+write) misses
1097 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1098 system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses
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1101 system.cpu.l2cache.overall_misses::cpu.dtb.walker 70 # number of overall misses
1102 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1103 system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses
1104 system.cpu.l2cache.overall_misses::cpu.data 169937 # number of overall misses
1105 system.cpu.l2cache.overall_misses::total 186375 # number of overall misses
1106 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23274500 # number of UpgradeReq miss cycles
1107 system.cpu.l2cache.UpgradeReq_miss_latency::total 23274500 # number of UpgradeReq miss cycles
1108 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10328890000 # number of ReadExReq miss cycles
1109 system.cpu.l2cache.ReadExReq_miss_latency::total 10328890000 # number of ReadExReq miss cycles
1110 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1358981500 # number of ReadCleanReq miss cycles
1111 system.cpu.l2cache.ReadCleanReq_miss_latency::total 1358981500 # number of ReadCleanReq miss cycles
1112 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 6541000 # number of ReadSharedReq miss cycles
1113 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 429500 # number of ReadSharedReq miss cycles
1114 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3085479000 # number of ReadSharedReq miss cycles
1115 system.cpu.l2cache.ReadSharedReq_miss_latency::total 3092449500 # number of ReadSharedReq miss cycles
1116 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6541000 # number of demand (read+write) miss cycles
1117 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 429500 # number of demand (read+write) miss cycles
1118 system.cpu.l2cache.demand_miss_latency::cpu.inst 1358981500 # number of demand (read+write) miss cycles
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1120 system.cpu.l2cache.demand_miss_latency::total 14780321000 # number of demand (read+write) miss cycles
1121 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6541000 # number of overall miss cycles
1122 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 429500 # number of overall miss cycles
1123 system.cpu.l2cache.overall_miss_latency::cpu.inst 1358981500 # number of overall miss cycles
1124 system.cpu.l2cache.overall_miss_latency::cpu.data 13414369000 # number of overall miss cycles
1125 system.cpu.l2cache.overall_miss_latency::total 14780321000 # number of overall miss cycles
1126 system.cpu.l2cache.Writeback_accesses::writebacks 1577768 # number of Writeback accesses(hits+misses)
1127 system.cpu.l2cache.Writeback_accesses::total 1577768 # number of Writeback accesses(hits+misses)
1128 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1814 # number of UpgradeReq accesses(hits+misses)
1129 system.cpu.l2cache.UpgradeReq_accesses::total 1814 # number of UpgradeReq accesses(hits+misses)
1130 system.cpu.l2cache.ReadExReq_accesses::cpu.data 288081 # number of ReadExReq accesses(hits+misses)
1131 system.cpu.l2cache.ReadExReq_accesses::total 288081 # number of ReadExReq accesses(hits+misses)
1132 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 993798 # number of ReadCleanReq accesses(hits+misses)
1133 system.cpu.l2cache.ReadCleanReq_accesses::total 993798 # number of ReadCleanReq accesses(hits+misses)
1134 system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 69291 # number of ReadSharedReq accesses(hits+misses)
1135 system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12896 # number of ReadSharedReq accesses(hits+misses)
1136 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1374032 # number of ReadSharedReq accesses(hits+misses)
1137 system.cpu.l2cache.ReadSharedReq_accesses::total 1456219 # number of ReadSharedReq accesses(hits+misses)
1138 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69291 # number of demand (read+write) accesses
1139 system.cpu.l2cache.demand_accesses::cpu.itb.walker 12896 # number of demand (read+write) accesses
1140 system.cpu.l2cache.demand_accesses::cpu.inst 993798 # number of demand (read+write) accesses
1141 system.cpu.l2cache.demand_accesses::cpu.data 1662113 # number of demand (read+write) accesses
1142 system.cpu.l2cache.demand_accesses::total 2738098 # number of demand (read+write) accesses
1143 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69291 # number of overall (read+write) accesses
1144 system.cpu.l2cache.overall_accesses::cpu.itb.walker 12896 # number of overall (read+write) accesses
1145 system.cpu.l2cache.overall_accesses::cpu.inst 993798 # number of overall (read+write) accesses
1146 system.cpu.l2cache.overall_accesses::cpu.data 1662113 # number of overall (read+write) accesses
1147 system.cpu.l2cache.overall_accesses::total 2738098 # number of overall (read+write) accesses
1148 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.829658 # miss rate for UpgradeReq accesses
1149 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.829658 # miss rate for UpgradeReq accesses
1150 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.465682 # miss rate for ReadExReq accesses
1151 system.cpu.l2cache.ReadExReq_miss_rate::total 0.465682 # miss rate for ReadExReq accesses
1152 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016465 # miss rate for ReadCleanReq accesses
1153 system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016465 # miss rate for ReadCleanReq accesses
1154 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.001010 # miss rate for ReadSharedReq accesses
1155 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000388 # miss rate for ReadSharedReq accesses
1156 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026042 # miss rate for ReadSharedReq accesses
1157 system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024624 # miss rate for ReadSharedReq accesses
1158 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001010 # miss rate for demand accesses
1159 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000388 # miss rate for demand accesses
1160 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016465 # miss rate for demand accesses
1161 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102242 # miss rate for demand accesses
1162 system.cpu.l2cache.demand_miss_rate::total 0.068067 # miss rate for demand accesses
1163 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001010 # miss rate for overall accesses
1164 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000388 # miss rate for overall accesses
1165 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016465 # miss rate for overall accesses
1166 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102242 # miss rate for overall accesses
1167 system.cpu.l2cache.overall_miss_rate::total 0.068067 # miss rate for overall accesses
1168 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15464.784053 # average UpgradeReq miss latency
1169 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15464.784053 # average UpgradeReq miss latency
1170 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76992.784412 # average ReadExReq miss latency
1171 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76992.784412 # average ReadExReq miss latency
1172 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83052.099248 # average ReadCleanReq miss latency
1173 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83052.099248 # average ReadCleanReq miss latency
1174 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 93442.857143 # average ReadSharedReq miss latency
1175 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 85900 # average ReadSharedReq miss latency
1176 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86227.510270 # average ReadSharedReq miss latency
1177 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86241.550003 # average ReadSharedReq miss latency
1178 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93442.857143 # average overall miss latency
1179 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 85900 # average overall miss latency
1180 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83052.099248 # average overall miss latency
1181 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78937.306178 # average overall miss latency
1182 system.cpu.l2cache.demand_avg_miss_latency::total 79304.203890 # average overall miss latency
1183 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93442.857143 # average overall miss latency
1184 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 85900 # average overall miss latency
1185 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83052.099248 # average overall miss latency
1186 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78937.306178 # average overall miss latency
1187 system.cpu.l2cache.overall_avg_miss_latency::total 79304.203890 # average overall miss latency
1188 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1189 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1190 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1191 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1192 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1193 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1194 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1195 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1196 system.cpu.l2cache.writebacks::writebacks 103084 # number of writebacks
1197 system.cpu.l2cache.writebacks::total 103084 # number of writebacks
1198 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
1199 system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
1200 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits
1201 system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits
1202 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1203 system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
1204 system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
1205 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1206 system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
1207 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
1208 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 88 # number of CleanEvict MSHR misses
1209 system.cpu.l2cache.CleanEvict_mshr_misses::total 88 # number of CleanEvict MSHR misses
1210 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1505 # number of UpgradeReq MSHR misses
1211 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1505 # number of UpgradeReq MSHR misses
1212 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134154 # number of ReadExReq MSHR misses
1213 system.cpu.l2cache.ReadExReq_mshr_misses::total 134154 # number of ReadExReq MSHR misses
1214 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16361 # number of ReadCleanReq MSHR misses
1215 system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16361 # number of ReadCleanReq MSHR misses
1216 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 70 # number of ReadSharedReq MSHR misses
1217 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
1218 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35779 # number of ReadSharedReq MSHR misses
1219 system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35854 # number of ReadSharedReq MSHR misses
1220 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 70 # number of demand (read+write) MSHR misses
1221 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1222 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses
1223 system.cpu.l2cache.demand_mshr_misses::cpu.data 169933 # number of demand (read+write) MSHR misses
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1225 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 70 # number of overall MSHR misses
1226 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1227 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
1228 system.cpu.l2cache.overall_mshr_misses::cpu.data 169933 # number of overall MSHR misses
1229 system.cpu.l2cache.overall_mshr_misses::total 186369 # number of overall MSHR misses
1230 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602920 # number of ReadReq MSHR uncacheable
1231 system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602920 # number of ReadReq MSHR uncacheable
1232 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13934 # number of WriteReq MSHR uncacheable
1233 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13934 # number of WriteReq MSHR uncacheable
1234 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616854 # number of overall MSHR uncacheable misses
1235 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616854 # number of overall MSHR uncacheable misses
1236 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 32097000 # number of UpgradeReq MSHR miss cycles
1237 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 32097000 # number of UpgradeReq MSHR miss cycles
1238 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8987350000 # number of ReadExReq MSHR miss cycles
1239 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8987350000 # number of ReadExReq MSHR miss cycles
1240 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1195241000 # number of ReadCleanReq MSHR miss cycles
1241 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1195241000 # number of ReadCleanReq MSHR miss cycles
1242 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 5841000 # number of ReadSharedReq MSHR miss cycles
1243 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 379500 # number of ReadSharedReq MSHR miss cycles
1244 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2728894000 # number of ReadSharedReq MSHR miss cycles
1245 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2735114500 # number of ReadSharedReq MSHR miss cycles
1246 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5841000 # number of demand (read+write) MSHR miss cycles
1247 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 379500 # number of demand (read+write) MSHR miss cycles
1248 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1195241000 # number of demand (read+write) MSHR miss cycles
1249 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11716244000 # number of demand (read+write) MSHR miss cycles
1250 system.cpu.l2cache.demand_mshr_miss_latency::total 12917705500 # number of demand (read+write) MSHR miss cycles
1251 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5841000 # number of overall MSHR miss cycles
1252 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 379500 # number of overall MSHR miss cycles
1253 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1195241000 # number of overall MSHR miss cycles
1254 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11716244000 # number of overall MSHR miss cycles
1255 system.cpu.l2cache.overall_mshr_miss_latency::total 12917705500 # number of overall MSHR miss cycles
1256 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90260915500 # number of ReadReq MSHR uncacheable cycles
1257 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90260915500 # number of ReadReq MSHR uncacheable cycles
1258 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2463879500 # number of WriteReq MSHR uncacheable cycles
1259 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2463879500 # number of WriteReq MSHR uncacheable cycles
1260 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92724795000 # number of overall MSHR uncacheable cycles
1261 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92724795000 # number of overall MSHR uncacheable cycles
1262 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1263 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1264 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829658 # mshr miss rate for UpgradeReq accesses
1265 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829658 # mshr miss rate for UpgradeReq accesses
1266 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465682 # mshr miss rate for ReadExReq accesses
1267 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465682 # mshr miss rate for ReadExReq accesses
1268 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016463 # mshr miss rate for ReadCleanReq accesses
1269 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016463 # mshr miss rate for ReadCleanReq accesses
1270 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.001010 # mshr miss rate for ReadSharedReq accesses
1271 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000388 # mshr miss rate for ReadSharedReq accesses
1272 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026039 # mshr miss rate for ReadSharedReq accesses
1273 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024621 # mshr miss rate for ReadSharedReq accesses
1274 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001010 # mshr miss rate for demand accesses
1275 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000388 # mshr miss rate for demand accesses
1276 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016463 # mshr miss rate for demand accesses
1277 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102239 # mshr miss rate for demand accesses
1278 system.cpu.l2cache.demand_mshr_miss_rate::total 0.068065 # mshr miss rate for demand accesses
1279 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001010 # mshr miss rate for overall accesses
1280 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000388 # mshr miss rate for overall accesses
1281 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016463 # mshr miss rate for overall accesses
1282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102239 # mshr miss rate for overall accesses
1283 system.cpu.l2cache.overall_mshr_miss_rate::total 0.068065 # mshr miss rate for overall accesses
1284 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21326.910299 # average UpgradeReq mshr miss latency
1285 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21326.910299 # average UpgradeReq mshr miss latency
1286 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66992.784412 # average ReadExReq mshr miss latency
1287 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66992.784412 # average ReadExReq mshr miss latency
1288 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73054.275411 # average ReadCleanReq mshr miss latency
1289 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73054.275411 # average ReadCleanReq mshr miss latency
1290 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average ReadSharedReq mshr miss latency
1291 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75900 # average ReadSharedReq mshr miss latency
1292 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76270.829257 # average ReadSharedReq mshr miss latency
1293 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76284.779941 # average ReadSharedReq mshr miss latency
1294 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average overall mshr miss latency
1295 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75900 # average overall mshr miss latency
1296 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73054.275411 # average overall mshr miss latency
1297 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68946.255289 # average overall mshr miss latency
1298 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69312.522469 # average overall mshr miss latency
1299 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average overall mshr miss latency
1300 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75900 # average overall mshr miss latency
1301 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73054.275411 # average overall mshr miss latency
1302 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68946.255289 # average overall mshr miss latency
1303 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69312.522469 # average overall mshr miss latency
1304 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.288562 # average ReadReq mshr uncacheable latency
1305 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.288562 # average ReadReq mshr uncacheable latency
1306 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176824.996412 # average WriteReq mshr uncacheable latency
1307 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176824.996412 # average WriteReq mshr uncacheable latency
1308 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150318.867998 # average overall mshr uncacheable latency
1309 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150318.867998 # average overall mshr uncacheable latency
1310 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1311 system.cpu.toL2Bus.trans_dist::ReadReq 602920 # Transaction distribution
1312 system.cpu.toL2Bus.trans_dist::ReadResp 3061153 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::WriteReq 13934 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::WriteResp 13934 # Transaction distribution
1315 system.cpu.toL2Bus.trans_dist::Writeback 1727529 # Transaction distribution
1316 system.cpu.toL2Bus.trans_dist::CleanEvict 1124352 # Transaction distribution
1317 system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
1318 system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
1319 system.cpu.toL2Bus.trans_dist::ReadExReq 288090 # Transaction distribution
1320 system.cpu.toL2Bus.trans_dist::ReadExResp 288090 # Transaction distribution
1321 system.cpu.toL2Bus.trans_dist::ReadCleanReq 993903 # Transaction distribution
1322 system.cpu.toL2Bus.trans_dist::ReadSharedReq 1464872 # Transaction distribution
1323 system.cpu.toL2Bus.trans_dist::MessageReq 1650 # Transaction distribution
1324 system.cpu.toL2Bus.trans_dist::BadAddressError 12 # Transaction distribution
1325 system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
1326 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2979851 # Packet count per connected master and slave (bytes)
1327 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6223737 # Packet count per connected master and slave (bytes)
1328 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32716 # Packet count per connected master and slave (bytes)
1329 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 177236 # Packet count per connected master and slave (bytes)
1330 system.cpu.toL2Bus.pkt_count::total 9413540 # Packet count per connected master and slave (bytes)
1331 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63603072 # Cumulative packet size per connected master and slave (bytes)
1332 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208211079 # Cumulative packet size per connected master and slave (bytes)
1333 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 921280 # Cumulative packet size per connected master and slave (bytes)
1334 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5280832 # Cumulative packet size per connected master and slave (bytes)
1335 system.cpu.toL2Bus.pkt_size::total 278016263 # Cumulative packet size per connected master and slave (bytes)
1336 system.cpu.toL2Bus.snoops 218468 # Total snoops (count)
1337 system.cpu.toL2Bus.snoop_fanout::samples 6317764 # Request fanout histogram
1338 system.cpu.toL2Bus.snoop_fanout::mean 3.033210 # Request fanout histogram
1339 system.cpu.toL2Bus.snoop_fanout::stdev 0.179185 # Request fanout histogram
1340 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1341 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1342 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1343 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1344 system.cpu.toL2Bus.snoop_fanout::3 6107951 96.68% 96.68% # Request fanout histogram
1345 system.cpu.toL2Bus.snoop_fanout::4 209813 3.32% 100.00% # Request fanout histogram
1346 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1347 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1348 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1349 system.cpu.toL2Bus.snoop_fanout::total 6317764 # Request fanout histogram
1350 system.cpu.toL2Bus.reqLayer0.occupancy 4638715490 # Layer occupancy (ticks)
1351 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1352 system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks)
1353 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1354 system.cpu.toL2Bus.respLayer0.occupancy 1492354491 # Layer occupancy (ticks)
1355 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1356 system.cpu.toL2Bus.respLayer1.occupancy 3105124685 # Layer occupancy (ticks)
1357 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1358 system.cpu.toL2Bus.respLayer2.occupancy 22263487 # Layer occupancy (ticks)
1359 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1360 system.cpu.toL2Bus.respLayer3.occupancy 111892387 # Layer occupancy (ticks)
1361 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1362 system.iobus.trans_dist::ReadReq 222126 # Transaction distribution
1363 system.iobus.trans_dist::ReadResp 222126 # Transaction distribution
1364 system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
1365 system.iobus.trans_dist::WriteResp 57753 # Transaction distribution
1366 system.iobus.trans_dist::MessageReq 1650 # Transaction distribution
1367 system.iobus.trans_dist::MessageResp 1650 # Transaction distribution
1368 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1386 system.iobus.pkt_count_system.bridge.master::total 464488 # Packet count per connected master and slave (bytes)
1387 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes)
1388 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes)
1389 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes)
1390 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes)
1391 system.iobus.pkt_count::total 563058 # Packet count per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1410 system.iobus.pkt_size_system.bridge.master::total 238530 # Cumulative packet size per connected master and slave (bytes)
1411 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes)
1412 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes)
1413 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes)
1414 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes)
1415 system.iobus.pkt_size::total 3272994 # Cumulative packet size per connected master and slave (bytes)
1416 system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks)
1417 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1418 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1419 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1420 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1421 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1422 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1423 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1424 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1425 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1426 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1427 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1428 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1429 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1430 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1431 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1432 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1433 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1434 system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks)
1435 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1436 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1437 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1438 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1439 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1440 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1441 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1442 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1443 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1444 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1445 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1446 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1447 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1448 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1449 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1450 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1451 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1452 system.iobus.reqLayer19.occupancy 242643106 # Layer occupancy (ticks)
1453 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1454 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1455 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1456 system.iobus.respLayer0.occupancy 453455000 # Layer occupancy (ticks)
1457 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1458 system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks)
1459 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1460 system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks)
1461 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1462 system.iocache.tags.replacements 47580 # number of replacements
1463 system.iocache.tags.tagsinuse 0.177808 # Cycle average of tags in use
1464 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1465 system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks.
1466 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1467 system.iocache.tags.warmup_cycle 4993210705000 # Cycle when the warmup percentage was hit.
1468 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177808 # Average occupied blocks per requestor
1469 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011113 # Average percentage of cache occupancy
1470 system.iocache.tags.occ_percent::total 0.011113 # Average percentage of cache occupancy
1471 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1472 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1473 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1474 system.iocache.tags.tag_accesses 428715 # Number of tag accesses
1475 system.iocache.tags.data_accesses 428715 # Number of data accesses
1476 system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses
1477 system.iocache.ReadReq_misses::total 915 # number of ReadReq misses
1478 system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
1479 system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
1480 system.iocache.demand_misses::pc.south_bridge.ide 915 # number of demand (read+write) misses
1481 system.iocache.demand_misses::total 915 # number of demand (read+write) misses
1482 system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses
1483 system.iocache.overall_misses::total 915 # number of overall misses
1484 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142818702 # number of ReadReq miss cycles
1485 system.iocache.ReadReq_miss_latency::total 142818702 # number of ReadReq miss cycles
1486 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513453404 # number of WriteLineReq miss cycles
1487 system.iocache.WriteLineReq_miss_latency::total 5513453404 # number of WriteLineReq miss cycles
1488 system.iocache.demand_miss_latency::pc.south_bridge.ide 142818702 # number of demand (read+write) miss cycles
1489 system.iocache.demand_miss_latency::total 142818702 # number of demand (read+write) miss cycles
1490 system.iocache.overall_miss_latency::pc.south_bridge.ide 142818702 # number of overall miss cycles
1491 system.iocache.overall_miss_latency::total 142818702 # number of overall miss cycles
1492 system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses)
1493 system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
1494 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
1495 system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
1496 system.iocache.demand_accesses::pc.south_bridge.ide 915 # number of demand (read+write) accesses
1497 system.iocache.demand_accesses::total 915 # number of demand (read+write) accesses
1498 system.iocache.overall_accesses::pc.south_bridge.ide 915 # number of overall (read+write) accesses
1499 system.iocache.overall_accesses::total 915 # number of overall (read+write) accesses
1500 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1501 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1502 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
1503 system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1504 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1505 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1506 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1507 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1508 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average ReadReq miss latency
1509 system.iocache.ReadReq_avg_miss_latency::total 156086.013115 # average ReadReq miss latency
1510 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.560873 # average WriteLineReq miss latency
1511 system.iocache.WriteLineReq_avg_miss_latency::total 118010.560873 # average WriteLineReq miss latency
1512 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average overall miss latency
1513 system.iocache.demand_avg_miss_latency::total 156086.013115 # average overall miss latency
1514 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average overall miss latency
1515 system.iocache.overall_avg_miss_latency::total 156086.013115 # average overall miss latency
1516 system.iocache.blocked_cycles::no_mshrs 218 # number of cycles access was blocked
1517 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1518 system.iocache.blocked::no_mshrs 18 # number of cycles access was blocked
1519 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1520 system.iocache.avg_blocked_cycles::no_mshrs 12.111111 # average number of cycles each access was blocked
1521 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1522 system.iocache.fast_writes 0 # number of fast writes performed
1523 system.iocache.cache_copies 0 # number of cache copies performed
1524 system.iocache.writebacks::writebacks 46667 # number of writebacks
1525 system.iocache.writebacks::total 46667 # number of writebacks
1526 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses
1527 system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses
1528 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
1529 system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
1530 system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 # number of demand (read+write) MSHR misses
1531 system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses
1532 system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses
1533 system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses
1534 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of ReadReq MSHR miss cycles
1535 system.iocache.ReadReq_mshr_miss_latency::total 97068702 # number of ReadReq MSHR miss cycles
1536 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177453404 # number of WriteLineReq MSHR miss cycles
1537 system.iocache.WriteLineReq_mshr_miss_latency::total 3177453404 # number of WriteLineReq MSHR miss cycles
1538 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of demand (read+write) MSHR miss cycles
1539 system.iocache.demand_mshr_miss_latency::total 97068702 # number of demand (read+write) MSHR miss cycles
1540 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of overall MSHR miss cycles
1541 system.iocache.overall_mshr_miss_latency::total 97068702 # number of overall MSHR miss cycles
1542 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1543 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1544 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
1545 system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1546 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1547 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1548 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1549 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1550 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average ReadReq mshr miss latency
1551 system.iocache.ReadReq_avg_mshr_miss_latency::total 106086.013115 # average ReadReq mshr miss latency
1552 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.560873 # average WriteLineReq mshr miss latency
1553 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.560873 # average WriteLineReq mshr miss latency
1554 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average overall mshr miss latency
1555 system.iocache.demand_avg_mshr_miss_latency::total 106086.013115 # average overall mshr miss latency
1556 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average overall mshr miss latency
1557 system.iocache.overall_avg_mshr_miss_latency::total 106086.013115 # average overall mshr miss latency
1558 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1559 system.membus.trans_dist::ReadReq 602920 # Transaction distribution
1560 system.membus.trans_dist::ReadResp 656038 # Transaction distribution
1561 system.membus.trans_dist::WriteReq 13934 # Transaction distribution
1562 system.membus.trans_dist::WriteResp 13934 # Transaction distribution
1563 system.membus.trans_dist::Writeback 149751 # Transaction distribution
1564 system.membus.trans_dist::CleanEvict 10203 # Transaction distribution
1565 system.membus.trans_dist::UpgradeReq 2209 # Transaction distribution
1566 system.membus.trans_dist::UpgradeResp 1791 # Transaction distribution
1567 system.membus.trans_dist::ReadExReq 133869 # Transaction distribution
1568 system.membus.trans_dist::ReadExResp 133868 # Transaction distribution
1569 system.membus.trans_dist::ReadSharedReq 53130 # Transaction distribution
1570 system.membus.trans_dist::MessageReq 1650 # Transaction distribution
1571 system.membus.trans_dist::MessageResp 1650 # Transaction distribution
1572 system.membus.trans_dist::BadAddressError 12 # Transaction distribution
1573 system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
1574 system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
1575 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes)
1576 system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes)
1577 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464488 # Packet count per connected master and slave (bytes)
1578 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes)
1579 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 488383 # Packet count per connected master and slave (bytes)
1580 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 24 # Packet count per connected master and slave (bytes)
1581 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1722115 # Packet count per connected master and slave (bytes)
1582 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141817 # Packet count per connected master and slave (bytes)
1583 system.membus.pkt_count_system.iocache.mem_side::total 141817 # Packet count per connected master and slave (bytes)
1584 system.membus.pkt_count::total 1867232 # Packet count per connected master and slave (bytes)
1585 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes)
1586 system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes)
1587 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238530 # Cumulative packet size per connected master and slave (bytes)
1588 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes)
1589 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18462656 # Cumulative packet size per connected master and slave (bytes)
1590 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20239623 # Cumulative packet size per connected master and slave (bytes)
1591 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
1592 system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
1593 system.membus.pkt_size::total 23261263 # Cumulative packet size per connected master and slave (bytes)
1594 system.membus.snoops 1586 # Total snoops (count)
1595 system.membus.snoop_fanout::samples 1014957 # Request fanout histogram
1596 system.membus.snoop_fanout::mean 1.001626 # Request fanout histogram
1597 system.membus.snoop_fanout::stdev 0.040287 # Request fanout histogram
1598 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1599 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1600 system.membus.snoop_fanout::1 1013307 99.84% 99.84% # Request fanout histogram
1601 system.membus.snoop_fanout::2 1650 0.16% 100.00% # Request fanout histogram
1602 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1603 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1604 system.membus.snoop_fanout::max_value 2 # Request fanout histogram
1605 system.membus.snoop_fanout::total 1014957 # Request fanout histogram
1606 system.membus.reqLayer0.occupancy 355040500 # Layer occupancy (ticks)
1607 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1608 system.membus.reqLayer1.occupancy 388549500 # Layer occupancy (ticks)
1609 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1610 system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks)
1611 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1612 system.membus.reqLayer3.occupancy 1018755770 # Layer occupancy (ticks)
1613 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1614 system.membus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
1615 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1616 system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks)
1617 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1618 system.membus.respLayer2.occupancy 2209187226 # Layer occupancy (ticks)
1619 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1620 system.membus.respLayer4.occupancy 86115345 # Layer occupancy (ticks)
1621 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1622 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1623 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1624 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1625 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1626 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1627 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1628 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1629 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1630 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1631 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1632 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1633 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1634 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1635 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1637 ---------- End Simulation Statistics ----------
projects / gem5.git / blob