2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.157514 # Number of seconds simulated
4 sim_ticks 5157514159500 # Number of ticks simulated
5 final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 123762 # Simulator instruction rate (inst/s)
8 host_op_rate 243888 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1496586873 # Simulator tick rate (ticks/s)
10 host_mem_usage 369148 # Number of bytes of host memory used
11 host_seconds 3446.18 # Real time elapsed on the host
12 sim_insts 426506235 # Number of instructions simulated
13 sim_ops 840483958 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s)
49 system.l2c.replacements 167142 # number of replacements
50 system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use
51 system.l2c.total_refs 3843284 # Total number of references to valid blocks.
52 system.l2c.sampled_refs 202399 # Sample count of references to valid blocks.
53 system.l2c.avg_refs 18.988651 # Average number of references to valid blocks.
54 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
55 system.l2c.occ_blocks::writebacks 26702.073389 # Average occupied blocks per requestor
56 system.l2c.occ_blocks::cpu.dtb.walker 8.025761 # Average occupied blocks per requestor
57 system.l2c.occ_blocks::cpu.itb.walker 0.043125 # Average occupied blocks per requestor
58 system.l2c.occ_blocks::cpu.inst 2426.285000 # Average occupied blocks per requestor
59 system.l2c.occ_blocks::cpu.data 8680.262415 # Average occupied blocks per requestor
60 system.l2c.occ_percent::writebacks 0.407441 # Average percentage of cache occupancy
61 system.l2c.occ_percent::cpu.dtb.walker 0.000122 # Average percentage of cache occupancy
62 system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
63 system.l2c.occ_percent::cpu.inst 0.037022 # Average percentage of cache occupancy
64 system.l2c.occ_percent::cpu.data 0.132450 # Average percentage of cache occupancy
65 system.l2c.occ_percent::total 0.577037 # Average percentage of cache occupancy
66 system.l2c.ReadReq_hits::cpu.dtb.walker 109565 # number of ReadReq hits
67 system.l2c.ReadReq_hits::cpu.itb.walker 8804 # number of ReadReq hits
68 system.l2c.ReadReq_hits::cpu.inst 1063948 # number of ReadReq hits
69 system.l2c.ReadReq_hits::cpu.data 1334758 # number of ReadReq hits
70 system.l2c.ReadReq_hits::total 2517075 # number of ReadReq hits
71 system.l2c.Writeback_hits::writebacks 1600724 # number of Writeback hits
72 system.l2c.Writeback_hits::total 1600724 # number of Writeback hits
73 system.l2c.UpgradeReq_hits::cpu.data 336 # number of UpgradeReq hits
74 system.l2c.UpgradeReq_hits::total 336 # number of UpgradeReq hits
75 system.l2c.ReadExReq_hits::cpu.data 151728 # number of ReadExReq hits
76 system.l2c.ReadExReq_hits::total 151728 # number of ReadExReq hits
77 system.l2c.demand_hits::cpu.dtb.walker 109565 # number of demand (read+write) hits
78 system.l2c.demand_hits::cpu.itb.walker 8804 # number of demand (read+write) hits
79 system.l2c.demand_hits::cpu.inst 1063948 # number of demand (read+write) hits
80 system.l2c.demand_hits::cpu.data 1486486 # number of demand (read+write) hits
81 system.l2c.demand_hits::total 2668803 # number of demand (read+write) hits
82 system.l2c.overall_hits::cpu.dtb.walker 109565 # number of overall hits
83 system.l2c.overall_hits::cpu.itb.walker 8804 # number of overall hits
84 system.l2c.overall_hits::cpu.inst 1063948 # number of overall hits
85 system.l2c.overall_hits::cpu.data 1486486 # number of overall hits
86 system.l2c.overall_hits::total 2668803 # number of overall hits
87 system.l2c.ReadReq_misses::cpu.dtb.walker 105 # number of ReadReq misses
88 system.l2c.ReadReq_misses::cpu.itb.walker 17 # number of ReadReq misses
89 system.l2c.ReadReq_misses::cpu.inst 19652 # number of ReadReq misses
90 system.l2c.ReadReq_misses::cpu.data 45660 # number of ReadReq misses
91 system.l2c.ReadReq_misses::total 65434 # number of ReadReq misses
92 system.l2c.UpgradeReq_misses::cpu.data 2521 # number of UpgradeReq misses
93 system.l2c.UpgradeReq_misses::total 2521 # number of UpgradeReq misses
94 system.l2c.ReadExReq_misses::cpu.data 141129 # number of ReadExReq misses
95 system.l2c.ReadExReq_misses::total 141129 # number of ReadExReq misses
96 system.l2c.demand_misses::cpu.dtb.walker 105 # number of demand (read+write) misses
97 system.l2c.demand_misses::cpu.itb.walker 17 # number of demand (read+write) misses
98 system.l2c.demand_misses::cpu.inst 19652 # number of demand (read+write) misses
99 system.l2c.demand_misses::cpu.data 186789 # number of demand (read+write) misses
100 system.l2c.demand_misses::total 206563 # number of demand (read+write) misses
101 system.l2c.overall_misses::cpu.dtb.walker 105 # number of overall misses
102 system.l2c.overall_misses::cpu.itb.walker 17 # number of overall misses
103 system.l2c.overall_misses::cpu.inst 19652 # number of overall misses
104 system.l2c.overall_misses::cpu.data 186789 # number of overall misses
105 system.l2c.overall_misses::total 206563 # number of overall misses
106 system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5480500 # number of ReadReq miss cycles
107 system.l2c.ReadReq_miss_latency::cpu.itb.walker 886000 # number of ReadReq miss cycles
108 system.l2c.ReadReq_miss_latency::cpu.inst 1027000000 # number of ReadReq miss cycles
109 system.l2c.ReadReq_miss_latency::cpu.data 2399872000 # number of ReadReq miss cycles
110 system.l2c.ReadReq_miss_latency::total 3433238500 # number of ReadReq miss cycles
111 system.l2c.UpgradeReq_miss_latency::cpu.data 39054500 # number of UpgradeReq miss cycles
112 system.l2c.UpgradeReq_miss_latency::total 39054500 # number of UpgradeReq miss cycles
113 system.l2c.ReadExReq_miss_latency::cpu.data 7349617000 # number of ReadExReq miss cycles
114 system.l2c.ReadExReq_miss_latency::total 7349617000 # number of ReadExReq miss cycles
115 system.l2c.demand_miss_latency::cpu.dtb.walker 5480500 # number of demand (read+write) miss cycles
116 system.l2c.demand_miss_latency::cpu.itb.walker 886000 # number of demand (read+write) miss cycles
117 system.l2c.demand_miss_latency::cpu.inst 1027000000 # number of demand (read+write) miss cycles
118 system.l2c.demand_miss_latency::cpu.data 9749489000 # number of demand (read+write) miss cycles
119 system.l2c.demand_miss_latency::total 10782855500 # number of demand (read+write) miss cycles
120 system.l2c.overall_miss_latency::cpu.dtb.walker 5480500 # number of overall miss cycles
121 system.l2c.overall_miss_latency::cpu.itb.walker 886000 # number of overall miss cycles
122 system.l2c.overall_miss_latency::cpu.inst 1027000000 # number of overall miss cycles
123 system.l2c.overall_miss_latency::cpu.data 9749489000 # number of overall miss cycles
124 system.l2c.overall_miss_latency::total 10782855500 # number of overall miss cycles
125 system.l2c.ReadReq_accesses::cpu.dtb.walker 109670 # number of ReadReq accesses(hits+misses)
126 system.l2c.ReadReq_accesses::cpu.itb.walker 8821 # number of ReadReq accesses(hits+misses)
127 system.l2c.ReadReq_accesses::cpu.inst 1083600 # number of ReadReq accesses(hits+misses)
128 system.l2c.ReadReq_accesses::cpu.data 1380418 # number of ReadReq accesses(hits+misses)
129 system.l2c.ReadReq_accesses::total 2582509 # number of ReadReq accesses(hits+misses)
130 system.l2c.Writeback_accesses::writebacks 1600724 # number of Writeback accesses(hits+misses)
131 system.l2c.Writeback_accesses::total 1600724 # number of Writeback accesses(hits+misses)
132 system.l2c.UpgradeReq_accesses::cpu.data 2857 # number of UpgradeReq accesses(hits+misses)
133 system.l2c.UpgradeReq_accesses::total 2857 # number of UpgradeReq accesses(hits+misses)
134 system.l2c.ReadExReq_accesses::cpu.data 292857 # number of ReadExReq accesses(hits+misses)
135 system.l2c.ReadExReq_accesses::total 292857 # number of ReadExReq accesses(hits+misses)
136 system.l2c.demand_accesses::cpu.dtb.walker 109670 # number of demand (read+write) accesses
137 system.l2c.demand_accesses::cpu.itb.walker 8821 # number of demand (read+write) accesses
138 system.l2c.demand_accesses::cpu.inst 1083600 # number of demand (read+write) accesses
139 system.l2c.demand_accesses::cpu.data 1673275 # number of demand (read+write) accesses
140 system.l2c.demand_accesses::total 2875366 # number of demand (read+write) accesses
141 system.l2c.overall_accesses::cpu.dtb.walker 109670 # number of overall (read+write) accesses
142 system.l2c.overall_accesses::cpu.itb.walker 8821 # number of overall (read+write) accesses
143 system.l2c.overall_accesses::cpu.inst 1083600 # number of overall (read+write) accesses
144 system.l2c.overall_accesses::cpu.data 1673275 # number of overall (read+write) accesses
145 system.l2c.overall_accesses::total 2875366 # number of overall (read+write) accesses
146 system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 # miss rate for ReadReq accesses
147 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses
148 system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses
149 system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses
150 system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses
151 system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses
152 system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses
153 system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses
154 system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses
155 system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses
156 system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses
157 system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses
158 system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses
159 system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses
160 system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses
161 system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses
162 system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses
163 system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses
164 system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses
165 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency
166 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency
167 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency
168 system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency
169 system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency
170 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency
171 system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency
172 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency
173 system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency
174 system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency
175 system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency
176 system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency
177 system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency
178 system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency
179 system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency
180 system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency
181 system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency
182 system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency
183 system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency
184 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
185 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
186 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
187 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
188 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
189 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
190 system.l2c.fast_writes 0 # number of fast writes performed
191 system.l2c.cache_copies 0 # number of cache copies performed
192 system.l2c.writebacks::writebacks 141616 # number of writebacks
193 system.l2c.writebacks::total 141616 # number of writebacks
194 system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
195 system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
196 system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
197 system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
198 system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
199 system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
200 system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
201 system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
202 system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
203 system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 105 # number of ReadReq MSHR misses
204 system.l2c.ReadReq_mshr_misses::cpu.itb.walker 17 # number of ReadReq MSHR misses
205 system.l2c.ReadReq_mshr_misses::cpu.inst 19651 # number of ReadReq MSHR misses
206 system.l2c.ReadReq_mshr_misses::cpu.data 45659 # number of ReadReq MSHR misses
207 system.l2c.ReadReq_mshr_misses::total 65432 # number of ReadReq MSHR misses
208 system.l2c.UpgradeReq_mshr_misses::cpu.data 2521 # number of UpgradeReq MSHR misses
209 system.l2c.UpgradeReq_mshr_misses::total 2521 # number of UpgradeReq MSHR misses
210 system.l2c.ReadExReq_mshr_misses::cpu.data 141129 # number of ReadExReq MSHR misses
211 system.l2c.ReadExReq_mshr_misses::total 141129 # number of ReadExReq MSHR misses
212 system.l2c.demand_mshr_misses::cpu.dtb.walker 105 # number of demand (read+write) MSHR misses
213 system.l2c.demand_mshr_misses::cpu.itb.walker 17 # number of demand (read+write) MSHR misses
214 system.l2c.demand_mshr_misses::cpu.inst 19651 # number of demand (read+write) MSHR misses
215 system.l2c.demand_mshr_misses::cpu.data 186788 # number of demand (read+write) MSHR misses
216 system.l2c.demand_mshr_misses::total 206561 # number of demand (read+write) MSHR misses
217 system.l2c.overall_mshr_misses::cpu.dtb.walker 105 # number of overall MSHR misses
218 system.l2c.overall_mshr_misses::cpu.itb.walker 17 # number of overall MSHR misses
219 system.l2c.overall_mshr_misses::cpu.inst 19651 # number of overall MSHR misses
220 system.l2c.overall_mshr_misses::cpu.data 186788 # number of overall MSHR misses
221 system.l2c.overall_mshr_misses::total 206561 # number of overall MSHR misses
222 system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 4210000 # number of ReadReq MSHR miss cycles
223 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 680000 # number of ReadReq MSHR miss cycles
224 system.l2c.ReadReq_mshr_miss_latency::cpu.inst 786943000 # number of ReadReq MSHR miss cycles
225 system.l2c.ReadReq_mshr_miss_latency::cpu.data 1841762000 # number of ReadReq MSHR miss cycles
226 system.l2c.ReadReq_mshr_miss_latency::total 2633595000 # number of ReadReq MSHR miss cycles
227 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 101204500 # number of UpgradeReq MSHR miss cycles
228 system.l2c.UpgradeReq_mshr_miss_latency::total 101204500 # number of UpgradeReq MSHR miss cycles
229 system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5646584500 # number of ReadExReq MSHR miss cycles
230 system.l2c.ReadExReq_mshr_miss_latency::total 5646584500 # number of ReadExReq MSHR miss cycles
231 system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 4210000 # number of demand (read+write) MSHR miss cycles
232 system.l2c.demand_mshr_miss_latency::cpu.itb.walker 680000 # number of demand (read+write) MSHR miss cycles
233 system.l2c.demand_mshr_miss_latency::cpu.inst 786943000 # number of demand (read+write) MSHR miss cycles
234 system.l2c.demand_mshr_miss_latency::cpu.data 7488346500 # number of demand (read+write) MSHR miss cycles
235 system.l2c.demand_mshr_miss_latency::total 8280179500 # number of demand (read+write) MSHR miss cycles
236 system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 4210000 # number of overall MSHR miss cycles
237 system.l2c.overall_mshr_miss_latency::cpu.itb.walker 680000 # number of overall MSHR miss cycles
238 system.l2c.overall_mshr_miss_latency::cpu.inst 786943000 # number of overall MSHR miss cycles
239 system.l2c.overall_mshr_miss_latency::cpu.data 7488346500 # number of overall MSHR miss cycles
240 system.l2c.overall_mshr_miss_latency::total 8280179500 # number of overall MSHR miss cycles
241 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975402500 # number of ReadReq MSHR uncacheable cycles
242 system.l2c.ReadReq_mshr_uncacheable_latency::total 59975402500 # number of ReadReq MSHR uncacheable cycles
243 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1229367500 # number of WriteReq MSHR uncacheable cycles
244 system.l2c.WriteReq_mshr_uncacheable_latency::total 1229367500 # number of WriteReq MSHR uncacheable cycles
245 system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204770000 # number of overall MSHR uncacheable cycles
246 system.l2c.overall_mshr_uncacheable_latency::total 61204770000 # number of overall MSHR uncacheable cycles
247 system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for ReadReq accesses
248 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses
249 system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses
250 system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses
251 system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses
252 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses
253 system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses
254 system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses
255 system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses
256 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses
257 system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses
258 system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses
259 system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses
260 system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses
261 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses
262 system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses
263 system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses
264 system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses
265 system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses
266 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency
267 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
268 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency
269 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency
270 system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency
271 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency
272 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency
273 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency
274 system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency
275 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency
276 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
277 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency
278 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency
279 system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
280 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency
281 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
282 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency
283 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency
284 system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
285 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
286 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
287 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
288 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
289 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
290 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
291 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
292 system.iocache.replacements 47578 # number of replacements
293 system.iocache.tagsinuse 0.166155 # Cycle average of tags in use
294 system.iocache.total_refs 0 # Total number of references to valid blocks.
295 system.iocache.sampled_refs 47594 # Sample count of references to valid blocks.
296 system.iocache.avg_refs 0 # Average number of references to valid blocks.
297 system.iocache.warmup_cycle 4996370640000 # Cycle when the warmup percentage was hit.
298 system.iocache.occ_blocks::pc.south_bridge.ide 0.166155 # Average occupied blocks per requestor
299 system.iocache.occ_percent::pc.south_bridge.ide 0.010385 # Average percentage of cache occupancy
300 system.iocache.occ_percent::total 0.010385 # Average percentage of cache occupancy
301 system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses
302 system.iocache.ReadReq_misses::total 913 # number of ReadReq misses
303 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
304 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
305 system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses
306 system.iocache.demand_misses::total 47633 # number of demand (read+write) misses
307 system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses
308 system.iocache.overall_misses::total 47633 # number of overall misses
309 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114379932 # number of ReadReq miss cycles
310 system.iocache.ReadReq_miss_latency::total 114379932 # number of ReadReq miss cycles
311 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6373400160 # number of WriteReq miss cycles
312 system.iocache.WriteReq_miss_latency::total 6373400160 # number of WriteReq miss cycles
313 system.iocache.demand_miss_latency::pc.south_bridge.ide 6487780092 # number of demand (read+write) miss cycles
314 system.iocache.demand_miss_latency::total 6487780092 # number of demand (read+write) miss cycles
315 system.iocache.overall_miss_latency::pc.south_bridge.ide 6487780092 # number of overall miss cycles
316 system.iocache.overall_miss_latency::total 6487780092 # number of overall miss cycles
317 system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses)
318 system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses)
319 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
320 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
321 system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses
322 system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses
323 system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses
324 system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses
325 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
326 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
327 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
328 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
329 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
330 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
331 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
332 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
333 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency
334 system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency
335 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency
336 system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency
337 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency
338 system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency
339 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency
340 system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency
341 system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked
342 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
343 system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked
344 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
345 system.iocache.avg_blocked_cycles::no_mshrs 6125.258142 # average number of cycles each access was blocked
346 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
347 system.iocache.fast_writes 0 # number of fast writes performed
348 system.iocache.cache_copies 0 # number of cache copies performed
349 system.iocache.writebacks::writebacks 46667 # number of writebacks
350 system.iocache.writebacks::total 46667 # number of writebacks
351 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses
352 system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses
353 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
354 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
355 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses
356 system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses
357 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses
358 system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses
359 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66880982 # number of ReadReq MSHR miss cycles
360 system.iocache.ReadReq_mshr_miss_latency::total 66880982 # number of ReadReq MSHR miss cycles
361 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3943643878 # number of WriteReq MSHR miss cycles
362 system.iocache.WriteReq_mshr_miss_latency::total 3943643878 # number of WriteReq MSHR miss cycles
363 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of demand (read+write) MSHR miss cycles
364 system.iocache.demand_mshr_miss_latency::total 4010524860 # number of demand (read+write) MSHR miss cycles
365 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles
366 system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles
367 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
368 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
369 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
370 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
371 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
372 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
373 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
374 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
375 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency
376 system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency
377 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency
378 system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency
379 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency
380 system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
381 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency
382 system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
383 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
384 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
385 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
386 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
387 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
388 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
389 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
390 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
391 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
392 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
393 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
394 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
395 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
396 system.cpu.numCycles 461333918 # number of cpu cycles simulated
397 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
398 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
399 system.cpu.BPredUnit.lookups 90003796 # Number of BP lookups
400 system.cpu.BPredUnit.condPredicted 90003796 # Number of conditional branches predicted
401 system.cpu.BPredUnit.condIncorrect 1173183 # Number of conditional branches incorrect
402 system.cpu.BPredUnit.BTBLookups 84315614 # Number of BTB lookups
403 system.cpu.BPredUnit.BTBHits 81694619 # Number of BTB hits
404 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
405 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
406 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
407 system.cpu.fetch.icacheStallCycles 29624871 # Number of cycles fetch is stalled on an Icache miss
408 system.cpu.fetch.Insts 446885817 # Number of instructions fetch has processed
409 system.cpu.fetch.Branches 90003796 # Number of branches that fetch encountered
410 system.cpu.fetch.predictedBranches 81694619 # Number of branches that fetch has predicted taken
411 system.cpu.fetch.Cycles 169759235 # Number of cycles fetch has run and was not squashing or blocked
412 system.cpu.fetch.SquashCycles 5280537 # Number of cycles fetch has spent squashing
413 system.cpu.fetch.TlbCycles 141697 # Number of cycles fetch has spent waiting for tlb
414 system.cpu.fetch.BlockedCycles 98681847 # Number of cycles fetch has spent blocked
415 system.cpu.fetch.MiscStallCycles 37486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416 system.cpu.fetch.PendingTrapStallCycles 37869 # Number of stall cycles due to pending traps
417 system.cpu.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR
418 system.cpu.fetch.CacheLines 9366803 # Number of cache lines fetched
419 system.cpu.fetch.IcacheSquashes 526850 # Number of outstanding Icache misses that were squashed
420 system.cpu.fetch.ItlbSquashes 4968 # Number of outstanding ITLB misses that were squashed
421 system.cpu.fetch.rateDist::samples 302354351 # Number of instructions fetched each cycle (Total)
422 system.cpu.fetch.rateDist::mean 2.908315 # Number of instructions fetched each cycle (Total)
423 system.cpu.fetch.rateDist::stdev 3.388599 # Number of instructions fetched each cycle (Total)
424 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
425 system.cpu.fetch.rateDist::0 133032171 44.00% 44.00% # Number of instructions fetched each cycle (Total)
426 system.cpu.fetch.rateDist::1 1767192 0.58% 44.58% # Number of instructions fetched each cycle (Total)
427 system.cpu.fetch.rateDist::2 72774261 24.07% 68.65% # Number of instructions fetched each cycle (Total)
428 system.cpu.fetch.rateDist::3 988290 0.33% 68.98% # Number of instructions fetched each cycle (Total)
429 system.cpu.fetch.rateDist::4 1636300 0.54% 69.52% # Number of instructions fetched each cycle (Total)
430 system.cpu.fetch.rateDist::5 3666710 1.21% 70.73% # Number of instructions fetched each cycle (Total)
431 system.cpu.fetch.rateDist::6 1141173 0.38% 71.11% # Number of instructions fetched each cycle (Total)
432 system.cpu.fetch.rateDist::7 1450765 0.48% 71.59% # Number of instructions fetched each cycle (Total)
433 system.cpu.fetch.rateDist::8 85897489 28.41% 100.00% # Number of instructions fetched each cycle (Total)
434 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
435 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
436 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
437 system.cpu.fetch.rateDist::total 302354351 # Number of instructions fetched each cycle (Total)
438 system.cpu.fetch.branchRate 0.195095 # Number of branch fetches per cycle
439 system.cpu.fetch.rate 0.968682 # Number of inst fetches per cycle
440 system.cpu.decode.IdleCycles 34659888 # Number of cycles decode is idle
441 system.cpu.decode.BlockedCycles 94852238 # Number of cycles decode is blocked
442 system.cpu.decode.RunCycles 163950875 # Number of cycles decode is running
443 system.cpu.decode.UnblockCycles 4820336 # Number of cycles decode is unblocking
444 system.cpu.decode.SquashCycles 4071014 # Number of cycles decode is squashing
445 system.cpu.decode.DecodedInsts 876062076 # Number of instructions handled by decode
446 system.cpu.decode.SquashedInsts 946 # Number of squashed instructions handled by decode
447 system.cpu.rename.SquashCycles 4071014 # Number of cycles rename is squashing
448 system.cpu.rename.IdleCycles 38916721 # Number of cycles rename is idle
449 system.cpu.rename.BlockCycles 39863124 # Number of cycles rename is blocking
450 system.cpu.rename.serializeStallCycles 10415671 # count of cycles rename stalled for serializing inst
451 system.cpu.rename.RunCycles 164017891 # Number of cycles rename is running
452 system.cpu.rename.UnblockCycles 45069930 # Number of cycles rename is unblocking
453 system.cpu.rename.RenamedInsts 872218550 # Number of instructions processed by rename
454 system.cpu.rename.ROBFullEvents 9888 # Number of times rename has blocked due to ROB full
455 system.cpu.rename.IQFullEvents 34551329 # Number of times rename has blocked due to IQ full
456 system.cpu.rename.LSQFullEvents 3873333 # Number of times rename has blocked due to LSQ full
457 system.cpu.rename.FullRegisterEvents 31844673 # Number of times there has been no free registers
458 system.cpu.rename.RenamedOperands 1393807250 # Number of destination operands rename has renamed
459 system.cpu.rename.RenameLookups 2487751490 # Number of register rename lookups that rename has made
460 system.cpu.rename.int_rename_lookups 2487750754 # Number of integer rename lookups
461 system.cpu.rename.fp_rename_lookups 736 # Number of floating rename lookups
462 system.cpu.rename.CommittedMaps 1347499622 # Number of HB maps that are committed
463 system.cpu.rename.UndoneMaps 46307621 # Number of HB maps that are undone due to squashing
464 system.cpu.rename.serializingInsts 471559 # count of serializing insts renamed
465 system.cpu.rename.tempSerializingInsts 478592 # count of temporary serializing insts renamed
466 system.cpu.rename.skidInsts 46419855 # count of insts added to the skid buffer
467 system.cpu.memDep0.insertedLoads 18887370 # Number of loads inserted to the mem dependence unit.
468 system.cpu.memDep0.insertedStores 10441908 # Number of stores inserted to the mem dependence unit.
469 system.cpu.memDep0.conflictingLoads 1295912 # Number of conflicting loads.
470 system.cpu.memDep0.conflictingStores 1023550 # Number of conflicting stores.
471 system.cpu.iq.iqInstsAdded 865497785 # Number of instructions added to the IQ (excludes non-spec)
472 system.cpu.iq.iqNonSpecInstsAdded 1720774 # Number of non-speculative instructions added to the IQ
473 system.cpu.iq.iqInstsIssued 864256485 # Number of instructions issued
474 system.cpu.iq.iqSquashedInstsIssued 112298 # Number of squashed instructions issued
475 system.cpu.iq.iqSquashedInstsExamined 25797308 # Number of squashed instructions iterated over during squash; mainly for profiling
476 system.cpu.iq.iqSquashedOperandsExamined 52868100 # Number of squashed operands that are examined and possibly removed from graph
477 system.cpu.iq.iqSquashedNonSpecRemoved 205226 # Number of squashed non-spec instructions that were removed
478 system.cpu.iq.issued_per_cycle::samples 302354351 # Number of insts issued each cycle
479 system.cpu.iq.issued_per_cycle::mean 2.858423 # Number of insts issued each cycle
480 system.cpu.iq.issued_per_cycle::stdev 2.389396 # Number of insts issued each cycle
481 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
482 system.cpu.iq.issued_per_cycle::0 95961753 31.74% 31.74% # Number of insts issued each cycle
483 system.cpu.iq.issued_per_cycle::1 22210791 7.35% 39.08% # Number of insts issued each cycle
484 system.cpu.iq.issued_per_cycle::2 18920489 6.26% 45.34% # Number of insts issued each cycle
485 system.cpu.iq.issued_per_cycle::3 7861035 2.60% 47.94% # Number of insts issued each cycle
486 system.cpu.iq.issued_per_cycle::4 80643891 26.67% 74.61% # Number of insts issued each cycle
487 system.cpu.iq.issued_per_cycle::5 3288348 1.09% 75.70% # Number of insts issued each cycle
488 system.cpu.iq.issued_per_cycle::6 72804040 24.08% 99.78% # Number of insts issued each cycle
489 system.cpu.iq.issued_per_cycle::7 531965 0.18% 99.96% # Number of insts issued each cycle
490 system.cpu.iq.issued_per_cycle::8 132039 0.04% 100.00% # Number of insts issued each cycle
491 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
492 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
493 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
494 system.cpu.iq.issued_per_cycle::total 302354351 # Number of insts issued each cycle
495 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
496 system.cpu.iq.fu_full::IntAlu 168781 8.00% 8.00% # attempts to use FU when none available
497 system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available
498 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available
499 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available
500 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available
501 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available
502 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available
503 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available
504 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available
505 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available
506 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available
507 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available
508 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available
509 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available
510 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available
511 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available
512 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available
513 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available
514 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available
515 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available
516 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available
517 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available
518 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available
519 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available
520 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available
521 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available
522 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available
523 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available
524 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available
525 system.cpu.iq.fu_full::MemRead 1775830 84.20% 92.20% # attempts to use FU when none available
526 system.cpu.iq.fu_full::MemWrite 164454 7.80% 100.00% # attempts to use FU when none available
527 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
528 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
529 system.cpu.iq.FU_type_0::No_OpClass 295147 0.03% 0.03% # Type of FU issued
530 system.cpu.iq.FU_type_0::IntAlu 829365416 95.96% 96.00% # Type of FU issued
531 system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued
532 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued
533 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued
534 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued
535 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued
536 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued
537 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued
538 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued
539 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued
540 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued
541 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued
542 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued
543 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued
544 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued
545 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued
546 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued
547 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued
548 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued
549 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued
550 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued
551 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued
552 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued
553 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued
554 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued
555 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued
556 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued
557 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued
558 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued
559 system.cpu.iq.FU_type_0::MemRead 25156928 2.91% 98.91% # Type of FU issued
560 system.cpu.iq.FU_type_0::MemWrite 9438994 1.09% 100.00% # Type of FU issued
561 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
562 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
563 system.cpu.iq.FU_type_0::total 864256485 # Type of FU issued
564 system.cpu.iq.rate 1.873386 # Inst issue rate
565 system.cpu.iq.fu_busy_cnt 2109065 # FU busy when requested
566 system.cpu.iq.fu_busy_rate 0.002440 # FU busy rate (busy events/executed inst)
567 system.cpu.iq.int_inst_queue_reads 2033227215 # Number of integer instruction queue reads
568 system.cpu.iq.int_inst_queue_writes 893026339 # Number of integer instruction queue writes
569 system.cpu.iq.int_inst_queue_wakeup_accesses 853844323 # Number of integer instruction queue wakeup accesses
570 system.cpu.iq.fp_inst_queue_reads 314 # Number of floating instruction queue reads
571 system.cpu.iq.fp_inst_queue_writes 348 # Number of floating instruction queue writes
572 system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
573 system.cpu.iq.int_alu_accesses 866070258 # Number of integer alu accesses
574 system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses
575 system.cpu.iew.lsq.thread0.forwLoads 1582954 # Number of loads that had data forwarded from stores
576 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
577 system.cpu.iew.lsq.thread0.squashedLoads 3588586 # Number of loads squashed
578 system.cpu.iew.lsq.thread0.ignoredResponses 21998 # Number of memory responses ignored because the instruction is squashed
579 system.cpu.iew.lsq.thread0.memOrderViolation 11829 # Number of memory ordering violations
580 system.cpu.iew.lsq.thread0.squashedStores 2035325 # Number of stores squashed
581 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
582 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
583 system.cpu.iew.lsq.thread0.rescheduledLoads 7821677 # Number of loads that were rescheduled
584 system.cpu.iew.lsq.thread0.cacheBlocked 2614 # Number of times an access to memory failed due to the cache being blocked
585 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
586 system.cpu.iew.iewSquashCycles 4071014 # Number of cycles IEW is squashing
587 system.cpu.iew.iewBlockCycles 26002336 # Number of cycles IEW is blocking
588 system.cpu.iew.iewUnblockCycles 1398631 # Number of cycles IEW is unblocking
589 system.cpu.iew.iewDispatchedInsts 867218559 # Number of instructions dispatched to IQ
590 system.cpu.iew.iewDispSquashedInsts 301512 # Number of squashed instructions skipped by dispatch
591 system.cpu.iew.iewDispLoadInsts 18887370 # Number of dispatched load instructions
592 system.cpu.iew.iewDispStoreInsts 10441908 # Number of dispatched store instructions
593 system.cpu.iew.iewDispNonSpecInsts 882377 # Number of dispatched non-speculative instructions
594 system.cpu.iew.iewIQFullEvents 699130 # Number of times the IQ has become full, causing a stall
595 system.cpu.iew.iewLSQFullEvents 12813 # Number of times the LSQ has become full, causing a stall
596 system.cpu.iew.memOrderViolationEvents 11829 # Number of memory order violations
597 system.cpu.iew.predictedTakenIncorrect 701390 # Number of branches that were predicted taken incorrectly
598 system.cpu.iew.predictedNotTakenIncorrect 622436 # Number of branches that were predicted not taken incorrectly
599 system.cpu.iew.branchMispredicts 1323826 # Number of branch mispredicts detected at execute
600 system.cpu.iew.iewExecutedInsts 862338984 # Number of executed instructions
601 system.cpu.iew.iewExecLoadInsts 24725426 # Number of load instructions executed
602 system.cpu.iew.iewExecSquashedInsts 1917500 # Number of squashed instructions skipped in execute
603 system.cpu.iew.exec_swp 0 # number of swp insts executed
604 system.cpu.iew.exec_nop 0 # number of nop insts executed
605 system.cpu.iew.exec_refs 33920026 # number of memory reference insts executed
606 system.cpu.iew.exec_branches 86488789 # Number of branches executed
607 system.cpu.iew.exec_stores 9194600 # Number of stores executed
608 system.cpu.iew.exec_rate 1.869230 # Inst execution rate
609 system.cpu.iew.wb_sent 861878608 # cumulative count of insts sent to commit
610 system.cpu.iew.wb_count 853844403 # cumulative count of insts written-back
611 system.cpu.iew.wb_producers 669889230 # num instructions producing a value
612 system.cpu.iew.wb_consumers 1919047361 # num instructions consuming a value
613 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
614 system.cpu.iew.wb_rate 1.850816 # insts written-back per cycle
615 system.cpu.iew.wb_fanout 0.349074 # average fanout of values written-back
616 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
617 system.cpu.commit.commitCommittedInsts 426506235 # The number of committed instructions
618 system.cpu.commit.commitCommittedOps 840483958 # The number of committed instructions
619 system.cpu.commit.commitSquashedInsts 26630365 # The number of squashed insts skipped by commit
620 system.cpu.commit.commitNonSpecStalls 1515546 # The number of times commit has been forced to stall to communicate backwards
621 system.cpu.commit.branchMispredicts 1177301 # The number of times a branch was mispredicted
622 system.cpu.commit.committed_per_cycle::samples 298298866 # Number of insts commited each cycle
623 system.cpu.commit.committed_per_cycle::mean 2.817590 # Number of insts commited each cycle
624 system.cpu.commit.committed_per_cycle::stdev 2.864095 # Number of insts commited each cycle
625 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
626 system.cpu.commit.committed_per_cycle::0 117621447 39.43% 39.43% # Number of insts commited each cycle
627 system.cpu.commit.committed_per_cycle::1 14371375 4.82% 44.25% # Number of insts commited each cycle
628 system.cpu.commit.committed_per_cycle::2 4300832 1.44% 45.69% # Number of insts commited each cycle
629 system.cpu.commit.committed_per_cycle::3 76665686 25.70% 71.39% # Number of insts commited each cycle
630 system.cpu.commit.committed_per_cycle::4 3908070 1.31% 72.70% # Number of insts commited each cycle
631 system.cpu.commit.committed_per_cycle::5 1784515 0.60% 73.30% # Number of insts commited each cycle
632 system.cpu.commit.committed_per_cycle::6 1116090 0.37% 73.67% # Number of insts commited each cycle
633 system.cpu.commit.committed_per_cycle::7 71984342 24.13% 97.81% # Number of insts commited each cycle
634 system.cpu.commit.committed_per_cycle::8 6546509 2.19% 100.00% # Number of insts commited each cycle
635 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
636 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
637 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
638 system.cpu.commit.committed_per_cycle::total 298298866 # Number of insts commited each cycle
639 system.cpu.commit.committedInsts 426506235 # Number of instructions committed
640 system.cpu.commit.committedOps 840483958 # Number of ops (including micro ops) committed
641 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
642 system.cpu.commit.refs 23705364 # Number of memory references committed
643 system.cpu.commit.loads 15298781 # Number of loads committed
644 system.cpu.commit.membars 781557 # Number of memory barriers committed
645 system.cpu.commit.branches 85502209 # Number of branches committed
646 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
647 system.cpu.commit.int_insts 768310964 # Number of committed integer instructions.
648 system.cpu.commit.function_calls 0 # Number of function calls committed.
649 system.cpu.commit.bw_lim_events 6546509 # number cycles where commit BW limit reached
650 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
651 system.cpu.rob.rob_reads 1158787398 # The number of ROB reads
652 system.cpu.rob.rob_writes 1738314967 # The number of ROB writes
653 system.cpu.timesIdled 2905540 # Number of times that the entire CPU went into an idle state and unscheduled itself
654 system.cpu.idleCycles 158979567 # Total number of cycles that the CPU has spent unscheduled due to idling
655 system.cpu.quiesceCycles 9853691832 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
656 system.cpu.committedInsts 426506235 # Number of Instructions Simulated
657 system.cpu.committedOps 840483958 # Number of Ops (including micro ops) Simulated
658 system.cpu.committedInsts_total 426506235 # Number of Instructions Simulated
659 system.cpu.cpi 1.081658 # CPI: Cycles Per Instruction
660 system.cpu.cpi_total 1.081658 # CPI: Total CPI of All Threads
661 system.cpu.ipc 0.924507 # IPC: Instructions Per Cycle
662 system.cpu.ipc_total 0.924507 # IPC: Total IPC of All Threads
663 system.cpu.int_regfile_reads 2163093750 # number of integer regfile reads
664 system.cpu.int_regfile_writes 1362601470 # number of integer regfile writes
665 system.cpu.fp_regfile_reads 80 # number of floating regfile reads
666 system.cpu.misc_regfile_reads 281025584 # number of misc regfile reads
667 system.cpu.misc_regfile_writes 403474 # number of misc regfile writes
668 system.cpu.icache.replacements 1083149 # number of replacements
669 system.cpu.icache.tagsinuse 510.211811 # Cycle average of tags in use
670 system.cpu.icache.total_refs 8213603 # Total number of references to valid blocks.
671 system.cpu.icache.sampled_refs 1083661 # Sample count of references to valid blocks.
672 system.cpu.icache.avg_refs 7.579495 # Average number of references to valid blocks.
673 system.cpu.icache.warmup_cycle 56616978000 # Cycle when the warmup percentage was hit.
674 system.cpu.icache.occ_blocks::cpu.inst 510.211811 # Average occupied blocks per requestor
675 system.cpu.icache.occ_percent::cpu.inst 0.996507 # Average percentage of cache occupancy
676 system.cpu.icache.occ_percent::total 0.996507 # Average percentage of cache occupancy
677 system.cpu.icache.ReadReq_hits::cpu.inst 8213603 # number of ReadReq hits
678 system.cpu.icache.ReadReq_hits::total 8213603 # number of ReadReq hits
679 system.cpu.icache.demand_hits::cpu.inst 8213603 # number of demand (read+write) hits
680 system.cpu.icache.demand_hits::total 8213603 # number of demand (read+write) hits
681 system.cpu.icache.overall_hits::cpu.inst 8213603 # number of overall hits
682 system.cpu.icache.overall_hits::total 8213603 # number of overall hits
683 system.cpu.icache.ReadReq_misses::cpu.inst 1153196 # number of ReadReq misses
684 system.cpu.icache.ReadReq_misses::total 1153196 # number of ReadReq misses
685 system.cpu.icache.demand_misses::cpu.inst 1153196 # number of demand (read+write) misses
686 system.cpu.icache.demand_misses::total 1153196 # number of demand (read+write) misses
687 system.cpu.icache.overall_misses::cpu.inst 1153196 # number of overall misses
688 system.cpu.icache.overall_misses::total 1153196 # number of overall misses
689 system.cpu.icache.ReadReq_miss_latency::cpu.inst 17226505491 # number of ReadReq miss cycles
690 system.cpu.icache.ReadReq_miss_latency::total 17226505491 # number of ReadReq miss cycles
691 system.cpu.icache.demand_miss_latency::cpu.inst 17226505491 # number of demand (read+write) miss cycles
692 system.cpu.icache.demand_miss_latency::total 17226505491 # number of demand (read+write) miss cycles
693 system.cpu.icache.overall_miss_latency::cpu.inst 17226505491 # number of overall miss cycles
694 system.cpu.icache.overall_miss_latency::total 17226505491 # number of overall miss cycles
695 system.cpu.icache.ReadReq_accesses::cpu.inst 9366799 # number of ReadReq accesses(hits+misses)
696 system.cpu.icache.ReadReq_accesses::total 9366799 # number of ReadReq accesses(hits+misses)
697 system.cpu.icache.demand_accesses::cpu.inst 9366799 # number of demand (read+write) accesses
698 system.cpu.icache.demand_accesses::total 9366799 # number of demand (read+write) accesses
699 system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses
700 system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses
701 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses
702 system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses
703 system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses
704 system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses
705 system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses
706 system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses
707 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency
708 system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency
709 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency
710 system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency
711 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency
712 system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency
713 system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked
714 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
715 system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked
716 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
717 system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990 # average number of cycles each access was blocked
718 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
719 system.cpu.icache.fast_writes 0 # number of fast writes performed
720 system.cpu.icache.cache_copies 0 # number of cache copies performed
721 system.cpu.icache.writebacks::writebacks 1570 # number of writebacks
722 system.cpu.icache.writebacks::total 1570 # number of writebacks
723 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68394 # number of ReadReq MSHR hits
724 system.cpu.icache.ReadReq_mshr_hits::total 68394 # number of ReadReq MSHR hits
725 system.cpu.icache.demand_mshr_hits::cpu.inst 68394 # number of demand (read+write) MSHR hits
726 system.cpu.icache.demand_mshr_hits::total 68394 # number of demand (read+write) MSHR hits
727 system.cpu.icache.overall_mshr_hits::cpu.inst 68394 # number of overall MSHR hits
728 system.cpu.icache.overall_mshr_hits::total 68394 # number of overall MSHR hits
729 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1084802 # number of ReadReq MSHR misses
730 system.cpu.icache.ReadReq_mshr_misses::total 1084802 # number of ReadReq MSHR misses
731 system.cpu.icache.demand_mshr_misses::cpu.inst 1084802 # number of demand (read+write) MSHR misses
732 system.cpu.icache.demand_mshr_misses::total 1084802 # number of demand (read+write) MSHR misses
733 system.cpu.icache.overall_mshr_misses::cpu.inst 1084802 # number of overall MSHR misses
734 system.cpu.icache.overall_mshr_misses::total 1084802 # number of overall MSHR misses
735 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13093471492 # number of ReadReq MSHR miss cycles
736 system.cpu.icache.ReadReq_mshr_miss_latency::total 13093471492 # number of ReadReq MSHR miss cycles
737 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13093471492 # number of demand (read+write) MSHR miss cycles
738 system.cpu.icache.demand_mshr_miss_latency::total 13093471492 # number of demand (read+write) MSHR miss cycles
739 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles
740 system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles
741 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses
742 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses
743 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses
744 system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses
745 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses
746 system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses
747 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency
748 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency
749 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency
750 system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
751 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency
752 system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
753 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
754 system.cpu.itb_walker_cache.replacements 10825 # number of replacements
755 system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use
756 system.cpu.itb_walker_cache.total_refs 27185 # Total number of references to valid blocks.
757 system.cpu.itb_walker_cache.sampled_refs 10834 # Sample count of references to valid blocks.
758 system.cpu.itb_walker_cache.avg_refs 2.509230 # Average number of references to valid blocks.
759 system.cpu.itb_walker_cache.warmup_cycle 5135028893000 # Cycle when the warmup percentage was hit.
760 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.011393 # Average occupied blocks per requestor
761 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375712 # Average percentage of cache occupancy
762 system.cpu.itb_walker_cache.occ_percent::total 0.375712 # Average percentage of cache occupancy
763 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27407 # number of ReadReq hits
764 system.cpu.itb_walker_cache.ReadReq_hits::total 27407 # number of ReadReq hits
765 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
766 system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
767 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27410 # number of demand (read+write) hits
768 system.cpu.itb_walker_cache.demand_hits::total 27410 # number of demand (read+write) hits
769 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27410 # number of overall hits
770 system.cpu.itb_walker_cache.overall_hits::total 27410 # number of overall hits
771 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11687 # number of ReadReq misses
772 system.cpu.itb_walker_cache.ReadReq_misses::total 11687 # number of ReadReq misses
773 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11687 # number of demand (read+write) misses
774 system.cpu.itb_walker_cache.demand_misses::total 11687 # number of demand (read+write) misses
775 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11687 # number of overall misses
776 system.cpu.itb_walker_cache.overall_misses::total 11687 # number of overall misses
777 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 148214000 # number of ReadReq miss cycles
778 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 148214000 # number of ReadReq miss cycles
779 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 148214000 # number of demand (read+write) miss cycles
780 system.cpu.itb_walker_cache.demand_miss_latency::total 148214000 # number of demand (read+write) miss cycles
781 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 148214000 # number of overall miss cycles
782 system.cpu.itb_walker_cache.overall_miss_latency::total 148214000 # number of overall miss cycles
783 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39094 # number of ReadReq accesses(hits+misses)
784 system.cpu.itb_walker_cache.ReadReq_accesses::total 39094 # number of ReadReq accesses(hits+misses)
785 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
786 system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
787 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39097 # number of demand (read+write) accesses
788 system.cpu.itb_walker_cache.demand_accesses::total 39097 # number of demand (read+write) accesses
789 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses
790 system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses
791 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses
792 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses
793 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses
794 system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses
795 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses
796 system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses
797 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency
798 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency
799 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency
800 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency
801 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency
802 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency
803 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
804 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
805 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
806 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
807 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
808 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
809 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
810 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
811 system.cpu.itb_walker_cache.writebacks::writebacks 1456 # number of writebacks
812 system.cpu.itb_walker_cache.writebacks::total 1456 # number of writebacks
813 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11687 # number of ReadReq MSHR misses
814 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11687 # number of ReadReq MSHR misses
815 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11687 # number of demand (read+write) MSHR misses
816 system.cpu.itb_walker_cache.demand_mshr_misses::total 11687 # number of demand (read+write) MSHR misses
817 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11687 # number of overall MSHR misses
818 system.cpu.itb_walker_cache.overall_mshr_misses::total 11687 # number of overall MSHR misses
819 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 112719500 # number of ReadReq MSHR miss cycles
820 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 112719500 # number of ReadReq MSHR miss cycles
821 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 112719500 # number of demand (read+write) MSHR miss cycles
822 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 # number of demand (read+write) MSHR miss cycles
823 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles
824 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles
825 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses
826 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses
827 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses
828 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses
829 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses
830 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses
831 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency
832 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency
833 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency
834 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
835 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency
836 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
837 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
838 system.cpu.dtb_walker_cache.replacements 116553 # number of replacements
839 system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use
840 system.cpu.dtb_walker_cache.total_refs 135956 # Total number of references to valid blocks.
841 system.cpu.dtb_walker_cache.sampled_refs 116568 # Sample count of references to valid blocks.
842 system.cpu.dtb_walker_cache.avg_refs 1.166324 # Average number of references to valid blocks.
843 system.cpu.dtb_walker_cache.warmup_cycle 5108641793000 # Cycle when the warmup percentage was hit.
844 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.859632 # Average occupied blocks per requestor
845 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866227 # Average percentage of cache occupancy
846 system.cpu.dtb_walker_cache.occ_percent::total 0.866227 # Average percentage of cache occupancy
847 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135961 # number of ReadReq hits
848 system.cpu.dtb_walker_cache.ReadReq_hits::total 135961 # number of ReadReq hits
849 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135961 # number of demand (read+write) hits
850 system.cpu.dtb_walker_cache.demand_hits::total 135961 # number of demand (read+write) hits
851 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135961 # number of overall hits
852 system.cpu.dtb_walker_cache.overall_hits::total 135961 # number of overall hits
853 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117570 # number of ReadReq misses
854 system.cpu.dtb_walker_cache.ReadReq_misses::total 117570 # number of ReadReq misses
855 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117570 # number of demand (read+write) misses
856 system.cpu.dtb_walker_cache.demand_misses::total 117570 # number of demand (read+write) misses
857 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117570 # number of overall misses
858 system.cpu.dtb_walker_cache.overall_misses::total 117570 # number of overall misses
859 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1642151000 # number of ReadReq miss cycles
860 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1642151000 # number of ReadReq miss cycles
861 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1642151000 # number of demand (read+write) miss cycles
862 system.cpu.dtb_walker_cache.demand_miss_latency::total 1642151000 # number of demand (read+write) miss cycles
863 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1642151000 # number of overall miss cycles
864 system.cpu.dtb_walker_cache.overall_miss_latency::total 1642151000 # number of overall miss cycles
865 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253531 # number of ReadReq accesses(hits+misses)
866 system.cpu.dtb_walker_cache.ReadReq_accesses::total 253531 # number of ReadReq accesses(hits+misses)
867 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253531 # number of demand (read+write) accesses
868 system.cpu.dtb_walker_cache.demand_accesses::total 253531 # number of demand (read+write) accesses
869 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses
870 system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses
871 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses
872 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses
873 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses
874 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses
875 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses
876 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses
877 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency
878 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency
879 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency
880 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency
881 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency
882 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency
883 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
884 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
885 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
886 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
887 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
888 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
889 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
890 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
891 system.cpu.dtb_walker_cache.writebacks::writebacks 36817 # number of writebacks
892 system.cpu.dtb_walker_cache.writebacks::total 36817 # number of writebacks
893 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117570 # number of ReadReq MSHR misses
894 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117570 # number of ReadReq MSHR misses
895 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117570 # number of demand (read+write) MSHR misses
896 system.cpu.dtb_walker_cache.demand_mshr_misses::total 117570 # number of demand (read+write) MSHR misses
897 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117570 # number of overall MSHR misses
898 system.cpu.dtb_walker_cache.overall_mshr_misses::total 117570 # number of overall MSHR misses
899 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of ReadReq MSHR miss cycles
900 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1286519500 # number of ReadReq MSHR miss cycles
901 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of demand (read+write) MSHR miss cycles
902 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 # number of demand (read+write) MSHR miss cycles
903 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles
904 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles
905 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses
906 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses
907 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses
908 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses
909 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses
910 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses
911 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency
912 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency
913 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency
914 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
915 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency
916 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
917 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
918 system.cpu.dcache.replacements 1673290 # number of replacements
919 system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use
920 system.cpu.dcache.total_refs 19026186 # Total number of references to valid blocks.
921 system.cpu.dcache.sampled_refs 1673802 # Sample count of references to valid blocks.
922 system.cpu.dcache.avg_refs 11.367047 # Average number of references to valid blocks.
923 system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit.
924 system.cpu.dcache.occ_blocks::cpu.data 511.997033 # Average occupied blocks per requestor
925 system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
926 system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
927 system.cpu.dcache.ReadReq_hits::cpu.data 10943323 # number of ReadReq hits
928 system.cpu.dcache.ReadReq_hits::total 10943323 # number of ReadReq hits
929 system.cpu.dcache.WriteReq_hits::cpu.data 8079241 # number of WriteReq hits
930 system.cpu.dcache.WriteReq_hits::total 8079241 # number of WriteReq hits
931 system.cpu.dcache.demand_hits::cpu.data 19022564 # number of demand (read+write) hits
932 system.cpu.dcache.demand_hits::total 19022564 # number of demand (read+write) hits
933 system.cpu.dcache.overall_hits::cpu.data 19022564 # number of overall hits
934 system.cpu.dcache.overall_hits::total 19022564 # number of overall hits
935 system.cpu.dcache.ReadReq_misses::cpu.data 2411423 # number of ReadReq misses
936 system.cpu.dcache.ReadReq_misses::total 2411423 # number of ReadReq misses
937 system.cpu.dcache.WriteReq_misses::cpu.data 318003 # number of WriteReq misses
938 system.cpu.dcache.WriteReq_misses::total 318003 # number of WriteReq misses
939 system.cpu.dcache.demand_misses::cpu.data 2729426 # number of demand (read+write) misses
940 system.cpu.dcache.demand_misses::total 2729426 # number of demand (read+write) misses
941 system.cpu.dcache.overall_misses::cpu.data 2729426 # number of overall misses
942 system.cpu.dcache.overall_misses::total 2729426 # number of overall misses
943 system.cpu.dcache.ReadReq_miss_latency::cpu.data 36183001500 # number of ReadReq miss cycles
944 system.cpu.dcache.ReadReq_miss_latency::total 36183001500 # number of ReadReq miss cycles
945 system.cpu.dcache.WriteReq_miss_latency::cpu.data 10564799496 # number of WriteReq miss cycles
946 system.cpu.dcache.WriteReq_miss_latency::total 10564799496 # number of WriteReq miss cycles
947 system.cpu.dcache.demand_miss_latency::cpu.data 46747800996 # number of demand (read+write) miss cycles
948 system.cpu.dcache.demand_miss_latency::total 46747800996 # number of demand (read+write) miss cycles
949 system.cpu.dcache.overall_miss_latency::cpu.data 46747800996 # number of overall miss cycles
950 system.cpu.dcache.overall_miss_latency::total 46747800996 # number of overall miss cycles
951 system.cpu.dcache.ReadReq_accesses::cpu.data 13354746 # number of ReadReq accesses(hits+misses)
952 system.cpu.dcache.ReadReq_accesses::total 13354746 # number of ReadReq accesses(hits+misses)
953 system.cpu.dcache.WriteReq_accesses::cpu.data 8397244 # number of WriteReq accesses(hits+misses)
954 system.cpu.dcache.WriteReq_accesses::total 8397244 # number of WriteReq accesses(hits+misses)
955 system.cpu.dcache.demand_accesses::cpu.data 21751990 # number of demand (read+write) accesses
956 system.cpu.dcache.demand_accesses::total 21751990 # number of demand (read+write) accesses
957 system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses
958 system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses
959 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses
960 system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses
961 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses
962 system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses
963 system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses
964 system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses
965 system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses
966 system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses
967 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency
968 system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency
969 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency
970 system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency
971 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency
972 system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency
973 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency
974 system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency
975 system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked
976 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
977 system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked
978 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
979 system.cpu.dcache.avg_blocked_cycles::no_mshrs 6822.145924 # average number of cycles each access was blocked
980 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
981 system.cpu.dcache.fast_writes 0 # number of fast writes performed
982 system.cpu.dcache.cache_copies 0 # number of cache copies performed
983 system.cpu.dcache.writebacks::writebacks 1560881 # number of writebacks
984 system.cpu.dcache.writebacks::total 1560881 # number of writebacks
985 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1029888 # number of ReadReq MSHR hits
986 system.cpu.dcache.ReadReq_mshr_hits::total 1029888 # number of ReadReq MSHR hits
987 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22394 # number of WriteReq MSHR hits
988 system.cpu.dcache.WriteReq_mshr_hits::total 22394 # number of WriteReq MSHR hits
989 system.cpu.dcache.demand_mshr_hits::cpu.data 1052282 # number of demand (read+write) MSHR hits
990 system.cpu.dcache.demand_mshr_hits::total 1052282 # number of demand (read+write) MSHR hits
991 system.cpu.dcache.overall_mshr_hits::cpu.data 1052282 # number of overall MSHR hits
992 system.cpu.dcache.overall_mshr_hits::total 1052282 # number of overall MSHR hits
993 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381535 # number of ReadReq MSHR misses
994 system.cpu.dcache.ReadReq_mshr_misses::total 1381535 # number of ReadReq MSHR misses
995 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295609 # number of WriteReq MSHR misses
996 system.cpu.dcache.WriteReq_mshr_misses::total 295609 # number of WriteReq MSHR misses
997 system.cpu.dcache.demand_mshr_misses::cpu.data 1677144 # number of demand (read+write) MSHR misses
998 system.cpu.dcache.demand_mshr_misses::total 1677144 # number of demand (read+write) MSHR misses
999 system.cpu.dcache.overall_mshr_misses::cpu.data 1677144 # number of overall MSHR misses
1000 system.cpu.dcache.overall_mshr_misses::total 1677144 # number of overall MSHR misses
1001 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18178804500 # number of ReadReq MSHR miss cycles
1002 system.cpu.dcache.ReadReq_mshr_miss_latency::total 18178804500 # number of ReadReq MSHR miss cycles
1003 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9348322497 # number of WriteReq MSHR miss cycles
1004 system.cpu.dcache.WriteReq_mshr_miss_latency::total 9348322497 # number of WriteReq MSHR miss cycles
1005 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27527126997 # number of demand (read+write) MSHR miss cycles
1006 system.cpu.dcache.demand_mshr_miss_latency::total 27527126997 # number of demand (read+write) MSHR miss cycles
1007 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27527126997 # number of overall MSHR miss cycles
1008 system.cpu.dcache.overall_mshr_miss_latency::total 27527126997 # number of overall MSHR miss cycles
1009 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207754500 # number of ReadReq MSHR uncacheable cycles
1010 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207754500 # number of ReadReq MSHR uncacheable cycles
1011 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392930500 # number of WriteReq MSHR uncacheable cycles
1012 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 # number of WriteReq MSHR uncacheable cycles
1013 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles
1014 system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles
1015 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses
1016 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses
1017 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses
1018 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses
1019 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses
1020 system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses
1021 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses
1022 system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses
1023 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency
1024 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency
1025 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency
1026 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency
1027 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency
1028 system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
1029 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency
1030 system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
1031 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1032 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1033 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1034 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1035 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1036 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1037 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1038 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1039 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1041 ---------- End Simulation Statistics ----------
projects / gem5.git / blob