2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.125946 # Number of seconds simulated
4 sim_ticks 5125946039500 # Number of ticks simulated
5 final_tick 5125946039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 214937 # Simulator instruction rate (inst/s)
8 host_op_rate 424847 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2699457200 # Simulator tick rate (ticks/s)
10 host_mem_usage 751580 # Number of bytes of host memory used
11 host_seconds 1898.88 # Real time elapsed on the host
12 sim_insts 408140259 # Number of instructions simulated
13 sim_ops 806733017 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1045568 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10796928 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11875520 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1045568 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1045568 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9590656 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9590656 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16337 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168702 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185555 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149854 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149854 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 849 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 203976 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2106329 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2316747 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 203976 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 203976 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1871002 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1871002 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1871002 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 849 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 203976 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2106329 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4187749 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185555 # Number of read requests accepted
52 system.physmem.writeReqs 196574 # Number of write requests accepted
53 system.physmem.readBursts 185555 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 196574 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11866560 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 12447744 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11875520 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 12580736 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 2049 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1754 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11700 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 10942 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 11772 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11534 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11556 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11202 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 11589 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11470 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 10957 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11574 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11037 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11773 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 12032 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 13037 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11759 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11481 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 13445 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 12349 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 11384 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 11463 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 12267 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 12371 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 11486 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 11359 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 11596 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 12338 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 11770 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 12080 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 12282 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 12669 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 12453 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 13184 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
97 system.physmem.totGap 5125945988000 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185555 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 196574 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 170769 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11917 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 2025 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 375 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2509 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 4824 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 9547 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 10935 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 11433 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 12449 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 12895 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 13963 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 13629 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 14296 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 13176 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 12672 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 11348 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 10803 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 9189 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 8678 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 8475 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 592 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 508 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 443 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 373 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 213 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 194 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 156 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 147 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 75192 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 323.362060 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 187.476414 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 341.898646 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 27996 37.23% 37.23% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17297 23.00% 60.24% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7451 9.91% 70.15% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4205 5.59% 75.74% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 3004 4.00% 79.73% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2064 2.74% 82.48% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1408 1.87% 84.35% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1199 1.59% 85.95% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 10568 14.05% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 75192 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7811 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 23.734349 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 544.550807 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7810 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7811 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7811 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 24.900269 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 20.294695 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 24.961495 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6395 81.87% 81.87% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 66 0.84% 82.72% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 12 0.15% 82.87% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 258 3.30% 86.17% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 186 2.38% 88.55% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 50 0.64% 89.19% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 38 0.49% 89.68% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 45 0.58% 90.26% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 169 2.16% 92.42% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 11 0.14% 92.56% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 12 0.15% 92.72% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 16 0.20% 92.92% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 26 0.33% 93.25% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 16 0.20% 93.46% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 15 0.19% 93.65% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 41 0.52% 94.17% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 93 1.19% 95.37% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::84-87 13 0.17% 95.53% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::88-91 9 0.12% 95.65% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::92-95 19 0.24% 95.89% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::96-99 147 1.88% 97.77% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::100-103 3 0.04% 97.81% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::104-107 13 0.17% 97.98% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::108-111 4 0.05% 98.03% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::112-115 20 0.26% 98.28% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::116-119 9 0.12% 98.40% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::120-123 5 0.06% 98.46% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::124-127 3 0.04% 98.50% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::128-131 27 0.35% 98.85% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::132-135 13 0.17% 99.01% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::136-139 2 0.03% 99.04% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::140-143 4 0.05% 99.09% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::144-147 11 0.14% 99.23% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::148-151 10 0.13% 99.36% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::152-155 4 0.05% 99.41% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::156-159 2 0.03% 99.44% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::160-163 5 0.06% 99.50% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::164-167 3 0.04% 99.54% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::168-171 3 0.04% 99.58% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::172-175 2 0.03% 99.60% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::176-179 7 0.09% 99.69% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::180-183 1 0.01% 99.71% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::184-187 1 0.01% 99.72% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::188-191 2 0.03% 99.74% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::208-211 1 0.01% 99.76% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::212-215 1 0.01% 99.77% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::216-219 1 0.01% 99.78% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::220-223 7 0.09% 99.87% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::224-227 3 0.04% 99.91% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::228-231 2 0.03% 99.94% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::248-251 4 0.05% 99.99% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::total 7811 # Writes before turning the bus around for reads
285 system.physmem.totQLat 1990259250 # Total ticks spent queuing
286 system.physmem.totMemAccLat 5466790500 # Total ticks spent from burst creation until serviced by the DRAM
287 system.physmem.totBusLat 927075000 # Total ticks spent in databus transfers
288 system.physmem.avgQLat 10734.08 # Average queueing delay per DRAM burst
289 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
290 system.physmem.avgMemAccLat 29484.08 # Average memory access latency per DRAM burst
291 system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
292 system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s
293 system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
294 system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
295 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
296 system.physmem.busUtil 0.04 # Data bus utilization in percentage
297 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
298 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
299 system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
300 system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing
301 system.physmem.readRowHits 152358 # Number of row buffer hits during reads
302 system.physmem.writeRowHits 152360 # Number of row buffer hits during writes
303 system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads
304 system.physmem.writeRowHitRate 78.32 # Row buffer hit rate for writes
305 system.physmem.avgGap 13414176.86 # Average gap between requests
306 system.physmem.pageHitRate 80.20 # Row buffer hit rate, read and write combined
307 system.physmem_0.actEnergy 277686360 # Energy for activate commands per rank (pJ)
308 system.physmem_0.preEnergy 151515375 # Energy for precharge commands per rank (pJ)
309 system.physmem_0.readEnergy 715759200 # Energy for read commands per rank (pJ)
310 system.physmem_0.writeEnergy 622883520 # Energy for write commands per rank (pJ)
311 system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ)
312 system.physmem_0.actBackEnergy 129454885665 # Energy for active background per rank (pJ)
313 system.physmem_0.preBackEnergy 2962010423250 # Energy for precharge background per rank (pJ)
314 system.physmem_0.totalEnergy 3428034983850 # Total energy per rank (pJ)
315 system.physmem_0.averagePower 668.761488 # Core power per rank (mW)
316 system.physmem_0.memoryStateTime::IDLE 4927497903250 # Time in different power states
317 system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states
318 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
319 system.physmem_0.memoryStateTime::ACT 27281453250 # Time in different power states
320 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
321 system.physmem_1.actEnergy 290765160 # Energy for activate commands per rank (pJ)
322 system.physmem_1.preEnergy 158651625 # Energy for precharge commands per rank (pJ)
323 system.physmem_1.readEnergy 730470000 # Energy for read commands per rank (pJ)
324 system.physmem_1.writeEnergy 637450560 # Energy for write commands per rank (pJ)
325 system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ)
326 system.physmem_1.actBackEnergy 129625961760 # Energy for active background per rank (pJ)
327 system.physmem_1.preBackEnergy 2961860356500 # Energy for precharge background per rank (pJ)
328 system.physmem_1.totalEnergy 3428105486085 # Total energy per rank (pJ)
329 system.physmem_1.averagePower 668.775242 # Core power per rank (mW)
330 system.physmem_1.memoryStateTime::IDLE 4927247811250 # Time in different power states
331 system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states
332 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
333 system.physmem_1.memoryStateTime::ACT 27531190000 # Time in different power states
334 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
335 system.cpu.branchPred.lookups 87010872 # Number of BP lookups
336 system.cpu.branchPred.condPredicted 87010872 # Number of conditional branches predicted
337 system.cpu.branchPred.condIncorrect 908907 # Number of conditional branches incorrect
338 system.cpu.branchPred.BTBLookups 80241948 # Number of BTB lookups
339 system.cpu.branchPred.BTBHits 78260393 # Number of BTB hits
340 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
341 system.cpu.branchPred.BTBHitPct 97.530525 # BTB Hit Percentage
342 system.cpu.branchPred.usedRAS 1567280 # Number of times the RAS was used to get a target.
343 system.cpu.branchPred.RASInCorrect 181222 # Number of incorrect RAS predictions.
344 system.cpu_clk_domain.clock 500 # Clock period in ticks
345 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
346 system.cpu.numCycles 449757362 # number of cpu cycles simulated
347 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
348 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
349 system.cpu.fetch.icacheStallCycles 27680627 # Number of cycles fetch is stalled on an Icache miss
350 system.cpu.fetch.Insts 429642410 # Number of instructions fetch has processed
351 system.cpu.fetch.Branches 87010872 # Number of branches that fetch encountered
352 system.cpu.fetch.predictedBranches 79827673 # Number of branches that fetch has predicted taken
353 system.cpu.fetch.Cycles 418150440 # Number of cycles fetch has run and was not squashing or blocked
354 system.cpu.fetch.SquashCycles 1906654 # Number of cycles fetch has spent squashing
355 system.cpu.fetch.TlbCycles 150208 # Number of cycles fetch has spent waiting for tlb
356 system.cpu.fetch.MiscStallCycles 58666 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
357 system.cpu.fetch.PendingTrapStallCycles 213443 # Number of stall cycles due to pending traps
358 system.cpu.fetch.PendingQuiesceStallCycles 140 # Number of stall cycles due to pending quiesce instructions
359 system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR
360 system.cpu.fetch.CacheLines 9233721 # Number of cache lines fetched
361 system.cpu.fetch.IcacheSquashes 451702 # Number of outstanding Icache misses that were squashed
362 system.cpu.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed
363 system.cpu.fetch.rateDist::samples 447207287 # Number of instructions fetched each cycle (Total)
364 system.cpu.fetch.rateDist::mean 1.895606 # Number of instructions fetched each cycle (Total)
365 system.cpu.fetch.rateDist::stdev 3.052695 # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::0 281559277 62.96% 62.96% # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::1 2214583 0.50% 63.45% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::2 72218429 16.15% 79.60% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::3 1625336 0.36% 79.97% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::4 2151026 0.48% 80.45% # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::5 2311115 0.52% 80.96% # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::6 1533968 0.34% 81.31% # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.rateDist::7 1910699 0.43% 81.73% # Number of instructions fetched each cycle (Total)
375 system.cpu.fetch.rateDist::8 81682854 18.27% 100.00% # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
378 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
379 system.cpu.fetch.rateDist::total 447207287 # Number of instructions fetched each cycle (Total)
380 system.cpu.fetch.branchRate 0.193462 # Number of branch fetches per cycle
381 system.cpu.fetch.rate 0.955276 # Number of inst fetches per cycle
382 system.cpu.decode.IdleCycles 23009193 # Number of cycles decode is idle
383 system.cpu.decode.BlockedCycles 264931793 # Number of cycles decode is blocked
384 system.cpu.decode.RunCycles 150859313 # Number of cycles decode is running
385 system.cpu.decode.UnblockCycles 7453661 # Number of cycles decode is unblocking
386 system.cpu.decode.SquashCycles 953327 # Number of cycles decode is squashing
387 system.cpu.decode.DecodedInsts 839350026 # Number of instructions handled by decode
388 system.cpu.rename.SquashCycles 953327 # Number of cycles rename is squashing
389 system.cpu.rename.IdleCycles 25875798 # Number of cycles rename is idle
390 system.cpu.rename.BlockCycles 223334745 # Number of cycles rename is blocking
391 system.cpu.rename.serializeStallCycles 13198087 # count of cycles rename stalled for serializing inst
392 system.cpu.rename.RunCycles 154759437 # Number of cycles rename is running
393 system.cpu.rename.UnblockCycles 29085893 # Number of cycles rename is unblocking
394 system.cpu.rename.RenamedInsts 835811014 # Number of instructions processed by rename
395 system.cpu.rename.ROBFullEvents 482001 # Number of times rename has blocked due to ROB full
396 system.cpu.rename.IQFullEvents 12419616 # Number of times rename has blocked due to IQ full
397 system.cpu.rename.LQFullEvents 206377 # Number of times rename has blocked due to LQ full
398 system.cpu.rename.SQFullEvents 13783403 # Number of times rename has blocked due to SQ full
399 system.cpu.rename.RenamedOperands 998347758 # Number of destination operands rename has renamed
400 system.cpu.rename.RenameLookups 1815644422 # Number of register rename lookups that rename has made
401 system.cpu.rename.int_rename_lookups 1116079946 # Number of integer rename lookups
402 system.cpu.rename.fp_rename_lookups 122 # Number of floating rename lookups
403 system.cpu.rename.CommittedMaps 964783456 # Number of HB maps that are committed
404 system.cpu.rename.UndoneMaps 33564300 # Number of HB maps that are undone due to squashing
405 system.cpu.rename.serializingInsts 467714 # count of serializing insts renamed
406 system.cpu.rename.tempSerializingInsts 471747 # count of temporary serializing insts renamed
407 system.cpu.rename.skidInsts 39093495 # count of insts added to the skid buffer
408 system.cpu.memDep0.insertedLoads 17396694 # Number of loads inserted to the mem dependence unit.
409 system.cpu.memDep0.insertedStores 10208602 # Number of stores inserted to the mem dependence unit.
410 system.cpu.memDep0.conflictingLoads 1304613 # Number of conflicting loads.
411 system.cpu.memDep0.conflictingStores 1095322 # Number of conflicting stores.
412 system.cpu.iq.iqInstsAdded 830247357 # Number of instructions added to the IQ (excludes non-spec)
413 system.cpu.iq.iqNonSpecInstsAdded 1203823 # Number of non-speculative instructions added to the IQ
414 system.cpu.iq.iqInstsIssued 824890478 # Number of instructions issued
415 system.cpu.iq.iqSquashedInstsIssued 241321 # Number of squashed instructions issued
416 system.cpu.iq.iqSquashedInstsExamined 23772173 # Number of squashed instructions iterated over during squash; mainly for profiling
417 system.cpu.iq.iqSquashedOperandsExamined 36627244 # Number of squashed operands that are examined and possibly removed from graph
418 system.cpu.iq.iqSquashedNonSpecRemoved 152885 # Number of squashed non-spec instructions that were removed
419 system.cpu.iq.issued_per_cycle::samples 447207287 # Number of insts issued each cycle
420 system.cpu.iq.issued_per_cycle::mean 1.844537 # Number of insts issued each cycle
421 system.cpu.iq.issued_per_cycle::stdev 2.418419 # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::0 262823455 58.77% 58.77% # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::1 13859186 3.10% 61.87% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::2 10127573 2.26% 64.13% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::3 6921797 1.55% 65.68% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::4 74369123 16.63% 82.31% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::5 4467728 1.00% 83.31% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::6 72848553 16.29% 99.60% # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::7 1214671 0.27% 99.87% # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::8 575201 0.13% 100.00% # Number of insts issued each cycle
432 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
433 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
434 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
435 system.cpu.iq.issued_per_cycle::total 447207287 # Number of insts issued each cycle
436 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
437 system.cpu.iq.fu_full::IntAlu 2002012 72.04% 72.04% # attempts to use FU when none available
438 system.cpu.iq.fu_full::IntMult 252 0.01% 72.05% # attempts to use FU when none available
439 system.cpu.iq.fu_full::IntDiv 1516 0.05% 72.10% # attempts to use FU when none available
440 system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.10% # attempts to use FU when none available
441 system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.10% # attempts to use FU when none available
442 system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.10% # attempts to use FU when none available
443 system.cpu.iq.fu_full::FloatMult 0 0.00% 72.10% # attempts to use FU when none available
444 system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.10% # attempts to use FU when none available
445 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.10% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.10% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.10% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.10% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.10% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.10% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.10% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdMult 0 0.00% 72.10% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.10% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdShift 0 0.00% 72.10% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.10% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.10% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.10% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.10% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.10% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.10% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.10% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.10% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.10% # attempts to use FU when none available
464 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.10% # attempts to use FU when none available
465 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.10% # attempts to use FU when none available
466 system.cpu.iq.fu_full::MemRead 615311 22.14% 94.24% # attempts to use FU when none available
467 system.cpu.iq.fu_full::MemWrite 160020 5.76% 100.00% # attempts to use FU when none available
468 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
469 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
470 system.cpu.iq.FU_type_0::No_OpClass 292641 0.04% 0.04% # Type of FU issued
471 system.cpu.iq.FU_type_0::IntAlu 796440241 96.55% 96.59% # Type of FU issued
472 system.cpu.iq.FU_type_0::IntMult 150873 0.02% 96.60% # Type of FU issued
473 system.cpu.iq.FU_type_0::IntDiv 125700 0.02% 96.62% # Type of FU issued
474 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
475 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
476 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
477 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
478 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
479 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
498 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
499 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
500 system.cpu.iq.FU_type_0::MemRead 18469737 2.24% 98.86% # Type of FU issued
501 system.cpu.iq.FU_type_0::MemWrite 9411286 1.14% 100.00% # Type of FU issued
502 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
503 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
504 system.cpu.iq.FU_type_0::total 824890478 # Type of FU issued
505 system.cpu.iq.rate 1.834079 # Inst issue rate
506 system.cpu.iq.fu_busy_cnt 2779111 # FU busy when requested
507 system.cpu.iq.fu_busy_rate 0.003369 # FU busy rate (busy events/executed inst)
508 system.cpu.iq.int_inst_queue_reads 2100008470 # Number of integer instruction queue reads
509 system.cpu.iq.int_inst_queue_writes 855235960 # Number of integer instruction queue writes
510 system.cpu.iq.int_inst_queue_wakeup_accesses 820301631 # Number of integer instruction queue wakeup accesses
511 system.cpu.iq.fp_inst_queue_reads 204 # Number of floating instruction queue reads
512 system.cpu.iq.fp_inst_queue_writes 226 # Number of floating instruction queue writes
513 system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses
514 system.cpu.iq.int_alu_accesses 827376851 # Number of integer alu accesses
515 system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
516 system.cpu.iew.lsq.thread0.forwLoads 1872015 # Number of loads that had data forwarded from stores
517 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
518 system.cpu.iew.lsq.thread0.squashedLoads 3394675 # Number of loads squashed
519 system.cpu.iew.lsq.thread0.ignoredResponses 15480 # Number of memory responses ignored because the instruction is squashed
520 system.cpu.iew.lsq.thread0.memOrderViolation 14595 # Number of memory ordering violations
521 system.cpu.iew.lsq.thread0.squashedStores 1778587 # Number of stores squashed
522 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
523 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
524 system.cpu.iew.lsq.thread0.rescheduledLoads 2224947 # Number of loads that were rescheduled
525 system.cpu.iew.lsq.thread0.cacheBlocked 72059 # Number of times an access to memory failed due to the cache being blocked
526 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
527 system.cpu.iew.iewSquashCycles 953327 # Number of cycles IEW is squashing
528 system.cpu.iew.iewBlockCycles 205633916 # Number of cycles IEW is blocking
529 system.cpu.iew.iewUnblockCycles 9395655 # Number of cycles IEW is unblocking
530 system.cpu.iew.iewDispatchedInsts 831451180 # Number of instructions dispatched to IQ
531 system.cpu.iew.iewDispSquashedInsts 157138 # Number of squashed instructions skipped by dispatch
532 system.cpu.iew.iewDispLoadInsts 17396694 # Number of dispatched load instructions
533 system.cpu.iew.iewDispStoreInsts 10208602 # Number of dispatched store instructions
534 system.cpu.iew.iewDispNonSpecInsts 706837 # Number of dispatched non-speculative instructions
535 system.cpu.iew.iewIQFullEvents 415978 # Number of times the IQ has become full, causing a stall
536 system.cpu.iew.iewLSQFullEvents 8079838 # Number of times the LSQ has become full, causing a stall
537 system.cpu.iew.memOrderViolationEvents 14595 # Number of memory order violations
538 system.cpu.iew.predictedTakenIncorrect 523025 # Number of branches that were predicted taken incorrectly
539 system.cpu.iew.predictedNotTakenIncorrect 540470 # Number of branches that were predicted not taken incorrectly
540 system.cpu.iew.branchMispredicts 1063495 # Number of branch mispredicts detected at execute
541 system.cpu.iew.iewExecutedInsts 823253062 # Number of executed instructions
542 system.cpu.iew.iewExecLoadInsts 18064803 # Number of load instructions executed
543 system.cpu.iew.iewExecSquashedInsts 1501922 # Number of squashed instructions skipped in execute
544 system.cpu.iew.exec_swp 0 # number of swp insts executed
545 system.cpu.iew.exec_nop 0 # number of nop insts executed
546 system.cpu.iew.exec_refs 27249763 # number of memory reference insts executed
547 system.cpu.iew.exec_branches 83367725 # Number of branches executed
548 system.cpu.iew.exec_stores 9184960 # Number of stores executed
549 system.cpu.iew.exec_rate 1.830438 # Inst execution rate
550 system.cpu.iew.wb_sent 822742058 # cumulative count of insts sent to commit
551 system.cpu.iew.wb_count 820301688 # cumulative count of insts written-back
552 system.cpu.iew.wb_producers 641478984 # num instructions producing a value
553 system.cpu.iew.wb_consumers 1051241156 # num instructions consuming a value
554 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
555 system.cpu.iew.wb_rate 1.823876 # insts written-back per cycle
556 system.cpu.iew.wb_fanout 0.610211 # average fanout of values written-back
557 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
558 system.cpu.commit.commitSquashedInsts 24588739 # The number of squashed insts skipped by commit
559 system.cpu.commit.commitNonSpecStalls 1050938 # The number of times commit has been forced to stall to communicate backwards
560 system.cpu.commit.branchMispredicts 921334 # The number of times a branch was mispredicted
561 system.cpu.commit.committed_per_cycle::samples 443513076 # Number of insts commited each cycle
562 system.cpu.commit.committed_per_cycle::mean 1.818961 # Number of insts commited each cycle
563 system.cpu.commit.committed_per_cycle::stdev 2.675251 # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::0 272623912 61.47% 61.47% # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::1 11196719 2.52% 63.99% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::2 3582296 0.81% 64.80% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::3 74597527 16.82% 81.62% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::4 2432522 0.55% 82.17% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::5 1609310 0.36% 82.53% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::6 947533 0.21% 82.75% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::7 71068767 16.02% 98.77% # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::8 5454490 1.23% 100.00% # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
575 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
576 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
577 system.cpu.commit.committed_per_cycle::total 443513076 # Number of insts commited each cycle
578 system.cpu.commit.committedInsts 408140259 # Number of instructions committed
579 system.cpu.commit.committedOps 806733017 # Number of ops (including micro ops) committed
580 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
581 system.cpu.commit.refs 22432033 # Number of memory references committed
582 system.cpu.commit.loads 14002018 # Number of loads committed
583 system.cpu.commit.membars 475437 # Number of memory barriers committed
584 system.cpu.commit.branches 82233213 # Number of branches committed
585 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
586 system.cpu.commit.int_insts 735520454 # Number of committed integer instructions.
587 system.cpu.commit.function_calls 1156067 # Number of function calls committed.
588 system.cpu.commit.op_class_0::No_OpClass 171671 0.02% 0.02% # Class of committed instruction
589 system.cpu.commit.op_class_0::IntAlu 783865362 97.17% 97.19% # Class of committed instruction
590 system.cpu.commit.op_class_0::IntMult 145082 0.02% 97.20% # Class of committed instruction
591 system.cpu.commit.op_class_0::IntDiv 121451 0.02% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
593 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
595 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
596 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
597 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
598 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
599 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
600 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
601 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
602 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
603 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
604 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
605 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
606 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
607 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
608 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
609 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
610 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
611 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
612 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
613 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
614 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
615 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
616 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
617 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
618 system.cpu.commit.op_class_0::MemRead 13999436 1.74% 98.96% # Class of committed instruction
619 system.cpu.commit.op_class_0::MemWrite 8430015 1.04% 100.00% # Class of committed instruction
620 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
621 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
622 system.cpu.commit.op_class_0::total 806733017 # Class of committed instruction
623 system.cpu.commit.bw_lim_events 5454490 # number cycles where commit BW limit reached
624 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
625 system.cpu.rob.rob_reads 1269302111 # The number of ROB reads
626 system.cpu.rob.rob_writes 1666357608 # The number of ROB writes
627 system.cpu.timesIdled 293383 # Number of times that the entire CPU went into an idle state and unscheduled itself
628 system.cpu.idleCycles 2550075 # Total number of cycles that the CPU has spent unscheduled due to idling
629 system.cpu.quiesceCycles 9802132382 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
630 system.cpu.committedInsts 408140259 # Number of Instructions Simulated
631 system.cpu.committedOps 806733017 # Number of Ops (including micro ops) Simulated
632 system.cpu.cpi 1.101968 # CPI: Cycles Per Instruction
633 system.cpu.cpi_total 1.101968 # CPI: Total CPI of All Threads
634 system.cpu.ipc 0.907468 # IPC: Instructions Per Cycle
635 system.cpu.ipc_total 0.907468 # IPC: Total IPC of All Threads
636 system.cpu.int_regfile_reads 1093345902 # number of integer regfile reads
637 system.cpu.int_regfile_writes 656583711 # number of integer regfile writes
638 system.cpu.fp_regfile_reads 57 # number of floating regfile reads
639 system.cpu.cc_regfile_reads 416569502 # number of cc regfile reads
640 system.cpu.cc_regfile_writes 322266839 # number of cc regfile writes
641 system.cpu.misc_regfile_reads 265844677 # number of misc regfile reads
642 system.cpu.misc_regfile_writes 400270 # number of misc regfile writes
643 system.cpu.dcache.tags.replacements 1661069 # number of replacements
644 system.cpu.dcache.tags.tagsinuse 511.997995 # Cycle average of tags in use
645 system.cpu.dcache.tags.total_refs 19180634 # Total number of references to valid blocks.
646 system.cpu.dcache.tags.sampled_refs 1661581 # Sample count of references to valid blocks.
647 system.cpu.dcache.tags.avg_refs 11.543605 # Average number of references to valid blocks.
648 system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
649 system.cpu.dcache.tags.occ_blocks::cpu.data 511.997995 # Average occupied blocks per requestor
650 system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
651 system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
652 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
653 system.cpu.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
654 system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
655 system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
656 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
657 system.cpu.dcache.tags.tag_accesses 88533012 # Number of tag accesses
658 system.cpu.dcache.tags.data_accesses 88533012 # Number of data accesses
659 system.cpu.dcache.ReadReq_hits::cpu.data 11025921 # number of ReadReq hits
660 system.cpu.dcache.ReadReq_hits::total 11025921 # number of ReadReq hits
661 system.cpu.dcache.WriteReq_hits::cpu.data 8086239 # number of WriteReq hits
662 system.cpu.dcache.WriteReq_hits::total 8086239 # number of WriteReq hits
663 system.cpu.dcache.SoftPFReq_hits::cpu.data 65769 # number of SoftPFReq hits
664 system.cpu.dcache.SoftPFReq_hits::total 65769 # number of SoftPFReq hits
665 system.cpu.dcache.demand_hits::cpu.data 19112160 # number of demand (read+write) hits
666 system.cpu.dcache.demand_hits::total 19112160 # number of demand (read+write) hits
667 system.cpu.dcache.overall_hits::cpu.data 19177929 # number of overall hits
668 system.cpu.dcache.overall_hits::total 19177929 # number of overall hits
669 system.cpu.dcache.ReadReq_misses::cpu.data 1799370 # number of ReadReq misses
670 system.cpu.dcache.ReadReq_misses::total 1799370 # number of ReadReq misses
671 system.cpu.dcache.WriteReq_misses::cpu.data 334097 # number of WriteReq misses
672 system.cpu.dcache.WriteReq_misses::total 334097 # number of WriteReq misses
673 system.cpu.dcache.SoftPFReq_misses::cpu.data 406460 # number of SoftPFReq misses
674 system.cpu.dcache.SoftPFReq_misses::total 406460 # number of SoftPFReq misses
675 system.cpu.dcache.demand_misses::cpu.data 2133467 # number of demand (read+write) misses
676 system.cpu.dcache.demand_misses::total 2133467 # number of demand (read+write) misses
677 system.cpu.dcache.overall_misses::cpu.data 2539927 # number of overall misses
678 system.cpu.dcache.overall_misses::total 2539927 # number of overall misses
679 system.cpu.dcache.ReadReq_miss_latency::cpu.data 26521555176 # number of ReadReq miss cycles
680 system.cpu.dcache.ReadReq_miss_latency::total 26521555176 # number of ReadReq miss cycles
681 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12869537398 # number of WriteReq miss cycles
682 system.cpu.dcache.WriteReq_miss_latency::total 12869537398 # number of WriteReq miss cycles
683 system.cpu.dcache.demand_miss_latency::cpu.data 39391092574 # number of demand (read+write) miss cycles
684 system.cpu.dcache.demand_miss_latency::total 39391092574 # number of demand (read+write) miss cycles
685 system.cpu.dcache.overall_miss_latency::cpu.data 39391092574 # number of overall miss cycles
686 system.cpu.dcache.overall_miss_latency::total 39391092574 # number of overall miss cycles
687 system.cpu.dcache.ReadReq_accesses::cpu.data 12825291 # number of ReadReq accesses(hits+misses)
688 system.cpu.dcache.ReadReq_accesses::total 12825291 # number of ReadReq accesses(hits+misses)
689 system.cpu.dcache.WriteReq_accesses::cpu.data 8420336 # number of WriteReq accesses(hits+misses)
690 system.cpu.dcache.WriteReq_accesses::total 8420336 # number of WriteReq accesses(hits+misses)
691 system.cpu.dcache.SoftPFReq_accesses::cpu.data 472229 # number of SoftPFReq accesses(hits+misses)
692 system.cpu.dcache.SoftPFReq_accesses::total 472229 # number of SoftPFReq accesses(hits+misses)
693 system.cpu.dcache.demand_accesses::cpu.data 21245627 # number of demand (read+write) accesses
694 system.cpu.dcache.demand_accesses::total 21245627 # number of demand (read+write) accesses
695 system.cpu.dcache.overall_accesses::cpu.data 21717856 # number of overall (read+write) accesses
696 system.cpu.dcache.overall_accesses::total 21717856 # number of overall (read+write) accesses
697 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140299 # miss rate for ReadReq accesses
698 system.cpu.dcache.ReadReq_miss_rate::total 0.140299 # miss rate for ReadReq accesses
699 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039677 # miss rate for WriteReq accesses
700 system.cpu.dcache.WriteReq_miss_rate::total 0.039677 # miss rate for WriteReq accesses
701 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860726 # miss rate for SoftPFReq accesses
702 system.cpu.dcache.SoftPFReq_miss_rate::total 0.860726 # miss rate for SoftPFReq accesses
703 system.cpu.dcache.demand_miss_rate::cpu.data 0.100419 # miss rate for demand accesses
704 system.cpu.dcache.demand_miss_rate::total 0.100419 # miss rate for demand accesses
705 system.cpu.dcache.overall_miss_rate::cpu.data 0.116951 # miss rate for overall accesses
706 system.cpu.dcache.overall_miss_rate::total 0.116951 # miss rate for overall accesses
707 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14739.356095 # average ReadReq miss latency
708 system.cpu.dcache.ReadReq_avg_miss_latency::total 14739.356095 # average ReadReq miss latency
709 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38520.362045 # average WriteReq miss latency
710 system.cpu.dcache.WriteReq_avg_miss_latency::total 38520.362045 # average WriteReq miss latency
711 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18463.417796 # average overall miss latency
712 system.cpu.dcache.demand_avg_miss_latency::total 18463.417796 # average overall miss latency
713 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15508.749887 # average overall miss latency
714 system.cpu.dcache.overall_avg_miss_latency::total 15508.749887 # average overall miss latency
715 system.cpu.dcache.blocked_cycles::no_mshrs 376355 # number of cycles access was blocked
716 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
717 system.cpu.dcache.blocked::no_mshrs 40236 # number of cycles access was blocked
718 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
719 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353688 # average number of cycles each access was blocked
720 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
721 system.cpu.dcache.fast_writes 0 # number of fast writes performed
722 system.cpu.dcache.cache_copies 0 # number of cache copies performed
723 system.cpu.dcache.writebacks::writebacks 1562436 # number of writebacks
724 system.cpu.dcache.writebacks::total 1562436 # number of writebacks
725 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 828680 # number of ReadReq MSHR hits
726 system.cpu.dcache.ReadReq_mshr_hits::total 828680 # number of ReadReq MSHR hits
727 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 43973 # number of WriteReq MSHR hits
728 system.cpu.dcache.WriteReq_mshr_hits::total 43973 # number of WriteReq MSHR hits
729 system.cpu.dcache.demand_mshr_hits::cpu.data 872653 # number of demand (read+write) MSHR hits
730 system.cpu.dcache.demand_mshr_hits::total 872653 # number of demand (read+write) MSHR hits
731 system.cpu.dcache.overall_mshr_hits::cpu.data 872653 # number of overall MSHR hits
732 system.cpu.dcache.overall_mshr_hits::total 872653 # number of overall MSHR hits
733 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970690 # number of ReadReq MSHR misses
734 system.cpu.dcache.ReadReq_mshr_misses::total 970690 # number of ReadReq MSHR misses
735 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290124 # number of WriteReq MSHR misses
736 system.cpu.dcache.WriteReq_mshr_misses::total 290124 # number of WriteReq MSHR misses
737 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403005 # number of SoftPFReq MSHR misses
738 system.cpu.dcache.SoftPFReq_mshr_misses::total 403005 # number of SoftPFReq MSHR misses
739 system.cpu.dcache.demand_mshr_misses::cpu.data 1260814 # number of demand (read+write) MSHR misses
740 system.cpu.dcache.demand_mshr_misses::total 1260814 # number of demand (read+write) MSHR misses
741 system.cpu.dcache.overall_mshr_misses::cpu.data 1663819 # number of overall MSHR misses
742 system.cpu.dcache.overall_mshr_misses::total 1663819 # number of overall MSHR misses
743 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12262338773 # number of ReadReq MSHR miss cycles
744 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12262338773 # number of ReadReq MSHR miss cycles
745 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11212126848 # number of WriteReq MSHR miss cycles
746 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11212126848 # number of WriteReq MSHR miss cycles
747 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584774002 # number of SoftPFReq MSHR miss cycles
748 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584774002 # number of SoftPFReq MSHR miss cycles
749 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23474465621 # number of demand (read+write) MSHR miss cycles
750 system.cpu.dcache.demand_mshr_miss_latency::total 23474465621 # number of demand (read+write) MSHR miss cycles
751 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29059239623 # number of overall MSHR miss cycles
752 system.cpu.dcache.overall_mshr_miss_latency::total 29059239623 # number of overall MSHR miss cycles
753 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97396245500 # number of ReadReq MSHR uncacheable cycles
754 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97396245500 # number of ReadReq MSHR uncacheable cycles
755 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2569003000 # number of WriteReq MSHR uncacheable cycles
756 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2569003000 # number of WriteReq MSHR uncacheable cycles
757 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99965248500 # number of overall MSHR uncacheable cycles
758 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99965248500 # number of overall MSHR uncacheable cycles
759 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075686 # mshr miss rate for ReadReq accesses
760 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075686 # mshr miss rate for ReadReq accesses
761 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses
762 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses
763 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853410 # mshr miss rate for SoftPFReq accesses
764 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853410 # mshr miss rate for SoftPFReq accesses
765 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059345 # mshr miss rate for demand accesses
766 system.cpu.dcache.demand_mshr_miss_rate::total 0.059345 # mshr miss rate for demand accesses
767 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076611 # mshr miss rate for overall accesses
768 system.cpu.dcache.overall_mshr_miss_rate::total 0.076611 # mshr miss rate for overall accesses
769 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12632.600287 # average ReadReq mshr miss latency
770 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12632.600287 # average ReadReq mshr miss latency
771 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38645.981884 # average WriteReq mshr miss latency
772 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38645.981884 # average WriteReq mshr miss latency
773 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13857.828072 # average SoftPFReq mshr miss latency
774 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13857.828072 # average SoftPFReq mshr miss latency
775 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18618.500128 # average overall mshr miss latency
776 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18618.500128 # average overall mshr miss latency
777 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17465.385131 # average overall mshr miss latency
778 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17465.385131 # average overall mshr miss latency
779 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
780 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
781 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
782 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
783 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
784 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
785 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
786 system.cpu.dtb_walker_cache.tags.replacements 76914 # number of replacements
787 system.cpu.dtb_walker_cache.tags.tagsinuse 15.799700 # Cycle average of tags in use
788 system.cpu.dtb_walker_cache.tags.total_refs 113377 # Total number of references to valid blocks.
789 system.cpu.dtb_walker_cache.tags.sampled_refs 76929 # Sample count of references to valid blocks.
790 system.cpu.dtb_walker_cache.tags.avg_refs 1.473788 # Average number of references to valid blocks.
791 system.cpu.dtb_walker_cache.tags.warmup_cycle 194539504500 # Cycle when the warmup percentage was hit.
792 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.799700 # Average occupied blocks per requestor
793 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.987481 # Average percentage of cache occupancy
794 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.987481 # Average percentage of cache occupancy
795 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
796 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
797 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
798 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
799 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
800 system.cpu.dtb_walker_cache.tags.tag_accesses 460761 # Number of tag accesses
801 system.cpu.dtb_walker_cache.tags.data_accesses 460761 # Number of data accesses
802 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113400 # number of ReadReq hits
803 system.cpu.dtb_walker_cache.ReadReq_hits::total 113400 # number of ReadReq hits
804 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113400 # number of demand (read+write) hits
805 system.cpu.dtb_walker_cache.demand_hits::total 113400 # number of demand (read+write) hits
806 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113400 # number of overall hits
807 system.cpu.dtb_walker_cache.overall_hits::total 113400 # number of overall hits
808 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77987 # number of ReadReq misses
809 system.cpu.dtb_walker_cache.ReadReq_misses::total 77987 # number of ReadReq misses
810 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77987 # number of demand (read+write) misses
811 system.cpu.dtb_walker_cache.demand_misses::total 77987 # number of demand (read+write) misses
812 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77987 # number of overall misses
813 system.cpu.dtb_walker_cache.overall_misses::total 77987 # number of overall misses
814 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 949066206 # number of ReadReq miss cycles
815 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 949066206 # number of ReadReq miss cycles
816 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 949066206 # number of demand (read+write) miss cycles
817 system.cpu.dtb_walker_cache.demand_miss_latency::total 949066206 # number of demand (read+write) miss cycles
818 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 949066206 # number of overall miss cycles
819 system.cpu.dtb_walker_cache.overall_miss_latency::total 949066206 # number of overall miss cycles
820 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191387 # number of ReadReq accesses(hits+misses)
821 system.cpu.dtb_walker_cache.ReadReq_accesses::total 191387 # number of ReadReq accesses(hits+misses)
822 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191387 # number of demand (read+write) accesses
823 system.cpu.dtb_walker_cache.demand_accesses::total 191387 # number of demand (read+write) accesses
824 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191387 # number of overall (read+write) accesses
825 system.cpu.dtb_walker_cache.overall_accesses::total 191387 # number of overall (read+write) accesses
826 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407483 # miss rate for ReadReq accesses
827 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407483 # miss rate for ReadReq accesses
828 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407483 # miss rate for demand accesses
829 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407483 # miss rate for demand accesses
830 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407483 # miss rate for overall accesses
831 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407483 # miss rate for overall accesses
832 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12169.543719 # average ReadReq miss latency
833 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12169.543719 # average ReadReq miss latency
834 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency
835 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12169.543719 # average overall miss latency
836 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency
837 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12169.543719 # average overall miss latency
838 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
839 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
840 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
841 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
842 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
843 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
844 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
845 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
846 system.cpu.dtb_walker_cache.writebacks::writebacks 21202 # number of writebacks
847 system.cpu.dtb_walker_cache.writebacks::total 21202 # number of writebacks
848 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77987 # number of ReadReq MSHR misses
849 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77987 # number of ReadReq MSHR misses
850 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77987 # number of demand (read+write) MSHR misses
851 system.cpu.dtb_walker_cache.demand_mshr_misses::total 77987 # number of demand (read+write) MSHR misses
852 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77987 # number of overall MSHR misses
853 system.cpu.dtb_walker_cache.overall_mshr_misses::total 77987 # number of overall MSHR misses
854 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 792970936 # number of ReadReq MSHR miss cycles
855 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 792970936 # number of ReadReq MSHR miss cycles
856 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 792970936 # number of demand (read+write) MSHR miss cycles
857 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 792970936 # number of demand (read+write) MSHR miss cycles
858 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 792970936 # number of overall MSHR miss cycles
859 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 792970936 # number of overall MSHR miss cycles
860 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for ReadReq accesses
861 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407483 # mshr miss rate for ReadReq accesses
862 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for demand accesses
863 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407483 # mshr miss rate for demand accesses
864 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for overall accesses
865 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407483 # mshr miss rate for overall accesses
866 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average ReadReq mshr miss latency
867 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10167.988716 # average ReadReq mshr miss latency
868 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency
869 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency
870 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency
871 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency
872 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
873 system.cpu.icache.tags.replacements 998047 # number of replacements
874 system.cpu.icache.tags.tagsinuse 509.614894 # Cycle average of tags in use
875 system.cpu.icache.tags.total_refs 8172291 # Total number of references to valid blocks.
876 system.cpu.icache.tags.sampled_refs 998559 # Sample count of references to valid blocks.
877 system.cpu.icache.tags.avg_refs 8.184084 # Average number of references to valid blocks.
878 system.cpu.icache.tags.warmup_cycle 147683889250 # Cycle when the warmup percentage was hit.
879 system.cpu.icache.tags.occ_blocks::cpu.inst 509.614894 # Average occupied blocks per requestor
880 system.cpu.icache.tags.occ_percent::cpu.inst 0.995342 # Average percentage of cache occupancy
881 system.cpu.icache.tags.occ_percent::total 0.995342 # Average percentage of cache occupancy
882 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
883 system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
884 system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
885 system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id
886 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
887 system.cpu.icache.tags.tag_accesses 10232340 # Number of tag accesses
888 system.cpu.icache.tags.data_accesses 10232340 # Number of data accesses
889 system.cpu.icache.ReadReq_hits::cpu.inst 8172291 # number of ReadReq hits
890 system.cpu.icache.ReadReq_hits::total 8172291 # number of ReadReq hits
891 system.cpu.icache.demand_hits::cpu.inst 8172291 # number of demand (read+write) hits
892 system.cpu.icache.demand_hits::total 8172291 # number of demand (read+write) hits
893 system.cpu.icache.overall_hits::cpu.inst 8172291 # number of overall hits
894 system.cpu.icache.overall_hits::total 8172291 # number of overall hits
895 system.cpu.icache.ReadReq_misses::cpu.inst 1061429 # number of ReadReq misses
896 system.cpu.icache.ReadReq_misses::total 1061429 # number of ReadReq misses
897 system.cpu.icache.demand_misses::cpu.inst 1061429 # number of demand (read+write) misses
898 system.cpu.icache.demand_misses::total 1061429 # number of demand (read+write) misses
899 system.cpu.icache.overall_misses::cpu.inst 1061429 # number of overall misses
900 system.cpu.icache.overall_misses::total 1061429 # number of overall misses
901 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14726887378 # number of ReadReq miss cycles
902 system.cpu.icache.ReadReq_miss_latency::total 14726887378 # number of ReadReq miss cycles
903 system.cpu.icache.demand_miss_latency::cpu.inst 14726887378 # number of demand (read+write) miss cycles
904 system.cpu.icache.demand_miss_latency::total 14726887378 # number of demand (read+write) miss cycles
905 system.cpu.icache.overall_miss_latency::cpu.inst 14726887378 # number of overall miss cycles
906 system.cpu.icache.overall_miss_latency::total 14726887378 # number of overall miss cycles
907 system.cpu.icache.ReadReq_accesses::cpu.inst 9233720 # number of ReadReq accesses(hits+misses)
908 system.cpu.icache.ReadReq_accesses::total 9233720 # number of ReadReq accesses(hits+misses)
909 system.cpu.icache.demand_accesses::cpu.inst 9233720 # number of demand (read+write) accesses
910 system.cpu.icache.demand_accesses::total 9233720 # number of demand (read+write) accesses
911 system.cpu.icache.overall_accesses::cpu.inst 9233720 # number of overall (read+write) accesses
912 system.cpu.icache.overall_accesses::total 9233720 # number of overall (read+write) accesses
913 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114951 # miss rate for ReadReq accesses
914 system.cpu.icache.ReadReq_miss_rate::total 0.114951 # miss rate for ReadReq accesses
915 system.cpu.icache.demand_miss_rate::cpu.inst 0.114951 # miss rate for demand accesses
916 system.cpu.icache.demand_miss_rate::total 0.114951 # miss rate for demand accesses
917 system.cpu.icache.overall_miss_rate::cpu.inst 0.114951 # miss rate for overall accesses
918 system.cpu.icache.overall_miss_rate::total 0.114951 # miss rate for overall accesses
919 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13874.585467 # average ReadReq miss latency
920 system.cpu.icache.ReadReq_avg_miss_latency::total 13874.585467 # average ReadReq miss latency
921 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency
922 system.cpu.icache.demand_avg_miss_latency::total 13874.585467 # average overall miss latency
923 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency
924 system.cpu.icache.overall_avg_miss_latency::total 13874.585467 # average overall miss latency
925 system.cpu.icache.blocked_cycles::no_mshrs 7528 # number of cycles access was blocked
926 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
927 system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked
928 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
929 system.cpu.icache.avg_blocked_cycles::no_mshrs 23.974522 # average number of cycles each access was blocked
930 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
931 system.cpu.icache.fast_writes 0 # number of fast writes performed
932 system.cpu.icache.cache_copies 0 # number of cache copies performed
933 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62809 # number of ReadReq MSHR hits
934 system.cpu.icache.ReadReq_mshr_hits::total 62809 # number of ReadReq MSHR hits
935 system.cpu.icache.demand_mshr_hits::cpu.inst 62809 # number of demand (read+write) MSHR hits
936 system.cpu.icache.demand_mshr_hits::total 62809 # number of demand (read+write) MSHR hits
937 system.cpu.icache.overall_mshr_hits::cpu.inst 62809 # number of overall MSHR hits
938 system.cpu.icache.overall_mshr_hits::total 62809 # number of overall MSHR hits
939 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998620 # number of ReadReq MSHR misses
940 system.cpu.icache.ReadReq_mshr_misses::total 998620 # number of ReadReq MSHR misses
941 system.cpu.icache.demand_mshr_misses::cpu.inst 998620 # number of demand (read+write) MSHR misses
942 system.cpu.icache.demand_mshr_misses::total 998620 # number of demand (read+write) MSHR misses
943 system.cpu.icache.overall_mshr_misses::cpu.inst 998620 # number of overall MSHR misses
944 system.cpu.icache.overall_mshr_misses::total 998620 # number of overall MSHR misses
945 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12093795712 # number of ReadReq MSHR miss cycles
946 system.cpu.icache.ReadReq_mshr_miss_latency::total 12093795712 # number of ReadReq MSHR miss cycles
947 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12093795712 # number of demand (read+write) MSHR miss cycles
948 system.cpu.icache.demand_mshr_miss_latency::total 12093795712 # number of demand (read+write) MSHR miss cycles
949 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12093795712 # number of overall MSHR miss cycles
950 system.cpu.icache.overall_mshr_miss_latency::total 12093795712 # number of overall MSHR miss cycles
951 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for ReadReq accesses
952 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108149 # mshr miss rate for ReadReq accesses
953 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for demand accesses
954 system.cpu.icache.demand_mshr_miss_rate::total 0.108149 # mshr miss rate for demand accesses
955 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for overall accesses
956 system.cpu.icache.overall_mshr_miss_rate::total 0.108149 # mshr miss rate for overall accesses
957 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.508213 # average ReadReq mshr miss latency
958 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.508213 # average ReadReq mshr miss latency
959 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency
960 system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency
961 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency
962 system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency
963 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
964 system.cpu.itb_walker_cache.tags.replacements 15839 # number of replacements
965 system.cpu.itb_walker_cache.tags.tagsinuse 6.015286 # Cycle average of tags in use
966 system.cpu.itb_walker_cache.tags.total_refs 25359 # Total number of references to valid blocks.
967 system.cpu.itb_walker_cache.tags.sampled_refs 15853 # Sample count of references to valid blocks.
968 system.cpu.itb_walker_cache.tags.avg_refs 1.599634 # Average number of references to valid blocks.
969 system.cpu.itb_walker_cache.tags.warmup_cycle 5101686667000 # Cycle when the warmup percentage was hit.
970 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.015286 # Average occupied blocks per requestor
971 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375955 # Average percentage of cache occupancy
972 system.cpu.itb_walker_cache.tags.occ_percent::total 0.375955 # Average percentage of cache occupancy
973 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
974 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
975 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
976 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
977 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
978 system.cpu.itb_walker_cache.tags.tag_accesses 101130 # Number of tag accesses
979 system.cpu.itb_walker_cache.tags.data_accesses 101130 # Number of data accesses
980 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25498 # number of ReadReq hits
981 system.cpu.itb_walker_cache.ReadReq_hits::total 25498 # number of ReadReq hits
982 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
983 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
984 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25500 # number of demand (read+write) hits
985 system.cpu.itb_walker_cache.demand_hits::total 25500 # number of demand (read+write) hits
986 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25500 # number of overall hits
987 system.cpu.itb_walker_cache.overall_hits::total 25500 # number of overall hits
988 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16710 # number of ReadReq misses
989 system.cpu.itb_walker_cache.ReadReq_misses::total 16710 # number of ReadReq misses
990 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16710 # number of demand (read+write) misses
991 system.cpu.itb_walker_cache.demand_misses::total 16710 # number of demand (read+write) misses
992 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16710 # number of overall misses
993 system.cpu.itb_walker_cache.overall_misses::total 16710 # number of overall misses
994 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 189443244 # number of ReadReq miss cycles
995 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 189443244 # number of ReadReq miss cycles
996 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 189443244 # number of demand (read+write) miss cycles
997 system.cpu.itb_walker_cache.demand_miss_latency::total 189443244 # number of demand (read+write) miss cycles
998 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 189443244 # number of overall miss cycles
999 system.cpu.itb_walker_cache.overall_miss_latency::total 189443244 # number of overall miss cycles
1000 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42208 # number of ReadReq accesses(hits+misses)
1001 system.cpu.itb_walker_cache.ReadReq_accesses::total 42208 # number of ReadReq accesses(hits+misses)
1002 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1003 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1004 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42210 # number of demand (read+write) accesses
1005 system.cpu.itb_walker_cache.demand_accesses::total 42210 # number of demand (read+write) accesses
1006 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42210 # number of overall (read+write) accesses
1007 system.cpu.itb_walker_cache.overall_accesses::total 42210 # number of overall (read+write) accesses
1008 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.395897 # miss rate for ReadReq accesses
1009 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.395897 # miss rate for ReadReq accesses
1010 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.395878 # miss rate for demand accesses
1011 system.cpu.itb_walker_cache.demand_miss_rate::total 0.395878 # miss rate for demand accesses
1012 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.395878 # miss rate for overall accesses
1013 system.cpu.itb_walker_cache.overall_miss_rate::total 0.395878 # miss rate for overall accesses
1014 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11337.118133 # average ReadReq miss latency
1015 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11337.118133 # average ReadReq miss latency
1016 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency
1017 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11337.118133 # average overall miss latency
1018 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency
1019 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11337.118133 # average overall miss latency
1020 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1021 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1022 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1023 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1024 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1025 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1026 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1027 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1028 system.cpu.itb_walker_cache.writebacks::writebacks 3245 # number of writebacks
1029 system.cpu.itb_walker_cache.writebacks::total 3245 # number of writebacks
1030 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16710 # number of ReadReq MSHR misses
1031 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16710 # number of ReadReq MSHR misses
1032 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16710 # number of demand (read+write) MSHR misses
1033 system.cpu.itb_walker_cache.demand_mshr_misses::total 16710 # number of demand (read+write) MSHR misses
1034 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16710 # number of overall MSHR misses
1035 system.cpu.itb_walker_cache.overall_mshr_misses::total 16710 # number of overall MSHR misses
1036 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 156005776 # number of ReadReq MSHR miss cycles
1037 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 156005776 # number of ReadReq MSHR miss cycles
1038 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 156005776 # number of demand (read+write) MSHR miss cycles
1039 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 156005776 # number of demand (read+write) MSHR miss cycles
1040 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 156005776 # number of overall MSHR miss cycles
1041 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 156005776 # number of overall MSHR miss cycles
1042 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.395897 # mshr miss rate for ReadReq accesses
1043 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.395897 # mshr miss rate for ReadReq accesses
1044 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for demand accesses
1045 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.395878 # mshr miss rate for demand accesses
1046 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for overall accesses
1047 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.395878 # mshr miss rate for overall accesses
1048 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average ReadReq mshr miss latency
1049 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9336.072771 # average ReadReq mshr miss latency
1050 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency
1051 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency
1052 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency
1053 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency
1054 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1055 system.cpu.l2cache.tags.replacements 112952 # number of replacements
1056 system.cpu.l2cache.tags.tagsinuse 64819.666116 # Cycle average of tags in use
1057 system.cpu.l2cache.tags.total_refs 3838789 # Total number of references to valid blocks.
1058 system.cpu.l2cache.tags.sampled_refs 176912 # Sample count of references to valid blocks.
1059 system.cpu.l2cache.tags.avg_refs 21.698862 # Average number of references to valid blocks.
1060 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1061 system.cpu.l2cache.tags.occ_blocks::writebacks 50506.549042 # Average occupied blocks per requestor
1062 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 19.197840 # Average occupied blocks per requestor
1063 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135379 # Average occupied blocks per requestor
1064 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3269.774951 # Average occupied blocks per requestor
1065 system.cpu.l2cache.tags.occ_blocks::cpu.data 11024.008903 # Average occupied blocks per requestor
1066 system.cpu.l2cache.tags.occ_percent::writebacks 0.770669 # Average percentage of cache occupancy
1067 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000293 # Average percentage of cache occupancy
1068 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1069 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049893 # Average percentage of cache occupancy
1070 system.cpu.l2cache.tags.occ_percent::cpu.data 0.168213 # Average percentage of cache occupancy
1071 system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy
1072 system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id
1073 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
1074 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 594 # Occupied blocks per task id
1075 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id
1076 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id
1077 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54407 # Occupied blocks per task id
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1080 system.cpu.l2cache.tags.data_accesses 35127054 # Number of data accesses
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1086 system.cpu.l2cache.Writeback_hits::writebacks 1586883 # number of Writeback hits
1087 system.cpu.l2cache.Writeback_hits::total 1586883 # number of Writeback hits
1088 system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
1089 system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
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1091 system.cpu.l2cache.ReadExReq_hits::total 154161 # number of ReadExReq hits
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1107 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1483 # number of UpgradeReq misses
1108 system.cpu.l2cache.UpgradeReq_misses::total 1483 # number of UpgradeReq misses
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1110 system.cpu.l2cache.ReadExReq_misses::total 133848 # number of ReadExReq misses
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1121 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6082250 # number of ReadReq miss cycles
1122 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 393250 # number of ReadReq miss cycles
1123 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1247981750 # number of ReadReq miss cycles
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1126 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17399310 # number of UpgradeReq miss cycles
1127 system.cpu.l2cache.UpgradeReq_miss_latency::total 17399310 # number of UpgradeReq miss cycles
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1129 system.cpu.l2cache.ReadExReq_miss_latency::total 9336961710 # number of ReadExReq miss cycles
1130 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6082250 # number of demand (read+write) miss cycles
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1135 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6082250 # number of overall miss cycles
1136 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 393250 # number of overall miss cycles
1137 system.cpu.l2cache.overall_miss_latency::cpu.inst 1247981750 # number of overall miss cycles
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1140 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69924 # number of ReadReq accesses(hits+misses)
1141 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13444 # number of ReadReq accesses(hits+misses)
1142 system.cpu.l2cache.ReadReq_accesses::cpu.inst 998513 # number of ReadReq accesses(hits+misses)
1143 system.cpu.l2cache.ReadReq_accesses::cpu.data 1373000 # number of ReadReq accesses(hits+misses)
1144 system.cpu.l2cache.ReadReq_accesses::total 2454881 # number of ReadReq accesses(hits+misses)
1145 system.cpu.l2cache.Writeback_accesses::writebacks 1586883 # number of Writeback accesses(hits+misses)
1146 system.cpu.l2cache.Writeback_accesses::total 1586883 # number of Writeback accesses(hits+misses)
1147 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1792 # number of UpgradeReq accesses(hits+misses)
1148 system.cpu.l2cache.UpgradeReq_accesses::total 1792 # number of UpgradeReq accesses(hits+misses)
1149 system.cpu.l2cache.ReadExReq_accesses::cpu.data 288009 # number of ReadExReq accesses(hits+misses)
1150 system.cpu.l2cache.ReadExReq_accesses::total 288009 # number of ReadExReq accesses(hits+misses)
1151 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69924 # number of demand (read+write) accesses
1152 system.cpu.l2cache.demand_accesses::cpu.itb.walker 13444 # number of demand (read+write) accesses
1153 system.cpu.l2cache.demand_accesses::cpu.inst 998513 # number of demand (read+write) accesses
1154 system.cpu.l2cache.demand_accesses::cpu.data 1661009 # number of demand (read+write) accesses
1155 system.cpu.l2cache.demand_accesses::total 2742890 # number of demand (read+write) accesses
1156 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69924 # number of overall (read+write) accesses
1157 system.cpu.l2cache.overall_accesses::cpu.itb.walker 13444 # number of overall (read+write) accesses
1158 system.cpu.l2cache.overall_accesses::cpu.inst 998513 # number of overall (read+write) accesses
1159 system.cpu.l2cache.overall_accesses::cpu.data 1661009 # number of overall (read+write) accesses
1160 system.cpu.l2cache.overall_accesses::total 2742890 # number of overall (read+write) accesses
1161 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000972 # miss rate for ReadReq accesses
1162 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000372 # miss rate for ReadReq accesses
1163 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016363 # miss rate for ReadReq accesses
1164 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026092 # miss rate for ReadReq accesses
1165 system.cpu.l2cache.ReadReq_miss_rate::total 0.021279 # miss rate for ReadReq accesses
1166 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827567 # miss rate for UpgradeReq accesses
1167 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827567 # miss rate for UpgradeReq accesses
1168 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464735 # miss rate for ReadExReq accesses
1169 system.cpu.l2cache.ReadExReq_miss_rate::total 0.464735 # miss rate for ReadExReq accesses
1170 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000972 # miss rate for demand accesses
1171 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000372 # miss rate for demand accesses
1172 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016363 # miss rate for demand accesses
1173 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102151 # miss rate for demand accesses
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1175 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000972 # miss rate for overall accesses
1176 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000372 # miss rate for overall accesses
1177 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016363 # miss rate for overall accesses
1178 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102151 # miss rate for overall accesses
1179 system.cpu.l2cache.overall_miss_rate::total 0.067843 # miss rate for overall accesses
1180 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89444.852941 # average ReadReq miss latency
1181 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78650 # average ReadReq miss latency
1182 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76380.546545 # average ReadReq miss latency
1183 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79093.642680 # average ReadReq miss latency
1184 system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.456630 # average ReadReq miss latency
1185 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11732.508429 # average UpgradeReq miss latency
1186 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11732.508429 # average UpgradeReq miss latency
1187 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69757.947149 # average ReadExReq miss latency
1188 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69757.947149 # average ReadExReq miss latency
1189 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89444.852941 # average overall miss latency
1190 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78650 # average overall miss latency
1191 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76380.546545 # average overall miss latency
1192 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71729.099262 # average overall miss latency
1193 system.cpu.l2cache.demand_avg_miss_latency::total 72144.174485 # average overall miss latency
1194 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89444.852941 # average overall miss latency
1195 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78650 # average overall miss latency
1196 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76380.546545 # average overall miss latency
1197 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71729.099262 # average overall miss latency
1198 system.cpu.l2cache.overall_avg_miss_latency::total 72144.174485 # average overall miss latency
1199 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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1201 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1202 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1203 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1204 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1205 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1206 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1207 system.cpu.l2cache.writebacks::writebacks 103187 # number of writebacks
1208 system.cpu.l2cache.writebacks::total 103187 # number of writebacks
1209 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
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1223 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1483 # number of UpgradeReq MSHR misses
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1243 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15771463 # number of UpgradeReq MSHR miss cycles
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1245 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656264290 # number of ReadExReq MSHR miss cycles
1246 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5240250 # number of demand (read+write) MSHR miss cycles
1247 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 330750 # number of demand (read+write) MSHR miss cycles
1248 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1042946750 # number of demand (read+write) MSHR miss cycles
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1251 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5240250 # number of overall MSHR miss cycles
1252 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 330750 # number of overall MSHR miss cycles
1253 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1042946750 # number of overall MSHR miss cycles
1254 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10045234289 # number of overall MSHR miss cycles
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1256 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89281194000 # number of ReadReq MSHR uncacheable cycles
1257 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89281194000 # number of ReadReq MSHR uncacheable cycles
1258 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401486500 # number of WriteReq MSHR uncacheable cycles
1259 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401486500 # number of WriteReq MSHR uncacheable cycles
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1261 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91682680500 # number of overall MSHR uncacheable cycles
1262 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for ReadReq accesses
1263 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for ReadReq accesses
1264 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for ReadReq accesses
1265 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026090 # mshr miss rate for ReadReq accesses
1266 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021277 # mshr miss rate for ReadReq accesses
1267 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827567 # mshr miss rate for UpgradeReq accesses
1268 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827567 # mshr miss rate for UpgradeReq accesses
1269 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464735 # mshr miss rate for ReadExReq accesses
1270 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464735 # mshr miss rate for ReadExReq accesses
1271 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for demand accesses
1272 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for demand accesses
1273 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for demand accesses
1274 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for demand accesses
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1276 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for overall accesses
1277 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for overall accesses
1278 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for overall accesses
1279 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for overall accesses
1280 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067841 # mshr miss rate for overall accesses
1281 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average ReadReq mshr miss latency
1282 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66150 # average ReadReq mshr miss latency
1283 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63839.551325 # average ReadReq mshr miss latency
1284 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66690.022863 # average ReadReq mshr miss latency
1285 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65811.911261 # average ReadReq mshr miss latency
1286 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.836817 # average UpgradeReq mshr miss latency
1287 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.836817 # average UpgradeReq mshr miss latency
1288 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57201.185599 # average ReadExReq mshr miss latency
1289 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57201.185599 # average ReadExReq mshr miss latency
1290 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency
1291 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency
1292 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency
1293 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency
1294 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency
1295 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency
1296 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency
1297 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency
1298 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency
1299 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency
1300 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1301 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1302 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1303 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1304 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1305 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1306 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1307 system.cpu.toL2Bus.trans_dist::ReadReq 3077249 # Transaction distribution
1308 system.cpu.toL2Bus.trans_dist::ReadResp 3076704 # Transaction distribution
1309 system.cpu.toL2Bus.trans_dist::WriteReq 13905 # Transaction distribution
1310 system.cpu.toL2Bus.trans_dist::WriteResp 13905 # Transaction distribution
1311 system.cpu.toL2Bus.trans_dist::Writeback 1586883 # Transaction distribution
1312 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution
1315 system.cpu.toL2Bus.trans_dist::ReadExReq 288016 # Transaction distribution
1316 system.cpu.toL2Bus.trans_dist::ReadExResp 288016 # Transaction distribution
1317 system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution
1318 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1997133 # Packet count per connected master and slave (bytes)
1319 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6136134 # Packet count per connected master and slave (bytes)
1320 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 33399 # Packet count per connected master and slave (bytes)
1321 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 169113 # Packet count per connected master and slave (bytes)
1322 system.cpu.toL2Bus.pkt_count::total 8335779 # Packet count per connected master and slave (bytes)
1323 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63904832 # Cumulative packet size per connected master and slave (bytes)
1324 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208116125 # Cumulative packet size per connected master and slave (bytes)
1325 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1068096 # Cumulative packet size per connected master and slave (bytes)
1326 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5832064 # Cumulative packet size per connected master and slave (bytes)
1327 system.cpu.toL2Bus.pkt_size::total 278921117 # Cumulative packet size per connected master and slave (bytes)
1328 system.cpu.toL2Bus.snoops 60473 # Total snoops (count)
1329 system.cpu.toL2Bus.snoop_fanout::samples 4391663 # Request fanout histogram
1330 system.cpu.toL2Bus.snoop_fanout::mean 3.010846 # Request fanout histogram
1331 system.cpu.toL2Bus.snoop_fanout::stdev 0.103577 # Request fanout histogram
1332 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1333 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1334 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1335 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1336 system.cpu.toL2Bus.snoop_fanout::3 4344032 98.92% 98.92% # Request fanout histogram
1337 system.cpu.toL2Bus.snoop_fanout::4 47631 1.08% 100.00% # Request fanout histogram
1338 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1339 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1340 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1341 system.cpu.toL2Bus.snoop_fanout::total 4391663 # Request fanout histogram
1342 system.cpu.toL2Bus.reqLayer0.occupancy 4077594873 # Layer occupancy (ticks)
1343 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1344 system.cpu.toL2Bus.snoopLayer0.occupancy 562500 # Layer occupancy (ticks)
1345 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1346 system.cpu.toL2Bus.respLayer0.occupancy 1502063776 # Layer occupancy (ticks)
1347 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1348 system.cpu.toL2Bus.respLayer1.occupancy 3145123125 # Layer occupancy (ticks)
1349 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1350 system.cpu.toL2Bus.respLayer2.occupancy 25073734 # Layer occupancy (ticks)
1351 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1352 system.cpu.toL2Bus.respLayer3.occupancy 117041135 # Layer occupancy (ticks)
1353 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1354 system.iobus.trans_dist::ReadReq 225706 # Transaction distribution
1355 system.iobus.trans_dist::ReadResp 225706 # Transaction distribution
1356 system.iobus.trans_dist::WriteReq 57738 # Transaction distribution
1357 system.iobus.trans_dist::WriteResp 11018 # Transaction distribution
1358 system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1359 system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
1360 system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
1361 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1362 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1363 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
1364 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1365 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1366 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1367 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1368 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::total 471626 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count::total 570174 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1386 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1387 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
1388 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1389 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1390 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1391 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::total 242096 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size::total 3276500 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.reqLayer0.occupancy 3915656 # Layer occupancy (ticks)
1410 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1411 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1412 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1413 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1414 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1415 system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
1416 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1417 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1418 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1419 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1420 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1421 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1422 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1423 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1424 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1426 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
1428 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1430 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1432 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1434 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1436 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1438 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1439 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1440 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1441 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1442 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1443 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1444 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1445 system.iobus.reqLayer19.occupancy 448351206 # Layer occupancy (ticks)
1446 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1447 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1448 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1449 system.iobus.respLayer0.occupancy 460608000 # Layer occupancy (ticks)
1450 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1451 system.iobus.respLayer1.occupancy 52362260 # Layer occupancy (ticks)
1452 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1453 system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
1454 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1455 system.iocache.tags.replacements 47576 # number of replacements
1456 system.iocache.tags.tagsinuse 0.091535 # Cycle average of tags in use
1457 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1458 system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks.
1459 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1460 system.iocache.tags.warmup_cycle 4992994629000 # Cycle when the warmup percentage was hit.
1461 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091535 # Average occupied blocks per requestor
1462 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005721 # Average percentage of cache occupancy
1463 system.iocache.tags.occ_percent::total 0.005721 # Average percentage of cache occupancy
1464 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1465 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1466 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1467 system.iocache.tags.tag_accesses 428679 # Number of tag accesses
1468 system.iocache.tags.data_accesses 428679 # Number of data accesses
1469 system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
1470 system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
1471 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1472 system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1473 system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses
1474 system.iocache.demand_misses::total 911 # number of demand (read+write) misses
1475 system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses
1476 system.iocache.overall_misses::total 911 # number of overall misses
1477 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147981947 # number of ReadReq miss cycles
1478 system.iocache.ReadReq_miss_latency::total 147981947 # number of ReadReq miss cycles
1479 system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12360245999 # number of WriteInvalidateReq miss cycles
1480 system.iocache.WriteInvalidateReq_miss_latency::total 12360245999 # number of WriteInvalidateReq miss cycles
1481 system.iocache.demand_miss_latency::pc.south_bridge.ide 147981947 # number of demand (read+write) miss cycles
1482 system.iocache.demand_miss_latency::total 147981947 # number of demand (read+write) miss cycles
1483 system.iocache.overall_miss_latency::pc.south_bridge.ide 147981947 # number of overall miss cycles
1484 system.iocache.overall_miss_latency::total 147981947 # number of overall miss cycles
1485 system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
1486 system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
1487 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1488 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1489 system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses
1490 system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses
1491 system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses
1492 system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses
1493 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1494 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1495 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1496 system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1497 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1498 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1499 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1500 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1501 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average ReadReq miss latency
1502 system.iocache.ReadReq_avg_miss_latency::total 162439.019759 # average ReadReq miss latency
1503 system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264560.059910 # average WriteInvalidateReq miss latency
1504 system.iocache.WriteInvalidateReq_avg_miss_latency::total 264560.059910 # average WriteInvalidateReq miss latency
1505 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency
1506 system.iocache.demand_avg_miss_latency::total 162439.019759 # average overall miss latency
1507 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency
1508 system.iocache.overall_avg_miss_latency::total 162439.019759 # average overall miss latency
1509 system.iocache.blocked_cycles::no_mshrs 70832 # number of cycles access was blocked
1510 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1511 system.iocache.blocked::no_mshrs 9173 # number of cycles access was blocked
1512 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1513 system.iocache.avg_blocked_cycles::no_mshrs 7.721792 # average number of cycles each access was blocked
1514 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1515 system.iocache.fast_writes 0 # number of fast writes performed
1516 system.iocache.cache_copies 0 # number of cache copies performed
1517 system.iocache.writebacks::writebacks 46667 # number of writebacks
1518 system.iocache.writebacks::total 46667 # number of writebacks
1519 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
1520 system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
1521 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1522 system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1523 system.iocache.demand_mshr_misses::pc.south_bridge.ide 911 # number of demand (read+write) MSHR misses
1524 system.iocache.demand_mshr_misses::total 911 # number of demand (read+write) MSHR misses
1525 system.iocache.overall_mshr_misses::pc.south_bridge.ide 911 # number of overall MSHR misses
1526 system.iocache.overall_mshr_misses::total 911 # number of overall MSHR misses
1527 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of ReadReq MSHR miss cycles
1528 system.iocache.ReadReq_mshr_miss_latency::total 100584447 # number of ReadReq MSHR miss cycles
1529 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9930786019 # number of WriteInvalidateReq MSHR miss cycles
1530 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9930786019 # number of WriteInvalidateReq MSHR miss cycles
1531 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of demand (read+write) MSHR miss cycles
1532 system.iocache.demand_mshr_miss_latency::total 100584447 # number of demand (read+write) MSHR miss cycles
1533 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of overall MSHR miss cycles
1534 system.iocache.overall_mshr_miss_latency::total 100584447 # number of overall MSHR miss cycles
1535 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1536 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1537 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1538 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1539 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1540 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1541 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1542 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1543 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average ReadReq mshr miss latency
1544 system.iocache.ReadReq_avg_mshr_miss_latency::total 110411.028540 # average ReadReq mshr miss latency
1545 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212559.632256 # average WriteInvalidateReq mshr miss latency
1546 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212559.632256 # average WriteInvalidateReq mshr miss latency
1547 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency
1548 system.iocache.demand_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency
1549 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency
1550 system.iocache.overall_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency
1551 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1552 system.membus.trans_dist::ReadReq 662583 # Transaction distribution
1553 system.membus.trans_dist::ReadResp 662574 # Transaction distribution
1554 system.membus.trans_dist::WriteReq 13905 # Transaction distribution
1555 system.membus.trans_dist::WriteResp 13905 # Transaction distribution
1556 system.membus.trans_dist::Writeback 149854 # Transaction distribution
1557 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1558 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1559 system.membus.trans_dist::UpgradeReq 2216 # Transaction distribution
1560 system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution
1561 system.membus.trans_dist::ReadExReq 133558 # Transaction distribution
1562 system.membus.trans_dist::ReadExResp 133558 # Transaction distribution
1563 system.membus.trans_dist::MessageReq 1643 # Transaction distribution
1564 system.membus.trans_dist::MessageResp 1643 # Transaction distribution
1565 system.membus.trans_dist::BadAddressError 9 # Transaction distribution
1566 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
1567 system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
1568 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471626 # Packet count per connected master and slave (bytes)
1569 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
1570 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478050 # Packet count per connected master and slave (bytes)
1571 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes)
1572 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724758 # Packet count per connected master and slave (bytes)
1573 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141461 # Packet count per connected master and slave (bytes)
1574 system.membus.pkt_count_system.iocache.mem_side::total 141461 # Packet count per connected master and slave (bytes)
1575 system.membus.pkt_count::total 1869505 # Packet count per connected master and slave (bytes)
1576 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
1577 system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1578 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242096 # Cumulative packet size per connected master and slave (bytes)
1579 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
1580 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18451136 # Cumulative packet size per connected master and slave (bytes)
1581 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20243357 # Cumulative packet size per connected master and slave (bytes)
1582 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1583 system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1584 system.membus.pkt_size::total 26255049 # Cumulative packet size per connected master and slave (bytes)
1585 system.membus.snoops 1599 # Total snoops (count)
1586 system.membus.snoop_fanout::samples 385491 # Request fanout histogram
1587 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1588 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1589 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1590 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1591 system.membus.snoop_fanout::1 385491 100.00% 100.00% # Request fanout histogram
1592 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1593 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1594 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1595 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1596 system.membus.snoop_fanout::total 385491 # Request fanout histogram
1597 system.membus.reqLayer0.occupancy 251614500 # Layer occupancy (ticks)
1598 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1599 system.membus.reqLayer1.occupancy 583372000 # Layer occupancy (ticks)
1600 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1601 system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
1602 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1603 system.membus.reqLayer3.occupancy 1995485500 # Layer occupancy (ticks)
1604 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1605 system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
1606 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1607 system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
1608 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1609 system.membus.respLayer2.occupancy 3161579497 # Layer occupancy (ticks)
1610 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
1611 system.membus.respLayer4.occupancy 54941740 # Layer occupancy (ticks)
1612 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1613 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1614 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1615 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1616 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1617 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1618 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1619 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1620 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1621 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1622 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1623 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1624 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1625 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1626 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1628 ---------- End Simulation Statistics ----------
projects / gem5.git / blob