2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.164643 # Number of seconds simulated
4 sim_ticks 5164643202500 # Number of ticks simulated
5 final_tick 5164643202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 258156 # Simulator instruction rate (inst/s)
8 host_tick_rate 1586008699 # Simulator tick rate (ticks/s)
9 host_mem_usage 390600 # Number of bytes of host memory used
10 host_seconds 3256.38 # Real time elapsed on the host
11 sim_insts 840653382 # Number of instructions simulated
12 system.physmem.bytes_read 15885120 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 1235904 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 12075328 # Number of bytes written to this memory
15 system.physmem.num_reads 248205 # Number of read requests responded to by this memory
16 system.physmem.num_writes 188677 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 3075744 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 239301 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_write 2338076 # Write bandwidth from this memory (bytes/s)
21 system.physmem.bw_total 5413820 # Total bandwidth to/from this memory (bytes/s)
22 system.l2c.replacements 166524 # number of replacements
23 system.l2c.tagsinuse 37860.019471 # Cycle average of tags in use
24 system.l2c.total_refs 3791499 # Total number of references to valid blocks.
25 system.l2c.sampled_refs 201257 # Sample count of references to valid blocks.
26 system.l2c.avg_refs 18.839091 # Average number of references to valid blocks.
27 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
28 system.l2c.occ_blocks::0 11072.402172 # Average occupied blocks per context
29 system.l2c.occ_blocks::1 26787.617299 # Average occupied blocks per context
30 system.l2c.occ_percent::0 0.168951 # Average percentage of cache occupancy
31 system.l2c.occ_percent::1 0.408747 # Average percentage of cache occupancy
32 system.l2c.ReadReq_hits::0 2329446 # number of ReadReq hits
33 system.l2c.ReadReq_hits::1 146092 # number of ReadReq hits
34 system.l2c.ReadReq_hits::total 2475538 # number of ReadReq hits
35 system.l2c.Writeback_hits::0 1599025 # number of Writeback hits
36 system.l2c.Writeback_hits::total 1599025 # number of Writeback hits
37 system.l2c.UpgradeReq_hits::0 316 # number of UpgradeReq hits
38 system.l2c.UpgradeReq_hits::total 316 # number of UpgradeReq hits
39 system.l2c.ReadExReq_hits::0 151571 # number of ReadExReq hits
40 system.l2c.ReadExReq_hits::total 151571 # number of ReadExReq hits
41 system.l2c.demand_hits::0 2481017 # number of demand (read+write) hits
42 system.l2c.demand_hits::1 146092 # number of demand (read+write) hits
43 system.l2c.demand_hits::total 2627109 # number of demand (read+write) hits
44 system.l2c.overall_hits::0 2481017 # number of overall hits
45 system.l2c.overall_hits::1 146092 # number of overall hits
46 system.l2c.overall_hits::total 2627109 # number of overall hits
47 system.l2c.ReadReq_misses::0 64214 # number of ReadReq misses
48 system.l2c.ReadReq_misses::1 107 # number of ReadReq misses
49 system.l2c.ReadReq_misses::total 64321 # number of ReadReq misses
50 system.l2c.UpgradeReq_misses::0 5085 # number of UpgradeReq misses
51 system.l2c.UpgradeReq_misses::total 5085 # number of UpgradeReq misses
52 system.l2c.ReadExReq_misses::0 141328 # number of ReadExReq misses
53 system.l2c.ReadExReq_misses::total 141328 # number of ReadExReq misses
54 system.l2c.demand_misses::0 205542 # number of demand (read+write) misses
55 system.l2c.demand_misses::1 107 # number of demand (read+write) misses
56 system.l2c.demand_misses::total 205649 # number of demand (read+write) misses
57 system.l2c.overall_misses::0 205542 # number of overall misses
58 system.l2c.overall_misses::1 107 # number of overall misses
59 system.l2c.overall_misses::total 205649 # number of overall misses
60 system.l2c.ReadReq_miss_latency 3375006500 # number of ReadReq miss cycles
61 system.l2c.UpgradeReq_miss_latency 39785500 # number of UpgradeReq miss cycles
62 system.l2c.ReadExReq_miss_latency 7360156500 # number of ReadExReq miss cycles
63 system.l2c.demand_miss_latency 10735163000 # number of demand (read+write) miss cycles
64 system.l2c.overall_miss_latency 10735163000 # number of overall miss cycles
65 system.l2c.ReadReq_accesses::0 2393660 # number of ReadReq accesses(hits+misses)
66 system.l2c.ReadReq_accesses::1 146199 # number of ReadReq accesses(hits+misses)
67 system.l2c.ReadReq_accesses::total 2539859 # number of ReadReq accesses(hits+misses)
68 system.l2c.Writeback_accesses::0 1599025 # number of Writeback accesses(hits+misses)
69 system.l2c.Writeback_accesses::total 1599025 # number of Writeback accesses(hits+misses)
70 system.l2c.UpgradeReq_accesses::0 5401 # number of UpgradeReq accesses(hits+misses)
71 system.l2c.UpgradeReq_accesses::total 5401 # number of UpgradeReq accesses(hits+misses)
72 system.l2c.ReadExReq_accesses::0 292899 # number of ReadExReq accesses(hits+misses)
73 system.l2c.ReadExReq_accesses::total 292899 # number of ReadExReq accesses(hits+misses)
74 system.l2c.demand_accesses::0 2686559 # number of demand (read+write) accesses
75 system.l2c.demand_accesses::1 146199 # number of demand (read+write) accesses
76 system.l2c.demand_accesses::total 2832758 # number of demand (read+write) accesses
77 system.l2c.overall_accesses::0 2686559 # number of overall (read+write) accesses
78 system.l2c.overall_accesses::1 146199 # number of overall (read+write) accesses
79 system.l2c.overall_accesses::total 2832758 # number of overall (read+write) accesses
80 system.l2c.ReadReq_miss_rate::0 0.026827 # miss rate for ReadReq accesses
81 system.l2c.ReadReq_miss_rate::1 0.000732 # miss rate for ReadReq accesses
82 system.l2c.ReadReq_miss_rate::total 0.027559 # miss rate for ReadReq accesses
83 system.l2c.UpgradeReq_miss_rate::0 0.941492 # miss rate for UpgradeReq accesses
84 system.l2c.ReadExReq_miss_rate::0 0.482514 # miss rate for ReadExReq accesses
85 system.l2c.demand_miss_rate::0 0.076508 # miss rate for demand accesses
86 system.l2c.demand_miss_rate::1 0.000732 # miss rate for demand accesses
87 system.l2c.demand_miss_rate::total 0.077239 # miss rate for demand accesses
88 system.l2c.overall_miss_rate::0 0.076508 # miss rate for overall accesses
89 system.l2c.overall_miss_rate::1 0.000732 # miss rate for overall accesses
90 system.l2c.overall_miss_rate::total 0.077239 # miss rate for overall accesses
91 system.l2c.ReadReq_avg_miss_latency::0 52558.733298 # average ReadReq miss latency
92 system.l2c.ReadReq_avg_miss_latency::1 31542116.822430 # average ReadReq miss latency
93 system.l2c.ReadReq_avg_miss_latency::total 31594675.555728 # average ReadReq miss latency
94 system.l2c.UpgradeReq_avg_miss_latency::0 7824.090462 # average UpgradeReq miss latency
95 system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
96 system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
97 system.l2c.ReadExReq_avg_miss_latency::0 52078.544238 # average ReadExReq miss latency
98 system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
99 system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
100 system.l2c.demand_avg_miss_latency::0 52228.561559 # average overall miss latency
101 system.l2c.demand_avg_miss_latency::1 100328626.168224 # average overall miss latency
102 system.l2c.demand_avg_miss_latency::total 100380854.729784 # average overall miss latency
103 system.l2c.overall_avg_miss_latency::0 52228.561559 # average overall miss latency
104 system.l2c.overall_avg_miss_latency::1 100328626.168224 # average overall miss latency
105 system.l2c.overall_avg_miss_latency::total 100380854.729784 # average overall miss latency
106 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
107 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
108 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
109 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
110 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
111 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
112 system.l2c.fast_writes 0 # number of fast writes performed
113 system.l2c.cache_copies 0 # number of cache copies performed
114 system.l2c.writebacks 142010 # number of writebacks
115 system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
116 system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits
117 system.l2c.overall_mshr_hits 2 # number of overall MSHR hits
118 system.l2c.ReadReq_mshr_misses 64319 # number of ReadReq MSHR misses
119 system.l2c.UpgradeReq_mshr_misses 5085 # number of UpgradeReq MSHR misses
120 system.l2c.ReadExReq_mshr_misses 141328 # number of ReadExReq MSHR misses
121 system.l2c.demand_mshr_misses 205647 # number of demand (read+write) MSHR misses
122 system.l2c.overall_mshr_misses 205647 # number of overall MSHR misses
123 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
124 system.l2c.ReadReq_mshr_miss_latency 2589128000 # number of ReadReq MSHR miss cycles
125 system.l2c.UpgradeReq_mshr_miss_latency 203766500 # number of UpgradeReq MSHR miss cycles
126 system.l2c.ReadExReq_mshr_miss_latency 5654353000 # number of ReadExReq MSHR miss cycles
127 system.l2c.demand_mshr_miss_latency 8243481000 # number of demand (read+write) MSHR miss cycles
128 system.l2c.overall_mshr_miss_latency 8243481000 # number of overall MSHR miss cycles
129 system.l2c.ReadReq_mshr_uncacheable_latency 59975261500 # number of ReadReq MSHR uncacheable cycles
130 system.l2c.WriteReq_mshr_uncacheable_latency 1228545000 # number of WriteReq MSHR uncacheable cycles
131 system.l2c.overall_mshr_uncacheable_latency 61203806500 # number of overall MSHR uncacheable cycles
132 system.l2c.ReadReq_mshr_miss_rate::0 0.026871 # mshr miss rate for ReadReq accesses
133 system.l2c.ReadReq_mshr_miss_rate::1 0.439941 # mshr miss rate for ReadReq accesses
134 system.l2c.ReadReq_mshr_miss_rate::total 0.466812 # mshr miss rate for ReadReq accesses
135 system.l2c.UpgradeReq_mshr_miss_rate::0 0.941492 # mshr miss rate for UpgradeReq accesses
136 system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
137 system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
138 system.l2c.ReadExReq_mshr_miss_rate::0 0.482514 # mshr miss rate for ReadExReq accesses
139 system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
140 system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
141 system.l2c.demand_mshr_miss_rate::0 0.076547 # mshr miss rate for demand accesses
142 system.l2c.demand_mshr_miss_rate::1 1.406624 # mshr miss rate for demand accesses
143 system.l2c.demand_mshr_miss_rate::total 1.483170 # mshr miss rate for demand accesses
144 system.l2c.overall_mshr_miss_rate::0 0.076547 # mshr miss rate for overall accesses
145 system.l2c.overall_mshr_miss_rate::1 1.406624 # mshr miss rate for overall accesses
146 system.l2c.overall_mshr_miss_rate::total 1.483170 # mshr miss rate for overall accesses
147 system.l2c.ReadReq_avg_mshr_miss_latency 40254.481568 # average ReadReq mshr miss latency
148 system.l2c.UpgradeReq_avg_mshr_miss_latency 40072.074730 # average UpgradeReq mshr miss latency
149 system.l2c.ReadExReq_avg_mshr_miss_latency 40008.724386 # average ReadExReq mshr miss latency
150 system.l2c.demand_avg_mshr_miss_latency 40085.588411 # average overall mshr miss latency
151 system.l2c.overall_avg_mshr_miss_latency 40085.588411 # average overall mshr miss latency
152 system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
153 system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
154 system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
155 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
156 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
157 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
158 system.iocache.replacements 47574 # number of replacements
159 system.iocache.tagsinuse 0.187855 # Cycle average of tags in use
160 system.iocache.total_refs 0 # Total number of references to valid blocks.
161 system.iocache.sampled_refs 47590 # Sample count of references to valid blocks.
162 system.iocache.avg_refs 0 # Average number of references to valid blocks.
163 system.iocache.warmup_cycle 4996389374000 # Cycle when the warmup percentage was hit.
164 system.iocache.occ_blocks::1 0.187855 # Average occupied blocks per context
165 system.iocache.occ_percent::1 0.011741 # Average percentage of cache occupancy
166 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
167 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
168 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
169 system.iocache.overall_hits::0 0 # number of overall hits
170 system.iocache.overall_hits::1 0 # number of overall hits
171 system.iocache.overall_hits::total 0 # number of overall hits
172 system.iocache.ReadReq_misses::1 909 # number of ReadReq misses
173 system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
174 system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
175 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
176 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
177 system.iocache.demand_misses::1 47629 # number of demand (read+write) misses
178 system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
179 system.iocache.overall_misses::0 0 # number of overall misses
180 system.iocache.overall_misses::1 47629 # number of overall misses
181 system.iocache.overall_misses::total 47629 # number of overall misses
182 system.iocache.ReadReq_miss_latency 113959932 # number of ReadReq miss cycles
183 system.iocache.WriteReq_miss_latency 6369072160 # number of WriteReq miss cycles
184 system.iocache.demand_miss_latency 6483032092 # number of demand (read+write) miss cycles
185 system.iocache.overall_miss_latency 6483032092 # number of overall miss cycles
186 system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses)
187 system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
188 system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
189 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
190 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
191 system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses
192 system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
193 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
194 system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses
195 system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
196 system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
197 system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
198 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
199 system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
200 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
201 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
202 system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
203 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
204 system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
205 system.iocache.ReadReq_avg_miss_latency::1 125368.462046 # average ReadReq miss latency
206 system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
207 system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
208 system.iocache.WriteReq_avg_miss_latency::1 136324.318493 # average WriteReq miss latency
209 system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
210 system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
211 system.iocache.demand_avg_miss_latency::1 136115.225850 # average overall miss latency
212 system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
213 system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
214 system.iocache.overall_avg_miss_latency::1 136115.225850 # average overall miss latency
215 system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
216 system.iocache.blocked_cycles::no_mshrs 68773500 # number of cycles access was blocked
217 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
218 system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked
219 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
220 system.iocache.avg_blocked_cycles::no_mshrs 6107.770870 # average number of cycles each access was blocked
221 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
222 system.iocache.fast_writes 0 # number of fast writes performed
223 system.iocache.cache_copies 0 # number of cache copies performed
224 system.iocache.writebacks 46667 # number of writebacks
225 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
226 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
227 system.iocache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
228 system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses
229 system.iocache.demand_mshr_misses 47629 # number of demand (read+write) MSHR misses
230 system.iocache.overall_mshr_misses 47629 # number of overall MSHR misses
231 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
232 system.iocache.ReadReq_mshr_miss_latency 66668982 # number of ReadReq MSHR miss cycles
233 system.iocache.WriteReq_mshr_miss_latency 3939322842 # number of WriteReq MSHR miss cycles
234 system.iocache.demand_mshr_miss_latency 4005991824 # number of demand (read+write) MSHR miss cycles
235 system.iocache.overall_mshr_miss_latency 4005991824 # number of overall MSHR miss cycles
236 system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
237 system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
238 system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
239 system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
240 system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
241 system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
242 system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
243 system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
244 system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
245 system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
246 system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
247 system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
248 system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
249 system.iocache.ReadReq_avg_mshr_miss_latency 73343.214521 # average ReadReq mshr miss latency
250 system.iocache.WriteReq_avg_mshr_miss_latency 84317.697817 # average WriteReq mshr miss latency
251 system.iocache.demand_avg_mshr_miss_latency 84108.249680 # average overall mshr miss latency
252 system.iocache.overall_avg_mshr_miss_latency 84108.249680 # average overall mshr miss latency
253 system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
254 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
255 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
256 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
257 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
258 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
259 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
260 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
261 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
262 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
263 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
264 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
265 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
266 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
267 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
268 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
269 system.cpu.numCycles 462648122 # number of cpu cycles simulated
270 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
271 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
272 system.cpu.BPredUnit.lookups 91002231 # Number of BP lookups
273 system.cpu.BPredUnit.condPredicted 91002231 # Number of conditional branches predicted
274 system.cpu.BPredUnit.condIncorrect 1246819 # Number of conditional branches incorrect
275 system.cpu.BPredUnit.BTBLookups 89740071 # Number of BTB lookups
276 system.cpu.BPredUnit.BTBHits 83586488 # Number of BTB hits
277 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
278 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
279 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
280 system.cpu.fetch.icacheStallCycles 29047716 # Number of cycles fetch is stalled on an Icache miss
281 system.cpu.fetch.Insts 449719579 # Number of instructions fetch has processed
282 system.cpu.fetch.Branches 91002231 # Number of branches that fetch encountered
283 system.cpu.fetch.predictedBranches 83586488 # Number of branches that fetch has predicted taken
284 system.cpu.fetch.Cycles 171232175 # Number of cycles fetch has run and was not squashing or blocked
285 system.cpu.fetch.SquashCycles 5868826 # Number of cycles fetch has spent squashing
286 system.cpu.fetch.TlbCycles 136581 # Number of cycles fetch has spent waiting for tlb
287 system.cpu.fetch.BlockedCycles 101975708 # Number of cycles fetch has spent blocked
288 system.cpu.fetch.MiscStallCycles 37095 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
289 system.cpu.fetch.PendingTrapStallCycles 37068 # Number of stall cycles due to pending traps
290 system.cpu.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR
291 system.cpu.fetch.CacheLines 9677008 # Number of cache lines fetched
292 system.cpu.fetch.IcacheSquashes 518282 # Number of outstanding Icache misses that were squashed
293 system.cpu.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed
294 system.cpu.fetch.rateDist::samples 307050159 # Number of instructions fetched each cycle (Total)
295 system.cpu.fetch.rateDist::mean 2.882718 # Number of instructions fetched each cycle (Total)
296 system.cpu.fetch.rateDist::stdev 3.377693 # Number of instructions fetched each cycle (Total)
297 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
298 system.cpu.fetch.rateDist::0 136328655 44.40% 44.40% # Number of instructions fetched each cycle (Total)
299 system.cpu.fetch.rateDist::1 1837704 0.60% 45.00% # Number of instructions fetched each cycle (Total)
300 system.cpu.fetch.rateDist::2 72797609 23.71% 68.71% # Number of instructions fetched each cycle (Total)
301 system.cpu.fetch.rateDist::3 1414382 0.46% 69.17% # Number of instructions fetched each cycle (Total)
302 system.cpu.fetch.rateDist::4 1803500 0.59% 69.75% # Number of instructions fetched each cycle (Total)
303 system.cpu.fetch.rateDist::5 3975077 1.29% 71.05% # Number of instructions fetched each cycle (Total)
304 system.cpu.fetch.rateDist::6 1554877 0.51% 71.56% # Number of instructions fetched each cycle (Total)
305 system.cpu.fetch.rateDist::7 1662423 0.54% 72.10% # Number of instructions fetched each cycle (Total)
306 system.cpu.fetch.rateDist::8 85675932 27.90% 100.00% # Number of instructions fetched each cycle (Total)
307 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
308 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
309 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
310 system.cpu.fetch.rateDist::total 307050159 # Number of instructions fetched each cycle (Total)
311 system.cpu.fetch.branchRate 0.196699 # Number of branch fetches per cycle
312 system.cpu.fetch.rate 0.972055 # Number of inst fetches per cycle
313 system.cpu.decode.IdleCycles 34173588 # Number of cycles decode is idle
314 system.cpu.decode.BlockedCycles 98204152 # Number of cycles decode is blocked
315 system.cpu.decode.RunCycles 165547565 # Number of cycles decode is running
316 system.cpu.decode.UnblockCycles 4541296 # Number of cycles decode is unblocking
317 system.cpu.decode.SquashCycles 4583558 # Number of cycles decode is squashing
318 system.cpu.decode.DecodedInsts 881331819 # Number of instructions handled by decode
319 system.cpu.decode.SquashedInsts 622 # Number of squashed instructions handled by decode
320 system.cpu.rename.SquashCycles 4583558 # Number of cycles rename is squashing
321 system.cpu.rename.IdleCycles 38558977 # Number of cycles rename is idle
322 system.cpu.rename.BlockCycles 67835236 # Number of cycles rename is blocking
323 system.cpu.rename.serializeStallCycles 11414000 # count of cycles rename stalled for serializing inst
324 system.cpu.rename.RunCycles 165163218 # Number of cycles rename is running
325 system.cpu.rename.UnblockCycles 19495170 # Number of cycles rename is unblocking
326 system.cpu.rename.RenamedInsts 877018517 # Number of instructions processed by rename
327 system.cpu.rename.ROBFullEvents 10722 # Number of times rename has blocked due to ROB full
328 system.cpu.rename.IQFullEvents 12485969 # Number of times rename has blocked due to IQ full
329 system.cpu.rename.LSQFullEvents 3867736 # Number of times rename has blocked due to LSQ full
330 system.cpu.rename.RenamedOperands 878675009 # Number of destination operands rename has renamed
331 system.cpu.rename.RenameLookups 1719931818 # Number of register rename lookups that rename has made
332 system.cpu.rename.int_rename_lookups 1719931354 # Number of integer rename lookups
333 system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups
334 system.cpu.rename.CommittedMaps 843258778 # Number of HB maps that are committed
335 system.cpu.rename.UndoneMaps 35416224 # Number of HB maps that are undone due to squashing
336 system.cpu.rename.serializingInsts 488329 # count of serializing insts renamed
337 system.cpu.rename.tempSerializingInsts 492601 # count of temporary serializing insts renamed
338 system.cpu.rename.skidInsts 46069220 # count of insts added to the skid buffer
339 system.cpu.memDep0.insertedLoads 19448734 # Number of loads inserted to the mem dependence unit.
340 system.cpu.memDep0.insertedStores 10510676 # Number of stores inserted to the mem dependence unit.
341 system.cpu.memDep0.conflictingLoads 1191191 # Number of conflicting loads.
342 system.cpu.memDep0.conflictingStores 913743 # Number of conflicting stores.
343 system.cpu.iq.iqInstsAdded 869530177 # Number of instructions added to the IQ (excludes non-spec)
344 system.cpu.iq.iqNonSpecInstsAdded 1725186 # Number of non-speculative instructions added to the IQ
345 system.cpu.iq.iqInstsIssued 866447166 # Number of instructions issued
346 system.cpu.iq.iqSquashedInstsIssued 122007 # Number of squashed instructions issued
347 system.cpu.iq.iqSquashedInstsExamined 29731249 # Number of squashed instructions iterated over during squash; mainly for profiling
348 system.cpu.iq.iqSquashedOperandsExamined 42741048 # Number of squashed operands that are examined and possibly removed from graph
349 system.cpu.iq.iqSquashedNonSpecRemoved 205599 # Number of squashed non-spec instructions that were removed
350 system.cpu.iq.issued_per_cycle::samples 307050159 # Number of insts issued each cycle
351 system.cpu.iq.issued_per_cycle::mean 2.821842 # Number of insts issued each cycle
352 system.cpu.iq.issued_per_cycle::stdev 2.403845 # Number of insts issued each cycle
353 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
354 system.cpu.iq.issued_per_cycle::0 100227598 32.64% 32.64% # Number of insts issued each cycle
355 system.cpu.iq.issued_per_cycle::1 25342786 8.25% 40.90% # Number of insts issued each cycle
356 system.cpu.iq.issued_per_cycle::2 13946244 4.54% 45.44% # Number of insts issued each cycle
357 system.cpu.iq.issued_per_cycle::3 9645579 3.14% 48.58% # Number of insts issued each cycle
358 system.cpu.iq.issued_per_cycle::4 79515480 25.90% 74.48% # Number of insts issued each cycle
359 system.cpu.iq.issued_per_cycle::5 4843126 1.58% 76.05% # Number of insts issued each cycle
360 system.cpu.iq.issued_per_cycle::6 72836741 23.72% 99.77% # Number of insts issued each cycle
361 system.cpu.iq.issued_per_cycle::7 563681 0.18% 99.96% # Number of insts issued each cycle
362 system.cpu.iq.issued_per_cycle::8 128924 0.04% 100.00% # Number of insts issued each cycle
363 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
364 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
365 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
366 system.cpu.iq.issued_per_cycle::total 307050159 # Number of insts issued each cycle
367 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
368 system.cpu.iq.fu_full::IntAlu 189288 8.89% 8.89% # attempts to use FU when none available
369 system.cpu.iq.fu_full::IntMult 0 0.00% 8.89% # attempts to use FU when none available
370 system.cpu.iq.fu_full::IntDiv 0 0.00% 8.89% # attempts to use FU when none available
371 system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.89% # attempts to use FU when none available
372 system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.89% # attempts to use FU when none available
373 system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.89% # attempts to use FU when none available
374 system.cpu.iq.fu_full::FloatMult 0 0.00% 8.89% # attempts to use FU when none available
375 system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.89% # attempts to use FU when none available
376 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.89% # attempts to use FU when none available
377 system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.89% # attempts to use FU when none available
378 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.89% # attempts to use FU when none available
379 system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.89% # attempts to use FU when none available
380 system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.89% # attempts to use FU when none available
381 system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.89% # attempts to use FU when none available
382 system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.89% # attempts to use FU when none available
383 system.cpu.iq.fu_full::SimdMult 0 0.00% 8.89% # attempts to use FU when none available
384 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.89% # attempts to use FU when none available
385 system.cpu.iq.fu_full::SimdShift 0 0.00% 8.89% # attempts to use FU when none available
386 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.89% # attempts to use FU when none available
387 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.89% # attempts to use FU when none available
388 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.89% # attempts to use FU when none available
389 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.89% # attempts to use FU when none available
390 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.89% # attempts to use FU when none available
391 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.89% # attempts to use FU when none available
392 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.89% # attempts to use FU when none available
393 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.89% # attempts to use FU when none available
394 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.89% # attempts to use FU when none available
395 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.89% # attempts to use FU when none available
396 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.89% # attempts to use FU when none available
397 system.cpu.iq.fu_full::MemRead 1772779 83.25% 92.14% # attempts to use FU when none available
398 system.cpu.iq.fu_full::MemWrite 167484 7.86% 100.00% # attempts to use FU when none available
399 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
400 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
401 system.cpu.iq.FU_type_0::No_OpClass 305473 0.04% 0.04% # Type of FU issued
402 system.cpu.iq.FU_type_0::IntAlu 831218521 95.93% 95.97% # Type of FU issued
403 system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued
404 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued
405 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued
406 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued
407 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued
408 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued
409 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued
410 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued
411 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued
412 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued
413 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued
414 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued
415 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued
416 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued
417 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued
418 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued
419 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued
420 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued
421 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued
422 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued
423 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued
424 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued
425 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued
426 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued
427 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued
428 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued
429 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued
430 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued
431 system.cpu.iq.FU_type_0::MemRead 25430215 2.93% 98.90% # Type of FU issued
432 system.cpu.iq.FU_type_0::MemWrite 9492957 1.10% 100.00% # Type of FU issued
433 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
434 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
435 system.cpu.iq.FU_type_0::total 866447166 # Type of FU issued
436 system.cpu.iq.rate 1.872799 # Inst issue rate
437 system.cpu.iq.fu_busy_cnt 2129551 # FU busy when requested
438 system.cpu.iq.fu_busy_rate 0.002458 # FU busy rate (busy events/executed inst)
439 system.cpu.iq.int_inst_queue_reads 2042346945 # Number of integer instruction queue reads
440 system.cpu.iq.int_inst_queue_writes 900997029 # Number of integer instruction queue writes
441 system.cpu.iq.int_inst_queue_wakeup_accesses 855808882 # Number of integer instruction queue wakeup accesses
442 system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads
443 system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes
444 system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses
445 system.cpu.iq.int_alu_accesses 868271157 # Number of integer alu accesses
446 system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses
447 system.cpu.iew.lsq.thread0.forwLoads 1634079 # Number of loads that had data forwarded from stores
448 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
449 system.cpu.iew.lsq.thread0.squashedLoads 4122999 # Number of loads squashed
450 system.cpu.iew.lsq.thread0.ignoredResponses 16974 # Number of memory responses ignored because the instruction is squashed
451 system.cpu.iew.lsq.thread0.memOrderViolation 11449 # Number of memory ordering violations
452 system.cpu.iew.lsq.thread0.squashedStores 2081373 # Number of stores squashed
453 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
454 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
455 system.cpu.iew.lsq.thread0.rescheduledLoads 7821312 # Number of loads that were rescheduled
456 system.cpu.iew.lsq.thread0.cacheBlocked 4401 # Number of times an access to memory failed due to the cache being blocked
457 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
458 system.cpu.iew.iewSquashCycles 4583558 # Number of cycles IEW is squashing
459 system.cpu.iew.iewBlockCycles 45537576 # Number of cycles IEW is blocking
460 system.cpu.iew.iewUnblockCycles 6145383 # Number of cycles IEW is unblocking
461 system.cpu.iew.iewDispatchedInsts 871255363 # Number of instructions dispatched to IQ
462 system.cpu.iew.iewDispSquashedInsts 286386 # Number of squashed instructions skipped by dispatch
463 system.cpu.iew.iewDispLoadInsts 19448734 # Number of dispatched load instructions
464 system.cpu.iew.iewDispStoreInsts 10510706 # Number of dispatched store instructions
465 system.cpu.iew.iewDispNonSpecInsts 890989 # Number of dispatched non-speculative instructions
466 system.cpu.iew.iewIQFullEvents 5371019 # Number of times the IQ has become full, causing a stall
467 system.cpu.iew.iewLSQFullEvents 12371 # Number of times the LSQ has become full, causing a stall
468 system.cpu.iew.memOrderViolationEvents 11449 # Number of memory order violations
469 system.cpu.iew.predictedTakenIncorrect 894854 # Number of branches that were predicted taken incorrectly
470 system.cpu.iew.predictedNotTakenIncorrect 527277 # Number of branches that were predicted not taken incorrectly
471 system.cpu.iew.branchMispredicts 1422131 # Number of branch mispredicts detected at execute
472 system.cpu.iew.iewExecutedInsts 864388820 # Number of executed instructions
473 system.cpu.iew.iewExecLoadInsts 24990007 # Number of load instructions executed
474 system.cpu.iew.iewExecSquashedInsts 2058345 # Number of squashed instructions skipped in execute
475 system.cpu.iew.exec_swp 0 # number of swp insts executed
476 system.cpu.iew.exec_nop 0 # number of nop insts executed
477 system.cpu.iew.exec_refs 34246643 # number of memory reference insts executed
478 system.cpu.iew.exec_branches 86674452 # Number of branches executed
479 system.cpu.iew.exec_stores 9256636 # Number of stores executed
480 system.cpu.iew.exec_rate 1.868350 # Inst execution rate
481 system.cpu.iew.wb_sent 863858871 # cumulative count of insts sent to commit
482 system.cpu.iew.wb_count 855808933 # cumulative count of insts written-back
483 system.cpu.iew.wb_producers 670117555 # num instructions producing a value
484 system.cpu.iew.wb_consumers 1169388275 # num instructions consuming a value
485 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
486 system.cpu.iew.wb_rate 1.849805 # insts written-back per cycle
487 system.cpu.iew.wb_fanout 0.573050 # average fanout of values written-back
488 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
489 system.cpu.commit.commitCommittedInsts 840653382 # The number of committed instructions
490 system.cpu.commit.commitSquashedInsts 30493739 # The number of squashed insts skipped by commit
491 system.cpu.commit.commitNonSpecStalls 1519585 # The number of times commit has been forced to stall to communicate backwards
492 system.cpu.commit.branchMispredicts 1250852 # The number of times a branch was mispredicted
493 system.cpu.commit.committed_per_cycle::samples 302482532 # Number of insts commited each cycle
494 system.cpu.commit.committed_per_cycle::mean 2.779180 # Number of insts commited each cycle
495 system.cpu.commit.committed_per_cycle::stdev 2.862928 # Number of insts commited each cycle
496 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
497 system.cpu.commit.committed_per_cycle::0 121705322 40.24% 40.24% # Number of insts commited each cycle
498 system.cpu.commit.committed_per_cycle::1 14450311 4.78% 45.01% # Number of insts commited each cycle
499 system.cpu.commit.committed_per_cycle::2 4296632 1.42% 46.43% # Number of insts commited each cycle
500 system.cpu.commit.committed_per_cycle::3 76653351 25.34% 71.77% # Number of insts commited each cycle
501 system.cpu.commit.committed_per_cycle::4 3954227 1.31% 73.08% # Number of insts commited each cycle
502 system.cpu.commit.committed_per_cycle::5 1803566 0.60% 73.68% # Number of insts commited each cycle
503 system.cpu.commit.committed_per_cycle::6 1076627 0.36% 74.03% # Number of insts commited each cycle
504 system.cpu.commit.committed_per_cycle::7 71984714 23.80% 97.83% # Number of insts commited each cycle
505 system.cpu.commit.committed_per_cycle::8 6557782 2.17% 100.00% # Number of insts commited each cycle
506 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
507 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
508 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
509 system.cpu.commit.committed_per_cycle::total 302482532 # Number of insts commited each cycle
510 system.cpu.commit.count 840653382 # Number of instructions committed
511 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
512 system.cpu.commit.refs 23755065 # Number of memory references committed
513 system.cpu.commit.loads 15325732 # Number of loads committed
514 system.cpu.commit.membars 781571 # Number of memory barriers committed
515 system.cpu.commit.branches 85522464 # Number of branches committed
516 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
517 system.cpu.commit.int_insts 768481836 # Number of committed integer instructions.
518 system.cpu.commit.function_calls 0 # Number of function calls committed.
519 system.cpu.commit.bw_lim_events 6557782 # number cycles where commit BW limit reached
520 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
521 system.cpu.rob.rob_reads 1166989570 # The number of ROB reads
522 system.cpu.rob.rob_writes 1746890100 # The number of ROB writes
523 system.cpu.timesIdled 2859611 # Number of times that the entire CPU went into an idle state and unscheduled itself
524 system.cpu.idleCycles 155597963 # Total number of cycles that the CPU has spent unscheduled due to idling
525 system.cpu.quiesceCycles 9866635724 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
526 system.cpu.committedInsts 840653382 # Number of Instructions Simulated
527 system.cpu.committedInsts_total 840653382 # Number of Instructions Simulated
528 system.cpu.cpi 0.550343 # CPI: Cycles Per Instruction
529 system.cpu.cpi_total 0.550343 # CPI: Total CPI of All Threads
530 system.cpu.ipc 1.817047 # IPC: Instructions Per Cycle
531 system.cpu.ipc_total 1.817047 # IPC: Total IPC of All Threads
532 system.cpu.int_regfile_reads 1406419580 # number of integer regfile reads
533 system.cpu.int_regfile_writes 857121538 # number of integer regfile writes
534 system.cpu.fp_regfile_reads 51 # number of floating regfile reads
535 system.cpu.misc_regfile_reads 282006262 # number of misc regfile reads
536 system.cpu.misc_regfile_writes 409317 # number of misc regfile writes
537 system.cpu.icache.replacements 1024030 # number of replacements
538 system.cpu.icache.tagsinuse 510.509684 # Cycle average of tags in use
539 system.cpu.icache.total_refs 8586920 # Total number of references to valid blocks.
540 system.cpu.icache.sampled_refs 1024542 # Sample count of references to valid blocks.
541 system.cpu.icache.avg_refs 8.381228 # Average number of references to valid blocks.
542 system.cpu.icache.warmup_cycle 56648663000 # Cycle when the warmup percentage was hit.
543 system.cpu.icache.occ_blocks::0 510.509684 # Average occupied blocks per context
544 system.cpu.icache.occ_percent::0 0.997089 # Average percentage of cache occupancy
545 system.cpu.icache.ReadReq_hits::0 8586920 # number of ReadReq hits
546 system.cpu.icache.ReadReq_hits::total 8586920 # number of ReadReq hits
547 system.cpu.icache.demand_hits::0 8586920 # number of demand (read+write) hits
548 system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
549 system.cpu.icache.demand_hits::total 8586920 # number of demand (read+write) hits
550 system.cpu.icache.overall_hits::0 8586920 # number of overall hits
551 system.cpu.icache.overall_hits::1 0 # number of overall hits
552 system.cpu.icache.overall_hits::total 8586920 # number of overall hits
553 system.cpu.icache.ReadReq_misses::0 1090085 # number of ReadReq misses
554 system.cpu.icache.ReadReq_misses::total 1090085 # number of ReadReq misses
555 system.cpu.icache.demand_misses::0 1090085 # number of demand (read+write) misses
556 system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
557 system.cpu.icache.demand_misses::total 1090085 # number of demand (read+write) misses
558 system.cpu.icache.overall_misses::0 1090085 # number of overall misses
559 system.cpu.icache.overall_misses::1 0 # number of overall misses
560 system.cpu.icache.overall_misses::total 1090085 # number of overall misses
561 system.cpu.icache.ReadReq_miss_latency 16354144492 # number of ReadReq miss cycles
562 system.cpu.icache.demand_miss_latency 16354144492 # number of demand (read+write) miss cycles
563 system.cpu.icache.overall_miss_latency 16354144492 # number of overall miss cycles
564 system.cpu.icache.ReadReq_accesses::0 9677005 # number of ReadReq accesses(hits+misses)
565 system.cpu.icache.ReadReq_accesses::total 9677005 # number of ReadReq accesses(hits+misses)
566 system.cpu.icache.demand_accesses::0 9677005 # number of demand (read+write) accesses
567 system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
568 system.cpu.icache.demand_accesses::total 9677005 # number of demand (read+write) accesses
569 system.cpu.icache.overall_accesses::0 9677005 # number of overall (read+write) accesses
570 system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
571 system.cpu.icache.overall_accesses::total 9677005 # number of overall (read+write) accesses
572 system.cpu.icache.ReadReq_miss_rate::0 0.112647 # miss rate for ReadReq accesses
573 system.cpu.icache.demand_miss_rate::0 0.112647 # miss rate for demand accesses
574 system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
575 system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
576 system.cpu.icache.overall_miss_rate::0 0.112647 # miss rate for overall accesses
577 system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
578 system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
579 system.cpu.icache.ReadReq_avg_miss_latency::0 15002.632356 # average ReadReq miss latency
580 system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
581 system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
582 system.cpu.icache.demand_avg_miss_latency::0 15002.632356 # average overall miss latency
583 system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
584 system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
585 system.cpu.icache.overall_avg_miss_latency::0 15002.632356 # average overall miss latency
586 system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
587 system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
588 system.cpu.icache.blocked_cycles::no_mshrs 2751493 # number of cycles access was blocked
589 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590 system.cpu.icache.blocked::no_mshrs 271 # number of cycles access was blocked
591 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
592 system.cpu.icache.avg_blocked_cycles::no_mshrs 10153.110701 # average number of cycles each access was blocked
593 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
594 system.cpu.icache.fast_writes 0 # number of fast writes performed
595 system.cpu.icache.cache_copies 0 # number of cache copies performed
596 system.cpu.icache.writebacks 1551 # number of writebacks
597 system.cpu.icache.ReadReq_mshr_hits 61895 # number of ReadReq MSHR hits
598 system.cpu.icache.demand_mshr_hits 61895 # number of demand (read+write) MSHR hits
599 system.cpu.icache.overall_mshr_hits 61895 # number of overall MSHR hits
600 system.cpu.icache.ReadReq_mshr_misses 1028190 # number of ReadReq MSHR misses
601 system.cpu.icache.demand_mshr_misses 1028190 # number of demand (read+write) MSHR misses
602 system.cpu.icache.overall_mshr_misses 1028190 # number of overall MSHR misses
603 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
604 system.cpu.icache.ReadReq_mshr_miss_latency 12436535493 # number of ReadReq MSHR miss cycles
605 system.cpu.icache.demand_mshr_miss_latency 12436535493 # number of demand (read+write) MSHR miss cycles
606 system.cpu.icache.overall_mshr_miss_latency 12436535493 # number of overall MSHR miss cycles
607 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
608 system.cpu.icache.ReadReq_mshr_miss_rate::0 0.106251 # mshr miss rate for ReadReq accesses
609 system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
610 system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
611 system.cpu.icache.demand_mshr_miss_rate::0 0.106251 # mshr miss rate for demand accesses
612 system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
613 system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
614 system.cpu.icache.overall_mshr_miss_rate::0 0.106251 # mshr miss rate for overall accesses
615 system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
616 system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
617 system.cpu.icache.ReadReq_avg_mshr_miss_latency 12095.561611 # average ReadReq mshr miss latency
618 system.cpu.icache.demand_avg_mshr_miss_latency 12095.561611 # average overall mshr miss latency
619 system.cpu.icache.overall_avg_mshr_miss_latency 12095.561611 # average overall mshr miss latency
620 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
621 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
622 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
623 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
624 system.cpu.itb_walker_cache.replacements 9946 # number of replacements
625 system.cpu.itb_walker_cache.tagsinuse 6.010746 # Cycle average of tags in use
626 system.cpu.itb_walker_cache.total_refs 24573 # Total number of references to valid blocks.
627 system.cpu.itb_walker_cache.sampled_refs 9958 # Sample count of references to valid blocks.
628 system.cpu.itb_walker_cache.avg_refs 2.467664 # Average number of references to valid blocks.
629 system.cpu.itb_walker_cache.warmup_cycle 5129655075000 # Cycle when the warmup percentage was hit.
630 system.cpu.itb_walker_cache.occ_blocks::1 6.010746 # Average occupied blocks per context
631 system.cpu.itb_walker_cache.occ_percent::1 0.375672 # Average percentage of cache occupancy
632 system.cpu.itb_walker_cache.ReadReq_hits::1 24609 # number of ReadReq hits
633 system.cpu.itb_walker_cache.ReadReq_hits::total 24609 # number of ReadReq hits
634 system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits
635 system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
636 system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
637 system.cpu.itb_walker_cache.demand_hits::1 24612 # number of demand (read+write) hits
638 system.cpu.itb_walker_cache.demand_hits::total 24612 # number of demand (read+write) hits
639 system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
640 system.cpu.itb_walker_cache.overall_hits::1 24612 # number of overall hits
641 system.cpu.itb_walker_cache.overall_hits::total 24612 # number of overall hits
642 system.cpu.itb_walker_cache.ReadReq_misses::1 10808 # number of ReadReq misses
643 system.cpu.itb_walker_cache.ReadReq_misses::total 10808 # number of ReadReq misses
644 system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
645 system.cpu.itb_walker_cache.demand_misses::1 10808 # number of demand (read+write) misses
646 system.cpu.itb_walker_cache.demand_misses::total 10808 # number of demand (read+write) misses
647 system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
648 system.cpu.itb_walker_cache.overall_misses::1 10808 # number of overall misses
649 system.cpu.itb_walker_cache.overall_misses::total 10808 # number of overall misses
650 system.cpu.itb_walker_cache.ReadReq_miss_latency 135307500 # number of ReadReq miss cycles
651 system.cpu.itb_walker_cache.demand_miss_latency 135307500 # number of demand (read+write) miss cycles
652 system.cpu.itb_walker_cache.overall_miss_latency 135307500 # number of overall miss cycles
653 system.cpu.itb_walker_cache.ReadReq_accesses::1 35417 # number of ReadReq accesses(hits+misses)
654 system.cpu.itb_walker_cache.ReadReq_accesses::total 35417 # number of ReadReq accesses(hits+misses)
655 system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses)
656 system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
657 system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
658 system.cpu.itb_walker_cache.demand_accesses::1 35420 # number of demand (read+write) accesses
659 system.cpu.itb_walker_cache.demand_accesses::total 35420 # number of demand (read+write) accesses
660 system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
661 system.cpu.itb_walker_cache.overall_accesses::1 35420 # number of overall (read+write) accesses
662 system.cpu.itb_walker_cache.overall_accesses::total 35420 # number of overall (read+write) accesses
663 system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.305164 # miss rate for ReadReq accesses
664 system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
665 system.cpu.itb_walker_cache.demand_miss_rate::1 0.305138 # miss rate for demand accesses
666 system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
667 system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
668 system.cpu.itb_walker_cache.overall_miss_rate::1 0.305138 # miss rate for overall accesses
669 system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
670 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
671 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12519.198742 # average ReadReq miss latency
672 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
673 system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
674 system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12519.198742 # average overall miss latency
675 system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
676 system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
677 system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12519.198742 # average overall miss latency
678 system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
679 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
680 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
681 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
682 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
683 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
684 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
685 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
686 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
687 system.cpu.itb_walker_cache.writebacks 1317 # number of writebacks
688 system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
689 system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
690 system.cpu.itb_walker_cache.ReadReq_mshr_misses 10808 # number of ReadReq MSHR misses
691 system.cpu.itb_walker_cache.demand_mshr_misses 10808 # number of demand (read+write) MSHR misses
692 system.cpu.itb_walker_cache.overall_mshr_misses 10808 # number of overall MSHR misses
693 system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
694 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 102536000 # number of ReadReq MSHR miss cycles
695 system.cpu.itb_walker_cache.demand_mshr_miss_latency 102536000 # number of demand (read+write) MSHR miss cycles
696 system.cpu.itb_walker_cache.overall_mshr_miss_latency 102536000 # number of overall MSHR miss cycles
697 system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
698 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
699 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.305164 # mshr miss rate for ReadReq accesses
700 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
701 system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
702 system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.305138 # mshr miss rate for demand accesses
703 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
704 system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
705 system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.305138 # mshr miss rate for overall accesses
706 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
707 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9487.046632 # average ReadReq mshr miss latency
708 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9487.046632 # average overall mshr miss latency
709 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9487.046632 # average overall mshr miss latency
710 system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
711 system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
712 system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
713 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
714 system.cpu.dtb_walker_cache.replacements 147569 # number of replacements
715 system.cpu.dtb_walker_cache.tagsinuse 13.856334 # Cycle average of tags in use
716 system.cpu.dtb_walker_cache.total_refs 141316 # Total number of references to valid blocks.
717 system.cpu.dtb_walker_cache.sampled_refs 147583 # Sample count of references to valid blocks.
718 system.cpu.dtb_walker_cache.avg_refs 0.957536 # Average number of references to valid blocks.
719 system.cpu.dtb_walker_cache.warmup_cycle 5108660928000 # Cycle when the warmup percentage was hit.
720 system.cpu.dtb_walker_cache.occ_blocks::1 13.856334 # Average occupied blocks per context
721 system.cpu.dtb_walker_cache.occ_percent::1 0.866021 # Average percentage of cache occupancy
722 system.cpu.dtb_walker_cache.ReadReq_hits::1 141317 # number of ReadReq hits
723 system.cpu.dtb_walker_cache.ReadReq_hits::total 141317 # number of ReadReq hits
724 system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
725 system.cpu.dtb_walker_cache.demand_hits::1 141317 # number of demand (read+write) hits
726 system.cpu.dtb_walker_cache.demand_hits::total 141317 # number of demand (read+write) hits
727 system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
728 system.cpu.dtb_walker_cache.overall_hits::1 141317 # number of overall hits
729 system.cpu.dtb_walker_cache.overall_hits::total 141317 # number of overall hits
730 system.cpu.dtb_walker_cache.ReadReq_misses::1 148425 # number of ReadReq misses
731 system.cpu.dtb_walker_cache.ReadReq_misses::total 148425 # number of ReadReq misses
732 system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
733 system.cpu.dtb_walker_cache.demand_misses::1 148425 # number of demand (read+write) misses
734 system.cpu.dtb_walker_cache.demand_misses::total 148425 # number of demand (read+write) misses
735 system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
736 system.cpu.dtb_walker_cache.overall_misses::1 148425 # number of overall misses
737 system.cpu.dtb_walker_cache.overall_misses::total 148425 # number of overall misses
738 system.cpu.dtb_walker_cache.ReadReq_miss_latency 2057871000 # number of ReadReq miss cycles
739 system.cpu.dtb_walker_cache.demand_miss_latency 2057871000 # number of demand (read+write) miss cycles
740 system.cpu.dtb_walker_cache.overall_miss_latency 2057871000 # number of overall miss cycles
741 system.cpu.dtb_walker_cache.ReadReq_accesses::1 289742 # number of ReadReq accesses(hits+misses)
742 system.cpu.dtb_walker_cache.ReadReq_accesses::total 289742 # number of ReadReq accesses(hits+misses)
743 system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
744 system.cpu.dtb_walker_cache.demand_accesses::1 289742 # number of demand (read+write) accesses
745 system.cpu.dtb_walker_cache.demand_accesses::total 289742 # number of demand (read+write) accesses
746 system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
747 system.cpu.dtb_walker_cache.overall_accesses::1 289742 # number of overall (read+write) accesses
748 system.cpu.dtb_walker_cache.overall_accesses::total 289742 # number of overall (read+write) accesses
749 system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.512266 # miss rate for ReadReq accesses
750 system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
751 system.cpu.dtb_walker_cache.demand_miss_rate::1 0.512266 # miss rate for demand accesses
752 system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
753 system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
754 system.cpu.dtb_walker_cache.overall_miss_rate::1 0.512266 # miss rate for overall accesses
755 system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
756 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
757 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13864.719555 # average ReadReq miss latency
758 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
759 system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
760 system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13864.719555 # average overall miss latency
761 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
762 system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
763 system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13864.719555 # average overall miss latency
764 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
765 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
766 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
767 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
768 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
769 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
770 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
771 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
772 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
773 system.cpu.dtb_walker_cache.writebacks 45859 # number of writebacks
774 system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
775 system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
776 system.cpu.dtb_walker_cache.ReadReq_mshr_misses 148425 # number of ReadReq MSHR misses
777 system.cpu.dtb_walker_cache.demand_mshr_misses 148425 # number of demand (read+write) MSHR misses
778 system.cpu.dtb_walker_cache.overall_mshr_misses 148425 # number of overall MSHR misses
779 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
780 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1608796000 # number of ReadReq MSHR miss cycles
781 system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1608796000 # number of demand (read+write) MSHR miss cycles
782 system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1608796000 # number of overall MSHR miss cycles
783 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
784 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
785 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.512266 # mshr miss rate for ReadReq accesses
786 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
787 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
788 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.512266 # mshr miss rate for demand accesses
789 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
790 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
791 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.512266 # mshr miss rate for overall accesses
792 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
793 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10839.117399 # average ReadReq mshr miss latency
794 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10839.117399 # average overall mshr miss latency
795 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10839.117399 # average overall mshr miss latency
796 system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
797 system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
798 system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
799 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
800 system.cpu.dcache.replacements 1662019 # number of replacements
801 system.cpu.dcache.tagsinuse 511.997109 # Cycle average of tags in use
802 system.cpu.dcache.total_refs 19289790 # Total number of references to valid blocks.
803 system.cpu.dcache.sampled_refs 1662531 # Sample count of references to valid blocks.
804 system.cpu.dcache.avg_refs 11.602665 # Average number of references to valid blocks.
805 system.cpu.dcache.warmup_cycle 34336000 # Cycle when the warmup percentage was hit.
806 system.cpu.dcache.occ_blocks::0 511.997109 # Average occupied blocks per context
807 system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy
808 system.cpu.dcache.ReadReq_hits::0 11184512 # number of ReadReq hits
809 system.cpu.dcache.ReadReq_hits::total 11184512 # number of ReadReq hits
810 system.cpu.dcache.WriteReq_hits::0 8099002 # number of WriteReq hits
811 system.cpu.dcache.WriteReq_hits::total 8099002 # number of WriteReq hits
812 system.cpu.dcache.demand_hits::0 19283514 # number of demand (read+write) hits
813 system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
814 system.cpu.dcache.demand_hits::total 19283514 # number of demand (read+write) hits
815 system.cpu.dcache.overall_hits::0 19283514 # number of overall hits
816 system.cpu.dcache.overall_hits::1 0 # number of overall hits
817 system.cpu.dcache.overall_hits::total 19283514 # number of overall hits
818 system.cpu.dcache.ReadReq_misses::0 2387566 # number of ReadReq misses
819 system.cpu.dcache.ReadReq_misses::total 2387566 # number of ReadReq misses
820 system.cpu.dcache.WriteReq_misses::0 320977 # number of WriteReq misses
821 system.cpu.dcache.WriteReq_misses::total 320977 # number of WriteReq misses
822 system.cpu.dcache.demand_misses::0 2708543 # number of demand (read+write) misses
823 system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
824 system.cpu.dcache.demand_misses::total 2708543 # number of demand (read+write) misses
825 system.cpu.dcache.overall_misses::0 2708543 # number of overall misses
826 system.cpu.dcache.overall_misses::1 0 # number of overall misses
827 system.cpu.dcache.overall_misses::total 2708543 # number of overall misses
828 system.cpu.dcache.ReadReq_miss_latency 35727347000 # number of ReadReq miss cycles
829 system.cpu.dcache.WriteReq_miss_latency 10720598495 # number of WriteReq miss cycles
830 system.cpu.dcache.demand_miss_latency 46447945495 # number of demand (read+write) miss cycles
831 system.cpu.dcache.overall_miss_latency 46447945495 # number of overall miss cycles
832 system.cpu.dcache.ReadReq_accesses::0 13572078 # number of ReadReq accesses(hits+misses)
833 system.cpu.dcache.ReadReq_accesses::total 13572078 # number of ReadReq accesses(hits+misses)
834 system.cpu.dcache.WriteReq_accesses::0 8419979 # number of WriteReq accesses(hits+misses)
835 system.cpu.dcache.WriteReq_accesses::total 8419979 # number of WriteReq accesses(hits+misses)
836 system.cpu.dcache.demand_accesses::0 21992057 # number of demand (read+write) accesses
837 system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
838 system.cpu.dcache.demand_accesses::total 21992057 # number of demand (read+write) accesses
839 system.cpu.dcache.overall_accesses::0 21992057 # number of overall (read+write) accesses
840 system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
841 system.cpu.dcache.overall_accesses::total 21992057 # number of overall (read+write) accesses
842 system.cpu.dcache.ReadReq_miss_rate::0 0.175917 # miss rate for ReadReq accesses
843 system.cpu.dcache.WriteReq_miss_rate::0 0.038121 # miss rate for WriteReq accesses
844 system.cpu.dcache.demand_miss_rate::0 0.123160 # miss rate for demand accesses
845 system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
846 system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
847 system.cpu.dcache.overall_miss_rate::0 0.123160 # miss rate for overall accesses
848 system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
849 system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
850 system.cpu.dcache.ReadReq_avg_miss_latency::0 14963.920160 # average ReadReq miss latency
851 system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
852 system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
853 system.cpu.dcache.WriteReq_avg_miss_latency::0 33399.896239 # average WriteReq miss latency
854 system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
855 system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
856 system.cpu.dcache.demand_avg_miss_latency::0 17148.683072 # average overall miss latency
857 system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
858 system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
859 system.cpu.dcache.overall_avg_miss_latency::0 17148.683072 # average overall miss latency
860 system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
861 system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
862 system.cpu.dcache.blocked_cycles::no_mshrs 28980495 # number of cycles access was blocked
863 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
864 system.cpu.dcache.blocked::no_mshrs 5023 # number of cycles access was blocked
865 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
866 system.cpu.dcache.avg_blocked_cycles::no_mshrs 5769.559028 # average number of cycles each access was blocked
867 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
868 system.cpu.dcache.fast_writes 0 # number of fast writes performed
869 system.cpu.dcache.cache_copies 0 # number of cache copies performed
870 system.cpu.dcache.writebacks 1550298 # number of writebacks
871 system.cpu.dcache.ReadReq_mshr_hits 1017351 # number of ReadReq MSHR hits
872 system.cpu.dcache.WriteReq_mshr_hits 22830 # number of WriteReq MSHR hits
873 system.cpu.dcache.demand_mshr_hits 1040181 # number of demand (read+write) MSHR hits
874 system.cpu.dcache.overall_mshr_hits 1040181 # number of overall MSHR hits
875 system.cpu.dcache.ReadReq_mshr_misses 1370215 # number of ReadReq MSHR misses
876 system.cpu.dcache.WriteReq_mshr_misses 298147 # number of WriteReq MSHR misses
877 system.cpu.dcache.demand_mshr_misses 1668362 # number of demand (read+write) MSHR misses
878 system.cpu.dcache.overall_mshr_misses 1668362 # number of overall MSHR misses
879 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
880 system.cpu.dcache.ReadReq_mshr_miss_latency 17997979500 # number of ReadReq MSHR miss cycles
881 system.cpu.dcache.WriteReq_mshr_miss_latency 9490426995 # number of WriteReq MSHR miss cycles
882 system.cpu.dcache.demand_mshr_miss_latency 27488406495 # number of demand (read+write) MSHR miss cycles
883 system.cpu.dcache.overall_mshr_miss_latency 27488406495 # number of overall MSHR miss cycles
884 system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85207522500 # number of ReadReq MSHR uncacheable cycles
885 system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1392017000 # number of WriteReq MSHR uncacheable cycles
886 system.cpu.dcache.overall_mshr_uncacheable_latency 86599539500 # number of overall MSHR uncacheable cycles
887 system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.100958 # mshr miss rate for ReadReq accesses
888 system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
889 system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
890 system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035409 # mshr miss rate for WriteReq accesses
891 system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
892 system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
893 system.cpu.dcache.demand_mshr_miss_rate::0 0.075862 # mshr miss rate for demand accesses
894 system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
895 system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
896 system.cpu.dcache.overall_mshr_miss_rate::0 0.075862 # mshr miss rate for overall accesses
897 system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
898 system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
899 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13135.149958 # average ReadReq mshr miss latency
900 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31831.368402 # average WriteReq mshr miss latency
901 system.cpu.dcache.demand_avg_mshr_miss_latency 16476.284221 # average overall mshr miss latency
902 system.cpu.dcache.overall_avg_mshr_miss_latency 16476.284221 # average overall mshr miss latency
903 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
904 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
905 system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
906 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
907 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
908 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
909 system.cpu.kern.inst.arm 0 # number of arm instructions executed
910 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
912 ---------- End Simulation Statistics ----------
projects / gem5.git / blob