2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.129943 # Number of seconds simulated
4 sim_ticks 5129943020500 # Number of ticks simulated
5 final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 121408 # Simulator instruction rate (inst/s)
8 host_op_rate 239988 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 1526556123 # Simulator tick rate (ticks/s)
10 host_mem_usage 798272 # Number of bytes of host memory used
11 host_seconds 3360.47 # Real time elapsed on the host
12 sim_insts 407987808 # Number of instructions simulated
13 sim_ops 806471132 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185604 # Number of read requests accepted
52 system.physmem.writeReqs 196636 # Number of write requests accepted
53 system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11483 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 10958 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 11903 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11497 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 11986 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11369 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 11563 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11462 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11178 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11812 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11732 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11823 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 11783 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12309 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11732 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 10811 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 14023 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 13077 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 12485 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 11134 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 11942 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 11710 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 11692 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 11673 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 11519 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 11764 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 12914 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 11938 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 12257 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 11913 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 12398 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 11971 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
97 system.physmem.totGap 5129942968500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185604 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 196636 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 170730 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11911 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 2018 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 400 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 28 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 28 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2574 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 4997 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 9722 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 11014 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 11539 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 12555 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 13007 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 14095 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 13776 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 14313 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 13208 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 12728 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 11239 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 10589 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 8962 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8627 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 8507 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 8355 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 411 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 382 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 322 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 228 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 235 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 122 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 75289 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 322.860444 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 187.432072 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 341.383638 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 27971 37.15% 37.15% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17364 23.06% 60.21% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7569 10.05% 70.27% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4193 5.57% 75.84% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 3123 4.15% 79.99% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 1949 2.59% 82.57% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1359 1.81% 84.38% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1178 1.56% 85.94% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 10583 14.06% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7789 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 23.801643 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 545.365861 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7788 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7789 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7789 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 24.959558 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 20.372117 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 24.594707 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6350 81.53% 81.53% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 59 0.76% 82.28% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 17 0.22% 82.50% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 286 3.67% 86.17% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 164 2.11% 88.28% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 59 0.76% 89.04% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 41 0.53% 89.56% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 34 0.44% 90.00% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 175 2.25% 92.25% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 16 0.21% 92.45% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 16 0.21% 92.66% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 13 0.17% 92.82% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 28 0.36% 93.18% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 16 0.21% 93.39% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 10 0.13% 93.52% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 42 0.54% 94.06% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 108 1.39% 95.44% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::84-87 9 0.12% 95.56% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::88-91 9 0.12% 95.67% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::92-95 24 0.31% 95.98% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::96-99 141 1.81% 97.79% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::100-103 3 0.04% 97.83% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::104-107 13 0.17% 98.00% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::108-111 4 0.05% 98.05% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::112-115 34 0.44% 98.49% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads
287 system.physmem.totQLat 1998636250 # Total ticks spent queuing
288 system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM
289 system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers
290 system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst
291 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
292 system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst
293 system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
294 system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s
295 system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
296 system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
297 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
298 system.physmem.busUtil 0.04 # Data bus utilization in percentage
299 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
300 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
301 system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
302 system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing
303 system.physmem.readRowHits 152292 # Number of row buffer hits during reads
304 system.physmem.writeRowHits 152229 # Number of row buffer hits during writes
305 system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
306 system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes
307 system.physmem.avgGap 13420738.20 # Average gap between requests
308 system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
309 system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ)
310 system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ)
311 system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ)
312 system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ)
313 system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ)
314 system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ)
315 system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ)
316 system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ)
317 system.physmem_0.averagePower 668.764961 # Core power per rank (mW)
318 system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states
319 system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states
320 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
321 system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states
322 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
323 system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ)
324 system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ)
325 system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ)
326 system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ)
327 system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ)
328 system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ)
329 system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ)
330 system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ)
331 system.physmem_1.averagePower 668.773213 # Core power per rank (mW)
332 system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states
333 system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states
334 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
335 system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states
336 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
337 system.cpu.branchPred.lookups 86966196 # Number of BP lookups
338 system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted
339 system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect
340 system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups
341 system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits
342 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
343 system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage
344 system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target.
345 system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions.
346 system.cpu_clk_domain.clock 500 # Clock period in ticks
347 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
348 system.cpu.numCycles 449725865 # number of cpu cycles simulated
349 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
350 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
351 system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss
352 system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed
353 system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered
354 system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken
355 system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked
356 system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing
357 system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb
358 system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
359 system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps
360 system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions
361 system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR
362 system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched
363 system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed
364 system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed
365 system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total)
375 system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total)
378 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
379 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
380 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
381 system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total)
382 system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle
383 system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle
384 system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle
385 system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked
386 system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running
387 system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking
388 system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing
389 system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode
390 system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing
391 system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle
392 system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking
393 system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst
394 system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running
395 system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking
396 system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename
397 system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full
398 system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full
399 system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full
400 system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full
401 system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed
402 system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made
403 system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups
404 system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups
405 system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed
406 system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing
407 system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed
408 system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed
409 system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer
410 system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit.
411 system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit.
412 system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads.
413 system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores.
414 system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec)
415 system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ
416 system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued
417 system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued
418 system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling
419 system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph
420 system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed
421 system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle
432 system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle
433 system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle
434 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
435 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
436 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
437 system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle
438 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
439 system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available
440 system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available
441 system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available
442 system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available
443 system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available
444 system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available
445 system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available
446 system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available
447 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available
463 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available
464 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available
465 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available
466 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available
467 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available
468 system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available
469 system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available
470 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
471 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
472 system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued
473 system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued
474 system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued
475 system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued
476 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
477 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
478 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
479 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
480 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
481 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
497 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
498 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
499 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
500 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
501 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
502 system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued
503 system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued
504 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
505 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
506 system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued
507 system.cpu.iq.rate 1.833352 # Inst issue rate
508 system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested
509 system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst)
510 system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads
511 system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes
512 system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses
513 system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads
514 system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes
515 system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
516 system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses
517 system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses
518 system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores
519 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
520 system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed
521 system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed
522 system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations
523 system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed
524 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
525 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
526 system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled
527 system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked
528 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
529 system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing
530 system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking
531 system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking
532 system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ
533 system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch
534 system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions
535 system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions
536 system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions
537 system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall
538 system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall
539 system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations
540 system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly
541 system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly
542 system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute
543 system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions
544 system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed
545 system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute
546 system.cpu.iew.exec_swp 0 # number of swp insts executed
547 system.cpu.iew.exec_nop 0 # number of nop insts executed
548 system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed
549 system.cpu.iew.exec_branches 83327917 # Number of branches executed
550 system.cpu.iew.exec_stores 9177504 # Number of stores executed
551 system.cpu.iew.exec_rate 1.829721 # Inst execution rate
552 system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit
553 system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back
554 system.cpu.iew.wb_producers 641186937 # num instructions producing a value
555 system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value
556 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
557 system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle
558 system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back
559 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
560 system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit
561 system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards
562 system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted
563 system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle
575 system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle
576 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
577 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
578 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
579 system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle
580 system.cpu.commit.committedInsts 407987808 # Number of instructions committed
581 system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed
582 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
583 system.cpu.commit.refs 22432051 # Number of memory references committed
584 system.cpu.commit.loads 14002440 # Number of loads committed
585 system.cpu.commit.membars 475347 # Number of memory barriers committed
586 system.cpu.commit.branches 82201961 # Number of branches committed
587 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
588 system.cpu.commit.int_insts 735281139 # Number of committed integer instructions.
589 system.cpu.commit.function_calls 1155976 # Number of function calls committed.
590 system.cpu.commit.op_class_0::No_OpClass 174273 0.02% 0.02% # Class of committed instruction
591 system.cpu.commit.op_class_0::IntAlu 783598184 97.16% 97.19% # Class of committed instruction
592 system.cpu.commit.op_class_0::IntMult 145019 0.02% 97.20% # Class of committed instruction
593 system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
595 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
596 system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
597 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
598 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
599 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
600 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
601 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
602 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
603 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
604 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
605 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
606 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
607 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
608 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
609 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
610 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
611 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
612 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
613 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
614 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
615 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
616 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
617 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
618 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
619 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
620 system.cpu.commit.op_class_0::MemRead 14002440 1.74% 98.95% # Class of committed instruction
621 system.cpu.commit.op_class_0::MemWrite 8429611 1.05% 100.00% # Class of committed instruction
622 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
623 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
624 system.cpu.commit.op_class_0::total 806471132 # Class of committed instruction
625 system.cpu.commit.bw_lim_events 5452798 # number cycles where commit BW limit reached
626 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
627 system.cpu.rob.rob_reads 1268912158 # The number of ROB reads
628 system.cpu.rob.rob_writes 1665595320 # The number of ROB writes
629 system.cpu.timesIdled 297665 # Number of times that the entire CPU went into an idle state and unscheduled itself
630 system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling
631 system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
632 system.cpu.committedInsts 407987808 # Number of Instructions Simulated
633 system.cpu.committedOps 806471132 # Number of Ops (including micro ops) Simulated
634 system.cpu.cpi 1.102302 # CPI: Cycles Per Instruction
635 system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads
636 system.cpu.ipc 0.907192 # IPC: Instructions Per Cycle
637 system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads
638 system.cpu.int_regfile_reads 1092777925 # number of integer regfile reads
639 system.cpu.int_regfile_writes 656276714 # number of integer regfile writes
640 system.cpu.fp_regfile_reads 50 # number of floating regfile reads
641 system.cpu.cc_regfile_reads 416321461 # number of cc regfile reads
642 system.cpu.cc_regfile_writes 322134346 # number of cc regfile writes
643 system.cpu.misc_regfile_reads 265712042 # number of misc regfile reads
644 system.cpu.misc_regfile_writes 402822 # number of misc regfile writes
645 system.cpu.dcache.tags.replacements 1660901 # number of replacements
646 system.cpu.dcache.tags.tagsinuse 511.996168 # Cycle average of tags in use
647 system.cpu.dcache.tags.total_refs 19148306 # Total number of references to valid blocks.
648 system.cpu.dcache.tags.sampled_refs 1661413 # Sample count of references to valid blocks.
649 system.cpu.dcache.tags.avg_refs 11.525314 # Average number of references to valid blocks.
650 system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
651 system.cpu.dcache.tags.occ_blocks::cpu.data 511.996168 # Average occupied blocks per requestor
652 system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
653 system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
654 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
655 system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id
656 system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id
657 system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
658 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
659 system.cpu.dcache.tags.tag_accesses 88407170 # Number of tag accesses
660 system.cpu.dcache.tags.data_accesses 88407170 # Number of data accesses
661 system.cpu.dcache.ReadReq_hits::cpu.data 10993462 # number of ReadReq hits
662 system.cpu.dcache.ReadReq_hits::total 10993462 # number of ReadReq hits
663 system.cpu.dcache.WriteReq_hits::cpu.data 8086554 # number of WriteReq hits
664 system.cpu.dcache.WriteReq_hits::total 8086554 # number of WriteReq hits
665 system.cpu.dcache.SoftPFReq_hits::cpu.data 65615 # number of SoftPFReq hits
666 system.cpu.dcache.SoftPFReq_hits::total 65615 # number of SoftPFReq hits
667 system.cpu.dcache.demand_hits::cpu.data 19080016 # number of demand (read+write) hits
668 system.cpu.dcache.demand_hits::total 19080016 # number of demand (read+write) hits
669 system.cpu.dcache.overall_hits::cpu.data 19145631 # number of overall hits
670 system.cpu.dcache.overall_hits::total 19145631 # number of overall hits
671 system.cpu.dcache.ReadReq_misses::cpu.data 1801010 # number of ReadReq misses
672 system.cpu.dcache.ReadReq_misses::total 1801010 # number of ReadReq misses
673 system.cpu.dcache.WriteReq_misses::cpu.data 333393 # number of WriteReq misses
674 system.cpu.dcache.WriteReq_misses::total 333393 # number of WriteReq misses
675 system.cpu.dcache.SoftPFReq_misses::cpu.data 406403 # number of SoftPFReq misses
676 system.cpu.dcache.SoftPFReq_misses::total 406403 # number of SoftPFReq misses
677 system.cpu.dcache.demand_misses::cpu.data 2134403 # number of demand (read+write) misses
678 system.cpu.dcache.demand_misses::total 2134403 # number of demand (read+write) misses
679 system.cpu.dcache.overall_misses::cpu.data 2540806 # number of overall misses
680 system.cpu.dcache.overall_misses::total 2540806 # number of overall misses
681 system.cpu.dcache.ReadReq_miss_latency::cpu.data 26556774697 # number of ReadReq miss cycles
682 system.cpu.dcache.ReadReq_miss_latency::total 26556774697 # number of ReadReq miss cycles
683 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12861853063 # number of WriteReq miss cycles
684 system.cpu.dcache.WriteReq_miss_latency::total 12861853063 # number of WriteReq miss cycles
685 system.cpu.dcache.demand_miss_latency::cpu.data 39418627760 # number of demand (read+write) miss cycles
686 system.cpu.dcache.demand_miss_latency::total 39418627760 # number of demand (read+write) miss cycles
687 system.cpu.dcache.overall_miss_latency::cpu.data 39418627760 # number of overall miss cycles
688 system.cpu.dcache.overall_miss_latency::total 39418627760 # number of overall miss cycles
689 system.cpu.dcache.ReadReq_accesses::cpu.data 12794472 # number of ReadReq accesses(hits+misses)
690 system.cpu.dcache.ReadReq_accesses::total 12794472 # number of ReadReq accesses(hits+misses)
691 system.cpu.dcache.WriteReq_accesses::cpu.data 8419947 # number of WriteReq accesses(hits+misses)
692 system.cpu.dcache.WriteReq_accesses::total 8419947 # number of WriteReq accesses(hits+misses)
693 system.cpu.dcache.SoftPFReq_accesses::cpu.data 472018 # number of SoftPFReq accesses(hits+misses)
694 system.cpu.dcache.SoftPFReq_accesses::total 472018 # number of SoftPFReq accesses(hits+misses)
695 system.cpu.dcache.demand_accesses::cpu.data 21214419 # number of demand (read+write) accesses
696 system.cpu.dcache.demand_accesses::total 21214419 # number of demand (read+write) accesses
697 system.cpu.dcache.overall_accesses::cpu.data 21686437 # number of overall (read+write) accesses
698 system.cpu.dcache.overall_accesses::total 21686437 # number of overall (read+write) accesses
699 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140765 # miss rate for ReadReq accesses
700 system.cpu.dcache.ReadReq_miss_rate::total 0.140765 # miss rate for ReadReq accesses
701 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039596 # miss rate for WriteReq accesses
702 system.cpu.dcache.WriteReq_miss_rate::total 0.039596 # miss rate for WriteReq accesses
703 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860990 # miss rate for SoftPFReq accesses
704 system.cpu.dcache.SoftPFReq_miss_rate::total 0.860990 # miss rate for SoftPFReq accesses
705 system.cpu.dcache.demand_miss_rate::cpu.data 0.100611 # miss rate for demand accesses
706 system.cpu.dcache.demand_miss_rate::total 0.100611 # miss rate for demand accesses
707 system.cpu.dcache.overall_miss_rate::cpu.data 0.117161 # miss rate for overall accesses
708 system.cpu.dcache.overall_miss_rate::total 0.117161 # miss rate for overall accesses
709 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.489862 # average ReadReq miss latency
710 system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.489862 # average ReadReq miss latency
711 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38578.653610 # average WriteReq miss latency
712 system.cpu.dcache.WriteReq_avg_miss_latency::total 38578.653610 # average WriteReq miss latency
713 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18468.221681 # average overall miss latency
714 system.cpu.dcache.demand_avg_miss_latency::total 18468.221681 # average overall miss latency
715 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15514.221771 # average overall miss latency
716 system.cpu.dcache.overall_avg_miss_latency::total 15514.221771 # average overall miss latency
717 system.cpu.dcache.blocked_cycles::no_mshrs 376585 # number of cycles access was blocked
718 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
719 system.cpu.dcache.blocked::no_mshrs 40128 # number of cycles access was blocked
720 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
721 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.384594 # average number of cycles each access was blocked
722 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
723 system.cpu.dcache.fast_writes 0 # number of fast writes performed
724 system.cpu.dcache.cache_copies 0 # number of cache copies performed
725 system.cpu.dcache.writebacks::writebacks 1561149 # number of writebacks
726 system.cpu.dcache.writebacks::total 1561149 # number of writebacks
727 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829563 # number of ReadReq MSHR hits
728 system.cpu.dcache.ReadReq_mshr_hits::total 829563 # number of ReadReq MSHR hits
729 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44151 # number of WriteReq MSHR hits
730 system.cpu.dcache.WriteReq_mshr_hits::total 44151 # number of WriteReq MSHR hits
731 system.cpu.dcache.demand_mshr_hits::cpu.data 873714 # number of demand (read+write) MSHR hits
732 system.cpu.dcache.demand_mshr_hits::total 873714 # number of demand (read+write) MSHR hits
733 system.cpu.dcache.overall_mshr_hits::cpu.data 873714 # number of overall MSHR hits
734 system.cpu.dcache.overall_mshr_hits::total 873714 # number of overall MSHR hits
735 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971447 # number of ReadReq MSHR misses
736 system.cpu.dcache.ReadReq_mshr_misses::total 971447 # number of ReadReq MSHR misses
737 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289242 # number of WriteReq MSHR misses
738 system.cpu.dcache.WriteReq_mshr_misses::total 289242 # number of WriteReq MSHR misses
739 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402941 # number of SoftPFReq MSHR misses
740 system.cpu.dcache.SoftPFReq_mshr_misses::total 402941 # number of SoftPFReq MSHR misses
741 system.cpu.dcache.demand_mshr_misses::cpu.data 1260689 # number of demand (read+write) MSHR misses
742 system.cpu.dcache.demand_mshr_misses::total 1260689 # number of demand (read+write) MSHR misses
743 system.cpu.dcache.overall_mshr_misses::cpu.data 1663630 # number of overall MSHR misses
744 system.cpu.dcache.overall_mshr_misses::total 1663630 # number of overall MSHR misses
745 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12263679766 # number of ReadReq MSHR miss cycles
746 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12263679766 # number of ReadReq MSHR miss cycles
747 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11196249664 # number of WriteReq MSHR miss cycles
748 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11196249664 # number of WriteReq MSHR miss cycles
749 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5590634504 # number of SoftPFReq MSHR miss cycles
750 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5590634504 # number of SoftPFReq MSHR miss cycles
751 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459929430 # number of demand (read+write) MSHR miss cycles
752 system.cpu.dcache.demand_mshr_miss_latency::total 23459929430 # number of demand (read+write) MSHR miss cycles
753 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050563934 # number of overall MSHR miss cycles
754 system.cpu.dcache.overall_mshr_miss_latency::total 29050563934 # number of overall MSHR miss cycles
755 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390328000 # number of ReadReq MSHR uncacheable cycles
756 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390328000 # number of ReadReq MSHR uncacheable cycles
757 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564382000 # number of WriteReq MSHR uncacheable cycles
758 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564382000 # number of WriteReq MSHR uncacheable cycles
759 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954710000 # number of overall MSHR uncacheable cycles
760 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954710000 # number of overall MSHR uncacheable cycles
761 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075927 # mshr miss rate for ReadReq accesses
762 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075927 # mshr miss rate for ReadReq accesses
763 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034352 # mshr miss rate for WriteReq accesses
764 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034352 # mshr miss rate for WriteReq accesses
765 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853656 # mshr miss rate for SoftPFReq accesses
766 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853656 # mshr miss rate for SoftPFReq accesses
767 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059426 # mshr miss rate for demand accesses
768 system.cpu.dcache.demand_mshr_miss_rate::total 0.059426 # mshr miss rate for demand accesses
769 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076713 # mshr miss rate for overall accesses
770 system.cpu.dcache.overall_mshr_miss_rate::total 0.076713 # mshr miss rate for overall accesses
771 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12624.136742 # average ReadReq mshr miss latency
772 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12624.136742 # average ReadReq mshr miss latency
773 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38708.934608 # average WriteReq mshr miss latency
774 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38708.934608 # average WriteReq mshr miss latency
775 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13874.573459 # average SoftPFReq mshr miss latency
776 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13874.573459 # average SoftPFReq mshr miss latency
777 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18608.815838 # average overall mshr miss latency
778 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18608.815838 # average overall mshr miss latency
779 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17462.154406 # average overall mshr miss latency
780 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17462.154406 # average overall mshr miss latency
781 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
782 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
783 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
784 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
785 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
786 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
787 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
788 system.cpu.dtb_walker_cache.tags.replacements 74149 # number of replacements
789 system.cpu.dtb_walker_cache.tags.tagsinuse 15.785870 # Cycle average of tags in use
790 system.cpu.dtb_walker_cache.tags.total_refs 117599 # Total number of references to valid blocks.
791 system.cpu.dtb_walker_cache.tags.sampled_refs 74165 # Sample count of references to valid blocks.
792 system.cpu.dtb_walker_cache.tags.avg_refs 1.585640 # Average number of references to valid blocks.
793 system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit.
794 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785870 # Average occupied blocks per requestor
795 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986617 # Average percentage of cache occupancy
796 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986617 # Average percentage of cache occupancy
797 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
798 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
799 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
800 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
801 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
802 system.cpu.dtb_walker_cache.tags.tag_accesses 460921 # Number of tag accesses
803 system.cpu.dtb_walker_cache.tags.data_accesses 460921 # Number of data accesses
804 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117599 # number of ReadReq hits
805 system.cpu.dtb_walker_cache.ReadReq_hits::total 117599 # number of ReadReq hits
806 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117599 # number of demand (read+write) hits
807 system.cpu.dtb_walker_cache.demand_hits::total 117599 # number of demand (read+write) hits
808 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117599 # number of overall hits
809 system.cpu.dtb_walker_cache.overall_hits::total 117599 # number of overall hits
810 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75241 # number of ReadReq misses
811 system.cpu.dtb_walker_cache.ReadReq_misses::total 75241 # number of ReadReq misses
812 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75241 # number of demand (read+write) misses
813 system.cpu.dtb_walker_cache.demand_misses::total 75241 # number of demand (read+write) misses
814 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75241 # number of overall misses
815 system.cpu.dtb_walker_cache.overall_misses::total 75241 # number of overall misses
816 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935995702 # number of ReadReq miss cycles
817 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935995702 # number of ReadReq miss cycles
818 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935995702 # number of demand (read+write) miss cycles
819 system.cpu.dtb_walker_cache.demand_miss_latency::total 935995702 # number of demand (read+write) miss cycles
820 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935995702 # number of overall miss cycles
821 system.cpu.dtb_walker_cache.overall_miss_latency::total 935995702 # number of overall miss cycles
822 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192840 # number of ReadReq accesses(hits+misses)
823 system.cpu.dtb_walker_cache.ReadReq_accesses::total 192840 # number of ReadReq accesses(hits+misses)
824 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192840 # number of demand (read+write) accesses
825 system.cpu.dtb_walker_cache.demand_accesses::total 192840 # number of demand (read+write) accesses
826 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192840 # number of overall (read+write) accesses
827 system.cpu.dtb_walker_cache.overall_accesses::total 192840 # number of overall (read+write) accesses
828 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.390173 # miss rate for ReadReq accesses
829 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.390173 # miss rate for ReadReq accesses
830 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.390173 # miss rate for demand accesses
831 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.390173 # miss rate for demand accesses
832 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.390173 # miss rate for overall accesses
833 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.390173 # miss rate for overall accesses
834 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12439.968927 # average ReadReq miss latency
835 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12439.968927 # average ReadReq miss latency
836 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency
837 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12439.968927 # average overall miss latency
838 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency
839 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12439.968927 # average overall miss latency
840 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
841 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
842 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
843 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
844 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
845 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
846 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
847 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
848 system.cpu.dtb_walker_cache.writebacks::writebacks 14429 # number of writebacks
849 system.cpu.dtb_walker_cache.writebacks::total 14429 # number of writebacks
850 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75241 # number of ReadReq MSHR misses
851 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75241 # number of ReadReq MSHR misses
852 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75241 # number of demand (read+write) MSHR misses
853 system.cpu.dtb_walker_cache.demand_mshr_misses::total 75241 # number of demand (read+write) MSHR misses
854 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75241 # number of overall MSHR misses
855 system.cpu.dtb_walker_cache.overall_mshr_misses::total 75241 # number of overall MSHR misses
856 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 785378468 # number of ReadReq MSHR miss cycles
857 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 785378468 # number of ReadReq MSHR miss cycles
858 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 785378468 # number of demand (read+write) MSHR miss cycles
859 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 785378468 # number of demand (read+write) MSHR miss cycles
860 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 785378468 # number of overall MSHR miss cycles
861 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 785378468 # number of overall MSHR miss cycles
862 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for ReadReq accesses
863 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.390173 # mshr miss rate for ReadReq accesses
864 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for demand accesses
865 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.390173 # mshr miss rate for demand accesses
866 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for overall accesses
867 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.390173 # mshr miss rate for overall accesses
868 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average ReadReq mshr miss latency
869 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10438.171582 # average ReadReq mshr miss latency
870 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency
871 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency
872 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency
873 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency
874 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
875 system.cpu.icache.tags.replacements 1000738 # number of replacements
876 system.cpu.icache.tags.tagsinuse 509.865289 # Cycle average of tags in use
877 system.cpu.icache.tags.total_refs 8144093 # Total number of references to valid blocks.
878 system.cpu.icache.tags.sampled_refs 1001250 # Sample count of references to valid blocks.
879 system.cpu.icache.tags.avg_refs 8.133926 # Average number of references to valid blocks.
880 system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit.
881 system.cpu.icache.tags.occ_blocks::cpu.inst 509.865289 # Average occupied blocks per requestor
882 system.cpu.icache.tags.occ_percent::cpu.inst 0.995831 # Average percentage of cache occupancy
883 system.cpu.icache.tags.occ_percent::total 0.995831 # Average percentage of cache occupancy
884 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
885 system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
886 system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
887 system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id
888 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
889 system.cpu.icache.tags.tag_accesses 10211253 # Number of tag accesses
890 system.cpu.icache.tags.data_accesses 10211253 # Number of data accesses
891 system.cpu.icache.ReadReq_hits::cpu.inst 8144093 # number of ReadReq hits
892 system.cpu.icache.ReadReq_hits::total 8144093 # number of ReadReq hits
893 system.cpu.icache.demand_hits::cpu.inst 8144093 # number of demand (read+write) hits
894 system.cpu.icache.demand_hits::total 8144093 # number of demand (read+write) hits
895 system.cpu.icache.overall_hits::cpu.inst 8144093 # number of overall hits
896 system.cpu.icache.overall_hits::total 8144093 # number of overall hits
897 system.cpu.icache.ReadReq_misses::cpu.inst 1065861 # number of ReadReq misses
898 system.cpu.icache.ReadReq_misses::total 1065861 # number of ReadReq misses
899 system.cpu.icache.demand_misses::cpu.inst 1065861 # number of demand (read+write) misses
900 system.cpu.icache.demand_misses::total 1065861 # number of demand (read+write) misses
901 system.cpu.icache.overall_misses::cpu.inst 1065861 # number of overall misses
902 system.cpu.icache.overall_misses::total 1065861 # number of overall misses
903 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14781190073 # number of ReadReq miss cycles
904 system.cpu.icache.ReadReq_miss_latency::total 14781190073 # number of ReadReq miss cycles
905 system.cpu.icache.demand_miss_latency::cpu.inst 14781190073 # number of demand (read+write) miss cycles
906 system.cpu.icache.demand_miss_latency::total 14781190073 # number of demand (read+write) miss cycles
907 system.cpu.icache.overall_miss_latency::cpu.inst 14781190073 # number of overall miss cycles
908 system.cpu.icache.overall_miss_latency::total 14781190073 # number of overall miss cycles
909 system.cpu.icache.ReadReq_accesses::cpu.inst 9209954 # number of ReadReq accesses(hits+misses)
910 system.cpu.icache.ReadReq_accesses::total 9209954 # number of ReadReq accesses(hits+misses)
911 system.cpu.icache.demand_accesses::cpu.inst 9209954 # number of demand (read+write) accesses
912 system.cpu.icache.demand_accesses::total 9209954 # number of demand (read+write) accesses
913 system.cpu.icache.overall_accesses::cpu.inst 9209954 # number of overall (read+write) accesses
914 system.cpu.icache.overall_accesses::total 9209954 # number of overall (read+write) accesses
915 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115729 # miss rate for ReadReq accesses
916 system.cpu.icache.ReadReq_miss_rate::total 0.115729 # miss rate for ReadReq accesses
917 system.cpu.icache.demand_miss_rate::cpu.inst 0.115729 # miss rate for demand accesses
918 system.cpu.icache.demand_miss_rate::total 0.115729 # miss rate for demand accesses
919 system.cpu.icache.overall_miss_rate::cpu.inst 0.115729 # miss rate for overall accesses
920 system.cpu.icache.overall_miss_rate::total 0.115729 # miss rate for overall accesses
921 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13867.840247 # average ReadReq miss latency
922 system.cpu.icache.ReadReq_avg_miss_latency::total 13867.840247 # average ReadReq miss latency
923 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency
924 system.cpu.icache.demand_avg_miss_latency::total 13867.840247 # average overall miss latency
925 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency
926 system.cpu.icache.overall_avg_miss_latency::total 13867.840247 # average overall miss latency
927 system.cpu.icache.blocked_cycles::no_mshrs 8856 # number of cycles access was blocked
928 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
929 system.cpu.icache.blocked::no_mshrs 270 # number of cycles access was blocked
930 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
931 system.cpu.icache.avg_blocked_cycles::no_mshrs 32.800000 # average number of cycles each access was blocked
932 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
933 system.cpu.icache.fast_writes 0 # number of fast writes performed
934 system.cpu.icache.cache_copies 0 # number of cache copies performed
935 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 64562 # number of ReadReq MSHR hits
936 system.cpu.icache.ReadReq_mshr_hits::total 64562 # number of ReadReq MSHR hits
937 system.cpu.icache.demand_mshr_hits::cpu.inst 64562 # number of demand (read+write) MSHR hits
938 system.cpu.icache.demand_mshr_hits::total 64562 # number of demand (read+write) MSHR hits
939 system.cpu.icache.overall_mshr_hits::cpu.inst 64562 # number of overall MSHR hits
940 system.cpu.icache.overall_mshr_hits::total 64562 # number of overall MSHR hits
941 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001299 # number of ReadReq MSHR misses
942 system.cpu.icache.ReadReq_mshr_misses::total 1001299 # number of ReadReq MSHR misses
943 system.cpu.icache.demand_mshr_misses::cpu.inst 1001299 # number of demand (read+write) MSHR misses
944 system.cpu.icache.demand_mshr_misses::total 1001299 # number of demand (read+write) MSHR misses
945 system.cpu.icache.overall_mshr_misses::cpu.inst 1001299 # number of overall MSHR misses
946 system.cpu.icache.overall_mshr_misses::total 1001299 # number of overall MSHR misses
947 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12129331538 # number of ReadReq MSHR miss cycles
948 system.cpu.icache.ReadReq_mshr_miss_latency::total 12129331538 # number of ReadReq MSHR miss cycles
949 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12129331538 # number of demand (read+write) MSHR miss cycles
950 system.cpu.icache.demand_mshr_miss_latency::total 12129331538 # number of demand (read+write) MSHR miss cycles
951 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12129331538 # number of overall MSHR miss cycles
952 system.cpu.icache.overall_mshr_miss_latency::total 12129331538 # number of overall MSHR miss cycles
953 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for ReadReq accesses
954 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108719 # mshr miss rate for ReadReq accesses
955 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for demand accesses
956 system.cpu.icache.demand_mshr_miss_rate::total 0.108719 # mshr miss rate for demand accesses
957 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for overall accesses
958 system.cpu.icache.overall_mshr_miss_rate::total 0.108719 # mshr miss rate for overall accesses
959 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.595977 # average ReadReq mshr miss latency
960 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.595977 # average ReadReq mshr miss latency
961 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency
962 system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency
963 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency
964 system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency
965 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
966 system.cpu.itb_walker_cache.tags.replacements 16111 # number of replacements
967 system.cpu.itb_walker_cache.tags.tagsinuse 6.022557 # Cycle average of tags in use
968 system.cpu.itb_walker_cache.tags.total_refs 25852 # Total number of references to valid blocks.
969 system.cpu.itb_walker_cache.tags.sampled_refs 16125 # Sample count of references to valid blocks.
970 system.cpu.itb_walker_cache.tags.avg_refs 1.603225 # Average number of references to valid blocks.
971 system.cpu.itb_walker_cache.tags.warmup_cycle 5103942671000 # Cycle when the warmup percentage was hit.
972 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022557 # Average occupied blocks per requestor
973 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376410 # Average percentage of cache occupancy
974 system.cpu.itb_walker_cache.tags.occ_percent::total 0.376410 # Average percentage of cache occupancy
975 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
976 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
977 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
978 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
979 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
980 system.cpu.itb_walker_cache.tags.tag_accesses 102724 # Number of tag accesses
981 system.cpu.itb_walker_cache.tags.data_accesses 102724 # Number of data accesses
982 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25863 # number of ReadReq hits
983 system.cpu.itb_walker_cache.ReadReq_hits::total 25863 # number of ReadReq hits
984 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
985 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
986 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25865 # number of demand (read+write) hits
987 system.cpu.itb_walker_cache.demand_hits::total 25865 # number of demand (read+write) hits
988 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25865 # number of overall hits
989 system.cpu.itb_walker_cache.overall_hits::total 25865 # number of overall hits
990 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16998 # number of ReadReq misses
991 system.cpu.itb_walker_cache.ReadReq_misses::total 16998 # number of ReadReq misses
992 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16998 # number of demand (read+write) misses
993 system.cpu.itb_walker_cache.demand_misses::total 16998 # number of demand (read+write) misses
994 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16998 # number of overall misses
995 system.cpu.itb_walker_cache.overall_misses::total 16998 # number of overall misses
996 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 202038998 # number of ReadReq miss cycles
997 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 202038998 # number of ReadReq miss cycles
998 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 202038998 # number of demand (read+write) miss cycles
999 system.cpu.itb_walker_cache.demand_miss_latency::total 202038998 # number of demand (read+write) miss cycles
1000 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 202038998 # number of overall miss cycles
1001 system.cpu.itb_walker_cache.overall_miss_latency::total 202038998 # number of overall miss cycles
1002 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42861 # number of ReadReq accesses(hits+misses)
1003 system.cpu.itb_walker_cache.ReadReq_accesses::total 42861 # number of ReadReq accesses(hits+misses)
1004 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1005 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1006 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42863 # number of demand (read+write) accesses
1007 system.cpu.itb_walker_cache.demand_accesses::total 42863 # number of demand (read+write) accesses
1008 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42863 # number of overall (read+write) accesses
1009 system.cpu.itb_walker_cache.overall_accesses::total 42863 # number of overall (read+write) accesses
1010 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.396584 # miss rate for ReadReq accesses
1011 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.396584 # miss rate for ReadReq accesses
1012 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.396566 # miss rate for demand accesses
1013 system.cpu.itb_walker_cache.demand_miss_rate::total 0.396566 # miss rate for demand accesses
1014 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.396566 # miss rate for overall accesses
1015 system.cpu.itb_walker_cache.overall_miss_rate::total 0.396566 # miss rate for overall accesses
1016 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11886.045299 # average ReadReq miss latency
1017 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11886.045299 # average ReadReq miss latency
1018 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency
1019 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11886.045299 # average overall miss latency
1020 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency
1021 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11886.045299 # average overall miss latency
1022 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1023 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1024 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1025 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1026 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1027 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1028 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1029 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1030 system.cpu.itb_walker_cache.writebacks::writebacks 2256 # number of writebacks
1031 system.cpu.itb_walker_cache.writebacks::total 2256 # number of writebacks
1032 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16998 # number of ReadReq MSHR misses
1033 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16998 # number of ReadReq MSHR misses
1034 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16998 # number of demand (read+write) MSHR misses
1035 system.cpu.itb_walker_cache.demand_mshr_misses::total 16998 # number of demand (read+write) MSHR misses
1036 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16998 # number of overall MSHR misses
1037 system.cpu.itb_walker_cache.overall_mshr_misses::total 16998 # number of overall MSHR misses
1038 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 168025032 # number of ReadReq MSHR miss cycles
1039 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 168025032 # number of ReadReq MSHR miss cycles
1040 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 168025032 # number of demand (read+write) MSHR miss cycles
1041 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 168025032 # number of demand (read+write) MSHR miss cycles
1042 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 168025032 # number of overall MSHR miss cycles
1043 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 168025032 # number of overall MSHR miss cycles
1044 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.396584 # mshr miss rate for ReadReq accesses
1045 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.396584 # mshr miss rate for ReadReq accesses
1046 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for demand accesses
1047 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.396566 # mshr miss rate for demand accesses
1048 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for overall accesses
1049 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.396566 # mshr miss rate for overall accesses
1050 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average ReadReq mshr miss latency
1051 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9884.988352 # average ReadReq mshr miss latency
1052 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency
1053 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency
1054 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency
1055 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency
1056 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1057 system.cpu.l2cache.tags.replacements 112974 # number of replacements
1058 system.cpu.l2cache.tags.tagsinuse 64818.744711 # Cycle average of tags in use
1059 system.cpu.l2cache.tags.total_refs 3837920 # Total number of references to valid blocks.
1060 system.cpu.l2cache.tags.sampled_refs 177018 # Sample count of references to valid blocks.
1061 system.cpu.l2cache.tags.avg_refs 21.680959 # Average number of references to valid blocks.
1062 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1063 system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor
1064 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.441797 # Average occupied blocks per requestor
1065 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125760 # Average occupied blocks per requestor
1066 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor
1067 system.cpu.l2cache.tags.occ_blocks::cpu.data 11145.935958 # Average occupied blocks per requestor
1068 system.cpu.l2cache.tags.occ_percent::writebacks 0.768860 # Average percentage of cache occupancy
1069 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy
1070 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1071 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049854 # Average percentage of cache occupancy
1072 system.cpu.l2cache.tags.occ_percent::cpu.data 0.170073 # Average percentage of cache occupancy
1073 system.cpu.l2cache.tags.occ_percent::total 0.989056 # Average percentage of cache occupancy
1074 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64044 # Occupied blocks per task id
1075 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
1076 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 598 # Occupied blocks per task id
1077 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3343 # Occupied blocks per task id
1078 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7275 # Occupied blocks per task id
1079 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52773 # Occupied blocks per task id
1080 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977234 # Percentage of cache occupancy per task id
1081 system.cpu.l2cache.tags.tag_accesses 35081259 # Number of tag accesses
1082 system.cpu.l2cache.tags.data_accesses 35081259 # Number of data accesses
1083 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69593 # number of ReadReq hits
1084 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 14758 # number of ReadReq hits
1085 system.cpu.l2cache.ReadReq_hits::cpu.inst 984803 # number of ReadReq hits
1086 system.cpu.l2cache.ReadReq_hits::cpu.data 1337710 # number of ReadReq hits
1087 system.cpu.l2cache.ReadReq_hits::total 2406864 # number of ReadReq hits
1088 system.cpu.l2cache.Writeback_hits::writebacks 1577834 # number of Writeback hits
1089 system.cpu.l2cache.Writeback_hits::total 1577834 # number of Writeback hits
1090 system.cpu.l2cache.UpgradeReq_hits::cpu.data 300 # number of UpgradeReq hits
1091 system.cpu.l2cache.UpgradeReq_hits::total 300 # number of UpgradeReq hits
1092 system.cpu.l2cache.ReadExReq_hits::cpu.data 153385 # number of ReadExReq hits
1093 system.cpu.l2cache.ReadExReq_hits::total 153385 # number of ReadExReq hits
1094 system.cpu.l2cache.demand_hits::cpu.dtb.walker 69593 # number of demand (read+write) hits
1095 system.cpu.l2cache.demand_hits::cpu.itb.walker 14758 # number of demand (read+write) hits
1096 system.cpu.l2cache.demand_hits::cpu.inst 984803 # number of demand (read+write) hits
1097 system.cpu.l2cache.demand_hits::cpu.data 1491095 # number of demand (read+write) hits
1098 system.cpu.l2cache.demand_hits::total 2560249 # number of demand (read+write) hits
1099 system.cpu.l2cache.overall_hits::cpu.dtb.walker 69593 # number of overall hits
1100 system.cpu.l2cache.overall_hits::cpu.itb.walker 14758 # number of overall hits
1101 system.cpu.l2cache.overall_hits::cpu.inst 984803 # number of overall hits
1102 system.cpu.l2cache.overall_hits::cpu.data 1491095 # number of overall hits
1103 system.cpu.l2cache.overall_hits::total 2560249 # number of overall hits
1104 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 68 # number of ReadReq misses
1105 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
1106 system.cpu.l2cache.ReadReq_misses::cpu.inst 16393 # number of ReadReq misses
1107 system.cpu.l2cache.ReadReq_misses::cpu.data 35895 # number of ReadReq misses
1108 system.cpu.l2cache.ReadReq_misses::total 52361 # number of ReadReq misses
1109 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
1110 system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
1111 system.cpu.l2cache.ReadExReq_misses::cpu.data 133756 # number of ReadExReq misses
1112 system.cpu.l2cache.ReadExReq_misses::total 133756 # number of ReadExReq misses
1113 system.cpu.l2cache.demand_misses::cpu.dtb.walker 68 # number of demand (read+write) misses
1114 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1115 system.cpu.l2cache.demand_misses::cpu.inst 16393 # number of demand (read+write) misses
1116 system.cpu.l2cache.demand_misses::cpu.data 169651 # number of demand (read+write) misses
1117 system.cpu.l2cache.demand_misses::total 186117 # number of demand (read+write) misses
1118 system.cpu.l2cache.overall_misses::cpu.dtb.walker 68 # number of overall misses
1119 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1120 system.cpu.l2cache.overall_misses::cpu.inst 16393 # number of overall misses
1121 system.cpu.l2cache.overall_misses::cpu.data 169651 # number of overall misses
1122 system.cpu.l2cache.overall_misses::total 186117 # number of overall misses
1123 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6414250 # number of ReadReq miss cycles
1124 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 407500 # number of ReadReq miss cycles
1125 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1255247500 # number of ReadReq miss cycles
1126 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2834689998 # number of ReadReq miss cycles
1127 system.cpu.l2cache.ReadReq_miss_latency::total 4096759248 # number of ReadReq miss cycles
1128 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17266314 # number of UpgradeReq miss cycles
1129 system.cpu.l2cache.UpgradeReq_miss_latency::total 17266314 # number of UpgradeReq miss cycles
1130 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9330791213 # number of ReadExReq miss cycles
1131 system.cpu.l2cache.ReadExReq_miss_latency::total 9330791213 # number of ReadExReq miss cycles
1132 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6414250 # number of demand (read+write) miss cycles
1133 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 407500 # number of demand (read+write) miss cycles
1134 system.cpu.l2cache.demand_miss_latency::cpu.inst 1255247500 # number of demand (read+write) miss cycles
1135 system.cpu.l2cache.demand_miss_latency::cpu.data 12165481211 # number of demand (read+write) miss cycles
1136 system.cpu.l2cache.demand_miss_latency::total 13427550461 # number of demand (read+write) miss cycles
1137 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6414250 # number of overall miss cycles
1138 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 407500 # number of overall miss cycles
1139 system.cpu.l2cache.overall_miss_latency::cpu.inst 1255247500 # number of overall miss cycles
1140 system.cpu.l2cache.overall_miss_latency::cpu.data 12165481211 # number of overall miss cycles
1141 system.cpu.l2cache.overall_miss_latency::total 13427550461 # number of overall miss cycles
1142 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69661 # number of ReadReq accesses(hits+misses)
1143 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 14763 # number of ReadReq accesses(hits+misses)
1144 system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001196 # number of ReadReq accesses(hits+misses)
1145 system.cpu.l2cache.ReadReq_accesses::cpu.data 1373605 # number of ReadReq accesses(hits+misses)
1146 system.cpu.l2cache.ReadReq_accesses::total 2459225 # number of ReadReq accesses(hits+misses)
1147 system.cpu.l2cache.Writeback_accesses::writebacks 1577834 # number of Writeback accesses(hits+misses)
1148 system.cpu.l2cache.Writeback_accesses::total 1577834 # number of Writeback accesses(hits+misses)
1149 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1744 # number of UpgradeReq accesses(hits+misses)
1150 system.cpu.l2cache.UpgradeReq_accesses::total 1744 # number of UpgradeReq accesses(hits+misses)
1151 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287141 # number of ReadExReq accesses(hits+misses)
1152 system.cpu.l2cache.ReadExReq_accesses::total 287141 # number of ReadExReq accesses(hits+misses)
1153 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69661 # number of demand (read+write) accesses
1154 system.cpu.l2cache.demand_accesses::cpu.itb.walker 14763 # number of demand (read+write) accesses
1155 system.cpu.l2cache.demand_accesses::cpu.inst 1001196 # number of demand (read+write) accesses
1156 system.cpu.l2cache.demand_accesses::cpu.data 1660746 # number of demand (read+write) accesses
1157 system.cpu.l2cache.demand_accesses::total 2746366 # number of demand (read+write) accesses
1158 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69661 # number of overall (read+write) accesses
1159 system.cpu.l2cache.overall_accesses::cpu.itb.walker 14763 # number of overall (read+write) accesses
1160 system.cpu.l2cache.overall_accesses::cpu.inst 1001196 # number of overall (read+write) accesses
1161 system.cpu.l2cache.overall_accesses::cpu.data 1660746 # number of overall (read+write) accesses
1162 system.cpu.l2cache.overall_accesses::total 2746366 # number of overall (read+write) accesses
1163 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000976 # miss rate for ReadReq accesses
1164 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000339 # miss rate for ReadReq accesses
1165 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016373 # miss rate for ReadReq accesses
1166 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026132 # miss rate for ReadReq accesses
1167 system.cpu.l2cache.ReadReq_miss_rate::total 0.021292 # miss rate for ReadReq accesses
1168 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827982 # miss rate for UpgradeReq accesses
1169 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827982 # miss rate for UpgradeReq accesses
1170 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.465820 # miss rate for ReadExReq accesses
1171 system.cpu.l2cache.ReadExReq_miss_rate::total 0.465820 # miss rate for ReadExReq accesses
1172 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000976 # miss rate for demand accesses
1173 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000339 # miss rate for demand accesses
1174 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016373 # miss rate for demand accesses
1175 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102153 # miss rate for demand accesses
1176 system.cpu.l2cache.demand_miss_rate::total 0.067768 # miss rate for demand accesses
1177 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000976 # miss rate for overall accesses
1178 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000339 # miss rate for overall accesses
1179 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016373 # miss rate for overall accesses
1180 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102153 # miss rate for overall accesses
1181 system.cpu.l2cache.overall_miss_rate::total 0.067768 # miss rate for overall accesses
1182 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 94327.205882 # average ReadReq miss latency
1183 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81500 # average ReadReq miss latency
1184 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.164948 # average ReadReq miss latency
1185 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78971.723025 # average ReadReq miss latency
1186 system.cpu.l2cache.ReadReq_avg_miss_latency::total 78240.660950 # average ReadReq miss latency
1187 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11957.281163 # average UpgradeReq miss latency
1188 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11957.281163 # average UpgradeReq miss latency
1189 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69759.795546 # average ReadExReq miss latency
1190 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69759.795546 # average ReadExReq miss latency
1191 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 94327.205882 # average overall miss latency
1192 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81500 # average overall miss latency
1193 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.164948 # average overall miss latency
1194 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71708.868271 # average overall miss latency
1195 system.cpu.l2cache.demand_avg_miss_latency::total 72145.749507 # average overall miss latency
1196 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 94327.205882 # average overall miss latency
1197 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81500 # average overall miss latency
1198 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.164948 # average overall miss latency
1199 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71708.868271 # average overall miss latency
1200 system.cpu.l2cache.overall_avg_miss_latency::total 72145.749507 # average overall miss latency
1201 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1202 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1203 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1204 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1205 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1206 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1207 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1208 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1209 system.cpu.l2cache.writebacks::writebacks 103249 # number of writebacks
1210 system.cpu.l2cache.writebacks::total 103249 # number of writebacks
1211 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1212 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
1213 system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1214 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1215 system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
1216 system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1217 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1218 system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
1219 system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1220 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 68 # number of ReadReq MSHR misses
1221 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
1222 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16392 # number of ReadReq MSHR misses
1223 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35893 # number of ReadReq MSHR misses
1224 system.cpu.l2cache.ReadReq_mshr_misses::total 52358 # number of ReadReq MSHR misses
1225 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
1226 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
1227 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133756 # number of ReadExReq MSHR misses
1228 system.cpu.l2cache.ReadExReq_mshr_misses::total 133756 # number of ReadExReq MSHR misses
1229 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 68 # number of demand (read+write) MSHR misses
1230 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1231 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16392 # number of demand (read+write) MSHR misses
1232 system.cpu.l2cache.demand_mshr_misses::cpu.data 169649 # number of demand (read+write) MSHR misses
1233 system.cpu.l2cache.demand_mshr_misses::total 186114 # number of demand (read+write) MSHR misses
1234 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 68 # number of overall MSHR misses
1235 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1236 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16392 # number of overall MSHR misses
1237 system.cpu.l2cache.overall_mshr_misses::cpu.data 169649 # number of overall MSHR misses
1238 system.cpu.l2cache.overall_mshr_misses::total 186114 # number of overall MSHR misses
1239 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5576250 # number of ReadReq MSHR miss cycles
1240 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 344500 # number of ReadReq MSHR miss cycles
1241 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049607750 # number of ReadReq MSHR miss cycles
1242 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2389031498 # number of ReadReq MSHR miss cycles
1243 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3444559998 # number of ReadReq MSHR miss cycles
1244 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15363423 # number of UpgradeReq MSHR miss cycles
1245 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15363423 # number of UpgradeReq MSHR miss cycles
1246 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7651301287 # number of ReadExReq MSHR miss cycles
1247 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7651301287 # number of ReadExReq MSHR miss cycles
1248 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5576250 # number of demand (read+write) MSHR miss cycles
1249 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 344500 # number of demand (read+write) MSHR miss cycles
1250 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049607750 # number of demand (read+write) MSHR miss cycles
1251 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10040332785 # number of demand (read+write) MSHR miss cycles
1252 system.cpu.l2cache.demand_mshr_miss_latency::total 11095861285 # number of demand (read+write) MSHR miss cycles
1253 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5576250 # number of overall MSHR miss cycles
1254 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 344500 # number of overall MSHR miss cycles
1255 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049607750 # number of overall MSHR miss cycles
1256 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10040332785 # number of overall MSHR miss cycles
1257 system.cpu.l2cache.overall_mshr_miss_latency::total 11095861285 # number of overall MSHR miss cycles
1258 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275596500 # number of ReadReq MSHR uncacheable cycles
1259 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275596500 # number of ReadReq MSHR uncacheable cycles
1260 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397352000 # number of WriteReq MSHR uncacheable cycles
1261 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397352000 # number of WriteReq MSHR uncacheable cycles
1262 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672948500 # number of overall MSHR uncacheable cycles
1263 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672948500 # number of overall MSHR uncacheable cycles
1264 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for ReadReq accesses
1265 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for ReadReq accesses
1266 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for ReadReq accesses
1267 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026131 # mshr miss rate for ReadReq accesses
1268 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021290 # mshr miss rate for ReadReq accesses
1269 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827982 # mshr miss rate for UpgradeReq accesses
1270 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827982 # mshr miss rate for UpgradeReq accesses
1271 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465820 # mshr miss rate for ReadExReq accesses
1272 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465820 # mshr miss rate for ReadExReq accesses
1273 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for demand accesses
1274 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for demand accesses
1275 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for demand accesses
1276 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for demand accesses
1277 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067767 # mshr miss rate for demand accesses
1278 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for overall accesses
1279 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for overall accesses
1280 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for overall accesses
1281 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for overall accesses
1282 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067767 # mshr miss rate for overall accesses
1283 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average ReadReq mshr miss latency
1284 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68900 # average ReadReq mshr miss latency
1285 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64031.707540 # average ReadReq mshr miss latency
1286 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66559.816622 # average ReadReq mshr miss latency
1287 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65788.609152 # average ReadReq mshr miss latency
1288 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10639.489612 # average UpgradeReq mshr miss latency
1289 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10639.489612 # average UpgradeReq mshr miss latency
1290 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57203.424796 # average ReadExReq mshr miss latency
1291 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57203.424796 # average ReadExReq mshr miss latency
1292 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency
1293 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency
1294 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency
1295 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency
1296 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency
1297 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency
1298 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency
1299 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency
1300 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency
1301 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency
1302 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1303 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1304 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1305 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1306 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1307 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1308 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1309 system.cpu.toL2Bus.trans_dist::ReadReq 3078150 # Transaction distribution
1310 system.cpu.toL2Bus.trans_dist::ReadResp 3077612 # Transaction distribution
1311 system.cpu.toL2Bus.trans_dist::WriteReq 13891 # Transaction distribution
1312 system.cpu.toL2Bus.trans_dist::WriteResp 13891 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::Writeback 1577834 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1315 system.cpu.toL2Bus.trans_dist::UpgradeReq 2215 # Transaction distribution
1316 system.cpu.toL2Bus.trans_dist::UpgradeResp 2215 # Transaction distribution
1317 system.cpu.toL2Bus.trans_dist::ReadExReq 287149 # Transaction distribution
1318 system.cpu.toL2Bus.trans_dist::ReadExResp 287149 # Transaction distribution
1319 system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
1320 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002495 # Packet count per connected master and slave (bytes)
1321 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6134281 # Packet count per connected master and slave (bytes)
1322 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34017 # Packet count per connected master and slave (bytes)
1323 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159331 # Packet count per connected master and slave (bytes)
1324 system.cpu.toL2Bus.pkt_count::total 8330124 # Packet count per connected master and slave (bytes)
1325 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64076544 # Cumulative packet size per connected master and slave (bytes)
1326 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208017731 # Cumulative packet size per connected master and slave (bytes)
1327 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1089216 # Cumulative packet size per connected master and slave (bytes)
1328 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5381760 # Cumulative packet size per connected master and slave (bytes)
1329 system.cpu.toL2Bus.pkt_size::total 278565251 # Cumulative packet size per connected master and slave (bytes)
1330 system.cpu.toL2Bus.snoops 57093 # Total snoops (count)
1331 system.cpu.toL2Bus.snoop_fanout::samples 4382652 # Request fanout histogram
1332 system.cpu.toL2Bus.snoop_fanout::mean 3.010869 # Request fanout histogram
1333 system.cpu.toL2Bus.snoop_fanout::stdev 0.103688 # Request fanout histogram
1334 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1335 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1336 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1337 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1338 system.cpu.toL2Bus.snoop_fanout::3 4335015 98.91% 98.91% # Request fanout histogram
1339 system.cpu.toL2Bus.snoop_fanout::4 47637 1.09% 100.00% # Request fanout histogram
1340 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1341 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1342 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1343 system.cpu.toL2Bus.snoop_fanout::total 4382652 # Request fanout histogram
1344 system.cpu.toL2Bus.reqLayer0.occupancy 4064000382 # Layer occupancy (ticks)
1345 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1346 system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks)
1347 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1348 system.cpu.toL2Bus.respLayer0.occupancy 1506120456 # Layer occupancy (ticks)
1349 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1350 system.cpu.toL2Bus.respLayer1.occupancy 3144694054 # Layer occupancy (ticks)
1351 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1352 system.cpu.toL2Bus.respLayer2.occupancy 25505983 # Layer occupancy (ticks)
1353 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1354 system.cpu.toL2Bus.respLayer3.occupancy 112929117 # Layer occupancy (ticks)
1355 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1356 system.iobus.trans_dist::ReadReq 225688 # Transaction distribution
1357 system.iobus.trans_dist::ReadResp 225688 # Transaction distribution
1358 system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
1359 system.iobus.trans_dist::WriteResp 11001 # Transaction distribution
1360 system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1361 system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
1362 system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
1363 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1364 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1365 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1366 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1367 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1368 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95274 # Packet count per connected master and slave (bytes)
1383 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95274 # Packet count per connected master and slave (bytes)
1384 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
1385 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
1386 system.iobus.pkt_count::total 570106 # Packet count per connected master and slave (bytes)
1387 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1388 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1389 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1390 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1391 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027880 # Cumulative packet size per connected master and slave (bytes)
1407 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027880 # Cumulative packet size per connected master and slave (bytes)
1408 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
1409 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
1410 system.iobus.pkt_size::total 3276514 # Cumulative packet size per connected master and slave (bytes)
1411 system.iobus.reqLayer0.occupancy 3918684 # Layer occupancy (ticks)
1412 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1413 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1414 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1415 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1416 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1417 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1418 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1419 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1420 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1421 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1422 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1423 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1424 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1425 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1426 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1427 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1428 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1429 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
1430 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1431 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1432 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1433 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1434 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1435 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1436 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1437 system.iobus.reqLayer14.occupancy 20719000 # Layer occupancy (ticks)
1438 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1439 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1440 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1441 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1442 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1443 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1444 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1445 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1446 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1447 system.iobus.reqLayer19.occupancy 448342458 # Layer occupancy (ticks)
1448 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1449 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1450 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1451 system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
1452 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1453 system.iobus.respLayer1.occupancy 52374503 # Layer occupancy (ticks)
1454 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1455 system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
1456 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1457 system.iocache.tags.replacements 47582 # number of replacements
1458 system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use
1459 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1460 system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks.
1461 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1462 system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit.
1463 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor
1464 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy
1465 system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy
1466 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1467 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1468 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1469 system.iocache.tags.tag_accesses 428733 # Number of tag accesses
1470 system.iocache.tags.data_accesses 428733 # Number of data accesses
1471 system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses
1472 system.iocache.ReadReq_misses::total 917 # number of ReadReq misses
1473 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1474 system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1475 system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses
1476 system.iocache.demand_misses::total 917 # number of demand (read+write) misses
1477 system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses
1478 system.iocache.overall_misses::total 917 # number of overall misses
1479 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles
1480 system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles
1481 system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles
1482 system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles
1483 system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles
1484 system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles
1485 system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles
1486 system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles
1487 system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses)
1488 system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses)
1489 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1490 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1491 system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses
1492 system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses
1493 system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses
1494 system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses
1495 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1496 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1497 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1498 system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1499 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1500 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1501 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1502 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1503 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency
1504 system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency
1505 system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency
1506 system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency
1507 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency
1508 system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency
1509 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency
1510 system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency
1511 system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked
1512 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1513 system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked
1514 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1515 system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked
1516 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1517 system.iocache.fast_writes 0 # number of fast writes performed
1518 system.iocache.cache_copies 0 # number of cache copies performed
1519 system.iocache.writebacks::writebacks 46667 # number of writebacks
1520 system.iocache.writebacks::total 46667 # number of writebacks
1521 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses
1522 system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses
1523 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1524 system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1525 system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses
1526 system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses
1527 system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses
1528 system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses
1529 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles
1530 system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles
1531 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles
1532 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles
1533 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles
1534 system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles
1535 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles
1536 system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles
1537 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1538 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1539 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1540 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1541 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1542 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1543 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1544 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1545 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency
1546 system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency
1547 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency
1548 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency
1549 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency
1550 system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency
1551 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency
1552 system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency
1553 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1554 system.membus.trans_dist::ReadReq 662691 # Transaction distribution
1555 system.membus.trans_dist::ReadResp 662685 # Transaction distribution
1556 system.membus.trans_dist::WriteReq 13891 # Transaction distribution
1557 system.membus.trans_dist::WriteResp 13891 # Transaction distribution
1558 system.membus.trans_dist::Writeback 149916 # Transaction distribution
1559 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1560 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1561 system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution
1562 system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution
1563 system.membus.trans_dist::ReadExReq 133471 # Transaction distribution
1564 system.membus.trans_dist::ReadExResp 133469 # Transaction distribution
1565 system.membus.trans_dist::MessageReq 1644 # Transaction distribution
1566 system.membus.trans_dist::MessageResp 1644 # Transaction distribution
1567 system.membus.trans_dist::BadAddressError 6 # Transaction distribution
1568 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
1569 system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
1570 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
1571 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
1572 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes)
1573 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
1574 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes)
1575 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes)
1576 system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes)
1577 system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes)
1578 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
1579 system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
1580 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
1581 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
1582 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes)
1583 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes)
1584 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1585 system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1586 system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes)
1587 system.membus.snoops 1626 # Total snoops (count)
1588 system.membus.snoop_fanout::samples 385584 # Request fanout histogram
1589 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1590 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1591 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1592 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1593 system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram
1594 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1595 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1596 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1597 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1598 system.membus.snoop_fanout::total 385584 # Request fanout histogram
1599 system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks)
1600 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1601 system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks)
1602 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1603 system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
1604 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1605 system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks)
1606 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1607 system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks)
1608 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1609 system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
1610 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1611 system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks)
1612 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
1613 system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks)
1614 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1615 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1616 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1617 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1618 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1619 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1620 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1621 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1622 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1623 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1624 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1625 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1626 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1627 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1628 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1630 ---------- End Simulation Statistics ----------
projects / gem5.git / blob