2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.133933 # Number of seconds simulated
4 sim_ticks 5133933067000 # Number of ticks simulated
5 final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 186687 # Simulator instruction rate (inst/s)
8 host_op_rate 369023 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2350538489 # Simulator tick rate (ticks/s)
10 host_mem_usage 736008 # Number of bytes of host memory used
11 host_seconds 2184.15 # Real time elapsed on the host
12 sim_insts 407751929 # Number of instructions simulated
13 sim_ops 806002693 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory
26 system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory
30 system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory
34 system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 222145 # Number of read requests accepted
52 system.physmem.writeReqs 148323 # Number of write requests accepted
53 system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 14970 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 13960 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 14769 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 13764 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 13644 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 13392 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 13407 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 13589 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 13408 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 13258 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 13821 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 13878 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 14332 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 14527 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 13749 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 13589 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 10370 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 9405 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 9871 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 9165 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 9017 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 8953 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 8740 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 8992 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 8721 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 8568 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 9309 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 9216 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 9686 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 9800 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 9415 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 9091 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
97 system.physmem.totGap 5133933013500 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 222145 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 148323 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see
176 system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation
177 system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation
178 system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation
179 system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation
180 system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation
181 system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation
182 system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation
183 system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation
184 system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation
185 system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation
186 system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation
187 system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation
188 system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation
189 system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation
190 system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation
191 system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation
192 system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation
193 system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation
194 system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation
195 system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation
196 system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation
197 system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation
198 system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation
199 system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation
200 system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation
201 system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation
202 system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation
203 system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation
204 system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation
205 system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation
206 system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation
207 system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation
208 system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation
222 system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation
223 system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation
224 system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation
225 system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation
226 system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation
227 system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation
228 system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation
229 system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation
230 system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation
231 system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation
232 system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::3456-3459 25 0.04% 98.73% # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.74% # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.74% # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.75% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::3712-3715 26 0.04% 98.79% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::3776-3779 10 0.01% 98.80% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::3840-3843 5 0.01% 98.81% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::3904-3907 9 0.01% 98.82% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.86% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.87% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::4096-4099 15 0.02% 98.89% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::4160-4163 3 0.00% 98.90% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::4224-4227 27 0.04% 98.94% # Bytes accessed per row activation
246 system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation
247 system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.94% # Bytes accessed per row activation
248 system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.95% # Bytes accessed per row activation
249 system.physmem.bytesPerActivate::4480-4483 23 0.03% 98.98% # Bytes accessed per row activation
250 system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.98% # Bytes accessed per row activation
251 system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation
252 system.physmem.bytesPerActivate::4672-4675 5 0.01% 98.99% # Bytes accessed per row activation
253 system.physmem.bytesPerActivate::4736-4739 25 0.04% 99.03% # Bytes accessed per row activation
254 system.physmem.bytesPerActivate::4800-4803 4 0.01% 99.04% # Bytes accessed per row activation
255 system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation
256 system.physmem.bytesPerActivate::4992-4995 22 0.03% 99.07% # Bytes accessed per row activation
257 system.physmem.bytesPerActivate::5056-5059 2 0.00% 99.07% # Bytes accessed per row activation
258 system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation
259 system.physmem.bytesPerActivate::5184-5187 4 0.01% 99.08% # Bytes accessed per row activation
260 system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation
261 system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation
262 system.physmem.bytesPerActivate::5440-5443 2 0.00% 99.12% # Bytes accessed per row activation
263 system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation
264 system.physmem.bytesPerActivate::5568-5571 4 0.01% 99.16% # Bytes accessed per row activation
265 system.physmem.bytesPerActivate::5696-5699 3 0.00% 99.17% # Bytes accessed per row activation
266 system.physmem.bytesPerActivate::5760-5763 24 0.03% 99.20% # Bytes accessed per row activation
267 system.physmem.bytesPerActivate::5824-5827 4 0.01% 99.21% # Bytes accessed per row activation
268 system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.21% # Bytes accessed per row activation
269 system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.21% # Bytes accessed per row activation
270 system.physmem.bytesPerActivate::6016-6019 24 0.03% 99.25% # Bytes accessed per row activation
271 system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.25% # Bytes accessed per row activation
272 system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.25% # Bytes accessed per row activation
273 system.physmem.bytesPerActivate::6208-6211 3 0.00% 99.25% # Bytes accessed per row activation
274 system.physmem.bytesPerActivate::6272-6275 24 0.03% 99.29% # Bytes accessed per row activation
275 system.physmem.bytesPerActivate::6336-6339 3 0.00% 99.29% # Bytes accessed per row activation
276 system.physmem.bytesPerActivate::6400-6403 4 0.01% 99.30% # Bytes accessed per row activation
277 system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.30% # Bytes accessed per row activation
278 system.physmem.bytesPerActivate::6528-6531 23 0.03% 99.33% # Bytes accessed per row activation
279 system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.34% # Bytes accessed per row activation
280 system.physmem.bytesPerActivate::6656-6659 75 0.11% 99.45% # Bytes accessed per row activation
281 system.physmem.bytesPerActivate::6720-6723 3 0.00% 99.45% # Bytes accessed per row activation
282 system.physmem.bytesPerActivate::6784-6787 2 0.00% 99.45% # Bytes accessed per row activation
283 system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.46% # Bytes accessed per row activation
284 system.physmem.bytesPerActivate::6912-6915 5 0.01% 99.47% # Bytes accessed per row activation
285 system.physmem.bytesPerActivate::6976-6979 3 0.00% 99.47% # Bytes accessed per row activation
286 system.physmem.bytesPerActivate::7040-7043 9 0.01% 99.49% # Bytes accessed per row activation
287 system.physmem.bytesPerActivate::7104-7107 2 0.00% 99.49% # Bytes accessed per row activation
288 system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.51% # Bytes accessed per row activation
289 system.physmem.bytesPerActivate::7232-7235 2 0.00% 99.51% # Bytes accessed per row activation
290 system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.51% # Bytes accessed per row activation
291 system.physmem.bytesPerActivate::7488-7491 2 0.00% 99.51% # Bytes accessed per row activation
292 system.physmem.bytesPerActivate::7552-7555 2 0.00% 99.52% # Bytes accessed per row activation
293 system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.52% # Bytes accessed per row activation
294 system.physmem.bytesPerActivate::7680-7683 1 0.00% 99.52% # Bytes accessed per row activation
295 system.physmem.bytesPerActivate::7744-7747 2 0.00% 99.52% # Bytes accessed per row activation
296 system.physmem.bytesPerActivate::7808-7811 3 0.00% 99.53% # Bytes accessed per row activation
297 system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.53% # Bytes accessed per row activation
298 system.physmem.bytesPerActivate::7936-7939 3 0.00% 99.54% # Bytes accessed per row activation
299 system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.54% # Bytes accessed per row activation
300 system.physmem.bytesPerActivate::8064-8067 5 0.01% 99.55% # Bytes accessed per row activation
301 system.physmem.bytesPerActivate::8128-8131 3 0.00% 99.55% # Bytes accessed per row activation
302 system.physmem.bytesPerActivate::8192-8195 15 0.02% 99.57% # Bytes accessed per row activation
303 system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.57% # Bytes accessed per row activation
304 system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.58% # Bytes accessed per row activation
305 system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.58% # Bytes accessed per row activation
306 system.physmem.bytesPerActivate::8512-8515 5 0.01% 99.58% # Bytes accessed per row activation
307 system.physmem.bytesPerActivate::8640-8643 2 0.00% 99.59% # Bytes accessed per row activation
308 system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.59% # Bytes accessed per row activation
309 system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.59% # Bytes accessed per row activation
310 system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.59% # Bytes accessed per row activation
311 system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.60% # Bytes accessed per row activation
312 system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.60% # Bytes accessed per row activation
313 system.physmem.bytesPerActivate::9152-9155 4 0.01% 99.60% # Bytes accessed per row activation
314 system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.61% # Bytes accessed per row activation
315 system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.61% # Bytes accessed per row activation
316 system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.61% # Bytes accessed per row activation
317 system.physmem.bytesPerActivate::9536-9539 4 0.01% 99.62% # Bytes accessed per row activation
318 system.physmem.bytesPerActivate::9600-9603 4 0.01% 99.62% # Bytes accessed per row activation
319 system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.63% # Bytes accessed per row activation
320 system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.63% # Bytes accessed per row activation
321 system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.63% # Bytes accessed per row activation
322 system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.64% # Bytes accessed per row activation
323 system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.64% # Bytes accessed per row activation
324 system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.65% # Bytes accessed per row activation
325 system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation
326 system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.65% # Bytes accessed per row activation
327 system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation
328 system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.65% # Bytes accessed per row activation
329 system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.65% # Bytes accessed per row activation
330 system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation
331 system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.66% # Bytes accessed per row activation
332 system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.66% # Bytes accessed per row activation
333 system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.66% # Bytes accessed per row activation
334 system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.66% # Bytes accessed per row activation
335 system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.66% # Bytes accessed per row activation
336 system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.66% # Bytes accessed per row activation
337 system.physmem.bytesPerActivate::11392-11395 3 0.00% 99.67% # Bytes accessed per row activation
338 system.physmem.bytesPerActivate::11520-11523 3 0.00% 99.67% # Bytes accessed per row activation
339 system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.68% # Bytes accessed per row activation
340 system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.68% # Bytes accessed per row activation
341 system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation
342 system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation
343 system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation
344 system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation
345 system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation
346 system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation
347 system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation
348 system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation
349 system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation
350 system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation
351 system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation
352 system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation
353 system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation
354 system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation
355 system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation
356 system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation
357 system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation
358 system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation
359 system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation
360 system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation
361 system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation
362 system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation
363 system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation
364 system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation
365 system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation
366 system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation
367 system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation
368 system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation
369 system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation
370 system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation
371 system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation
372 system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation
373 system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation
374 system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation
375 system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation
376 system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation
377 system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation
378 system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation
379 system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation
380 system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation
381 system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation
382 system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation
383 system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation
384 system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation
385 system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation
386 system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation
387 system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation
388 system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation
389 system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation
390 system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation
391 system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation
392 system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation
393 system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation
394 system.physmem.totQLat 5103462500 # Total ticks spent queuing
395 system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM
396 system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers
397 system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks
398 system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst
399 system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst
400 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
401 system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst
402 system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s
403 system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
404 system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s
405 system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
406 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
407 system.physmem.busUtil 0.04 # Data bus utilization in percentage
408 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
409 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
410 system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
411 system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing
412 system.physmem.readRowHits 193293 # Number of row buffer hits during reads
413 system.physmem.writeRowHits 108329 # Number of row buffer hits during writes
414 system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
415 system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes
416 system.physmem.avgGap 13857966.18 # Average gap between requests
417 system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
418 system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state
419 system.membus.throughput 5095991 # Throughput (bytes/s)
420 system.membus.trans_dist::ReadReq 662317 # Transaction distribution
421 system.membus.trans_dist::ReadResp 662311 # Transaction distribution
422 system.membus.trans_dist::WriteReq 13762 # Transaction distribution
423 system.membus.trans_dist::WriteResp 13762 # Transaction distribution
424 system.membus.trans_dist::Writeback 148323 # Transaction distribution
425 system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution
426 system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution
427 system.membus.trans_dist::ReadExReq 179351 # Transaction distribution
428 system.membus.trans_dist::ReadExResp 179346 # Transaction distribution
429 system.membus.trans_dist::MessageReq 1642 # Transaction distribution
430 system.membus.trans_dist::MessageResp 1642 # Transaction distribution
431 system.membus.trans_dist::BadAddressError 6 # Transaction distribution
432 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
433 system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
434 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes)
435 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
436 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes)
437 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
438 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes)
439 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes)
440 system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes)
441 system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes)
442 system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
443 system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
444 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes)
445 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
446 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes)
447 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes)
448 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes)
449 system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes)
450 system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes)
451 system.membus.data_through_bus 25508463 # Total data (bytes)
452 system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes)
453 system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks)
454 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
455 system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks)
456 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
457 system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
458 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
459 system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks)
460 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
461 system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
462 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
463 system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
464 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
465 system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks)
466 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
467 system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks)
468 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
469 system.iocache.tags.replacements 47576 # number of replacements
470 system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use
471 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
472 system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks.
473 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
474 system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit.
475 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor
476 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy
477 system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy
478 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
479 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
480 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
481 system.iocache.tags.tag_accesses 428679 # Number of tag accesses
482 system.iocache.tags.data_accesses 428679 # Number of data accesses
483 system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
484 system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
485 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
486 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
487 system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
488 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
489 system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
490 system.iocache.overall_misses::total 47631 # number of overall misses
491 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles
492 system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles
493 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles
494 system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles
495 system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles
496 system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles
497 system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles
498 system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles
499 system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
500 system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
501 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
502 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
503 system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
504 system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
505 system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
506 system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
507 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
508 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
509 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
510 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
511 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
512 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
513 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
514 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
515 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency
516 system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency
517 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency
518 system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency
519 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency
520 system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency
521 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency
522 system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency
523 system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked
524 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
525 system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked
526 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
527 system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked
528 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529 system.iocache.fast_writes 0 # number of fast writes performed
530 system.iocache.cache_copies 0 # number of cache copies performed
531 system.iocache.writebacks::writebacks 46667 # number of writebacks
532 system.iocache.writebacks::total 46667 # number of writebacks
533 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
534 system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
535 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
536 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
537 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
538 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
539 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
540 system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
541 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles
542 system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles
543 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles
544 system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles
545 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles
546 system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles
547 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles
548 system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles
549 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
550 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
551 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
552 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
553 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
554 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
555 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
556 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
557 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency
558 system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency
559 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency
560 system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency
561 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency
562 system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency
563 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency
564 system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency
565 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
566 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
567 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
568 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
569 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
570 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
571 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
572 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
573 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
574 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
575 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
576 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
577 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
578 system.iobus.throughput 638147 # Throughput (bytes/s)
579 system.iobus.trans_dist::ReadReq 225559 # Transaction distribution
580 system.iobus.trans_dist::ReadResp 225559 # Transaction distribution
581 system.iobus.trans_dist::WriteReq 57591 # Transaction distribution
582 system.iobus.trans_dist::WriteResp 57591 # Transaction distribution
583 system.iobus.trans_dist::MessageReq 1642 # Transaction distribution
584 system.iobus.trans_dist::MessageResp 1642 # Transaction distribution
585 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
586 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
587 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
588 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
589 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
590 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
591 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
592 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
593 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
594 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
595 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
596 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
597 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
598 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
599 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
600 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
601 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
602 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
603 system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes)
604 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes)
605 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes)
606 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
607 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
608 system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes)
609 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
610 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
611 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
612 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
613 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
614 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
615 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
616 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
617 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
618 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
619 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
620 system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
621 system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
622 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
623 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
624 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
625 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
626 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
627 system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes)
628 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes)
629 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes)
630 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
631 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
632 system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes)
633 system.iobus.data_through_bus 3276202 # Total data (bytes)
634 system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks)
635 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
636 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
637 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
638 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
639 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
640 system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
641 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
642 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
643 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
644 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
645 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
646 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
647 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
648 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
649 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
650 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
651 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
652 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
653 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
654 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
655 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
656 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
657 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
658 system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
659 system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
660 system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
661 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
662 system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
663 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
664 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
665 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
666 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
667 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
668 system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
669 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
670 system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks)
671 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
672 system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
673 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
674 system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks)
675 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
676 system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks)
677 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
678 system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks)
679 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
680 system.cpu_clk_domain.clock 500 # Clock period in ticks
681 system.cpu.branchPred.lookups 85602749 # Number of BP lookups
682 system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted
683 system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect
684 system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups
685 system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits
686 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
687 system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage
688 system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target.
689 system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions.
690 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
691 system.cpu.numCycles 453810576 # number of cpu cycles simulated
692 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
693 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
694 system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss
695 system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed
696 system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered
697 system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken
698 system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked
699 system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing
700 system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb
701 system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked
702 system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
703 system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps
704 system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR
705 system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched
706 system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed
707 system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed
708 system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total)
709 system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total)
710 system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total)
711 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
712 system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total)
713 system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total)
714 system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total)
715 system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total)
716 system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total)
717 system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total)
718 system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total)
719 system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total)
720 system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total)
721 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
722 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
723 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
724 system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total)
725 system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle
726 system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle
727 system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle
728 system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked
729 system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running
730 system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking
731 system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing
732 system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode
733 system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode
734 system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing
735 system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle
736 system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking
737 system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst
738 system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running
739 system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking
740 system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename
741 system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full
742 system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full
743 system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full
744 system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed
745 system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made
746 system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups
747 system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups
748 system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed
749 system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing
750 system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed
751 system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed
752 system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer
753 system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit.
754 system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit.
755 system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads.
756 system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores.
757 system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec)
758 system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ
759 system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued
760 system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued
761 system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling
762 system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph
763 system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed
764 system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle
765 system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle
766 system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle
767 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
768 system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle
769 system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle
770 system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle
771 system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle
772 system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle
773 system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle
774 system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle
775 system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle
776 system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle
777 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
778 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
779 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
780 system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle
781 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
782 system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available
783 system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available
784 system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available
785 system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available
786 system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available
787 system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available
788 system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available
789 system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available
790 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available
791 system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available
792 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available
793 system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available
794 system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available
795 system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available
796 system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available
797 system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available
798 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available
799 system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available
800 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available
801 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available
802 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available
803 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available
804 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available
805 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available
806 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available
807 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available
808 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available
809 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available
810 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available
811 system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available
812 system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available
813 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
814 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
815 system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued
816 system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued
817 system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued
818 system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued
819 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
820 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
821 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
822 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
823 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
824 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
825 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
826 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
827 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
828 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
829 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
830 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
831 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
832 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
833 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
834 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
835 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
836 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
837 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
838 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
839 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
840 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
841 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
842 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
843 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
844 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
845 system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued
846 system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued
847 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
848 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
849 system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued
850 system.cpu.iq.rate 1.809048 # Inst issue rate
851 system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested
852 system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst)
853 system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads
854 system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes
855 system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses
856 system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads
857 system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes
858 system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
859 system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses
860 system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses
861 system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores
862 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
863 system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed
864 system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed
865 system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations
866 system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed
867 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
868 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
869 system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled
870 system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked
871 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
872 system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing
873 system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking
874 system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking
875 system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ
876 system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch
877 system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions
878 system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions
879 system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions
880 system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall
881 system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall
882 system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations
883 system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly
884 system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly
885 system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute
886 system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions
887 system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed
888 system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute
889 system.cpu.iew.exec_swp 0 # number of swp insts executed
890 system.cpu.iew.exec_nop 0 # number of nop insts executed
891 system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed
892 system.cpu.iew.exec_branches 83090233 # Number of branches executed
893 system.cpu.iew.exec_stores 9042949 # Number of stores executed
894 system.cpu.iew.exec_rate 1.805939 # Inst execution rate
895 system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit
896 system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back
897 system.cpu.iew.wb_producers 638575855 # num instructions producing a value
898 system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value
899 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
900 system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle
901 system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back
902 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
903 system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit
904 system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards
905 system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted
906 system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle
907 system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle
908 system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle
909 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
910 system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle
911 system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle
912 system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle
913 system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle
914 system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle
915 system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle
916 system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle
917 system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle
918 system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle
919 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
920 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
921 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
922 system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle
923 system.cpu.commit.committedInsts 407751929 # Number of instructions committed
924 system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed
925 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
926 system.cpu.commit.refs 22412111 # Number of memory references committed
927 system.cpu.commit.loads 13990076 # Number of loads committed
928 system.cpu.commit.membars 474663 # Number of memory barriers committed
929 system.cpu.commit.branches 82157264 # Number of branches committed
930 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
931 system.cpu.commit.int_insts 734852381 # Number of committed integer instructions.
932 system.cpu.commit.function_calls 1155163 # Number of function calls committed.
933 system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached
934 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
935 system.cpu.rob.rob_reads 1080228878 # The number of ROB reads
936 system.cpu.rob.rob_writes 1655077473 # The number of ROB writes
937 system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself
938 system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling
939 system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
940 system.cpu.committedInsts 407751929 # Number of Instructions Simulated
941 system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated
942 system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated
943 system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction
944 system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads
945 system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle
946 system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads
947 system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads
948 system.cpu.int_regfile_writes 653821136 # number of integer regfile writes
949 system.cpu.fp_regfile_reads 54 # number of floating regfile reads
950 system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads
951 system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes
952 system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads
953 system.cpu.misc_regfile_writes 402300 # number of misc regfile writes
954 system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s)
955 system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution
956 system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution
957 system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution
958 system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution
959 system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution
960 system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution
961 system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution
962 system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution
963 system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution
964 system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
965 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes)
966 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes)
967 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes)
968 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes)
969 system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes)
970 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes)
971 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes)
972 system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes)
973 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes)
974 system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes)
975 system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes)
976 system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes)
977 system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks)
978 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
979 system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks)
980 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
981 system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks)
982 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
983 system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks)
984 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
985 system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks)
986 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
987 system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks)
988 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
989 system.cpu.icache.tags.replacements 957724 # number of replacements
990 system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use
991 system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks.
992 system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks.
993 system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks.
994 system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit.
995 system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor
996 system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy
997 system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy
998 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
999 system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
1000 system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
1001 system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id
1002 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1003 system.cpu.icache.tags.tag_accesses 9447804 # Number of tag accesses
1004 system.cpu.icache.tags.data_accesses 9447804 # Number of data accesses
1005 system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits
1006 system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits
1007 system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits
1008 system.cpu.icache.demand_hits::total 7477774 # number of demand (read+write) hits
1009 system.cpu.icache.overall_hits::cpu.inst 7477774 # number of overall hits
1010 system.cpu.icache.overall_hits::total 7477774 # number of overall hits
1011 system.cpu.icache.ReadReq_misses::cpu.inst 1011731 # number of ReadReq misses
1012 system.cpu.icache.ReadReq_misses::total 1011731 # number of ReadReq misses
1013 system.cpu.icache.demand_misses::cpu.inst 1011731 # number of demand (read+write) misses
1014 system.cpu.icache.demand_misses::total 1011731 # number of demand (read+write) misses
1015 system.cpu.icache.overall_misses::cpu.inst 1011731 # number of overall misses
1016 system.cpu.icache.overall_misses::total 1011731 # number of overall misses
1017 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14180716030 # number of ReadReq miss cycles
1018 system.cpu.icache.ReadReq_miss_latency::total 14180716030 # number of ReadReq miss cycles
1019 system.cpu.icache.demand_miss_latency::cpu.inst 14180716030 # number of demand (read+write) miss cycles
1020 system.cpu.icache.demand_miss_latency::total 14180716030 # number of demand (read+write) miss cycles
1021 system.cpu.icache.overall_miss_latency::cpu.inst 14180716030 # number of overall miss cycles
1022 system.cpu.icache.overall_miss_latency::total 14180716030 # number of overall miss cycles
1023 system.cpu.icache.ReadReq_accesses::cpu.inst 8489505 # number of ReadReq accesses(hits+misses)
1024 system.cpu.icache.ReadReq_accesses::total 8489505 # number of ReadReq accesses(hits+misses)
1025 system.cpu.icache.demand_accesses::cpu.inst 8489505 # number of demand (read+write) accesses
1026 system.cpu.icache.demand_accesses::total 8489505 # number of demand (read+write) accesses
1027 system.cpu.icache.overall_accesses::cpu.inst 8489505 # number of overall (read+write) accesses
1028 system.cpu.icache.overall_accesses::total 8489505 # number of overall (read+write) accesses
1029 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119174 # miss rate for ReadReq accesses
1030 system.cpu.icache.ReadReq_miss_rate::total 0.119174 # miss rate for ReadReq accesses
1031 system.cpu.icache.demand_miss_rate::cpu.inst 0.119174 # miss rate for demand accesses
1032 system.cpu.icache.demand_miss_rate::total 0.119174 # miss rate for demand accesses
1033 system.cpu.icache.overall_miss_rate::cpu.inst 0.119174 # miss rate for overall accesses
1034 system.cpu.icache.overall_miss_rate::total 0.119174 # miss rate for overall accesses
1035 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921 # average ReadReq miss latency
1036 system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921 # average ReadReq miss latency
1037 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency
1038 system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency
1039 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency
1040 system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency
1041 system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked
1042 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1043 system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked
1044 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1045 system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked
1046 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1047 system.cpu.icache.fast_writes 0 # number of fast writes performed
1048 system.cpu.icache.cache_copies 0 # number of cache copies performed
1049 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53432 # number of ReadReq MSHR hits
1050 system.cpu.icache.ReadReq_mshr_hits::total 53432 # number of ReadReq MSHR hits
1051 system.cpu.icache.demand_mshr_hits::cpu.inst 53432 # number of demand (read+write) MSHR hits
1052 system.cpu.icache.demand_mshr_hits::total 53432 # number of demand (read+write) MSHR hits
1053 system.cpu.icache.overall_mshr_hits::cpu.inst 53432 # number of overall MSHR hits
1054 system.cpu.icache.overall_mshr_hits::total 53432 # number of overall MSHR hits
1055 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958299 # number of ReadReq MSHR misses
1056 system.cpu.icache.ReadReq_mshr_misses::total 958299 # number of ReadReq MSHR misses
1057 system.cpu.icache.demand_mshr_misses::cpu.inst 958299 # number of demand (read+write) MSHR misses
1058 system.cpu.icache.demand_mshr_misses::total 958299 # number of demand (read+write) MSHR misses
1059 system.cpu.icache.overall_mshr_misses::cpu.inst 958299 # number of overall MSHR misses
1060 system.cpu.icache.overall_mshr_misses::total 958299 # number of overall MSHR misses
1061 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11693776143 # number of ReadReq MSHR miss cycles
1062 system.cpu.icache.ReadReq_mshr_miss_latency::total 11693776143 # number of ReadReq MSHR miss cycles
1063 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11693776143 # number of demand (read+write) MSHR miss cycles
1064 system.cpu.icache.demand_mshr_miss_latency::total 11693776143 # number of demand (read+write) MSHR miss cycles
1065 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11693776143 # number of overall MSHR miss cycles
1066 system.cpu.icache.overall_mshr_miss_latency::total 11693776143 # number of overall MSHR miss cycles
1067 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for ReadReq accesses
1068 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112880 # mshr miss rate for ReadReq accesses
1069 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for demand accesses
1070 system.cpu.icache.demand_mshr_miss_rate::total 0.112880 # mshr miss rate for demand accesses
1071 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for overall accesses
1072 system.cpu.icache.overall_mshr_miss_rate::total 0.112880 # mshr miss rate for overall accesses
1073 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365 # average ReadReq mshr miss latency
1074 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365 # average ReadReq mshr miss latency
1075 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency
1076 system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency
1077 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency
1078 system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency
1079 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1080 system.cpu.itb_walker_cache.tags.replacements 8926 # number of replacements
1081 system.cpu.itb_walker_cache.tags.tagsinuse 6.004704 # Cycle average of tags in use
1082 system.cpu.itb_walker_cache.tags.total_refs 20407 # Total number of references to valid blocks.
1083 system.cpu.itb_walker_cache.tags.sampled_refs 8940 # Sample count of references to valid blocks.
1084 system.cpu.itb_walker_cache.tags.avg_refs 2.282662 # Average number of references to valid blocks.
1085 system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500 # Cycle when the warmup percentage was hit.
1086 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor
1087 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy
1088 system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy
1089 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
1090 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
1091 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
1092 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
1093 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
1094 system.cpu.itb_walker_cache.tags.tag_accesses 70243 # Number of tag accesses
1095 system.cpu.itb_walker_cache.tags.data_accesses 70243 # Number of data accesses
1096 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits
1097 system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits
1098 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
1099 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
1100 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20417 # number of demand (read+write) hits
1101 system.cpu.itb_walker_cache.demand_hits::total 20417 # number of demand (read+write) hits
1102 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20417 # number of overall hits
1103 system.cpu.itb_walker_cache.overall_hits::total 20417 # number of overall hits
1104 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9803 # number of ReadReq misses
1105 system.cpu.itb_walker_cache.ReadReq_misses::total 9803 # number of ReadReq misses
1106 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9803 # number of demand (read+write) misses
1107 system.cpu.itb_walker_cache.demand_misses::total 9803 # number of demand (read+write) misses
1108 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9803 # number of overall misses
1109 system.cpu.itb_walker_cache.overall_misses::total 9803 # number of overall misses
1110 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109186247 # number of ReadReq miss cycles
1111 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109186247 # number of ReadReq miss cycles
1112 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109186247 # number of demand (read+write) miss cycles
1113 system.cpu.itb_walker_cache.demand_miss_latency::total 109186247 # number of demand (read+write) miss cycles
1114 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109186247 # number of overall miss cycles
1115 system.cpu.itb_walker_cache.overall_miss_latency::total 109186247 # number of overall miss cycles
1116 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30218 # number of ReadReq accesses(hits+misses)
1117 system.cpu.itb_walker_cache.ReadReq_accesses::total 30218 # number of ReadReq accesses(hits+misses)
1118 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1119 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1120 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30220 # number of demand (read+write) accesses
1121 system.cpu.itb_walker_cache.demand_accesses::total 30220 # number of demand (read+write) accesses
1122 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30220 # number of overall (read+write) accesses
1123 system.cpu.itb_walker_cache.overall_accesses::total 30220 # number of overall (read+write) accesses
1124 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.324409 # miss rate for ReadReq accesses
1125 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.324409 # miss rate for ReadReq accesses
1126 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.324388 # miss rate for demand accesses
1127 system.cpu.itb_walker_cache.demand_miss_rate::total 0.324388 # miss rate for demand accesses
1128 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.324388 # miss rate for overall accesses
1129 system.cpu.itb_walker_cache.overall_miss_rate::total 0.324388 # miss rate for overall accesses
1130 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11138.044170 # average ReadReq miss latency
1131 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11138.044170 # average ReadReq miss latency
1132 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency
1133 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170 # average overall miss latency
1134 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency
1135 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170 # average overall miss latency
1136 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1137 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1138 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1139 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1140 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1141 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1142 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1143 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1144 system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks
1145 system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks
1146 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9803 # number of ReadReq MSHR misses
1147 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9803 # number of ReadReq MSHR misses
1148 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9803 # number of demand (read+write) MSHR misses
1149 system.cpu.itb_walker_cache.demand_mshr_misses::total 9803 # number of demand (read+write) MSHR misses
1150 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9803 # number of overall MSHR misses
1151 system.cpu.itb_walker_cache.overall_mshr_misses::total 9803 # number of overall MSHR misses
1152 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 89573259 # number of ReadReq MSHR miss cycles
1153 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 89573259 # number of ReadReq MSHR miss cycles
1154 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 89573259 # number of demand (read+write) MSHR miss cycles
1155 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 89573259 # number of demand (read+write) MSHR miss cycles
1156 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 89573259 # number of overall MSHR miss cycles
1157 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 89573259 # number of overall MSHR miss cycles
1158 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.324409 # mshr miss rate for ReadReq accesses
1159 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.324409 # mshr miss rate for ReadReq accesses
1160 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for demand accesses
1161 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.324388 # mshr miss rate for demand accesses
1162 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for overall accesses
1163 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses
1164 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency
1165 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency
1166 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency
1167 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency
1168 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency
1169 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency
1170 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1171 system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements
1172 system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use
1173 system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks.
1174 system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks.
1175 system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks.
1176 system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit.
1177 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor
1178 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy
1179 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy
1180 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
1181 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
1182 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
1183 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
1184 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1185 system.cpu.dtb_walker_cache.tags.tag_accesses 390650 # Number of tag accesses
1186 system.cpu.dtb_walker_cache.tags.data_accesses 390650 # Number of data accesses
1187 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits
1188 system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits
1189 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits
1190 system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits
1191 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits
1192 system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits
1193 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses
1194 system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses
1195 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses
1196 system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses
1197 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses
1198 system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses
1199 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles
1200 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles
1201 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles
1202 system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles
1203 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles
1204 system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles
1205 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses)
1206 system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses)
1207 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses
1208 system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses
1209 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses
1210 system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses
1211 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses
1212 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses
1213 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses
1214 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses
1215 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses
1216 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses
1217 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency
1218 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency
1219 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency
1220 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency
1221 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency
1222 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency
1223 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1224 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1225 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1226 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1227 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1228 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1229 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
1230 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
1231 system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks
1232 system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks
1233 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses
1234 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses
1235 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses
1236 system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses
1237 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses
1238 system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses
1239 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles
1240 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles
1241 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles
1242 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles
1243 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles
1244 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles
1245 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses
1246 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses
1247 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses
1248 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses
1249 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses
1250 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses
1251 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency
1252 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency
1253 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency
1254 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency
1255 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency
1256 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency
1257 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1258 system.cpu.dcache.tags.replacements 1656829 # number of replacements
1259 system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use
1260 system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks.
1261 system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks.
1262 system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks.
1263 system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit.
1264 system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor
1265 system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
1266 system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
1267 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1268 system.cpu.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
1269 system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
1270 system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
1271 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1272 system.cpu.dcache.tags.tag_accesses 87846935 # Number of tag accesses
1273 system.cpu.dcache.tags.data_accesses 87846935 # Number of data accesses
1274 system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits
1275 system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits
1276 system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits
1277 system.cpu.dcache.WriteReq_hits::total 8096443 # number of WriteReq hits
1278 system.cpu.dcache.demand_hits::cpu.data 18995279 # number of demand (read+write) hits
1279 system.cpu.dcache.demand_hits::total 18995279 # number of demand (read+write) hits
1280 system.cpu.dcache.overall_hits::cpu.data 18995279 # number of overall hits
1281 system.cpu.dcache.overall_hits::total 18995279 # number of overall hits
1282 system.cpu.dcache.ReadReq_misses::cpu.data 2236048 # number of ReadReq misses
1283 system.cpu.dcache.ReadReq_misses::total 2236048 # number of ReadReq misses
1284 system.cpu.dcache.WriteReq_misses::cpu.data 316058 # number of WriteReq misses
1285 system.cpu.dcache.WriteReq_misses::total 316058 # number of WriteReq misses
1286 system.cpu.dcache.demand_misses::cpu.data 2552106 # number of demand (read+write) misses
1287 system.cpu.dcache.demand_misses::total 2552106 # number of demand (read+write) misses
1288 system.cpu.dcache.overall_misses::cpu.data 2552106 # number of overall misses
1289 system.cpu.dcache.overall_misses::total 2552106 # number of overall misses
1290 system.cpu.dcache.ReadReq_miss_latency::cpu.data 33041447208 # number of ReadReq miss cycles
1291 system.cpu.dcache.ReadReq_miss_latency::total 33041447208 # number of ReadReq miss cycles
1292 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12234670517 # number of WriteReq miss cycles
1293 system.cpu.dcache.WriteReq_miss_latency::total 12234670517 # number of WriteReq miss cycles
1294 system.cpu.dcache.demand_miss_latency::cpu.data 45276117725 # number of demand (read+write) miss cycles
1295 system.cpu.dcache.demand_miss_latency::total 45276117725 # number of demand (read+write) miss cycles
1296 system.cpu.dcache.overall_miss_latency::cpu.data 45276117725 # number of overall miss cycles
1297 system.cpu.dcache.overall_miss_latency::total 45276117725 # number of overall miss cycles
1298 system.cpu.dcache.ReadReq_accesses::cpu.data 13134884 # number of ReadReq accesses(hits+misses)
1299 system.cpu.dcache.ReadReq_accesses::total 13134884 # number of ReadReq accesses(hits+misses)
1300 system.cpu.dcache.WriteReq_accesses::cpu.data 8412501 # number of WriteReq accesses(hits+misses)
1301 system.cpu.dcache.WriteReq_accesses::total 8412501 # number of WriteReq accesses(hits+misses)
1302 system.cpu.dcache.demand_accesses::cpu.data 21547385 # number of demand (read+write) accesses
1303 system.cpu.dcache.demand_accesses::total 21547385 # number of demand (read+write) accesses
1304 system.cpu.dcache.overall_accesses::cpu.data 21547385 # number of overall (read+write) accesses
1305 system.cpu.dcache.overall_accesses::total 21547385 # number of overall (read+write) accesses
1306 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170237 # miss rate for ReadReq accesses
1307 system.cpu.dcache.ReadReq_miss_rate::total 0.170237 # miss rate for ReadReq accesses
1308 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037570 # miss rate for WriteReq accesses
1309 system.cpu.dcache.WriteReq_miss_rate::total 0.037570 # miss rate for WriteReq accesses
1310 system.cpu.dcache.demand_miss_rate::cpu.data 0.118442 # miss rate for demand accesses
1311 system.cpu.dcache.demand_miss_rate::total 0.118442 # miss rate for demand accesses
1312 system.cpu.dcache.overall_miss_rate::cpu.data 0.118442 # miss rate for overall accesses
1313 system.cpu.dcache.overall_miss_rate::total 0.118442 # miss rate for overall accesses
1314 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14776.716425 # average ReadReq miss latency
1315 system.cpu.dcache.ReadReq_avg_miss_latency::total 14776.716425 # average ReadReq miss latency
1316 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38710.206725 # average WriteReq miss latency
1317 system.cpu.dcache.WriteReq_avg_miss_latency::total 38710.206725 # average WriteReq miss latency
1318 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency
1319 system.cpu.dcache.demand_avg_miss_latency::total 17740.688563 # average overall miss latency
1320 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency
1321 system.cpu.dcache.overall_avg_miss_latency::total 17740.688563 # average overall miss latency
1322 system.cpu.dcache.blocked_cycles::no_mshrs 395761 # number of cycles access was blocked
1323 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1324 system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked
1325 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1326 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked
1327 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1328 system.cpu.dcache.fast_writes 0 # number of fast writes performed
1329 system.cpu.dcache.cache_copies 0 # number of cache copies performed
1330 system.cpu.dcache.writebacks::writebacks 1558454 # number of writebacks
1331 system.cpu.dcache.writebacks::total 1558454 # number of writebacks
1332 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866560 # number of ReadReq MSHR hits
1333 system.cpu.dcache.ReadReq_mshr_hits::total 866560 # number of ReadReq MSHR hits
1334 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25905 # number of WriteReq MSHR hits
1335 system.cpu.dcache.WriteReq_mshr_hits::total 25905 # number of WriteReq MSHR hits
1336 system.cpu.dcache.demand_mshr_hits::cpu.data 892465 # number of demand (read+write) MSHR hits
1337 system.cpu.dcache.demand_mshr_hits::total 892465 # number of demand (read+write) MSHR hits
1338 system.cpu.dcache.overall_mshr_hits::cpu.data 892465 # number of overall MSHR hits
1339 system.cpu.dcache.overall_mshr_hits::total 892465 # number of overall MSHR hits
1340 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369488 # number of ReadReq MSHR misses
1341 system.cpu.dcache.ReadReq_mshr_misses::total 1369488 # number of ReadReq MSHR misses
1342 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290153 # number of WriteReq MSHR misses
1343 system.cpu.dcache.WriteReq_mshr_misses::total 290153 # number of WriteReq MSHR misses
1344 system.cpu.dcache.demand_mshr_misses::cpu.data 1659641 # number of demand (read+write) MSHR misses
1345 system.cpu.dcache.demand_mshr_misses::total 1659641 # number of demand (read+write) MSHR misses
1346 system.cpu.dcache.overall_mshr_misses::cpu.data 1659641 # number of overall MSHR misses
1347 system.cpu.dcache.overall_mshr_misses::total 1659641 # number of overall MSHR misses
1348 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17811534705 # number of ReadReq MSHR miss cycles
1349 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17811534705 # number of ReadReq MSHR miss cycles
1350 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11340798474 # number of WriteReq MSHR miss cycles
1351 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11340798474 # number of WriteReq MSHR miss cycles
1352 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29152333179 # number of demand (read+write) MSHR miss cycles
1353 system.cpu.dcache.demand_mshr_miss_latency::total 29152333179 # number of demand (read+write) MSHR miss cycles
1354 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29152333179 # number of overall MSHR miss cycles
1355 system.cpu.dcache.overall_mshr_miss_latency::total 29152333179 # number of overall MSHR miss cycles
1356 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363398000 # number of ReadReq MSHR uncacheable cycles
1357 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363398000 # number of ReadReq MSHR uncacheable cycles
1358 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536146500 # number of WriteReq MSHR uncacheable cycles
1359 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536146500 # number of WriteReq MSHR uncacheable cycles
1360 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899544500 # number of overall MSHR uncacheable cycles
1361 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899544500 # number of overall MSHR uncacheable cycles
1362 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104263 # mshr miss rate for ReadReq accesses
1363 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104263 # mshr miss rate for ReadReq accesses
1364 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034491 # mshr miss rate for WriteReq accesses
1365 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034491 # mshr miss rate for WriteReq accesses
1366 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for demand accesses
1367 system.cpu.dcache.demand_mshr_miss_rate::total 0.077023 # mshr miss rate for demand accesses
1368 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for overall accesses
1369 system.cpu.dcache.overall_mshr_miss_rate::total 0.077023 # mshr miss rate for overall accesses
1370 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.980852 # average ReadReq mshr miss latency
1371 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852 # average ReadReq mshr miss latency
1372 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621 # average WriteReq mshr miss latency
1373 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39085.580621 # average WriteReq mshr miss latency
1374 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency
1375 system.cpu.dcache.demand_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency
1376 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency
1377 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency
1378 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1379 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1380 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1381 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1382 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1383 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1384 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1385 system.cpu.l2cache.tags.replacements 111322 # number of replacements
1386 system.cpu.l2cache.tags.tagsinuse 64824.350244 # Cycle average of tags in use
1387 system.cpu.l2cache.tags.total_refs 3788284 # Total number of references to valid blocks.
1388 system.cpu.l2cache.tags.sampled_refs 175285 # Sample count of references to valid blocks.
1389 system.cpu.l2cache.tags.avg_refs 21.612140 # Average number of references to valid blocks.
1390 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1391 system.cpu.l2cache.tags.occ_blocks::writebacks 50850.934653 # Average occupied blocks per requestor
1392 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.783858 # Average occupied blocks per requestor
1393 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126014 # Average occupied blocks per requestor
1394 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3002.561725 # Average occupied blocks per requestor
1395 system.cpu.l2cache.tags.occ_blocks::cpu.data 10960.943994 # Average occupied blocks per requestor
1396 system.cpu.l2cache.tags.occ_percent::writebacks 0.775924 # Average percentage of cache occupancy
1397 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000149 # Average percentage of cache occupancy
1398 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1399 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045815 # Average percentage of cache occupancy
1400 system.cpu.l2cache.tags.occ_percent::cpu.data 0.167251 # Average percentage of cache occupancy
1401 system.cpu.l2cache.tags.occ_percent::total 0.989141 # Average percentage of cache occupancy
1402 system.cpu.l2cache.tags.occ_task_id_blocks::1024 63963 # Occupied blocks per task id
1403 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
1404 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 514 # Occupied blocks per task id
1405 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3380 # Occupied blocks per task id
1406 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id
1407 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54576 # Occupied blocks per task id
1408 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975998 # Percentage of cache occupancy per task id
1409 system.cpu.l2cache.tags.tag_accesses 34635418 # Number of tag accesses
1410 system.cpu.l2cache.tags.data_accesses 34635418 # Number of data accesses
1411 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64096 # number of ReadReq hits
1412 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7642 # number of ReadReq hits
1413 system.cpu.l2cache.ReadReq_hits::cpu.inst 942107 # number of ReadReq hits
1414 system.cpu.l2cache.ReadReq_hits::cpu.data 1332840 # number of ReadReq hits
1415 system.cpu.l2cache.ReadReq_hits::total 2346685 # number of ReadReq hits
1416 system.cpu.l2cache.Writeback_hits::writebacks 1581663 # number of Writeback hits
1417 system.cpu.l2cache.Writeback_hits::total 1581663 # number of Writeback hits
1418 system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits
1419 system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits
1420 system.cpu.l2cache.ReadExReq_hits::cpu.data 155094 # number of ReadExReq hits
1421 system.cpu.l2cache.ReadExReq_hits::total 155094 # number of ReadExReq hits
1422 system.cpu.l2cache.demand_hits::cpu.dtb.walker 64096 # number of demand (read+write) hits
1423 system.cpu.l2cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits
1424 system.cpu.l2cache.demand_hits::cpu.inst 942107 # number of demand (read+write) hits
1425 system.cpu.l2cache.demand_hits::cpu.data 1487934 # number of demand (read+write) hits
1426 system.cpu.l2cache.demand_hits::total 2501779 # number of demand (read+write) hits
1427 system.cpu.l2cache.overall_hits::cpu.dtb.walker 64096 # number of overall hits
1428 system.cpu.l2cache.overall_hits::cpu.itb.walker 7642 # number of overall hits
1429 system.cpu.l2cache.overall_hits::cpu.inst 942107 # number of overall hits
1430 system.cpu.l2cache.overall_hits::cpu.data 1487934 # number of overall hits
1431 system.cpu.l2cache.overall_hits::total 2501779 # number of overall hits
1432 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses
1433 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
1434 system.cpu.l2cache.ReadReq_misses::cpu.inst 16085 # number of ReadReq misses
1435 system.cpu.l2cache.ReadReq_misses::cpu.data 35964 # number of ReadReq misses
1436 system.cpu.l2cache.ReadReq_misses::total 52115 # number of ReadReq misses
1437 system.cpu.l2cache.UpgradeReq_misses::cpu.data 1454 # number of UpgradeReq misses
1438 system.cpu.l2cache.UpgradeReq_misses::total 1454 # number of UpgradeReq misses
1439 system.cpu.l2cache.ReadExReq_misses::cpu.data 132906 # number of ReadExReq misses
1440 system.cpu.l2cache.ReadExReq_misses::total 132906 # number of ReadExReq misses
1441 system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses
1442 system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1443 system.cpu.l2cache.demand_misses::cpu.inst 16085 # number of demand (read+write) misses
1444 system.cpu.l2cache.demand_misses::cpu.data 168870 # number of demand (read+write) misses
1445 system.cpu.l2cache.demand_misses::total 185021 # number of demand (read+write) misses
1446 system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses
1447 system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1448 system.cpu.l2cache.overall_misses::cpu.inst 16085 # number of overall misses
1449 system.cpu.l2cache.overall_misses::cpu.data 168870 # number of overall misses
1450 system.cpu.l2cache.overall_misses::total 185021 # number of overall misses
1451 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5922249 # number of ReadReq miss cycles
1452 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 375500 # number of ReadReq miss cycles
1453 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1293203490 # number of ReadReq miss cycles
1454 system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2919351194 # number of ReadReq miss cycles
1455 system.cpu.l2cache.ReadReq_miss_latency::total 4218852433 # number of ReadReq miss cycles
1456 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17719300 # number of UpgradeReq miss cycles
1457 system.cpu.l2cache.UpgradeReq_miss_latency::total 17719300 # number of UpgradeReq miss cycles
1458 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9455061655 # number of ReadExReq miss cycles
1459 system.cpu.l2cache.ReadExReq_miss_latency::total 9455061655 # number of ReadExReq miss cycles
1460 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5922249 # number of demand (read+write) miss cycles
1461 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 375500 # number of demand (read+write) miss cycles
1462 system.cpu.l2cache.demand_miss_latency::cpu.inst 1293203490 # number of demand (read+write) miss cycles
1463 system.cpu.l2cache.demand_miss_latency::cpu.data 12374412849 # number of demand (read+write) miss cycles
1464 system.cpu.l2cache.demand_miss_latency::total 13673914088 # number of demand (read+write) miss cycles
1465 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5922249 # number of overall miss cycles
1466 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 375500 # number of overall miss cycles
1467 system.cpu.l2cache.overall_miss_latency::cpu.inst 1293203490 # number of overall miss cycles
1468 system.cpu.l2cache.overall_miss_latency::cpu.data 12374412849 # number of overall miss cycles
1469 system.cpu.l2cache.overall_miss_latency::total 13673914088 # number of overall miss cycles
1470 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64157 # number of ReadReq accesses(hits+misses)
1471 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7647 # number of ReadReq accesses(hits+misses)
1472 system.cpu.l2cache.ReadReq_accesses::cpu.inst 958192 # number of ReadReq accesses(hits+misses)
1473 system.cpu.l2cache.ReadReq_accesses::cpu.data 1368804 # number of ReadReq accesses(hits+misses)
1474 system.cpu.l2cache.ReadReq_accesses::total 2398800 # number of ReadReq accesses(hits+misses)
1475 system.cpu.l2cache.Writeback_accesses::writebacks 1581663 # number of Writeback accesses(hits+misses)
1476 system.cpu.l2cache.Writeback_accesses::total 1581663 # number of Writeback accesses(hits+misses)
1477 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1774 # number of UpgradeReq accesses(hits+misses)
1478 system.cpu.l2cache.UpgradeReq_accesses::total 1774 # number of UpgradeReq accesses(hits+misses)
1479 system.cpu.l2cache.ReadExReq_accesses::cpu.data 288000 # number of ReadExReq accesses(hits+misses)
1480 system.cpu.l2cache.ReadExReq_accesses::total 288000 # number of ReadExReq accesses(hits+misses)
1481 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64157 # number of demand (read+write) accesses
1482 system.cpu.l2cache.demand_accesses::cpu.itb.walker 7647 # number of demand (read+write) accesses
1483 system.cpu.l2cache.demand_accesses::cpu.inst 958192 # number of demand (read+write) accesses
1484 system.cpu.l2cache.demand_accesses::cpu.data 1656804 # number of demand (read+write) accesses
1485 system.cpu.l2cache.demand_accesses::total 2686800 # number of demand (read+write) accesses
1486 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64157 # number of overall (read+write) accesses
1487 system.cpu.l2cache.overall_accesses::cpu.itb.walker 7647 # number of overall (read+write) accesses
1488 system.cpu.l2cache.overall_accesses::cpu.inst 958192 # number of overall (read+write) accesses
1489 system.cpu.l2cache.overall_accesses::cpu.data 1656804 # number of overall (read+write) accesses
1490 system.cpu.l2cache.overall_accesses::total 2686800 # number of overall (read+write) accesses
1491 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000951 # miss rate for ReadReq accesses
1492 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000654 # miss rate for ReadReq accesses
1493 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016787 # miss rate for ReadReq accesses
1494 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026274 # miss rate for ReadReq accesses
1495 system.cpu.l2cache.ReadReq_miss_rate::total 0.021725 # miss rate for ReadReq accesses
1496 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.819617 # miss rate for UpgradeReq accesses
1497 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.819617 # miss rate for UpgradeReq accesses
1498 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461479 # miss rate for ReadExReq accesses
1499 system.cpu.l2cache.ReadExReq_miss_rate::total 0.461479 # miss rate for ReadExReq accesses
1500 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000951 # miss rate for demand accesses
1501 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000654 # miss rate for demand accesses
1502 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016787 # miss rate for demand accesses
1503 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101925 # miss rate for demand accesses
1504 system.cpu.l2cache.demand_miss_rate::total 0.068863 # miss rate for demand accesses
1505 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000951 # miss rate for overall accesses
1506 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000654 # miss rate for overall accesses
1507 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016787 # miss rate for overall accesses
1508 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101925 # miss rate for overall accesses
1509 system.cpu.l2cache.overall_miss_rate::total 0.068863 # miss rate for overall accesses
1510 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97086.049180 # average ReadReq miss latency
1511 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75100 # average ReadReq miss latency
1512 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80398.103202 # average ReadReq miss latency
1513 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81174.262985 # average ReadReq miss latency
1514 system.cpu.l2cache.ReadReq_avg_miss_latency::total 80952.747443 # average ReadReq miss latency
1515 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12186.588721 # average UpgradeReq miss latency
1516 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12186.588721 # average UpgradeReq miss latency
1517 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71140.969219 # average ReadExReq miss latency
1518 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71140.969219 # average ReadExReq miss latency
1519 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency
1520 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency
1521 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency
1522 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency
1523 system.cpu.l2cache.demand_avg_miss_latency::total 73904.659947 # average overall miss latency
1524 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency
1525 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency
1526 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency
1527 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency
1528 system.cpu.l2cache.overall_avg_miss_latency::total 73904.659947 # average overall miss latency
1529 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1530 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1531 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1532 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1533 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1534 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1535 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1536 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1537 system.cpu.l2cache.writebacks::writebacks 101656 # number of writebacks
1538 system.cpu.l2cache.writebacks::total 101656 # number of writebacks
1539 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1540 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1541 system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
1542 system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1543 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1544 system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
1545 system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1546 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1547 system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
1548 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses
1549 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
1550 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16084 # number of ReadReq MSHR misses
1551 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35963 # number of ReadReq MSHR misses
1552 system.cpu.l2cache.ReadReq_mshr_misses::total 52113 # number of ReadReq MSHR misses
1553 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1454 # number of UpgradeReq MSHR misses
1554 system.cpu.l2cache.UpgradeReq_mshr_misses::total 1454 # number of UpgradeReq MSHR misses
1555 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132906 # number of ReadExReq MSHR misses
1556 system.cpu.l2cache.ReadExReq_mshr_misses::total 132906 # number of ReadExReq MSHR misses
1557 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses
1558 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1559 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16084 # number of demand (read+write) MSHR misses
1560 system.cpu.l2cache.demand_mshr_misses::cpu.data 168869 # number of demand (read+write) MSHR misses
1561 system.cpu.l2cache.demand_mshr_misses::total 185019 # number of demand (read+write) MSHR misses
1562 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses
1563 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1564 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16084 # number of overall MSHR misses
1565 system.cpu.l2cache.overall_mshr_misses::cpu.data 168869 # number of overall MSHR misses
1566 system.cpu.l2cache.overall_mshr_misses::total 185019 # number of overall MSHR misses
1567 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5166251 # number of ReadReq MSHR miss cycles
1568 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 312500 # number of ReadReq MSHR miss cycles
1569 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1091253760 # number of ReadReq MSHR miss cycles
1570 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2471371556 # number of ReadReq MSHR miss cycles
1571 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3568104067 # number of ReadReq MSHR miss cycles
1572 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15558435 # number of UpgradeReq MSHR miss cycles
1573 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15558435 # number of UpgradeReq MSHR miss cycles
1574 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7786682845 # number of ReadExReq MSHR miss cycles
1575 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7786682845 # number of ReadExReq MSHR miss cycles
1576 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5166251 # number of demand (read+write) MSHR miss cycles
1577 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) MSHR miss cycles
1578 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1091253760 # number of demand (read+write) MSHR miss cycles
1579 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10258054401 # number of demand (read+write) MSHR miss cycles
1580 system.cpu.l2cache.demand_mshr_miss_latency::total 11354786912 # number of demand (read+write) MSHR miss cycles
1581 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5166251 # number of overall MSHR miss cycles
1582 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 312500 # number of overall MSHR miss cycles
1583 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1091253760 # number of overall MSHR miss cycles
1584 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10258054401 # number of overall MSHR miss cycles
1585 system.cpu.l2cache.overall_mshr_miss_latency::total 11354786912 # number of overall MSHR miss cycles
1586 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250274500 # number of ReadReq MSHR uncacheable cycles
1587 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250274500 # number of ReadReq MSHR uncacheable cycles
1588 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370476500 # number of WriteReq MSHR uncacheable cycles
1589 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370476500 # number of WriteReq MSHR uncacheable cycles
1590 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620751000 # number of overall MSHR uncacheable cycles
1591 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620751000 # number of overall MSHR uncacheable cycles
1592 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for ReadReq accesses
1593 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for ReadReq accesses
1594 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for ReadReq accesses
1595 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026273 # mshr miss rate for ReadReq accesses
1596 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021725 # mshr miss rate for ReadReq accesses
1597 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819617 # mshr miss rate for UpgradeReq accesses
1598 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819617 # mshr miss rate for UpgradeReq accesses
1599 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461479 # mshr miss rate for ReadExReq accesses
1600 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461479 # mshr miss rate for ReadExReq accesses
1601 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for demand accesses
1602 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for demand accesses
1603 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for demand accesses
1604 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for demand accesses
1605 system.cpu.l2cache.demand_mshr_miss_rate::total 0.068862 # mshr miss rate for demand accesses
1606 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for overall accesses
1607 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for overall accesses
1608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for overall accesses
1609 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for overall accesses
1610 system.cpu.l2cache.overall_mshr_miss_rate::total 0.068862 # mshr miss rate for overall accesses
1611 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average ReadReq mshr miss latency
1612 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
1613 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397 # average ReadReq mshr miss latency
1614 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612 # average ReadReq mshr miss latency
1615 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373 # average ReadReq mshr miss latency
1616 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726 # average UpgradeReq mshr miss latency
1617 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726 # average UpgradeReq mshr miss latency
1618 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543 # average ReadExReq mshr miss latency
1619 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543 # average ReadExReq mshr miss latency
1620 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency
1621 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
1622 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency
1623 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency
1624 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency
1625 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency
1626 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
1627 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency
1628 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency
1629 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency
1630 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1631 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1632 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1633 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1634 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1635 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1636 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1637 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1638 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1640 ---------- End Simulation Statistics ----------
projects / gem5.git / blob