2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.121937 # Number of seconds simulated
4 sim_ticks 5121937205500 # Number of ticks simulated
5 final_tick 5121937205500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 250170 # Simulator instruction rate (inst/s)
8 host_op_rate 494496 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 3139783576 # Simulator tick rate (ticks/s)
10 host_mem_usage 754660 # Number of bytes of host memory used
11 host_seconds 1631.30 # Real time elapsed on the host
12 sim_insts 408103625 # Number of instructions simulated
13 sim_ops 806672783 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.inst 1046784 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu.data 10762752 # Number of bytes read from this memory
20 system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
21 system.physmem.bytes_read::total 11842240 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read::cpu.inst 1046784 # Number of instructions bytes read from this memory
23 system.physmem.bytes_inst_read::total 1046784 # Number of instructions bytes read from this memory
24 system.physmem.bytes_written::writebacks 9571648 # Number of bytes written to this memory
25 system.physmem.bytes_written::total 9571648 # Number of bytes written to this memory
26 system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.inst 16356 # Number of read requests responded to by this memory
29 system.physmem.num_reads::cpu.data 168168 # Number of read requests responded to by this memory
30 system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
31 system.physmem.num_reads::total 185035 # Number of read requests responded to by this memory
32 system.physmem.num_writes::writebacks 149557 # Number of write requests responded to by this memory
33 system.physmem.num_writes::total 149557 # Number of write requests responded to by this memory
34 system.physmem.bw_read::cpu.dtb.walker 775 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.inst 204373 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::cpu.data 2101305 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s)
39 system.physmem.bw_read::total 2312063 # Total read bandwidth from this memory (bytes/s)
40 system.physmem.bw_inst_read::cpu.inst 204373 # Instruction read bandwidth from this memory (bytes/s)
41 system.physmem.bw_inst_read::total 204373 # Instruction read bandwidth from this memory (bytes/s)
42 system.physmem.bw_write::writebacks 1868755 # Write bandwidth from this memory (bytes/s)
43 system.physmem.bw_write::total 1868755 # Write bandwidth from this memory (bytes/s)
44 system.physmem.bw_total::writebacks 1868755 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.dtb.walker 775 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.inst 204373 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::cpu.data 2101305 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s)
50 system.physmem.bw_total::total 4180818 # Total bandwidth to/from this memory (bytes/s)
51 system.physmem.readReqs 185035 # Number of read requests accepted
52 system.physmem.writeReqs 196277 # Number of write requests accepted
53 system.physmem.readBursts 185035 # Number of DRAM read bursts, including those serviced by the write queue
54 system.physmem.writeBursts 196277 # Number of DRAM write bursts, including those merged in the write queue
55 system.physmem.bytesReadDRAM 11833600 # Total number of bytes read from DRAM
56 system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue
57 system.physmem.bytesWritten 12404928 # Total number of bytes written to DRAM
58 system.physmem.bytesReadSys 11842240 # Total read bytes from the system interface side
59 system.physmem.bytesWrittenSys 12561728 # Total written bytes from the system interface side
60 system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue
61 system.physmem.mergedWrBursts 2419 # Number of DRAM write bursts merged with an existing one
62 system.physmem.neitherReadNorWriteReqs 1772 # Number of requests that are neither read nor write
63 system.physmem.perBankRdBursts::0 11869 # Per bank write bursts
64 system.physmem.perBankRdBursts::1 11279 # Per bank write bursts
65 system.physmem.perBankRdBursts::2 11900 # Per bank write bursts
66 system.physmem.perBankRdBursts::3 11555 # Per bank write bursts
67 system.physmem.perBankRdBursts::4 12140 # Per bank write bursts
68 system.physmem.perBankRdBursts::5 11427 # Per bank write bursts
69 system.physmem.perBankRdBursts::6 11446 # Per bank write bursts
70 system.physmem.perBankRdBursts::7 11418 # Per bank write bursts
71 system.physmem.perBankRdBursts::8 11156 # Per bank write bursts
72 system.physmem.perBankRdBursts::9 11288 # Per bank write bursts
73 system.physmem.perBankRdBursts::10 11167 # Per bank write bursts
74 system.physmem.perBankRdBursts::11 11604 # Per bank write bursts
75 system.physmem.perBankRdBursts::12 11474 # Per bank write bursts
76 system.physmem.perBankRdBursts::13 12255 # Per bank write bursts
77 system.physmem.perBankRdBursts::14 11757 # Per bank write bursts
78 system.physmem.perBankRdBursts::15 11165 # Per bank write bursts
79 system.physmem.perBankWrBursts::0 12900 # Per bank write bursts
80 system.physmem.perBankWrBursts::1 13064 # Per bank write bursts
81 system.physmem.perBankWrBursts::2 11983 # Per bank write bursts
82 system.physmem.perBankWrBursts::3 10698 # Per bank write bursts
83 system.physmem.perBankWrBursts::4 10899 # Per bank write bursts
84 system.physmem.perBankWrBursts::5 11057 # Per bank write bursts
85 system.physmem.perBankWrBursts::6 11263 # Per bank write bursts
86 system.physmem.perBankWrBursts::7 11237 # Per bank write bursts
87 system.physmem.perBankWrBursts::8 11985 # Per bank write bursts
88 system.physmem.perBankWrBursts::9 12151 # Per bank write bursts
89 system.physmem.perBankWrBursts::10 12710 # Per bank write bursts
90 system.physmem.perBankWrBursts::11 12714 # Per bank write bursts
91 system.physmem.perBankWrBursts::12 13328 # Per bank write bursts
92 system.physmem.perBankWrBursts::13 13119 # Per bank write bursts
93 system.physmem.perBankWrBursts::14 12767 # Per bank write bursts
94 system.physmem.perBankWrBursts::15 11952 # Per bank write bursts
95 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96 system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
97 system.physmem.totGap 5121937091000 # Total gap between requests
98 system.physmem.readPktSize::0 0 # Read request sizes (log2)
99 system.physmem.readPktSize::1 0 # Read request sizes (log2)
100 system.physmem.readPktSize::2 0 # Read request sizes (log2)
101 system.physmem.readPktSize::3 0 # Read request sizes (log2)
102 system.physmem.readPktSize::4 0 # Read request sizes (log2)
103 system.physmem.readPktSize::5 0 # Read request sizes (log2)
104 system.physmem.readPktSize::6 185035 # Read request sizes (log2)
105 system.physmem.writePktSize::0 0 # Write request sizes (log2)
106 system.physmem.writePktSize::1 0 # Write request sizes (log2)
107 system.physmem.writePktSize::2 0 # Write request sizes (log2)
108 system.physmem.writePktSize::3 0 # Write request sizes (log2)
109 system.physmem.writePktSize::4 0 # Write request sizes (log2)
110 system.physmem.writePktSize::5 0 # Write request sizes (log2)
111 system.physmem.writePktSize::6 196277 # Write request sizes (log2)
112 system.physmem.rdQLenPdf::0 170268 # What read queue length does an incoming req see
113 system.physmem.rdQLenPdf::1 11906 # What read queue length does an incoming req see
114 system.physmem.rdQLenPdf::2 2015 # What read queue length does an incoming req see
115 system.physmem.rdQLenPdf::3 383 # What read queue length does an incoming req see
116 system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see
117 system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
118 system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
119 system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see
120 system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144 system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
145 system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
146 system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
147 system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
148 system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
149 system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
150 system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
151 system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152 system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153 system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::15 2596 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::16 4963 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::17 9714 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::18 11101 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::19 11484 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::20 12594 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::21 13080 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::22 14093 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::23 13730 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::24 14384 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::25 13174 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::26 12623 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::27 11181 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::28 10537 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::29 8939 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::30 8632 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::31 8525 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::33 450 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::35 334 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::37 242 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::38 221 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::39 209 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::41 227 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::43 187 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
208 system.physmem.bytesPerActivate::samples 74867 # Bytes accessed per row activation
209 system.physmem.bytesPerActivate::mean 323.753643 # Bytes accessed per row activation
210 system.physmem.bytesPerActivate::gmean 187.995922 # Bytes accessed per row activation
211 system.physmem.bytesPerActivate::stdev 341.769329 # Bytes accessed per row activation
212 system.physmem.bytesPerActivate::0-127 27720 37.03% 37.03% # Bytes accessed per row activation
213 system.physmem.bytesPerActivate::128-255 17254 23.05% 60.07% # Bytes accessed per row activation
214 system.physmem.bytesPerActivate::256-383 7564 10.10% 70.18% # Bytes accessed per row activation
215 system.physmem.bytesPerActivate::384-511 4205 5.62% 75.79% # Bytes accessed per row activation
216 system.physmem.bytesPerActivate::512-639 3013 4.02% 79.82% # Bytes accessed per row activation
217 system.physmem.bytesPerActivate::640-767 2021 2.70% 82.52% # Bytes accessed per row activation
218 system.physmem.bytesPerActivate::768-895 1360 1.82% 84.33% # Bytes accessed per row activation
219 system.physmem.bytesPerActivate::896-1023 1151 1.54% 85.87% # Bytes accessed per row activation
220 system.physmem.bytesPerActivate::1024-1151 10579 14.13% 100.00% # Bytes accessed per row activation
221 system.physmem.bytesPerActivate::total 74867 # Bytes accessed per row activation
222 system.physmem.rdPerTurnAround::samples 7807 # Reads before turning the bus around for writes
223 system.physmem.rdPerTurnAround::mean 23.681312 # Reads before turning the bus around for writes
224 system.physmem.rdPerTurnAround::stdev 544.837786 # Reads before turning the bus around for writes
225 system.physmem.rdPerTurnAround::0-2047 7806 99.99% 99.99% # Reads before turning the bus around for writes
226 system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227 system.physmem.rdPerTurnAround::total 7807 # Reads before turning the bus around for writes
228 system.physmem.wrPerTurnAround::samples 7807 # Writes before turning the bus around for reads
229 system.physmem.wrPerTurnAround::mean 24.827334 # Writes before turning the bus around for reads
230 system.physmem.wrPerTurnAround::gmean 20.378246 # Writes before turning the bus around for reads
231 system.physmem.wrPerTurnAround::stdev 23.718812 # Writes before turning the bus around for reads
232 system.physmem.wrPerTurnAround::16-19 6359 81.45% 81.45% # Writes before turning the bus around for reads
233 system.physmem.wrPerTurnAround::20-23 60 0.77% 82.22% # Writes before turning the bus around for reads
234 system.physmem.wrPerTurnAround::24-27 16 0.20% 82.43% # Writes before turning the bus around for reads
235 system.physmem.wrPerTurnAround::28-31 274 3.51% 85.94% # Writes before turning the bus around for reads
236 system.physmem.wrPerTurnAround::32-35 187 2.40% 88.33% # Writes before turning the bus around for reads
237 system.physmem.wrPerTurnAround::36-39 50 0.64% 88.97% # Writes before turning the bus around for reads
238 system.physmem.wrPerTurnAround::40-43 34 0.44% 89.41% # Writes before turning the bus around for reads
239 system.physmem.wrPerTurnAround::44-47 41 0.53% 89.93% # Writes before turning the bus around for reads
240 system.physmem.wrPerTurnAround::48-51 177 2.27% 92.20% # Writes before turning the bus around for reads
241 system.physmem.wrPerTurnAround::52-55 17 0.22% 92.42% # Writes before turning the bus around for reads
242 system.physmem.wrPerTurnAround::56-59 12 0.15% 92.57% # Writes before turning the bus around for reads
243 system.physmem.wrPerTurnAround::60-63 13 0.17% 92.74% # Writes before turning the bus around for reads
244 system.physmem.wrPerTurnAround::64-67 35 0.45% 93.19% # Writes before turning the bus around for reads
245 system.physmem.wrPerTurnAround::68-71 16 0.20% 93.39% # Writes before turning the bus around for reads
246 system.physmem.wrPerTurnAround::72-75 8 0.10% 93.49% # Writes before turning the bus around for reads
247 system.physmem.wrPerTurnAround::76-79 51 0.65% 94.15% # Writes before turning the bus around for reads
248 system.physmem.wrPerTurnAround::80-83 104 1.33% 95.48% # Writes before turning the bus around for reads
249 system.physmem.wrPerTurnAround::84-87 7 0.09% 95.57% # Writes before turning the bus around for reads
250 system.physmem.wrPerTurnAround::88-91 10 0.13% 95.70% # Writes before turning the bus around for reads
251 system.physmem.wrPerTurnAround::92-95 27 0.35% 96.04% # Writes before turning the bus around for reads
252 system.physmem.wrPerTurnAround::96-99 148 1.90% 97.94% # Writes before turning the bus around for reads
253 system.physmem.wrPerTurnAround::100-103 8 0.10% 98.04% # Writes before turning the bus around for reads
254 system.physmem.wrPerTurnAround::104-107 6 0.08% 98.12% # Writes before turning the bus around for reads
255 system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::112-115 33 0.42% 98.57% # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::116-119 2 0.03% 98.59% # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::120-123 12 0.15% 98.74% # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::124-127 3 0.04% 98.78% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::128-131 28 0.36% 99.14% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::132-135 4 0.05% 99.19% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::140-143 6 0.08% 99.27% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::144-147 12 0.15% 99.42% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::148-151 3 0.04% 99.46% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::152-155 3 0.04% 99.50% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::156-159 7 0.09% 99.59% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::160-163 8 0.10% 99.69% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::168-171 2 0.03% 99.72% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::172-175 3 0.04% 99.76% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::176-179 4 0.05% 99.81% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::180-183 1 0.01% 99.82% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::184-187 1 0.01% 99.83% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::188-191 2 0.03% 99.86% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::192-195 1 0.01% 99.87% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::204-207 4 0.05% 99.92% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::212-215 2 0.03% 99.95% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::232-235 1 0.01% 99.99% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::total 7807 # Writes before turning the bus around for reads
282 system.physmem.totQLat 1977045500 # Total ticks spent queuing
283 system.physmem.totMemAccLat 5443920500 # Total ticks spent from burst creation until serviced by the DRAM
284 system.physmem.totBusLat 924500000 # Total ticks spent in databus transfers
285 system.physmem.avgQLat 10692.51 # Average queueing delay per DRAM burst
286 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
287 system.physmem.avgMemAccLat 29442.51 # Average memory access latency per DRAM burst
288 system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
289 system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s
290 system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s
291 system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
292 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
293 system.physmem.busUtil 0.04 # Data bus utilization in percentage
294 system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
295 system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
296 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
297 system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing
298 system.physmem.readRowHits 151994 # Number of row buffer hits during reads
299 system.physmem.writeRowHits 151865 # Number of row buffer hits during writes
300 system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads
301 system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes
302 system.physmem.avgGap 13432404.67 # Average gap between requests
303 system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined
304 system.physmem_0.actEnergy 281753640 # Energy for activate commands per rank (pJ)
305 system.physmem_0.preEnergy 153734625 # Energy for precharge commands per rank (pJ)
306 system.physmem_0.readEnergy 725665200 # Energy for read commands per rank (pJ)
307 system.physmem_0.writeEnergy 603294480 # Energy for write commands per rank (pJ)
308 system.physmem_0.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ)
309 system.physmem_0.actBackEnergy 129490880310 # Energy for active background per rank (pJ)
310 system.physmem_0.preBackEnergy 2959572897750 # Energy for precharge background per rank (pJ)
311 system.physmem_0.totalEnergy 3425368148085 # Total energy per rank (pJ)
312 system.physmem_0.averagePower 668.764386 # Core power per rank (mW)
313 system.physmem_0.memoryStateTime::IDLE 4923440733500 # Time in different power states
314 system.physmem_0.memoryStateTime::REF 171032680000 # Time in different power states
315 system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
316 system.physmem_0.memoryStateTime::ACT 27462249000 # Time in different power states
317 system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
318 system.physmem_1.actEnergy 284240880 # Energy for activate commands per rank (pJ)
319 system.physmem_1.preEnergy 155091750 # Energy for precharge commands per rank (pJ)
320 system.physmem_1.readEnergy 716547000 # Energy for read commands per rank (pJ)
321 system.physmem_1.writeEnergy 652704480 # Energy for write commands per rank (pJ)
322 system.physmem_1.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ)
323 system.physmem_1.actBackEnergy 129160456155 # Energy for active background per rank (pJ)
324 system.physmem_1.preBackEnergy 2959862743500 # Energy for precharge background per rank (pJ)
325 system.physmem_1.totalEnergy 3425371705845 # Total energy per rank (pJ)
326 system.physmem_1.averagePower 668.765080 # Core power per rank (mW)
327 system.physmem_1.memoryStateTime::IDLE 4923925616750 # Time in different power states
328 system.physmem_1.memoryStateTime::REF 171032680000 # Time in different power states
329 system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
330 system.physmem_1.memoryStateTime::ACT 26978805250 # Time in different power states
331 system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
332 system.cpu.branchPred.lookups 86925803 # Number of BP lookups
333 system.cpu.branchPred.condPredicted 86925803 # Number of conditional branches predicted
334 system.cpu.branchPred.condIncorrect 896443 # Number of conditional branches incorrect
335 system.cpu.branchPred.BTBLookups 80098191 # Number of BTB lookups
336 system.cpu.branchPred.BTBHits 78212465 # Number of BTB hits
337 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
338 system.cpu.branchPred.BTBHitPct 97.645732 # BTB Hit Percentage
339 system.cpu.branchPred.usedRAS 1561001 # Number of times the RAS was used to get a target.
340 system.cpu.branchPred.RASInCorrect 180305 # Number of incorrect RAS predictions.
341 system.cpu_clk_domain.clock 500 # Clock period in ticks
342 system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
343 system.cpu.numCycles 449601109 # number of cpu cycles simulated
344 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
345 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
346 system.cpu.fetch.icacheStallCycles 27685322 # Number of cycles fetch is stalled on an Icache miss
347 system.cpu.fetch.Insts 429319828 # Number of instructions fetch has processed
348 system.cpu.fetch.Branches 86925803 # Number of branches that fetch encountered
349 system.cpu.fetch.predictedBranches 79773466 # Number of branches that fetch has predicted taken
350 system.cpu.fetch.Cycles 418005810 # Number of cycles fetch has run and was not squashing or blocked
351 system.cpu.fetch.SquashCycles 1881156 # Number of cycles fetch has spent squashing
352 system.cpu.fetch.TlbCycles 145066 # Number of cycles fetch has spent waiting for tlb
353 system.cpu.fetch.MiscStallCycles 56340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
354 system.cpu.fetch.PendingTrapStallCycles 216419 # Number of stall cycles due to pending traps
355 system.cpu.fetch.PendingQuiesceStallCycles 69 # Number of stall cycles due to pending quiesce instructions
356 system.cpu.fetch.IcacheWaitRetryStallCycles 534 # Number of stall cycles due to full MSHR
357 system.cpu.fetch.CacheLines 9181154 # Number of cache lines fetched
358 system.cpu.fetch.IcacheSquashes 448969 # Number of outstanding Icache misses that were squashed
359 system.cpu.fetch.ItlbSquashes 4854 # Number of outstanding ITLB misses that were squashed
360 system.cpu.fetch.rateDist::samples 447050138 # Number of instructions fetched each cycle (Total)
361 system.cpu.fetch.rateDist::mean 1.894862 # Number of instructions fetched each cycle (Total)
362 system.cpu.fetch.rateDist::stdev 3.052352 # Number of instructions fetched each cycle (Total)
363 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
364 system.cpu.fetch.rateDist::0 281515886 62.97% 62.97% # Number of instructions fetched each cycle (Total)
365 system.cpu.fetch.rateDist::1 2210439 0.49% 63.47% # Number of instructions fetched each cycle (Total)
366 system.cpu.fetch.rateDist::2 72204596 16.15% 79.62% # Number of instructions fetched each cycle (Total)
367 system.cpu.fetch.rateDist::3 1602689 0.36% 79.98% # Number of instructions fetched each cycle (Total)
368 system.cpu.fetch.rateDist::4 2146844 0.48% 80.46% # Number of instructions fetched each cycle (Total)
369 system.cpu.fetch.rateDist::5 2305649 0.52% 80.97% # Number of instructions fetched each cycle (Total)
370 system.cpu.fetch.rateDist::6 1524322 0.34% 81.31% # Number of instructions fetched each cycle (Total)
371 system.cpu.fetch.rateDist::7 1908424 0.43% 81.74% # Number of instructions fetched each cycle (Total)
372 system.cpu.fetch.rateDist::8 81631289 18.26% 100.00% # Number of instructions fetched each cycle (Total)
373 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
374 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
375 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
376 system.cpu.fetch.rateDist::total 447050138 # Number of instructions fetched each cycle (Total)
377 system.cpu.fetch.branchRate 0.193340 # Number of branch fetches per cycle
378 system.cpu.fetch.rate 0.954891 # Number of inst fetches per cycle
379 system.cpu.decode.IdleCycles 23043701 # Number of cycles decode is idle
380 system.cpu.decode.BlockedCycles 264854286 # Number of cycles decode is blocked
381 system.cpu.decode.RunCycles 150758526 # Number of cycles decode is running
382 system.cpu.decode.UnblockCycles 7453047 # Number of cycles decode is unblocking
383 system.cpu.decode.SquashCycles 940578 # Number of cycles decode is squashing
384 system.cpu.decode.DecodedInsts 838760021 # Number of instructions handled by decode
385 system.cpu.rename.SquashCycles 940578 # Number of cycles rename is squashing
386 system.cpu.rename.IdleCycles 25901615 # Number of cycles rename is idle
387 system.cpu.rename.BlockCycles 223330945 # Number of cycles rename is blocking
388 system.cpu.rename.serializeStallCycles 13194802 # count of cycles rename stalled for serializing inst
389 system.cpu.rename.RunCycles 154665359 # Number of cycles rename is running
390 system.cpu.rename.UnblockCycles 29016839 # Number of cycles rename is unblocking
391 system.cpu.rename.RenamedInsts 835288144 # Number of instructions processed by rename
392 system.cpu.rename.ROBFullEvents 480498 # Number of times rename has blocked due to ROB full
393 system.cpu.rename.IQFullEvents 12432167 # Number of times rename has blocked due to IQ full
394 system.cpu.rename.LQFullEvents 195018 # Number of times rename has blocked due to LQ full
395 system.cpu.rename.SQFullEvents 13714744 # Number of times rename has blocked due to SQ full
396 system.cpu.rename.RenamedOperands 997792221 # Number of destination operands rename has renamed
397 system.cpu.rename.RenameLookups 1814468169 # Number of register rename lookups that rename has made
398 system.cpu.rename.int_rename_lookups 1115407405 # Number of integer rename lookups
399 system.cpu.rename.fp_rename_lookups 373 # Number of floating rename lookups
400 system.cpu.rename.CommittedMaps 964705167 # Number of HB maps that are committed
401 system.cpu.rename.UndoneMaps 33087052 # Number of HB maps that are undone due to squashing
402 system.cpu.rename.serializingInsts 465878 # count of serializing insts renamed
403 system.cpu.rename.tempSerializingInsts 469687 # count of temporary serializing insts renamed
404 system.cpu.rename.skidInsts 39083891 # count of insts added to the skid buffer
405 system.cpu.memDep0.insertedLoads 17351329 # Number of loads inserted to the mem dependence unit.
406 system.cpu.memDep0.insertedStores 10177979 # Number of stores inserted to the mem dependence unit.
407 system.cpu.memDep0.conflictingLoads 1302580 # Number of conflicting loads.
408 system.cpu.memDep0.conflictingStores 1089364 # Number of conflicting stores.
409 system.cpu.iq.iqInstsAdded 829800190 # Number of instructions added to the IQ (excludes non-spec)
410 system.cpu.iq.iqNonSpecInstsAdded 1202669 # Number of non-speculative instructions added to the IQ
411 system.cpu.iq.iqInstsIssued 824540368 # Number of instructions issued
412 system.cpu.iq.iqSquashedInstsIssued 243435 # Number of squashed instructions issued
413 system.cpu.iq.iqSquashedInstsExamined 23398238 # Number of squashed instructions iterated over during squash; mainly for profiling
414 system.cpu.iq.iqSquashedOperandsExamined 36211142 # Number of squashed operands that are examined and possibly removed from graph
415 system.cpu.iq.iqSquashedNonSpecRemoved 151712 # Number of squashed non-spec instructions that were removed
416 system.cpu.iq.issued_per_cycle::samples 447050138 # Number of insts issued each cycle
417 system.cpu.iq.issued_per_cycle::mean 1.844402 # Number of insts issued each cycle
418 system.cpu.iq.issued_per_cycle::stdev 2.418243 # Number of insts issued each cycle
419 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
420 system.cpu.iq.issued_per_cycle::0 262726585 58.77% 58.77% # Number of insts issued each cycle
421 system.cpu.iq.issued_per_cycle::1 13876357 3.10% 61.87% # Number of insts issued each cycle
422 system.cpu.iq.issued_per_cycle::2 10104726 2.26% 64.13% # Number of insts issued each cycle
423 system.cpu.iq.issued_per_cycle::3 6925504 1.55% 65.68% # Number of insts issued each cycle
424 system.cpu.iq.issued_per_cycle::4 74353941 16.63% 82.31% # Number of insts issued each cycle
425 system.cpu.iq.issued_per_cycle::5 4450821 1.00% 83.31% # Number of insts issued each cycle
426 system.cpu.iq.issued_per_cycle::6 72845421 16.29% 99.60% # Number of insts issued each cycle
427 system.cpu.iq.issued_per_cycle::7 1198612 0.27% 99.87% # Number of insts issued each cycle
428 system.cpu.iq.issued_per_cycle::8 568171 0.13% 100.00% # Number of insts issued each cycle
429 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
430 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
431 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
432 system.cpu.iq.issued_per_cycle::total 447050138 # Number of insts issued each cycle
433 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
434 system.cpu.iq.fu_full::IntAlu 1991949 71.90% 71.90% # attempts to use FU when none available
435 system.cpu.iq.fu_full::IntMult 123 0.00% 71.91% # attempts to use FU when none available
436 system.cpu.iq.fu_full::IntDiv 1473 0.05% 71.96% # attempts to use FU when none available
437 system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available
438 system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available
439 system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.96% # attempts to use FU when none available
440 system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available
441 system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available
442 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available
443 system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available
444 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available
445 system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available
446 system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available
447 system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available
448 system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available
449 system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available
450 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available
451 system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available
452 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available
453 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available
454 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available
455 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available
456 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available
457 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available
458 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available
459 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available
460 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available
461 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available
462 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available
463 system.cpu.iq.fu_full::MemRead 615411 22.21% 94.17% # attempts to use FU when none available
464 system.cpu.iq.fu_full::MemWrite 161409 5.83% 100.00% # attempts to use FU when none available
465 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
466 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
467 system.cpu.iq.FU_type_0::No_OpClass 289852 0.04% 0.04% # Type of FU issued
468 system.cpu.iq.FU_type_0::IntAlu 796144481 96.56% 96.59% # Type of FU issued
469 system.cpu.iq.FU_type_0::IntMult 150888 0.02% 96.61% # Type of FU issued
470 system.cpu.iq.FU_type_0::IntDiv 125650 0.02% 96.62% # Type of FU issued
471 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
472 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
473 system.cpu.iq.FU_type_0::FloatCvt 123 0.00% 96.62% # Type of FU issued
474 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
475 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
476 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
477 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
478 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
479 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
480 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
481 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
482 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
483 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
484 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
485 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
486 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
487 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
488 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
489 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
490 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
491 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
492 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
493 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
494 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
495 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
496 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
497 system.cpu.iq.FU_type_0::MemRead 18436778 2.24% 98.86% # Type of FU issued
498 system.cpu.iq.FU_type_0::MemWrite 9392596 1.14% 100.00% # Type of FU issued
499 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
500 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
501 system.cpu.iq.FU_type_0::total 824540368 # Type of FU issued
502 system.cpu.iq.rate 1.833938 # Inst issue rate
503 system.cpu.iq.fu_busy_cnt 2770367 # FU busy when requested
504 system.cpu.iq.fu_busy_rate 0.003360 # FU busy rate (busy events/executed inst)
505 system.cpu.iq.int_inst_queue_reads 2099144137 # Number of integer instruction queue reads
506 system.cpu.iq.int_inst_queue_writes 854413357 # Number of integer instruction queue writes
507 system.cpu.iq.int_inst_queue_wakeup_accesses 819991210 # Number of integer instruction queue wakeup accesses
508 system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads
509 system.cpu.iq.fp_inst_queue_writes 510 # Number of floating instruction queue writes
510 system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses
511 system.cpu.iq.int_alu_accesses 827020625 # Number of integer alu accesses
512 system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses
513 system.cpu.iew.lsq.thread0.forwLoads 1864655 # Number of loads that had data forwarded from stores
514 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
515 system.cpu.iew.lsq.thread0.squashedLoads 3351077 # Number of loads squashed
516 system.cpu.iew.lsq.thread0.ignoredResponses 13836 # Number of memory responses ignored because the instruction is squashed
517 system.cpu.iew.lsq.thread0.memOrderViolation 14513 # Number of memory ordering violations
518 system.cpu.iew.lsq.thread0.squashedStores 1751193 # Number of stores squashed
519 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
520 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
521 system.cpu.iew.lsq.thread0.rescheduledLoads 2224299 # Number of loads that were rescheduled
522 system.cpu.iew.lsq.thread0.cacheBlocked 72996 # Number of times an access to memory failed due to the cache being blocked
523 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
524 system.cpu.iew.iewSquashCycles 940578 # Number of cycles IEW is squashing
525 system.cpu.iew.iewBlockCycles 205605732 # Number of cycles IEW is blocking
526 system.cpu.iew.iewUnblockCycles 9422457 # Number of cycles IEW is unblocking
527 system.cpu.iew.iewDispatchedInsts 831002859 # Number of instructions dispatched to IQ
528 system.cpu.iew.iewDispSquashedInsts 153624 # Number of squashed instructions skipped by dispatch
529 system.cpu.iew.iewDispLoadInsts 17351329 # Number of dispatched load instructions
530 system.cpu.iew.iewDispStoreInsts 10177979 # Number of dispatched store instructions
531 system.cpu.iew.iewDispNonSpecInsts 705669 # Number of dispatched non-speculative instructions
532 system.cpu.iew.iewIQFullEvents 415252 # Number of times the IQ has become full, causing a stall
533 system.cpu.iew.iewLSQFullEvents 8108448 # Number of times the LSQ has become full, causing a stall
534 system.cpu.iew.memOrderViolationEvents 14513 # Number of memory order violations
535 system.cpu.iew.predictedTakenIncorrect 513988 # Number of branches that were predicted taken incorrectly
536 system.cpu.iew.predictedNotTakenIncorrect 533382 # Number of branches that were predicted not taken incorrectly
537 system.cpu.iew.branchMispredicts 1047370 # Number of branch mispredicts detected at execute
538 system.cpu.iew.iewExecutedInsts 822936172 # Number of executed instructions
539 system.cpu.iew.iewExecLoadInsts 18038480 # Number of load instructions executed
540 system.cpu.iew.iewExecSquashedInsts 1469642 # Number of squashed instructions skipped in execute
541 system.cpu.iew.exec_swp 0 # number of swp insts executed
542 system.cpu.iew.exec_nop 0 # number of nop insts executed
543 system.cpu.iew.exec_refs 27207078 # number of memory reference insts executed
544 system.cpu.iew.exec_branches 83328554 # Number of branches executed
545 system.cpu.iew.exec_stores 9168598 # Number of stores executed
546 system.cpu.iew.exec_rate 1.830370 # Inst execution rate
547 system.cpu.iew.wb_sent 822433213 # cumulative count of insts sent to commit
548 system.cpu.iew.wb_count 819991395 # cumulative count of insts written-back
549 system.cpu.iew.wb_producers 641244168 # num instructions producing a value
550 system.cpu.iew.wb_consumers 1050921658 # num instructions consuming a value
551 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
552 system.cpu.iew.wb_rate 1.823820 # insts written-back per cycle
553 system.cpu.iew.wb_fanout 0.610173 # average fanout of values written-back
554 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
555 system.cpu.commit.commitSquashedInsts 24200169 # The number of squashed insts skipped by commit
556 system.cpu.commit.commitNonSpecStalls 1050957 # The number of times commit has been forced to stall to communicate backwards
557 system.cpu.commit.branchMispredicts 908606 # The number of times a branch was mispredicted
558 system.cpu.commit.committed_per_cycle::samples 443415424 # Number of insts commited each cycle
559 system.cpu.commit.committed_per_cycle::mean 1.819226 # Number of insts commited each cycle
560 system.cpu.commit.committed_per_cycle::stdev 2.675431 # Number of insts commited each cycle
561 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
562 system.cpu.commit.committed_per_cycle::0 272547704 61.47% 61.47% # Number of insts commited each cycle
563 system.cpu.commit.committed_per_cycle::1 11191107 2.52% 63.99% # Number of insts commited each cycle
564 system.cpu.commit.committed_per_cycle::2 3581688 0.81% 64.80% # Number of insts commited each cycle
565 system.cpu.commit.committed_per_cycle::3 74592593 16.82% 81.62% # Number of insts commited each cycle
566 system.cpu.commit.committed_per_cycle::4 2424395 0.55% 82.17% # Number of insts commited each cycle
567 system.cpu.commit.committed_per_cycle::5 1607477 0.36% 82.53% # Number of insts commited each cycle
568 system.cpu.commit.committed_per_cycle::6 945915 0.21% 82.74% # Number of insts commited each cycle
569 system.cpu.commit.committed_per_cycle::7 71066294 16.03% 98.77% # Number of insts commited each cycle
570 system.cpu.commit.committed_per_cycle::8 5458251 1.23% 100.00% # Number of insts commited each cycle
571 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
572 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
573 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
574 system.cpu.commit.committed_per_cycle::total 443415424 # Number of insts commited each cycle
575 system.cpu.commit.committedInsts 408103625 # Number of instructions committed
576 system.cpu.commit.committedOps 806672783 # Number of ops (including micro ops) committed
577 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
578 system.cpu.commit.refs 22427037 # Number of memory references committed
579 system.cpu.commit.loads 14000251 # Number of loads committed
580 system.cpu.commit.membars 475479 # Number of memory barriers committed
581 system.cpu.commit.branches 82225235 # Number of branches committed
582 system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
583 system.cpu.commit.int_insts 735463006 # Number of committed integer instructions.
584 system.cpu.commit.function_calls 1156113 # Number of function calls committed.
585 system.cpu.commit.op_class_0::No_OpClass 171674 0.02% 0.02% # Class of committed instruction
586 system.cpu.commit.op_class_0::IntAlu 783810008 97.17% 97.19% # Class of committed instruction
587 system.cpu.commit.op_class_0::IntMult 145072 0.02% 97.21% # Class of committed instruction
588 system.cpu.commit.op_class_0::IntDiv 121556 0.02% 97.22% # Class of committed instruction
589 system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
590 system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
591 system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
592 system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
593 system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
594 system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
595 system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
596 system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
597 system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
598 system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
599 system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
600 system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
601 system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
602 system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
603 system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
604 system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
605 system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
606 system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
607 system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
608 system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
609 system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
610 system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
611 system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
612 system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
613 system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
614 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
615 system.cpu.commit.op_class_0::MemRead 13997671 1.74% 98.96% # Class of committed instruction
616 system.cpu.commit.op_class_0::MemWrite 8426786 1.04% 100.00% # Class of committed instruction
617 system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
618 system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
619 system.cpu.commit.op_class_0::total 806672783 # Class of committed instruction
620 system.cpu.commit.bw_lim_events 5458251 # number cycles where commit BW limit reached
621 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
622 system.cpu.rob.rob_reads 1268751952 # The number of ROB reads
623 system.cpu.rob.rob_writes 1665400460 # The number of ROB writes
624 system.cpu.timesIdled 293768 # Number of times that the entire CPU went into an idle state and unscheduled itself
625 system.cpu.idleCycles 2550971 # Total number of cycles that the CPU has spent unscheduled due to idling
626 system.cpu.quiesceCycles 9794270972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
627 system.cpu.committedInsts 408103625 # Number of Instructions Simulated
628 system.cpu.committedOps 806672783 # Number of Ops (including micro ops) Simulated
629 system.cpu.cpi 1.101684 # CPI: Cycles Per Instruction
630 system.cpu.cpi_total 1.101684 # CPI: Total CPI of All Threads
631 system.cpu.ipc 0.907702 # IPC: Instructions Per Cycle
632 system.cpu.ipc_total 0.907702 # IPC: Total IPC of All Threads
633 system.cpu.int_regfile_reads 1092990942 # number of integer regfile reads
634 system.cpu.int_regfile_writes 656343554 # number of integer regfile writes
635 system.cpu.fp_regfile_reads 191 # number of floating regfile reads
636 system.cpu.cc_regfile_reads 416454943 # number of cc regfile reads
637 system.cpu.cc_regfile_writes 322187827 # number of cc regfile writes
638 system.cpu.misc_regfile_reads 265705543 # number of misc regfile reads
639 system.cpu.misc_regfile_writes 400219 # number of misc regfile writes
640 system.cpu.dcache.tags.replacements 1658771 # number of replacements
641 system.cpu.dcache.tags.tagsinuse 511.995092 # Cycle average of tags in use
642 system.cpu.dcache.tags.total_refs 19161993 # Total number of references to valid blocks.
643 system.cpu.dcache.tags.sampled_refs 1659283 # Sample count of references to valid blocks.
644 system.cpu.dcache.tags.avg_refs 11.548357 # Average number of references to valid blocks.
645 system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
646 system.cpu.dcache.tags.occ_blocks::cpu.data 511.995092 # Average occupied blocks per requestor
647 system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
648 system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
649 system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
650 system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
651 system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
652 system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
653 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
654 system.cpu.dcache.tags.tag_accesses 88441081 # Number of tag accesses
655 system.cpu.dcache.tags.data_accesses 88441081 # Number of data accesses
656 system.cpu.dcache.ReadReq_hits::cpu.data 11011311 # number of ReadReq hits
657 system.cpu.dcache.ReadReq_hits::total 11011311 # number of ReadReq hits
658 system.cpu.dcache.WriteReq_hits::cpu.data 8082990 # number of WriteReq hits
659 system.cpu.dcache.WriteReq_hits::total 8082990 # number of WriteReq hits
660 system.cpu.dcache.SoftPFReq_hits::cpu.data 64916 # number of SoftPFReq hits
661 system.cpu.dcache.SoftPFReq_hits::total 64916 # number of SoftPFReq hits
662 system.cpu.dcache.demand_hits::cpu.data 19094301 # number of demand (read+write) hits
663 system.cpu.dcache.demand_hits::total 19094301 # number of demand (read+write) hits
664 system.cpu.dcache.overall_hits::cpu.data 19159217 # number of overall hits
665 system.cpu.dcache.overall_hits::total 19159217 # number of overall hits
666 system.cpu.dcache.ReadReq_misses::cpu.data 1795762 # number of ReadReq misses
667 system.cpu.dcache.ReadReq_misses::total 1795762 # number of ReadReq misses
668 system.cpu.dcache.WriteReq_misses::cpu.data 334107 # number of WriteReq misses
669 system.cpu.dcache.WriteReq_misses::total 334107 # number of WriteReq misses
670 system.cpu.dcache.SoftPFReq_misses::cpu.data 406359 # number of SoftPFReq misses
671 system.cpu.dcache.SoftPFReq_misses::total 406359 # number of SoftPFReq misses
672 system.cpu.dcache.demand_misses::cpu.data 2129869 # number of demand (read+write) misses
673 system.cpu.dcache.demand_misses::total 2129869 # number of demand (read+write) misses
674 system.cpu.dcache.overall_misses::cpu.data 2536228 # number of overall misses
675 system.cpu.dcache.overall_misses::total 2536228 # number of overall misses
676 system.cpu.dcache.ReadReq_miss_latency::cpu.data 26474085005 # number of ReadReq miss cycles
677 system.cpu.dcache.ReadReq_miss_latency::total 26474085005 # number of ReadReq miss cycles
678 system.cpu.dcache.WriteReq_miss_latency::cpu.data 12834716256 # number of WriteReq miss cycles
679 system.cpu.dcache.WriteReq_miss_latency::total 12834716256 # number of WriteReq miss cycles
680 system.cpu.dcache.demand_miss_latency::cpu.data 39308801261 # number of demand (read+write) miss cycles
681 system.cpu.dcache.demand_miss_latency::total 39308801261 # number of demand (read+write) miss cycles
682 system.cpu.dcache.overall_miss_latency::cpu.data 39308801261 # number of overall miss cycles
683 system.cpu.dcache.overall_miss_latency::total 39308801261 # number of overall miss cycles
684 system.cpu.dcache.ReadReq_accesses::cpu.data 12807073 # number of ReadReq accesses(hits+misses)
685 system.cpu.dcache.ReadReq_accesses::total 12807073 # number of ReadReq accesses(hits+misses)
686 system.cpu.dcache.WriteReq_accesses::cpu.data 8417097 # number of WriteReq accesses(hits+misses)
687 system.cpu.dcache.WriteReq_accesses::total 8417097 # number of WriteReq accesses(hits+misses)
688 system.cpu.dcache.SoftPFReq_accesses::cpu.data 471275 # number of SoftPFReq accesses(hits+misses)
689 system.cpu.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses)
690 system.cpu.dcache.demand_accesses::cpu.data 21224170 # number of demand (read+write) accesses
691 system.cpu.dcache.demand_accesses::total 21224170 # number of demand (read+write) accesses
692 system.cpu.dcache.overall_accesses::cpu.data 21695445 # number of overall (read+write) accesses
693 system.cpu.dcache.overall_accesses::total 21695445 # number of overall (read+write) accesses
694 system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140216 # miss rate for ReadReq accesses
695 system.cpu.dcache.ReadReq_miss_rate::total 0.140216 # miss rate for ReadReq accesses
696 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039694 # miss rate for WriteReq accesses
697 system.cpu.dcache.WriteReq_miss_rate::total 0.039694 # miss rate for WriteReq accesses
698 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862255 # miss rate for SoftPFReq accesses
699 system.cpu.dcache.SoftPFReq_miss_rate::total 0.862255 # miss rate for SoftPFReq accesses
700 system.cpu.dcache.demand_miss_rate::cpu.data 0.100351 # miss rate for demand accesses
701 system.cpu.dcache.demand_miss_rate::total 0.100351 # miss rate for demand accesses
702 system.cpu.dcache.overall_miss_rate::cpu.data 0.116901 # miss rate for overall accesses
703 system.cpu.dcache.overall_miss_rate::total 0.116901 # miss rate for overall accesses
704 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14742.535484 # average ReadReq miss latency
705 system.cpu.dcache.ReadReq_avg_miss_latency::total 14742.535484 # average ReadReq miss latency
706 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38414.987582 # average WriteReq miss latency
707 system.cpu.dcache.WriteReq_avg_miss_latency::total 38414.987582 # average WriteReq miss latency
708 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18455.971358 # average overall miss latency
709 system.cpu.dcache.demand_avg_miss_latency::total 18455.971358 # average overall miss latency
710 system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.922518 # average overall miss latency
711 system.cpu.dcache.overall_avg_miss_latency::total 15498.922518 # average overall miss latency
712 system.cpu.dcache.blocked_cycles::no_mshrs 371080 # number of cycles access was blocked
713 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
714 system.cpu.dcache.blocked::no_mshrs 39978 # number of cycles access was blocked
715 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
716 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.282105 # average number of cycles each access was blocked
717 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
718 system.cpu.dcache.fast_writes 0 # number of fast writes performed
719 system.cpu.dcache.cache_copies 0 # number of cache copies performed
720 system.cpu.dcache.writebacks::writebacks 1560107 # number of writebacks
721 system.cpu.dcache.writebacks::total 1560107 # number of writebacks
722 system.cpu.dcache.ReadReq_mshr_hits::cpu.data 826960 # number of ReadReq MSHR hits
723 system.cpu.dcache.ReadReq_mshr_hits::total 826960 # number of ReadReq MSHR hits
724 system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44237 # number of WriteReq MSHR hits
725 system.cpu.dcache.WriteReq_mshr_hits::total 44237 # number of WriteReq MSHR hits
726 system.cpu.dcache.demand_mshr_hits::cpu.data 871197 # number of demand (read+write) MSHR hits
727 system.cpu.dcache.demand_mshr_hits::total 871197 # number of demand (read+write) MSHR hits
728 system.cpu.dcache.overall_mshr_hits::cpu.data 871197 # number of overall MSHR hits
729 system.cpu.dcache.overall_mshr_hits::total 871197 # number of overall MSHR hits
730 system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968802 # number of ReadReq MSHR misses
731 system.cpu.dcache.ReadReq_mshr_misses::total 968802 # number of ReadReq MSHR misses
732 system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289870 # number of WriteReq MSHR misses
733 system.cpu.dcache.WriteReq_mshr_misses::total 289870 # number of WriteReq MSHR misses
734 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402896 # number of SoftPFReq MSHR misses
735 system.cpu.dcache.SoftPFReq_mshr_misses::total 402896 # number of SoftPFReq MSHR misses
736 system.cpu.dcache.demand_mshr_misses::cpu.data 1258672 # number of demand (read+write) MSHR misses
737 system.cpu.dcache.demand_mshr_misses::total 1258672 # number of demand (read+write) MSHR misses
738 system.cpu.dcache.overall_mshr_misses::cpu.data 1661568 # number of overall MSHR misses
739 system.cpu.dcache.overall_mshr_misses::total 1661568 # number of overall MSHR misses
740 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12247021519 # number of ReadReq MSHR miss cycles
741 system.cpu.dcache.ReadReq_mshr_miss_latency::total 12247021519 # number of ReadReq MSHR miss cycles
742 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11168468751 # number of WriteReq MSHR miss cycles
743 system.cpu.dcache.WriteReq_mshr_miss_latency::total 11168468751 # number of WriteReq MSHR miss cycles
744 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5577776251 # number of SoftPFReq MSHR miss cycles
745 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5577776251 # number of SoftPFReq MSHR miss cycles
746 system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23415490270 # number of demand (read+write) MSHR miss cycles
747 system.cpu.dcache.demand_mshr_miss_latency::total 23415490270 # number of demand (read+write) MSHR miss cycles
748 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993266521 # number of overall MSHR miss cycles
749 system.cpu.dcache.overall_mshr_miss_latency::total 28993266521 # number of overall MSHR miss cycles
750 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97397501000 # number of ReadReq MSHR uncacheable cycles
751 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97397501000 # number of ReadReq MSHR uncacheable cycles
752 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2571147000 # number of WriteReq MSHR uncacheable cycles
753 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2571147000 # number of WriteReq MSHR uncacheable cycles
754 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99968648000 # number of overall MSHR uncacheable cycles
755 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99968648000 # number of overall MSHR uncacheable cycles
756 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075646 # mshr miss rate for ReadReq accesses
757 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075646 # mshr miss rate for ReadReq accesses
758 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034438 # mshr miss rate for WriteReq accesses
759 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034438 # mshr miss rate for WriteReq accesses
760 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854906 # mshr miss rate for SoftPFReq accesses
761 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854906 # mshr miss rate for SoftPFReq accesses
762 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059304 # mshr miss rate for demand accesses
763 system.cpu.dcache.demand_mshr_miss_rate::total 0.059304 # mshr miss rate for demand accesses
764 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076586 # mshr miss rate for overall accesses
765 system.cpu.dcache.overall_mshr_miss_rate::total 0.076586 # mshr miss rate for overall accesses
766 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171 # average ReadReq mshr miss latency
767 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171 # average ReadReq mshr miss latency
768 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935 # average WriteReq mshr miss latency
769 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935 # average WriteReq mshr miss latency
770 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558 # average SoftPFReq mshr miss latency
771 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558 # average SoftPFReq mshr miss latency
772 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755 # average overall mshr miss latency
773 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755 # average overall mshr miss latency
774 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936 # average overall mshr miss latency
775 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936 # average overall mshr miss latency
776 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
777 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
778 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
779 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
780 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
781 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
782 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
783 system.cpu.dtb_walker_cache.tags.replacements 75411 # number of replacements
784 system.cpu.dtb_walker_cache.tags.tagsinuse 15.808771 # Cycle average of tags in use
785 system.cpu.dtb_walker_cache.tags.total_refs 114018 # Total number of references to valid blocks.
786 system.cpu.dtb_walker_cache.tags.sampled_refs 75427 # Sample count of references to valid blocks.
787 system.cpu.dtb_walker_cache.tags.avg_refs 1.511634 # Average number of references to valid blocks.
788 system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500 # Cycle when the warmup percentage was hit.
789 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.808771 # Average occupied blocks per requestor
790 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988048 # Average percentage of cache occupancy
791 system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988048 # Average percentage of cache occupancy
792 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
793 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
794 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
795 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
796 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
797 system.cpu.dtb_walker_cache.tags.tag_accesses 457557 # Number of tag accesses
798 system.cpu.dtb_walker_cache.tags.data_accesses 457557 # Number of data accesses
799 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114018 # number of ReadReq hits
800 system.cpu.dtb_walker_cache.ReadReq_hits::total 114018 # number of ReadReq hits
801 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114018 # number of demand (read+write) hits
802 system.cpu.dtb_walker_cache.demand_hits::total 114018 # number of demand (read+write) hits
803 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114018 # number of overall hits
804 system.cpu.dtb_walker_cache.overall_hits::total 114018 # number of overall hits
805 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 76507 # number of ReadReq misses
806 system.cpu.dtb_walker_cache.ReadReq_misses::total 76507 # number of ReadReq misses
807 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 76507 # number of demand (read+write) misses
808 system.cpu.dtb_walker_cache.demand_misses::total 76507 # number of demand (read+write) misses
809 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 76507 # number of overall misses
810 system.cpu.dtb_walker_cache.overall_misses::total 76507 # number of overall misses
811 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935770691 # number of ReadReq miss cycles
812 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935770691 # number of ReadReq miss cycles
813 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935770691 # number of demand (read+write) miss cycles
814 system.cpu.dtb_walker_cache.demand_miss_latency::total 935770691 # number of demand (read+write) miss cycles
815 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935770691 # number of overall miss cycles
816 system.cpu.dtb_walker_cache.overall_miss_latency::total 935770691 # number of overall miss cycles
817 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190525 # number of ReadReq accesses(hits+misses)
818 system.cpu.dtb_walker_cache.ReadReq_accesses::total 190525 # number of ReadReq accesses(hits+misses)
819 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190525 # number of demand (read+write) accesses
820 system.cpu.dtb_walker_cache.demand_accesses::total 190525 # number of demand (read+write) accesses
821 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190525 # number of overall (read+write) accesses
822 system.cpu.dtb_walker_cache.overall_accesses::total 190525 # number of overall (read+write) accesses
823 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.401559 # miss rate for ReadReq accesses
824 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.401559 # miss rate for ReadReq accesses
825 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.401559 # miss rate for demand accesses
826 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.401559 # miss rate for demand accesses
827 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.401559 # miss rate for overall accesses
828 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.401559 # miss rate for overall accesses
829 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177422 # average ReadReq miss latency
830 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177422 # average ReadReq miss latency
831 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency
832 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177422 # average overall miss latency
833 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency
834 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177422 # average overall miss latency
835 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
838 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
839 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
842 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
843 system.cpu.dtb_walker_cache.writebacks::writebacks 22022 # number of writebacks
844 system.cpu.dtb_walker_cache.writebacks::total 22022 # number of writebacks
845 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 76507 # number of ReadReq MSHR misses
846 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 76507 # number of ReadReq MSHR misses
847 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 76507 # number of demand (read+write) MSHR misses
848 system.cpu.dtb_walker_cache.demand_mshr_misses::total 76507 # number of demand (read+write) MSHR misses
849 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 76507 # number of overall MSHR misses
850 system.cpu.dtb_walker_cache.overall_mshr_misses::total 76507 # number of overall MSHR misses
851 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 782624451 # number of ReadReq MSHR miss cycles
852 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 782624451 # number of ReadReq MSHR miss cycles
853 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 782624451 # number of demand (read+write) MSHR miss cycles
854 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 782624451 # number of demand (read+write) MSHR miss cycles
855 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 782624451 # number of overall MSHR miss cycles
856 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 782624451 # number of overall MSHR miss cycles
857 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for ReadReq accesses
858 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.401559 # mshr miss rate for ReadReq accesses
859 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for demand accesses
860 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.401559 # mshr miss rate for demand accesses
861 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for overall accesses
862 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.401559 # mshr miss rate for overall accesses
863 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average ReadReq mshr miss latency
864 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448952 # average ReadReq mshr miss latency
865 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency
866 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency
867 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency
868 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency
869 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
870 system.cpu.icache.tags.replacements 1000352 # number of replacements
871 system.cpu.icache.tags.tagsinuse 509.220531 # Cycle average of tags in use
872 system.cpu.icache.tags.total_refs 8118136 # Total number of references to valid blocks.
873 system.cpu.icache.tags.sampled_refs 1000864 # Sample count of references to valid blocks.
874 system.cpu.icache.tags.avg_refs 8.111128 # Average number of references to valid blocks.
875 system.cpu.icache.tags.warmup_cycle 147684343000 # Cycle when the warmup percentage was hit.
876 system.cpu.icache.tags.occ_blocks::cpu.inst 509.220531 # Average occupied blocks per requestor
877 system.cpu.icache.tags.occ_percent::cpu.inst 0.994571 # Average percentage of cache occupancy
878 system.cpu.icache.tags.occ_percent::total 0.994571 # Average percentage of cache occupancy
879 system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
880 system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
881 system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
882 system.cpu.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id
883 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
884 system.cpu.icache.tags.tag_accesses 10182088 # Number of tag accesses
885 system.cpu.icache.tags.data_accesses 10182088 # Number of data accesses
886 system.cpu.icache.ReadReq_hits::cpu.inst 8118136 # number of ReadReq hits
887 system.cpu.icache.ReadReq_hits::total 8118136 # number of ReadReq hits
888 system.cpu.icache.demand_hits::cpu.inst 8118136 # number of demand (read+write) hits
889 system.cpu.icache.demand_hits::total 8118136 # number of demand (read+write) hits
890 system.cpu.icache.overall_hits::cpu.inst 8118136 # number of overall hits
891 system.cpu.icache.overall_hits::total 8118136 # number of overall hits
892 system.cpu.icache.ReadReq_misses::cpu.inst 1063017 # number of ReadReq misses
893 system.cpu.icache.ReadReq_misses::total 1063017 # number of ReadReq misses
894 system.cpu.icache.demand_misses::cpu.inst 1063017 # number of demand (read+write) misses
895 system.cpu.icache.demand_misses::total 1063017 # number of demand (read+write) misses
896 system.cpu.icache.overall_misses::cpu.inst 1063017 # number of overall misses
897 system.cpu.icache.overall_misses::total 1063017 # number of overall misses
898 system.cpu.icache.ReadReq_miss_latency::cpu.inst 14764552848 # number of ReadReq miss cycles
899 system.cpu.icache.ReadReq_miss_latency::total 14764552848 # number of ReadReq miss cycles
900 system.cpu.icache.demand_miss_latency::cpu.inst 14764552848 # number of demand (read+write) miss cycles
901 system.cpu.icache.demand_miss_latency::total 14764552848 # number of demand (read+write) miss cycles
902 system.cpu.icache.overall_miss_latency::cpu.inst 14764552848 # number of overall miss cycles
903 system.cpu.icache.overall_miss_latency::total 14764552848 # number of overall miss cycles
904 system.cpu.icache.ReadReq_accesses::cpu.inst 9181153 # number of ReadReq accesses(hits+misses)
905 system.cpu.icache.ReadReq_accesses::total 9181153 # number of ReadReq accesses(hits+misses)
906 system.cpu.icache.demand_accesses::cpu.inst 9181153 # number of demand (read+write) accesses
907 system.cpu.icache.demand_accesses::total 9181153 # number of demand (read+write) accesses
908 system.cpu.icache.overall_accesses::cpu.inst 9181153 # number of overall (read+write) accesses
909 system.cpu.icache.overall_accesses::total 9181153 # number of overall (read+write) accesses
910 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115783 # miss rate for ReadReq accesses
911 system.cpu.icache.ReadReq_miss_rate::total 0.115783 # miss rate for ReadReq accesses
912 system.cpu.icache.demand_miss_rate::cpu.inst 0.115783 # miss rate for demand accesses
913 system.cpu.icache.demand_miss_rate::total 0.115783 # miss rate for demand accesses
914 system.cpu.icache.overall_miss_rate::cpu.inst 0.115783 # miss rate for overall accesses
915 system.cpu.icache.overall_miss_rate::total 0.115783 # miss rate for overall accesses
916 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13889.291374 # average ReadReq miss latency
917 system.cpu.icache.ReadReq_avg_miss_latency::total 13889.291374 # average ReadReq miss latency
918 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency
919 system.cpu.icache.demand_avg_miss_latency::total 13889.291374 # average overall miss latency
920 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency
921 system.cpu.icache.overall_avg_miss_latency::total 13889.291374 # average overall miss latency
922 system.cpu.icache.blocked_cycles::no_mshrs 7778 # number of cycles access was blocked
923 system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked
924 system.cpu.icache.blocked::no_mshrs 283 # number of cycles access was blocked
925 system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
926 system.cpu.icache.avg_blocked_cycles::no_mshrs 27.484099 # average number of cycles each access was blocked
927 system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
928 system.cpu.icache.fast_writes 0 # number of fast writes performed
929 system.cpu.icache.cache_copies 0 # number of cache copies performed
930 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62082 # number of ReadReq MSHR hits
931 system.cpu.icache.ReadReq_mshr_hits::total 62082 # number of ReadReq MSHR hits
932 system.cpu.icache.demand_mshr_hits::cpu.inst 62082 # number of demand (read+write) MSHR hits
933 system.cpu.icache.demand_mshr_hits::total 62082 # number of demand (read+write) MSHR hits
934 system.cpu.icache.overall_mshr_hits::cpu.inst 62082 # number of overall MSHR hits
935 system.cpu.icache.overall_mshr_hits::total 62082 # number of overall MSHR hits
936 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1000935 # number of ReadReq MSHR misses
937 system.cpu.icache.ReadReq_mshr_misses::total 1000935 # number of ReadReq MSHR misses
938 system.cpu.icache.demand_mshr_misses::cpu.inst 1000935 # number of demand (read+write) MSHR misses
939 system.cpu.icache.demand_mshr_misses::total 1000935 # number of demand (read+write) MSHR misses
940 system.cpu.icache.overall_mshr_misses::cpu.inst 1000935 # number of overall MSHR misses
941 system.cpu.icache.overall_mshr_misses::total 1000935 # number of overall MSHR misses
942 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12121618509 # number of ReadReq MSHR miss cycles
943 system.cpu.icache.ReadReq_mshr_miss_latency::total 12121618509 # number of ReadReq MSHR miss cycles
944 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12121618509 # number of demand (read+write) MSHR miss cycles
945 system.cpu.icache.demand_mshr_miss_latency::total 12121618509 # number of demand (read+write) MSHR miss cycles
946 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12121618509 # number of overall MSHR miss cycles
947 system.cpu.icache.overall_mshr_miss_latency::total 12121618509 # number of overall MSHR miss cycles
948 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for ReadReq accesses
949 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109021 # mshr miss rate for ReadReq accesses
950 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for demand accesses
951 system.cpu.icache.demand_mshr_miss_rate::total 0.109021 # mshr miss rate for demand accesses
952 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for overall accesses
953 system.cpu.icache.overall_mshr_miss_rate::total 0.109021 # mshr miss rate for overall accesses
954 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383 # average ReadReq mshr miss latency
955 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383 # average ReadReq mshr miss latency
956 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency
957 system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency
958 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency
959 system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency
960 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
961 system.cpu.itb_walker_cache.tags.replacements 14419 # number of replacements
962 system.cpu.itb_walker_cache.tags.tagsinuse 6.299272 # Cycle average of tags in use
963 system.cpu.itb_walker_cache.tags.total_refs 25752 # Total number of references to valid blocks.
964 system.cpu.itb_walker_cache.tags.sampled_refs 14435 # Sample count of references to valid blocks.
965 system.cpu.itb_walker_cache.tags.avg_refs 1.783997 # Average number of references to valid blocks.
966 system.cpu.itb_walker_cache.tags.warmup_cycle 5101096739000 # Cycle when the warmup percentage was hit.
967 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.299272 # Average occupied blocks per requestor
968 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.393704 # Average percentage of cache occupancy
969 system.cpu.itb_walker_cache.tags.occ_percent::total 0.393704 # Average percentage of cache occupancy
970 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
971 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
972 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
973 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
974 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
975 system.cpu.itb_walker_cache.tags.tag_accesses 97449 # Number of tag accesses
976 system.cpu.itb_walker_cache.tags.data_accesses 97449 # Number of data accesses
977 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25750 # number of ReadReq hits
978 system.cpu.itb_walker_cache.ReadReq_hits::total 25750 # number of ReadReq hits
979 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
980 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
981 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25752 # number of demand (read+write) hits
982 system.cpu.itb_walker_cache.demand_hits::total 25752 # number of demand (read+write) hits
983 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25752 # number of overall hits
984 system.cpu.itb_walker_cache.overall_hits::total 25752 # number of overall hits
985 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15315 # number of ReadReq misses
986 system.cpu.itb_walker_cache.ReadReq_misses::total 15315 # number of ReadReq misses
987 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15315 # number of demand (read+write) misses
988 system.cpu.itb_walker_cache.demand_misses::total 15315 # number of demand (read+write) misses
989 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15315 # number of overall misses
990 system.cpu.itb_walker_cache.overall_misses::total 15315 # number of overall misses
991 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 177860992 # number of ReadReq miss cycles
992 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 177860992 # number of ReadReq miss cycles
993 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 177860992 # number of demand (read+write) miss cycles
994 system.cpu.itb_walker_cache.demand_miss_latency::total 177860992 # number of demand (read+write) miss cycles
995 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 177860992 # number of overall miss cycles
996 system.cpu.itb_walker_cache.overall_miss_latency::total 177860992 # number of overall miss cycles
997 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41065 # number of ReadReq accesses(hits+misses)
998 system.cpu.itb_walker_cache.ReadReq_accesses::total 41065 # number of ReadReq accesses(hits+misses)
999 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
1000 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
1001 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41067 # number of demand (read+write) accesses
1002 system.cpu.itb_walker_cache.demand_accesses::total 41067 # number of demand (read+write) accesses
1003 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41067 # number of overall (read+write) accesses
1004 system.cpu.itb_walker_cache.overall_accesses::total 41067 # number of overall (read+write) accesses
1005 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372945 # miss rate for ReadReq accesses
1006 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372945 # miss rate for ReadReq accesses
1007 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372927 # miss rate for demand accesses
1008 system.cpu.itb_walker_cache.demand_miss_rate::total 0.372927 # miss rate for demand accesses
1009 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372927 # miss rate for overall accesses
1010 system.cpu.itb_walker_cache.overall_miss_rate::total 0.372927 # miss rate for overall accesses
1011 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11613.515638 # average ReadReq miss latency
1012 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11613.515638 # average ReadReq miss latency
1013 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency
1014 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11613.515638 # average overall miss latency
1015 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency
1016 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11613.515638 # average overall miss latency
1017 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1018 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1019 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
1020 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
1021 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1022 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1023 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
1024 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
1025 system.cpu.itb_walker_cache.writebacks::writebacks 3318 # number of writebacks
1026 system.cpu.itb_walker_cache.writebacks::total 3318 # number of writebacks
1027 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15315 # number of ReadReq MSHR misses
1028 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15315 # number of ReadReq MSHR misses
1029 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15315 # number of demand (read+write) MSHR misses
1030 system.cpu.itb_walker_cache.demand_mshr_misses::total 15315 # number of demand (read+write) MSHR misses
1031 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15315 # number of overall MSHR misses
1032 system.cpu.itb_walker_cache.overall_mshr_misses::total 15315 # number of overall MSHR misses
1033 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147213024 # number of ReadReq MSHR miss cycles
1034 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147213024 # number of ReadReq MSHR miss cycles
1035 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147213024 # number of demand (read+write) MSHR miss cycles
1036 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147213024 # number of demand (read+write) MSHR miss cycles
1037 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147213024 # number of overall MSHR miss cycles
1038 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147213024 # number of overall MSHR miss cycles
1039 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372945 # mshr miss rate for ReadReq accesses
1040 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372945 # mshr miss rate for ReadReq accesses
1041 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for demand accesses
1042 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372927 # mshr miss rate for demand accesses
1043 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for overall accesses
1044 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372927 # mshr miss rate for overall accesses
1045 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average ReadReq mshr miss latency
1046 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9612.342409 # average ReadReq mshr miss latency
1047 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency
1048 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency
1049 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency
1050 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency
1051 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
1052 system.cpu.l2cache.tags.replacements 112445 # number of replacements
1053 system.cpu.l2cache.tags.tagsinuse 64830.405135 # Cycle average of tags in use
1054 system.cpu.l2cache.tags.total_refs 3843138 # Total number of references to valid blocks.
1055 system.cpu.l2cache.tags.sampled_refs 176455 # Sample count of references to valid blocks.
1056 system.cpu.l2cache.tags.avg_refs 21.779706 # Average number of references to valid blocks.
1057 system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1058 system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670 # Average occupied blocks per requestor
1059 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.644782 # Average occupied blocks per requestor
1060 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.444532 # Average occupied blocks per requestor
1061 system.cpu.l2cache.tags.occ_blocks::cpu.inst 3208.377327 # Average occupied blocks per requestor
1062 system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824 # Average occupied blocks per requestor
1063 system.cpu.l2cache.tags.occ_percent::writebacks 0.768115 # Average percentage of cache occupancy
1064 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000223 # Average percentage of cache occupancy
1065 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy
1066 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048956 # Average percentage of cache occupancy
1067 system.cpu.l2cache.tags.occ_percent::cpu.data 0.171932 # Average percentage of cache occupancy
1068 system.cpu.l2cache.tags.occ_percent::total 0.989233 # Average percentage of cache occupancy
1069 system.cpu.l2cache.tags.occ_task_id_blocks::1024 64010 # Occupied blocks per task id
1070 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
1071 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 596 # Occupied blocks per task id
1072 system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id
1073 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7208 # Occupied blocks per task id
1074 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52806 # Occupied blocks per task id
1075 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976715 # Percentage of cache occupancy per task id
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1083 system.cpu.l2cache.Writeback_hits::writebacks 1585447 # number of Writeback hits
1084 system.cpu.l2cache.Writeback_hits::total 1585447 # number of Writeback hits
1085 system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
1086 system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
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1089 system.cpu.l2cache.demand_hits::cpu.dtb.walker 69111 # number of demand (read+write) hits
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1132 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5303750 # number of overall miss cycles
1133 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467500 # number of overall miss cycles
1134 system.cpu.l2cache.overall_miss_latency::cpu.inst 1250815250 # number of overall miss cycles
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1137 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69173 # number of ReadReq accesses(hits+misses)
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1139 system.cpu.l2cache.ReadReq_accesses::cpu.inst 1000818 # number of ReadReq accesses(hits+misses)
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1141 system.cpu.l2cache.ReadReq_accesses::total 2453773 # number of ReadReq accesses(hits+misses)
1142 system.cpu.l2cache.Writeback_accesses::writebacks 1585447 # number of Writeback accesses(hits+misses)
1143 system.cpu.l2cache.Writeback_accesses::total 1585447 # number of Writeback accesses(hits+misses)
1144 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1813 # number of UpgradeReq accesses(hits+misses)
1145 system.cpu.l2cache.UpgradeReq_accesses::total 1813 # number of UpgradeReq accesses(hits+misses)
1146 system.cpu.l2cache.ReadExReq_accesses::cpu.data 287737 # number of ReadExReq accesses(hits+misses)
1147 system.cpu.l2cache.ReadExReq_accesses::total 287737 # number of ReadExReq accesses(hits+misses)
1148 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69173 # number of demand (read+write) accesses
1149 system.cpu.l2cache.demand_accesses::cpu.itb.walker 12774 # number of demand (read+write) accesses
1150 system.cpu.l2cache.demand_accesses::cpu.inst 1000818 # number of demand (read+write) accesses
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1153 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69173 # number of overall (read+write) accesses
1154 system.cpu.l2cache.overall_accesses::cpu.itb.walker 12774 # number of overall (read+write) accesses
1155 system.cpu.l2cache.overall_accesses::cpu.inst 1000818 # number of overall (read+write) accesses
1156 system.cpu.l2cache.overall_accesses::cpu.data 1658745 # number of overall (read+write) accesses
1157 system.cpu.l2cache.overall_accesses::total 2741510 # number of overall (read+write) accesses
1158 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses
1159 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000470 # miss rate for ReadReq accesses
1160 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016346 # miss rate for ReadReq accesses
1161 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026130 # miss rate for ReadReq accesses
1162 system.cpu.l2cache.ReadReq_miss_rate::total 0.021294 # miss rate for ReadReq accesses
1163 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.829564 # miss rate for UpgradeReq accesses
1164 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.829564 # miss rate for UpgradeReq accesses
1165 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463364 # miss rate for ReadExReq accesses
1166 system.cpu.l2cache.ReadExReq_miss_rate::total 0.463364 # miss rate for ReadExReq accesses
1167 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses
1168 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000470 # miss rate for demand accesses
1169 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016346 # miss rate for demand accesses
1170 system.cpu.l2cache.demand_miss_rate::cpu.data 0.101975 # miss rate for demand accesses
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1172 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses
1173 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000470 # miss rate for overall accesses
1174 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016346 # miss rate for overall accesses
1175 system.cpu.l2cache.overall_miss_rate::cpu.data 0.101975 # miss rate for overall accesses
1176 system.cpu.l2cache.overall_miss_rate::total 0.067692 # miss rate for overall accesses
1177 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85544.354839 # average ReadReq miss latency
1178 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77916.666667 # average ReadReq miss latency
1179 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76460.373495 # average ReadReq miss latency
1180 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79005.289638 # average ReadReq miss latency
1181 system.cpu.l2cache.ReadReq_avg_miss_latency::total 78216.148897 # average ReadReq miss latency
1182 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11779.784574 # average UpgradeReq miss latency
1183 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11779.784574 # average UpgradeReq miss latency
1184 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69682.710269 # average ReadExReq miss latency
1185 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69682.710269 # average ReadExReq miss latency
1186 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency
1187 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency
1188 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency
1189 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency
1190 system.cpu.l2cache.demand_avg_miss_latency::total 72085.369537 # average overall miss latency
1191 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency
1192 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency
1193 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency
1194 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency
1195 system.cpu.l2cache.overall_avg_miss_latency::total 72085.369537 # average overall miss latency
1196 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1197 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1198 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1199 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1200 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1201 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1202 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1203 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1204 system.cpu.l2cache.writebacks::writebacks 102890 # number of writebacks
1205 system.cpu.l2cache.writebacks::total 102890 # number of writebacks
1206 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
1207 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits
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1210 system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits
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1213 system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits
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1220 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1504 # number of UpgradeReq MSHR misses
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1231 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16356 # number of overall MSHR misses
1232 system.cpu.l2cache.overall_mshr_misses::cpu.data 169148 # number of overall MSHR misses
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1235 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles
1236 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1045537500 # number of ReadReq MSHR miss cycles
1237 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2387984748 # number of ReadReq MSHR miss cycles
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1239 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15960982 # number of UpgradeReq MSHR miss cycles
1240 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15960982 # number of UpgradeReq MSHR miss cycles
1241 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7616458286 # number of ReadExReq MSHR miss cycles
1242 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7616458286 # number of ReadExReq MSHR miss cycles
1243 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4538750 # number of demand (read+write) MSHR miss cycles
1244 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles
1245 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1045537500 # number of demand (read+write) MSHR miss cycles
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1248 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4538750 # number of overall MSHR miss cycles
1249 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles
1250 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1045537500 # number of overall MSHR miss cycles
1251 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10004443034 # number of overall MSHR miss cycles
1252 system.cpu.l2cache.overall_mshr_miss_latency::total 11054910784 # number of overall MSHR miss cycles
1253 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89282348000 # number of ReadReq MSHR uncacheable cycles
1254 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89282348000 # number of ReadReq MSHR uncacheable cycles
1255 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2403570000 # number of WriteReq MSHR uncacheable cycles
1256 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2403570000 # number of WriteReq MSHR uncacheable cycles
1257 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91685918000 # number of overall MSHR uncacheable cycles
1258 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91685918000 # number of overall MSHR uncacheable cycles
1259 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses
1260 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for ReadReq accesses
1261 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for ReadReq accesses
1262 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026127 # mshr miss rate for ReadReq accesses
1263 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021292 # mshr miss rate for ReadReq accesses
1264 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829564 # mshr miss rate for UpgradeReq accesses
1265 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829564 # mshr miss rate for UpgradeReq accesses
1266 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463364 # mshr miss rate for ReadExReq accesses
1267 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463364 # mshr miss rate for ReadExReq accesses
1268 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses
1269 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for demand accesses
1270 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for demand accesses
1271 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for demand accesses
1272 system.cpu.l2cache.demand_mshr_miss_rate::total 0.067690 # mshr miss rate for demand accesses
1273 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses
1274 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for overall accesses
1275 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for overall accesses
1276 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for overall accesses
1277 system.cpu.l2cache.overall_mshr_miss_rate::total 0.067690 # mshr miss rate for overall accesses
1278 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average ReadReq mshr miss latency
1279 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
1280 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63923.789435 # average ReadReq mshr miss latency
1281 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66664.379777 # average ReadReq mshr miss latency
1282 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65814.001302 # average ReadReq mshr miss latency
1283 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10612.355053 # average UpgradeReq mshr miss latency
1284 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10612.355053 # average UpgradeReq mshr miss latency
1285 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57126.150637 # average ReadExReq mshr miss latency
1286 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57126.150637 # average ReadExReq mshr miss latency
1287 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency
1288 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
1289 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency
1290 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency
1291 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency
1292 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency
1293 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
1294 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency
1295 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency
1296 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency
1297 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1298 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1299 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1300 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1301 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1302 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1303 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1304 system.cpu.toL2Bus.trans_dist::ReadReq 3074706 # Transaction distribution
1305 system.cpu.toL2Bus.trans_dist::ReadResp 3074138 # Transaction distribution
1306 system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
1307 system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
1308 system.cpu.toL2Bus.trans_dist::Writeback 1585447 # Transaction distribution
1309 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1310 system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution
1311 system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution
1312 system.cpu.toL2Bus.trans_dist::ReadExReq 287746 # Transaction distribution
1313 system.cpu.toL2Bus.trans_dist::ReadExResp 287746 # Transaction distribution
1314 system.cpu.toL2Bus.trans_dist::BadAddressError 27 # Transaction distribution
1315 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2001753 # Packet count per connected master and slave (bytes)
1316 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6129358 # Packet count per connected master and slave (bytes)
1317 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31407 # Packet count per connected master and slave (bytes)
1318 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 167702 # Packet count per connected master and slave (bytes)
1319 system.cpu.toL2Bus.pkt_count::total 8330220 # Packet count per connected master and slave (bytes)
1320 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64052352 # Cumulative packet size per connected master and slave (bytes)
1321 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207821235 # Cumulative packet size per connected master and slave (bytes)
1322 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1029888 # Cumulative packet size per connected master and slave (bytes)
1323 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5836480 # Cumulative packet size per connected master and slave (bytes)
1324 system.cpu.toL2Bus.pkt_size::total 278739955 # Cumulative packet size per connected master and slave (bytes)
1325 system.cpu.toL2Bus.snoops 59032 # Total snoops (count)
1326 system.cpu.toL2Bus.snoop_fanout::samples 4387424 # Request fanout histogram
1327 system.cpu.toL2Bus.snoop_fanout::mean 3.010858 # Request fanout histogram
1328 system.cpu.toL2Bus.snoop_fanout::stdev 0.103635 # Request fanout histogram
1329 system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1330 system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1331 system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1332 system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1333 system.cpu.toL2Bus.snoop_fanout::3 4339785 98.91% 98.91% # Request fanout histogram
1334 system.cpu.toL2Bus.snoop_fanout::4 47639 1.09% 100.00% # Request fanout histogram
1335 system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1336 system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1337 system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1338 system.cpu.toL2Bus.snoop_fanout::total 4387424 # Request fanout histogram
1339 system.cpu.toL2Bus.reqLayer0.occupancy 4074051871 # Layer occupancy (ticks)
1340 system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1341 system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
1342 system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1343 system.cpu.toL2Bus.respLayer0.occupancy 1505430236 # Layer occupancy (ticks)
1344 system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1345 system.cpu.toL2Bus.respLayer1.occupancy 3141534733 # Layer occupancy (ticks)
1346 system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1347 system.cpu.toL2Bus.respLayer2.occupancy 22981484 # Layer occupancy (ticks)
1348 system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1349 system.cpu.toL2Bus.respLayer3.occupancy 114826620 # Layer occupancy (ticks)
1350 system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1351 system.iobus.trans_dist::ReadReq 225722 # Transaction distribution
1352 system.iobus.trans_dist::ReadResp 225722 # Transaction distribution
1353 system.iobus.trans_dist::WriteReq 57753 # Transaction distribution
1354 system.iobus.trans_dist::WriteResp 11033 # Transaction distribution
1355 system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1356 system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
1357 system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
1358 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
1359 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
1360 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
1361 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
1362 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
1363 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
1364 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
1365 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
1366 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
1367 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
1368 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
1369 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
1370 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
1371 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
1372 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
1373 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
1374 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
1375 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
1376 system.iobus.pkt_count_system.bridge.master::total 471672 # Packet count per connected master and slave (bytes)
1377 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes)
1378 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes)
1379 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
1380 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
1381 system.iobus.pkt_count::total 570236 # Packet count per connected master and slave (bytes)
1382 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
1383 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
1384 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
1385 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
1386 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
1387 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
1388 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
1389 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
1390 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
1391 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
1392 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
1393 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
1394 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
1395 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
1396 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
1397 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
1398 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
1399 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
1400 system.iobus.pkt_size_system.bridge.master::total 242122 # Cumulative packet size per connected master and slave (bytes)
1401 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes)
1402 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes)
1403 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
1404 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1405 system.iobus.pkt_size::total 3276590 # Cumulative packet size per connected master and slave (bytes)
1406 system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks)
1407 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1408 system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
1409 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1410 system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
1411 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1412 system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
1413 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1414 system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
1415 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1416 system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
1417 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1418 system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
1419 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1420 system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
1421 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1422 system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
1423 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1424 system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
1425 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1426 system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
1427 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1428 system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
1429 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1430 system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
1431 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1432 system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
1433 system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1434 system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
1435 system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1436 system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
1437 system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1438 system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
1439 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1440 system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1441 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1442 system.iobus.reqLayer19.occupancy 448363457 # Layer occupancy (ticks)
1443 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1444 system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
1445 system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1446 system.iobus.respLayer0.occupancy 460639000 # Layer occupancy (ticks)
1447 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1448 system.iobus.respLayer1.occupancy 52378260 # Layer occupancy (ticks)
1449 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1450 system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
1451 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1452 system.iocache.tags.replacements 47584 # number of replacements
1453 system.iocache.tags.tagsinuse 0.079092 # Cycle average of tags in use
1454 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1455 system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks.
1456 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1457 system.iocache.tags.warmup_cycle 4992999647000 # Cycle when the warmup percentage was hit.
1458 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079092 # Average occupied blocks per requestor
1459 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004943 # Average percentage of cache occupancy
1460 system.iocache.tags.occ_percent::total 0.004943 # Average percentage of cache occupancy
1461 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1462 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1463 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1464 system.iocache.tags.tag_accesses 428751 # Number of tag accesses
1465 system.iocache.tags.data_accesses 428751 # Number of data accesses
1466 system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses
1467 system.iocache.ReadReq_misses::total 919 # number of ReadReq misses
1468 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
1469 system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
1470 system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses
1471 system.iocache.demand_misses::total 919 # number of demand (read+write) misses
1472 system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses
1473 system.iocache.overall_misses::total 919 # number of overall misses
1474 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149123196 # number of ReadReq miss cycles
1475 system.iocache.ReadReq_miss_latency::total 149123196 # number of ReadReq miss cycles
1476 system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12357582001 # number of WriteInvalidateReq miss cycles
1477 system.iocache.WriteInvalidateReq_miss_latency::total 12357582001 # number of WriteInvalidateReq miss cycles
1478 system.iocache.demand_miss_latency::pc.south_bridge.ide 149123196 # number of demand (read+write) miss cycles
1479 system.iocache.demand_miss_latency::total 149123196 # number of demand (read+write) miss cycles
1480 system.iocache.overall_miss_latency::pc.south_bridge.ide 149123196 # number of overall miss cycles
1481 system.iocache.overall_miss_latency::total 149123196 # number of overall miss cycles
1482 system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses)
1483 system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses)
1484 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
1485 system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
1486 system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses
1487 system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses
1488 system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses
1489 system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses
1490 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
1491 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1492 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
1493 system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1494 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
1495 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1496 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
1497 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1498 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average ReadReq miss latency
1499 system.iocache.ReadReq_avg_miss_latency::total 162266.807399 # average ReadReq miss latency
1500 system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405 # average WriteInvalidateReq miss latency
1501 system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405 # average WriteInvalidateReq miss latency
1502 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency
1503 system.iocache.demand_avg_miss_latency::total 162266.807399 # average overall miss latency
1504 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency
1505 system.iocache.overall_avg_miss_latency::total 162266.807399 # average overall miss latency
1506 system.iocache.blocked_cycles::no_mshrs 70647 # number of cycles access was blocked
1507 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1508 system.iocache.blocked::no_mshrs 9165 # number of cycles access was blocked
1509 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1510 system.iocache.avg_blocked_cycles::no_mshrs 7.708347 # average number of cycles each access was blocked
1511 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1512 system.iocache.fast_writes 0 # number of fast writes performed
1513 system.iocache.cache_copies 0 # number of cache copies performed
1514 system.iocache.writebacks::writebacks 46667 # number of writebacks
1515 system.iocache.writebacks::total 46667 # number of writebacks
1516 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses
1517 system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses
1518 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
1519 system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
1520 system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses
1521 system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses
1522 system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses
1523 system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses
1524 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of ReadReq MSHR miss cycles
1525 system.iocache.ReadReq_mshr_miss_latency::total 101309696 # number of ReadReq MSHR miss cycles
1526 system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9928122021 # number of WriteInvalidateReq MSHR miss cycles
1527 system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9928122021 # number of WriteInvalidateReq MSHR miss cycles
1528 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of demand (read+write) MSHR miss cycles
1529 system.iocache.demand_mshr_miss_latency::total 101309696 # number of demand (read+write) MSHR miss cycles
1530 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of overall MSHR miss cycles
1531 system.iocache.overall_mshr_miss_latency::total 101309696 # number of overall MSHR miss cycles
1532 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
1533 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1534 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1535 system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1536 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
1537 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1538 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
1539 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1540 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average ReadReq mshr miss latency
1541 system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848 # average ReadReq mshr miss latency
1542 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751 # average WriteInvalidateReq mshr miss latency
1543 system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751 # average WriteInvalidateReq mshr miss latency
1544 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency
1545 system.iocache.demand_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency
1546 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency
1547 system.iocache.overall_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency
1548 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1549 system.membus.trans_dist::ReadReq 662612 # Transaction distribution
1550 system.membus.trans_dist::ReadResp 662585 # Transaction distribution
1551 system.membus.trans_dist::WriteReq 13919 # Transaction distribution
1552 system.membus.trans_dist::WriteResp 13919 # Transaction distribution
1553 system.membus.trans_dist::Writeback 149557 # Transaction distribution
1554 system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
1555 system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1556 system.membus.trans_dist::UpgradeReq 2230 # Transaction distribution
1557 system.membus.trans_dist::UpgradeResp 1790 # Transaction distribution
1558 system.membus.trans_dist::ReadExReq 133043 # Transaction distribution
1559 system.membus.trans_dist::ReadExResp 133041 # Transaction distribution
1560 system.membus.trans_dist::MessageReq 1643 # Transaction distribution
1561 system.membus.trans_dist::MessageResp 1643 # Transaction distribution
1562 system.membus.trans_dist::BadAddressError 27 # Transaction distribution
1563 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
1564 system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
1565 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471672 # Packet count per connected master and slave (bytes)
1566 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775062 # Packet count per connected master and slave (bytes)
1567 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476745 # Packet count per connected master and slave (bytes)
1568 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 54 # Packet count per connected master and slave (bytes)
1569 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723533 # Packet count per connected master and slave (bytes)
1570 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141469 # Packet count per connected master and slave (bytes)
1571 system.membus.pkt_count_system.iocache.mem_side::total 141469 # Packet count per connected master and slave (bytes)
1572 system.membus.pkt_count::total 1868288 # Packet count per connected master and slave (bytes)
1573 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
1574 system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
1575 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242122 # Cumulative packet size per connected master and slave (bytes)
1576 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550121 # Cumulative packet size per connected master and slave (bytes)
1577 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18398848 # Cumulative packet size per connected master and slave (bytes)
1578 system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20191091 # Cumulative packet size per connected master and slave (bytes)
1579 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
1580 system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
1581 system.membus.pkt_size::total 26202783 # Cumulative packet size per connected master and slave (bytes)
1582 system.membus.snoops 1603 # Total snoops (count)
1583 system.membus.snoop_fanout::samples 384714 # Request fanout histogram
1584 system.membus.snoop_fanout::mean 1 # Request fanout histogram
1585 system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1586 system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1587 system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1588 system.membus.snoop_fanout::1 384714 100.00% 100.00% # Request fanout histogram
1589 system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1590 system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1591 system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1592 system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1593 system.membus.snoop_fanout::total 384714 # Request fanout histogram
1594 system.membus.reqLayer0.occupancy 251770499 # Layer occupancy (ticks)
1595 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1596 system.membus.reqLayer1.occupancy 583267500 # Layer occupancy (ticks)
1597 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1598 system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
1599 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1600 system.membus.reqLayer3.occupancy 1992294999 # Layer occupancy (ticks)
1601 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
1602 system.membus.reqLayer4.occupancy 33000 # Layer occupancy (ticks)
1603 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
1604 system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
1605 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
1606 system.membus.respLayer2.occupancy 3156735730 # Layer occupancy (ticks)
1607 system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
1608 system.membus.respLayer4.occupancy 55013740 # Layer occupancy (ticks)
1609 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
1610 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1611 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
1612 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
1613 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
1614 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
1615 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
1616 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1617 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1618 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1619 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
1620 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
1621 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
1622 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1623 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1625 ---------- End Simulation Statistics ----------
projects / gem5.git / blob