2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.136862 # Number of seconds simulated
4 sim_ticks 5136862311000 # Number of ticks simulated
5 final_tick 5136862311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 202420 # Simulator instruction rate (inst/s)
8 host_op_rate 400133 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 2548945395 # Simulator tick rate (ticks/s)
10 host_mem_usage 760276 # Number of bytes of host memory used
11 host_seconds 2015.29 # Real time elapsed on the host
12 sim_insts 407935752 # Number of instructions simulated
13 sim_ops 806383618 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2490880 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu.inst 1078272 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu.data 10788032 # Number of bytes read from this memory
19 system.physmem.bytes_read::total 14361024 # Number of bytes read from this memory
20 system.physmem.bytes_inst_read::cpu.inst 1078272 # Number of instructions bytes read from this memory
21 system.physmem.bytes_inst_read::total 1078272 # Number of instructions bytes read from this memory
22 system.physmem.bytes_written::writebacks 9547840 # Number of bytes written to this memory
23 system.physmem.bytes_written::total 9547840 # Number of bytes written to this memory
24 system.physmem.num_reads::pc.south_bridge.ide 38920 # Number of read requests responded to by this memory
25 system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory
26 system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
27 system.physmem.num_reads::cpu.inst 16848 # Number of read requests responded to by this memory
28 system.physmem.num_reads::cpu.data 168563 # Number of read requests responded to by this memory
29 system.physmem.num_reads::total 224391 # Number of read requests responded to by this memory
30 system.physmem.num_writes::writebacks 149185 # Number of write requests responded to by this memory
31 system.physmem.num_writes::total 149185 # Number of write requests responded to by this memory
32 system.physmem.bw_read::pc.south_bridge.ide 484903 # Total read bandwidth from this memory (bytes/s)
33 system.physmem.bw_read::cpu.dtb.walker 660 # Total read bandwidth from this memory (bytes/s)
34 system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
35 system.physmem.bw_read::cpu.inst 209909 # Total read bandwidth from this memory (bytes/s)
36 system.physmem.bw_read::cpu.data 2100121 # Total read bandwidth from this memory (bytes/s)
37 system.physmem.bw_read::total 2795680 # Total read bandwidth from this memory (bytes/s)
38 system.physmem.bw_inst_read::cpu.inst 209909 # Instruction read bandwidth from this memory (bytes/s)
39 system.physmem.bw_inst_read::total 209909 # Instruction read bandwidth from this memory (bytes/s)
40 system.physmem.bw_write::writebacks 1858691 # Write bandwidth from this memory (bytes/s)
41 system.physmem.bw_write::total 1858691 # Write bandwidth from this memory (bytes/s)
42 system.physmem.bw_total::writebacks 1858691 # Total bandwidth to/from this memory (bytes/s)
43 system.physmem.bw_total::pc.south_bridge.ide 484903 # Total bandwidth to/from this memory (bytes/s)
44 system.physmem.bw_total::cpu.dtb.walker 660 # Total bandwidth to/from this memory (bytes/s)
45 system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
46 system.physmem.bw_total::cpu.inst 209909 # Total bandwidth to/from this memory (bytes/s)
47 system.physmem.bw_total::cpu.data 2100121 # Total bandwidth to/from this memory (bytes/s)
48 system.physmem.bw_total::total 4654371 # Total bandwidth to/from this memory (bytes/s)
49 system.physmem.readReqs 224391 # Total number of read requests seen
50 system.physmem.writeReqs 149185 # Total number of write requests seen
51 system.physmem.cpureqs 388105 # Reqs generatd by CPU via cache - shady
52 system.physmem.bytesRead 14361024 # Total number of bytes read from memory
53 system.physmem.bytesWritten 9547840 # Total number of bytes written to memory
54 system.physmem.bytesConsumedRd 14361024 # bytesRead derated as per pkt->getSize()
55 system.physmem.bytesConsumedWr 9547840 # bytesWritten derated as per pkt->getSize()
56 system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q
57 system.physmem.neitherReadNorWrite 3903 # Reqs where no action is needed
58 system.physmem.perBankRdReqs::0 14157 # Track reads on a per bank basis
59 system.physmem.perBankRdReqs::1 13127 # Track reads on a per bank basis
60 system.physmem.perBankRdReqs::2 13393 # Track reads on a per bank basis
61 system.physmem.perBankRdReqs::3 16573 # Track reads on a per bank basis
62 system.physmem.perBankRdReqs::4 13535 # Track reads on a per bank basis
63 system.physmem.perBankRdReqs::5 12962 # Track reads on a per bank basis
64 system.physmem.perBankRdReqs::6 13580 # Track reads on a per bank basis
65 system.physmem.perBankRdReqs::7 16342 # Track reads on a per bank basis
66 system.physmem.perBankRdReqs::8 13760 # Track reads on a per bank basis
67 system.physmem.perBankRdReqs::9 13186 # Track reads on a per bank basis
68 system.physmem.perBankRdReqs::10 13242 # Track reads on a per bank basis
69 system.physmem.perBankRdReqs::11 15501 # Track reads on a per bank basis
70 system.physmem.perBankRdReqs::12 13187 # Track reads on a per bank basis
71 system.physmem.perBankRdReqs::13 12719 # Track reads on a per bank basis
72 system.physmem.perBankRdReqs::14 13259 # Track reads on a per bank basis
73 system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis
74 system.physmem.perBankWrReqs::0 9129 # Track writes on a per bank basis
75 system.physmem.perBankWrReqs::1 8570 # Track writes on a per bank basis
76 system.physmem.perBankWrReqs::2 8702 # Track writes on a per bank basis
77 system.physmem.perBankWrReqs::3 11948 # Track writes on a per bank basis
78 system.physmem.perBankWrReqs::4 8746 # Track writes on a per bank basis
79 system.physmem.perBankWrReqs::5 8430 # Track writes on a per bank basis
80 system.physmem.perBankWrReqs::6 8914 # Track writes on a per bank basis
81 system.physmem.perBankWrReqs::7 11741 # Track writes on a per bank basis
82 system.physmem.perBankWrReqs::8 8779 # Track writes on a per bank basis
83 system.physmem.perBankWrReqs::9 8505 # Track writes on a per bank basis
84 system.physmem.perBankWrReqs::10 8628 # Track writes on a per bank basis
85 system.physmem.perBankWrReqs::11 10975 # Track writes on a per bank basis
86 system.physmem.perBankWrReqs::12 8406 # Track writes on a per bank basis
87 system.physmem.perBankWrReqs::13 8212 # Track writes on a per bank basis
88 system.physmem.perBankWrReqs::14 8505 # Track writes on a per bank basis
89 system.physmem.perBankWrReqs::15 10995 # Track writes on a per bank basis
90 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
91 system.physmem.numWrRetry 794 # Number of times wr buffer was full causing retry
92 system.physmem.totGap 5136862258500 # Total gap between requests
93 system.physmem.readPktSize::0 0 # Categorize read packet sizes
94 system.physmem.readPktSize::1 0 # Categorize read packet sizes
95 system.physmem.readPktSize::2 0 # Categorize read packet sizes
96 system.physmem.readPktSize::3 0 # Categorize read packet sizes
97 system.physmem.readPktSize::4 0 # Categorize read packet sizes
98 system.physmem.readPktSize::5 0 # Categorize read packet sizes
99 system.physmem.readPktSize::6 224391 # Categorize read packet sizes
100 system.physmem.readPktSize::7 0 # Categorize read packet sizes
101 system.physmem.readPktSize::8 0 # Categorize read packet sizes
102 system.physmem.writePktSize::0 0 # categorize write packet sizes
103 system.physmem.writePktSize::1 0 # categorize write packet sizes
104 system.physmem.writePktSize::2 0 # categorize write packet sizes
105 system.physmem.writePktSize::3 0 # categorize write packet sizes
106 system.physmem.writePktSize::4 0 # categorize write packet sizes
107 system.physmem.writePktSize::5 0 # categorize write packet sizes
108 system.physmem.writePktSize::6 149979 # categorize write packet sizes
109 system.physmem.writePktSize::7 0 # categorize write packet sizes
110 system.physmem.writePktSize::8 0 # categorize write packet sizes
111 system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
112 system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
113 system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
114 system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
115 system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
116 system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
117 system.physmem.neitherpktsize::6 3903 # categorize neither packet sizes
118 system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
119 system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
120 system.physmem.rdQLenPdf::0 173046 # What read queue length does an incoming req see
121 system.physmem.rdQLenPdf::1 19422 # What read queue length does an incoming req see
122 system.physmem.rdQLenPdf::2 7578 # What read queue length does an incoming req see
123 system.physmem.rdQLenPdf::3 3497 # What read queue length does an incoming req see
124 system.physmem.rdQLenPdf::4 3020 # What read queue length does an incoming req see
125 system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see
126 system.physmem.rdQLenPdf::6 1930 # What read queue length does an incoming req see
127 system.physmem.rdQLenPdf::7 1866 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::8 1777 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::9 1691 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::10 1133 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::11 1016 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::12 933 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::13 874 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::14 828 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::16 915 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::17 867 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::18 384 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::19 221 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
153 system.physmem.wrQLenPdf::0 5322 # What write queue length does an incoming req see
154 system.physmem.wrQLenPdf::1 5660 # What write queue length does an incoming req see
155 system.physmem.wrQLenPdf::2 6306 # What write queue length does an incoming req see
156 system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see
157 system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see
158 system.physmem.wrQLenPdf::5 6455 # What write queue length does an incoming req see
159 system.physmem.wrQLenPdf::6 6463 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::7 6468 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::8 6472 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::9 6486 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::10 6486 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::11 6486 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::12 6486 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::13 6486 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::14 6486 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::15 6486 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::16 6486 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::17 6486 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::18 6486 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::19 6486 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::20 6486 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::21 6486 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::23 1165 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::24 827 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::25 181 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::26 92 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
186 system.physmem.totQLat 4730288859 # Total cycles spent in queuing delays
187 system.physmem.totMemAccLat 9241012609 # Sum of mem lat for all requests
188 system.physmem.totBusLat 1121280000 # Total cycles spent in databus access
189 system.physmem.totBankLat 3389443750 # Total cycles spent in bank access
190 system.physmem.avgQLat 21093.25 # Average queueing delay per request
191 system.physmem.avgBankLat 15114.17 # Average bank access latency per request
192 system.physmem.avgBusLat 5000.00 # Average bus latency per request
193 system.physmem.avgMemAccLat 41207.43 # Average memory access latency
194 system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
195 system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
196 system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
197 system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
198 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
199 system.physmem.busUtil 0.04 # Data bus utilization in percentage
200 system.physmem.avgRdQLen 0.00 # Average read queue length over time
201 system.physmem.avgWrQLen 12.83 # Average write queue length over time
202 system.physmem.readRowHits 193267 # Number of row buffer hits during reads
203 system.physmem.writeRowHits 105785 # Number of row buffer hits during writes
204 system.physmem.readRowHitRate 86.18 # Row buffer hit rate for reads
205 system.physmem.writeRowHitRate 70.91 # Row buffer hit rate for writes
206 system.physmem.avgGap 13750514.64 # Average gap between requests
207 system.iocache.replacements 47583 # number of replacements
208 system.iocache.tagsinuse 0.137403 # Cycle average of tags in use
209 system.iocache.total_refs 0 # Total number of references to valid blocks.
210 system.iocache.sampled_refs 47599 # Sample count of references to valid blocks.
211 system.iocache.avg_refs 0 # Average number of references to valid blocks.
212 system.iocache.warmup_cycle 4991910569000 # Cycle when the warmup percentage was hit.
213 system.iocache.occ_blocks::pc.south_bridge.ide 0.137403 # Average occupied blocks per requestor
214 system.iocache.occ_percent::pc.south_bridge.ide 0.008588 # Average percentage of cache occupancy
215 system.iocache.occ_percent::total 0.008588 # Average percentage of cache occupancy
216 system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
217 system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
218 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
219 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
220 system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
221 system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
222 system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
223 system.iocache.overall_misses::total 47632 # number of overall misses
224 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144324932 # number of ReadReq miss cycles
225 system.iocache.ReadReq_miss_latency::total 144324932 # number of ReadReq miss cycles
226 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10020383160 # number of WriteReq miss cycles
227 system.iocache.WriteReq_miss_latency::total 10020383160 # number of WriteReq miss cycles
228 system.iocache.demand_miss_latency::pc.south_bridge.ide 10164708092 # number of demand (read+write) miss cycles
229 system.iocache.demand_miss_latency::total 10164708092 # number of demand (read+write) miss cycles
230 system.iocache.overall_miss_latency::pc.south_bridge.ide 10164708092 # number of overall miss cycles
231 system.iocache.overall_miss_latency::total 10164708092 # number of overall miss cycles
232 system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
233 system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
234 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
235 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
236 system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
237 system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
238 system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
239 system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
240 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
241 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
242 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
243 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
244 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
245 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
246 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
247 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
248 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158251.021930 # average ReadReq miss latency
249 system.iocache.ReadReq_avg_miss_latency::total 158251.021930 # average ReadReq miss latency
250 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214477.379281 # average WriteReq miss latency
251 system.iocache.WriteReq_avg_miss_latency::total 214477.379281 # average WriteReq miss latency
252 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency
253 system.iocache.demand_avg_miss_latency::total 213400.824908 # average overall miss latency
254 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency
255 system.iocache.overall_avg_miss_latency::total 213400.824908 # average overall miss latency
256 system.iocache.blocked_cycles::no_mshrs 133472 # number of cycles access was blocked
257 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
258 system.iocache.blocked::no_mshrs 12161 # number of cycles access was blocked
259 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
260 system.iocache.avg_blocked_cycles::no_mshrs 10.975413 # average number of cycles each access was blocked
261 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
262 system.iocache.fast_writes 0 # number of fast writes performed
263 system.iocache.cache_copies 0 # number of cache copies performed
264 system.iocache.writebacks::writebacks 46673 # number of writebacks
265 system.iocache.writebacks::total 46673 # number of writebacks
266 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
267 system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
268 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
269 system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
270 system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
271 system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
272 system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
273 system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
274 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96878242 # number of ReadReq MSHR miss cycles
275 system.iocache.ReadReq_mshr_miss_latency::total 96878242 # number of ReadReq MSHR miss cycles
276 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7589579568 # number of WriteReq MSHR miss cycles
277 system.iocache.WriteReq_mshr_miss_latency::total 7589579568 # number of WriteReq MSHR miss cycles
278 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of demand (read+write) MSHR miss cycles
279 system.iocache.demand_mshr_miss_latency::total 7686457810 # number of demand (read+write) MSHR miss cycles
280 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of overall MSHR miss cycles
281 system.iocache.overall_mshr_miss_latency::total 7686457810 # number of overall MSHR miss cycles
282 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
283 system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
284 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
285 system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
286 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
287 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
288 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
289 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
290 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106226.142544 # average ReadReq mshr miss latency
291 system.iocache.ReadReq_avg_mshr_miss_latency::total 106226.142544 # average ReadReq mshr miss latency
292 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162448.192808 # average WriteReq mshr miss latency
293 system.iocache.WriteReq_avg_mshr_miss_latency::total 162448.192808 # average WriteReq mshr miss latency
294 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency
295 system.iocache.demand_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency
296 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency
297 system.iocache.overall_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency
298 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
299 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
300 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
301 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
302 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
303 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
304 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
305 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
306 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
307 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
308 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
309 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
310 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
311 system.cpu.branchPred.lookups 86190273 # Number of BP lookups
312 system.cpu.branchPred.condPredicted 86190273 # Number of conditional branches predicted
313 system.cpu.branchPred.condIncorrect 1107531 # Number of conditional branches incorrect
314 system.cpu.branchPred.BTBLookups 81286866 # Number of BTB lookups
315 system.cpu.branchPred.BTBHits 79207834 # Number of BTB hits
316 system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
317 system.cpu.branchPred.BTBHitPct 97.442352 # BTB Hit Percentage
318 system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
319 system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
320 system.cpu.numCycles 448143159 # number of cpu cycles simulated
321 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
322 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
323 system.cpu.fetch.icacheStallCycles 27503051 # Number of cycles fetch is stalled on an Icache miss
324 system.cpu.fetch.Insts 425930482 # Number of instructions fetch has processed
325 system.cpu.fetch.Branches 86190273 # Number of branches that fetch encountered
326 system.cpu.fetch.predictedBranches 79207834 # Number of branches that fetch has predicted taken
327 system.cpu.fetch.Cycles 163575255 # Number of cycles fetch has run and was not squashing or blocked
328 system.cpu.fetch.SquashCycles 4699027 # Number of cycles fetch has spent squashing
329 system.cpu.fetch.TlbCycles 119359 # Number of cycles fetch has spent waiting for tlb
330 system.cpu.fetch.BlockedCycles 63002200 # Number of cycles fetch has spent blocked
331 system.cpu.fetch.MiscStallCycles 36275 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
332 system.cpu.fetch.PendingTrapStallCycles 56191 # Number of stall cycles due to pending traps
333 system.cpu.fetch.IcacheWaitRetryStallCycles 501 # Number of stall cycles due to full MSHR
334 system.cpu.fetch.CacheLines 9012986 # Number of cache lines fetched
335 system.cpu.fetch.IcacheSquashes 485449 # Number of outstanding Icache misses that were squashed
336 system.cpu.fetch.ItlbSquashes 3601 # Number of outstanding ITLB misses that were squashed
337 system.cpu.fetch.rateDist::samples 257845073 # Number of instructions fetched each cycle (Total)
338 system.cpu.fetch.rateDist::mean 3.261142 # Number of instructions fetched each cycle (Total)
339 system.cpu.fetch.rateDist::stdev 3.418049 # Number of instructions fetched each cycle (Total)
340 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
341 system.cpu.fetch.rateDist::0 94696195 36.73% 36.73% # Number of instructions fetched each cycle (Total)
342 system.cpu.fetch.rateDist::1 1566516 0.61% 37.33% # Number of instructions fetched each cycle (Total)
343 system.cpu.fetch.rateDist::2 71918479 27.89% 65.23% # Number of instructions fetched each cycle (Total)
344 system.cpu.fetch.rateDist::3 936665 0.36% 65.59% # Number of instructions fetched each cycle (Total)
345 system.cpu.fetch.rateDist::4 1597376 0.62% 66.21% # Number of instructions fetched each cycle (Total)
346 system.cpu.fetch.rateDist::5 2419164 0.94% 67.15% # Number of instructions fetched each cycle (Total)
347 system.cpu.fetch.rateDist::6 1071712 0.42% 67.56% # Number of instructions fetched each cycle (Total)
348 system.cpu.fetch.rateDist::7 1371295 0.53% 68.09% # Number of instructions fetched each cycle (Total)
349 system.cpu.fetch.rateDist::8 82267671 31.91% 100.00% # Number of instructions fetched each cycle (Total)
350 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
351 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
352 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
353 system.cpu.fetch.rateDist::total 257845073 # Number of instructions fetched each cycle (Total)
354 system.cpu.fetch.branchRate 0.192328 # Number of branch fetches per cycle
355 system.cpu.fetch.rate 0.950434 # Number of inst fetches per cycle
356 system.cpu.decode.IdleCycles 31188651 # Number of cycles decode is idle
357 system.cpu.decode.BlockedCycles 60472166 # Number of cycles decode is blocked
358 system.cpu.decode.RunCycles 159373926 # Number of cycles decode is running
359 system.cpu.decode.UnblockCycles 3258089 # Number of cycles decode is unblocking
360 system.cpu.decode.SquashCycles 3552241 # Number of cycles decode is squashing
361 system.cpu.decode.DecodedInsts 837743575 # Number of instructions handled by decode
362 system.cpu.decode.SquashedInsts 790 # Number of squashed instructions handled by decode
363 system.cpu.rename.SquashCycles 3552241 # Number of cycles rename is squashing
364 system.cpu.rename.IdleCycles 33924496 # Number of cycles rename is idle
365 system.cpu.rename.BlockCycles 37350938 # Number of cycles rename is blocking
366 system.cpu.rename.serializeStallCycles 11010617 # count of cycles rename stalled for serializing inst
367 system.cpu.rename.RunCycles 159571112 # Number of cycles rename is running
368 system.cpu.rename.UnblockCycles 12435669 # Number of cycles rename is unblocking
369 system.cpu.rename.RenamedInsts 834099694 # Number of instructions processed by rename
370 system.cpu.rename.ROBFullEvents 18960 # Number of times rename has blocked due to ROB full
371 system.cpu.rename.IQFullEvents 5861549 # Number of times rename has blocked due to IQ full
372 system.cpu.rename.LSQFullEvents 4743149 # Number of times rename has blocked due to LSQ full
373 system.cpu.rename.FullRegisterEvents 8341 # Number of times there has been no free registers
374 system.cpu.rename.RenamedOperands 995593221 # Number of destination operands rename has renamed
375 system.cpu.rename.RenameLookups 1810589255 # Number of register rename lookups that rename has made
376 system.cpu.rename.int_rename_lookups 1810588751 # Number of integer rename lookups
377 system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups
378 system.cpu.rename.CommittedMaps 964361742 # Number of HB maps that are committed
379 system.cpu.rename.UndoneMaps 31231472 # Number of HB maps that are undone due to squashing
380 system.cpu.rename.serializingInsts 459351 # count of serializing insts renamed
381 system.cpu.rename.tempSerializingInsts 467339 # count of temporary serializing insts renamed
382 system.cpu.rename.skidInsts 28773559 # count of insts added to the skid buffer
383 system.cpu.memDep0.insertedLoads 17056832 # Number of loads inserted to the mem dependence unit.
384 system.cpu.memDep0.insertedStores 10125853 # Number of stores inserted to the mem dependence unit.
385 system.cpu.memDep0.conflictingLoads 1239786 # Number of conflicting loads.
386 system.cpu.memDep0.conflictingStores 991765 # Number of conflicting stores.
387 system.cpu.iq.iqInstsAdded 827988990 # Number of instructions added to the IQ (excludes non-spec)
388 system.cpu.iq.iqNonSpecInstsAdded 1249374 # Number of non-speculative instructions added to the IQ
389 system.cpu.iq.iqInstsIssued 823075347 # Number of instructions issued
390 system.cpu.iq.iqSquashedInstsIssued 149433 # Number of squashed instructions issued
391 system.cpu.iq.iqSquashedInstsExamined 21943198 # Number of squashed instructions iterated over during squash; mainly for profiling
392 system.cpu.iq.iqSquashedOperandsExamined 33340930 # Number of squashed operands that are examined and possibly removed from graph
393 system.cpu.iq.iqSquashedNonSpecRemoved 196529 # Number of squashed non-spec instructions that were removed
394 system.cpu.iq.issued_per_cycle::samples 257845073 # Number of insts issued each cycle
395 system.cpu.iq.issued_per_cycle::mean 3.192131 # Number of insts issued each cycle
396 system.cpu.iq.issued_per_cycle::stdev 2.383978 # Number of insts issued each cycle
397 system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
398 system.cpu.iq.issued_per_cycle::0 71377289 27.68% 27.68% # Number of insts issued each cycle
399 system.cpu.iq.issued_per_cycle::1 15522092 6.02% 33.70% # Number of insts issued each cycle
400 system.cpu.iq.issued_per_cycle::2 10290654 3.99% 37.69% # Number of insts issued each cycle
401 system.cpu.iq.issued_per_cycle::3 7462079 2.89% 40.59% # Number of insts issued each cycle
402 system.cpu.iq.issued_per_cycle::4 75909573 29.44% 70.03% # Number of insts issued each cycle
403 system.cpu.iq.issued_per_cycle::5 3836908 1.49% 71.52% # Number of insts issued each cycle
404 system.cpu.iq.issued_per_cycle::6 72514603 28.12% 99.64% # Number of insts issued each cycle
405 system.cpu.iq.issued_per_cycle::7 779740 0.30% 99.94% # Number of insts issued each cycle
406 system.cpu.iq.issued_per_cycle::8 152135 0.06% 100.00% # Number of insts issued each cycle
407 system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
408 system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
409 system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
410 system.cpu.iq.issued_per_cycle::total 257845073 # Number of insts issued each cycle
411 system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
412 system.cpu.iq.fu_full::IntAlu 361447 33.94% 33.94% # attempts to use FU when none available
413 system.cpu.iq.fu_full::IntMult 0 0.00% 33.94% # attempts to use FU when none available
414 system.cpu.iq.fu_full::IntDiv 0 0.00% 33.94% # attempts to use FU when none available
415 system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.94% # attempts to use FU when none available
416 system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.94% # attempts to use FU when none available
417 system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.94% # attempts to use FU when none available
418 system.cpu.iq.fu_full::FloatMult 0 0.00% 33.94% # attempts to use FU when none available
419 system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.94% # attempts to use FU when none available
420 system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.94% # attempts to use FU when none available
421 system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.94% # attempts to use FU when none available
422 system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.94% # attempts to use FU when none available
423 system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.94% # attempts to use FU when none available
424 system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.94% # attempts to use FU when none available
425 system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.94% # attempts to use FU when none available
426 system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.94% # attempts to use FU when none available
427 system.cpu.iq.fu_full::SimdMult 0 0.00% 33.94% # attempts to use FU when none available
428 system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.94% # attempts to use FU when none available
429 system.cpu.iq.fu_full::SimdShift 0 0.00% 33.94% # attempts to use FU when none available
430 system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.94% # attempts to use FU when none available
431 system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.94% # attempts to use FU when none available
432 system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.94% # attempts to use FU when none available
433 system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.94% # attempts to use FU when none available
434 system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.94% # attempts to use FU when none available
435 system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.94% # attempts to use FU when none available
436 system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.94% # attempts to use FU when none available
437 system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.94% # attempts to use FU when none available
438 system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.94% # attempts to use FU when none available
439 system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.94% # attempts to use FU when none available
440 system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.94% # attempts to use FU when none available
441 system.cpu.iq.fu_full::MemRead 553013 51.93% 85.87% # attempts to use FU when none available
442 system.cpu.iq.fu_full::MemWrite 150537 14.13% 100.00% # attempts to use FU when none available
443 system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
444 system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
445 system.cpu.iq.FU_type_0::No_OpClass 311265 0.04% 0.04% # Type of FU issued
446 system.cpu.iq.FU_type_0::IntAlu 795546265 96.66% 96.69% # Type of FU issued
447 system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
448 system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
449 system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
450 system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
451 system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
452 system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
453 system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
454 system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
455 system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
456 system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
457 system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
458 system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
459 system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
460 system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
461 system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
462 system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
463 system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
464 system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
465 system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
466 system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
467 system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
468 system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
469 system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
470 system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
471 system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
472 system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
473 system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
474 system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
475 system.cpu.iq.FU_type_0::MemRead 17838711 2.17% 98.86% # Type of FU issued
476 system.cpu.iq.FU_type_0::MemWrite 9379106 1.14% 100.00% # Type of FU issued
477 system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
478 system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
479 system.cpu.iq.FU_type_0::total 823075347 # Type of FU issued
480 system.cpu.iq.rate 1.836635 # Inst issue rate
481 system.cpu.iq.fu_busy_cnt 1064997 # FU busy when requested
482 system.cpu.iq.fu_busy_rate 0.001294 # FU busy rate (busy events/executed inst)
483 system.cpu.iq.int_inst_queue_reads 1905340193 # Number of integer instruction queue reads
484 system.cpu.iq.int_inst_queue_writes 851191548 # Number of integer instruction queue writes
485 system.cpu.iq.int_inst_queue_wakeup_accesses 818612199 # Number of integer instruction queue wakeup accesses
486 system.cpu.iq.fp_inst_queue_reads 185 # Number of floating instruction queue reads
487 system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
488 system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
489 system.cpu.iq.int_alu_accesses 823828994 # Number of integer alu accesses
490 system.cpu.iq.fp_alu_accesses 85 # Number of floating point alu accesses
491 system.cpu.iew.lsq.thread0.forwLoads 1638396 # Number of loads that had data forwarded from stores
492 system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
493 system.cpu.iew.lsq.thread0.squashedLoads 3078783 # Number of loads squashed
494 system.cpu.iew.lsq.thread0.ignoredResponses 22684 # Number of memory responses ignored because the instruction is squashed
495 system.cpu.iew.lsq.thread0.memOrderViolation 11490 # Number of memory ordering violations
496 system.cpu.iew.lsq.thread0.squashedStores 1711608 # Number of stores squashed
497 system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
498 system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
499 system.cpu.iew.lsq.thread0.rescheduledLoads 1932396 # Number of loads that were rescheduled
500 system.cpu.iew.lsq.thread0.cacheBlocked 11890 # Number of times an access to memory failed due to the cache being blocked
501 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
502 system.cpu.iew.iewSquashCycles 3552241 # Number of cycles IEW is squashing
503 system.cpu.iew.iewBlockCycles 26088999 # Number of cycles IEW is blocking
504 system.cpu.iew.iewUnblockCycles 2114690 # Number of cycles IEW is unblocking
505 system.cpu.iew.iewDispatchedInsts 829238364 # Number of instructions dispatched to IQ
506 system.cpu.iew.iewDispSquashedInsts 319607 # Number of squashed instructions skipped by dispatch
507 system.cpu.iew.iewDispLoadInsts 17056832 # Number of dispatched load instructions
508 system.cpu.iew.iewDispStoreInsts 10125853 # Number of dispatched store instructions
509 system.cpu.iew.iewDispNonSpecInsts 718701 # Number of dispatched non-speculative instructions
510 system.cpu.iew.iewIQFullEvents 1615260 # Number of times the IQ has become full, causing a stall
511 system.cpu.iew.iewLSQFullEvents 11047 # Number of times the LSQ has become full, causing a stall
512 system.cpu.iew.memOrderViolationEvents 11490 # Number of memory order violations
513 system.cpu.iew.predictedTakenIncorrect 650165 # Number of branches that were predicted taken incorrectly
514 system.cpu.iew.predictedNotTakenIncorrect 594804 # Number of branches that were predicted not taken incorrectly
515 system.cpu.iew.branchMispredicts 1244969 # Number of branch mispredicts detected at execute
516 system.cpu.iew.iewExecutedInsts 821209157 # Number of executed instructions
517 system.cpu.iew.iewExecLoadInsts 17428424 # Number of load instructions executed
518 system.cpu.iew.iewExecSquashedInsts 1866189 # Number of squashed instructions skipped in execute
519 system.cpu.iew.exec_swp 0 # number of swp insts executed
520 system.cpu.iew.exec_nop 0 # number of nop insts executed
521 system.cpu.iew.exec_refs 26576192 # number of memory reference insts executed
522 system.cpu.iew.exec_branches 83198528 # Number of branches executed
523 system.cpu.iew.exec_stores 9147768 # Number of stores executed
524 system.cpu.iew.exec_rate 1.832471 # Inst execution rate
525 system.cpu.iew.wb_sent 820748086 # cumulative count of insts sent to commit
526 system.cpu.iew.wb_count 818612249 # cumulative count of insts written-back
527 system.cpu.iew.wb_producers 639805768 # num instructions producing a value
528 system.cpu.iew.wb_consumers 1045573656 # num instructions consuming a value
529 system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
530 system.cpu.iew.wb_rate 1.826676 # insts written-back per cycle
531 system.cpu.iew.wb_fanout 0.611918 # average fanout of values written-back
532 system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
533 system.cpu.commit.commitSquashedInsts 22746956 # The number of squashed insts skipped by commit
534 system.cpu.commit.commitNonSpecStalls 1052843 # The number of times commit has been forced to stall to communicate backwards
535 system.cpu.commit.branchMispredicts 1113134 # The number of times a branch was mispredicted
536 system.cpu.commit.committed_per_cycle::samples 254292832 # Number of insts commited each cycle
537 system.cpu.commit.committed_per_cycle::mean 3.171083 # Number of insts commited each cycle
538 system.cpu.commit.committed_per_cycle::stdev 2.853965 # Number of insts commited each cycle
539 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
540 system.cpu.commit.committed_per_cycle::0 82512721 32.45% 32.45% # Number of insts commited each cycle
541 system.cpu.commit.committed_per_cycle::1 11810250 4.64% 37.09% # Number of insts commited each cycle
542 system.cpu.commit.committed_per_cycle::2 3911409 1.54% 38.63% # Number of insts commited each cycle
543 system.cpu.commit.committed_per_cycle::3 74946899 29.47% 68.10% # Number of insts commited each cycle
544 system.cpu.commit.committed_per_cycle::4 2433458 0.96% 69.06% # Number of insts commited each cycle
545 system.cpu.commit.committed_per_cycle::5 1482000 0.58% 69.64% # Number of insts commited each cycle
546 system.cpu.commit.committed_per_cycle::6 941049 0.37% 70.01% # Number of insts commited each cycle
547 system.cpu.commit.committed_per_cycle::7 70920641 27.89% 97.90% # Number of insts commited each cycle
548 system.cpu.commit.committed_per_cycle::8 5334405 2.10% 100.00% # Number of insts commited each cycle
549 system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
550 system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
551 system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
552 system.cpu.commit.committed_per_cycle::total 254292832 # Number of insts commited each cycle
553 system.cpu.commit.committedInsts 407935752 # Number of instructions committed
554 system.cpu.commit.committedOps 806383618 # Number of ops (including micro ops) committed
555 system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
556 system.cpu.commit.refs 22392291 # Number of memory references committed
557 system.cpu.commit.loads 13978046 # Number of loads committed
558 system.cpu.commit.membars 473511 # Number of memory barriers committed
559 system.cpu.commit.branches 82192705 # Number of branches committed
560 system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
561 system.cpu.commit.int_insts 735323034 # Number of committed integer instructions.
562 system.cpu.commit.function_calls 0 # Number of function calls committed.
563 system.cpu.commit.bw_lim_events 5334405 # number cycles where commit BW limit reached
564 system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
565 system.cpu.rob.rob_reads 1078010714 # The number of ROB reads
566 system.cpu.rob.rob_writes 1661832245 # The number of ROB writes
567 system.cpu.timesIdled 1221118 # Number of times that the entire CPU went into an idle state and unscheduled itself
568 system.cpu.idleCycles 190298086 # Total number of cycles that the CPU has spent unscheduled due to idling
569 system.cpu.quiesceCycles 9825578883 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
570 system.cpu.committedInsts 407935752 # Number of Instructions Simulated
571 system.cpu.committedOps 806383618 # Number of Ops (including micro ops) Simulated
572 system.cpu.committedInsts_total 407935752 # Number of Instructions Simulated
573 system.cpu.cpi 1.098563 # CPI: Cycles Per Instruction
574 system.cpu.cpi_total 1.098563 # CPI: Total CPI of All Threads
575 system.cpu.ipc 0.910280 # IPC: Instructions Per Cycle
576 system.cpu.ipc_total 0.910280 # IPC: Total IPC of All Threads
577 system.cpu.int_regfile_reads 1506729750 # number of integer regfile reads
578 system.cpu.int_regfile_writes 976791944 # number of integer regfile writes
579 system.cpu.fp_regfile_reads 50 # number of floating regfile reads
580 system.cpu.misc_regfile_reads 264623965 # number of misc regfile reads
581 system.cpu.misc_regfile_writes 402412 # number of misc regfile writes
582 system.cpu.icache.replacements 1049766 # number of replacements
583 system.cpu.icache.tagsinuse 510.907265 # Cycle average of tags in use
584 system.cpu.icache.total_refs 7899601 # Total number of references to valid blocks.
585 system.cpu.icache.sampled_refs 1050278 # Sample count of references to valid blocks.
586 system.cpu.icache.avg_refs 7.521438 # Average number of references to valid blocks.
587 system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit.
588 system.cpu.icache.occ_blocks::cpu.inst 510.907265 # Average occupied blocks per requestor
589 system.cpu.icache.occ_percent::cpu.inst 0.997866 # Average percentage of cache occupancy
590 system.cpu.icache.occ_percent::total 0.997866 # Average percentage of cache occupancy
591 system.cpu.icache.ReadReq_hits::cpu.inst 7899601 # number of ReadReq hits
592 system.cpu.icache.ReadReq_hits::total 7899601 # number of ReadReq hits
593 system.cpu.icache.demand_hits::cpu.inst 7899601 # number of demand (read+write) hits
594 system.cpu.icache.demand_hits::total 7899601 # number of demand (read+write) hits
595 system.cpu.icache.overall_hits::cpu.inst 7899601 # number of overall hits
596 system.cpu.icache.overall_hits::total 7899601 # number of overall hits
597 system.cpu.icache.ReadReq_misses::cpu.inst 1113380 # number of ReadReq misses
598 system.cpu.icache.ReadReq_misses::total 1113380 # number of ReadReq misses
599 system.cpu.icache.demand_misses::cpu.inst 1113380 # number of demand (read+write) misses
600 system.cpu.icache.demand_misses::total 1113380 # number of demand (read+write) misses
601 system.cpu.icache.overall_misses::cpu.inst 1113380 # number of overall misses
602 system.cpu.icache.overall_misses::total 1113380 # number of overall misses
603 system.cpu.icache.ReadReq_miss_latency::cpu.inst 15333448488 # number of ReadReq miss cycles
604 system.cpu.icache.ReadReq_miss_latency::total 15333448488 # number of ReadReq miss cycles
605 system.cpu.icache.demand_miss_latency::cpu.inst 15333448488 # number of demand (read+write) miss cycles
606 system.cpu.icache.demand_miss_latency::total 15333448488 # number of demand (read+write) miss cycles
607 system.cpu.icache.overall_miss_latency::cpu.inst 15333448488 # number of overall miss cycles
608 system.cpu.icache.overall_miss_latency::total 15333448488 # number of overall miss cycles
609 system.cpu.icache.ReadReq_accesses::cpu.inst 9012981 # number of ReadReq accesses(hits+misses)
610 system.cpu.icache.ReadReq_accesses::total 9012981 # number of ReadReq accesses(hits+misses)
611 system.cpu.icache.demand_accesses::cpu.inst 9012981 # number of demand (read+write) accesses
612 system.cpu.icache.demand_accesses::total 9012981 # number of demand (read+write) accesses
613 system.cpu.icache.overall_accesses::cpu.inst 9012981 # number of overall (read+write) accesses
614 system.cpu.icache.overall_accesses::total 9012981 # number of overall (read+write) accesses
615 system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123531 # miss rate for ReadReq accesses
616 system.cpu.icache.ReadReq_miss_rate::total 0.123531 # miss rate for ReadReq accesses
617 system.cpu.icache.demand_miss_rate::cpu.inst 0.123531 # miss rate for demand accesses
618 system.cpu.icache.demand_miss_rate::total 0.123531 # miss rate for demand accesses
619 system.cpu.icache.overall_miss_rate::cpu.inst 0.123531 # miss rate for overall accesses
620 system.cpu.icache.overall_miss_rate::total 0.123531 # miss rate for overall accesses
621 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.981253 # average ReadReq miss latency
622 system.cpu.icache.ReadReq_avg_miss_latency::total 13771.981253 # average ReadReq miss latency
623 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency
624 system.cpu.icache.demand_avg_miss_latency::total 13771.981253 # average overall miss latency
625 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency
626 system.cpu.icache.overall_avg_miss_latency::total 13771.981253 # average overall miss latency
627 system.cpu.icache.blocked_cycles::no_mshrs 13782 # number of cycles access was blocked
628 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
629 system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked
630 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
631 system.cpu.icache.avg_blocked_cycles::no_mshrs 45.485149 # average number of cycles each access was blocked
632 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
633 system.cpu.icache.fast_writes 0 # number of fast writes performed
634 system.cpu.icache.cache_copies 0 # number of cache copies performed
635 system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60842 # number of ReadReq MSHR hits
636 system.cpu.icache.ReadReq_mshr_hits::total 60842 # number of ReadReq MSHR hits
637 system.cpu.icache.demand_mshr_hits::cpu.inst 60842 # number of demand (read+write) MSHR hits
638 system.cpu.icache.demand_mshr_hits::total 60842 # number of demand (read+write) MSHR hits
639 system.cpu.icache.overall_mshr_hits::cpu.inst 60842 # number of overall MSHR hits
640 system.cpu.icache.overall_mshr_hits::total 60842 # number of overall MSHR hits
641 system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052538 # number of ReadReq MSHR misses
642 system.cpu.icache.ReadReq_mshr_misses::total 1052538 # number of ReadReq MSHR misses
643 system.cpu.icache.demand_mshr_misses::cpu.inst 1052538 # number of demand (read+write) MSHR misses
644 system.cpu.icache.demand_mshr_misses::total 1052538 # number of demand (read+write) MSHR misses
645 system.cpu.icache.overall_mshr_misses::cpu.inst 1052538 # number of overall MSHR misses
646 system.cpu.icache.overall_mshr_misses::total 1052538 # number of overall MSHR misses
647 system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12613347488 # number of ReadReq MSHR miss cycles
648 system.cpu.icache.ReadReq_mshr_miss_latency::total 12613347488 # number of ReadReq MSHR miss cycles
649 system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12613347488 # number of demand (read+write) MSHR miss cycles
650 system.cpu.icache.demand_mshr_miss_latency::total 12613347488 # number of demand (read+write) MSHR miss cycles
651 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12613347488 # number of overall MSHR miss cycles
652 system.cpu.icache.overall_mshr_miss_latency::total 12613347488 # number of overall MSHR miss cycles
653 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for ReadReq accesses
654 system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116780 # mshr miss rate for ReadReq accesses
655 system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for demand accesses
656 system.cpu.icache.demand_mshr_miss_rate::total 0.116780 # mshr miss rate for demand accesses
657 system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for overall accesses
658 system.cpu.icache.overall_mshr_miss_rate::total 0.116780 # mshr miss rate for overall accesses
659 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.745469 # average ReadReq mshr miss latency
660 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.745469 # average ReadReq mshr miss latency
661 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency
662 system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency
663 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency
664 system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency
665 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
666 system.cpu.itb_walker_cache.replacements 9783 # number of replacements
667 system.cpu.itb_walker_cache.tagsinuse 6.014217 # Cycle average of tags in use
668 system.cpu.itb_walker_cache.total_refs 28141 # Total number of references to valid blocks.
669 system.cpu.itb_walker_cache.sampled_refs 9798 # Sample count of references to valid blocks.
670 system.cpu.itb_walker_cache.avg_refs 2.872117 # Average number of references to valid blocks.
671 system.cpu.itb_walker_cache.warmup_cycle 5106728958500 # Cycle when the warmup percentage was hit.
672 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.014217 # Average occupied blocks per requestor
673 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375889 # Average percentage of cache occupancy
674 system.cpu.itb_walker_cache.occ_percent::total 0.375889 # Average percentage of cache occupancy
675 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28140 # number of ReadReq hits
676 system.cpu.itb_walker_cache.ReadReq_hits::total 28140 # number of ReadReq hits
677 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
678 system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
679 system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28142 # number of demand (read+write) hits
680 system.cpu.itb_walker_cache.demand_hits::total 28142 # number of demand (read+write) hits
681 system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28142 # number of overall hits
682 system.cpu.itb_walker_cache.overall_hits::total 28142 # number of overall hits
683 system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10689 # number of ReadReq misses
684 system.cpu.itb_walker_cache.ReadReq_misses::total 10689 # number of ReadReq misses
685 system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10689 # number of demand (read+write) misses
686 system.cpu.itb_walker_cache.demand_misses::total 10689 # number of demand (read+write) misses
687 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10689 # number of overall misses
688 system.cpu.itb_walker_cache.overall_misses::total 10689 # number of overall misses
689 system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118046500 # number of ReadReq miss cycles
690 system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118046500 # number of ReadReq miss cycles
691 system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118046500 # number of demand (read+write) miss cycles
692 system.cpu.itb_walker_cache.demand_miss_latency::total 118046500 # number of demand (read+write) miss cycles
693 system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118046500 # number of overall miss cycles
694 system.cpu.itb_walker_cache.overall_miss_latency::total 118046500 # number of overall miss cycles
695 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38829 # number of ReadReq accesses(hits+misses)
696 system.cpu.itb_walker_cache.ReadReq_accesses::total 38829 # number of ReadReq accesses(hits+misses)
697 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
698 system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
699 system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38831 # number of demand (read+write) accesses
700 system.cpu.itb_walker_cache.demand_accesses::total 38831 # number of demand (read+write) accesses
701 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38831 # number of overall (read+write) accesses
702 system.cpu.itb_walker_cache.overall_accesses::total 38831 # number of overall (read+write) accesses
703 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275284 # miss rate for ReadReq accesses
704 system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275284 # miss rate for ReadReq accesses
705 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275270 # miss rate for demand accesses
706 system.cpu.itb_walker_cache.demand_miss_rate::total 0.275270 # miss rate for demand accesses
707 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275270 # miss rate for overall accesses
708 system.cpu.itb_walker_cache.overall_miss_rate::total 0.275270 # miss rate for overall accesses
709 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11043.736552 # average ReadReq miss latency
710 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11043.736552 # average ReadReq miss latency
711 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency
712 system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11043.736552 # average overall miss latency
713 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency
714 system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11043.736552 # average overall miss latency
715 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
716 system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
717 system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
718 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
719 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
720 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
721 system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
722 system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
723 system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks
724 system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks
725 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10689 # number of ReadReq MSHR misses
726 system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10689 # number of ReadReq MSHR misses
727 system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10689 # number of demand (read+write) MSHR misses
728 system.cpu.itb_walker_cache.demand_mshr_misses::total 10689 # number of demand (read+write) MSHR misses
729 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10689 # number of overall MSHR misses
730 system.cpu.itb_walker_cache.overall_mshr_misses::total 10689 # number of overall MSHR misses
731 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96668500 # number of ReadReq MSHR miss cycles
732 system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96668500 # number of ReadReq MSHR miss cycles
733 system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96668500 # number of demand (read+write) MSHR miss cycles
734 system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96668500 # number of demand (read+write) MSHR miss cycles
735 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96668500 # number of overall MSHR miss cycles
736 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96668500 # number of overall MSHR miss cycles
737 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275284 # mshr miss rate for ReadReq accesses
738 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275284 # mshr miss rate for ReadReq accesses
739 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for demand accesses
740 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275270 # mshr miss rate for demand accesses
741 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for overall accesses
742 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275270 # mshr miss rate for overall accesses
743 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average ReadReq mshr miss latency
744 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9043.736552 # average ReadReq mshr miss latency
745 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency
746 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency
747 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency
748 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency
749 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
750 system.cpu.dtb_walker_cache.replacements 108113 # number of replacements
751 system.cpu.dtb_walker_cache.tagsinuse 13.301181 # Cycle average of tags in use
752 system.cpu.dtb_walker_cache.total_refs 134692 # Total number of references to valid blocks.
753 system.cpu.dtb_walker_cache.sampled_refs 108129 # Sample count of references to valid blocks.
754 system.cpu.dtb_walker_cache.avg_refs 1.245660 # Average number of references to valid blocks.
755 system.cpu.dtb_walker_cache.warmup_cycle 5100502305500 # Cycle when the warmup percentage was hit.
756 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.301181 # Average occupied blocks per requestor
757 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.831324 # Average percentage of cache occupancy
758 system.cpu.dtb_walker_cache.occ_percent::total 0.831324 # Average percentage of cache occupancy
759 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134692 # number of ReadReq hits
760 system.cpu.dtb_walker_cache.ReadReq_hits::total 134692 # number of ReadReq hits
761 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134692 # number of demand (read+write) hits
762 system.cpu.dtb_walker_cache.demand_hits::total 134692 # number of demand (read+write) hits
763 system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134692 # number of overall hits
764 system.cpu.dtb_walker_cache.overall_hits::total 134692 # number of overall hits
765 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109183 # number of ReadReq misses
766 system.cpu.dtb_walker_cache.ReadReq_misses::total 109183 # number of ReadReq misses
767 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109183 # number of demand (read+write) misses
768 system.cpu.dtb_walker_cache.demand_misses::total 109183 # number of demand (read+write) misses
769 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109183 # number of overall misses
770 system.cpu.dtb_walker_cache.overall_misses::total 109183 # number of overall misses
771 system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1366356000 # number of ReadReq miss cycles
772 system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1366356000 # number of ReadReq miss cycles
773 system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1366356000 # number of demand (read+write) miss cycles
774 system.cpu.dtb_walker_cache.demand_miss_latency::total 1366356000 # number of demand (read+write) miss cycles
775 system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1366356000 # number of overall miss cycles
776 system.cpu.dtb_walker_cache.overall_miss_latency::total 1366356000 # number of overall miss cycles
777 system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243875 # number of ReadReq accesses(hits+misses)
778 system.cpu.dtb_walker_cache.ReadReq_accesses::total 243875 # number of ReadReq accesses(hits+misses)
779 system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243875 # number of demand (read+write) accesses
780 system.cpu.dtb_walker_cache.demand_accesses::total 243875 # number of demand (read+write) accesses
781 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243875 # number of overall (read+write) accesses
782 system.cpu.dtb_walker_cache.overall_accesses::total 243875 # number of overall (read+write) accesses
783 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447701 # miss rate for ReadReq accesses
784 system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447701 # miss rate for ReadReq accesses
785 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447701 # miss rate for demand accesses
786 system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447701 # miss rate for demand accesses
787 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447701 # miss rate for overall accesses
788 system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447701 # miss rate for overall accesses
789 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12514.365790 # average ReadReq miss latency
790 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12514.365790 # average ReadReq miss latency
791 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency
792 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12514.365790 # average overall miss latency
793 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency
794 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12514.365790 # average overall miss latency
795 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
796 system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
797 system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
798 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
799 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
800 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
801 system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
802 system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
803 system.cpu.dtb_walker_cache.writebacks::writebacks 35577 # number of writebacks
804 system.cpu.dtb_walker_cache.writebacks::total 35577 # number of writebacks
805 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109183 # number of ReadReq MSHR misses
806 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109183 # number of ReadReq MSHR misses
807 system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109183 # number of demand (read+write) MSHR misses
808 system.cpu.dtb_walker_cache.demand_mshr_misses::total 109183 # number of demand (read+write) MSHR misses
809 system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109183 # number of overall MSHR misses
810 system.cpu.dtb_walker_cache.overall_mshr_misses::total 109183 # number of overall MSHR misses
811 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of ReadReq MSHR miss cycles
812 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1147990000 # number of ReadReq MSHR miss cycles
813 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of demand (read+write) MSHR miss cycles
814 system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1147990000 # number of demand (read+write) MSHR miss cycles
815 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of overall MSHR miss cycles
816 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1147990000 # number of overall MSHR miss cycles
817 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for ReadReq accesses
818 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447701 # mshr miss rate for ReadReq accesses
819 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for demand accesses
820 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447701 # mshr miss rate for demand accesses
821 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for overall accesses
822 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447701 # mshr miss rate for overall accesses
823 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average ReadReq mshr miss latency
824 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10514.365790 # average ReadReq mshr miss latency
825 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency
826 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency
827 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency
828 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency
829 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
830 system.cpu.dcache.replacements 1659590 # number of replacements
831 system.cpu.dcache.tagsinuse 511.997640 # Cycle average of tags in use
832 system.cpu.dcache.total_refs 19085008 # Total number of references to valid blocks.
833 system.cpu.dcache.sampled_refs 1660102 # Sample count of references to valid blocks.
834 system.cpu.dcache.avg_refs 11.496286 # Average number of references to valid blocks.
835 system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit.
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838 system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
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840 system.cpu.dcache.ReadReq_hits::total 10993134 # number of ReadReq hits
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842 system.cpu.dcache.WriteReq_hits::total 8086930 # number of WriteReq hits
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848 system.cpu.dcache.ReadReq_misses::total 2235074 # number of ReadReq misses
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850 system.cpu.dcache.WriteReq_misses::total 318068 # number of WriteReq misses
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854 system.cpu.dcache.overall_misses::total 2553142 # number of overall misses
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858 system.cpu.dcache.WriteReq_miss_latency::total 9628285992 # number of WriteReq miss cycles
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862 system.cpu.dcache.overall_miss_latency::total 41750993992 # number of overall miss cycles
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864 system.cpu.dcache.ReadReq_accesses::total 13228208 # number of ReadReq accesses(hits+misses)
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870 system.cpu.dcache.overall_accesses::total 21633206 # number of overall (read+write) accesses
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874 system.cpu.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses
875 system.cpu.dcache.demand_miss_rate::cpu.data 0.118020 # miss rate for demand accesses
876 system.cpu.dcache.demand_miss_rate::total 0.118020 # miss rate for demand accesses
877 system.cpu.dcache.overall_miss_rate::cpu.data 0.118020 # miss rate for overall accesses
878 system.cpu.dcache.overall_miss_rate::total 0.118020 # miss rate for overall accesses
879 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14372.100432 # average ReadReq miss latency
880 system.cpu.dcache.ReadReq_avg_miss_latency::total 14372.100432 # average ReadReq miss latency
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882 system.cpu.dcache.WriteReq_avg_miss_latency::total 30271.155828 # average WriteReq miss latency
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884 system.cpu.dcache.demand_avg_miss_latency::total 16352.789618 # average overall miss latency
885 system.cpu.dcache.overall_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency
886 system.cpu.dcache.overall_avg_miss_latency::total 16352.789618 # average overall miss latency
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888 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
889 system.cpu.dcache.blocked::no_mshrs 42426 # number of cycles access was blocked
890 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
891 system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397916 # average number of cycles each access was blocked
892 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
893 system.cpu.dcache.fast_writes 0 # number of fast writes performed
894 system.cpu.dcache.cache_copies 0 # number of cache copies performed
895 system.cpu.dcache.writebacks::writebacks 1560986 # number of writebacks
896 system.cpu.dcache.writebacks::total 1560986 # number of writebacks
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898 system.cpu.dcache.ReadReq_mshr_hits::total 863566 # number of ReadReq MSHR hits
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900 system.cpu.dcache.WriteReq_mshr_hits::total 25004 # number of WriteReq MSHR hits
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902 system.cpu.dcache.demand_mshr_hits::total 888570 # number of demand (read+write) MSHR hits
903 system.cpu.dcache.overall_mshr_hits::cpu.data 888570 # number of overall MSHR hits
904 system.cpu.dcache.overall_mshr_hits::total 888570 # number of overall MSHR hits
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908 system.cpu.dcache.WriteReq_mshr_misses::total 293064 # number of WriteReq MSHR misses
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912 system.cpu.dcache.overall_mshr_misses::total 1664572 # number of overall MSHR misses
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914 system.cpu.dcache.ReadReq_mshr_miss_latency::total 17458468000 # number of ReadReq MSHR miss cycles
915 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8785727992 # number of WriteReq MSHR miss cycles
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918 system.cpu.dcache.demand_mshr_miss_latency::total 26244195992 # number of demand (read+write) MSHR miss cycles
919 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26244195992 # number of overall MSHR miss cycles
920 system.cpu.dcache.overall_mshr_miss_latency::total 26244195992 # number of overall MSHR miss cycles
921 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97297948500 # number of ReadReq MSHR uncacheable cycles
922 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97297948500 # number of ReadReq MSHR uncacheable cycles
923 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473076000 # number of WriteReq MSHR uncacheable cycles
924 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473076000 # number of WriteReq MSHR uncacheable cycles
925 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771024500 # number of overall MSHR uncacheable cycles
926 system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771024500 # number of overall MSHR uncacheable cycles
927 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103681 # mshr miss rate for ReadReq accesses
928 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103681 # mshr miss rate for ReadReq accesses
929 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034868 # mshr miss rate for WriteReq accesses
930 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034868 # mshr miss rate for WriteReq accesses
931 system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076945 # mshr miss rate for demand accesses
932 system.cpu.dcache.demand_mshr_miss_rate::total 0.076945 # mshr miss rate for demand accesses
933 system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076945 # mshr miss rate for overall accesses
934 system.cpu.dcache.overall_mshr_miss_rate::total 0.076945 # mshr miss rate for overall accesses
935 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12729.395673 # average ReadReq mshr miss latency
936 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12729.395673 # average ReadReq mshr miss latency
937 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29978.871482 # average WriteReq mshr miss latency
938 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29978.871482 # average WriteReq mshr miss latency
939 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.332722 # average overall mshr miss latency
940 system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.332722 # average overall mshr miss latency
941 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15766.332722 # average overall mshr miss latency
942 system.cpu.dcache.overall_avg_mshr_miss_latency::total 15766.332722 # average overall mshr miss latency
943 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
944 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
945 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
946 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
947 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
948 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
949 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
950 system.cpu.l2cache.replacements 113184 # number of replacements
951 system.cpu.l2cache.tagsinuse 64838.652063 # Cycle average of tags in use
952 system.cpu.l2cache.total_refs 3931021 # Total number of references to valid blocks.
953 system.cpu.l2cache.sampled_refs 177284 # Sample count of references to valid blocks.
954 system.cpu.l2cache.avg_refs 22.173580 # Average number of references to valid blocks.
955 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
956 system.cpu.l2cache.occ_blocks::writebacks 50168.170279 # Average occupied blocks per requestor
957 system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.493195 # Average occupied blocks per requestor
958 system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133179 # Average occupied blocks per requestor
959 system.cpu.l2cache.occ_blocks::cpu.inst 3227.427363 # Average occupied blocks per requestor
960 system.cpu.l2cache.occ_blocks::cpu.data 11429.428047 # Average occupied blocks per requestor
961 system.cpu.l2cache.occ_percent::writebacks 0.765506 # Average percentage of cache occupancy
962 system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000206 # Average percentage of cache occupancy
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964 system.cpu.l2cache.occ_percent::cpu.inst 0.049247 # Average percentage of cache occupancy
965 system.cpu.l2cache.occ_percent::cpu.data 0.174399 # Average percentage of cache occupancy
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972 system.cpu.l2cache.Writeback_hits::writebacks 1598556 # number of Writeback hits
973 system.cpu.l2cache.Writeback_hits::total 1598556 # number of Writeback hits
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975 system.cpu.l2cache.UpgradeReq_hits::total 335 # number of UpgradeReq hits
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977 system.cpu.l2cache.ReadExReq_hits::total 156370 # number of ReadExReq hits
978 system.cpu.l2cache.demand_hits::cpu.dtb.walker 101466 # number of demand (read+write) hits
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1016 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4666500 # number of demand (read+write) miss cycles
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1021 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4666500 # number of overall miss cycles
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1023 system.cpu.l2cache.overall_miss_latency::cpu.inst 1174285000 # number of overall miss cycles
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1026 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101519 # number of ReadReq accesses(hits+misses)
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1030 system.cpu.l2cache.ReadReq_accesses::total 2530182 # number of ReadReq accesses(hits+misses)
1031 system.cpu.l2cache.Writeback_accesses::writebacks 1598556 # number of Writeback accesses(hits+misses)
1032 system.cpu.l2cache.Writeback_accesses::total 1598556 # number of Writeback accesses(hits+misses)
1033 system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3960 # number of UpgradeReq accesses(hits+misses)
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1042 system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101519 # number of overall (read+write) accesses
1043 system.cpu.l2cache.overall_accesses::cpu.itb.walker 8121 # number of overall (read+write) accesses
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1045 system.cpu.l2cache.overall_accesses::cpu.data 1659486 # number of overall (read+write) accesses
1046 system.cpu.l2cache.overall_accesses::total 2819361 # number of overall (read+write) accesses
1047 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000522 # miss rate for ReadReq accesses
1048 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000862 # miss rate for ReadReq accesses
1049 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016044 # miss rate for ReadReq accesses
1050 system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026776 # miss rate for ReadReq accesses
1051 system.cpu.l2cache.ReadReq_miss_rate::total 0.021185 # miss rate for ReadReq accesses
1052 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.915404 # miss rate for UpgradeReq accesses
1053 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.915404 # miss rate for UpgradeReq accesses
1054 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459262 # miss rate for ReadExReq accesses
1055 system.cpu.l2cache.ReadExReq_miss_rate::total 0.459262 # miss rate for ReadExReq accesses
1056 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000522 # miss rate for demand accesses
1057 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000862 # miss rate for demand accesses
1058 system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016044 # miss rate for demand accesses
1059 system.cpu.l2cache.demand_miss_rate::cpu.data 0.102140 # miss rate for demand accesses
1060 system.cpu.l2cache.demand_miss_rate::total 0.066118 # miss rate for demand accesses
1061 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000522 # miss rate for overall accesses
1062 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000862 # miss rate for overall accesses
1063 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016044 # miss rate for overall accesses
1064 system.cpu.l2cache.overall_miss_rate::cpu.data 0.102140 # miss rate for overall accesses
1065 system.cpu.l2cache.overall_miss_rate::total 0.066118 # miss rate for overall accesses
1066 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88047.169811 # average ReadReq miss latency
1067 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65571.428571 # average ReadReq miss latency
1068 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69690.504451 # average ReadReq miss latency
1069 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68722.956556 # average ReadReq miss latency
1070 system.cpu.l2cache.ReadReq_avg_miss_latency::total 69045.810694 # average ReadReq miss latency
1071 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4733.379310 # average UpgradeReq miss latency
1072 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4733.379310 # average UpgradeReq miss latency
1073 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51491.713664 # average ReadExReq miss latency
1074 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51491.713664 # average ReadExReq miss latency
1075 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88047.169811 # average overall miss latency
1076 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65571.428571 # average overall miss latency
1077 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69690.504451 # average overall miss latency
1078 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55221.693209 # average overall miss latency
1079 system.cpu.l2cache.demand_avg_miss_latency::total 56539.281686 # average overall miss latency
1080 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88047.169811 # average overall miss latency
1081 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65571.428571 # average overall miss latency
1082 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69690.504451 # average overall miss latency
1083 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55221.693209 # average overall miss latency
1084 system.cpu.l2cache.overall_avg_miss_latency::total 56539.281686 # average overall miss latency
1085 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1086 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1087 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1088 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1089 system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1090 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1091 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1092 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1093 system.cpu.l2cache.writebacks::writebacks 102512 # number of writebacks
1094 system.cpu.l2cache.writebacks::total 102512 # number of writebacks
1095 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
1096 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
1097 system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
1098 system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
1099 system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
1100 system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
1101 system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
1102 system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
1103 system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
1104 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses
1105 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
1106 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16848 # number of ReadReq MSHR misses
1107 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36690 # number of ReadReq MSHR misses
1108 system.cpu.l2cache.ReadReq_mshr_misses::total 53598 # number of ReadReq MSHR misses
1109 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3625 # number of UpgradeReq MSHR misses
1110 system.cpu.l2cache.UpgradeReq_mshr_misses::total 3625 # number of UpgradeReq MSHR misses
1111 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132809 # number of ReadExReq MSHR misses
1112 system.cpu.l2cache.ReadExReq_mshr_misses::total 132809 # number of ReadExReq MSHR misses
1113 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses
1114 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
1115 system.cpu.l2cache.demand_mshr_misses::cpu.inst 16848 # number of demand (read+write) MSHR misses
1116 system.cpu.l2cache.demand_mshr_misses::cpu.data 169499 # number of demand (read+write) MSHR misses
1117 system.cpu.l2cache.demand_mshr_misses::total 186407 # number of demand (read+write) MSHR misses
1118 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses
1119 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
1120 system.cpu.l2cache.overall_mshr_misses::cpu.inst 16848 # number of overall MSHR misses
1121 system.cpu.l2cache.overall_mshr_misses::cpu.data 169499 # number of overall MSHR misses
1122 system.cpu.l2cache.overall_mshr_misses::total 186407 # number of overall MSHR misses
1123 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4003602 # number of ReadReq MSHR miss cycles
1124 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 370512 # number of ReadReq MSHR miss cycles
1125 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964285581 # number of ReadReq MSHR miss cycles
1126 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2065462567 # number of ReadReq MSHR miss cycles
1127 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3034122262 # number of ReadReq MSHR miss cycles
1128 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37079107 # number of UpgradeReq MSHR miss cycles
1129 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37079107 # number of UpgradeReq MSHR miss cycles
1130 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200762570 # number of ReadExReq MSHR miss cycles
1131 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200762570 # number of ReadExReq MSHR miss cycles
1132 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4003602 # number of demand (read+write) MSHR miss cycles
1133 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 370512 # number of demand (read+write) MSHR miss cycles
1134 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964285581 # number of demand (read+write) MSHR miss cycles
1135 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7266225137 # number of demand (read+write) MSHR miss cycles
1136 system.cpu.l2cache.demand_mshr_miss_latency::total 8234884832 # number of demand (read+write) MSHR miss cycles
1137 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4003602 # number of overall MSHR miss cycles
1138 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 370512 # number of overall MSHR miss cycles
1139 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964285581 # number of overall MSHR miss cycles
1140 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7266225137 # number of overall MSHR miss cycles
1141 system.cpu.l2cache.overall_mshr_miss_latency::total 8234884832 # number of overall MSHR miss cycles
1142 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89188560000 # number of ReadReq MSHR uncacheable cycles
1143 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89188560000 # number of ReadReq MSHR uncacheable cycles
1144 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2310705000 # number of WriteReq MSHR uncacheable cycles
1145 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2310705000 # number of WriteReq MSHR uncacheable cycles
1146 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91499265000 # number of overall MSHR uncacheable cycles
1147 system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91499265000 # number of overall MSHR uncacheable cycles
1148 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for ReadReq accesses
1149 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for ReadReq accesses
1150 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for ReadReq accesses
1151 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026775 # mshr miss rate for ReadReq accesses
1152 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021183 # mshr miss rate for ReadReq accesses
1153 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915404 # mshr miss rate for UpgradeReq accesses
1154 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915404 # mshr miss rate for UpgradeReq accesses
1155 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459262 # mshr miss rate for ReadExReq accesses
1156 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459262 # mshr miss rate for ReadExReq accesses
1157 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for demand accesses
1158 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for demand accesses
1159 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for demand accesses
1160 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for demand accesses
1161 system.cpu.l2cache.demand_mshr_miss_rate::total 0.066117 # mshr miss rate for demand accesses
1162 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for overall accesses
1163 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for overall accesses
1164 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for overall accesses
1165 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for overall accesses
1166 system.cpu.l2cache.overall_mshr_miss_rate::total 0.066117 # mshr miss rate for overall accesses
1167 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average ReadReq mshr miss latency
1168 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average ReadReq mshr miss latency
1169 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57234.424323 # average ReadReq mshr miss latency
1170 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56294.973208 # average ReadReq mshr miss latency
1171 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56608.870891 # average ReadReq mshr miss latency
1172 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10228.719172 # average UpgradeReq mshr miss latency
1173 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10228.719172 # average UpgradeReq mshr miss latency
1174 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39159.714854 # average ReadExReq mshr miss latency
1175 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39159.714854 # average ReadExReq mshr miss latency
1176 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency
1177 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency
1178 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency
1179 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency
1180 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency
1181 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency
1182 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency
1183 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency
1184 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency
1185 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency
1186 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1187 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1188 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1189 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1190 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1191 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1192 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1193 system.cpu.kern.inst.arm 0 # number of arm instructions executed
1194 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
1196 ---------- End Simulation Statistics ----------
projects / gem5.git / blob