8 time_sync_period=100000000000
9 time_sync_spin_threshold=100000000
13 children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
14 acpi_description_table_pointer=system.acpi_description_table_pointer
15 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
17 clk_domain=system.clk_domain
18 e820_table=system.e820_table
21 intel_mp_pointer=system.intel_mp_pointer
22 intel_mp_table=system.intel_mp_table
23 kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
24 load_addr_mask=18446744073709551615
27 mem_ranges=0:134217727
28 memories=system.physmem
30 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
31 smbios_table=system.smbios_table
33 work_begin_ckpt_count=0
34 work_begin_cpu_id_exit=-1
35 work_begin_exit_count=0
36 work_cpus_ckpt_count=0
40 system_port=system.membus.slave[1]
42 [system.acpi_description_table_pointer]
49 xsdt=system.acpi_description_table_pointer.xsdt
51 [system.acpi_description_table_pointer.xsdt]
63 clk_domain=system.clk_domain
66 ranges=11529215046068469760:11529215046068473855
69 master=system.membus.slave[0]
70 slave=system.iobus.master[0]
74 clk_domain=system.clk_domain
77 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
80 master=system.iobus.slave[0]
81 slave=system.membus.master[0]
87 voltage_domain=system.voltage_domain
91 children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
94 clk_domain=system.cpu_clk_domain
96 do_checkpoint_insts=true
98 do_statistics_insts=true
103 function_trace_start=0
104 interrupts=system.cpu0.interrupts
107 max_insts_all_threads=0
108 max_insts_any_thread=0
109 max_loads_all_threads=0
110 max_loads_any_thread=0
114 simpoint_interval=100000000
115 simpoint_profile=false
116 simpoint_profile_file=simpoint.bb.gz
117 simpoint_start_insts=
118 simulate_data_stalls=false
119 simulate_inst_stalls=false
123 tracer=system.cpu0.tracer
126 dcache_port=system.cpu0.dcache.cpu_side
127 icache_port=system.cpu0.icache.cpu_side
129 [system.cpu0.apic_clk_domain]
130 type=DerivedClockDomain
132 clk_domain=system.cpu_clk_domain
138 addr_ranges=0:18446744073709551615
140 clk_domain=system.cpu_clk_domain
147 prefetch_on_access=false
150 sequential_access=false
153 tags=system.cpu0.dcache.tags
157 cpu_side=system.cpu0.dcache_port
158 mem_side=system.toL2Bus.slave[1]
160 [system.cpu0.dcache.tags]
164 clk_domain=system.cpu_clk_domain
167 sequential_access=false
175 walker=system.cpu0.dtb.walker
177 [system.cpu0.dtb.walker]
178 type=X86PagetableWalker
179 clk_domain=system.cpu_clk_domain
181 num_squash_per_cycle=4
183 port=system.toL2Bus.slave[3]
188 addr_ranges=0:18446744073709551615
190 clk_domain=system.cpu_clk_domain
197 prefetch_on_access=false
200 sequential_access=false
203 tags=system.cpu0.icache.tags
207 cpu_side=system.cpu0.icache_port
208 mem_side=system.toL2Bus.slave[0]
210 [system.cpu0.icache.tags]
214 clk_domain=system.cpu_clk_domain
217 sequential_access=false
220 [system.cpu0.interrupts]
222 clk_domain=system.cpu0.apic_clk_domain
225 pio_addr=2305843009213693952
228 int_master=system.membus.slave[3]
229 int_slave=system.membus.master[2]
230 pio=system.membus.master[1]
241 walker=system.cpu0.itb.walker
243 [system.cpu0.itb.walker]
244 type=X86PagetableWalker
245 clk_domain=system.cpu_clk_domain
247 num_squash_per_cycle=4
249 port=system.toL2Bus.slave[2]
257 children=dtb isa itb tracer
260 clk_domain=system.cpu_clk_domain
262 do_checkpoint_insts=true
264 do_statistics_insts=true
268 function_trace_start=0
272 max_insts_all_threads=0
273 max_insts_any_thread=0
274 max_loads_all_threads=0
275 max_loads_any_thread=0
279 simpoint_start_insts=
283 tracer=system.cpu1.tracer
291 walker=system.cpu1.dtb.walker
293 [system.cpu1.dtb.walker]
294 type=X86PagetableWalker
295 clk_domain=system.cpu_clk_domain
297 num_squash_per_cycle=4
309 walker=system.cpu1.itb.walker
311 [system.cpu1.itb.walker]
312 type=X86PagetableWalker
313 clk_domain=system.cpu_clk_domain
315 num_squash_per_cycle=4
324 children=branchPred dtb fuPool isa itb tracer
333 branchPred=system.cpu2.branchPred
336 clk_domain=system.cpu_clk_domain
337 commitToDecodeDelay=1
340 commitToRenameDelay=1
344 decodeToRenameDelay=1
347 do_checkpoint_insts=true
349 do_statistics_insts=true
357 fuPool=system.cpu2.fuPool
359 function_trace_start=0
366 issueToExecuteDelay=1
369 max_insts_all_threads=0
370 max_insts_any_thread=0
371 max_loads_all_threads=0
372 max_loads_any_thread=0
383 renameToDecodeDelay=1
388 simpoint_start_insts=
389 smtCommitPolicy=RoundRobin
390 smtFetchPolicy=SingleThread
391 smtIQPolicy=Partitioned
393 smtLSQPolicy=Partitioned
395 smtNumFetchingThreads=1
396 smtROBPolicy=Partitioned
400 store_set_clear_period=250000
403 tracer=system.cpu2.tracer
409 [system.cpu2.branchPred]
415 choicePredictorSize=8192
418 globalPredictorSize=8192
421 localHistoryTableSize=2048
422 localPredictorSize=2048
431 walker=system.cpu2.dtb.walker
433 [system.cpu2.dtb.walker]
434 type=X86PagetableWalker
435 clk_domain=system.cpu_clk_domain
437 num_squash_per_cycle=4
442 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
443 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
446 [system.cpu2.fuPool.FUList0]
451 opList=system.cpu2.fuPool.FUList0.opList
453 [system.cpu2.fuPool.FUList0.opList]
460 [system.cpu2.fuPool.FUList1]
462 children=opList0 opList1
465 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
467 [system.cpu2.fuPool.FUList1.opList0]
474 [system.cpu2.fuPool.FUList1.opList1]
481 [system.cpu2.fuPool.FUList2]
483 children=opList0 opList1 opList2
486 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
488 [system.cpu2.fuPool.FUList2.opList0]
495 [system.cpu2.fuPool.FUList2.opList1]
502 [system.cpu2.fuPool.FUList2.opList2]
509 [system.cpu2.fuPool.FUList3]
511 children=opList0 opList1 opList2
514 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
516 [system.cpu2.fuPool.FUList3.opList0]
523 [system.cpu2.fuPool.FUList3.opList1]
530 [system.cpu2.fuPool.FUList3.opList2]
537 [system.cpu2.fuPool.FUList4]
542 opList=system.cpu2.fuPool.FUList4.opList
544 [system.cpu2.fuPool.FUList4.opList]
551 [system.cpu2.fuPool.FUList5]
553 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
556 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
558 [system.cpu2.fuPool.FUList5.opList00]
565 [system.cpu2.fuPool.FUList5.opList01]
572 [system.cpu2.fuPool.FUList5.opList02]
579 [system.cpu2.fuPool.FUList5.opList03]
586 [system.cpu2.fuPool.FUList5.opList04]
593 [system.cpu2.fuPool.FUList5.opList05]
600 [system.cpu2.fuPool.FUList5.opList06]
607 [system.cpu2.fuPool.FUList5.opList07]
614 [system.cpu2.fuPool.FUList5.opList08]
621 [system.cpu2.fuPool.FUList5.opList09]
628 [system.cpu2.fuPool.FUList5.opList10]
635 [system.cpu2.fuPool.FUList5.opList11]
642 [system.cpu2.fuPool.FUList5.opList12]
649 [system.cpu2.fuPool.FUList5.opList13]
656 [system.cpu2.fuPool.FUList5.opList14]
663 [system.cpu2.fuPool.FUList5.opList15]
670 [system.cpu2.fuPool.FUList5.opList16]
674 opClass=SimdFloatMisc
677 [system.cpu2.fuPool.FUList5.opList17]
681 opClass=SimdFloatMult
684 [system.cpu2.fuPool.FUList5.opList18]
688 opClass=SimdFloatMultAcc
691 [system.cpu2.fuPool.FUList5.opList19]
695 opClass=SimdFloatSqrt
698 [system.cpu2.fuPool.FUList6]
703 opList=system.cpu2.fuPool.FUList6.opList
705 [system.cpu2.fuPool.FUList6.opList]
712 [system.cpu2.fuPool.FUList7]
714 children=opList0 opList1
717 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
719 [system.cpu2.fuPool.FUList7.opList0]
726 [system.cpu2.fuPool.FUList7.opList1]
733 [system.cpu2.fuPool.FUList8]
738 opList=system.cpu2.fuPool.FUList8.opList
740 [system.cpu2.fuPool.FUList8.opList]
756 walker=system.cpu2.itb.walker
758 [system.cpu2.itb.walker]
759 type=X86PagetableWalker
760 clk_domain=system.cpu_clk_domain
762 num_squash_per_cycle=4
769 [system.cpu_clk_domain]
773 voltage_domain=system.voltage_domain
777 children=entries0 entries1 entries2 entries3
778 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
781 [system.e820_table.entries0]
788 [system.e820_table.entries1]
795 [system.e820_table.entries2]
802 [system.e820_table.entries3]
809 [system.intel_mp_pointer]
810 type=X86IntelMPFloatingPointer
816 [system.intel_mp_table]
817 type=X86IntelMPConfigTable
818 children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
819 base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
821 ext_entries=system.intel_mp_table.ext_entries
822 local_apic=4276092928
829 [system.intel_mp_table.base_entries00]
830 type=X86IntelMPProcessor
837 local_apic_version=20
841 [system.intel_mp_table.base_entries01]
842 type=X86IntelMPIOAPIC
849 [system.intel_mp_table.base_entries02]
855 [system.intel_mp_table.base_entries03]
861 [system.intel_mp_table.base_entries04]
862 type=X86IntelMPIOIntAssignment
864 dest_io_apic_intin=16
867 polarity=ConformPolarity
870 trigger=ConformTrigger
872 [system.intel_mp_table.base_entries05]
873 type=X86IntelMPIOIntAssignment
877 interrupt_type=ExtInt
878 polarity=ConformPolarity
881 trigger=ConformTrigger
883 [system.intel_mp_table.base_entries06]
884 type=X86IntelMPIOIntAssignment
889 polarity=ConformPolarity
892 trigger=ConformTrigger
894 [system.intel_mp_table.base_entries07]
895 type=X86IntelMPIOIntAssignment
899 interrupt_type=ExtInt
900 polarity=ConformPolarity
903 trigger=ConformTrigger
905 [system.intel_mp_table.base_entries08]
906 type=X86IntelMPIOIntAssignment
911 polarity=ConformPolarity
914 trigger=ConformTrigger
916 [system.intel_mp_table.base_entries09]
917 type=X86IntelMPIOIntAssignment
921 interrupt_type=ExtInt
922 polarity=ConformPolarity
925 trigger=ConformTrigger
927 [system.intel_mp_table.base_entries10]
928 type=X86IntelMPIOIntAssignment
933 polarity=ConformPolarity
936 trigger=ConformTrigger
938 [system.intel_mp_table.base_entries11]
939 type=X86IntelMPIOIntAssignment
943 interrupt_type=ExtInt
944 polarity=ConformPolarity
947 trigger=ConformTrigger
949 [system.intel_mp_table.base_entries12]
950 type=X86IntelMPIOIntAssignment
955 polarity=ConformPolarity
958 trigger=ConformTrigger
960 [system.intel_mp_table.base_entries13]
961 type=X86IntelMPIOIntAssignment
965 interrupt_type=ExtInt
966 polarity=ConformPolarity
969 trigger=ConformTrigger
971 [system.intel_mp_table.base_entries14]
972 type=X86IntelMPIOIntAssignment
977 polarity=ConformPolarity
980 trigger=ConformTrigger
982 [system.intel_mp_table.base_entries15]
983 type=X86IntelMPIOIntAssignment
987 interrupt_type=ExtInt
988 polarity=ConformPolarity
991 trigger=ConformTrigger
993 [system.intel_mp_table.base_entries16]
994 type=X86IntelMPIOIntAssignment
999 polarity=ConformPolarity
1002 trigger=ConformTrigger
1004 [system.intel_mp_table.base_entries17]
1005 type=X86IntelMPIOIntAssignment
1007 dest_io_apic_intin=0
1009 interrupt_type=ExtInt
1010 polarity=ConformPolarity
1013 trigger=ConformTrigger
1015 [system.intel_mp_table.base_entries18]
1016 type=X86IntelMPIOIntAssignment
1018 dest_io_apic_intin=7
1021 polarity=ConformPolarity
1024 trigger=ConformTrigger
1026 [system.intel_mp_table.base_entries19]
1027 type=X86IntelMPIOIntAssignment
1029 dest_io_apic_intin=0
1031 interrupt_type=ExtInt
1032 polarity=ConformPolarity
1035 trigger=ConformTrigger
1037 [system.intel_mp_table.base_entries20]
1038 type=X86IntelMPIOIntAssignment
1040 dest_io_apic_intin=8
1043 polarity=ConformPolarity
1046 trigger=ConformTrigger
1048 [system.intel_mp_table.base_entries21]
1049 type=X86IntelMPIOIntAssignment
1051 dest_io_apic_intin=0
1053 interrupt_type=ExtInt
1054 polarity=ConformPolarity
1057 trigger=ConformTrigger
1059 [system.intel_mp_table.base_entries22]
1060 type=X86IntelMPIOIntAssignment
1062 dest_io_apic_intin=9
1065 polarity=ConformPolarity
1068 trigger=ConformTrigger
1070 [system.intel_mp_table.base_entries23]
1071 type=X86IntelMPIOIntAssignment
1073 dest_io_apic_intin=0
1075 interrupt_type=ExtInt
1076 polarity=ConformPolarity
1079 trigger=ConformTrigger
1081 [system.intel_mp_table.base_entries24]
1082 type=X86IntelMPIOIntAssignment
1084 dest_io_apic_intin=10
1087 polarity=ConformPolarity
1090 trigger=ConformTrigger
1092 [system.intel_mp_table.base_entries25]
1093 type=X86IntelMPIOIntAssignment
1095 dest_io_apic_intin=0
1097 interrupt_type=ExtInt
1098 polarity=ConformPolarity
1101 trigger=ConformTrigger
1103 [system.intel_mp_table.base_entries26]
1104 type=X86IntelMPIOIntAssignment
1106 dest_io_apic_intin=11
1109 polarity=ConformPolarity
1112 trigger=ConformTrigger
1114 [system.intel_mp_table.base_entries27]
1115 type=X86IntelMPIOIntAssignment
1117 dest_io_apic_intin=0
1119 interrupt_type=ExtInt
1120 polarity=ConformPolarity
1123 trigger=ConformTrigger
1125 [system.intel_mp_table.base_entries28]
1126 type=X86IntelMPIOIntAssignment
1128 dest_io_apic_intin=12
1131 polarity=ConformPolarity
1134 trigger=ConformTrigger
1136 [system.intel_mp_table.base_entries29]
1137 type=X86IntelMPIOIntAssignment
1139 dest_io_apic_intin=0
1141 interrupt_type=ExtInt
1142 polarity=ConformPolarity
1145 trigger=ConformTrigger
1147 [system.intel_mp_table.base_entries30]
1148 type=X86IntelMPIOIntAssignment
1150 dest_io_apic_intin=13
1153 polarity=ConformPolarity
1156 trigger=ConformTrigger
1158 [system.intel_mp_table.base_entries31]
1159 type=X86IntelMPIOIntAssignment
1161 dest_io_apic_intin=0
1163 interrupt_type=ExtInt
1164 polarity=ConformPolarity
1167 trigger=ConformTrigger
1169 [system.intel_mp_table.base_entries32]
1170 type=X86IntelMPIOIntAssignment
1172 dest_io_apic_intin=14
1175 polarity=ConformPolarity
1178 trigger=ConformTrigger
1180 [system.intel_mp_table.ext_entries]
1181 type=X86IntelMPBusHierarchy
1185 subtractive_decode=true
1194 clk_domain=system.clk_domain
1197 use_default_range=true
1199 default=system.pc.pciconfig.pio
1200 master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
1201 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
1206 addr_ranges=0:134217727
1208 clk_domain=system.clk_domain
1210 forward_snoops=false
1215 prefetch_on_access=false
1218 sequential_access=false
1221 tags=system.iocache.tags
1225 cpu_side=system.iobus.master[18]
1226 mem_side=system.membus.slave[4]
1228 [system.iocache.tags]
1232 clk_domain=system.clk_domain
1235 sequential_access=false
1241 addr_ranges=0:18446744073709551615
1243 clk_domain=system.cpu_clk_domain
1250 prefetch_on_access=false
1253 sequential_access=false
1256 tags=system.l2c.tags
1260 cpu_side=system.toL2Bus.master[0]
1261 mem_side=system.membus.slave[2]
1267 clk_domain=system.cpu_clk_domain
1270 sequential_access=false
1275 children=badaddr_responder
1276 clk_domain=system.clk_domain
1280 use_default_range=false
1282 default=system.membus.badaddr_responder.pio
1283 master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
1284 slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
1286 [system.membus.badaddr_responder]
1288 clk_domain=system.clk_domain
1296 ret_data32=4294967295
1297 ret_data64=18446744073709551615
1302 pio=system.membus.default
1306 children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
1308 intrctrl=system.intrctrl
1311 [system.pc.behind_pci]
1313 clk_domain=system.clk_domain
1316 pio_addr=9223372036854779128
1321 ret_data32=4294967295
1322 ret_data64=18446744073709551615
1327 pio=system.iobus.master[12]
1332 clk_domain=system.clk_domain
1334 pio_addr=9223372036854776824
1338 terminal=system.pc.com_1.terminal
1339 pio=system.iobus.master[13]
1341 [system.pc.com_1.terminal]
1344 intr_control=system.intrctrl
1349 [system.pc.fake_com_2]
1351 clk_domain=system.clk_domain
1354 pio_addr=9223372036854776568
1359 ret_data32=4294967295
1360 ret_data64=18446744073709551615
1365 pio=system.iobus.master[14]
1367 [system.pc.fake_com_3]
1369 clk_domain=system.clk_domain
1372 pio_addr=9223372036854776808
1377 ret_data32=4294967295
1378 ret_data64=18446744073709551615
1383 pio=system.iobus.master[15]
1385 [system.pc.fake_com_4]
1387 clk_domain=system.clk_domain
1390 pio_addr=9223372036854776552
1395 ret_data32=4294967295
1396 ret_data64=18446744073709551615
1401 pio=system.iobus.master[16]
1403 [system.pc.fake_floppy]
1405 clk_domain=system.clk_domain
1408 pio_addr=9223372036854776818
1413 ret_data32=4294967295
1414 ret_data64=18446744073709551615
1419 pio=system.iobus.master[17]
1421 [system.pc.i_dont_exist]
1423 clk_domain=system.clk_domain
1426 pio_addr=9223372036854775936
1431 ret_data32=4294967295
1432 ret_data64=18446744073709551615
1437 pio=system.iobus.master[11]
1439 [system.pc.pciconfig]
1442 clk_domain=system.clk_domain
1449 pio=system.iobus.default
1451 [system.pc.south_bridge]
1453 children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
1454 cmos=system.pc.south_bridge.cmos
1455 dma1=system.pc.south_bridge.dma1
1457 io_apic=system.pc.south_bridge.io_apic
1458 keyboard=system.pc.south_bridge.keyboard
1459 pic1=system.pc.south_bridge.pic1
1460 pic2=system.pc.south_bridge.pic2
1461 pit=system.pc.south_bridge.pit
1463 speaker=system.pc.south_bridge.speaker
1465 [system.pc.south_bridge.cmos]
1468 clk_domain=system.clk_domain
1470 int_pin=system.pc.south_bridge.cmos.int_pin
1471 pio_addr=9223372036854775920
1474 time=Sun Jan 1 00:00:00 2012
1475 pio=system.iobus.master[1]
1477 [system.pc.south_bridge.cmos.int_pin]
1478 type=X86IntSourcePin
1481 [system.pc.south_bridge.dma1]
1483 clk_domain=system.clk_domain
1485 pio_addr=9223372036854775808
1488 pio=system.iobus.master[2]
1490 [system.pc.south_bridge.ide]
1492 children=disks0 disks1
1529 MSICAPMsgUpperAddr=0
1530 MSICAPNextCapability=0
1534 MSIXCAPNextCapability=0
1544 PMCAPNextCapability=0
1549 PXCAPDevCapabilities=0
1556 PXCAPNextCapability=0
1564 clk_domain=system.clk_domain
1565 config_latency=20000
1567 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
1576 config=system.iobus.master[4]
1577 dma=system.iobus.slave[1]
1578 pio=system.iobus.master[3]
1580 [system.pc.south_bridge.ide.disks0]
1586 image=system.pc.south_bridge.ide.disks0.image
1588 [system.pc.south_bridge.ide.disks0.image]
1591 child=system.pc.south_bridge.ide.disks0.image.child
1597 [system.pc.south_bridge.ide.disks0.image.child]
1600 image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
1603 [system.pc.south_bridge.ide.disks1]
1609 image=system.pc.south_bridge.ide.disks1.image
1611 [system.pc.south_bridge.ide.disks1.image]
1614 child=system.pc.south_bridge.ide.disks1.image.child
1620 [system.pc.south_bridge.ide.disks1.image.child]
1623 image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
1626 [system.pc.south_bridge.int_lines0]
1630 sink=system.pc.south_bridge.int_lines0.sink
1631 source=system.pc.south_bridge.pic1.output
1633 [system.pc.south_bridge.int_lines0.sink]
1635 device=system.pc.south_bridge.io_apic
1639 [system.pc.south_bridge.int_lines1]
1643 sink=system.pc.south_bridge.int_lines1.sink
1644 source=system.pc.south_bridge.pic2.output
1646 [system.pc.south_bridge.int_lines1.sink]
1648 device=system.pc.south_bridge.pic1
1652 [system.pc.south_bridge.int_lines2]
1656 sink=system.pc.south_bridge.int_lines2.sink
1657 source=system.pc.south_bridge.cmos.int_pin
1659 [system.pc.south_bridge.int_lines2.sink]
1661 device=system.pc.south_bridge.pic2
1665 [system.pc.south_bridge.int_lines3]
1669 sink=system.pc.south_bridge.int_lines3.sink
1670 source=system.pc.south_bridge.pit.int_pin
1672 [system.pc.south_bridge.int_lines3.sink]
1674 device=system.pc.south_bridge.pic1
1678 [system.pc.south_bridge.int_lines4]
1682 sink=system.pc.south_bridge.int_lines4.sink
1683 source=system.pc.south_bridge.pit.int_pin
1685 [system.pc.south_bridge.int_lines4.sink]
1687 device=system.pc.south_bridge.io_apic
1691 [system.pc.south_bridge.int_lines5]
1695 sink=system.pc.south_bridge.int_lines5.sink
1696 source=system.pc.south_bridge.keyboard.keyboard_int_pin
1698 [system.pc.south_bridge.int_lines5.sink]
1700 device=system.pc.south_bridge.io_apic
1704 [system.pc.south_bridge.int_lines6]
1708 sink=system.pc.south_bridge.int_lines6.sink
1709 source=system.pc.south_bridge.keyboard.mouse_int_pin
1711 [system.pc.south_bridge.int_lines6.sink]
1713 device=system.pc.south_bridge.io_apic
1717 [system.pc.south_bridge.io_apic]
1720 clk_domain=system.clk_domain
1722 external_int_pic=system.pc.south_bridge.pic1
1727 int_master=system.iobus.slave[2]
1728 pio=system.iobus.master[10]
1730 [system.pc.south_bridge.keyboard]
1732 children=keyboard_int_pin mouse_int_pin
1733 clk_domain=system.clk_domain
1734 command_port=9223372036854775908
1735 data_port=9223372036854775904
1737 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
1738 mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
1742 pio=system.iobus.master[5]
1744 [system.pc.south_bridge.keyboard.keyboard_int_pin]
1745 type=X86IntSourcePin
1748 [system.pc.south_bridge.keyboard.mouse_int_pin]
1749 type=X86IntSourcePin
1752 [system.pc.south_bridge.pic1]
1755 clk_domain=system.clk_domain
1758 output=system.pc.south_bridge.pic1.output
1759 pio_addr=9223372036854775840
1761 slave=system.pc.south_bridge.pic2
1763 pio=system.iobus.master[6]
1765 [system.pc.south_bridge.pic1.output]
1766 type=X86IntSourcePin
1769 [system.pc.south_bridge.pic2]
1772 clk_domain=system.clk_domain
1775 output=system.pc.south_bridge.pic2.output
1776 pio_addr=9223372036854775968
1780 pio=system.iobus.master[7]
1782 [system.pc.south_bridge.pic2.output]
1783 type=X86IntSourcePin
1786 [system.pc.south_bridge.pit]
1789 clk_domain=system.clk_domain
1791 int_pin=system.pc.south_bridge.pit.int_pin
1792 pio_addr=9223372036854775872
1795 pio=system.iobus.master[8]
1797 [system.pc.south_bridge.pit.int_pin]
1798 type=X86IntSourcePin
1801 [system.pc.south_bridge.speaker]
1803 clk_domain=system.clk_domain
1805 i8254=system.pc.south_bridge.pit
1806 pio_addr=9223372036854775905
1809 pio=system.iobus.master[9]
1814 addr_mapping=RoRaBaChCo
1818 clk_domain=system.clk_domain
1819 conf_table_reported=true
1821 device_rowbuffer_size=1024
1825 max_accesses_per_row=16
1826 mem_sched_policy=frfcfs
1827 min_writes_per_switch=16
1829 page_policy=open_adaptive
1833 static_backend_latency=10000
1834 static_frontend_latency=10000
1849 write_buffer_size=64
1850 write_high_thresh_perc=85
1851 write_low_thresh_perc=50
1852 port=system.membus.master[3]
1854 [system.smbios_table]
1855 type=X86SMBiosSMBiosTable
1860 structures=system.smbios_table.structures
1862 [system.smbios_table.structures]
1863 type=X86SMBiosBiosInformation
1864 characteristic_ext_bytes=
1866 emb_cont_firmware_major=0
1867 emb_cont_firmware_minor=0
1871 release_date=06/08/2008
1873 starting_addr_segment=0
1879 clk_domain=system.cpu_clk_domain
1883 use_default_range=false
1885 master=system.l2c.cpu_side
1886 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
1888 [system.voltage_domain]