2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.139775 # Number of seconds simulated
4 sim_ticks 5139775442500 # Number of ticks simulated
5 final_tick 5139775442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 241106 # Simulator instruction rate (inst/s)
8 host_op_rate 479260 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 5080243819 # Simulator tick rate (ticks/s)
10 host_mem_usage 990760 # Number of bytes of host memory used
11 host_seconds 1011.72 # Real time elapsed on the host
12 sim_insts 243931071 # Number of instructions simulated
13 sim_ops 484875903 # Number of ops (including micro ops) simulated
14 system.voltage_domain.voltage 1 # Voltage in Volts
15 system.clk_domain.clock 1000 # Clock period in ticks
16 system.physmem.bytes_read::pc.south_bridge.ide 2452480 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu0.inst 439552 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu0.data 5834944 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu1.inst 98048 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu1.data 1717440 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory
23 system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory
24 system.physmem.bytes_read::cpu2.inst 432064 # Number of bytes read from this memory
25 system.physmem.bytes_read::cpu2.data 2820032 # Number of bytes read from this memory
26 system.physmem.bytes_read::total 13796608 # Number of bytes read from this memory
27 system.physmem.bytes_inst_read::cpu0.inst 439552 # Number of instructions bytes read from this memory
28 system.physmem.bytes_inst_read::cpu1.inst 98048 # Number of instructions bytes read from this memory
29 system.physmem.bytes_inst_read::cpu2.inst 432064 # Number of instructions bytes read from this memory
30 system.physmem.bytes_inst_read::total 969664 # Number of instructions bytes read from this memory
31 system.physmem.bytes_written::writebacks 9118784 # Number of bytes written to this memory
32 system.physmem.bytes_written::total 9118784 # Number of bytes written to this memory
33 system.physmem.num_reads::pc.south_bridge.ide 38320 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu0.inst 6868 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu0.data 91171 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu1.inst 1532 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu1.data 26835 # Number of read requests responded to by this memory
39 system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory
40 system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory
41 system.physmem.num_reads::cpu2.inst 6751 # Number of read requests responded to by this memory
42 system.physmem.num_reads::cpu2.data 44063 # Number of read requests responded to by this memory
43 system.physmem.num_reads::total 215572 # Number of read requests responded to by this memory
44 system.physmem.num_writes::writebacks 142481 # Number of write requests responded to by this memory
45 system.physmem.num_writes::total 142481 # Number of write requests responded to by this memory
46 system.physmem.bw_read::pc.south_bridge.ide 477157 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::cpu0.inst 85520 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_read::cpu0.data 1135253 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu1.inst 19076 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::cpu1.data 334147 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_read::cpu2.dtb.walker 324 # Total read bandwidth from this memory (bytes/s)
53 system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
54 system.physmem.bw_read::cpu2.inst 84063 # Total read bandwidth from this memory (bytes/s)
55 system.physmem.bw_read::cpu2.data 548668 # Total read bandwidth from this memory (bytes/s)
56 system.physmem.bw_read::total 2684282 # Total read bandwidth from this memory (bytes/s)
57 system.physmem.bw_inst_read::cpu0.inst 85520 # Instruction read bandwidth from this memory (bytes/s)
58 system.physmem.bw_inst_read::cpu1.inst 19076 # Instruction read bandwidth from this memory (bytes/s)
59 system.physmem.bw_inst_read::cpu2.inst 84063 # Instruction read bandwidth from this memory (bytes/s)
60 system.physmem.bw_inst_read::total 188659 # Instruction read bandwidth from this memory (bytes/s)
61 system.physmem.bw_write::writebacks 1774160 # Write bandwidth from this memory (bytes/s)
62 system.physmem.bw_write::total 1774160 # Write bandwidth from this memory (bytes/s)
63 system.physmem.bw_total::writebacks 1774160 # Total bandwidth to/from this memory (bytes/s)
64 system.physmem.bw_total::pc.south_bridge.ide 477157 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
66 system.physmem.bw_total::cpu0.inst 85520 # Total bandwidth to/from this memory (bytes/s)
67 system.physmem.bw_total::cpu0.data 1135253 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::cpu1.inst 19076 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.bw_total::cpu1.data 334147 # Total bandwidth to/from this memory (bytes/s)
70 system.physmem.bw_total::cpu2.dtb.walker 324 # Total bandwidth to/from this memory (bytes/s)
71 system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
72 system.physmem.bw_total::cpu2.inst 84063 # Total bandwidth to/from this memory (bytes/s)
73 system.physmem.bw_total::cpu2.data 548668 # Total bandwidth to/from this memory (bytes/s)
74 system.physmem.bw_total::total 4458442 # Total bandwidth to/from this memory (bytes/s)
75 system.physmem.readReqs 98736 # Number of read requests accepted
76 system.physmem.writeReqs 74818 # Number of write requests accepted
77 system.physmem.readBursts 98736 # Number of DRAM read bursts, including those serviced by the write queue
78 system.physmem.writeBursts 74818 # Number of DRAM write bursts, including those merged in the write queue
79 system.physmem.bytesReadDRAM 6312704 # Total number of bytes read from DRAM
80 system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue
81 system.physmem.bytesWritten 4788352 # Total number of bytes written to DRAM
82 system.physmem.bytesReadSys 6319104 # Total read bytes from the system interface side
83 system.physmem.bytesWrittenSys 4788352 # Total written bytes from the system interface side
84 system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue
85 system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
86 system.physmem.neitherReadNorWriteReqs 734 # Number of requests that are neither read nor write
87 system.physmem.perBankRdBursts::0 6153 # Per bank write bursts
88 system.physmem.perBankRdBursts::1 6286 # Per bank write bursts
89 system.physmem.perBankRdBursts::2 6219 # Per bank write bursts
90 system.physmem.perBankRdBursts::3 6279 # Per bank write bursts
91 system.physmem.perBankRdBursts::4 6331 # Per bank write bursts
92 system.physmem.perBankRdBursts::5 6377 # Per bank write bursts
93 system.physmem.perBankRdBursts::6 5798 # Per bank write bursts
94 system.physmem.perBankRdBursts::7 6202 # Per bank write bursts
95 system.physmem.perBankRdBursts::8 5707 # Per bank write bursts
96 system.physmem.perBankRdBursts::9 6391 # Per bank write bursts
97 system.physmem.perBankRdBursts::10 5673 # Per bank write bursts
98 system.physmem.perBankRdBursts::11 6223 # Per bank write bursts
99 system.physmem.perBankRdBursts::12 6101 # Per bank write bursts
100 system.physmem.perBankRdBursts::13 6086 # Per bank write bursts
101 system.physmem.perBankRdBursts::14 6643 # Per bank write bursts
102 system.physmem.perBankRdBursts::15 6167 # Per bank write bursts
103 system.physmem.perBankWrBursts::0 4924 # Per bank write bursts
104 system.physmem.perBankWrBursts::1 4781 # Per bank write bursts
105 system.physmem.perBankWrBursts::2 4796 # Per bank write bursts
106 system.physmem.perBankWrBursts::3 4885 # Per bank write bursts
107 system.physmem.perBankWrBursts::4 4841 # Per bank write bursts
108 system.physmem.perBankWrBursts::5 4959 # Per bank write bursts
109 system.physmem.perBankWrBursts::6 4374 # Per bank write bursts
110 system.physmem.perBankWrBursts::7 4731 # Per bank write bursts
111 system.physmem.perBankWrBursts::8 4283 # Per bank write bursts
112 system.physmem.perBankWrBursts::9 4855 # Per bank write bursts
113 system.physmem.perBankWrBursts::10 4375 # Per bank write bursts
114 system.physmem.perBankWrBursts::11 4455 # Per bank write bursts
115 system.physmem.perBankWrBursts::12 4488 # Per bank write bursts
116 system.physmem.perBankWrBursts::13 4484 # Per bank write bursts
117 system.physmem.perBankWrBursts::14 5021 # Per bank write bursts
118 system.physmem.perBankWrBursts::15 4566 # Per bank write bursts
119 system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120 system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
121 system.physmem.totGap 5135962999500 # Total gap between requests
122 system.physmem.readPktSize::0 0 # Read request sizes (log2)
123 system.physmem.readPktSize::1 0 # Read request sizes (log2)
124 system.physmem.readPktSize::2 0 # Read request sizes (log2)
125 system.physmem.readPktSize::3 0 # Read request sizes (log2)
126 system.physmem.readPktSize::4 0 # Read request sizes (log2)
127 system.physmem.readPktSize::5 0 # Read request sizes (log2)
128 system.physmem.readPktSize::6 98736 # Read request sizes (log2)
129 system.physmem.writePktSize::0 0 # Write request sizes (log2)
130 system.physmem.writePktSize::1 0 # Write request sizes (log2)
131 system.physmem.writePktSize::2 0 # Write request sizes (log2)
132 system.physmem.writePktSize::3 0 # Write request sizes (log2)
133 system.physmem.writePktSize::4 0 # Write request sizes (log2)
134 system.physmem.writePktSize::5 0 # Write request sizes (log2)
135 system.physmem.writePktSize::6 74818 # Write request sizes (log2)
136 system.physmem.rdQLenPdf::0 76556 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::1 4428 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::2 2029 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::3 1295 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::4 1291 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::5 2072 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::8 1521 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::9 1005 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::10 865 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::11 756 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::12 662 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::13 578 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::14 432 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::15 398 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::16 380 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::18 340 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::19 203 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
159 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
160 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
168 system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::3 61 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::4 58 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::15 1029 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::16 1079 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::17 1337 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::18 3068 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::19 3176 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::20 3199 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::21 3215 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::22 3295 # What write queue length does an incoming req see
191 system.physmem.wrQLenPdf::23 3317 # What write queue length does an incoming req see
192 system.physmem.wrQLenPdf::24 3341 # What write queue length does an incoming req see
193 system.physmem.wrQLenPdf::25 4472 # What write queue length does an incoming req see
194 system.physmem.wrQLenPdf::26 3777 # What write queue length does an incoming req see
195 system.physmem.wrQLenPdf::27 3885 # What write queue length does an incoming req see
196 system.physmem.wrQLenPdf::28 4534 # What write queue length does an incoming req see
197 system.physmem.wrQLenPdf::29 4146 # What write queue length does an incoming req see
198 system.physmem.wrQLenPdf::30 4247 # What write queue length does an incoming req see
199 system.physmem.wrQLenPdf::31 4212 # What write queue length does an incoming req see
200 system.physmem.wrQLenPdf::32 4224 # What write queue length does an incoming req see
201 system.physmem.wrQLenPdf::33 1287 # What write queue length does an incoming req see
202 system.physmem.wrQLenPdf::34 1217 # What write queue length does an incoming req see
203 system.physmem.wrQLenPdf::35 1095 # What write queue length does an incoming req see
204 system.physmem.wrQLenPdf::36 1013 # What write queue length does an incoming req see
205 system.physmem.wrQLenPdf::37 1004 # What write queue length does an incoming req see
206 system.physmem.wrQLenPdf::38 996 # What write queue length does an incoming req see
207 system.physmem.wrQLenPdf::39 896 # What write queue length does an incoming req see
208 system.physmem.wrQLenPdf::40 877 # What write queue length does an incoming req see
209 system.physmem.wrQLenPdf::41 856 # What write queue length does an incoming req see
210 system.physmem.wrQLenPdf::42 814 # What write queue length does an incoming req see
211 system.physmem.wrQLenPdf::43 759 # What write queue length does an incoming req see
212 system.physmem.wrQLenPdf::44 656 # What write queue length does an incoming req see
213 system.physmem.wrQLenPdf::45 558 # What write queue length does an incoming req see
214 system.physmem.wrQLenPdf::46 491 # What write queue length does an incoming req see
215 system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see
216 system.physmem.wrQLenPdf::48 353 # What write queue length does an incoming req see
217 system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see
218 system.physmem.wrQLenPdf::50 223 # What write queue length does an incoming req see
219 system.physmem.wrQLenPdf::51 163 # What write queue length does an incoming req see
220 system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see
221 system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see
222 system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see
223 system.physmem.wrQLenPdf::55 43 # What write queue length does an incoming req see
224 system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
225 system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see
226 system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see
227 system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see
228 system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see
229 system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
230 system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
231 system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
232 system.physmem.bytesPerActivate::samples 22863 # Bytes accessed per row activation
233 system.physmem.bytesPerActivate::mean 371.369637 # Bytes accessed per row activation
234 system.physmem.bytesPerActivate::gmean 216.870030 # Bytes accessed per row activation
235 system.physmem.bytesPerActivate::stdev 366.414967 # Bytes accessed per row activation
236 system.physmem.bytesPerActivate::0-127 7224 31.60% 31.60% # Bytes accessed per row activation
237 system.physmem.bytesPerActivate::128-255 5292 23.15% 54.74% # Bytes accessed per row activation
238 system.physmem.bytesPerActivate::256-383 2324 10.16% 64.91% # Bytes accessed per row activation
239 system.physmem.bytesPerActivate::384-511 1423 6.22% 71.13% # Bytes accessed per row activation
240 system.physmem.bytesPerActivate::512-639 882 3.86% 74.99% # Bytes accessed per row activation
241 system.physmem.bytesPerActivate::640-767 607 2.65% 77.65% # Bytes accessed per row activation
242 system.physmem.bytesPerActivate::768-895 442 1.93% 79.58% # Bytes accessed per row activation
243 system.physmem.bytesPerActivate::896-1023 389 1.70% 81.28% # Bytes accessed per row activation
244 system.physmem.bytesPerActivate::1024-1151 4280 18.72% 100.00% # Bytes accessed per row activation
245 system.physmem.bytesPerActivate::total 22863 # Bytes accessed per row activation
246 system.physmem.rdPerTurnAround::samples 4109 # Reads before turning the bus around for writes
247 system.physmem.rdPerTurnAround::mean 24.004867 # Reads before turning the bus around for writes
248 system.physmem.rdPerTurnAround::stdev 117.614100 # Reads before turning the bus around for writes
249 system.physmem.rdPerTurnAround::0-255 4100 99.78% 99.78% # Reads before turning the bus around for writes
250 system.physmem.rdPerTurnAround::256-511 6 0.15% 99.93% # Reads before turning the bus around for writes
251 system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes
252 system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes
253 system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes
254 system.physmem.rdPerTurnAround::total 4109 # Reads before turning the bus around for writes
255 system.physmem.wrPerTurnAround::samples 4109 # Writes before turning the bus around for reads
256 system.physmem.wrPerTurnAround::mean 18.208323 # Writes before turning the bus around for reads
257 system.physmem.wrPerTurnAround::gmean 17.187975 # Writes before turning the bus around for reads
258 system.physmem.wrPerTurnAround::stdev 6.583219 # Writes before turning the bus around for reads
259 system.physmem.wrPerTurnAround::0-1 44 1.07% 1.07% # Writes before turning the bus around for reads
260 system.physmem.wrPerTurnAround::2-3 6 0.15% 1.22% # Writes before turning the bus around for reads
261 system.physmem.wrPerTurnAround::4-5 4 0.10% 1.31% # Writes before turning the bus around for reads
262 system.physmem.wrPerTurnAround::6-7 4 0.10% 1.41% # Writes before turning the bus around for reads
263 system.physmem.wrPerTurnAround::8-9 2 0.05% 1.46% # Writes before turning the bus around for reads
264 system.physmem.wrPerTurnAround::14-15 4 0.10% 1.56% # Writes before turning the bus around for reads
265 system.physmem.wrPerTurnAround::16-17 2755 67.05% 68.61% # Writes before turning the bus around for reads
266 system.physmem.wrPerTurnAround::18-19 853 20.76% 89.36% # Writes before turning the bus around for reads
267 system.physmem.wrPerTurnAround::20-21 55 1.34% 90.70% # Writes before turning the bus around for reads
268 system.physmem.wrPerTurnAround::22-23 41 1.00% 91.70% # Writes before turning the bus around for reads
269 system.physmem.wrPerTurnAround::24-25 36 0.88% 92.58% # Writes before turning the bus around for reads
270 system.physmem.wrPerTurnAround::26-27 45 1.10% 93.67% # Writes before turning the bus around for reads
271 system.physmem.wrPerTurnAround::28-29 25 0.61% 94.28% # Writes before turning the bus around for reads
272 system.physmem.wrPerTurnAround::30-31 36 0.88% 95.16% # Writes before turning the bus around for reads
273 system.physmem.wrPerTurnAround::32-33 20 0.49% 95.64% # Writes before turning the bus around for reads
274 system.physmem.wrPerTurnAround::34-35 26 0.63% 96.28% # Writes before turning the bus around for reads
275 system.physmem.wrPerTurnAround::36-37 28 0.68% 96.96% # Writes before turning the bus around for reads
276 system.physmem.wrPerTurnAround::38-39 10 0.24% 97.20% # Writes before turning the bus around for reads
277 system.physmem.wrPerTurnAround::40-41 24 0.58% 97.79% # Writes before turning the bus around for reads
278 system.physmem.wrPerTurnAround::42-43 13 0.32% 98.10% # Writes before turning the bus around for reads
279 system.physmem.wrPerTurnAround::44-45 21 0.51% 98.61% # Writes before turning the bus around for reads
280 system.physmem.wrPerTurnAround::46-47 18 0.44% 99.05% # Writes before turning the bus around for reads
281 system.physmem.wrPerTurnAround::48-49 6 0.15% 99.20% # Writes before turning the bus around for reads
282 system.physmem.wrPerTurnAround::50-51 4 0.10% 99.29% # Writes before turning the bus around for reads
283 system.physmem.wrPerTurnAround::52-53 10 0.24% 99.54% # Writes before turning the bus around for reads
284 system.physmem.wrPerTurnAround::56-57 1 0.02% 99.56% # Writes before turning the bus around for reads
285 system.physmem.wrPerTurnAround::58-59 2 0.05% 99.61% # Writes before turning the bus around for reads
286 system.physmem.wrPerTurnAround::60-61 1 0.02% 99.63% # Writes before turning the bus around for reads
287 system.physmem.wrPerTurnAround::62-63 4 0.10% 99.73% # Writes before turning the bus around for reads
288 system.physmem.wrPerTurnAround::64-65 9 0.22% 99.95% # Writes before turning the bus around for reads
289 system.physmem.wrPerTurnAround::68-69 1 0.02% 99.98% # Writes before turning the bus around for reads
290 system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads
291 system.physmem.wrPerTurnAround::total 4109 # Writes before turning the bus around for reads
292 system.physmem.totQLat 2553947750 # Total ticks spent queuing
293 system.physmem.totMemAccLat 4444375250 # Total ticks spent from burst creation until serviced by the DRAM
294 system.physmem.totBusLat 493180000 # Total ticks spent in databus transfers
295 system.physmem.totBankLat 1397247500 # Total ticks spent accessing banks
296 system.physmem.avgQLat 25892.65 # Average queueing delay per DRAM burst
297 system.physmem.avgBankLat 14165.70 # Average bank access latency per DRAM burst
298 system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
299 system.physmem.avgMemAccLat 45058.35 # Average memory access latency per DRAM burst
300 system.physmem.avgRdBW 1.23 # Average DRAM read bandwidth in MiByte/s
301 system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s
302 system.physmem.avgRdBWSys 1.23 # Average system read bandwidth in MiByte/s
303 system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s
304 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
305 system.physmem.busUtil 0.02 # Data bus utilization in percentage
306 system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
307 system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
308 system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
309 system.physmem.avgWrQLen 10.06 # Average write queue length when enqueuing
310 system.physmem.readRowHits 80976 # Number of row buffer hits during reads
311 system.physmem.writeRowHits 55952 # Number of row buffer hits during writes
312 system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads
313 system.physmem.writeRowHitRate 74.78 # Row buffer hit rate for writes
314 system.physmem.avgGap 29592881.75 # Average gap between requests
315 system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
316 system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state
317 system.membus.throughput 6444852 # Throughput (bytes/s)
318 system.membus.trans_dist::ReadReq 422305 # Transaction distribution
319 system.membus.trans_dist::ReadResp 422303 # Transaction distribution
320 system.membus.trans_dist::WriteReq 6370 # Transaction distribution
321 system.membus.trans_dist::WriteResp 6370 # Transaction distribution
322 system.membus.trans_dist::Writeback 74818 # Transaction distribution
323 system.membus.trans_dist::UpgradeReq 747 # Transaction distribution
324 system.membus.trans_dist::UpgradeResp 747 # Transaction distribution
325 system.membus.trans_dist::ReadExReq 78043 # Transaction distribution
326 system.membus.trans_dist::ReadExResp 78043 # Transaction distribution
327 system.membus.trans_dist::MessageReq 885 # Transaction distribution
328 system.membus.trans_dist::MessageResp 885 # Transaction distribution
329 system.membus.trans_dist::BadAddressError 2 # Transaction distribution
330 system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1770 # Packet count per connected master and slave (bytes)
331 system.membus.pkt_count_system.apicbridge.master::total 1770 # Packet count per connected master and slave (bytes)
332 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 309432 # Packet count per connected master and slave (bytes)
333 system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497538 # Packet count per connected master and slave (bytes)
334 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 212160 # Packet count per connected master and slave (bytes)
335 system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
336 system.membus.pkt_count_system.l2c.mem_side::total 1019134 # Packet count per connected master and slave (bytes)
337 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 66106 # Packet count per connected master and slave (bytes)
338 system.membus.pkt_count_system.iocache.mem_side::total 66106 # Packet count per connected master and slave (bytes)
339 system.membus.pkt_count::total 1087010 # Packet count per connected master and slave (bytes)
340 system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3540 # Cumulative packet size per connected master and slave (bytes)
341 system.membus.tot_pkt_size_system.apicbridge.master::total 3540 # Cumulative packet size per connected master and slave (bytes)
342 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158682 # Cumulative packet size per connected master and slave (bytes)
343 system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995073 # Cumulative packet size per connected master and slave (bytes)
344 system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8391680 # Cumulative packet size per connected master and slave (bytes)
345 system.membus.tot_pkt_size_system.l2c.mem_side::total 9545435 # Cumulative packet size per connected master and slave (bytes)
346 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2715776 # Cumulative packet size per connected master and slave (bytes)
347 system.membus.tot_pkt_size_system.iocache.mem_side::total 2715776 # Cumulative packet size per connected master and slave (bytes)
348 system.membus.tot_pkt_size::total 12264751 # Cumulative packet size per connected master and slave (bytes)
349 system.membus.data_through_bus 32837413 # Total data (bytes)
350 system.membus.snoop_data_through_bus 287680 # Total snoop data (bytes)
351 system.membus.reqLayer0.occupancy 162853500 # Layer occupancy (ticks)
352 system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
353 system.membus.reqLayer1.occupancy 315156500 # Layer occupancy (ticks)
354 system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
355 system.membus.reqLayer2.occupancy 1770000 # Layer occupancy (ticks)
356 system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
357 system.membus.reqLayer3.occupancy 821391499 # Layer occupancy (ticks)
358 system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
359 system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
360 system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
361 system.membus.respLayer0.occupancy 885000 # Layer occupancy (ticks)
362 system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
363 system.membus.respLayer2.occupancy 1625485201 # Layer occupancy (ticks)
364 system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
365 system.membus.respLayer4.occupancy 213559749 # Layer occupancy (ticks)
366 system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
367 system.cpu_clk_domain.clock 500 # Clock period in ticks
368 system.l2c.tags.replacements 104632 # number of replacements
369 system.l2c.tags.tagsinuse 64756.494280 # Cycle average of tags in use
370 system.l2c.tags.total_refs 3664896 # Total number of references to valid blocks.
371 system.l2c.tags.sampled_refs 168700 # Sample count of references to valid blocks.
372 system.l2c.tags.avg_refs 21.724339 # Average number of references to valid blocks.
373 system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
374 system.l2c.tags.occ_blocks::writebacks 51511.220399 # Average occupied blocks per requestor
375 system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131167 # Average occupied blocks per requestor
376 system.l2c.tags.occ_blocks::cpu0.inst 1228.361726 # Average occupied blocks per requestor
377 system.l2c.tags.occ_blocks::cpu0.data 4265.224240 # Average occupied blocks per requestor
378 system.l2c.tags.occ_blocks::cpu1.inst 282.161159 # Average occupied blocks per requestor
379 system.l2c.tags.occ_blocks::cpu1.data 1465.784470 # Average occupied blocks per requestor
380 system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.322385 # Average occupied blocks per requestor
381 system.l2c.tags.occ_blocks::cpu2.itb.walker 0.042344 # Average occupied blocks per requestor
382 system.l2c.tags.occ_blocks::cpu2.inst 1365.490726 # Average occupied blocks per requestor
383 system.l2c.tags.occ_blocks::cpu2.data 4627.755664 # Average occupied blocks per requestor
384 system.l2c.tags.occ_percent::writebacks 0.785999 # Average percentage of cache occupancy
385 system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
386 system.l2c.tags.occ_percent::cpu0.inst 0.018743 # Average percentage of cache occupancy
387 system.l2c.tags.occ_percent::cpu0.data 0.065082 # Average percentage of cache occupancy
388 system.l2c.tags.occ_percent::cpu1.inst 0.004305 # Average percentage of cache occupancy
389 system.l2c.tags.occ_percent::cpu1.data 0.022366 # Average percentage of cache occupancy
390 system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000158 # Average percentage of cache occupancy
391 system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy
392 system.l2c.tags.occ_percent::cpu2.inst 0.020836 # Average percentage of cache occupancy
393 system.l2c.tags.occ_percent::cpu2.data 0.070614 # Average percentage of cache occupancy
394 system.l2c.tags.occ_percent::total 0.988106 # Average percentage of cache occupancy
395 system.l2c.tags.occ_task_id_blocks::1024 64068 # Occupied blocks per task id
396 system.l2c.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
397 system.l2c.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
398 system.l2c.tags.age_task_id_blocks_1024::2 2732 # Occupied blocks per task id
399 system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id
400 system.l2c.tags.age_task_id_blocks_1024::4 53790 # Occupied blocks per task id
401 system.l2c.tags.occ_task_id_percent::1024 0.977600 # Percentage of cache occupancy per task id
402 system.l2c.tags.tag_accesses 33688290 # Number of tag accesses
403 system.l2c.tags.data_accesses 33688290 # Number of data accesses
404 system.l2c.ReadReq_hits::cpu0.dtb.walker 22061 # number of ReadReq hits
405 system.l2c.ReadReq_hits::cpu0.itb.walker 11615 # number of ReadReq hits
406 system.l2c.ReadReq_hits::cpu0.inst 344470 # number of ReadReq hits
407 system.l2c.ReadReq_hits::cpu0.data 519863 # number of ReadReq hits
408 system.l2c.ReadReq_hits::cpu1.dtb.walker 10165 # number of ReadReq hits
409 system.l2c.ReadReq_hits::cpu1.itb.walker 5243 # number of ReadReq hits
410 system.l2c.ReadReq_hits::cpu1.inst 139799 # number of ReadReq hits
411 system.l2c.ReadReq_hits::cpu1.data 221175 # number of ReadReq hits
412 system.l2c.ReadReq_hits::cpu2.dtb.walker 54188 # number of ReadReq hits
413 system.l2c.ReadReq_hits::cpu2.itb.walker 10719 # number of ReadReq hits
414 system.l2c.ReadReq_hits::cpu2.inst 354261 # number of ReadReq hits
415 system.l2c.ReadReq_hits::cpu2.data 566062 # number of ReadReq hits
416 system.l2c.ReadReq_hits::total 2259621 # number of ReadReq hits
417 system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
418 system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
419 system.l2c.Writeback_hits::writebacks 1545523 # number of Writeback hits
420 system.l2c.Writeback_hits::total 1545523 # number of Writeback hits
421 system.l2c.UpgradeReq_hits::cpu0.data 137 # number of UpgradeReq hits
422 system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits
423 system.l2c.UpgradeReq_hits::cpu2.data 93 # number of UpgradeReq hits
424 system.l2c.UpgradeReq_hits::total 276 # number of UpgradeReq hits
425 system.l2c.ReadExReq_hits::cpu0.data 73996 # number of ReadExReq hits
426 system.l2c.ReadExReq_hits::cpu1.data 34699 # number of ReadExReq hits
427 system.l2c.ReadExReq_hits::cpu2.data 57996 # number of ReadExReq hits
428 system.l2c.ReadExReq_hits::total 166691 # number of ReadExReq hits
429 system.l2c.demand_hits::cpu0.dtb.walker 22061 # number of demand (read+write) hits
430 system.l2c.demand_hits::cpu0.itb.walker 11617 # number of demand (read+write) hits
431 system.l2c.demand_hits::cpu0.inst 344470 # number of demand (read+write) hits
432 system.l2c.demand_hits::cpu0.data 593859 # number of demand (read+write) hits
433 system.l2c.demand_hits::cpu1.dtb.walker 10165 # number of demand (read+write) hits
434 system.l2c.demand_hits::cpu1.itb.walker 5243 # number of demand (read+write) hits
435 system.l2c.demand_hits::cpu1.inst 139799 # number of demand (read+write) hits
436 system.l2c.demand_hits::cpu1.data 255874 # number of demand (read+write) hits
437 system.l2c.demand_hits::cpu2.dtb.walker 54188 # number of demand (read+write) hits
438 system.l2c.demand_hits::cpu2.itb.walker 10719 # number of demand (read+write) hits
439 system.l2c.demand_hits::cpu2.inst 354261 # number of demand (read+write) hits
440 system.l2c.demand_hits::cpu2.data 624058 # number of demand (read+write) hits
441 system.l2c.demand_hits::total 2426314 # number of demand (read+write) hits
442 system.l2c.overall_hits::cpu0.dtb.walker 22061 # number of overall hits
443 system.l2c.overall_hits::cpu0.itb.walker 11617 # number of overall hits
444 system.l2c.overall_hits::cpu0.inst 344470 # number of overall hits
445 system.l2c.overall_hits::cpu0.data 593859 # number of overall hits
446 system.l2c.overall_hits::cpu1.dtb.walker 10165 # number of overall hits
447 system.l2c.overall_hits::cpu1.itb.walker 5243 # number of overall hits
448 system.l2c.overall_hits::cpu1.inst 139799 # number of overall hits
449 system.l2c.overall_hits::cpu1.data 255874 # number of overall hits
450 system.l2c.overall_hits::cpu2.dtb.walker 54188 # number of overall hits
451 system.l2c.overall_hits::cpu2.itb.walker 10719 # number of overall hits
452 system.l2c.overall_hits::cpu2.inst 354261 # number of overall hits
453 system.l2c.overall_hits::cpu2.data 624058 # number of overall hits
454 system.l2c.overall_hits::total 2426314 # number of overall hits
455 system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
456 system.l2c.ReadReq_misses::cpu0.inst 6868 # number of ReadReq misses
457 system.l2c.ReadReq_misses::cpu0.data 16704 # number of ReadReq misses
458 system.l2c.ReadReq_misses::cpu1.inst 1533 # number of ReadReq misses
459 system.l2c.ReadReq_misses::cpu1.data 3888 # number of ReadReq misses
460 system.l2c.ReadReq_misses::cpu2.dtb.walker 26 # number of ReadReq misses
461 system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses
462 system.l2c.ReadReq_misses::cpu2.inst 6752 # number of ReadReq misses
463 system.l2c.ReadReq_misses::cpu2.data 12246 # number of ReadReq misses
464 system.l2c.ReadReq_misses::total 48023 # number of ReadReq misses
465 system.l2c.UpgradeReq_misses::cpu0.data 754 # number of UpgradeReq misses
466 system.l2c.UpgradeReq_misses::cpu1.data 206 # number of UpgradeReq misses
467 system.l2c.UpgradeReq_misses::cpu2.data 371 # number of UpgradeReq misses
468 system.l2c.UpgradeReq_misses::total 1331 # number of UpgradeReq misses
469 system.l2c.ReadExReq_misses::cpu0.data 74862 # number of ReadExReq misses
470 system.l2c.ReadExReq_misses::cpu1.data 23137 # number of ReadExReq misses
471 system.l2c.ReadExReq_misses::cpu2.data 32148 # number of ReadExReq misses
472 system.l2c.ReadExReq_misses::total 130147 # number of ReadExReq misses
473 system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
474 system.l2c.demand_misses::cpu0.inst 6868 # number of demand (read+write) misses
475 system.l2c.demand_misses::cpu0.data 91566 # number of demand (read+write) misses
476 system.l2c.demand_misses::cpu1.inst 1533 # number of demand (read+write) misses
477 system.l2c.demand_misses::cpu1.data 27025 # number of demand (read+write) misses
478 system.l2c.demand_misses::cpu2.dtb.walker 26 # number of demand (read+write) misses
479 system.l2c.demand_misses::cpu2.itb.walker 2 # number of demand (read+write) misses
480 system.l2c.demand_misses::cpu2.inst 6752 # number of demand (read+write) misses
481 system.l2c.demand_misses::cpu2.data 44394 # number of demand (read+write) misses
482 system.l2c.demand_misses::total 178170 # number of demand (read+write) misses
483 system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
484 system.l2c.overall_misses::cpu0.inst 6868 # number of overall misses
485 system.l2c.overall_misses::cpu0.data 91566 # number of overall misses
486 system.l2c.overall_misses::cpu1.inst 1533 # number of overall misses
487 system.l2c.overall_misses::cpu1.data 27025 # number of overall misses
488 system.l2c.overall_misses::cpu2.dtb.walker 26 # number of overall misses
489 system.l2c.overall_misses::cpu2.itb.walker 2 # number of overall misses
490 system.l2c.overall_misses::cpu2.inst 6752 # number of overall misses
491 system.l2c.overall_misses::cpu2.data 44394 # number of overall misses
492 system.l2c.overall_misses::total 178170 # number of overall misses
493 system.l2c.ReadReq_miss_latency::cpu1.inst 112485250 # number of ReadReq miss cycles
494 system.l2c.ReadReq_miss_latency::cpu1.data 293047996 # number of ReadReq miss cycles
495 system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2104000 # number of ReadReq miss cycles
496 system.l2c.ReadReq_miss_latency::cpu2.itb.walker 149000 # number of ReadReq miss cycles
497 system.l2c.ReadReq_miss_latency::cpu2.inst 524939486 # number of ReadReq miss cycles
498 system.l2c.ReadReq_miss_latency::cpu2.data 946518491 # number of ReadReq miss cycles
499 system.l2c.ReadReq_miss_latency::total 1879244223 # number of ReadReq miss cycles
500 system.l2c.UpgradeReq_miss_latency::cpu1.data 2976906 # number of UpgradeReq miss cycles
501 system.l2c.UpgradeReq_miss_latency::cpu2.data 4826300 # number of UpgradeReq miss cycles
502 system.l2c.UpgradeReq_miss_latency::total 7803206 # number of UpgradeReq miss cycles
503 system.l2c.ReadExReq_miss_latency::cpu1.data 1584451415 # number of ReadExReq miss cycles
504 system.l2c.ReadExReq_miss_latency::cpu2.data 2283457099 # number of ReadExReq miss cycles
505 system.l2c.ReadExReq_miss_latency::total 3867908514 # number of ReadExReq miss cycles
506 system.l2c.demand_miss_latency::cpu1.inst 112485250 # number of demand (read+write) miss cycles
507 system.l2c.demand_miss_latency::cpu1.data 1877499411 # number of demand (read+write) miss cycles
508 system.l2c.demand_miss_latency::cpu2.dtb.walker 2104000 # number of demand (read+write) miss cycles
509 system.l2c.demand_miss_latency::cpu2.itb.walker 149000 # number of demand (read+write) miss cycles
510 system.l2c.demand_miss_latency::cpu2.inst 524939486 # number of demand (read+write) miss cycles
511 system.l2c.demand_miss_latency::cpu2.data 3229975590 # number of demand (read+write) miss cycles
512 system.l2c.demand_miss_latency::total 5747152737 # number of demand (read+write) miss cycles
513 system.l2c.overall_miss_latency::cpu1.inst 112485250 # number of overall miss cycles
514 system.l2c.overall_miss_latency::cpu1.data 1877499411 # number of overall miss cycles
515 system.l2c.overall_miss_latency::cpu2.dtb.walker 2104000 # number of overall miss cycles
516 system.l2c.overall_miss_latency::cpu2.itb.walker 149000 # number of overall miss cycles
517 system.l2c.overall_miss_latency::cpu2.inst 524939486 # number of overall miss cycles
518 system.l2c.overall_miss_latency::cpu2.data 3229975590 # number of overall miss cycles
519 system.l2c.overall_miss_latency::total 5747152737 # number of overall miss cycles
520 system.l2c.ReadReq_accesses::cpu0.dtb.walker 22061 # number of ReadReq accesses(hits+misses)
521 system.l2c.ReadReq_accesses::cpu0.itb.walker 11619 # number of ReadReq accesses(hits+misses)
522 system.l2c.ReadReq_accesses::cpu0.inst 351338 # number of ReadReq accesses(hits+misses)
523 system.l2c.ReadReq_accesses::cpu0.data 536567 # number of ReadReq accesses(hits+misses)
524 system.l2c.ReadReq_accesses::cpu1.dtb.walker 10165 # number of ReadReq accesses(hits+misses)
525 system.l2c.ReadReq_accesses::cpu1.itb.walker 5243 # number of ReadReq accesses(hits+misses)
526 system.l2c.ReadReq_accesses::cpu1.inst 141332 # number of ReadReq accesses(hits+misses)
527 system.l2c.ReadReq_accesses::cpu1.data 225063 # number of ReadReq accesses(hits+misses)
528 system.l2c.ReadReq_accesses::cpu2.dtb.walker 54214 # number of ReadReq accesses(hits+misses)
529 system.l2c.ReadReq_accesses::cpu2.itb.walker 10721 # number of ReadReq accesses(hits+misses)
530 system.l2c.ReadReq_accesses::cpu2.inst 361013 # number of ReadReq accesses(hits+misses)
531 system.l2c.ReadReq_accesses::cpu2.data 578308 # number of ReadReq accesses(hits+misses)
532 system.l2c.ReadReq_accesses::total 2307644 # number of ReadReq accesses(hits+misses)
533 system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
534 system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
535 system.l2c.Writeback_accesses::writebacks 1545523 # number of Writeback accesses(hits+misses)
536 system.l2c.Writeback_accesses::total 1545523 # number of Writeback accesses(hits+misses)
537 system.l2c.UpgradeReq_accesses::cpu0.data 891 # number of UpgradeReq accesses(hits+misses)
538 system.l2c.UpgradeReq_accesses::cpu1.data 252 # number of UpgradeReq accesses(hits+misses)
539 system.l2c.UpgradeReq_accesses::cpu2.data 464 # number of UpgradeReq accesses(hits+misses)
540 system.l2c.UpgradeReq_accesses::total 1607 # number of UpgradeReq accesses(hits+misses)
541 system.l2c.ReadExReq_accesses::cpu0.data 148858 # number of ReadExReq accesses(hits+misses)
542 system.l2c.ReadExReq_accesses::cpu1.data 57836 # number of ReadExReq accesses(hits+misses)
543 system.l2c.ReadExReq_accesses::cpu2.data 90144 # number of ReadExReq accesses(hits+misses)
544 system.l2c.ReadExReq_accesses::total 296838 # number of ReadExReq accesses(hits+misses)
545 system.l2c.demand_accesses::cpu0.dtb.walker 22061 # number of demand (read+write) accesses
546 system.l2c.demand_accesses::cpu0.itb.walker 11621 # number of demand (read+write) accesses
547 system.l2c.demand_accesses::cpu0.inst 351338 # number of demand (read+write) accesses
548 system.l2c.demand_accesses::cpu0.data 685425 # number of demand (read+write) accesses
549 system.l2c.demand_accesses::cpu1.dtb.walker 10165 # number of demand (read+write) accesses
550 system.l2c.demand_accesses::cpu1.itb.walker 5243 # number of demand (read+write) accesses
551 system.l2c.demand_accesses::cpu1.inst 141332 # number of demand (read+write) accesses
552 system.l2c.demand_accesses::cpu1.data 282899 # number of demand (read+write) accesses
553 system.l2c.demand_accesses::cpu2.dtb.walker 54214 # number of demand (read+write) accesses
554 system.l2c.demand_accesses::cpu2.itb.walker 10721 # number of demand (read+write) accesses
555 system.l2c.demand_accesses::cpu2.inst 361013 # number of demand (read+write) accesses
556 system.l2c.demand_accesses::cpu2.data 668452 # number of demand (read+write) accesses
557 system.l2c.demand_accesses::total 2604484 # number of demand (read+write) accesses
558 system.l2c.overall_accesses::cpu0.dtb.walker 22061 # number of overall (read+write) accesses
559 system.l2c.overall_accesses::cpu0.itb.walker 11621 # number of overall (read+write) accesses
560 system.l2c.overall_accesses::cpu0.inst 351338 # number of overall (read+write) accesses
561 system.l2c.overall_accesses::cpu0.data 685425 # number of overall (read+write) accesses
562 system.l2c.overall_accesses::cpu1.dtb.walker 10165 # number of overall (read+write) accesses
563 system.l2c.overall_accesses::cpu1.itb.walker 5243 # number of overall (read+write) accesses
564 system.l2c.overall_accesses::cpu1.inst 141332 # number of overall (read+write) accesses
565 system.l2c.overall_accesses::cpu1.data 282899 # number of overall (read+write) accesses
566 system.l2c.overall_accesses::cpu2.dtb.walker 54214 # number of overall (read+write) accesses
567 system.l2c.overall_accesses::cpu2.itb.walker 10721 # number of overall (read+write) accesses
568 system.l2c.overall_accesses::cpu2.inst 361013 # number of overall (read+write) accesses
569 system.l2c.overall_accesses::cpu2.data 668452 # number of overall (read+write) accesses
570 system.l2c.overall_accesses::total 2604484 # number of overall (read+write) accesses
571 system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000344 # miss rate for ReadReq accesses
572 system.l2c.ReadReq_miss_rate::cpu0.inst 0.019548 # miss rate for ReadReq accesses
573 system.l2c.ReadReq_miss_rate::cpu0.data 0.031131 # miss rate for ReadReq accesses
574 system.l2c.ReadReq_miss_rate::cpu1.inst 0.010847 # miss rate for ReadReq accesses
575 system.l2c.ReadReq_miss_rate::cpu1.data 0.017275 # miss rate for ReadReq accesses
576 system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000480 # miss rate for ReadReq accesses
577 system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000187 # miss rate for ReadReq accesses
578 system.l2c.ReadReq_miss_rate::cpu2.inst 0.018703 # miss rate for ReadReq accesses
579 system.l2c.ReadReq_miss_rate::cpu2.data 0.021176 # miss rate for ReadReq accesses
580 system.l2c.ReadReq_miss_rate::total 0.020810 # miss rate for ReadReq accesses
581 system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846240 # miss rate for UpgradeReq accesses
582 system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817460 # miss rate for UpgradeReq accesses
583 system.l2c.UpgradeReq_miss_rate::cpu2.data 0.799569 # miss rate for UpgradeReq accesses
584 system.l2c.UpgradeReq_miss_rate::total 0.828251 # miss rate for UpgradeReq accesses
585 system.l2c.ReadExReq_miss_rate::cpu0.data 0.502909 # miss rate for ReadExReq accesses
586 system.l2c.ReadExReq_miss_rate::cpu1.data 0.400045 # miss rate for ReadExReq accesses
587 system.l2c.ReadExReq_miss_rate::cpu2.data 0.356629 # miss rate for ReadExReq accesses
588 system.l2c.ReadExReq_miss_rate::total 0.438445 # miss rate for ReadExReq accesses
589 system.l2c.demand_miss_rate::cpu0.itb.walker 0.000344 # miss rate for demand accesses
590 system.l2c.demand_miss_rate::cpu0.inst 0.019548 # miss rate for demand accesses
591 system.l2c.demand_miss_rate::cpu0.data 0.133590 # miss rate for demand accesses
592 system.l2c.demand_miss_rate::cpu1.inst 0.010847 # miss rate for demand accesses
593 system.l2c.demand_miss_rate::cpu1.data 0.095529 # miss rate for demand accesses
594 system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000480 # miss rate for demand accesses
595 system.l2c.demand_miss_rate::cpu2.itb.walker 0.000187 # miss rate for demand accesses
596 system.l2c.demand_miss_rate::cpu2.inst 0.018703 # miss rate for demand accesses
597 system.l2c.demand_miss_rate::cpu2.data 0.066413 # miss rate for demand accesses
598 system.l2c.demand_miss_rate::total 0.068409 # miss rate for demand accesses
599 system.l2c.overall_miss_rate::cpu0.itb.walker 0.000344 # miss rate for overall accesses
600 system.l2c.overall_miss_rate::cpu0.inst 0.019548 # miss rate for overall accesses
601 system.l2c.overall_miss_rate::cpu0.data 0.133590 # miss rate for overall accesses
602 system.l2c.overall_miss_rate::cpu1.inst 0.010847 # miss rate for overall accesses
603 system.l2c.overall_miss_rate::cpu1.data 0.095529 # miss rate for overall accesses
604 system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000480 # miss rate for overall accesses
605 system.l2c.overall_miss_rate::cpu2.itb.walker 0.000187 # miss rate for overall accesses
606 system.l2c.overall_miss_rate::cpu2.inst 0.018703 # miss rate for overall accesses
607 system.l2c.overall_miss_rate::cpu2.data 0.066413 # miss rate for overall accesses
608 system.l2c.overall_miss_rate::total 0.068409 # miss rate for overall accesses
609 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73375.896934 # average ReadReq miss latency
610 system.l2c.ReadReq_avg_miss_latency::cpu1.data 75372.426955 # average ReadReq miss latency
611 system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80923.076923 # average ReadReq miss latency
612 system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 74500 # average ReadReq miss latency
613 system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77745.776955 # average ReadReq miss latency
614 system.l2c.ReadReq_avg_miss_latency::cpu2.data 77292.053813 # average ReadReq miss latency
615 system.l2c.ReadReq_avg_miss_latency::total 39132.170481 # average ReadReq miss latency
616 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14451 # average UpgradeReq miss latency
617 system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 13008.894879 # average UpgradeReq miss latency
618 system.l2c.UpgradeReq_avg_miss_latency::total 5862.664162 # average UpgradeReq miss latency
619 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68481.281713 # average ReadExReq miss latency
620 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71029.522801 # average ReadExReq miss latency
621 system.l2c.ReadExReq_avg_miss_latency::total 29719.536478 # average ReadExReq miss latency
622 system.l2c.demand_avg_miss_latency::cpu1.inst 73375.896934 # average overall miss latency
623 system.l2c.demand_avg_miss_latency::cpu1.data 69472.688659 # average overall miss latency
624 system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80923.076923 # average overall miss latency
625 system.l2c.demand_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency
626 system.l2c.demand_avg_miss_latency::cpu2.inst 77745.776955 # average overall miss latency
627 system.l2c.demand_avg_miss_latency::cpu2.data 72757.030004 # average overall miss latency
628 system.l2c.demand_avg_miss_latency::total 32256.568092 # average overall miss latency
629 system.l2c.overall_avg_miss_latency::cpu1.inst 73375.896934 # average overall miss latency
630 system.l2c.overall_avg_miss_latency::cpu1.data 69472.688659 # average overall miss latency
631 system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80923.076923 # average overall miss latency
632 system.l2c.overall_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency
633 system.l2c.overall_avg_miss_latency::cpu2.inst 77745.776955 # average overall miss latency
634 system.l2c.overall_avg_miss_latency::cpu2.data 72757.030004 # average overall miss latency
635 system.l2c.overall_avg_miss_latency::total 32256.568092 # average overall miss latency
636 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
637 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
638 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
639 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
640 system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
641 system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
642 system.l2c.fast_writes 0 # number of fast writes performed
643 system.l2c.cache_copies 0 # number of cache copies performed
644 system.l2c.writebacks::writebacks 95814 # number of writebacks
645 system.l2c.writebacks::total 95814 # number of writebacks
646 system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
647 system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
648 system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
649 system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
650 system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
651 system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
652 system.l2c.ReadReq_mshr_misses::cpu1.inst 1533 # number of ReadReq MSHR misses
653 system.l2c.ReadReq_mshr_misses::cpu1.data 3888 # number of ReadReq MSHR misses
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655 system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 2 # number of ReadReq MSHR misses
656 system.l2c.ReadReq_mshr_misses::cpu2.inst 6751 # number of ReadReq MSHR misses
657 system.l2c.ReadReq_mshr_misses::cpu2.data 12246 # number of ReadReq MSHR misses
658 system.l2c.ReadReq_mshr_misses::total 24446 # number of ReadReq MSHR misses
659 system.l2c.UpgradeReq_mshr_misses::cpu1.data 206 # number of UpgradeReq MSHR misses
660 system.l2c.UpgradeReq_mshr_misses::cpu2.data 371 # number of UpgradeReq MSHR misses
661 system.l2c.UpgradeReq_mshr_misses::total 577 # number of UpgradeReq MSHR misses
662 system.l2c.ReadExReq_mshr_misses::cpu1.data 23137 # number of ReadExReq MSHR misses
663 system.l2c.ReadExReq_mshr_misses::cpu2.data 32148 # number of ReadExReq MSHR misses
664 system.l2c.ReadExReq_mshr_misses::total 55285 # number of ReadExReq MSHR misses
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667 system.l2c.demand_mshr_misses::cpu2.dtb.walker 26 # number of demand (read+write) MSHR misses
668 system.l2c.demand_mshr_misses::cpu2.itb.walker 2 # number of demand (read+write) MSHR misses
669 system.l2c.demand_mshr_misses::cpu2.inst 6751 # number of demand (read+write) MSHR misses
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671 system.l2c.demand_mshr_misses::total 79731 # number of demand (read+write) MSHR misses
672 system.l2c.overall_mshr_misses::cpu1.inst 1533 # number of overall MSHR misses
673 system.l2c.overall_mshr_misses::cpu1.data 27025 # number of overall MSHR misses
674 system.l2c.overall_mshr_misses::cpu2.dtb.walker 26 # number of overall MSHR misses
675 system.l2c.overall_mshr_misses::cpu2.itb.walker 2 # number of overall MSHR misses
676 system.l2c.overall_mshr_misses::cpu2.inst 6751 # number of overall MSHR misses
677 system.l2c.overall_mshr_misses::cpu2.data 44394 # number of overall MSHR misses
678 system.l2c.overall_mshr_misses::total 79731 # number of overall MSHR misses
679 system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 93050250 # number of ReadReq MSHR miss cycles
680 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 244480004 # number of ReadReq MSHR miss cycles
681 system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1780500 # number of ReadReq MSHR miss cycles
682 system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 125000 # number of ReadReq MSHR miss cycles
683 system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 440173014 # number of ReadReq MSHR miss cycles
684 system.l2c.ReadReq_mshr_miss_latency::cpu2.data 793487001 # number of ReadReq MSHR miss cycles
685 system.l2c.ReadReq_mshr_miss_latency::total 1573095769 # number of ReadReq MSHR miss cycles
686 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2610195 # number of UpgradeReq MSHR miss cycles
687 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3849868 # number of UpgradeReq MSHR miss cycles
688 system.l2c.UpgradeReq_mshr_miss_latency::total 6460063 # number of UpgradeReq MSHR miss cycles
689 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1288379085 # number of ReadExReq MSHR miss cycles
690 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1870619355 # number of ReadExReq MSHR miss cycles
691 system.l2c.ReadExReq_mshr_miss_latency::total 3158998440 # number of ReadExReq MSHR miss cycles
692 system.l2c.demand_mshr_miss_latency::cpu1.inst 93050250 # number of demand (read+write) MSHR miss cycles
693 system.l2c.demand_mshr_miss_latency::cpu1.data 1532859089 # number of demand (read+write) MSHR miss cycles
694 system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1780500 # number of demand (read+write) MSHR miss cycles
695 system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
696 system.l2c.demand_mshr_miss_latency::cpu2.inst 440173014 # number of demand (read+write) MSHR miss cycles
697 system.l2c.demand_mshr_miss_latency::cpu2.data 2664106356 # number of demand (read+write) MSHR miss cycles
698 system.l2c.demand_mshr_miss_latency::total 4732094209 # number of demand (read+write) MSHR miss cycles
699 system.l2c.overall_mshr_miss_latency::cpu1.inst 93050250 # number of overall MSHR miss cycles
700 system.l2c.overall_mshr_miss_latency::cpu1.data 1532859089 # number of overall MSHR miss cycles
701 system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1780500 # number of overall MSHR miss cycles
702 system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 125000 # number of overall MSHR miss cycles
703 system.l2c.overall_mshr_miss_latency::cpu2.inst 440173014 # number of overall MSHR miss cycles
704 system.l2c.overall_mshr_miss_latency::cpu2.data 2664106356 # number of overall MSHR miss cycles
705 system.l2c.overall_mshr_miss_latency::total 4732094209 # number of overall MSHR miss cycles
706 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28007446000 # number of ReadReq MSHR uncacheable cycles
707 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30457930500 # number of ReadReq MSHR uncacheable cycles
708 system.l2c.ReadReq_mshr_uncacheable_latency::total 58465376500 # number of ReadReq MSHR uncacheable cycles
709 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 376483500 # number of WriteReq MSHR uncacheable cycles
710 system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 742130500 # number of WriteReq MSHR uncacheable cycles
711 system.l2c.WriteReq_mshr_uncacheable_latency::total 1118614000 # number of WriteReq MSHR uncacheable cycles
712 system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28383929500 # number of overall MSHR uncacheable cycles
713 system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31200061000 # number of overall MSHR uncacheable cycles
714 system.l2c.overall_mshr_uncacheable_latency::total 59583990500 # number of overall MSHR uncacheable cycles
715 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010847 # mshr miss rate for ReadReq accesses
716 system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017275 # mshr miss rate for ReadReq accesses
717 system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000480 # mshr miss rate for ReadReq accesses
718 system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000187 # mshr miss rate for ReadReq accesses
719 system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018700 # mshr miss rate for ReadReq accesses
720 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021176 # mshr miss rate for ReadReq accesses
721 system.l2c.ReadReq_mshr_miss_rate::total 0.010593 # mshr miss rate for ReadReq accesses
722 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817460 # mshr miss rate for UpgradeReq accesses
723 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.799569 # mshr miss rate for UpgradeReq accesses
724 system.l2c.UpgradeReq_mshr_miss_rate::total 0.359054 # mshr miss rate for UpgradeReq accesses
725 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.400045 # mshr miss rate for ReadExReq accesses
726 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.356629 # mshr miss rate for ReadExReq accesses
727 system.l2c.ReadExReq_mshr_miss_rate::total 0.186246 # mshr miss rate for ReadExReq accesses
728 system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010847 # mshr miss rate for demand accesses
729 system.l2c.demand_mshr_miss_rate::cpu1.data 0.095529 # mshr miss rate for demand accesses
730 system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000480 # mshr miss rate for demand accesses
731 system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000187 # mshr miss rate for demand accesses
732 system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018700 # mshr miss rate for demand accesses
733 system.l2c.demand_mshr_miss_rate::cpu2.data 0.066413 # mshr miss rate for demand accesses
734 system.l2c.demand_mshr_miss_rate::total 0.030613 # mshr miss rate for demand accesses
735 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010847 # mshr miss rate for overall accesses
736 system.l2c.overall_mshr_miss_rate::cpu1.data 0.095529 # mshr miss rate for overall accesses
737 system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000480 # mshr miss rate for overall accesses
738 system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000187 # mshr miss rate for overall accesses
739 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018700 # mshr miss rate for overall accesses
740 system.l2c.overall_mshr_miss_rate::cpu2.data 0.066413 # mshr miss rate for overall accesses
741 system.l2c.overall_mshr_miss_rate::total 0.030613 # mshr miss rate for overall accesses
742 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60698.140900 # average ReadReq mshr miss latency
743 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62880.659465 # average ReadReq mshr miss latency
744 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231 # average ReadReq mshr miss latency
745 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency
746 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65201.157458 # average ReadReq mshr miss latency
747 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64795.606810 # average ReadReq mshr miss latency
748 system.l2c.ReadReq_avg_mshr_miss_latency::total 64349.822834 # average ReadReq mshr miss latency
749 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12670.849515 # average UpgradeReq mshr miss latency
750 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10377.002695 # average UpgradeReq mshr miss latency
751 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11195.949740 # average UpgradeReq mshr miss latency
752 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55684.794269 # average ReadExReq mshr miss latency
753 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58187.736562 # average ReadExReq mshr miss latency
754 system.l2c.ReadExReq_avg_mshr_miss_latency::total 57140.244913 # average ReadExReq mshr miss latency
755 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60698.140900 # average overall mshr miss latency
756 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56720.040296 # average overall mshr miss latency
757 system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231 # average overall mshr miss latency
758 system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency
759 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65201.157458 # average overall mshr miss latency
760 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60010.504933 # average overall mshr miss latency
761 system.l2c.demand_avg_mshr_miss_latency::total 59350.744491 # average overall mshr miss latency
762 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60698.140900 # average overall mshr miss latency
763 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56720.040296 # average overall mshr miss latency
764 system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231 # average overall mshr miss latency
765 system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency
766 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65201.157458 # average overall mshr miss latency
767 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60010.504933 # average overall mshr miss latency
768 system.l2c.overall_avg_mshr_miss_latency::total 59350.744491 # average overall mshr miss latency
769 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
770 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
771 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
772 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
773 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
774 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
775 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
776 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
777 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
778 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
779 system.iocache.tags.replacements 47572 # number of replacements
780 system.iocache.tags.tagsinuse 0.107425 # Cycle average of tags in use
781 system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
782 system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
783 system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
784 system.iocache.tags.warmup_cycle 5000219024509 # Cycle when the warmup percentage was hit.
785 system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.107425 # Average occupied blocks per requestor
786 system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006714 # Average percentage of cache occupancy
787 system.iocache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy
788 system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
789 system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
790 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
791 system.iocache.tags.tag_accesses 428643 # Number of tag accesses
792 system.iocache.tags.data_accesses 428643 # Number of data accesses
793 system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
794 system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
795 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
796 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
797 system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
798 system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
799 system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
800 system.iocache.overall_misses::total 47627 # number of overall misses
801 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128792785 # number of ReadReq miss cycles
802 system.iocache.ReadReq_miss_latency::total 128792785 # number of ReadReq miss cycles
803 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5668191006 # number of WriteReq miss cycles
804 system.iocache.WriteReq_miss_latency::total 5668191006 # number of WriteReq miss cycles
805 system.iocache.demand_miss_latency::pc.south_bridge.ide 5796983791 # number of demand (read+write) miss cycles
806 system.iocache.demand_miss_latency::total 5796983791 # number of demand (read+write) miss cycles
807 system.iocache.overall_miss_latency::pc.south_bridge.ide 5796983791 # number of overall miss cycles
808 system.iocache.overall_miss_latency::total 5796983791 # number of overall miss cycles
809 system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
810 system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
811 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
812 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
813 system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
814 system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
815 system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
816 system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
817 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
818 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
819 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
820 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
821 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
822 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
823 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
824 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
825 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 141998.660419 # average ReadReq miss latency
826 system.iocache.ReadReq_avg_miss_latency::total 141998.660419 # average ReadReq miss latency
827 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 121322.581464 # average WriteReq miss latency
828 system.iocache.WriteReq_avg_miss_latency::total 121322.581464 # average WriteReq miss latency
829 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency
830 system.iocache.demand_avg_miss_latency::total 121716.332983 # average overall miss latency
831 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency
832 system.iocache.overall_avg_miss_latency::total 121716.332983 # average overall miss latency
833 system.iocache.blocked_cycles::no_mshrs 88529 # number of cycles access was blocked
834 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
835 system.iocache.blocked::no_mshrs 7334 # number of cycles access was blocked
836 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
837 system.iocache.avg_blocked_cycles::no_mshrs 12.071039 # average number of cycles each access was blocked
838 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
839 system.iocache.fast_writes 0 # number of fast writes performed
840 system.iocache.cache_copies 0 # number of cache copies performed
841 system.iocache.writebacks::writebacks 46667 # number of writebacks
842 system.iocache.writebacks::total 46667 # number of writebacks
843 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 744 # number of ReadReq MSHR misses
844 system.iocache.ReadReq_mshr_misses::total 744 # number of ReadReq MSHR misses
845 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 22928 # number of WriteReq MSHR misses
846 system.iocache.WriteReq_mshr_misses::total 22928 # number of WriteReq MSHR misses
847 system.iocache.demand_mshr_misses::pc.south_bridge.ide 23672 # number of demand (read+write) MSHR misses
848 system.iocache.demand_mshr_misses::total 23672 # number of demand (read+write) MSHR misses
849 system.iocache.overall_mshr_misses::pc.south_bridge.ide 23672 # number of overall MSHR misses
850 system.iocache.overall_mshr_misses::total 23672 # number of overall MSHR misses
851 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90079785 # number of ReadReq MSHR miss cycles
852 system.iocache.ReadReq_mshr_miss_latency::total 90079785 # number of ReadReq MSHR miss cycles
853 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4474936508 # number of WriteReq MSHR miss cycles
854 system.iocache.WriteReq_mshr_miss_latency::total 4474936508 # number of WriteReq MSHR miss cycles
855 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of demand (read+write) MSHR miss cycles
856 system.iocache.demand_mshr_miss_latency::total 4565016293 # number of demand (read+write) MSHR miss cycles
857 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of overall MSHR miss cycles
858 system.iocache.overall_mshr_miss_latency::total 4565016293 # number of overall MSHR miss cycles
859 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.820287 # mshr miss rate for ReadReq accesses
860 system.iocache.ReadReq_mshr_miss_rate::total 0.820287 # mshr miss rate for ReadReq accesses
861 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.490753 # mshr miss rate for WriteReq accesses
862 system.iocache.WriteReq_mshr_miss_rate::total 0.490753 # mshr miss rate for WriteReq accesses
863 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for demand accesses
864 system.iocache.demand_mshr_miss_rate::total 0.497029 # mshr miss rate for demand accesses
865 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for overall accesses
866 system.iocache.overall_mshr_miss_rate::total 0.497029 # mshr miss rate for overall accesses
867 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121074.979839 # average ReadReq mshr miss latency
868 system.iocache.ReadReq_avg_mshr_miss_latency::total 121074.979839 # average ReadReq mshr miss latency
869 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195173.434578 # average WriteReq mshr miss latency
870 system.iocache.WriteReq_avg_mshr_miss_latency::total 195173.434578 # average WriteReq mshr miss latency
871 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency
872 system.iocache.demand_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency
873 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency
874 system.iocache.overall_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency
875 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
876 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
877 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
878 system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
879 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
880 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
881 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
882 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
883 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
884 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
885 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
886 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
887 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
888 system.toL2Bus.throughput 52329028 # Throughput (bytes/s)
889 system.toL2Bus.trans_dist::ReadReq 1794981 # Transaction distribution
890 system.toL2Bus.trans_dist::ReadResp 1794440 # Transaction distribution
891 system.toL2Bus.trans_dist::WriteReq 6370 # Transaction distribution
892 system.toL2Bus.trans_dist::WriteResp 6370 # Transaction distribution
893 system.toL2Bus.trans_dist::Writeback 902417 # Transaction distribution
894 system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution
895 system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution
896 system.toL2Bus.trans_dist::ReadExReq 170908 # Transaction distribution
897 system.toL2Bus.trans_dist::ReadExResp 147982 # Transaction distribution
898 system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
899 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1004724 # Packet count per connected master and slave (bytes)
900 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3613728 # Packet count per connected master and slave (bytes)
901 system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 35279 # Packet count per connected master and slave (bytes)
902 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 136436 # Packet count per connected master and slave (bytes)
903 system.toL2Bus.pkt_count::total 4790167 # Packet count per connected master and slave (bytes)
904 system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32150080 # Cumulative packet size per connected master and slave (bytes)
905 system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119808027 # Cumulative packet size per connected master and slave (bytes)
906 system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 127712 # Cumulative packet size per connected master and slave (bytes)
907 system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 515032 # Cumulative packet size per connected master and slave (bytes)
908 system.toL2Bus.tot_pkt_size::total 152600851 # Cumulative packet size per connected master and slave (bytes)
909 system.toL2Bus.data_through_bus 268845429 # Total data (bytes)
910 system.toL2Bus.snoop_data_through_bus 114024 # Total snoop data (bytes)
911 system.toL2Bus.reqLayer0.occupancy 5038805323 # Layer occupancy (ticks)
912 system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
913 system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks)
914 system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
915 system.toL2Bus.respLayer0.occupancy 2262930320 # Layer occupancy (ticks)
916 system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
917 system.toL2Bus.respLayer1.occupancy 4696428413 # Layer occupancy (ticks)
918 system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
919 system.toL2Bus.respLayer2.occupancy 19332464 # Layer occupancy (ticks)
920 system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
921 system.toL2Bus.respLayer3.occupancy 72173756 # Layer occupancy (ticks)
922 system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
923 system.iobus.throughput 1276348 # Throughput (bytes/s)
924 system.iobus.trans_dist::ReadReq 149977 # Transaction distribution
925 system.iobus.trans_dist::ReadResp 149977 # Transaction distribution
926 system.iobus.trans_dist::WriteReq 28411 # Transaction distribution
927 system.iobus.trans_dist::WriteResp 28411 # Transaction distribution
928 system.iobus.trans_dist::MessageReq 885 # Transaction distribution
929 system.iobus.trans_dist::MessageResp 885 # Transaction distribution
930 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
931 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
932 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5752 # Packet count per connected master and slave (bytes)
933 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
934 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 582 # Packet count per connected master and slave (bytes)
935 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes)
936 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes)
937 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
938 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287032 # Packet count per connected master and slave (bytes)
939 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 332 # Packet count per connected master and slave (bytes)
940 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
941 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13448 # Packet count per connected master and slave (bytes)
942 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
943 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes)
944 system.iobus.pkt_count_system.bridge.master::total 309432 # Packet count per connected master and slave (bytes)
945 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 47344 # Packet count per connected master and slave (bytes)
946 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 47344 # Packet count per connected master and slave (bytes)
947 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1770 # Packet count per connected master and slave (bytes)
948 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1770 # Packet count per connected master and slave (bytes)
949 system.iobus.pkt_count::total 358546 # Packet count per connected master and slave (bytes)
950 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
951 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
952 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3245 # Cumulative packet size per connected master and slave (bytes)
953 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
954 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 291 # Cumulative packet size per connected master and slave (bytes)
955 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes)
956 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes)
957 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
958 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143516 # Cumulative packet size per connected master and slave (bytes)
959 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 664 # Cumulative packet size per connected master and slave (bytes)
960 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
961 system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6724 # Cumulative packet size per connected master and slave (bytes)
962 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
963 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes)
964 system.iobus.tot_pkt_size_system.bridge.master::total 158682 # Cumulative packet size per connected master and slave (bytes)
965 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1503808 # Cumulative packet size per connected master and slave (bytes)
966 system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1503808 # Cumulative packet size per connected master and slave (bytes)
967 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3540 # Cumulative packet size per connected master and slave (bytes)
968 system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3540 # Cumulative packet size per connected master and slave (bytes)
969 system.iobus.tot_pkt_size::total 1666030 # Cumulative packet size per connected master and slave (bytes)
970 system.iobus.data_through_bus 6560144 # Total data (bytes)
971 system.iobus.reqLayer0.occupancy 2116890 # Layer occupancy (ticks)
972 system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
973 system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
974 system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
975 system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks)
976 system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
977 system.iobus.reqLayer3.occupancy 4753000 # Layer occupancy (ticks)
978 system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
979 system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
980 system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
981 system.iobus.reqLayer5.occupancy 383000 # Layer occupancy (ticks)
982 system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
983 system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks)
984 system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
985 system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks)
986 system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
987 system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
988 system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
989 system.iobus.reqLayer9.occupancy 143517000 # Layer occupancy (ticks)
990 system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
991 system.iobus.reqLayer10.occupancy 264000 # Layer occupancy (ticks)
992 system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
993 system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
994 system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
995 system.iobus.reqLayer13.occupancy 10048000 # Layer occupancy (ticks)
996 system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
997 system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks)
998 system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
999 system.iobus.reqLayer18.occupancy 209101042 # Layer occupancy (ticks)
1000 system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1001 system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks)
1002 system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1003 system.iobus.respLayer0.occupancy 303949000 # Layer occupancy (ticks)
1004 system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1005 system.iobus.respLayer1.occupancy 28759251 # Layer occupancy (ticks)
1006 system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1007 system.iobus.respLayer2.occupancy 885000 # Layer occupancy (ticks)
1008 system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
1009 system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
1010 system.cpu0.numCycles 1144797664 # number of cpu cycles simulated
1011 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1012 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1013 system.cpu0.committedInsts 72999922 # Number of instructions committed
1014 system.cpu0.committedOps 148305710 # Number of ops (including micro ops) committed
1015 system.cpu0.num_int_alu_accesses 136279674 # Number of integer alu accesses
1016 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
1017 system.cpu0.num_func_calls 1016299 # number of times a function call or return occured
1018 system.cpu0.num_conditional_control_insts 14345558 # number of instructions that are conditional controls
1019 system.cpu0.num_int_insts 136279674 # number of integer instructions
1020 system.cpu0.num_fp_insts 0 # number of float instructions
1021 system.cpu0.num_int_register_reads 250792350 # number of times the integer registers were read
1022 system.cpu0.num_int_register_writes 116890419 # number of times the integer registers were written
1023 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
1024 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
1025 system.cpu0.num_cc_register_reads 84577193 # number of times the CC registers were read
1026 system.cpu0.num_cc_register_writes 56435831 # number of times the CC registers were written
1027 system.cpu0.num_mem_refs 14370687 # number of memory refs
1028 system.cpu0.num_load_insts 10454117 # Number of load instructions
1029 system.cpu0.num_store_insts 3916570 # Number of store instructions
1030 system.cpu0.num_idle_cycles 1087719763.352511 # Number of idle cycles
1031 system.cpu0.num_busy_cycles 57077900.647489 # Number of busy cycles
1032 system.cpu0.not_idle_fraction 0.049859 # Percentage of non-idle cycles
1033 system.cpu0.idle_fraction 0.950141 # Percentage of idle cycles
1034 system.cpu0.Branches 15728655 # Number of branches fetched
1035 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1036 system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
1037 system.cpu0.icache.tags.replacements 853193 # number of replacements
1038 system.cpu0.icache.tags.tagsinuse 510.838528 # Cycle average of tags in use
1039 system.cpu0.icache.tags.total_refs 129757026 # Total number of references to valid blocks.
1040 system.cpu0.icache.tags.sampled_refs 853705 # Sample count of references to valid blocks.
1041 system.cpu0.icache.tags.avg_refs 151.992815 # Average number of references to valid blocks.
1042 system.cpu0.icache.tags.warmup_cycle 147468978000 # Cycle when the warmup percentage was hit.
1043 system.cpu0.icache.tags.occ_blocks::cpu0.inst 295.878537 # Average occupied blocks per requestor
1044 system.cpu0.icache.tags.occ_blocks::cpu1.inst 138.959383 # Average occupied blocks per requestor
1045 system.cpu0.icache.tags.occ_blocks::cpu2.inst 76.000608 # Average occupied blocks per requestor
1046 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.577888 # Average percentage of cache occupancy
1047 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.271405 # Average percentage of cache occupancy
1048 system.cpu0.icache.tags.occ_percent::cpu2.inst 0.148439 # Average percentage of cache occupancy
1049 system.cpu0.icache.tags.occ_percent::total 0.997732 # Average percentage of cache occupancy
1050 system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1051 system.cpu0.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
1052 system.cpu0.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
1053 system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
1054 system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
1055 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1056 system.cpu0.icache.tags.tag_accesses 131484548 # Number of tag accesses
1057 system.cpu0.icache.tags.data_accesses 131484548 # Number of data accesses
1058 system.cpu0.icache.ReadReq_hits::cpu0.inst 88843413 # number of ReadReq hits
1059 system.cpu0.icache.ReadReq_hits::cpu1.inst 38144708 # number of ReadReq hits
1060 system.cpu0.icache.ReadReq_hits::cpu2.inst 2768905 # number of ReadReq hits
1061 system.cpu0.icache.ReadReq_hits::total 129757026 # number of ReadReq hits
1062 system.cpu0.icache.demand_hits::cpu0.inst 88843413 # number of demand (read+write) hits
1063 system.cpu0.icache.demand_hits::cpu1.inst 38144708 # number of demand (read+write) hits
1064 system.cpu0.icache.demand_hits::cpu2.inst 2768905 # number of demand (read+write) hits
1065 system.cpu0.icache.demand_hits::total 129757026 # number of demand (read+write) hits
1066 system.cpu0.icache.overall_hits::cpu0.inst 88843413 # number of overall hits
1067 system.cpu0.icache.overall_hits::cpu1.inst 38144708 # number of overall hits
1068 system.cpu0.icache.overall_hits::cpu2.inst 2768905 # number of overall hits
1069 system.cpu0.icache.overall_hits::total 129757026 # number of overall hits
1070 system.cpu0.icache.ReadReq_misses::cpu0.inst 351339 # number of ReadReq misses
1071 system.cpu0.icache.ReadReq_misses::cpu1.inst 141332 # number of ReadReq misses
1072 system.cpu0.icache.ReadReq_misses::cpu2.inst 381133 # number of ReadReq misses
1073 system.cpu0.icache.ReadReq_misses::total 873804 # number of ReadReq misses
1074 system.cpu0.icache.demand_misses::cpu0.inst 351339 # number of demand (read+write) misses
1075 system.cpu0.icache.demand_misses::cpu1.inst 141332 # number of demand (read+write) misses
1076 system.cpu0.icache.demand_misses::cpu2.inst 381133 # number of demand (read+write) misses
1077 system.cpu0.icache.demand_misses::total 873804 # number of demand (read+write) misses
1078 system.cpu0.icache.overall_misses::cpu0.inst 351339 # number of overall misses
1079 system.cpu0.icache.overall_misses::cpu1.inst 141332 # number of overall misses
1080 system.cpu0.icache.overall_misses::cpu2.inst 381133 # number of overall misses
1081 system.cpu0.icache.overall_misses::total 873804 # number of overall misses
1082 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1941508750 # number of ReadReq miss cycles
1083 system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5443063468 # number of ReadReq miss cycles
1084 system.cpu0.icache.ReadReq_miss_latency::total 7384572218 # number of ReadReq miss cycles
1085 system.cpu0.icache.demand_miss_latency::cpu1.inst 1941508750 # number of demand (read+write) miss cycles
1086 system.cpu0.icache.demand_miss_latency::cpu2.inst 5443063468 # number of demand (read+write) miss cycles
1087 system.cpu0.icache.demand_miss_latency::total 7384572218 # number of demand (read+write) miss cycles
1088 system.cpu0.icache.overall_miss_latency::cpu1.inst 1941508750 # number of overall miss cycles
1089 system.cpu0.icache.overall_miss_latency::cpu2.inst 5443063468 # number of overall miss cycles
1090 system.cpu0.icache.overall_miss_latency::total 7384572218 # number of overall miss cycles
1091 system.cpu0.icache.ReadReq_accesses::cpu0.inst 89194752 # number of ReadReq accesses(hits+misses)
1092 system.cpu0.icache.ReadReq_accesses::cpu1.inst 38286040 # number of ReadReq accesses(hits+misses)
1093 system.cpu0.icache.ReadReq_accesses::cpu2.inst 3150038 # number of ReadReq accesses(hits+misses)
1094 system.cpu0.icache.ReadReq_accesses::total 130630830 # number of ReadReq accesses(hits+misses)
1095 system.cpu0.icache.demand_accesses::cpu0.inst 89194752 # number of demand (read+write) accesses
1096 system.cpu0.icache.demand_accesses::cpu1.inst 38286040 # number of demand (read+write) accesses
1097 system.cpu0.icache.demand_accesses::cpu2.inst 3150038 # number of demand (read+write) accesses
1098 system.cpu0.icache.demand_accesses::total 130630830 # number of demand (read+write) accesses
1099 system.cpu0.icache.overall_accesses::cpu0.inst 89194752 # number of overall (read+write) accesses
1100 system.cpu0.icache.overall_accesses::cpu1.inst 38286040 # number of overall (read+write) accesses
1101 system.cpu0.icache.overall_accesses::cpu2.inst 3150038 # number of overall (read+write) accesses
1102 system.cpu0.icache.overall_accesses::total 130630830 # number of overall (read+write) accesses
1103 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003939 # miss rate for ReadReq accesses
1104 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003691 # miss rate for ReadReq accesses
1105 system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120993 # miss rate for ReadReq accesses
1106 system.cpu0.icache.ReadReq_miss_rate::total 0.006689 # miss rate for ReadReq accesses
1107 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003939 # miss rate for demand accesses
1108 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003691 # miss rate for demand accesses
1109 system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120993 # miss rate for demand accesses
1110 system.cpu0.icache.demand_miss_rate::total 0.006689 # miss rate for demand accesses
1111 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003939 # miss rate for overall accesses
1112 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003691 # miss rate for overall accesses
1113 system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120993 # miss rate for overall accesses
1114 system.cpu0.icache.overall_miss_rate::total 0.006689 # miss rate for overall accesses
1115 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13737.219809 # average ReadReq miss latency
1116 system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14281.270496 # average ReadReq miss latency
1117 system.cpu0.icache.ReadReq_avg_miss_latency::total 8451.062501 # average ReadReq miss latency
1118 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13737.219809 # average overall miss latency
1119 system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14281.270496 # average overall miss latency
1120 system.cpu0.icache.demand_avg_miss_latency::total 8451.062501 # average overall miss latency
1121 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13737.219809 # average overall miss latency
1122 system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14281.270496 # average overall miss latency
1123 system.cpu0.icache.overall_avg_miss_latency::total 8451.062501 # average overall miss latency
1124 system.cpu0.icache.blocked_cycles::no_mshrs 4847 # number of cycles access was blocked
1125 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1126 system.cpu0.icache.blocked::no_mshrs 200 # number of cycles access was blocked
1127 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1128 system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.235000 # average number of cycles each access was blocked
1129 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1130 system.cpu0.icache.fast_writes 0 # number of fast writes performed
1131 system.cpu0.icache.cache_copies 0 # number of cache copies performed
1132 system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 20086 # number of ReadReq MSHR hits
1133 system.cpu0.icache.ReadReq_mshr_hits::total 20086 # number of ReadReq MSHR hits
1134 system.cpu0.icache.demand_mshr_hits::cpu2.inst 20086 # number of demand (read+write) MSHR hits
1135 system.cpu0.icache.demand_mshr_hits::total 20086 # number of demand (read+write) MSHR hits
1136 system.cpu0.icache.overall_mshr_hits::cpu2.inst 20086 # number of overall MSHR hits
1137 system.cpu0.icache.overall_mshr_hits::total 20086 # number of overall MSHR hits
1138 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 141332 # number of ReadReq MSHR misses
1139 system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 361047 # number of ReadReq MSHR misses
1140 system.cpu0.icache.ReadReq_mshr_misses::total 502379 # number of ReadReq MSHR misses
1141 system.cpu0.icache.demand_mshr_misses::cpu1.inst 141332 # number of demand (read+write) MSHR misses
1142 system.cpu0.icache.demand_mshr_misses::cpu2.inst 361047 # number of demand (read+write) MSHR misses
1143 system.cpu0.icache.demand_mshr_misses::total 502379 # number of demand (read+write) MSHR misses
1144 system.cpu0.icache.overall_mshr_misses::cpu1.inst 141332 # number of overall MSHR misses
1145 system.cpu0.icache.overall_mshr_misses::cpu2.inst 361047 # number of overall MSHR misses
1146 system.cpu0.icache.overall_mshr_misses::total 502379 # number of overall MSHR misses
1147 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1658307250 # number of ReadReq MSHR miss cycles
1148 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510414171 # number of ReadReq MSHR miss cycles
1149 system.cpu0.icache.ReadReq_mshr_miss_latency::total 6168721421 # number of ReadReq MSHR miss cycles
1150 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1658307250 # number of demand (read+write) MSHR miss cycles
1151 system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4510414171 # number of demand (read+write) MSHR miss cycles
1152 system.cpu0.icache.demand_mshr_miss_latency::total 6168721421 # number of demand (read+write) MSHR miss cycles
1153 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1658307250 # number of overall MSHR miss cycles
1154 system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4510414171 # number of overall MSHR miss cycles
1155 system.cpu0.icache.overall_mshr_miss_latency::total 6168721421 # number of overall MSHR miss cycles
1156 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003691 # mshr miss rate for ReadReq accesses
1157 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114617 # mshr miss rate for ReadReq accesses
1158 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003846 # mshr miss rate for ReadReq accesses
1159 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003691 # mshr miss rate for demand accesses
1160 system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114617 # mshr miss rate for demand accesses
1161 system.cpu0.icache.demand_mshr_miss_rate::total 0.003846 # mshr miss rate for demand accesses
1162 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003691 # mshr miss rate for overall accesses
1163 system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114617 # mshr miss rate for overall accesses
1164 system.cpu0.icache.overall_mshr_miss_rate::total 0.003846 # mshr miss rate for overall accesses
1165 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11733.416707 # average ReadReq mshr miss latency
1166 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12492.595621 # average ReadReq mshr miss latency
1167 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12279.019268 # average ReadReq mshr miss latency
1168 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11733.416707 # average overall mshr miss latency
1169 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12492.595621 # average overall mshr miss latency
1170 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12279.019268 # average overall mshr miss latency
1171 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11733.416707 # average overall mshr miss latency
1172 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12492.595621 # average overall mshr miss latency
1173 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12279.019268 # average overall mshr miss latency
1174 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1175 system.cpu0.dcache.tags.replacements 1636224 # number of replacements
1176 system.cpu0.dcache.tags.tagsinuse 511.999323 # Cycle average of tags in use
1177 system.cpu0.dcache.tags.total_refs 19637131 # Total number of references to valid blocks.
1178 system.cpu0.dcache.tags.sampled_refs 1636736 # Sample count of references to valid blocks.
1179 system.cpu0.dcache.tags.avg_refs 11.997739 # Average number of references to valid blocks.
1180 system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
1181 system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.200499 # Average occupied blocks per requestor
1182 system.cpu0.dcache.tags.occ_blocks::cpu1.data 230.134495 # Average occupied blocks per requestor
1183 system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.664329 # Average occupied blocks per requestor
1184 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.539454 # Average percentage of cache occupancy
1185 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.449481 # Average percentage of cache occupancy
1186 system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011063 # Average percentage of cache occupancy
1187 system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
1188 system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1189 system.cpu0.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id
1190 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id
1191 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
1192 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1193 system.cpu0.dcache.tags.tag_accesses 88232962 # Number of tag accesses
1194 system.cpu0.dcache.tags.data_accesses 88232962 # Number of data accesses
1195 system.cpu0.dcache.ReadReq_hits::cpu0.data 5302290 # number of ReadReq hits
1196 system.cpu0.dcache.ReadReq_hits::cpu1.data 2343807 # number of ReadReq hits
1197 system.cpu0.dcache.ReadReq_hits::cpu2.data 3905907 # number of ReadReq hits
1198 system.cpu0.dcache.ReadReq_hits::total 11552004 # number of ReadReq hits
1199 system.cpu0.dcache.WriteReq_hits::cpu0.data 3762855 # number of WriteReq hits
1200 system.cpu0.dcache.WriteReq_hits::cpu1.data 1548346 # number of WriteReq hits
1201 system.cpu0.dcache.WriteReq_hits::cpu2.data 2772193 # number of WriteReq hits
1202 system.cpu0.dcache.WriteReq_hits::total 8083394 # number of WriteReq hits
1203 system.cpu0.dcache.demand_hits::cpu0.data 9065145 # number of demand (read+write) hits
1204 system.cpu0.dcache.demand_hits::cpu1.data 3892153 # number of demand (read+write) hits
1205 system.cpu0.dcache.demand_hits::cpu2.data 6678100 # number of demand (read+write) hits
1206 system.cpu0.dcache.demand_hits::total 19635398 # number of demand (read+write) hits
1207 system.cpu0.dcache.overall_hits::cpu0.data 9065145 # number of overall hits
1208 system.cpu0.dcache.overall_hits::cpu1.data 3892153 # number of overall hits
1209 system.cpu0.dcache.overall_hits::cpu2.data 6678100 # number of overall hits
1210 system.cpu0.dcache.overall_hits::total 19635398 # number of overall hits
1211 system.cpu0.dcache.ReadReq_misses::cpu0.data 536567 # number of ReadReq misses
1212 system.cpu0.dcache.ReadReq_misses::cpu1.data 225063 # number of ReadReq misses
1213 system.cpu0.dcache.ReadReq_misses::cpu2.data 936224 # number of ReadReq misses
1214 system.cpu0.dcache.ReadReq_misses::total 1697854 # number of ReadReq misses
1215 system.cpu0.dcache.WriteReq_misses::cpu0.data 149749 # number of WriteReq misses
1216 system.cpu0.dcache.WriteReq_misses::cpu1.data 58088 # number of WriteReq misses
1217 system.cpu0.dcache.WriteReq_misses::cpu2.data 107958 # number of WriteReq misses
1218 system.cpu0.dcache.WriteReq_misses::total 315795 # number of WriteReq misses
1219 system.cpu0.dcache.demand_misses::cpu0.data 686316 # number of demand (read+write) misses
1220 system.cpu0.dcache.demand_misses::cpu1.data 283151 # number of demand (read+write) misses
1221 system.cpu0.dcache.demand_misses::cpu2.data 1044182 # number of demand (read+write) misses
1222 system.cpu0.dcache.demand_misses::total 2013649 # number of demand (read+write) misses
1223 system.cpu0.dcache.overall_misses::cpu0.data 686316 # number of overall misses
1224 system.cpu0.dcache.overall_misses::cpu1.data 283151 # number of overall misses
1225 system.cpu0.dcache.overall_misses::cpu2.data 1044182 # number of overall misses
1226 system.cpu0.dcache.overall_misses::total 2013649 # number of overall misses
1227 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3188254504 # number of ReadReq miss cycles
1228 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14965969569 # number of ReadReq miss cycles
1229 system.cpu0.dcache.ReadReq_miss_latency::total 18154224073 # number of ReadReq miss cycles
1230 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2125358780 # number of WriteReq miss cycles
1231 system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3377412183 # number of WriteReq miss cycles
1232 system.cpu0.dcache.WriteReq_miss_latency::total 5502770963 # number of WriteReq miss cycles
1233 system.cpu0.dcache.demand_miss_latency::cpu1.data 5313613284 # number of demand (read+write) miss cycles
1234 system.cpu0.dcache.demand_miss_latency::cpu2.data 18343381752 # number of demand (read+write) miss cycles
1235 system.cpu0.dcache.demand_miss_latency::total 23656995036 # number of demand (read+write) miss cycles
1236 system.cpu0.dcache.overall_miss_latency::cpu1.data 5313613284 # number of overall miss cycles
1237 system.cpu0.dcache.overall_miss_latency::cpu2.data 18343381752 # number of overall miss cycles
1238 system.cpu0.dcache.overall_miss_latency::total 23656995036 # number of overall miss cycles
1239 system.cpu0.dcache.ReadReq_accesses::cpu0.data 5838857 # number of ReadReq accesses(hits+misses)
1240 system.cpu0.dcache.ReadReq_accesses::cpu1.data 2568870 # number of ReadReq accesses(hits+misses)
1241 system.cpu0.dcache.ReadReq_accesses::cpu2.data 4842131 # number of ReadReq accesses(hits+misses)
1242 system.cpu0.dcache.ReadReq_accesses::total 13249858 # number of ReadReq accesses(hits+misses)
1243 system.cpu0.dcache.WriteReq_accesses::cpu0.data 3912604 # number of WriteReq accesses(hits+misses)
1244 system.cpu0.dcache.WriteReq_accesses::cpu1.data 1606434 # number of WriteReq accesses(hits+misses)
1245 system.cpu0.dcache.WriteReq_accesses::cpu2.data 2880151 # number of WriteReq accesses(hits+misses)
1246 system.cpu0.dcache.WriteReq_accesses::total 8399189 # number of WriteReq accesses(hits+misses)
1247 system.cpu0.dcache.demand_accesses::cpu0.data 9751461 # number of demand (read+write) accesses
1248 system.cpu0.dcache.demand_accesses::cpu1.data 4175304 # number of demand (read+write) accesses
1249 system.cpu0.dcache.demand_accesses::cpu2.data 7722282 # number of demand (read+write) accesses
1250 system.cpu0.dcache.demand_accesses::total 21649047 # number of demand (read+write) accesses
1251 system.cpu0.dcache.overall_accesses::cpu0.data 9751461 # number of overall (read+write) accesses
1252 system.cpu0.dcache.overall_accesses::cpu1.data 4175304 # number of overall (read+write) accesses
1253 system.cpu0.dcache.overall_accesses::cpu2.data 7722282 # number of overall (read+write) accesses
1254 system.cpu0.dcache.overall_accesses::total 21649047 # number of overall (read+write) accesses
1255 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.091896 # miss rate for ReadReq accesses
1256 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.087612 # miss rate for ReadReq accesses
1257 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.193350 # miss rate for ReadReq accesses
1258 system.cpu0.dcache.ReadReq_miss_rate::total 0.128141 # miss rate for ReadReq accesses
1259 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038273 # miss rate for WriteReq accesses
1260 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036160 # miss rate for WriteReq accesses
1261 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037483 # miss rate for WriteReq accesses
1262 system.cpu0.dcache.WriteReq_miss_rate::total 0.037598 # miss rate for WriteReq accesses
1263 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.070381 # miss rate for demand accesses
1264 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.067816 # miss rate for demand accesses
1265 system.cpu0.dcache.demand_miss_rate::cpu2.data 0.135217 # miss rate for demand accesses
1266 system.cpu0.dcache.demand_miss_rate::total 0.093013 # miss rate for demand accesses
1267 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070381 # miss rate for overall accesses
1268 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.067816 # miss rate for overall accesses
1269 system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135217 # miss rate for overall accesses
1270 system.cpu0.dcache.overall_miss_rate::total 0.093013 # miss rate for overall accesses
1271 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14166.053523 # average ReadReq miss latency
1272 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.458148 # average ReadReq miss latency
1273 system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.452987 # average ReadReq miss latency
1274 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.603154 # average WriteReq miss latency
1275 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31284.501223 # average WriteReq miss latency
1276 system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.136443 # average WriteReq miss latency
1277 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18766.005714 # average overall miss latency
1278 system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17567.226549 # average overall miss latency
1279 system.cpu0.dcache.demand_avg_miss_latency::total 11748.321101 # average overall miss latency
1280 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18766.005714 # average overall miss latency
1281 system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17567.226549 # average overall miss latency
1282 system.cpu0.dcache.overall_avg_miss_latency::total 11748.321101 # average overall miss latency
1283 system.cpu0.dcache.blocked_cycles::no_mshrs 168342 # number of cycles access was blocked
1284 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1285 system.cpu0.dcache.blocked::no_mshrs 11795 # number of cycles access was blocked
1286 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1287 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.272319 # average number of cycles each access was blocked
1288 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1289 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1290 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1291 system.cpu0.dcache.writebacks::writebacks 1545523 # number of writebacks
1292 system.cpu0.dcache.writebacks::total 1545523 # number of writebacks
1293 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 357871 # number of ReadReq MSHR hits
1294 system.cpu0.dcache.ReadReq_mshr_hits::total 357871 # number of ReadReq MSHR hits
1295 system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17395 # number of WriteReq MSHR hits
1296 system.cpu0.dcache.WriteReq_mshr_hits::total 17395 # number of WriteReq MSHR hits
1297 system.cpu0.dcache.demand_mshr_hits::cpu2.data 375266 # number of demand (read+write) MSHR hits
1298 system.cpu0.dcache.demand_mshr_hits::total 375266 # number of demand (read+write) MSHR hits
1299 system.cpu0.dcache.overall_mshr_hits::cpu2.data 375266 # number of overall MSHR hits
1300 system.cpu0.dcache.overall_mshr_hits::total 375266 # number of overall MSHR hits
1301 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225063 # number of ReadReq MSHR misses
1302 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578353 # number of ReadReq MSHR misses
1303 system.cpu0.dcache.ReadReq_mshr_misses::total 803416 # number of ReadReq MSHR misses
1304 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58088 # number of WriteReq MSHR misses
1305 system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90563 # number of WriteReq MSHR misses
1306 system.cpu0.dcache.WriteReq_mshr_misses::total 148651 # number of WriteReq MSHR misses
1307 system.cpu0.dcache.demand_mshr_misses::cpu1.data 283151 # number of demand (read+write) MSHR misses
1308 system.cpu0.dcache.demand_mshr_misses::cpu2.data 668916 # number of demand (read+write) MSHR misses
1309 system.cpu0.dcache.demand_mshr_misses::total 952067 # number of demand (read+write) MSHR misses
1310 system.cpu0.dcache.overall_mshr_misses::cpu1.data 283151 # number of overall MSHR misses
1311 system.cpu0.dcache.overall_mshr_misses::cpu2.data 668916 # number of overall MSHR misses
1312 system.cpu0.dcache.overall_mshr_misses::total 952067 # number of overall MSHR misses
1313 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2737161496 # number of ReadReq MSHR miss cycles
1314 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8309689554 # number of ReadReq MSHR miss cycles
1315 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11046851050 # number of ReadReq MSHR miss cycles
1316 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1998659220 # number of WriteReq MSHR miss cycles
1317 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2996226317 # number of WriteReq MSHR miss cycles
1318 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4994885537 # number of WriteReq MSHR miss cycles
1319 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4735820716 # number of demand (read+write) MSHR miss cycles
1320 system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11305915871 # number of demand (read+write) MSHR miss cycles
1321 system.cpu0.dcache.demand_mshr_miss_latency::total 16041736587 # number of demand (read+write) MSHR miss cycles
1322 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4735820716 # number of overall MSHR miss cycles
1323 system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11305915871 # number of overall MSHR miss cycles
1324 system.cpu0.dcache.overall_mshr_miss_latency::total 16041736587 # number of overall MSHR miss cycles
1325 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30467694000 # number of ReadReq MSHR uncacheable cycles
1326 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33225580500 # number of ReadReq MSHR uncacheable cycles
1327 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63693274500 # number of ReadReq MSHR uncacheable cycles
1328 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 404660000 # number of WriteReq MSHR uncacheable cycles
1329 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 790542000 # number of WriteReq MSHR uncacheable cycles
1330 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1195202000 # number of WriteReq MSHR uncacheable cycles
1331 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30872354000 # number of overall MSHR uncacheable cycles
1332 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34016122500 # number of overall MSHR uncacheable cycles
1333 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64888476500 # number of overall MSHR uncacheable cycles
1334 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087612 # mshr miss rate for ReadReq accesses
1335 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119442 # mshr miss rate for ReadReq accesses
1336 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060636 # mshr miss rate for ReadReq accesses
1337 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036160 # mshr miss rate for WriteReq accesses
1338 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031444 # mshr miss rate for WriteReq accesses
1339 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017698 # mshr miss rate for WriteReq accesses
1340 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067816 # mshr miss rate for demand accesses
1341 system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086622 # mshr miss rate for demand accesses
1342 system.cpu0.dcache.demand_mshr_miss_rate::total 0.043977 # mshr miss rate for demand accesses
1343 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067816 # mshr miss rate for overall accesses
1344 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086622 # mshr miss rate for overall accesses
1345 system.cpu0.dcache.overall_mshr_miss_rate::total 0.043977 # mshr miss rate for overall accesses
1346 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12161.756913 # average ReadReq mshr miss latency
1347 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14367.850697 # average ReadReq mshr miss latency
1348 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13749.851945 # average ReadReq mshr miss latency
1349 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34407.437336 # average WriteReq mshr miss latency
1350 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33084.441958 # average WriteReq mshr miss latency
1351 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33601.425735 # average WriteReq mshr miss latency
1352 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16725.424653 # average overall mshr miss latency
1353 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16901.846975 # average overall mshr miss latency
1354 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16849.377814 # average overall mshr miss latency
1355 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16725.424653 # average overall mshr miss latency
1356 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16901.846975 # average overall mshr miss latency
1357 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16849.377814 # average overall mshr miss latency
1358 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1359 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
1360 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1361 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1362 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
1363 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1364 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1365 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
1366 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1367 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1368 system.cpu1.numCycles 2608015730 # number of cpu cycles simulated
1369 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1370 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1371 system.cpu1.committedInsts 34716890 # Number of instructions committed
1372 system.cpu1.committedOps 67541836 # Number of ops (including micro ops) committed
1373 system.cpu1.num_int_alu_accesses 62669042 # Number of integer alu accesses
1374 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
1375 system.cpu1.num_func_calls 430919 # number of times a function call or return occured
1376 system.cpu1.num_conditional_control_insts 6413966 # number of instructions that are conditional controls
1377 system.cpu1.num_int_insts 62669042 # number of integer instructions
1378 system.cpu1.num_fp_insts 0 # number of float instructions
1379 system.cpu1.num_int_register_reads 115548964 # number of times the integer registers were read
1380 system.cpu1.num_int_register_writes 54160900 # number of times the integer registers were written
1381 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
1382 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
1383 system.cpu1.num_cc_register_reads 35562537 # number of times the CC registers were read
1384 system.cpu1.num_cc_register_writes 26614034 # number of times the CC registers were written
1385 system.cpu1.num_mem_refs 4364452 # number of memory refs
1386 system.cpu1.num_load_insts 2756893 # Number of load instructions
1387 system.cpu1.num_store_insts 1607559 # Number of store instructions
1388 system.cpu1.num_idle_cycles 2483429860.768801 # Number of idle cycles
1389 system.cpu1.num_busy_cycles 124585869.231199 # Number of busy cycles
1390 system.cpu1.not_idle_fraction 0.047770 # Percentage of non-idle cycles
1391 system.cpu1.idle_fraction 0.952230 # Percentage of idle cycles
1392 system.cpu1.Branches 7003911 # Number of branches fetched
1393 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1394 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1395 system.cpu2.branchPred.lookups 28782114 # Number of BP lookups
1396 system.cpu2.branchPred.condPredicted 28782114 # Number of conditional branches predicted
1397 system.cpu2.branchPred.condIncorrect 316524 # Number of conditional branches incorrect
1398 system.cpu2.branchPred.BTBLookups 26348266 # Number of BTB lookups
1399 system.cpu2.branchPred.BTBHits 25752004 # Number of BTB hits
1400 system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1401 system.cpu2.branchPred.BTBHitPct 97.736997 # BTB Hit Percentage
1402 system.cpu2.branchPred.usedRAS 537542 # Number of times the RAS was used to get a target.
1403 system.cpu2.branchPred.RASInCorrect 63717 # Number of incorrect RAS predictions.
1404 system.cpu2.numCycles 155552038 # number of cpu cycles simulated
1405 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1406 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1407 system.cpu2.fetch.icacheStallCycles 9686701 # Number of cycles fetch is stalled on an Icache miss
1408 system.cpu2.fetch.Insts 141772190 # Number of instructions fetch has processed
1409 system.cpu2.fetch.Branches 28782114 # Number of branches that fetch encountered
1410 system.cpu2.fetch.predictedBranches 26289546 # Number of branches that fetch has predicted taken
1411 system.cpu2.fetch.Cycles 54340809 # Number of cycles fetch has run and was not squashing or blocked
1412 system.cpu2.fetch.SquashCycles 1470890 # Number of cycles fetch has spent squashing
1413 system.cpu2.fetch.TlbCycles 70055 # Number of cycles fetch has spent waiting for tlb
1414 system.cpu2.fetch.BlockedCycles 24627328 # Number of cycles fetch has spent blocked
1415 system.cpu2.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1416 system.cpu2.fetch.PendingDrainCycles 7901 # Number of cycles fetch has spent waiting on pipes to drain
1417 system.cpu2.fetch.PendingTrapStallCycles 23768 # Number of stall cycles due to pending traps
1418 system.cpu2.fetch.IcacheWaitRetryStallCycles 376 # Number of stall cycles due to full MSHR
1419 system.cpu2.fetch.CacheLines 3150040 # Number of cache lines fetched
1420 system.cpu2.fetch.IcacheSquashes 144648 # Number of outstanding Icache misses that were squashed
1421 system.cpu2.fetch.ItlbSquashes 2015 # Number of outstanding ITLB misses that were squashed
1422 system.cpu2.fetch.rateDist::samples 89899907 # Number of instructions fetched each cycle (Total)
1423 system.cpu2.fetch.rateDist::mean 3.110146 # Number of instructions fetched each cycle (Total)
1424 system.cpu2.fetch.rateDist::stdev 3.408280 # Number of instructions fetched each cycle (Total)
1425 system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1426 system.cpu2.fetch.rateDist::0 35694732 39.70% 39.70% # Number of instructions fetched each cycle (Total)
1427 system.cpu2.fetch.rateDist::1 594255 0.66% 40.37% # Number of instructions fetched each cycle (Total)
1428 system.cpu2.fetch.rateDist::2 23712499 26.38% 66.74% # Number of instructions fetched each cycle (Total)
1429 system.cpu2.fetch.rateDist::3 314699 0.35% 67.09% # Number of instructions fetched each cycle (Total)
1430 system.cpu2.fetch.rateDist::4 599600 0.67% 67.76% # Number of instructions fetched each cycle (Total)
1431 system.cpu2.fetch.rateDist::5 812421 0.90% 68.66% # Number of instructions fetched each cycle (Total)
1432 system.cpu2.fetch.rateDist::6 338881 0.38% 69.04% # Number of instructions fetched each cycle (Total)
1433 system.cpu2.fetch.rateDist::7 517837 0.58% 69.62% # Number of instructions fetched each cycle (Total)
1434 system.cpu2.fetch.rateDist::8 27314983 30.38% 100.00% # Number of instructions fetched each cycle (Total)
1435 system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1436 system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1437 system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1438 system.cpu2.fetch.rateDist::total 89899907 # Number of instructions fetched each cycle (Total)
1439 system.cpu2.fetch.branchRate 0.185032 # Number of branch fetches per cycle
1440 system.cpu2.fetch.rate 0.911413 # Number of inst fetches per cycle
1441 system.cpu2.decode.IdleCycles 11154829 # Number of cycles decode is idle
1442 system.cpu2.decode.BlockedCycles 23540580 # Number of cycles decode is blocked
1443 system.cpu2.decode.RunCycles 30801007 # Number of cycles decode is running
1444 system.cpu2.decode.UnblockCycles 1287318 # Number of cycles decode is unblocking
1445 system.cpu2.decode.SquashCycles 1141583 # Number of cycles decode is squashing
1446 system.cpu2.decode.DecodedInsts 278785410 # Number of instructions handled by decode
1447 system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode
1448 system.cpu2.rename.SquashCycles 1141583 # Number of cycles rename is squashing
1449 system.cpu2.rename.IdleCycles 12143079 # Number of cycles rename is idle
1450 system.cpu2.rename.BlockCycles 13933433 # Number of cycles rename is blocking
1451 system.cpu2.rename.serializeStallCycles 4524497 # count of cycles rename stalled for serializing inst
1452 system.cpu2.rename.RunCycles 30930733 # Number of cycles rename is running
1453 system.cpu2.rename.UnblockCycles 5252059 # Number of cycles rename is unblocking
1454 system.cpu2.rename.RenamedInsts 277791777 # Number of instructions processed by rename
1455 system.cpu2.rename.ROBFullEvents 7238 # Number of times rename has blocked due to ROB full
1456 system.cpu2.rename.IQFullEvents 2464468 # Number of times rename has blocked due to IQ full
1457 system.cpu2.rename.LSQFullEvents 2117220 # Number of times rename has blocked due to LSQ full
1458 system.cpu2.rename.RenamedOperands 331976691 # Number of destination operands rename has renamed
1459 system.cpu2.rename.RenameLookups 604531856 # Number of register rename lookups that rename has made
1460 system.cpu2.rename.int_rename_lookups 371338716 # Number of integer rename lookups
1461 system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups
1462 system.cpu2.rename.CommittedMaps 321781805 # Number of HB maps that are committed
1463 system.cpu2.rename.UndoneMaps 10194886 # Number of HB maps that are undone due to squashing
1464 system.cpu2.rename.serializingInsts 148461 # count of serializing insts renamed
1465 system.cpu2.rename.tempSerializingInsts 149473 # count of temporary serializing insts renamed
1466 system.cpu2.rename.skidInsts 11392573 # count of insts added to the skid buffer
1467 system.cpu2.memDep0.insertedLoads 6171654 # Number of loads inserted to the mem dependence unit.
1468 system.cpu2.memDep0.insertedStores 3395563 # Number of stores inserted to the mem dependence unit.
1469 system.cpu2.memDep0.conflictingLoads 345995 # Number of conflicting loads.
1470 system.cpu2.memDep0.conflictingStores 292325 # Number of conflicting stores.
1471 system.cpu2.iq.iqInstsAdded 276091246 # Number of instructions added to the IQ (excludes non-spec)
1472 system.cpu2.iq.iqNonSpecInstsAdded 414813 # Number of non-speculative instructions added to the IQ
1473 system.cpu2.iq.iqInstsIssued 274477250 # Number of instructions issued
1474 system.cpu2.iq.iqSquashedInstsIssued 60541 # Number of squashed instructions issued
1475 system.cpu2.iq.iqSquashedInstsExamined 7173454 # Number of squashed instructions iterated over during squash; mainly for profiling
1476 system.cpu2.iq.iqSquashedOperandsExamined 11041443 # Number of squashed operands that are examined and possibly removed from graph
1477 system.cpu2.iq.iqSquashedNonSpecRemoved 56132 # Number of squashed non-spec instructions that were removed
1478 system.cpu2.iq.issued_per_cycle::samples 89899907 # Number of insts issued each cycle
1479 system.cpu2.iq.issued_per_cycle::mean 3.053143 # Number of insts issued each cycle
1480 system.cpu2.iq.issued_per_cycle::stdev 2.400877 # Number of insts issued each cycle
1481 system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1482 system.cpu2.iq.issued_per_cycle::0 26563563 29.55% 29.55% # Number of insts issued each cycle
1483 system.cpu2.iq.issued_per_cycle::1 6130901 6.82% 36.37% # Number of insts issued each cycle
1484 system.cpu2.iq.issued_per_cycle::2 3934206 4.38% 40.74% # Number of insts issued each cycle
1485 system.cpu2.iq.issued_per_cycle::3 2710119 3.01% 43.76% # Number of insts issued each cycle
1486 system.cpu2.iq.issued_per_cycle::4 25036419 27.85% 71.61% # Number of insts issued each cycle
1487 system.cpu2.iq.issued_per_cycle::5 1342117 1.49% 73.10% # Number of insts issued each cycle
1488 system.cpu2.iq.issued_per_cycle::6 23840310 26.52% 99.62% # Number of insts issued each cycle
1489 system.cpu2.iq.issued_per_cycle::7 288717 0.32% 99.94% # Number of insts issued each cycle
1490 system.cpu2.iq.issued_per_cycle::8 53555 0.06% 100.00% # Number of insts issued each cycle
1491 system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1492 system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1493 system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1494 system.cpu2.iq.issued_per_cycle::total 89899907 # Number of insts issued each cycle
1495 system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1496 system.cpu2.iq.fu_full::IntAlu 122290 33.50% 33.50% # attempts to use FU when none available
1497 system.cpu2.iq.fu_full::IntMult 245 0.07% 33.57% # attempts to use FU when none available
1498 system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available
1499 system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available
1500 system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available
1501 system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available
1502 system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available
1503 system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available
1504 system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available
1505 system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available
1506 system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available
1507 system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available
1508 system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available
1509 system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available
1510 system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available
1511 system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available
1512 system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available
1513 system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available
1514 system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available
1515 system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available
1516 system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available
1517 system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available
1518 system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available
1519 system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available
1520 system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available
1521 system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available
1522 system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available
1523 system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available
1524 system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available
1525 system.cpu2.iq.fu_full::MemRead 189949 52.03% 85.60% # attempts to use FU when none available
1526 system.cpu2.iq.fu_full::MemWrite 52573 14.40% 100.00% # attempts to use FU when none available
1527 system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1528 system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1529 system.cpu2.iq.FU_type_0::No_OpClass 80536 0.03% 0.03% # Type of FU issued
1530 system.cpu2.iq.FU_type_0::IntAlu 264658650 96.42% 96.45% # Type of FU issued
1531 system.cpu2.iq.FU_type_0::IntMult 54855 0.02% 96.47% # Type of FU issued
1532 system.cpu2.iq.FU_type_0::IntDiv 48402 0.02% 96.49% # Type of FU issued
1533 system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.49% # Type of FU issued
1534 system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.49% # Type of FU issued
1535 system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.49% # Type of FU issued
1536 system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.49% # Type of FU issued
1537 system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.49% # Type of FU issued
1538 system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.49% # Type of FU issued
1539 system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.49% # Type of FU issued
1540 system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.49% # Type of FU issued
1541 system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.49% # Type of FU issued
1542 system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.49% # Type of FU issued
1543 system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.49% # Type of FU issued
1544 system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.49% # Type of FU issued
1545 system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.49% # Type of FU issued
1546 system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.49% # Type of FU issued
1547 system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.49% # Type of FU issued
1548 system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.49% # Type of FU issued
1549 system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.49% # Type of FU issued
1550 system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.49% # Type of FU issued
1551 system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.49% # Type of FU issued
1552 system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.49% # Type of FU issued
1553 system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.49% # Type of FU issued
1554 system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.49% # Type of FU issued
1555 system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.49% # Type of FU issued
1556 system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.49% # Type of FU issued
1557 system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.49% # Type of FU issued
1558 system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.49% # Type of FU issued
1559 system.cpu2.iq.FU_type_0::MemRead 6455691 2.35% 98.84% # Type of FU issued
1560 system.cpu2.iq.FU_type_0::MemWrite 3179116 1.16% 100.00% # Type of FU issued
1561 system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1562 system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1563 system.cpu2.iq.FU_type_0::total 274477250 # Type of FU issued
1564 system.cpu2.iq.rate 1.764537 # Inst issue rate
1565 system.cpu2.iq.fu_busy_cnt 365057 # FU busy when requested
1566 system.cpu2.iq.fu_busy_rate 0.001330 # FU busy rate (busy events/executed inst)
1567 system.cpu2.iq.int_inst_queue_reads 639321511 # Number of integer instruction queue reads
1568 system.cpu2.iq.int_inst_queue_writes 283683445 # Number of integer instruction queue writes
1569 system.cpu2.iq.int_inst_queue_wakeup_accesses 273115126 # Number of integer instruction queue wakeup accesses
1570 system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads
1571 system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes
1572 system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses
1573 system.cpu2.iq.int_alu_accesses 274761742 # Number of integer alu accesses
1574 system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses
1575 system.cpu2.iew.lsq.thread0.forwLoads 634301 # Number of loads that had data forwarded from stores
1576 system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1577 system.cpu2.iew.lsq.thread0.squashedLoads 1002623 # Number of loads squashed
1578 system.cpu2.iew.lsq.thread0.ignoredResponses 6718 # Number of memory responses ignored because the instruction is squashed
1579 system.cpu2.iew.lsq.thread0.memOrderViolation 4440 # Number of memory ordering violations
1580 system.cpu2.iew.lsq.thread0.squashedStores 510444 # Number of stores squashed
1581 system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1582 system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1583 system.cpu2.iew.lsq.thread0.rescheduledLoads 656391 # Number of loads that were rescheduled
1584 system.cpu2.iew.lsq.thread0.cacheBlocked 10280 # Number of times an access to memory failed due to the cache being blocked
1585 system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1586 system.cpu2.iew.iewSquashCycles 1141583 # Number of cycles IEW is squashing
1587 system.cpu2.iew.iewBlockCycles 9227965 # Number of cycles IEW is blocking
1588 system.cpu2.iew.iewUnblockCycles 815382 # Number of cycles IEW is unblocking
1589 system.cpu2.iew.iewDispatchedInsts 276506059 # Number of instructions dispatched to IQ
1590 system.cpu2.iew.iewDispSquashedInsts 71664 # Number of squashed instructions skipped by dispatch
1591 system.cpu2.iew.iewDispLoadInsts 6171654 # Number of dispatched load instructions
1592 system.cpu2.iew.iewDispStoreInsts 3395563 # Number of dispatched store instructions
1593 system.cpu2.iew.iewDispNonSpecInsts 234992 # Number of dispatched non-speculative instructions
1594 system.cpu2.iew.iewIQFullEvents 633068 # Number of times the IQ has become full, causing a stall
1595 system.cpu2.iew.iewLSQFullEvents 3849 # Number of times the LSQ has become full, causing a stall
1596 system.cpu2.iew.memOrderViolationEvents 4440 # Number of memory order violations
1597 system.cpu2.iew.predictedTakenIncorrect 176570 # Number of branches that were predicted taken incorrectly
1598 system.cpu2.iew.predictedNotTakenIncorrect 182318 # Number of branches that were predicted not taken incorrectly
1599 system.cpu2.iew.branchMispredicts 358888 # Number of branch mispredicts detected at execute
1600 system.cpu2.iew.iewExecutedInsts 273973436 # Number of executed instructions
1601 system.cpu2.iew.iewExecLoadInsts 6342946 # Number of load instructions executed
1602 system.cpu2.iew.iewExecSquashedInsts 503814 # Number of squashed instructions skipped in execute
1603 system.cpu2.iew.exec_swp 0 # number of swp insts executed
1604 system.cpu2.iew.exec_nop 0 # number of nop insts executed
1605 system.cpu2.iew.exec_refs 9455734 # number of memory reference insts executed
1606 system.cpu2.iew.exec_branches 27867681 # Number of branches executed
1607 system.cpu2.iew.exec_stores 3112788 # Number of stores executed
1608 system.cpu2.iew.exec_rate 1.761298 # Inst execution rate
1609 system.cpu2.iew.wb_sent 273823666 # cumulative count of insts sent to commit
1610 system.cpu2.iew.wb_count 273115144 # cumulative count of insts written-back
1611 system.cpu2.iew.wb_producers 212986974 # num instructions producing a value
1612 system.cpu2.iew.wb_consumers 348231532 # num instructions consuming a value
1613 system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1614 system.cpu2.iew.wb_rate 1.755780 # insts written-back per cycle
1615 system.cpu2.iew.wb_fanout 0.611625 # average fanout of values written-back
1616 system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1617 system.cpu2.commit.commitSquashedInsts 7474898 # The number of squashed insts skipped by commit
1618 system.cpu2.commit.commitNonSpecStalls 358681 # The number of times commit has been forced to stall to communicate backwards
1619 system.cpu2.commit.branchMispredicts 318992 # The number of times a branch was mispredicted
1620 system.cpu2.commit.committed_per_cycle::samples 88758324 # Number of insts commited each cycle
1621 system.cpu2.commit.committed_per_cycle::mean 3.031021 # Number of insts commited each cycle
1622 system.cpu2.commit.committed_per_cycle::stdev 2.870805 # Number of insts commited each cycle
1623 system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1624 system.cpu2.commit.committed_per_cycle::0 31301057 35.27% 35.27% # Number of insts commited each cycle
1625 system.cpu2.commit.committed_per_cycle::1 4393147 4.95% 40.22% # Number of insts commited each cycle
1626 system.cpu2.commit.committed_per_cycle::2 1229186 1.38% 41.60% # Number of insts commited each cycle
1627 system.cpu2.commit.committed_per_cycle::3 24655081 27.78% 69.38% # Number of insts commited each cycle
1628 system.cpu2.commit.committed_per_cycle::4 868070 0.98% 70.36% # Number of insts commited each cycle
1629 system.cpu2.commit.committed_per_cycle::5 585819 0.66% 71.02% # Number of insts commited each cycle
1630 system.cpu2.commit.committed_per_cycle::6 347474 0.39% 71.41% # Number of insts commited each cycle
1631 system.cpu2.commit.committed_per_cycle::7 23302544 26.25% 97.66% # Number of insts commited each cycle
1632 system.cpu2.commit.committed_per_cycle::8 2075946 2.34% 100.00% # Number of insts commited each cycle
1633 system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1634 system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1635 system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1636 system.cpu2.commit.committed_per_cycle::total 88758324 # Number of insts commited each cycle
1637 system.cpu2.commit.committedInsts 136214259 # Number of instructions committed
1638 system.cpu2.commit.committedOps 269028357 # Number of ops (including micro ops) committed
1639 system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1640 system.cpu2.commit.refs 8054150 # Number of memory references committed
1641 system.cpu2.commit.loads 5169031 # Number of loads committed
1642 system.cpu2.commit.membars 165004 # Number of memory barriers committed
1643 system.cpu2.commit.branches 27530478 # Number of branches committed
1644 system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1645 system.cpu2.commit.int_insts 245624895 # Number of committed integer instructions.
1646 system.cpu2.commit.function_calls 430032 # Number of function calls committed.
1647 system.cpu2.commit.bw_lim_events 2075946 # number cycles where commit BW limit reached
1648 system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1649 system.cpu2.rob.rob_reads 363157720 # The number of ROB reads
1650 system.cpu2.rob.rob_writes 554152180 # The number of ROB writes
1651 system.cpu2.timesIdled 477715 # Number of times that the entire CPU went into an idle state and unscheduled itself
1652 system.cpu2.idleCycles 65652131 # Total number of cycles that the CPU has spent unscheduled due to idling
1653 system.cpu2.quiesceCycles 4906975665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1654 system.cpu2.committedInsts 136214259 # Number of Instructions Simulated
1655 system.cpu2.committedOps 269028357 # Number of Ops (including micro ops) Simulated
1656 system.cpu2.committedInsts_total 136214259 # Number of Instructions Simulated
1657 system.cpu2.cpi 1.141966 # CPI: Cycles Per Instruction
1658 system.cpu2.cpi_total 1.141966 # CPI: Total CPI of All Threads
1659 system.cpu2.ipc 0.875683 # IPC: Instructions Per Cycle
1660 system.cpu2.ipc_total 0.875683 # IPC: Total IPC of All Threads
1661 system.cpu2.int_regfile_reads 364409735 # number of integer regfile reads
1662 system.cpu2.int_regfile_writes 218808578 # number of integer regfile writes
1663 system.cpu2.fp_regfile_reads 73042 # number of floating regfile reads
1664 system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes
1665 system.cpu2.cc_regfile_reads 139320542 # number of cc regfile reads
1666 system.cpu2.cc_regfile_writes 107246688 # number of cc regfile writes
1667 system.cpu2.misc_regfile_reads 88724841 # number of misc regfile reads
1668 system.cpu2.misc_regfile_writes 132896 # number of misc regfile writes
1669 system.cpu2.kern.inst.arm 0 # number of arm instructions executed
1670 system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
1672 ---------- End Simulation Statistics ----------
projects / gem5.git / blob