2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 5.139557 # Number of seconds simulated
4 sim_ticks 5139557121500 # Number of ticks simulated
5 final_tick 5139557121500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 183644 # Simulator instruction rate (inst/s)
8 host_op_rate 364835 # Simulator op (including micro ops) rate (op/s)
9 host_tick_rate 3871369364 # Simulator tick rate (ticks/s)
10 host_mem_usage 967408 # Number of bytes of host memory used
11 host_seconds 1327.58 # Real time elapsed on the host
12 sim_insts 243802016 # Number of instructions simulated
13 sim_ops 484348047 # Number of ops (including micro ops) simulated
14 system.physmem.bytes_read::pc.south_bridge.ide 2455296 # Number of bytes read from this memory
15 system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
16 system.physmem.bytes_read::cpu0.inst 466944 # Number of bytes read from this memory
17 system.physmem.bytes_read::cpu0.data 5828928 # Number of bytes read from this memory
18 system.physmem.bytes_read::cpu1.inst 127616 # Number of bytes read from this memory
19 system.physmem.bytes_read::cpu1.data 1842944 # Number of bytes read from this memory
20 system.physmem.bytes_read::cpu2.dtb.walker 1536 # Number of bytes read from this memory
21 system.physmem.bytes_read::cpu2.inst 356032 # Number of bytes read from this memory
22 system.physmem.bytes_read::cpu2.data 2734144 # Number of bytes read from this memory
23 system.physmem.bytes_read::total 13813760 # Number of bytes read from this memory
24 system.physmem.bytes_inst_read::cpu0.inst 466944 # Number of instructions bytes read from this memory
25 system.physmem.bytes_inst_read::cpu1.inst 127616 # Number of instructions bytes read from this memory
26 system.physmem.bytes_inst_read::cpu2.inst 356032 # Number of instructions bytes read from this memory
27 system.physmem.bytes_inst_read::total 950592 # Number of instructions bytes read from this memory
28 system.physmem.bytes_written::writebacks 9154048 # Number of bytes written to this memory
29 system.physmem.bytes_written::total 9154048 # Number of bytes written to this memory
30 system.physmem.num_reads::pc.south_bridge.ide 38364 # Number of read requests responded to by this memory
31 system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
32 system.physmem.num_reads::cpu0.inst 7296 # Number of read requests responded to by this memory
33 system.physmem.num_reads::cpu0.data 91077 # Number of read requests responded to by this memory
34 system.physmem.num_reads::cpu1.inst 1994 # Number of read requests responded to by this memory
35 system.physmem.num_reads::cpu1.data 28796 # Number of read requests responded to by this memory
36 system.physmem.num_reads::cpu2.dtb.walker 24 # Number of read requests responded to by this memory
37 system.physmem.num_reads::cpu2.inst 5563 # Number of read requests responded to by this memory
38 system.physmem.num_reads::cpu2.data 42721 # Number of read requests responded to by this memory
39 system.physmem.num_reads::total 215840 # Number of read requests responded to by this memory
40 system.physmem.num_writes::writebacks 143032 # Number of write requests responded to by this memory
41 system.physmem.num_writes::total 143032 # Number of write requests responded to by this memory
42 system.physmem.bw_read::pc.south_bridge.ide 477725 # Total read bandwidth from this memory (bytes/s)
43 system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
44 system.physmem.bw_read::cpu0.inst 90853 # Total read bandwidth from this memory (bytes/s)
45 system.physmem.bw_read::cpu0.data 1134130 # Total read bandwidth from this memory (bytes/s)
46 system.physmem.bw_read::cpu1.inst 24830 # Total read bandwidth from this memory (bytes/s)
47 system.physmem.bw_read::cpu1.data 358580 # Total read bandwidth from this memory (bytes/s)
48 system.physmem.bw_read::cpu2.dtb.walker 299 # Total read bandwidth from this memory (bytes/s)
49 system.physmem.bw_read::cpu2.inst 69273 # Total read bandwidth from this memory (bytes/s)
50 system.physmem.bw_read::cpu2.data 531980 # Total read bandwidth from this memory (bytes/s)
51 system.physmem.bw_read::total 2687734 # Total read bandwidth from this memory (bytes/s)
52 system.physmem.bw_inst_read::cpu0.inst 90853 # Instruction read bandwidth from this memory (bytes/s)
53 system.physmem.bw_inst_read::cpu1.inst 24830 # Instruction read bandwidth from this memory (bytes/s)
54 system.physmem.bw_inst_read::cpu2.inst 69273 # Instruction read bandwidth from this memory (bytes/s)
55 system.physmem.bw_inst_read::total 184956 # Instruction read bandwidth from this memory (bytes/s)
56 system.physmem.bw_write::writebacks 1781097 # Write bandwidth from this memory (bytes/s)
57 system.physmem.bw_write::total 1781097 # Write bandwidth from this memory (bytes/s)
58 system.physmem.bw_total::writebacks 1781097 # Total bandwidth to/from this memory (bytes/s)
59 system.physmem.bw_total::pc.south_bridge.ide 477725 # Total bandwidth to/from this memory (bytes/s)
60 system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
61 system.physmem.bw_total::cpu0.inst 90853 # Total bandwidth to/from this memory (bytes/s)
62 system.physmem.bw_total::cpu0.data 1134130 # Total bandwidth to/from this memory (bytes/s)
63 system.physmem.bw_total::cpu1.inst 24830 # Total bandwidth to/from this memory (bytes/s)
64 system.physmem.bw_total::cpu1.data 358580 # Total bandwidth to/from this memory (bytes/s)
65 system.physmem.bw_total::cpu2.dtb.walker 299 # Total bandwidth to/from this memory (bytes/s)
66 system.physmem.bw_total::cpu2.inst 69273 # Total bandwidth to/from this memory (bytes/s)
67 system.physmem.bw_total::cpu2.data 531980 # Total bandwidth to/from this memory (bytes/s)
68 system.physmem.bw_total::total 4468830 # Total bandwidth to/from this memory (bytes/s)
69 system.physmem.readReqs 99105 # Total number of read requests seen
70 system.physmem.writeReqs 78746 # Total number of write requests seen
71 system.physmem.cpureqs 178569 # Reqs generatd by CPU via cache - shady
72 system.physmem.bytesRead 6342720 # Total number of bytes read from memory
73 system.physmem.bytesWritten 5039744 # Total number of bytes written to memory
74 system.physmem.bytesConsumedRd 6342720 # bytesRead derated as per pkt->getSize()
75 system.physmem.bytesConsumedWr 5039744 # bytesWritten derated as per pkt->getSize()
76 system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
77 system.physmem.neitherReadNorWrite 712 # Reqs where no action is needed
78 system.physmem.perBankRdReqs::0 6100 # Track reads on a per bank basis
79 system.physmem.perBankRdReqs::1 5671 # Track reads on a per bank basis
80 system.physmem.perBankRdReqs::2 5539 # Track reads on a per bank basis
81 system.physmem.perBankRdReqs::3 6946 # Track reads on a per bank basis
82 system.physmem.perBankRdReqs::4 5876 # Track reads on a per bank basis
83 system.physmem.perBankRdReqs::5 5654 # Track reads on a per bank basis
84 system.physmem.perBankRdReqs::6 5883 # Track reads on a per bank basis
85 system.physmem.perBankRdReqs::7 7012 # Track reads on a per bank basis
86 system.physmem.perBankRdReqs::8 6334 # Track reads on a per bank basis
87 system.physmem.perBankRdReqs::9 6064 # Track reads on a per bank basis
88 system.physmem.perBankRdReqs::10 5868 # Track reads on a per bank basis
89 system.physmem.perBankRdReqs::11 7100 # Track reads on a per bank basis
90 system.physmem.perBankRdReqs::12 5762 # Track reads on a per bank basis
91 system.physmem.perBankRdReqs::13 5656 # Track reads on a per bank basis
92 system.physmem.perBankRdReqs::14 6255 # Track reads on a per bank basis
93 system.physmem.perBankRdReqs::15 7374 # Track reads on a per bank basis
94 system.physmem.perBankWrReqs::0 4754 # Track writes on a per bank basis
95 system.physmem.perBankWrReqs::1 4366 # Track writes on a per bank basis
96 system.physmem.perBankWrReqs::2 4230 # Track writes on a per bank basis
97 system.physmem.perBankWrReqs::3 5859 # Track writes on a per bank basis
98 system.physmem.perBankWrReqs::4 4494 # Track writes on a per bank basis
99 system.physmem.perBankWrReqs::5 4387 # Track writes on a per bank basis
100 system.physmem.perBankWrReqs::6 4605 # Track writes on a per bank basis
101 system.physmem.perBankWrReqs::7 5921 # Track writes on a per bank basis
102 system.physmem.perBankWrReqs::8 5001 # Track writes on a per bank basis
103 system.physmem.perBankWrReqs::9 4809 # Track writes on a per bank basis
104 system.physmem.perBankWrReqs::10 4668 # Track writes on a per bank basis
105 system.physmem.perBankWrReqs::11 5984 # Track writes on a per bank basis
106 system.physmem.perBankWrReqs::12 4422 # Track writes on a per bank basis
107 system.physmem.perBankWrReqs::13 4352 # Track writes on a per bank basis
108 system.physmem.perBankWrReqs::14 4757 # Track writes on a per bank basis
109 system.physmem.perBankWrReqs::15 6137 # Track writes on a per bank basis
110 system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
111 system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry
112 system.physmem.totGap 5135869541000 # Total gap between requests
113 system.physmem.readPktSize::0 0 # Categorize read packet sizes
114 system.physmem.readPktSize::1 0 # Categorize read packet sizes
115 system.physmem.readPktSize::2 0 # Categorize read packet sizes
116 system.physmem.readPktSize::3 0 # Categorize read packet sizes
117 system.physmem.readPktSize::4 0 # Categorize read packet sizes
118 system.physmem.readPktSize::5 0 # Categorize read packet sizes
119 system.physmem.readPktSize::6 99105 # Categorize read packet sizes
120 system.physmem.writePktSize::0 0 # Categorize write packet sizes
121 system.physmem.writePktSize::1 0 # Categorize write packet sizes
122 system.physmem.writePktSize::2 0 # Categorize write packet sizes
123 system.physmem.writePktSize::3 0 # Categorize write packet sizes
124 system.physmem.writePktSize::4 0 # Categorize write packet sizes
125 system.physmem.writePktSize::5 0 # Categorize write packet sizes
126 system.physmem.writePktSize::6 78746 # Categorize write packet sizes
127 system.physmem.rdQLenPdf::0 75637 # What read queue length does an incoming req see
128 system.physmem.rdQLenPdf::1 7751 # What read queue length does an incoming req see
129 system.physmem.rdQLenPdf::2 3409 # What read queue length does an incoming req see
130 system.physmem.rdQLenPdf::3 1725 # What read queue length does an incoming req see
131 system.physmem.rdQLenPdf::4 1554 # What read queue length does an incoming req see
132 system.physmem.rdQLenPdf::5 1226 # What read queue length does an incoming req see
133 system.physmem.rdQLenPdf::6 983 # What read queue length does an incoming req see
134 system.physmem.rdQLenPdf::7 957 # What read queue length does an incoming req see
135 system.physmem.rdQLenPdf::8 916 # What read queue length does an incoming req see
136 system.physmem.rdQLenPdf::9 876 # What read queue length does an incoming req see
137 system.physmem.rdQLenPdf::10 581 # What read queue length does an incoming req see
138 system.physmem.rdQLenPdf::11 527 # What read queue length does an incoming req see
139 system.physmem.rdQLenPdf::12 479 # What read queue length does an incoming req see
140 system.physmem.rdQLenPdf::13 448 # What read queue length does an incoming req see
141 system.physmem.rdQLenPdf::14 405 # What read queue length does an incoming req see
142 system.physmem.rdQLenPdf::15 409 # What read queue length does an incoming req see
143 system.physmem.rdQLenPdf::16 465 # What read queue length does an incoming req see
144 system.physmem.rdQLenPdf::17 448 # What read queue length does an incoming req see
145 system.physmem.rdQLenPdf::18 189 # What read queue length does an incoming req see
146 system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see
147 system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
148 system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
149 system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
150 system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
151 system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
152 system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
153 system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
154 system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
155 system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
156 system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
157 system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
158 system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
159 system.physmem.wrQLenPdf::0 2865 # What write queue length does an incoming req see
160 system.physmem.wrQLenPdf::1 3038 # What write queue length does an incoming req see
161 system.physmem.wrQLenPdf::2 3360 # What write queue length does an incoming req see
162 system.physmem.wrQLenPdf::3 3392 # What write queue length does an incoming req see
163 system.physmem.wrQLenPdf::4 3411 # What write queue length does an incoming req see
164 system.physmem.wrQLenPdf::5 3426 # What write queue length does an incoming req see
165 system.physmem.wrQLenPdf::6 3425 # What write queue length does an incoming req see
166 system.physmem.wrQLenPdf::7 3425 # What write queue length does an incoming req see
167 system.physmem.wrQLenPdf::8 3422 # What write queue length does an incoming req see
168 system.physmem.wrQLenPdf::9 3426 # What write queue length does an incoming req see
169 system.physmem.wrQLenPdf::10 3424 # What write queue length does an incoming req see
170 system.physmem.wrQLenPdf::11 3421 # What write queue length does an incoming req see
171 system.physmem.wrQLenPdf::12 3419 # What write queue length does an incoming req see
172 system.physmem.wrQLenPdf::13 3417 # What write queue length does an incoming req see
173 system.physmem.wrQLenPdf::14 3415 # What write queue length does an incoming req see
174 system.physmem.wrQLenPdf::15 3414 # What write queue length does an incoming req see
175 system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see
176 system.physmem.wrQLenPdf::17 3407 # What write queue length does an incoming req see
177 system.physmem.wrQLenPdf::18 3405 # What write queue length does an incoming req see
178 system.physmem.wrQLenPdf::19 3404 # What write queue length does an incoming req see
179 system.physmem.wrQLenPdf::20 3403 # What write queue length does an incoming req see
180 system.physmem.wrQLenPdf::21 3402 # What write queue length does an incoming req see
181 system.physmem.wrQLenPdf::22 3400 # What write queue length does an incoming req see
182 system.physmem.wrQLenPdf::23 594 # What write queue length does an incoming req see
183 system.physmem.wrQLenPdf::24 412 # What write queue length does an incoming req see
184 system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see
185 system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
186 system.physmem.wrQLenPdf::27 30 # What write queue length does an incoming req see
187 system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see
188 system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
189 system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
190 system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
191 system.physmem.totQLat 2229520000 # Total cycles spent in queuing delays
192 system.physmem.totMemAccLat 4250910000 # Sum of mem lat for all requests
193 system.physmem.totBusLat 495470000 # Total cycles spent in databus access
194 system.physmem.totBankLat 1525920000 # Total cycles spent in bank access
195 system.physmem.avgQLat 22499.04 # Average queueing delay per request
196 system.physmem.avgBankLat 15398.71 # Average bank access latency per request
197 system.physmem.avgBusLat 5000.00 # Average bus latency per request
198 system.physmem.avgMemAccLat 42897.75 # Average memory access latency
199 system.physmem.avgRdBW 1.23 # Average achieved read bandwidth in MB/s
200 system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s
201 system.physmem.avgConsumedRdBW 1.23 # Average consumed read bandwidth in MB/s
202 system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s
203 system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
204 system.physmem.busUtil 0.02 # Data bus utilization in percentage
205 system.physmem.avgRdQLen 0.00 # Average read queue length over time
206 system.physmem.avgWrQLen 0.10 # Average write queue length over time
207 system.physmem.readRowHits 83478 # Number of row buffer hits during reads
208 system.physmem.writeRowHits 56534 # Number of row buffer hits during writes
209 system.physmem.readRowHitRate 84.24 # Row buffer hit rate for reads
210 system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes
211 system.physmem.avgGap 28877372.30 # Average gap between requests
212 system.l2c.replacements 104936 # number of replacements
213 system.l2c.tagsinuse 64827.217537 # Cycle average of tags in use
214 system.l2c.total_refs 3630977 # Total number of references to valid blocks.
215 system.l2c.sampled_refs 168979 # Sample count of references to valid blocks.
216 system.l2c.avg_refs 21.487741 # Average number of references to valid blocks.
217 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
218 system.l2c.occ_blocks::writebacks 50639.454481 # Average occupied blocks per requestor
219 system.l2c.occ_blocks::cpu0.itb.walker 0.125451 # Average occupied blocks per requestor
220 system.l2c.occ_blocks::cpu0.inst 1092.997242 # Average occupied blocks per requestor
221 system.l2c.occ_blocks::cpu0.data 4517.674660 # Average occupied blocks per requestor
222 system.l2c.occ_blocks::cpu1.inst 223.356063 # Average occupied blocks per requestor
223 system.l2c.occ_blocks::cpu1.data 1300.523613 # Average occupied blocks per requestor
224 system.l2c.occ_blocks::cpu2.dtb.walker 6.306120 # Average occupied blocks per requestor
225 system.l2c.occ_blocks::cpu2.inst 1891.819622 # Average occupied blocks per requestor
226 system.l2c.occ_blocks::cpu2.data 5154.960284 # Average occupied blocks per requestor
227 system.l2c.occ_percent::writebacks 0.772697 # Average percentage of cache occupancy
228 system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
229 system.l2c.occ_percent::cpu0.inst 0.016678 # Average percentage of cache occupancy
230 system.l2c.occ_percent::cpu0.data 0.068934 # Average percentage of cache occupancy
231 system.l2c.occ_percent::cpu1.inst 0.003408 # Average percentage of cache occupancy
232 system.l2c.occ_percent::cpu1.data 0.019844 # Average percentage of cache occupancy
233 system.l2c.occ_percent::cpu2.dtb.walker 0.000096 # Average percentage of cache occupancy
234 system.l2c.occ_percent::cpu2.inst 0.028867 # Average percentage of cache occupancy
235 system.l2c.occ_percent::cpu2.data 0.078658 # Average percentage of cache occupancy
236 system.l2c.occ_percent::total 0.989185 # Average percentage of cache occupancy
237 system.l2c.ReadReq_hits::cpu0.dtb.walker 20688 # number of ReadReq hits
238 system.l2c.ReadReq_hits::cpu0.itb.walker 11397 # number of ReadReq hits
239 system.l2c.ReadReq_hits::cpu0.inst 368018 # number of ReadReq hits
240 system.l2c.ReadReq_hits::cpu0.data 524840 # number of ReadReq hits
241 system.l2c.ReadReq_hits::cpu1.dtb.walker 3790 # number of ReadReq hits
242 system.l2c.ReadReq_hits::cpu1.itb.walker 1830 # number of ReadReq hits
243 system.l2c.ReadReq_hits::cpu1.inst 151783 # number of ReadReq hits
244 system.l2c.ReadReq_hits::cpu1.data 229669 # number of ReadReq hits
245 system.l2c.ReadReq_hits::cpu2.dtb.walker 45217 # number of ReadReq hits
246 system.l2c.ReadReq_hits::cpu2.itb.walker 8673 # number of ReadReq hits
247 system.l2c.ReadReq_hits::cpu2.inst 312711 # number of ReadReq hits
248 system.l2c.ReadReq_hits::cpu2.data 544544 # number of ReadReq hits
249 system.l2c.ReadReq_hits::total 2223160 # number of ReadReq hits
250 system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
251 system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
252 system.l2c.Writeback_hits::writebacks 1544951 # number of Writeback hits
253 system.l2c.Writeback_hits::total 1544951 # number of Writeback hits
254 system.l2c.UpgradeReq_hits::cpu0.data 152 # number of UpgradeReq hits
255 system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits
256 system.l2c.UpgradeReq_hits::cpu2.data 67 # number of UpgradeReq hits
257 system.l2c.UpgradeReq_hits::total 260 # number of UpgradeReq hits
258 system.l2c.ReadExReq_hits::cpu0.data 71407 # number of ReadExReq hits
259 system.l2c.ReadExReq_hits::cpu1.data 43953 # number of ReadExReq hits
260 system.l2c.ReadExReq_hits::cpu2.data 57565 # number of ReadExReq hits
261 system.l2c.ReadExReq_hits::total 172925 # number of ReadExReq hits
262 system.l2c.demand_hits::cpu0.dtb.walker 20688 # number of demand (read+write) hits
263 system.l2c.demand_hits::cpu0.itb.walker 11399 # number of demand (read+write) hits
264 system.l2c.demand_hits::cpu0.inst 368018 # number of demand (read+write) hits
265 system.l2c.demand_hits::cpu0.data 596247 # number of demand (read+write) hits
266 system.l2c.demand_hits::cpu1.dtb.walker 3790 # number of demand (read+write) hits
267 system.l2c.demand_hits::cpu1.itb.walker 1830 # number of demand (read+write) hits
268 system.l2c.demand_hits::cpu1.inst 151783 # number of demand (read+write) hits
269 system.l2c.demand_hits::cpu1.data 273622 # number of demand (read+write) hits
270 system.l2c.demand_hits::cpu2.dtb.walker 45217 # number of demand (read+write) hits
271 system.l2c.demand_hits::cpu2.itb.walker 8673 # number of demand (read+write) hits
272 system.l2c.demand_hits::cpu2.inst 312711 # number of demand (read+write) hits
273 system.l2c.demand_hits::cpu2.data 602109 # number of demand (read+write) hits
274 system.l2c.demand_hits::total 2396087 # number of demand (read+write) hits
275 system.l2c.overall_hits::cpu0.dtb.walker 20688 # number of overall hits
276 system.l2c.overall_hits::cpu0.itb.walker 11399 # number of overall hits
277 system.l2c.overall_hits::cpu0.inst 368018 # number of overall hits
278 system.l2c.overall_hits::cpu0.data 596247 # number of overall hits
279 system.l2c.overall_hits::cpu1.dtb.walker 3790 # number of overall hits
280 system.l2c.overall_hits::cpu1.itb.walker 1830 # number of overall hits
281 system.l2c.overall_hits::cpu1.inst 151783 # number of overall hits
282 system.l2c.overall_hits::cpu1.data 273622 # number of overall hits
283 system.l2c.overall_hits::cpu2.dtb.walker 45217 # number of overall hits
284 system.l2c.overall_hits::cpu2.itb.walker 8673 # number of overall hits
285 system.l2c.overall_hits::cpu2.inst 312711 # number of overall hits
286 system.l2c.overall_hits::cpu2.data 602109 # number of overall hits
287 system.l2c.overall_hits::total 2396087 # number of overall hits
288 system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
289 system.l2c.ReadReq_misses::cpu0.inst 7296 # number of ReadReq misses
290 system.l2c.ReadReq_misses::cpu0.data 14431 # number of ReadReq misses
291 system.l2c.ReadReq_misses::cpu1.inst 1994 # number of ReadReq misses
292 system.l2c.ReadReq_misses::cpu1.data 4052 # number of ReadReq misses
293 system.l2c.ReadReq_misses::cpu2.dtb.walker 24 # number of ReadReq misses
294 system.l2c.ReadReq_misses::cpu2.inst 5567 # number of ReadReq misses
295 system.l2c.ReadReq_misses::cpu2.data 14790 # number of ReadReq misses
296 system.l2c.ReadReq_misses::total 48159 # number of ReadReq misses
297 system.l2c.UpgradeReq_misses::cpu0.data 746 # number of UpgradeReq misses
298 system.l2c.UpgradeReq_misses::cpu1.data 231 # number of UpgradeReq misses
299 system.l2c.UpgradeReq_misses::cpu2.data 361 # number of UpgradeReq misses
300 system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses
301 system.l2c.ReadExReq_misses::cpu0.data 77254 # number of ReadExReq misses
302 system.l2c.ReadExReq_misses::cpu1.data 24966 # number of ReadExReq misses
303 system.l2c.ReadExReq_misses::cpu2.data 28044 # number of ReadExReq misses
304 system.l2c.ReadExReq_misses::total 130264 # number of ReadExReq misses
305 system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
306 system.l2c.demand_misses::cpu0.inst 7296 # number of demand (read+write) misses
307 system.l2c.demand_misses::cpu0.data 91685 # number of demand (read+write) misses
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547 system.l2c.demand_mshr_miss_rate::total 0.030854 # mshr miss rate for demand accesses
548 system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012967 # mshr miss rate for overall accesses
549 system.l2c.overall_mshr_miss_rate::cpu1.data 0.095883 # mshr miss rate for overall accesses
550 system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000530 # mshr miss rate for overall accesses
551 system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017478 # mshr miss rate for overall accesses
552 system.l2c.overall_mshr_miss_rate::cpu2.data 0.066415 # mshr miss rate for overall accesses
553 system.l2c.overall_mshr_miss_rate::total 0.030854 # mshr miss rate for overall accesses
554 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 49071.084754 # average ReadReq mshr miss latency
555 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49411.556515 # average ReadReq mshr miss latency
556 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333 # average ReadReq mshr miss latency
557 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57753.835341 # average ReadReq mshr miss latency
558 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 53590.521095 # average ReadReq mshr miss latency
559 system.l2c.ReadReq_avg_mshr_miss_latency::total 53493.056693 # average ReadReq mshr miss latency
560 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10436.056277 # average UpgradeReq mshr miss latency
561 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10157.504155 # average UpgradeReq mshr miss latency
562 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10266.195946 # average UpgradeReq mshr miss latency
563 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 39604.920652 # average ReadExReq mshr miss latency
564 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 42756.266082 # average ReadExReq mshr miss latency
565 system.l2c.ReadExReq_avg_mshr_miss_latency::total 41272.084041 # average ReadExReq mshr miss latency
566 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49071.084754 # average overall mshr miss latency
567 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40974.294438 # average overall mshr miss latency
568 system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333 # average overall mshr miss latency
569 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57753.835341 # average overall mshr miss latency
570 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46497.187585 # average overall mshr miss latency
571 system.l2c.demand_avg_mshr_miss_latency::total 45337.330983 # average overall mshr miss latency
572 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49071.084754 # average overall mshr miss latency
573 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40974.294438 # average overall mshr miss latency
574 system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333 # average overall mshr miss latency
575 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57753.835341 # average overall mshr miss latency
576 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46497.187585 # average overall mshr miss latency
577 system.l2c.overall_avg_mshr_miss_latency::total 45337.330983 # average overall mshr miss latency
578 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
579 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
580 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
581 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
582 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
583 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
584 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
585 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
586 system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
587 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
588 system.iocache.replacements 47571 # number of replacements
589 system.iocache.tagsinuse 0.100524 # Cycle average of tags in use
590 system.iocache.total_refs 0 # Total number of references to valid blocks.
591 system.iocache.sampled_refs 47587 # Sample count of references to valid blocks.
592 system.iocache.avg_refs 0 # Average number of references to valid blocks.
593 system.iocache.warmup_cycle 4999700789059 # Cycle when the warmup percentage was hit.
594 system.iocache.occ_blocks::pc.south_bridge.ide 0.100524 # Average occupied blocks per requestor
595 system.iocache.occ_percent::pc.south_bridge.ide 0.006283 # Average percentage of cache occupancy
596 system.iocache.occ_percent::total 0.006283 # Average percentage of cache occupancy
597 system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses
598 system.iocache.ReadReq_misses::total 906 # number of ReadReq misses
599 system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
600 system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
601 system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses
602 system.iocache.demand_misses::total 47626 # number of demand (read+write) misses
603 system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses
604 system.iocache.overall_misses::total 47626 # number of overall misses
605 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 21701996 # number of ReadReq miss cycles
606 system.iocache.ReadReq_miss_latency::total 21701996 # number of ReadReq miss cycles
607 system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5260229904 # number of WriteReq miss cycles
608 system.iocache.WriteReq_miss_latency::total 5260229904 # number of WriteReq miss cycles
609 system.iocache.demand_miss_latency::pc.south_bridge.ide 5281931900 # number of demand (read+write) miss cycles
610 system.iocache.demand_miss_latency::total 5281931900 # number of demand (read+write) miss cycles
611 system.iocache.overall_miss_latency::pc.south_bridge.ide 5281931900 # number of overall miss cycles
612 system.iocache.overall_miss_latency::total 5281931900 # number of overall miss cycles
613 system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses)
614 system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses)
615 system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
616 system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
617 system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses
618 system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses
619 system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses
620 system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses
621 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
622 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
623 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
624 system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
625 system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
626 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
627 system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
628 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
629 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23953.637969 # average ReadReq miss latency
630 system.iocache.ReadReq_avg_miss_latency::total 23953.637969 # average ReadReq miss latency
631 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 112590.537329 # average WriteReq miss latency
632 system.iocache.WriteReq_avg_miss_latency::total 112590.537329 # average WriteReq miss latency
633 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency
634 system.iocache.demand_avg_miss_latency::total 110904.377861 # average overall miss latency
635 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency
636 system.iocache.overall_avg_miss_latency::total 110904.377861 # average overall miss latency
637 system.iocache.blocked_cycles::no_mshrs 67344 # number of cycles access was blocked
638 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
639 system.iocache.blocked::no_mshrs 6552 # number of cycles access was blocked
640 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
641 system.iocache.avg_blocked_cycles::no_mshrs 10.278388 # average number of cycles each access was blocked
642 system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
643 system.iocache.fast_writes 0 # number of fast writes performed
644 system.iocache.cache_copies 0 # number of cache copies performed
645 system.iocache.writebacks::writebacks 46667 # number of writebacks
646 system.iocache.writebacks::total 46667 # number of writebacks
647 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 169 # number of ReadReq MSHR misses
648 system.iocache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses
649 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24864 # number of WriteReq MSHR misses
650 system.iocache.WriteReq_mshr_misses::total 24864 # number of WriteReq MSHR misses
651 system.iocache.demand_mshr_misses::pc.south_bridge.ide 25033 # number of demand (read+write) MSHR misses
652 system.iocache.demand_mshr_misses::total 25033 # number of demand (read+write) MSHR misses
653 system.iocache.overall_mshr_misses::pc.south_bridge.ide 25033 # number of overall MSHR misses
654 system.iocache.overall_mshr_misses::total 25033 # number of overall MSHR misses
655 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 12912498 # number of ReadReq MSHR miss cycles
656 system.iocache.ReadReq_mshr_miss_latency::total 12912498 # number of ReadReq MSHR miss cycles
657 system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3966572850 # number of WriteReq MSHR miss cycles
658 system.iocache.WriteReq_mshr_miss_latency::total 3966572850 # number of WriteReq MSHR miss cycles
659 system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of demand (read+write) MSHR miss cycles
660 system.iocache.demand_mshr_miss_latency::total 3979485348 # number of demand (read+write) MSHR miss cycles
661 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of overall MSHR miss cycles
662 system.iocache.overall_mshr_miss_latency::total 3979485348 # number of overall MSHR miss cycles
663 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.186534 # mshr miss rate for ReadReq accesses
664 system.iocache.ReadReq_mshr_miss_rate::total 0.186534 # mshr miss rate for ReadReq accesses
665 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.532192 # mshr miss rate for WriteReq accesses
666 system.iocache.WriteReq_mshr_miss_rate::total 0.532192 # mshr miss rate for WriteReq accesses
667 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for demand accesses
668 system.iocache.demand_mshr_miss_rate::total 0.525616 # mshr miss rate for demand accesses
669 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for overall accesses
670 system.iocache.overall_mshr_miss_rate::total 0.525616 # mshr miss rate for overall accesses
671 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 76405.313609 # average ReadReq mshr miss latency
672 system.iocache.ReadReq_avg_mshr_miss_latency::total 76405.313609 # average ReadReq mshr miss latency
673 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 159530.761342 # average WriteReq mshr miss latency
674 system.iocache.WriteReq_avg_mshr_miss_latency::total 159530.761342 # average WriteReq mshr miss latency
675 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency
676 system.iocache.demand_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency
677 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency
678 system.iocache.overall_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency
679 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
680 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
681 system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
682 system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
683 system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
684 system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
685 system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
686 system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
687 system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
688 system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
689 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
690 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
691 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
692 system.cpu0.numCycles 1838156995 # number of cpu cycles simulated
693 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
694 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
695 system.cpu0.committedInsts 73261263 # Number of instructions committed
696 system.cpu0.committedOps 148566469 # Number of ops (including micro ops) committed
697 system.cpu0.num_int_alu_accesses 136919559 # Number of integer alu accesses
698 system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
699 system.cpu0.num_func_calls 1069041 # number of times a function call or return occured
700 system.cpu0.num_conditional_control_insts 14289344 # number of instructions that are conditional controls
701 system.cpu0.num_int_insts 136919559 # number of integer instructions
702 system.cpu0.num_fp_insts 0 # number of float instructions
703 system.cpu0.num_int_register_reads 336929611 # number of times the integer registers were read
704 system.cpu0.num_int_register_writes 173945922 # number of times the integer registers were written
705 system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
706 system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
707 system.cpu0.num_mem_refs 14717824 # number of memory refs
708 system.cpu0.num_load_insts 10660250 # Number of load instructions
709 system.cpu0.num_store_insts 4057574 # Number of store instructions
710 system.cpu0.num_idle_cycles 1090327710419.609375 # Number of idle cycles
711 system.cpu0.num_busy_cycles -1088489553424.609375 # Number of busy cycles
712 system.cpu0.not_idle_fraction -592.163540 # Percentage of non-idle cycles
713 system.cpu0.idle_fraction 593.163540 # Percentage of idle cycles
714 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
715 system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
716 system.cpu0.icache.replacements 846873 # number of replacements
717 system.cpu0.icache.tagsinuse 510.809979 # Cycle average of tags in use
718 system.cpu0.icache.total_refs 129726169 # Total number of references to valid blocks.
719 system.cpu0.icache.sampled_refs 847385 # Sample count of references to valid blocks.
720 system.cpu0.icache.avg_refs 153.089999 # Average number of references to valid blocks.
721 system.cpu0.icache.warmup_cycle 147287067000 # Cycle when the warmup percentage was hit.
722 system.cpu0.icache.occ_blocks::cpu0.inst 322.415881 # Average occupied blocks per requestor
723 system.cpu0.icache.occ_blocks::cpu1.inst 27.501112 # Average occupied blocks per requestor
724 system.cpu0.icache.occ_blocks::cpu2.inst 160.892986 # Average occupied blocks per requestor
725 system.cpu0.icache.occ_percent::cpu0.inst 0.629719 # Average percentage of cache occupancy
726 system.cpu0.icache.occ_percent::cpu1.inst 0.053713 # Average percentage of cache occupancy
727 system.cpu0.icache.occ_percent::cpu2.inst 0.314244 # Average percentage of cache occupancy
728 system.cpu0.icache.occ_percent::total 0.997676 # Average percentage of cache occupancy
729 system.cpu0.icache.ReadReq_hits::cpu0.inst 89310227 # number of ReadReq hits
730 system.cpu0.icache.ReadReq_hits::cpu1.inst 37866681 # number of ReadReq hits
731 system.cpu0.icache.ReadReq_hits::cpu2.inst 2549261 # number of ReadReq hits
732 system.cpu0.icache.ReadReq_hits::total 129726169 # number of ReadReq hits
733 system.cpu0.icache.demand_hits::cpu0.inst 89310227 # number of demand (read+write) hits
734 system.cpu0.icache.demand_hits::cpu1.inst 37866681 # number of demand (read+write) hits
735 system.cpu0.icache.demand_hits::cpu2.inst 2549261 # number of demand (read+write) hits
736 system.cpu0.icache.demand_hits::total 129726169 # number of demand (read+write) hits
737 system.cpu0.icache.overall_hits::cpu0.inst 89310227 # number of overall hits
738 system.cpu0.icache.overall_hits::cpu1.inst 37866681 # number of overall hits
739 system.cpu0.icache.overall_hits::cpu2.inst 2549261 # number of overall hits
740 system.cpu0.icache.overall_hits::total 129726169 # number of overall hits
741 system.cpu0.icache.ReadReq_misses::cpu0.inst 375314 # number of ReadReq misses
742 system.cpu0.icache.ReadReq_misses::cpu1.inst 153777 # number of ReadReq misses
743 system.cpu0.icache.ReadReq_misses::cpu2.inst 335702 # number of ReadReq misses
744 system.cpu0.icache.ReadReq_misses::total 864793 # number of ReadReq misses
745 system.cpu0.icache.demand_misses::cpu0.inst 375314 # number of demand (read+write) misses
746 system.cpu0.icache.demand_misses::cpu1.inst 153777 # number of demand (read+write) misses
747 system.cpu0.icache.demand_misses::cpu2.inst 335702 # number of demand (read+write) misses
748 system.cpu0.icache.demand_misses::total 864793 # number of demand (read+write) misses
749 system.cpu0.icache.overall_misses::cpu0.inst 375314 # number of overall misses
750 system.cpu0.icache.overall_misses::cpu1.inst 153777 # number of overall misses
751 system.cpu0.icache.overall_misses::cpu2.inst 335702 # number of overall misses
752 system.cpu0.icache.overall_misses::total 864793 # number of overall misses
753 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2109411000 # number of ReadReq miss cycles
754 system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4767990981 # number of ReadReq miss cycles
755 system.cpu0.icache.ReadReq_miss_latency::total 6877401981 # number of ReadReq miss cycles
756 system.cpu0.icache.demand_miss_latency::cpu1.inst 2109411000 # number of demand (read+write) miss cycles
757 system.cpu0.icache.demand_miss_latency::cpu2.inst 4767990981 # number of demand (read+write) miss cycles
758 system.cpu0.icache.demand_miss_latency::total 6877401981 # number of demand (read+write) miss cycles
759 system.cpu0.icache.overall_miss_latency::cpu1.inst 2109411000 # number of overall miss cycles
760 system.cpu0.icache.overall_miss_latency::cpu2.inst 4767990981 # number of overall miss cycles
761 system.cpu0.icache.overall_miss_latency::total 6877401981 # number of overall miss cycles
762 system.cpu0.icache.ReadReq_accesses::cpu0.inst 89685541 # number of ReadReq accesses(hits+misses)
763 system.cpu0.icache.ReadReq_accesses::cpu1.inst 38020458 # number of ReadReq accesses(hits+misses)
764 system.cpu0.icache.ReadReq_accesses::cpu2.inst 2884963 # number of ReadReq accesses(hits+misses)
765 system.cpu0.icache.ReadReq_accesses::total 130590962 # number of ReadReq accesses(hits+misses)
766 system.cpu0.icache.demand_accesses::cpu0.inst 89685541 # number of demand (read+write) accesses
767 system.cpu0.icache.demand_accesses::cpu1.inst 38020458 # number of demand (read+write) accesses
768 system.cpu0.icache.demand_accesses::cpu2.inst 2884963 # number of demand (read+write) accesses
769 system.cpu0.icache.demand_accesses::total 130590962 # number of demand (read+write) accesses
770 system.cpu0.icache.overall_accesses::cpu0.inst 89685541 # number of overall (read+write) accesses
771 system.cpu0.icache.overall_accesses::cpu1.inst 38020458 # number of overall (read+write) accesses
772 system.cpu0.icache.overall_accesses::cpu2.inst 2884963 # number of overall (read+write) accesses
773 system.cpu0.icache.overall_accesses::total 130590962 # number of overall (read+write) accesses
774 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004185 # miss rate for ReadReq accesses
775 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004045 # miss rate for ReadReq accesses
776 system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116363 # miss rate for ReadReq accesses
777 system.cpu0.icache.ReadReq_miss_rate::total 0.006622 # miss rate for ReadReq accesses
778 system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004185 # miss rate for demand accesses
779 system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004045 # miss rate for demand accesses
780 system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116363 # miss rate for demand accesses
781 system.cpu0.icache.demand_miss_rate::total 0.006622 # miss rate for demand accesses
782 system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004185 # miss rate for overall accesses
783 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004045 # miss rate for overall accesses
784 system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116363 # miss rate for overall accesses
785 system.cpu0.icache.overall_miss_rate::total 0.006622 # miss rate for overall accesses
786 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13717.337443 # average ReadReq miss latency
787 system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14203.046097 # average ReadReq miss latency
788 system.cpu0.icache.ReadReq_avg_miss_latency::total 7952.656857 # average ReadReq miss latency
789 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13717.337443 # average overall miss latency
790 system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14203.046097 # average overall miss latency
791 system.cpu0.icache.demand_avg_miss_latency::total 7952.656857 # average overall miss latency
792 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13717.337443 # average overall miss latency
793 system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14203.046097 # average overall miss latency
794 system.cpu0.icache.overall_avg_miss_latency::total 7952.656857 # average overall miss latency
795 system.cpu0.icache.blocked_cycles::no_mshrs 6416 # number of cycles access was blocked
796 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
797 system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked
798 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
799 system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.515556 # average number of cycles each access was blocked
800 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
801 system.cpu0.icache.fast_writes 0 # number of fast writes performed
802 system.cpu0.icache.cache_copies 0 # number of cache copies performed
803 system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 17396 # number of ReadReq MSHR hits
804 system.cpu0.icache.ReadReq_mshr_hits::total 17396 # number of ReadReq MSHR hits
805 system.cpu0.icache.demand_mshr_hits::cpu2.inst 17396 # number of demand (read+write) MSHR hits
806 system.cpu0.icache.demand_mshr_hits::total 17396 # number of demand (read+write) MSHR hits
807 system.cpu0.icache.overall_mshr_hits::cpu2.inst 17396 # number of overall MSHR hits
808 system.cpu0.icache.overall_mshr_hits::total 17396 # number of overall MSHR hits
809 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 153777 # number of ReadReq MSHR misses
810 system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 318306 # number of ReadReq MSHR misses
811 system.cpu0.icache.ReadReq_mshr_misses::total 472083 # number of ReadReq MSHR misses
812 system.cpu0.icache.demand_mshr_misses::cpu1.inst 153777 # number of demand (read+write) MSHR misses
813 system.cpu0.icache.demand_mshr_misses::cpu2.inst 318306 # number of demand (read+write) MSHR misses
814 system.cpu0.icache.demand_mshr_misses::total 472083 # number of demand (read+write) MSHR misses
815 system.cpu0.icache.overall_mshr_misses::cpu1.inst 153777 # number of overall MSHR misses
816 system.cpu0.icache.overall_mshr_misses::cpu2.inst 318306 # number of overall MSHR misses
817 system.cpu0.icache.overall_mshr_misses::total 472083 # number of overall MSHR misses
818 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1801857000 # number of ReadReq MSHR miss cycles
819 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3960171483 # number of ReadReq MSHR miss cycles
820 system.cpu0.icache.ReadReq_mshr_miss_latency::total 5762028483 # number of ReadReq MSHR miss cycles
821 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1801857000 # number of demand (read+write) MSHR miss cycles
822 system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3960171483 # number of demand (read+write) MSHR miss cycles
823 system.cpu0.icache.demand_mshr_miss_latency::total 5762028483 # number of demand (read+write) MSHR miss cycles
824 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1801857000 # number of overall MSHR miss cycles
825 system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3960171483 # number of overall MSHR miss cycles
826 system.cpu0.icache.overall_mshr_miss_latency::total 5762028483 # number of overall MSHR miss cycles
827 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004045 # mshr miss rate for ReadReq accesses
828 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110333 # mshr miss rate for ReadReq accesses
829 system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003615 # mshr miss rate for ReadReq accesses
830 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004045 # mshr miss rate for demand accesses
831 system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110333 # mshr miss rate for demand accesses
832 system.cpu0.icache.demand_mshr_miss_rate::total 0.003615 # mshr miss rate for demand accesses
833 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004045 # mshr miss rate for overall accesses
834 system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110333 # mshr miss rate for overall accesses
835 system.cpu0.icache.overall_mshr_miss_rate::total 0.003615 # mshr miss rate for overall accesses
836 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.337443 # average ReadReq mshr miss latency
837 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12441.397533 # average ReadReq mshr miss latency
838 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12205.541151 # average ReadReq mshr miss latency
839 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.337443 # average overall mshr miss latency
840 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12441.397533 # average overall mshr miss latency
841 system.cpu0.icache.demand_avg_mshr_miss_latency::total 12205.541151 # average overall mshr miss latency
842 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.337443 # average overall mshr miss latency
843 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12441.397533 # average overall mshr miss latency
844 system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.541151 # average overall mshr miss latency
845 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
846 system.cpu0.dcache.replacements 1634958 # number of replacements
847 system.cpu0.dcache.tagsinuse 511.999366 # Cycle average of tags in use
848 system.cpu0.dcache.total_refs 19655982 # Total number of references to valid blocks.
849 system.cpu0.dcache.sampled_refs 1635470 # Sample count of references to valid blocks.
850 system.cpu0.dcache.avg_refs 12.018552 # Average number of references to valid blocks.
851 system.cpu0.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
852 system.cpu0.dcache.occ_blocks::cpu0.data 482.608033 # Average occupied blocks per requestor
853 system.cpu0.dcache.occ_blocks::cpu1.data 17.353549 # Average occupied blocks per requestor
854 system.cpu0.dcache.occ_blocks::cpu2.data 12.037784 # Average occupied blocks per requestor
855 system.cpu0.dcache.occ_percent::cpu0.data 0.942594 # Average percentage of cache occupancy
856 system.cpu0.dcache.occ_percent::cpu1.data 0.033894 # Average percentage of cache occupancy
857 system.cpu0.dcache.occ_percent::cpu2.data 0.023511 # Average percentage of cache occupancy
858 system.cpu0.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
859 system.cpu0.dcache.ReadReq_hits::cpu0.data 5624800 # number of ReadReq hits
860 system.cpu0.dcache.ReadReq_hits::cpu1.data 2207994 # number of ReadReq hits
861 system.cpu0.dcache.ReadReq_hits::cpu2.data 3726568 # number of ReadReq hits
862 system.cpu0.dcache.ReadReq_hits::total 11559362 # number of ReadReq hits
863 system.cpu0.dcache.WriteReq_hits::cpu0.data 3904284 # number of WriteReq hits
864 system.cpu0.dcache.WriteReq_hits::cpu1.data 1548034 # number of WriteReq hits
865 system.cpu0.dcache.WriteReq_hits::cpu2.data 2642598 # number of WriteReq hits
866 system.cpu0.dcache.WriteReq_hits::total 8094916 # number of WriteReq hits
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868 system.cpu0.dcache.demand_hits::cpu1.data 3756028 # number of demand (read+write) hits
869 system.cpu0.dcache.demand_hits::cpu2.data 6369166 # number of demand (read+write) hits
870 system.cpu0.dcache.demand_hits::total 19654278 # number of demand (read+write) hits
871 system.cpu0.dcache.overall_hits::cpu0.data 9529084 # number of overall hits
872 system.cpu0.dcache.overall_hits::cpu1.data 3756028 # number of overall hits
873 system.cpu0.dcache.overall_hits::cpu2.data 6369166 # number of overall hits
874 system.cpu0.dcache.overall_hits::total 19654278 # number of overall hits
875 system.cpu0.dcache.ReadReq_misses::cpu0.data 539271 # number of ReadReq misses
876 system.cpu0.dcache.ReadReq_misses::cpu1.data 233721 # number of ReadReq misses
877 system.cpu0.dcache.ReadReq_misses::cpu2.data 917659 # number of ReadReq misses
878 system.cpu0.dcache.ReadReq_misses::total 1690651 # number of ReadReq misses
879 system.cpu0.dcache.WriteReq_misses::cpu0.data 149559 # number of WriteReq misses
880 system.cpu0.dcache.WriteReq_misses::cpu1.data 69191 # number of WriteReq misses
881 system.cpu0.dcache.WriteReq_misses::cpu2.data 97336 # number of WriteReq misses
882 system.cpu0.dcache.WriteReq_misses::total 316086 # number of WriteReq misses
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887 system.cpu0.dcache.overall_misses::cpu0.data 688830 # number of overall misses
888 system.cpu0.dcache.overall_misses::cpu1.data 302912 # number of overall misses
889 system.cpu0.dcache.overall_misses::cpu2.data 1014995 # number of overall misses
890 system.cpu0.dcache.overall_misses::total 2006737 # number of overall misses
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892 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15046703000 # number of ReadReq miss cycles
893 system.cpu0.dcache.ReadReq_miss_latency::total 18303092500 # number of ReadReq miss cycles
894 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1959155500 # number of WriteReq miss cycles
895 system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 2564161499 # number of WriteReq miss cycles
896 system.cpu0.dcache.WriteReq_miss_latency::total 4523316999 # number of WriteReq miss cycles
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898 system.cpu0.dcache.demand_miss_latency::cpu2.data 17610864499 # number of demand (read+write) miss cycles
899 system.cpu0.dcache.demand_miss_latency::total 22826409499 # number of demand (read+write) miss cycles
900 system.cpu0.dcache.overall_miss_latency::cpu1.data 5215545000 # number of overall miss cycles
901 system.cpu0.dcache.overall_miss_latency::cpu2.data 17610864499 # number of overall miss cycles
902 system.cpu0.dcache.overall_miss_latency::total 22826409499 # number of overall miss cycles
903 system.cpu0.dcache.ReadReq_accesses::cpu0.data 6164071 # number of ReadReq accesses(hits+misses)
904 system.cpu0.dcache.ReadReq_accesses::cpu1.data 2441715 # number of ReadReq accesses(hits+misses)
905 system.cpu0.dcache.ReadReq_accesses::cpu2.data 4644227 # number of ReadReq accesses(hits+misses)
906 system.cpu0.dcache.ReadReq_accesses::total 13250013 # number of ReadReq accesses(hits+misses)
907 system.cpu0.dcache.WriteReq_accesses::cpu0.data 4053843 # number of WriteReq accesses(hits+misses)
908 system.cpu0.dcache.WriteReq_accesses::cpu1.data 1617225 # number of WriteReq accesses(hits+misses)
909 system.cpu0.dcache.WriteReq_accesses::cpu2.data 2739934 # number of WriteReq accesses(hits+misses)
910 system.cpu0.dcache.WriteReq_accesses::total 8411002 # number of WriteReq accesses(hits+misses)
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912 system.cpu0.dcache.demand_accesses::cpu1.data 4058940 # number of demand (read+write) accesses
913 system.cpu0.dcache.demand_accesses::cpu2.data 7384161 # number of demand (read+write) accesses
914 system.cpu0.dcache.demand_accesses::total 21661015 # number of demand (read+write) accesses
915 system.cpu0.dcache.overall_accesses::cpu0.data 10217914 # number of overall (read+write) accesses
916 system.cpu0.dcache.overall_accesses::cpu1.data 4058940 # number of overall (read+write) accesses
917 system.cpu0.dcache.overall_accesses::cpu2.data 7384161 # number of overall (read+write) accesses
918 system.cpu0.dcache.overall_accesses::total 21661015 # number of overall (read+write) accesses
919 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.087486 # miss rate for ReadReq accesses
920 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.095720 # miss rate for ReadReq accesses
921 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197591 # miss rate for ReadReq accesses
922 system.cpu0.dcache.ReadReq_miss_rate::total 0.127596 # miss rate for ReadReq accesses
923 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036893 # miss rate for WriteReq accesses
924 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.042784 # miss rate for WriteReq accesses
925 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.035525 # miss rate for WriteReq accesses
926 system.cpu0.dcache.WriteReq_miss_rate::total 0.037580 # miss rate for WriteReq accesses
927 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067414 # miss rate for demand accesses
928 system.cpu0.dcache.demand_miss_rate::cpu1.data 0.074628 # miss rate for demand accesses
929 system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137456 # miss rate for demand accesses
930 system.cpu0.dcache.demand_miss_rate::total 0.092643 # miss rate for demand accesses
931 system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067414 # miss rate for overall accesses
932 system.cpu0.dcache.overall_miss_rate::cpu1.data 0.074628 # miss rate for overall accesses
933 system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137456 # miss rate for overall accesses
934 system.cpu0.dcache.overall_miss_rate::total 0.092643 # miss rate for overall accesses
935 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13932.806637 # average ReadReq miss latency
936 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16396.834772 # average ReadReq miss latency
937 system.cpu0.dcache.ReadReq_avg_miss_latency::total 10826.061973 # average ReadReq miss latency
938 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28315.178275 # average WriteReq miss latency
939 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26343.403253 # average WriteReq miss latency
940 system.cpu0.dcache.WriteReq_avg_miss_latency::total 14310.399698 # average WriteReq miss latency
941 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17218.020415 # average overall miss latency
942 system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17350.690889 # average overall miss latency
943 system.cpu0.dcache.demand_avg_miss_latency::total 11374.888438 # average overall miss latency
944 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17218.020415 # average overall miss latency
945 system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17350.690889 # average overall miss latency
946 system.cpu0.dcache.overall_avg_miss_latency::total 11374.888438 # average overall miss latency
947 system.cpu0.dcache.blocked_cycles::no_mshrs 180086 # number of cycles access was blocked
948 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
949 system.cpu0.dcache.blocked::no_mshrs 11859 # number of cycles access was blocked
950 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
951 system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.185597 # average number of cycles each access was blocked
952 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
953 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
954 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
955 system.cpu0.dcache.writebacks::writebacks 1544951 # number of writebacks
956 system.cpu0.dcache.writebacks::total 1544951 # number of writebacks
957 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 358302 # number of ReadReq MSHR hits
958 system.cpu0.dcache.ReadReq_mshr_hits::total 358302 # number of ReadReq MSHR hits
959 system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 11322 # number of WriteReq MSHR hits
960 system.cpu0.dcache.WriteReq_mshr_hits::total 11322 # number of WriteReq MSHR hits
961 system.cpu0.dcache.demand_mshr_hits::cpu2.data 369624 # number of demand (read+write) MSHR hits
962 system.cpu0.dcache.demand_mshr_hits::total 369624 # number of demand (read+write) MSHR hits
963 system.cpu0.dcache.overall_mshr_hits::cpu2.data 369624 # number of overall MSHR hits
964 system.cpu0.dcache.overall_mshr_hits::total 369624 # number of overall MSHR hits
965 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 233721 # number of ReadReq MSHR misses
966 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 559357 # number of ReadReq MSHR misses
967 system.cpu0.dcache.ReadReq_mshr_misses::total 793078 # number of ReadReq MSHR misses
968 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 69191 # number of WriteReq MSHR misses
969 system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 86014 # number of WriteReq MSHR misses
970 system.cpu0.dcache.WriteReq_mshr_misses::total 155205 # number of WriteReq MSHR misses
971 system.cpu0.dcache.demand_mshr_misses::cpu1.data 302912 # number of demand (read+write) MSHR misses
972 system.cpu0.dcache.demand_mshr_misses::cpu2.data 645371 # number of demand (read+write) MSHR misses
973 system.cpu0.dcache.demand_mshr_misses::total 948283 # number of demand (read+write) MSHR misses
974 system.cpu0.dcache.overall_mshr_misses::cpu1.data 302912 # number of overall MSHR misses
975 system.cpu0.dcache.overall_mshr_misses::cpu2.data 645371 # number of overall MSHR misses
976 system.cpu0.dcache.overall_mshr_misses::total 948283 # number of overall MSHR misses
977 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2788947500 # number of ReadReq MSHR miss cycles
978 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8180959500 # number of ReadReq MSHR miss cycles
979 system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10969907000 # number of ReadReq MSHR miss cycles
980 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1820773500 # number of WriteReq MSHR miss cycles
981 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2270883499 # number of WriteReq MSHR miss cycles
982 system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4091656999 # number of WriteReq MSHR miss cycles
983 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4609721000 # number of demand (read+write) MSHR miss cycles
984 system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10451842999 # number of demand (read+write) MSHR miss cycles
985 system.cpu0.dcache.demand_mshr_miss_latency::total 15061563999 # number of demand (read+write) MSHR miss cycles
986 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4609721000 # number of overall MSHR miss cycles
987 system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10451842999 # number of overall MSHR miss cycles
988 system.cpu0.dcache.overall_mshr_miss_latency::total 15061563999 # number of overall MSHR miss cycles
989 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31167993500 # number of ReadReq MSHR uncacheable cycles
990 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33212773000 # number of ReadReq MSHR uncacheable cycles
991 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64380766500 # number of ReadReq MSHR uncacheable cycles
992 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 368756500 # number of WriteReq MSHR uncacheable cycles
993 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 730986500 # number of WriteReq MSHR uncacheable cycles
994 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1099743000 # number of WriteReq MSHR uncacheable cycles
995 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31536750000 # number of overall MSHR uncacheable cycles
996 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33943759500 # number of overall MSHR uncacheable cycles
997 system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65480509500 # number of overall MSHR uncacheable cycles
998 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.095720 # mshr miss rate for ReadReq accesses
999 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.120441 # mshr miss rate for ReadReq accesses
1000 system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059855 # mshr miss rate for ReadReq accesses
1001 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042784 # mshr miss rate for WriteReq accesses
1002 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031393 # mshr miss rate for WriteReq accesses
1003 system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018453 # mshr miss rate for WriteReq accesses
1004 system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for demand accesses
1005 system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for demand accesses
1006 system.cpu0.dcache.demand_mshr_miss_rate::total 0.043778 # mshr miss rate for demand accesses
1007 system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for overall accesses
1008 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for overall accesses
1009 system.cpu0.dcache.overall_mshr_miss_rate::total 0.043778 # mshr miss rate for overall accesses
1010 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11932.806637 # average ReadReq mshr miss latency
1011 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14625.649630 # average ReadReq mshr miss latency
1012 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13832.065698 # average ReadReq mshr miss latency
1013 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26315.178275 # average WriteReq mshr miss latency
1014 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26401.324191 # average WriteReq mshr miss latency
1015 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26362.920003 # average WriteReq mshr miss latency
1016 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency
1017 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency
1018 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency
1019 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency
1020 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency
1021 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency
1022 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1023 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
1024 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1025 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1026 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
1027 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1028 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1029 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
1030 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1031 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1032 system.cpu1.numCycles 2606004355 # number of cpu cycles simulated
1033 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1034 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1035 system.cpu1.committedInsts 34463532 # Number of instructions committed
1036 system.cpu1.committedOps 67005357 # Number of ops (including micro ops) committed
1037 system.cpu1.num_int_alu_accesses 62150402 # Number of integer alu accesses
1038 system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
1039 system.cpu1.num_func_calls 411236 # number of times a function call or return occured
1040 system.cpu1.num_conditional_control_insts 6382216 # number of instructions that are conditional controls
1041 system.cpu1.num_int_insts 62150402 # number of integer instructions
1042 system.cpu1.num_fp_insts 0 # number of float instructions
1043 system.cpu1.num_int_register_reads 149729485 # number of times the integer registers were read
1044 system.cpu1.num_int_register_writes 79937808 # number of times the integer registers were written
1045 system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
1046 system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
1047 system.cpu1.num_mem_refs 4253944 # number of memory refs
1048 system.cpu1.num_load_insts 2634755 # Number of load instructions
1049 system.cpu1.num_store_insts 1619189 # Number of store instructions
1050 system.cpu1.num_idle_cycles 7677367348.593150 # Number of idle cycles
1051 system.cpu1.num_busy_cycles -5071362993.593150 # Number of busy cycles
1052 system.cpu1.not_idle_fraction -1.946030 # Percentage of non-idle cycles
1053 system.cpu1.idle_fraction 2.946030 # Percentage of idle cycles
1054 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1055 system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
1056 system.cpu2.branchPred.lookups 28657213 # Number of BP lookups
1057 system.cpu2.branchPred.condPredicted 28657213 # Number of conditional branches predicted
1058 system.cpu2.branchPred.condIncorrect 282528 # Number of conditional branches incorrect
1059 system.cpu2.branchPred.BTBLookups 26332341 # Number of BTB lookups
1060 system.cpu2.branchPred.BTBHits 25809696 # Number of BTB hits
1061 system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1062 system.cpu2.branchPred.BTBHitPct 98.015197 # BTB Hit Percentage
1063 system.cpu2.branchPred.usedRAS 509678 # Number of times the RAS was used to get a target.
1064 system.cpu2.branchPred.RASInCorrect 56598 # Number of incorrect RAS predictions.
1065 system.cpu2.numCycles 152138342 # number of cpu cycles simulated
1066 system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
1067 system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
1068 system.cpu2.fetch.icacheStallCycles 8765036 # Number of cycles fetch is stalled on an Icache miss
1069 system.cpu2.fetch.Insts 141230370 # Number of instructions fetch has processed
1070 system.cpu2.fetch.Branches 28657213 # Number of branches that fetch encountered
1071 system.cpu2.fetch.predictedBranches 26319374 # Number of branches that fetch has predicted taken
1072 system.cpu2.fetch.Cycles 54195726 # Number of cycles fetch has run and was not squashing or blocked
1073 system.cpu2.fetch.SquashCycles 1350224 # Number of cycles fetch has spent squashing
1074 system.cpu2.fetch.TlbCycles 59186 # Number of cycles fetch has spent waiting for tlb
1075 system.cpu2.fetch.BlockedCycles 22546148 # Number of cycles fetch has spent blocked
1076 system.cpu2.fetch.MiscStallCycles 3184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1077 system.cpu2.fetch.PendingDrainCycles 6465 # Number of cycles fetch has spent waiting on pipes to drain
1078 system.cpu2.fetch.PendingTrapStallCycles 18223 # Number of stall cycles due to pending traps
1079 system.cpu2.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR
1080 system.cpu2.fetch.CacheLines 2884967 # Number of cache lines fetched
1081 system.cpu2.fetch.IcacheSquashes 126552 # Number of outstanding Icache misses that were squashed
1082 system.cpu2.fetch.ItlbSquashes 1685 # Number of outstanding ITLB misses that were squashed
1083 system.cpu2.fetch.rateDist::samples 86648155 # Number of instructions fetched each cycle (Total)
1084 system.cpu2.fetch.rateDist::mean 3.214672 # Number of instructions fetched each cycle (Total)
1085 system.cpu2.fetch.rateDist::stdev 3.414816 # Number of instructions fetched each cycle (Total)
1086 system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1087 system.cpu2.fetch.rateDist::0 32565830 37.58% 37.58% # Number of instructions fetched each cycle (Total)
1088 system.cpu2.fetch.rateDist::1 546380 0.63% 38.21% # Number of instructions fetched each cycle (Total)
1089 system.cpu2.fetch.rateDist::2 23846422 27.52% 65.74% # Number of instructions fetched each cycle (Total)
1090 system.cpu2.fetch.rateDist::3 287955 0.33% 66.07% # Number of instructions fetched each cycle (Total)
1091 system.cpu2.fetch.rateDist::4 558507 0.64% 66.71% # Number of instructions fetched each cycle (Total)
1092 system.cpu2.fetch.rateDist::5 803239 0.93% 67.64% # Number of instructions fetched each cycle (Total)
1093 system.cpu2.fetch.rateDist::6 320738 0.37% 68.01% # Number of instructions fetched each cycle (Total)
1094 system.cpu2.fetch.rateDist::7 484990 0.56% 68.57% # Number of instructions fetched each cycle (Total)
1095 system.cpu2.fetch.rateDist::8 27234094 31.43% 100.00% # Number of instructions fetched each cycle (Total)
1096 system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1097 system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1098 system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1099 system.cpu2.fetch.rateDist::total 86648155 # Number of instructions fetched each cycle (Total)
1100 system.cpu2.fetch.branchRate 0.188363 # Number of branch fetches per cycle
1101 system.cpu2.fetch.rate 0.928302 # Number of inst fetches per cycle
1102 system.cpu2.decode.IdleCycles 10203383 # Number of cycles decode is idle
1103 system.cpu2.decode.BlockedCycles 21434341 # Number of cycles decode is blocked
1104 system.cpu2.decode.RunCycles 42926723 # Number of cycles decode is running
1105 system.cpu2.decode.UnblockCycles 1270829 # Number of cycles decode is unblocking
1106 system.cpu2.decode.SquashCycles 1056674 # Number of cycles decode is squashing
1107 system.cpu2.decode.DecodedInsts 277800524 # Number of instructions handled by decode
1108 system.cpu2.decode.SquashedInsts 10 # Number of squashed instructions handled by decode
1109 system.cpu2.rename.SquashCycles 1056674 # Number of cycles rename is squashing
1110 system.cpu2.rename.IdleCycles 11171095 # Number of cycles rename is idle
1111 system.cpu2.rename.BlockCycles 12732005 # Number of cycles rename is blocking
1112 system.cpu2.rename.serializeStallCycles 3756843 # count of cycles rename stalled for serializing inst
1113 system.cpu2.rename.RunCycles 43068844 # Number of cycles rename is running
1114 system.cpu2.rename.UnblockCycles 5106557 # Number of cycles rename is unblocking
1115 system.cpu2.rename.RenamedInsts 276894625 # Number of instructions processed by rename
1116 system.cpu2.rename.ROBFullEvents 6426 # Number of times rename has blocked due to ROB full
1117 system.cpu2.rename.IQFullEvents 2483944 # Number of times rename has blocked due to IQ full
1118 system.cpu2.rename.LSQFullEvents 1961652 # Number of times rename has blocked due to LSQ full
1119 system.cpu2.rename.FullRegisterEvents 2548 # Number of times there has been no free registers
1120 system.cpu2.rename.RenamedOperands 331033770 # Number of destination operands rename has renamed
1121 system.cpu2.rename.RenameLookups 601753258 # Number of register rename lookups that rename has made
1122 system.cpu2.rename.int_rename_lookups 601753178 # Number of integer rename lookups
1123 system.cpu2.rename.fp_rename_lookups 80 # Number of floating rename lookups
1124 system.cpu2.rename.CommittedMaps 321557178 # Number of HB maps that are committed
1125 system.cpu2.rename.UndoneMaps 9476592 # Number of HB maps that are undone due to squashing
1126 system.cpu2.rename.serializingInsts 136008 # count of serializing insts renamed
1127 system.cpu2.rename.tempSerializingInsts 137084 # count of temporary serializing insts renamed
1128 system.cpu2.rename.skidInsts 11206153 # count of insts added to the skid buffer
1129 system.cpu2.memDep0.insertedLoads 5917951 # Number of loads inserted to the mem dependence unit.
1130 system.cpu2.memDep0.insertedStores 3223233 # Number of stores inserted to the mem dependence unit.
1131 system.cpu2.memDep0.conflictingLoads 365517 # Number of conflicting loads.
1132 system.cpu2.memDep0.conflictingStores 302609 # Number of conflicting stores.
1133 system.cpu2.iq.iqInstsAdded 275352384 # Number of instructions added to the IQ (excludes non-spec)
1134 system.cpu2.iq.iqNonSpecInstsAdded 397965 # Number of non-speculative instructions added to the IQ
1135 system.cpu2.iq.iqInstsIssued 273886109 # Number of instructions issued
1136 system.cpu2.iq.iqSquashedInstsIssued 53996 # Number of squashed instructions issued
1137 system.cpu2.iq.iqSquashedInstsExamined 6700477 # Number of squashed instructions iterated over during squash; mainly for profiling
1138 system.cpu2.iq.iqSquashedOperandsExamined 10323870 # Number of squashed operands that are examined and possibly removed from graph
1139 system.cpu2.iq.iqSquashedNonSpecRemoved 50144 # Number of squashed non-spec instructions that were removed
1140 system.cpu2.iq.issued_per_cycle::samples 86648155 # Number of insts issued each cycle
1141 system.cpu2.iq.issued_per_cycle::mean 3.160899 # Number of insts issued each cycle
1142 system.cpu2.iq.issued_per_cycle::stdev 2.377923 # Number of insts issued each cycle
1143 system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1144 system.cpu2.iq.issued_per_cycle::0 23779115 27.44% 27.44% # Number of insts issued each cycle
1145 system.cpu2.iq.issued_per_cycle::1 5842995 6.74% 34.19% # Number of insts issued each cycle
1146 system.cpu2.iq.issued_per_cycle::2 3792974 4.38% 38.56% # Number of insts issued each cycle
1147 system.cpu2.iq.issued_per_cycle::3 2596888 3.00% 41.56% # Number of insts issued each cycle
1148 system.cpu2.iq.issued_per_cycle::4 25119641 28.99% 70.55% # Number of insts issued each cycle
1149 system.cpu2.iq.issued_per_cycle::5 1266341 1.46% 72.01% # Number of insts issued each cycle
1150 system.cpu2.iq.issued_per_cycle::6 23944050 27.63% 99.65% # Number of insts issued each cycle
1151 system.cpu2.iq.issued_per_cycle::7 257275 0.30% 99.94% # Number of insts issued each cycle
1152 system.cpu2.iq.issued_per_cycle::8 48876 0.06% 100.00% # Number of insts issued each cycle
1153 system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1154 system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1155 system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1156 system.cpu2.iq.issued_per_cycle::total 86648155 # Number of insts issued each cycle
1157 system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1158 system.cpu2.iq.fu_full::IntAlu 118795 33.06% 33.06% # attempts to use FU when none available
1159 system.cpu2.iq.fu_full::IntMult 241 0.07% 33.13% # attempts to use FU when none available
1160 system.cpu2.iq.fu_full::IntDiv 86 0.02% 33.15% # attempts to use FU when none available
1161 system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.15% # attempts to use FU when none available
1162 system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.15% # attempts to use FU when none available
1163 system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.15% # attempts to use FU when none available
1164 system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.15% # attempts to use FU when none available
1165 system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.15% # attempts to use FU when none available
1166 system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.15% # attempts to use FU when none available
1167 system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.15% # attempts to use FU when none available
1168 system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.15% # attempts to use FU when none available
1169 system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.15% # attempts to use FU when none available
1170 system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.15% # attempts to use FU when none available
1171 system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.15% # attempts to use FU when none available
1172 system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.15% # attempts to use FU when none available
1173 system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.15% # attempts to use FU when none available
1174 system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.15% # attempts to use FU when none available
1175 system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.15% # attempts to use FU when none available
1176 system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.15% # attempts to use FU when none available
1177 system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.15% # attempts to use FU when none available
1178 system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.15% # attempts to use FU when none available
1179 system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.15% # attempts to use FU when none available
1180 system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.15% # attempts to use FU when none available
1181 system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.15% # attempts to use FU when none available
1182 system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.15% # attempts to use FU when none available
1183 system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.15% # attempts to use FU when none available
1184 system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.15% # attempts to use FU when none available
1185 system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.15% # attempts to use FU when none available
1186 system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.15% # attempts to use FU when none available
1187 system.cpu2.iq.fu_full::MemRead 188736 52.53% 85.68% # attempts to use FU when none available
1188 system.cpu2.iq.fu_full::MemWrite 51440 14.32% 100.00% # attempts to use FU when none available
1189 system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1190 system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1191 system.cpu2.iq.FU_type_0::No_OpClass 68063 0.02% 0.02% # Type of FU issued
1192 system.cpu2.iq.FU_type_0::IntAlu 264478225 96.57% 96.59% # Type of FU issued
1193 system.cpu2.iq.FU_type_0::IntMult 51078 0.02% 96.61% # Type of FU issued
1194 system.cpu2.iq.FU_type_0::IntDiv 47173 0.02% 96.63% # Type of FU issued
1195 system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
1196 system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
1197 system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
1198 system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
1199 system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
1200 system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
1201 system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
1202 system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
1203 system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
1204 system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
1205 system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
1206 system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
1207 system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
1208 system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
1209 system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
1210 system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
1211 system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
1212 system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
1213 system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
1214 system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
1215 system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
1216 system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
1217 system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
1218 system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
1219 system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
1220 system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
1221 system.cpu2.iq.FU_type_0::MemRead 6223177 2.27% 98.90% # Type of FU issued
1222 system.cpu2.iq.FU_type_0::MemWrite 3018393 1.10% 100.00% # Type of FU issued
1223 system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1224 system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1225 system.cpu2.iq.FU_type_0::total 273886109 # Type of FU issued
1226 system.cpu2.iq.rate 1.800244 # Inst issue rate
1227 system.cpu2.iq.fu_busy_cnt 359298 # FU busy when requested
1228 system.cpu2.iq.fu_busy_rate 0.001312 # FU busy rate (busy events/executed inst)
1229 system.cpu2.iq.int_inst_queue_reads 634870698 # Number of integer instruction queue reads
1230 system.cpu2.iq.int_inst_queue_writes 282454128 # Number of integer instruction queue writes
1231 system.cpu2.iq.int_inst_queue_wakeup_accesses 272600027 # Number of integer instruction queue wakeup accesses
1232 system.cpu2.iq.fp_inst_queue_reads 31 # Number of floating instruction queue reads
1233 system.cpu2.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
1234 system.cpu2.iq.fp_inst_queue_wakeup_accesses 8 # Number of floating instruction queue wakeup accesses
1235 system.cpu2.iq.int_alu_accesses 274177330 # Number of integer alu accesses
1236 system.cpu2.iq.fp_alu_accesses 14 # Number of floating point alu accesses
1237 system.cpu2.iew.lsq.thread0.forwLoads 614321 # Number of loads that had data forwarded from stores
1238 system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1239 system.cpu2.iew.lsq.thread0.squashedLoads 929558 # Number of loads squashed
1240 system.cpu2.iew.lsq.thread0.ignoredResponses 6267 # Number of memory responses ignored because the instruction is squashed
1241 system.cpu2.iew.lsq.thread0.memOrderViolation 3704 # Number of memory ordering violations
1242 system.cpu2.iew.lsq.thread0.squashedStores 478908 # Number of stores squashed
1243 system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1244 system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1245 system.cpu2.iew.lsq.thread0.rescheduledLoads 656133 # Number of loads that were rescheduled
1246 system.cpu2.iew.lsq.thread0.cacheBlocked 10377 # Number of times an access to memory failed due to the cache being blocked
1247 system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1248 system.cpu2.iew.iewSquashCycles 1056674 # Number of cycles IEW is squashing
1249 system.cpu2.iew.iewBlockCycles 8226180 # Number of cycles IEW is blocking
1250 system.cpu2.iew.iewUnblockCycles 803204 # Number of cycles IEW is unblocking
1251 system.cpu2.iew.iewDispatchedInsts 275750349 # Number of instructions dispatched to IQ
1252 system.cpu2.iew.iewDispSquashedInsts 63685 # Number of squashed instructions skipped by dispatch
1253 system.cpu2.iew.iewDispLoadInsts 5917951 # Number of dispatched load instructions
1254 system.cpu2.iew.iewDispStoreInsts 3223233 # Number of dispatched store instructions
1255 system.cpu2.iew.iewDispNonSpecInsts 220549 # Number of dispatched non-speculative instructions
1256 system.cpu2.iew.iewIQFullEvents 623968 # Number of times the IQ has become full, causing a stall
1257 system.cpu2.iew.iewLSQFullEvents 3956 # Number of times the LSQ has become full, causing a stall
1258 system.cpu2.iew.memOrderViolationEvents 3704 # Number of memory order violations
1259 system.cpu2.iew.predictedTakenIncorrect 161931 # Number of branches that were predicted taken incorrectly
1260 system.cpu2.iew.predictedNotTakenIncorrect 157888 # Number of branches that were predicted not taken incorrectly
1261 system.cpu2.iew.branchMispredicts 319819 # Number of branch mispredicts detected at execute
1262 system.cpu2.iew.iewExecutedInsts 273437676 # Number of executed instructions
1263 system.cpu2.iew.iewExecLoadInsts 6124763 # Number of load instructions executed
1264 system.cpu2.iew.iewExecSquashedInsts 448433 # Number of squashed instructions skipped in execute
1265 system.cpu2.iew.exec_swp 0 # number of swp insts executed
1266 system.cpu2.iew.exec_nop 0 # number of nop insts executed
1267 system.cpu2.iew.exec_refs 9083662 # number of memory reference insts executed
1268 system.cpu2.iew.exec_branches 27821550 # Number of branches executed
1269 system.cpu2.iew.exec_stores 2958899 # Number of stores executed
1270 system.cpu2.iew.exec_rate 1.797296 # Inst execution rate
1271 system.cpu2.iew.wb_sent 273301697 # cumulative count of insts sent to commit
1272 system.cpu2.iew.wb_count 272600035 # cumulative count of insts written-back
1273 system.cpu2.iew.wb_producers 212879972 # num instructions producing a value
1274 system.cpu2.iew.wb_consumers 348297595 # num instructions consuming a value
1275 system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1276 system.cpu2.iew.wb_rate 1.791790 # insts written-back per cycle
1277 system.cpu2.iew.wb_fanout 0.611201 # average fanout of values written-back
1278 system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1279 system.cpu2.commit.commitSquashedInsts 6973062 # The number of squashed insts skipped by commit
1280 system.cpu2.commit.commitNonSpecStalls 347821 # The number of times commit has been forced to stall to communicate backwards
1281 system.cpu2.commit.branchMispredicts 284653 # The number of times a branch was mispredicted
1282 system.cpu2.commit.committed_per_cycle::samples 85591481 # Number of insts commited each cycle
1283 system.cpu2.commit.committed_per_cycle::mean 3.140222 # Number of insts commited each cycle
1284 system.cpu2.commit.committed_per_cycle::stdev 2.867307 # Number of insts commited each cycle
1285 system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1286 system.cpu2.commit.committed_per_cycle::0 28429929 33.22% 33.22% # Number of insts commited each cycle
1287 system.cpu2.commit.committed_per_cycle::1 4148762 4.85% 38.06% # Number of insts commited each cycle
1288 system.cpu2.commit.committed_per_cycle::2 1193631 1.39% 39.46% # Number of insts commited each cycle
1289 system.cpu2.commit.committed_per_cycle::3 24678313 28.83% 68.29% # Number of insts commited each cycle
1290 system.cpu2.commit.committed_per_cycle::4 797871 0.93% 69.22% # Number of insts commited each cycle
1291 system.cpu2.commit.committed_per_cycle::5 541346 0.63% 69.85% # Number of insts commited each cycle
1292 system.cpu2.commit.committed_per_cycle::6 330295 0.39% 70.24% # Number of insts commited each cycle
1293 system.cpu2.commit.committed_per_cycle::7 23445398 27.39% 97.63% # Number of insts commited each cycle
1294 system.cpu2.commit.committed_per_cycle::8 2025936 2.37% 100.00% # Number of insts commited each cycle
1295 system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1296 system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1297 system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1298 system.cpu2.commit.committed_per_cycle::total 85591481 # Number of insts commited each cycle
1299 system.cpu2.commit.committedInsts 136077221 # Number of instructions committed
1300 system.cpu2.commit.committedOps 268776221 # Number of ops (including micro ops) committed
1301 system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
1302 system.cpu2.commit.refs 7732718 # Number of memory references committed
1303 system.cpu2.commit.loads 4988393 # Number of loads committed
1304 system.cpu2.commit.membars 163760 # Number of memory barriers committed
1305 system.cpu2.commit.branches 27507890 # Number of branches committed
1306 system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
1307 system.cpu2.commit.int_insts 245262632 # Number of committed integer instructions.
1308 system.cpu2.commit.function_calls 414873 # Number of function calls committed.
1309 system.cpu2.commit.bw_lim_events 2025936 # number cycles where commit BW limit reached
1310 system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
1311 system.cpu2.rob.rob_reads 359289994 # The number of ROB reads
1312 system.cpu2.rob.rob_writes 552558663 # The number of ROB writes
1313 system.cpu2.timesIdled 454161 # Number of times that the entire CPU went into an idle state and unscheduled itself
1314 system.cpu2.idleCycles 65490187 # Total number of cycles that the CPU has spent unscheduled due to idling
1315 system.cpu2.quiesceCycles 4914041775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1316 system.cpu2.committedInsts 136077221 # Number of Instructions Simulated
1317 system.cpu2.committedOps 268776221 # Number of Ops (including micro ops) Simulated
1318 system.cpu2.committedInsts_total 136077221 # Number of Instructions Simulated
1319 system.cpu2.cpi 1.118029 # CPI: Cycles Per Instruction
1320 system.cpu2.cpi_total 1.118029 # CPI: Total CPI of All Threads
1321 system.cpu2.ipc 0.894431 # IPC: Instructions Per Cycle
1322 system.cpu2.ipc_total 0.894431 # IPC: Total IPC of All Threads
1323 system.cpu2.int_regfile_reads 502349004 # number of integer regfile reads
1324 system.cpu2.int_regfile_writes 325553024 # number of integer regfile writes
1325 system.cpu2.fp_regfile_reads 62552 # number of floating regfile reads
1326 system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes
1327 system.cpu2.misc_regfile_reads 88383748 # number of misc regfile reads
1328 system.cpu2.misc_regfile_writes 121022 # number of misc regfile writes
1329 system.cpu2.kern.inst.arm 0 # number of arm instructions executed
1330 system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
1332 ---------- End Simulation Statistics ----------
projects / gem5.git / blob